fix some bug and update rtt driver

project_0/.config

@@ -8,8 +8,9 @@
 #
 CONFIG_RT_NAME_MAX=8
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
 # CONFIG_RT_USING_SMP is not set
-CONFIG_RT_ALIGN_SIZE=4
+CONFIG_RT_ALIGN_SIZE=8
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
 # CONFIG_RT_THREAD_PRIORITY_256 is not set
@@ -21,17 +22,20 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
-# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
 
 #
 # kservice optimization
 #
-# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
 # CONFIG_RT_USING_TINY_FFS is not set
-# CONFIG_RT_PRINTF_LONGLONG is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
 CONFIG_RT_DEBUG=y
-CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_COLOR is not set
 # CONFIG_RT_DEBUG_INIT_CONFIG is not set
 # CONFIG_RT_DEBUG_THREAD_CONFIG is not set
 # CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
@@ -74,16 +78,19 @@ CONFIG_RT_USING_HEAP=y
 #
 CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x40100
-CONFIG_ARCH_ARM=y
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_M3=y
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
@@ -93,17 +100,8 @@ CONFIG_RT_USING_USER_MAIN=y
 CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
 CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # CONFIG_RT_USING_LEGACY is not set
-
-#
-# C++ features
-#
-# CONFIG_RT_USING_CPLUSPLUS is not set
-
-#
-# Command shell
-#
-CONFIG_RT_USING_FINSH=y
 CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
 CONFIG_FINSH_USING_MSH=y
 CONFIG_FINSH_THREAD_NAME="tshell"
 CONFIG_FINSH_THREAD_PRIORITY=20
@@ -117,16 +115,26 @@ CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
 # CONFIG_FINSH_USING_AUTH is not set
 CONFIG_FINSH_ARG_MAX=10
-
-#
-# Device virtual file system
-#
-# CONFIG_RT_USING_DFS is not set
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+# CONFIG_RT_USING_DFS_DEVFS is not set
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_FAL is not set
 
 #
 # Device Drivers
 #
 CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_SERIAL_V1=y
@@ -141,10 +149,14 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
@@ -152,10 +164,13 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
 # CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
 # CONFIG_RT_USING_HWCRYPTO is not set
 # CONFIG_RT_USING_PULSE_ENCODER is not set
 # CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
 # CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
 
 #
 # Using USB
@@ -165,7 +180,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_USB_DEVICE is not set
 
 #
-# POSIX layer and C standard library
+# C/C++ and POSIX layer
 #
 CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 
@@ -189,36 +204,16 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # Socket is in the 'Network' category
 #
+# CONFIG_RT_USING_CPLUSPLUS is not set
 
 #
 # Network
 #
-
-#
-# Socket abstraction layer
-#
 # CONFIG_RT_USING_SAL is not set
-
-#
-# Network interface device
-#
 # CONFIG_RT_USING_NETDEV is not set
-
-#
-# light weight TCP/IP stack
-#
 # CONFIG_RT_USING_LWIP is not set
-
-#
-# AT commands
-#
 # CONFIG_RT_USING_AT is not set
 
-#
-# VBUS(Virtual Software BUS)
-#
-# CONFIG_RT_USING_VBUS is not set
-
 #
 # Utilities
 #
@@ -227,7 +222,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_RT_USING_UTEST is not set
 # CONFIG_RT_USING_VAR_EXPORT is not set
 # CONFIG_RT_USING_RT_LINK is not set
-# CONFIG_RT_USING_LWP is not set
+# CONFIG_RT_USING_VBUS is not set
 
 #
 # RT-Thread Utestcases
@@ -241,6 +236,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LWIP is not set
 # CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
 # CONFIG_PKG_USING_UMQTT is not set
@@ -251,12 +247,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_KAWAII_MQTT is not set
 # CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
-# CONFIG_PKG_USING_CJSON is not set
-# CONFIG_PKG_USING_JSMN is not set
 # CONFIG_PKG_USING_LIBMODBUS is not set
 # CONFIG_PKG_USING_FREEMODBUS is not set
-# CONFIG_PKG_USING_LJSON is not set
-# CONFIG_PKG_USING_EZXML is not set
 # CONFIG_PKG_USING_NANOPB is not set
 
 #
@@ -295,7 +287,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
 # CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
 # CONFIG_PKG_USING_IPMSG is not set
 # CONFIG_PKG_USING_LSSDP is not set
@@ -309,33 +303,34 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_ABUP_FOTA is not set
 # CONFIG_PKG_USING_LIBCURL2RTT is not set
 # CONFIG_PKG_USING_CAPNP is not set
-# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
 # CONFIG_PKG_USING_AGILE_TELNET is not set
 # CONFIG_PKG_USING_NMEALIB is not set
-# CONFIG_PKG_USING_AGILE_JSMN is not set
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 # CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 # CONFIG_PKG_USING_MAVLINK is not set
-# CONFIG_PKG_USING_RAPIDJSON is not set
 # CONFIG_PKG_USING_BSAL is not set
 # CONFIG_PKG_USING_AGILE_MODBUS is not set
 # CONFIG_PKG_USING_AGILE_FTP is not set
 # CONFIG_PKG_USING_EMBEDDEDPROTO is not set
 # CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
 # CONFIG_PKG_USING_LORA_PKT_FWD is not set
 # CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
 # CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
 # CONFIG_PKG_USING_HM is not set
 # CONFIG_PKG_USING_SMALL_MODBUS is not set
 # CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
 
 #
 # security packages
 #
 # CONFIG_PKG_USING_MBEDTLS is not set
 # CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
 # CONFIG_PKG_USING_TFM is not set
 # CONFIG_PKG_USING_YD_CRYPTO is not set
@@ -343,11 +338,29 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # language packages
 #
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
 # CONFIG_PKG_USING_LUATOS_SOC is not set
 # CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
 # CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
 
 #
 # multimedia packages
@@ -359,6 +372,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_LVGL is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
 
 #
 # u8g2: a monochrome graphic library
@@ -388,6 +402,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_TERMBOX is not set
 # CONFIG_PKG_USING_VT100 is not set
 # CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
 
 #
 # tools packages
@@ -399,7 +414,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_SEGGER_RTT is not set
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
-# CONFIG_PKG_USING_ULOG_FILE is not set
 # CONFIG_PKG_USING_LOGMGR is not set
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
@@ -430,6 +444,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_SOLAR_TERMS is not set
 # CONFIG_PKG_USING_GAN_ZHI is not set
 # CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
 
 #
 # system packages
@@ -442,14 +461,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
 # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
 
-#
-# POSIX extension functions
-#
-# CONFIG_PKG_USING_POSIX_GETLINE is not set
-# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
-# CONFIG_PKG_USING_POSIX_ITOA is not set
-# CONFIG_PKG_USING_POSIX_STRINGS is not set
-
 #
 # acceleration: Assembly language or algorithmic acceleration packages
 #
@@ -461,6 +472,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 #
 # CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
 # CONFIG_PKG_USING_CMSIS_RTOS2 is not set
 
 #
@@ -472,12 +484,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_UC_CLK is not set
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
-# CONFIG_RT_USING_ARDUINO is not set
-# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
-# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
 # CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
@@ -503,18 +514,97 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_ARM_2D is not set
 # CONFIG_PKG_USING_MCUBOOT is not set
 # CONFIG_PKG_USING_TINYUSB is not set
-# CONFIG_PKG_USING_USB_STACK is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
 
 #
 # peripheral libraries and drivers
 #
-# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
-# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
 # CONFIG_PKG_USING_AS7341 is not set
-# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_CW2015 is not set
 # CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
 # CONFIG_PKG_USING_SX12XX is not set
@@ -525,18 +615,21 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_NRF5X_SDK is not set
 # CONFIG_PKG_USING_NRFX is not set
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
 # CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
 # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
-# CONFIG_PKG_USING_AD7746 is not set
 # CONFIG_PKG_USING_PCA9685 is not set
 # CONFIG_PKG_USING_I2C_TOOLS is not set
 # CONFIG_PKG_USING_NRF24L01 is not set
-# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
-# CONFIG_PKG_USING_MAX17048 is not set
 # CONFIG_PKG_USING_RPLIDAR is not set
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
@@ -551,7 +644,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_CAN_YMODEM is not set
 # CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
 # CONFIG_PKG_USING_QLED is not set
-# CONFIG_PKG_USING_PAJ7620 is not set
 # CONFIG_PKG_USING_AGILE_CONSOLE is not set
 # CONFIG_PKG_USING_LD3320 is not set
 # CONFIG_PKG_USING_WK2124 is not set
@@ -582,7 +674,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_BL_MCU_SDK is not set
 # CONFIG_PKG_USING_SOFT_SERIAL is not set
 # CONFIG_PKG_USING_MB85RS16 is not set
-# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
 
 #
 # AI packages
@@ -597,10 +693,20 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
 
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
 #
 # miscellaneous packages
 #
 
+#
+# project laboratory
+#
+
 #
 # samples: kernel and components samples
 #
@@ -633,6 +739,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
 # CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 # CONFIG_PKG_USING_KENDRYTE_DEMO is not set
@@ -643,13 +750,222 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_VI is not set
 # CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
-# CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_CRCLIB is not set
 # CONFIG_PKG_USING_LWGPS is not set
 # CONFIG_PKG_USING_STATE_MACHINE is not set
 # CONFIG_PKG_USING_DESIGN_PATTERN is not set
 # CONFIG_PKG_USING_CONTROLLER is not set
 # CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+
+#
+# Other
+#
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
 CONFIG_SOC_FAMILY_APM32=y
 CONFIG_SOC_SERIES_APM32F1=y
 
@@ -664,3 +980,14 @@ CONFIG_SOC_APM32F103ZE=y
 CONFIG_BSP_USING_GPIO=y
 CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_DAC is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set
+# CONFIG_BSP_RTC_USING_LSE is not set
+# CONFIG_BSP_RTC_USING_LSI is not set
+# CONFIG_BSP_USING_I2C1 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_TMR is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_WDT is not set

project_0/.project

@@ -1,21 +1,21 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
-  <name>project</name>
+  <name>project_0</name>
   <comment />
   <projects>
-	</projects>
+    </projects>
   <buildSpec>
     <buildCommand>
       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
       <triggers>clean,full,incremental,</triggers>
       <arguments>
-			</arguments>
+            </arguments>
     </buildCommand>
     <buildCommand>
       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
       <triggers>full,incremental,</triggers>
       <arguments>
-			</arguments>
+            </arguments>
     </buildCommand>
   </buildSpec>
   <natures>

project_0/.settings/projcfg.ini

@@ -1,22 +1,20 @@
 #RT-Thread Studio Project Configuration
-#Sat Jan 16 15:18:32 CST 2021
-project_type=rtt
-chip_name=APM32F103ZE
-cpu_name=None
-target_freq=
-clock_source=
-dvendor_name=
-rx_pin_name=
-rtt_path=
-source_freq=
-csp_path=
-sub_series_name=
-selected_rtt_version=latest
+# Fri Mar 10 14:50:17 2023
 cfg_version=v3.0
-tool_chain=gcc
-uart_name=
-tx_pin_name=
-rtt_nano_path=
-output_project_path=
-hardware_adapter=J-Link
-project_name=project
+
+board_name=
+bsp_version=
+bsp_path=
+chip_name=
+project_base_rtt_bsp=true
+is_use_scons_build=true
+hardware_adapter=
+selected_rtt_version=latest
+board_base_nano_proj=false
+is_base_example_project=false
+example_name=
+project_type=rt-thread
+os_branch=master
+os_version=latest
+project_name=project_0
+output_project_path=D:\study material\RT-Thread\2023011402\rt-thread\bsp\apm32\apm32f103xe-minibroard - 01\project_0

project_0/README.md

@@ -27,7 +27,7 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO
 - 外部 FLASH：无
 - 常用外设
   - LED：2个，（黄色，PE5/PE6）
-  - 按键：2个，K1（兼具唤醒功能，PA0），K2（PC13）
+  - 按键：2个，K1（PA1），K2（PA0）
 - 常用接口：RS232转串口、USB SLAVE
 - 调试接口：标准 JTAG/SWD
 
@@ -37,20 +37,20 @@ APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO
 
 本 BSP 目前对外设的支持情况如下：
 
-| **板载外设** | **支持情况** | **备注**                              |
+| **板载外设** | **支持情况** | **备注**                             |
 | :----------- | :----------: | :------------------------------------ |
 | RS232转串口  |     支持     | 使用 UART1/ UART2(通过跳线选择)       |
-| **片上外设** | **支持情况** | **备注**                              |
-| GPIO         |     支持     | PA0, PA1... PG15 ---> PIN: 0, 1...143 |
+| **片上外设** | **支持情况** | **备注**                             |
+| GPIO         |     支持     | PA0, PA1... PG15 ---> PIN: 0, 1...108 |
 | UART         |     支持     | UART1/2                               |
 | ADC          |     支持     | ADC1/2/3                              |
 | DAC          |     支持     | DAC1                                  |
-| RTC          |     支持     |                                   |
-| TMR          |     支持     | TMR1/2/3/4/5/6/7/8                |
-| PWM          |     支持     | TMR3 ->CH1/2                      |
-| I2C          |     支持     | 软件I2C                           |
-| SPI          |     支持     | SPI1/2/3                          |
-| WDT          |     支持     | IWDT                              |
+| RTC          |     支持     | 支持外部晶振和内部低速时钟            |
+| TMR          |     支持     | TMR1/2/3/4/5/6/7/8                    |
+| PWM          |     支持     | TMR3 ->CH1/2/3/4                      |
+| I2C          |     支持     | 软件I2C                               |
+| SPI          |     支持     | SPI1/2/3                              |
+| WDT          |     支持     | IWDT                                  |
 
 ## 使用说明
 

project_0/SConstruct

@@ -30,7 +30,7 @@ env = Environment(tools = ['mingw'],
     LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 
-if rtconfig.PLATFORM == 'iar':
+if rtconfig.PLATFORM in ['iccarm']:
     env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
     env.Replace(ARFLAGS = [''])
     env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')

project_0/applications/main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,8 +17,12 @@
 
 int main(void)
 {
+    uint32_t sysclock = 0;
     /* set LED2 pin mode to output */
     rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
+    /* Print system clock */
+    sysclock = RCM_ReadSYSCLKFreq();
+    rt_kprintf("System Clock: %d\n", sysclock);
 
     while (1)
     {

project_0/board/Kconfig

@@ -22,7 +22,9 @@ menu "On-chip Peripheral Drivers"
             config BSP_USING_UART1
                 bool "Enable UART1"
                 default y
-
+            config BSP_USING_UART2
+                bool "Enable UART2"
+                default n
         endif
 
     menuconfig BSP_USING_ADC
@@ -147,7 +149,7 @@ menu "On-chip Peripheral Drivers"
         select RT_USING_PWM
         if BSP_USING_PWM
         menuconfig BSP_USING_PWM3
-            bool "Enable timer3 output pwm"
+            bool "Enable timer3 output PWM"
             default n
             if BSP_USING_PWM3
                 config BSP_USING_PWM3_CH1

project_0/board/SConscript

@@ -15,14 +15,14 @@ path =  [cwd]
 
 startup_path_prefix = SDK_LIB
 
-if rtconfig.CROSS_TOOL == 'keil':
+if rtconfig.PLATFORM in ['armcc', 'armclang']:
     src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s']
 
-if rtconfig.CROSS_TOOL == 'iar':
+if rtconfig.PLATFORM in ['iccarm']:
     src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s']
 
-if rtconfig.CROSS_TOOL == 'gcc':
-    src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s']
+if rtconfig.PLATFORM in ['gcc']:
+    src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.S']
 
 # You can select chips from the list above
 CPPDEFINES = ['APM32F10X_HD']

project_0/board/linker_scripts/link.lds

@@ -5,11 +5,11 @@
 /* Program Entry, set to mark it as "used" and avoid gc */
 MEMORY
 {
-    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
-    DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */
+    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* 512K flash */
+    RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128K /* 128K sram */
 }
 ENTRY(Reset_Handler)
-_system_stack_size = 0x200;
+_system_stack_size = 0x400;
 
 SECTIONS
 {
@@ -18,6 +18,7 @@ SECTIONS
         . = ALIGN(4);
         _stext = .;
         KEEP(*(.isr_vector))            /* Startup code */
+
         . = ALIGN(4);
         *(.text)                        /* remaining code */
         *(.text.*)                      /* remaining code */
@@ -32,22 +33,29 @@ SECTIONS
         __fsymtab_start = .;
         KEEP(*(FSymTab))
         __fsymtab_end = .;
+
         . = ALIGN(4);
         __vsymtab_start = .;
         KEEP(*(VSymTab))
         __vsymtab_end = .;
-        . = ALIGN(4);
 
         /* section information for initial. */
         . = ALIGN(4);
         __rt_init_start = .;
         KEEP(*(SORT(.rti_fn*)))
         __rt_init_end = .;
+
         . = ALIGN(4);
 
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
         . = ALIGN(4);
+
         _etext = .;
-    } > CODE = 0
+    } > ROM = 0
 
     /* .ARM.exidx is sorted, so has to go in its own output section.  */
     __exidx_start = .;
@@ -57,7 +65,8 @@ SECTIONS
 
         /* This is used by the startup in order to initialize the .data secion */
         _sidata = .;
-    } > CODE
+        _start_address_init_data = .;
+    } > ROM
     __exidx_end = .;
 
     /* .data section which is used for initialized data */
@@ -67,24 +76,36 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .data secion */
         _sdata = . ;
+        _start_address_data = .;
 
         *(.data)
         *(.data.*)
         *(.gnu.linkonce.d*)
 
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .data secion */
         _edata = . ;
-    } >DATA
+        _end_address_data = .;
+    } >RAM
 
     .stack : 
     {
+        . = ALIGN(4);
+        _sstack = .;
         . = . + _system_stack_size;
         . = ALIGN(4);
         _estack = .;
-    } >DATA
+        _end_stack = .;
+    } >RAM
 
     __bss_start = .;
+    _start_address_bss = .;
     .bss :
     {
         . = ALIGN(4);
@@ -98,10 +119,11 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .bss secion */
         _ebss = . ;
-        
+
         *(.bss.init)
-    } > DATA
+    } > RAM
     __bss_end = .;
+    _end_address_bss = .;
 
     _end = .;
 

project_0/libraries/APM32F10x_Library/APM32F10x_ETH_Driver/inc/apm32f10x_eth.h

@@ -0,0 +1,1406 @@
+/*!
+ * @file        apm32f10x_eth.c
+ *
+ * @brief       This file provides all the ETH firmware functions
+ *
+ * @version     V1.0.3
+ *
+ * @date        2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2021-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+/* Define to prevent recursive inclusion */
+#ifndef __APM32F10x_ETH_H
+#define __APM32F10x_ETH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes */
+#include "apm32f10x.h"
+
+/** @addtogroup APM32F10x_ETHDriver
+  @{
+*/
+
+/** @addtogroup ETH_Driver
+  @{
+*/
+
+/** @defgroup ETH_Enumerations
+  @{
+*/
+
+/**
+ * @brief    ETH AutoNegotiation
+ */
+typedef enum
+{
+    ETH_AUTONEGOTIATION_DISABLE,    /*!< Disable negotiation */
+    ETH_AUTONEGOTIATION_ENABLE      /*!< Enable negotiation */
+} ETH_AUTONEGOTIATION_T;
+
+/**
+ * @brief    ETH Watchdog
+ */
+typedef enum
+{
+    ETH_WATCHDOG_ENABLE,    /*!< Enable watch dog */
+    ETH_WATCHDOG_DISABLE    /*!< Disable watch dog */
+} ETH_WATCHDOG_T;
+
+/**
+ * @brief    ETH Jabber
+ */
+typedef enum
+{
+    ETH_JABBER_ENABLE,  /*!< Enable jabber */
+    ETH_JABBER_DISABLE  /*!< Disable jabber */
+} ETH_JABBER_T;
+
+/**
+ * @brief    ETH Inter Frame Gap
+ */
+typedef enum
+{
+    ETH_INTERFRAMEGAP_96BIT = 0x00, /*!< Inter-Frame gap = 96-bit */
+    ETH_INTERFRAMEGAP_88BIT = 0x01, /*!< Inter-Frame gap = 88-bit */
+    ETH_INTERFRAMEGAP_80BIT = 0x02, /*!< Inter-Frame gap = 80-bit */
+    ETH_INTERFRAMEGAP_72BIT = 0x03, /*!< Inter-Frame gap = 72-bit */
+    ETH_INTERFRAMEGAP_64BIT = 0x04, /*!< Inter-Frame gap = 64-bit */
+    ETH_INTERFRAMEGAP_56BIT = 0x05, /*!< Inter-Frame gap = 56-bit */
+    ETH_INTERFRAMEGAP_48BIT = 0x06, /*!< Inter-Frame gap = 48-bit */
+    ETH_INTERFRAMEGAP_40BIT = 0x07  /*!< Inter-Frame gap = 40-bit */
+} ETH_INTERFRAMEGAP_T;
+
+/**
+ * @brief    ETH Carrier Sense
+ */
+typedef enum
+{
+    ETH_CARRIERSENCE_ENABLE,    /*!< Disable carrier sense during transmission */
+    ETH_CARRIERSENCE_DISABLE    /*!< Ignore MII CRS signal */
+} ETH_CARRIERSENCE_T;
+
+/**
+ * @brief    ETH Speed
+ */
+typedef enum
+{
+    ETH_SPEED_10M,  /*!< 10M speed */
+    ETH_SPEED_100M  /*!< 100M speed */
+} ETH_SPEED_T;
+
+/**
+ * @brief    ETH Receive Own
+ */
+typedef enum
+{
+    ETH_RECEIVEOWN_ENABLE,  /*!< Enable receive own */
+    ETH_RECEIVEOWN_DISABLE  /*!< Disable receive own */
+} ETH_RECEIVEOWN_T;
+
+/**
+ * @brief    ETH Loop Back Mode
+ */
+typedef enum
+{
+    ETH_LOOPBACKMODE_DISABLE,   /*!< Disable loopback mode */
+    ETH_LOOPBACKMODE_ENABLE     /*!< Enable loopback mode */
+} ETH_LOOPBACKMODE_T;
+
+/**
+ * @brief    ETH Duplex Mode
+ */
+typedef enum
+{
+    ETH_MODE_HALFDUPLEX,    /*!< Half-Duplex */
+    ETH_MODE_FULLDUPLEX     /*!< Full-Duplex */
+} ETH_MODE_T;
+
+/**
+ * @brief    ETH Checksum Offload
+ */
+typedef enum
+{
+    ETH_CHECKSUMOFFLAOD_DISABLE,    /*!< Disable IPv4 checksum offload */
+    ETH_CHECKSUMOFFLAOD_ENABLE      /*!< Enable Ipv4 checksum offload */
+} ETH_CHECKSUMOFFLAOD_T;
+
+/**
+ * @brief    ETH Retry Transmission
+ */
+typedef enum
+{
+    ETH_RETRYTRANSMISSION_ENABLE,   /*!< Enable retry */
+    ETH_RETRYTRANSMISSION_DISABLE   /*!< Disable retry */
+} ETH_RETRYTRANSMISSION_T;
+
+/**
+ * @brief    ETH Automatic Pad CRC Strip
+ */
+typedef enum
+{
+    ETH_AUTOMATICPADCRCSTRIP_DISABLE,   /*!< Disable automatic pad or CRC stripping */
+    ETH_AUTOMATICPADCRCSTRIP_ENABLE     /*!< Enable automatic pad or CRC stripping */
+} ETH_AUTOMATICPADCRCSTRIP_T;
+
+/**
+ * @brief    ETH Back Off Limit
+ */
+typedef enum
+{
+    ETH_BACKOFFLIMIT_10,    /*!< Set back off limit to 10 */
+    ETH_BACKOFFLIMIT_8,     /*!< Set back off limit to 18 */
+    ETH_BACKOFFLIMIT_4,     /*!< Set back off limit to 4 */
+    ETH_BACKOFFLIMIT_1      /*!< Set back off limit to 1 */
+} ETH_BACKOFFLIMIT_T;
+
+/**
+ * @brief    ETH Deferral Check
+ */
+typedef enum
+{
+    ETH_DEFFERRALCHECK_DISABLE, /*!< Disable deferral check */
+    ETH_DEFFERRALCHECK_ENABLE   /*!< Enable deferral check */
+} ETH_DEFFERRALCHECK_T;
+
+/**
+ * @brief    ETH Receive All
+ */
+typedef enum
+{
+    ETH_RECEIVEAll_DISABLE, /*!< Disable receive all */
+    ETH_RECEIVEALL_ENABLE   /*!< Enable receive all */
+} ETH_RECEIVEAll_T;
+
+/**
+ * @brief    ETH Source Addr Filter
+ */
+typedef enum
+{
+    ETH_SOURCEADDRFILTER_DISABLE,                       /*!< Disable source address filter */
+    ETH_SOURCEADDRFILTER_NORMAL_ENABLE = BIT9,          /*!< Enable normal source address filter */
+    ETH_SOURCEADDRFILTER_INVERSE_ENABLE = BIT8 | BIT9,  /*!< Enable inverse source address filter */
+} ETH_SOURCEADDRFILTER_T;
+
+/**
+ * @brief    ETH Pass Control Frames
+ */
+typedef enum
+{
+    ETH_PASSCONTROLFRAMES_BLOCKALL = 1,             /*!< Even if all control frames except pause frames fail the
+                                                        address filter, MAC forwards them to the application */
+    ETH_PASSCONTROLFRAMES_FORWARDALL,               /*!< MAC forwards control frames to the application even if
+                                                        they do not pass the address filter */
+    ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER   /*!< MAC forwards control frames that pass through the address filter */
+} ETH_PASSCONTROLFRAMES_T;
+
+/**
+ * @brief    ETH Broadcast Frames Reception
+ */
+typedef enum
+{
+    ETH_BROADCASTFRAMESRECEPTION_ENABLE,    /*!< Enable broadcast frames */
+    ETH_BROADCASTFRAMESRECEPTION_DISABLE    /*!< Disable broadcast frames */
+} ETH_BROADCASTFRAMESRECEPTION_T;
+
+/**
+ * @brief    ETH Destination Addr Filter
+ */
+typedef enum
+{
+    ETH_DESTINATIONADDRFILTER_NORMAL,   /*!< Normal destination address filter */
+    ETH_DESTINATIONADDRFILTER_INVERSE   /*!< Inverse destination address filter */
+} ETH_DESTINATIONADDRFILTER_T;
+
+/**
+ * @brief    ETH Destination Addr Filter
+ */
+typedef enum
+{
+    ETH_PROMISCUOUS_MODE_DISABLE,   /*!< Disable promiscuous mode */
+    ETH_PROMISCUOUS_MODE_ENABLE     /*!< Enable promiscuous mode */
+} ETH_PROMISCUOUS_MODE_T;
+
+/**
+ * @brief    ETH Multicast Frames Filter
+ */
+typedef enum
+{
+    ETH_MULTICASTFRAMESFILTER_PERFECT,                      /*!< Multicast perfect filter */
+    ETH_MULTICASTFRAMESFILTER_NONE = BIT4,                  /*!< Multicast pass all multicast */
+    ETH_MULTICASTFRAMESFILTER_HASHTABLE = BIT2,             /*!< Multicast hash multicast */
+    ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE = BIT2 | BIT10 /*!< Multicast perfect hash table */
+} ETH_MULTICASTFRAMESFILTER_T;
+
+/**
+ * @brief    ETH Unicast Frames Filter
+ */
+typedef enum
+{
+    ETH_UNICASTFRAMESFILTER_PERFECT,                        /*!< Unicast perfect filter */
+    ETH_UNICASTFRAMESFILTER_HASHTABLE = BIT1,               /*!< Unicast hash table */
+    ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE = BIT1 | BIT10 /*!< Unicast perfect hash table */
+} ETH_UNICASTFRAMESFILTER_T;
+
+/**
+ * @brief    ETH Zero Quanta Pause
+ */
+typedef enum
+{
+    ETH_ZEROQUANTAPAUSE_ENABLE,     /*!< Enable zero-quanta pause */
+    ETH_ZEROQUANTAPAUSE_DISABLE     /*!< Disable zero-quanta pause */
+} ETH_ZEROQUANTAPAUSE_T;
+
+/**
+ * @brief    ETH Pause Low Threshold
+ */
+typedef enum
+{
+    ETH_PAUSELOWTHRESHOLD_MINUS4,   /*!< Minus 4 slot-time */
+    ETH_PAUSELOWTHRESHOLD_MINUS28,  /*!< Minus 28 slot-time */
+    ETH_PAUSELOWTHRESHOLD_MINUS144, /*!< Minus 144 slot-time */
+    ETH_PAUSELOWTHRESHOLD_MINUS256  /*!< Minus 256 slot-time */
+} ETH_PAUSELOWTHRESHOLD_T;
+
+/**
+ * @brief    ETH Unicast Pause Frame Detect
+ */
+typedef enum
+{
+    ETH_UNICASTPAUSEFRAMEDETECT_DISABLE,    /*!< Disable unicast pause frame detect */
+    ETH_UNICASTPAUSEFRAMEDETECT_ENABLE      /*!< Enable unicast pause frame detect */
+} ETH_UNICASTPAUSEFRAMEDETECT_T;
+
+/**
+ * @brief    ETH Receive Flow Control
+ */
+typedef enum
+{
+    ETH_RECEIVEFLOWCONTROL_DISABLE, /*!< Disable receive flow control */
+    ETH_RECEIVEFLOWCONTROL_ENABLE   /*!< Enable receive flow control */
+} ETH_RECEIVEFLOWCONTROL_T;
+
+/**
+ * @brief    ETH Transmit Flow Control
+ */
+typedef enum
+{
+    ETH_TRANSMITFLOWCONTROL_DISABLE,    /*!< Disable transmit flow control */
+    ETH_TRANSMITFLOWCONTROL_ENABLE      /*!< Enable transmit flow control */
+} ETH_TRANSMITFLOWCONTROL_T;
+
+/**
+ * @brief    ETH VLAN Tag Comparison
+ */
+typedef enum
+{
+    ETH_VLANTAGCOMPARISON_16BIT,    /*!< 16-bit VLAN tag comparison */
+    ETH_VLANTAGCOMPARISON_12BIT     /*!< 12-bit VLAN tag comparison */
+} ETH_VLANTAGCOMPARISON_T;
+
+/**
+ * @brief    ETH MAC Flags
+ */
+typedef enum
+{
+    ETH_MAC_FLAG_TST  = 0x00000200, /*!< Time stamp trigger flag */
+    ETH_MAC_FLAG_MMCT = 0x00000040, /*!< MMC transmit flag */
+    ETH_MAC_FLAG_MMCR = 0x00000020, /*!< MMC receive flag */
+    ETH_MAC_FLAG_MMC  = 0x00000010, /*!< MMC flag */
+    ETH_MAC_FLAG_PMT  = 0x00000008  /*!< PMT flag */
+} ETH_MAC_FLAG_T;
+
+/**
+ * @brief    ETH MAC Interrupts
+ */
+typedef enum
+{
+    ETH_MAC_INT_TST  = 0x00000200,  /*!< Time stamp trigger interrupt */
+    ETH_MAC_INT_MMCT = 0x00000040,  /*!< MMC transmit interrupt */
+    ETH_MAC_INT_MMCR = 0x00000020,  /*!< MMC receive interrupt */
+    ETH_MAC_INT_MMC  = 0x00000010,  /*!< MMC interrupt */
+    ETH_MAC_INT_PMT  = 0x00000008   /*!< PMT interrupt */
+} ETH_MAC_INT_T;
+
+/**
+ * @brief    ETH MAC Interrupts
+ */
+typedef enum
+{
+    ETH_MAC_ADDRESS0 = 0x00000000,  /*!< MAC Address0 */
+    ETH_MAC_ADDRESS1 = 0x00000008,  /*!< MAC Address1 */
+    ETH_MAC_ADDRESS2 = 0x00000010,  /*!< MAC Address2 */
+    ETH_MAC_ADDRESS3 = 0x00000018   /*!< MAC Address3 */
+} ETH_MAC_ADDRESS_T;
+
+/**
+ * @brief    ETH MAC addresses filter SA/DA
+ */
+typedef enum
+{
+    ETH_MAC_ADDRESSFILTER_SA,           /*!< MAC Address is used to compare with the
+                                            SA fields of the received frame */
+    ETH_MAC_ADDRESSFILTER_DA = BIT30    /*!< MAC Address is used to compare with the
+                                            DA fields of the received frame */
+} ETH_MAC_ADDRESSFILTER_T;
+
+/**
+ * @brief    ETH MAC addresses filter Mask bytes
+ */
+typedef enum
+{
+    ETH_MAC_ADDRESSMASK_BYTE6 = 0x20000000,  /*!< Mask MAC Address high reg bits [15:8] */
+    ETH_MAC_ADDRESSMASK_BYTE5 = 0x10000000,  /*!< Mask MAC Address high reg bits [7:0] */
+    ETH_MAC_ADDRESSMASK_BYTE4 = 0x08000000,  /*!< Mask MAC Address low reg bits [31:24] */
+    ETH_MAC_ADDRESSMASK_BYTE3 = 0x04000000,  /*!< Mask MAC Address low reg bits [23:16] */
+    ETH_MAC_ADDRESSMASK_BYTE2 = 0x02000000,  /*!< Mask MAC Address low reg bits [15:8] */
+    ETH_MAC_ADDRESSMASK_BYTE1 = 0x01000000   /*!< Mask MAC Address low reg bits [70] */
+} ETH_MAC_ADDRESSMASK_T;
+
+/**
+ * @brief    DMA Tx descriptor flags
+ */
+typedef enum
+{
+    ETH_DMATXDESC_OWN      = (int)0x80000000,   /*!< Descriptor is owned by DMA engine */
+    ETH_DMATXDESC_INTC     = 0x40000000,        /*!< Interrupt on completion */
+    ETH_DMATXDESC_LS       = 0x20000000,        /*!< Last Segment */
+    ETH_DMATXDESC_FS       = 0x10000000,        /*!< First Segment */
+    ETH_DMATXDESC_DISC     = 0x08000000,        /*!< Disable CRC */
+    ETH_DMATXDESC_DISP     = 0x04000000,        /*!< Disable Pad */
+    ETH_DMATXDESC_TXTSEN   = 0x02000000,        /*!< Transmit Time Stamp Enable */
+    ETH_DMATXDESC_TXENDR   = 0x00200000,        /*!< Transmit End of Ring */
+    ETH_DMATXDESC_TXCH     = 0x00100000,        /*!< Second Address Chained */
+    ETH_DMATXDESC_TXTSS    = 0x00020000,        /*!< Tx Time Stamp Status */
+    ETH_DMATXDESC_IHERR    = 0x00010000,        /*!< IP Header Error */
+    ETH_DMATXDESC_ERRS     = 0x00008000,        /*!< Error summary */
+    ETH_DMATXDESC_JTO      = 0x00004000,        /*!< Jabber Timeout */
+    ETH_DMATXDESC_FF       = 0x00002000,        /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+    ETH_DMATXDESC_IPERR    = 0x00001000,        /*!< Payload Checksum Error */
+    ETH_DMATXDESC_LSC      = 0x00000800,        /*!< Loss of Carrier: carrier lost during transmission */
+    ETH_DMATXDESC_NC       = 0x00000400,        /*!< No Carrier: no carrier signal from the transceiver */
+    ETH_DMATXDESC_LC       = 0x00000200,        /*!< Late Collision: transmission aborted due to collision */
+    ETH_DMATXDESC_EC       = 0x00000100,        /*!< Excessive Collision: transmission aborted after 16 collisions */
+    ETH_DMATXDESC_VLANF    = 0x00000080,        /*!< VLAN Frame */
+    ETH_DMATXDESC_CCNT     = 0x00000078,        /*!< Collision Count */
+    ETH_DMATXDESC_EDEF     = 0x00000004,        /*!< Excessive Deferral */
+    ETH_DMATXDESC_UFERR    = 0x00000002,        /*!< Underflow Error: late data arrival from the memory */
+    ETH_DMATXDESC_DEF      = 0x00000001         /*!< Deferred Bit */
+} ETH_DMATXDESC_FLAG_T;
+
+/**
+ * @brief    ETH DMA Tx descriptor segment
+ */
+typedef enum
+{
+    ETH_DMATXDESC_LASTSEGMENTS = BIT30, /*!< Actual Tx desc contain last segment */
+    ETH_DMATXDESC_FIRSTSEGMENT = BIT29  /*!< Actual Tx desc contain first segment */
+} ETH_DMATXDESC_SEGMENTS_T;
+
+/**
+ * @brief    ETH DMA Tx descriptor Checksum Insertion Control
+ */
+typedef enum
+{
+    ETH_DMATXDESC_CHECKSUMBYPASS,                       /*!< Checksum bypass */
+    ETH_DMATXDESC_CHECKSUMIPV4HEADER = BIT22,           /*!< IPv4 header checksum */
+    ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT = BIT23,    /*!< TCP/UDP/ICMP checksum. Pseudo header
+                                                            checksum is assumed to be present */
+    ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL = BIT22 | BIT23  /*!< TCP/UDP/ICMP checksum fully in hardware
+                                                            including pseudo header */
+} ETH_DMATXDESC_CHECKSUMB_T;
+
+/**
+ * @brief    DMA Rx descriptor status
+ */
+typedef enum
+{
+    ETH_DMARXDESC_OWN      = (int)0x80000000U,  /*!< Descriptor is owned by DMA engine */
+    ETH_DMARXDESC_ADDRF    =  0x40000000,       /*!< DA Filter Fail for the rx frame */
+    ETH_DMARXDESC_ERRS     =  0x00008000,       /*!< Error summary */
+    ETH_DMARXDESC_DESERR   =  0x00004000,       /*!< Descriptor error: no more descriptors for receive frame */
+    ETH_DMARXDESC_SADDRF   =  0x00002000,       /*!< SA Filter Fail for the received frame */
+    ETH_DMARXDESC_LERR     =  0x00001000,       /*!< Frame size not matching with length field */
+    ETH_DMARXDESC_OFERR    =  0x00000800,       /*!< Overflow Error: Frame was damaged due to buffer overflow */
+    ETH_DMARXDESC_VLANF    =  0x00000400,       /*!< VLAN Tag: received frame is a VLAN frame */
+    ETH_DMARXDESC_FDES     =  0x00000200,       /*!< First descriptor of the frame */
+    ETH_DMARXDESC_LDES     =  0x00000100,       /*!< Last descriptor of the frame */
+    ETH_DMARXDESC_IPV4HCE  =  0x00000080,       /*!< IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error */
+    ETH_DMARXDESC_LC       =  0x00000040,       /*!< Late collision occurred during reception */
+    ETH_DMARXDESC_FT       =  0x00000020,       /*!< Frame type - Ethernet, otherwise 802.3 */
+    ETH_DMARXDESC_RXWDTTO  =  0x00000010,       /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
+    ETH_DMARXDESC_RERR     =  0x00000008,       /*!< Receive error: error reported by MII interface */
+    ETH_DMARXDESC_DERR     =  0x00000004,       /*!< Dribble bit error: frame contains non int multiple of 8 bits */
+    ETH_DMARXDESC_CERR     =  0x00000002,       /*!< CRC error */
+    ETH_DMARXDESC_MAMPCE   =  0x00000001        /*!< Rx MAC Address/Payload Checksum Error:
+                                                    Rx MAC address matched/ Rx Payload Checksum Error */
+} ETH_DMARXDESC_FLAG_T;
+
+/**
+ * @brief    DMA Rx descriptor extended flags
+ */
+typedef enum
+{
+    ETH_DMAPTPRXDESC_PTPV   =  0x00002000,  /*!< PTP version */
+    ETH_DMAPTPRXDESC_PTPFT  =  0x00001000,  /*!< PTP frame type */
+    ETH_DMAPTPRXDESC_PTPMT  =  0x00000F00,  /*!< PTP message type */
+    ETH_DMAPTPRXDESC_IPV6P  =  0x00000080,  /*!< IPv6 packet received */
+    ETH_DMAPTPRXDESC_IPV4P  =  0x00000040,  /*!< IPv4 packet received */
+    ETH_DMAPTPRXDESC_IPCBP  =  0x00000020,  /*!< IP checksum bypassed */
+    ETH_DMAPTPRXDESC_IPPERR =  0x00000010,  /*!< IP payload error */
+    ETH_DMAPTPRXDESC_IPHERR =  0x00000008,  /*!< IP header error */
+    ETH_DMAPTPRXDESC_IPPT   =  0x00000007   /*!< IP payload type */
+} ETH_DMAPTPRXDESC_FLAG_T;
+
+/**
+ * @brief    ETH DMA Rx descriptor buffers
+ */
+typedef enum
+{
+    ETH_DMARXDESC_BUFFER1,  /*!< DMA Rx Desc Buffer1 */
+    ETH_DMARXDESC_BUFFER2   /*!< DMA Rx Desc Buffer2 */
+} ETH_DMARXDESC_BUFFER_T;
+
+/**
+ * @brief    ETH Drop TCP IP Checksum Error Frame
+ */
+typedef enum
+{
+    ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE,     /*!< Enable dropping of TCP/IP checksum error frame */
+    ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE     /*!< Disable dropping of TCP/IP checksum error frame */
+} ETH_DROPTCPIPCHECKSUMERRORFRAME_T;
+
+/**
+ * @brief    ETH Receive Store Forward
+ */
+typedef enum
+{
+    ETH_RECEIVESTOREFORWARD_DISABLE,    /*!< Disable receive store and forward */
+    ETH_RECEIVESTOREFORWARD_ENABLE      /*!< Enable receive store and forward */
+} ETH_RECEIVESTOREFORWARD_T;
+
+/**
+ * @brief    ETH Flush Received Frame
+ */
+typedef enum
+{
+    ETH_FLUSHRECEIVEDFRAME_ENABLE,  /*!< Enable flushing of received frames */
+    ETH_FLUSHRECEIVEDFRAME_DISABLE  /*!< Disable flushing of received frames */
+} ETH_FLUSHRECEIVEDFRAME_T;
+
+/**
+ * @brief    ETH Transmit Store Forward
+ */
+typedef enum
+{
+    ETH_TRANSMITSTOREFORWARD_DISABLE,   /*!< Disable transmit store and forward */
+    ETH_TRANSMITSTOREFORWARD_ENABLE     /*!< Enable transmit store and forward */
+} ETH_TRANSMITSTOREFORWARD_T;
+
+/**
+ * @brief    ETH Transmit Threshold Control
+ */
+typedef enum
+{
+    ETH_TRANSMITTHRESHOLDCONTROL_64BYTES,   /*!< Select 64 bytes transmit threshild level */
+    ETH_TRANSMITTHRESHOLDCONTROL_128BYTES,  /*!< Select 128 bytes transmit threshild level */
+    ETH_TRANSMITTHRESHOLDCONTROL_192BYTES,  /*!< Select 192 bytes transmit threshild level */
+    ETH_TRANSMITTHRESHOLDCONTROL_256BYTES,  /*!< Select 256 bytes transmit threshild level */
+    ETH_TRANSMITTHRESHOLDCONTROL_40BYTES,   /*!< Select 40 bytes transmit threshild level */
+    ETH_TRANSMITTHRESHOLDCONTROL_32BYTES,   /*!< Select 32 bytes transmit threshild level */
+    ETH_TRANSMITTHRESHOLDCONTROL_24BYTES,   /*!< Select 24 bytes transmit threshild level */
+    ETH_TRANSMITTHRESHOLDCONTROL_16BYTES    /*!< Select 16 bytes transmit threshild level */
+} ETH_TRANSMITTHRESHOLDCONTROL_T;
+
+/**
+ * @brief    ETH Forward Error Frames
+ */
+typedef enum
+{
+    ETH_FORWARDERRORFRAMES_DISABLE, /*!< Disable forward error frames */
+    ETH_FORWARDERRORFRAMES_ENABLE   /*!< Enable forward error frames */
+} ETH_FORWARDERRORFRAMES_T;
+
+/**
+ * @brief    ETH Forward Undersized Good Frames
+ */
+typedef enum
+{
+    ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE,    /*!< Disable forward undersized good frames */
+    ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE      /*!< Enable forward undersized good frames */
+} ETH_FORWARDUNDERSIZEDGOODFRAMES_T;
+
+/**
+ * @brief    ETH Receive Threshold Control
+ */
+typedef enum
+{
+    ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES,   /*!< Select 64 bytes receive threshold level */
+    ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES,   /*!< Select 32 bytes receive threshold level */
+    ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES,   /*!< Select 96 bytes receive threshold level */
+    ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES   /*!< Select 128 bytes receive threshold level */
+} ETH_RECEIVEDTHRESHOLDCONTROL_T;
+
+/**
+ * @brief    ETH Second Frame Operate
+ */
+typedef enum
+{
+    ETH_SECONDFRAMEOPERARTE_DISABLE,    /*!< Disable second frame operate */
+    ETH_SECONDFRAMEOPERARTE_ENABLE      /*!< Enable second frame operate */
+} ETH_SECONDFRAMEOPERARTE_T;
+
+/**
+ * @brief    ETH Address Aligned Beats
+ */
+typedef enum
+{
+    ETH_ADDRESSALIGNEDBEATS_DISABLE,    /*!< Disable address aligned beats */
+    ETH_ADDRESSALIGNEDBEATS_ENABLE      /*!< Enable address aligned beats */
+} ETH_ADDRESSALIGNEDBEATS_T;
+
+/**
+ * @brief    ETH Fixed Burst
+ */
+typedef enum
+{
+    ETH_FIXEDBURST_DISABLE, /*!< Disable fixed burst */
+    ETH_FIXEDBURST_ENABLE   /*!< Enable fixed burst */
+} ETH_FIXEDBURST_T;
+
+/**
+ * @brief    ETH Rx DMA Burst Length
+ */
+typedef enum
+{
+    ETH_RXDMABURSTLENGTH_1BEAT        = BIT17,          /*!< Maxnum number of Rx DMA transaction = 1 beat */
+    ETH_RXDMABURSTLENGTH_2BEAT        = BIT18,          /*!< Maxnum number of Rx DMA transaction = 2 beat */
+    ETH_RXDMABURSTLENGTH_4BEAT        = BIT19,          /*!< Maxnum number of Rx DMA transaction = 4 beat */
+    ETH_RXDMABURSTLENGTH_8BEAT        = BIT20,          /*!< Maxnum number of Rx DMA transaction = 8 beat */
+    ETH_RXDMABURSTLENGTH_16BEAT       = BIT21,          /*!< Maxnum number of Rx DMA transaction = 16 beat */
+    ETH_RXDMABURSTLENGTH_32BEAT       = BIT22,          /*!< Maxnum number of Rx DMA transaction = 32 beat */
+    ETH_RXDMABURSTLENGTH_4XPBL_4BEAT  = BIT17 | BIT24,  /*!< Maxnum number of Rx DMA transaction = 4 beat */
+    ETH_RXDMABURSTLENGTH_4XPBL_8BEAT  = BIT18 | BIT24,  /*!< Maxnum number of Rx DMA transaction = 8 beat */
+    ETH_RXDMABURSTLENGTH_4XPBL_16BEAT = BIT19 | BIT24,  /*!< Maxnum number of Rx DMA transaction = 16 beat */
+    ETH_RXDMABURSTLENGTH_4XPBL_32BEAT = BIT20 | BIT24,  /*!< Maxnum number of Rx DMA transaction = 32 beat */
+    ETH_RXDMABURSTLENGTH_4XPBL_64BEAT = BIT21 | BIT24,  /*!< Maxnum number of Rx DMA transaction = 64 beat */
+    ETH_RXDMABURSTLENGTH_4XPBL_128BEAT = BIT22 | BIT24  /*!< Maxnum number of Rx DMA transaction = 128 beat */
+} ETH_RXDMABURSTLENGTH_T;
+
+/**
+ * @brief    ETH Tx DMA Burst Length
+ */
+typedef enum
+{
+    ETH_TXDMABURSTLENGTH_1BEAT        = BIT8,           /*!< Maxnum number of Tx DMA transaction = 1 beat */
+    ETH_TXDMABURSTLENGTH_2BEAT        = BIT9,           /*!< Maxnum number of Tx DMA transaction = 2 beat */
+    ETH_TXDMABURSTLENGTH_4BEAT        = BIT10,          /*!< Maxnum number of Tx DMA transaction = 4 beat */
+    ETH_TXDMABURSTLENGTH_8BEAT        = BIT11,          /*!< Maxnum number of Tx DMA transaction = 8 beat */
+    ETH_TXDMABURSTLENGTH_16BEAT       = BIT12,          /*!< Maxnum number of Tx DMA transaction = 16 beat */
+    ETH_TXDMABURSTLENGTH_32BEAT       = BIT13,          /*!< Maxnum number of Tx DMA transaction = 32 beat */
+    ETH_TXDMABURSTLENGTH_4XPBL_4BEAT  = BIT8 | BIT24,   /*!< Maxnum number of Tx DMA transaction = 4 beat */
+    ETH_TXDMABURSTLENGTH_4XPBL_8BEAT  = BIT9 | BIT24,   /*!< Maxnum number of Tx DMA transaction = 8 beat */
+    ETH_TXDMABURSTLENGTH_4XPBL_16BEAT = BIT10 | BIT24,  /*!< Maxnum number of Tx DMA transaction = 16 beat */
+    ETH_TXDMABURSTLENGTH_4XPBL_32BEAT = BIT11 | BIT24,  /*!< Maxnum number of Tx DMA transaction = 32 beat */
+    ETH_TXDMABURSTLENGTH_4XPBL_64BEAT = BIT12 | BIT24,  /*!< Maxnum number of Tx DMA transaction = 64 beat */
+    ETH_TXDMABURSTLENGTH_4XPBL_128BEAT = BIT13 | BIT24  /*!< Maxnum number of Tx DMA transaction = 128 beat */
+} ETH_TXDMABURSTLENGTH_T;
+
+/**
+ * @brief    ETH DMA Arbitration
+ */
+typedef enum
+{
+    ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1,                 /*!< Priority ratio RX : TX = 1 : 1 */
+    ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 = BIT14,         /*!< Priority ratio RX : TX = 2 : 1 */
+    ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 = BIT15,         /*!< Priority ratio RX : TX = 3 : 1 */
+    ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 = BIT14 | BIT15, /*!< Priority ratio RX : TX = 4 : 1 */
+    ETH_DMAARBITRATION_RXPRIORTX = BIT1                     /*!< Rx priority ratio higher than Tx */
+} ETH_DMAARBITRATION_T;
+
+/**
+ * @brief    ETH DMA Flags
+ */
+typedef enum
+{
+    ETH_DMA_FLAG_TST               = 0x20000000,   /*!< Time-stamp trigger interrupt (on DMA) */
+    ETH_DMA_FLAG_PMT               = 0x10000000,   /*!< PMT interrupt (on DMA) */
+    ETH_DMA_FLAG_MMC               = 0x08000000,   /*!< MMC interrupt (on DMA) */
+    ETH_DMA_FLAG_DATATRANSFERERROR = 0x00800000,   /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+    ETH_DMA_FLAG_READWRITEERROR    = 0x01000000,   /*!< Error bits 0-write transfer, 1-read transfer */
+    ETH_DMA_FLAG_ACCESSERROR       = 0x02000000,   /*!< Error bits 0-data buffer, 1-desc. access */
+    ETH_DMA_FLAG_NIS               = 0x00010000,   /*!< Normal interrupt summary flag */
+    ETH_DMA_FLAG_AIS               = 0x00008000,   /*!< Abnormal interrupt summary flag */
+    ETH_DMA_FLAG_ER                = 0x00004000,   /*!< Early receive flag */
+    ETH_DMA_FLAG_FBE               = 0x00002000,   /*!< Fatal bus error flag */
+    ETH_DMA_FLAG_ET                = 0x00000400,   /*!< Early transmit flag */
+    ETH_DMA_FLAG_RWT               = 0x00000200,   /*!< Receive watchdog timeout flag */
+    ETH_DMA_FLAG_RPS               = 0x00000100,   /*!< Receive process stopped flag */
+    ETH_DMA_FLAG_RBU               = 0x00000080,   /*!< Receive buffer unavailable flag */
+    ETH_DMA_FLAG_RX                = 0x00000040,   /*!< Receive flag */
+    ETH_DMA_FLAG_TU                = 0x00000020,   /*!< Underflow flag */
+    ETH_DMA_FLAG_RO                = 0x00000010,   /*!< Overflow flag */
+    ETH_DMA_FLAG_TJT               = 0x00000008,   /*!< Transmit jabber timeout flag */
+    ETH_DMA_FLAG_TBU               = 0x00000004,   /*!< Transmit buffer unavailable flag */
+    ETH_DMA_FLAG_TPS               = 0x00000002,   /*!< Transmit process stopped flag */
+    ETH_DMA_FLAG_TX                = 0x00000001    /*!< Transmit flag */
+} ETH_DMA_FLAG_T;
+
+/**
+ * @brief    ETH DMA Interrupts
+ */
+typedef enum
+{
+    ETH_DMA_INT_TST   =   0x20000000,   /*!< Time-stamp trigger interrupt (on DMA) */
+    ETH_DMA_INT_PMT   =   0x10000000,   /*!< PMT interrupt (on DMA) */
+    ETH_DMA_INT_MMC   =   0x08000000,   /*!< MMC interrupt (on DMA) */
+    ETH_DMA_INT_NIS   =   0x00010000,   /*!< Normal interrupt summary */
+    ETH_DMA_INT_AIS   =   0x00008000,   /*!< Abnormal interrupt summary */
+    ETH_DMA_INT_ER    =   0x00004000,   /*!< Early receive interrupt */
+    ETH_DMA_INT_FBE   =   0x00002000,   /*!< Fatal bus error interrupt */
+    ETH_DMA_INT_ET    =   0x00000400,   /*!< Early transmit interrupt */
+    ETH_DMA_INT_RWT   =   0x00000200,   /*!< Receive watchdog timeout interrupt */
+    ETH_DMA_INT_RPS   =   0x00000100,   /*!< Receive process stopped interrupt */
+    ETH_DMA_INT_RBU   =   0x00000080,   /*!< Receive buffer unavailable interrupt */
+    ETH_DMA_INT_RX    =   0x00000040,   /*!< Receive interrupt */
+    ETH_DMA_INT_TU    =   0x00000020,   /*!< Underflow interrupt */
+    ETH_DMA_INT_RO    =   0x00000010,   /*!< Overflow interrupt */
+    ETH_DMA_INT_TJT   =   0x00000008,   /*!< Transmit jabber timeout interrupt */
+    ETH_DMA_INT_TBU   =   0x00000004,   /*!< Transmit buffer unavailable interrupt */
+    ETH_DMA_INT_TPS   =   0x00000002,   /*!< Transmit process stopped interrupt */
+    ETH_DMA_INT_TX    =   0x00000001    /*!< Transmit interrupt */
+} ETH_DMA_INT_T;
+
+/**
+ * @brief    ETH DMA transmit process state
+ */
+typedef enum
+{
+    ETH_DMA_TRANSMITPROCESS_STOPPED,            /*!< Stopped - Reset or Stop Tx Command issued */
+    ETH_DMA_TRANSMITPROCESS_FETCHING,           /*!< Running - fetching the Tx descriptor */
+    ETH_DMA_TRANSMITPROCESS_WAITING,            /*!< Running - waiting for status */
+    ETH_DMA_TRANSMITPROCESS_READING,            /*!< Running - reading the data from host memory */
+    ETH_DMA_TRANSMITPROCESS_SUSPENDED = 0x06,   /*!< Suspended - Tx Descriptor unavailable */
+    ETH_DMA_TRANSMITPROCESS_CLOSING = 0x07,     /*!< Running - closing Rx descriptor */
+} ETH_DMA_TRANSMITPROCESS_T;
+
+/**
+ * @brief    ETH DMA receive process state
+ */
+typedef enum
+{
+    ETH_DMA_RECEIVEPROCESS_STOPPED,             /*!< Stopped - Reset or Stop Rx Command issued */
+    ETH_DMA_RECEIVEPROCESS_FETCHING  = 0x02,    /*!< Running - fetching the Rx descriptor */
+    ETH_DMA_RECEIVEPROCESS_WAITING   = 0x06,    /*!< Running - waiting for packet */
+    ETH_DMA_RECEIVEPROCESS_SUSPENDED = 0x08,    /*!< Suspended - Rx Descriptor unavailable */
+    ETH_DMA_RECEIVEPROCESS_CLOSING   = 0x0A,    /*!< Running - closing descriptor */
+    ETH_DMA_RECEIVEPROCESS_QUEUING   = 0x0E     /*!< Running - queuing the receive frame into host memory */
+} ETH_DMA_RECEIVEPROCESS_T;
+
+/**
+ * @brief    ETH DMA overflow
+ */
+typedef enum
+{
+    ETH_DMA_OVERFLOW_RXFIFOCOUNTER = BIT28,     /*!< Overflow for FIFO Overflows Counter */
+    ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER = BIT16 /*!< Overflow for Buffer Unavailable Missed Frame Counter */
+} ETH_DMA_OVERFLOW_T;
+
+/**
+ * @brief    ETH PMT Flags
+ */
+typedef enum
+{
+    ETH_PMT_FLAG_WUFFRPR = (int)BIT31,  /*!< Wake-Up Frame Filter Register Pointer Reset */
+    ETH_PMT_FLAG_WUFR = BIT6,           /*!< Wake-Up Frame Received */
+    ETH_PMT_FLAG_MPR = BIT5             /*!< Magic Packet Received */
+} ETH_PMT_FLAG_T;
+
+/**
+ * @brief    ETH MMC Tx/RX Interrupts
+ */
+typedef enum
+{
+    ETH_MMC_INT_TGF    = BIT21,         /*!< When Tx good frame counter reaches half the maximum value */
+    ETH_MMC_INT_TGFMSC = BIT15,         /*!< When Tx good multi col counter reaches half the maximum value */
+    ETH_MMC_INT_TGFSC  = BIT14,         /*!< When Tx good single col counter reaches half the maximum value */
+    ETH_MMC_INT_RGUF   = BIT21 | BIT30, /*!< When Rx good unicast frames counter reaches half the maximum value */
+    ETH_MMC_INT_RFAE   = BIT6 | BIT30,  /*!< When Rx alignment error counter reaches half the maximum value */
+    ETH_MMC_INT_RFCE   = BIT5 | BIT30   /*!< When Rx crc error counter reaches half the maximum value */
+} ETH_MMC_INT_T;
+
+/**
+ * @brief    ETH MMC Registers
+ */
+typedef enum
+{
+    ETH_MMC_CTRL       =  0x00000100,   /*!< MMC CTRL register */
+    ETH_MMC_RXINT      =  0x00000104,   /*!< MMC RXINT register */
+    ETH_MMC_TXINT      =  0x00000108,   /*!< MMC TXINT register */
+    ETH_MMC_RXINTMASK  =  0x0000010C,   /*!< MMC RXINTMASK register */
+    ETH_MMC_TXINTMASK  =  0x00000110,   /*!< MMC TXINTMASK register */
+    ETH_MMC_TXGFSCCNT  =  0x0000014C,   /*!< MMC TXGFSCCNT register */
+    ETH_MMC_TXGFMCCNT  =  0x00000150,   /*!< MMC TXGFMCCNT register */
+    ETH_MMC_TXGFCNT    =  0x00000168,   /*!< MMC TXGFCNT register */
+    ETH_MMC_RXFCECNT   =  0x00000194,   /*!< MMC RXFCECNT register */
+    ETH_MMC_RXFAECNT   =  0x00000198,   /*!< MMC RXFAECNT register */
+    ETH_MMC_RXGUNCNT   =  0x000001C4    /*!< MMC RXGUNCNT register */
+} ETH_MMC_REG_T;
+
+/**@} end of group ETH_Enumerations*/
+
+
+/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
+  * @{
+  */
+
+/**
+*  DMA Tx Descriptor
+*  -----------------------------------------------------------------------------------------------
+*  TXDES0 | OWN(31) | CTRL[30:25] | Reserved(24) | CTRL[23:20] | Reserved[19:18] | Status[17:0]   |
+*  -----------------------------------------------------------------------------------------------
+*  TXDES1 | Reserved[31:29] | Buffer2 Size[28:16] | Reserved[15:13] | Buffer1 Size[12:0]          |
+*  -----------------------------------------------------------------------------------------------
+*  TXDES2 |                         Buffer1 Address [31:0]                                        |
+*  -----------------------------------------------------------------------------------------------
+*  TXDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]             |
+*  -----------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of TXDES0 register: DMA Tx descriptor status register
+  */
+#define ETH_DMATXDESC_OWN                     0x80000000U   /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXDESC_INTC                    0x40000000U   /*!< Interrupt on Completion */
+#define ETH_DMATXDESC_LS                      0x20000000U   /*!< Last Segment */
+#define ETH_DMATXDESC_FS                      0x10000000U   /*!< First Segment */
+#define ETH_DMATXDESC_DISC                    0x08000000U   /*!< Disable CRC */
+#define ETH_DMATXDESC_DISP                    0x04000000U   /*!< Disable Padding */
+#define ETH_DMATXDESC_TXTSEN                  0x02000000U   /*!< Transmit Time Stamp Enable */
+#define ETH_DMATXDESC_CIC                     0x00C00000U   /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXDESC_CIC_BYPASS              0x00000000U   /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATXDESC_CIC_IPV4HEADER          0x00400000U   /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  0x00800000U   /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     0x00C00000U   /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATXDESC_TXENDR                  0x00200000U   /*!< Transmit End of Ring */
+#define ETH_DMATXDESC_TXCH                    0x00100000U   /*!< Second Address Chained */
+#define ETH_DMATXDESC_TXTSS                   0x00020000U   /*!< Tx Time Stamp Status */
+#define ETH_DMATXDESC_IHERR                   0x00010000U   /*!< IP Header Error */
+#define ETH_DMATXDESC_ERRS                    0x00008000U   /*!< Error summary: OR of the following bits: UFERR || EDEF || EC || LC || NC || LSC || FF || JTO */
+#define ETH_DMATXDESC_JTO                     0x00004000U   /*!< Jabber Timeout */
+#define ETH_DMATXDESC_FF                      0x00002000U   /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATXDESC_IPERR                   0x00001000U   /*!< Payload Checksum Error */
+#define ETH_DMATXDESC_LSC                     0x00000800U   /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXDESC_NC                      0x00000400U   /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXDESC_LC                      0x00000200U   /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXDESC_EC                      0x00000100U   /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXDESC_VLANF                   0x00000080U   /*!< VLAN Frame */
+#define ETH_DMATXDESC_CCNT                    0x00000078U   /*!< Collision Count */
+#define ETH_DMATXDESC_EDEF                    0x00000004U   /*!< Excessive Deferral */
+#define ETH_DMATXDESC_UFERR                   0x00000002U   /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXDESC_DEF                     0x00000001U   /*!< Deferred Bit */
+
+/**
+  * @brief  Bit definition of TXDES1 register
+  */
+#define ETH_DMATXDESC_TXBS2  0x1FFF0000U /*!< Transmit Buffer2 Size */
+#define ETH_DMATXDESC_TXBS1  0x00001FFFU /*!< Transmit Buffer1 Size */
+
+/**
+  * @brief  Bit definition of TXDES2 register
+  */
+#define ETH_DMATXDESC_B1AP  0xFFFFFFFFU /*!< Buffer1 Address Pointer */
+
+/**
+  * @brief  Bit definition of TXDES3 register
+  */
+#define ETH_DMATXDESC_B2AP  0xFFFFFFFFU /*!< Buffer2 Address Pointer */
+
+/**
+*  ---------------------------------------------------------------------------------------------
+*  TXDES6 |                         Transmit Time Stamp Low [31:0]                               |
+*  ---------------------------------------------------------------------------------------------
+*  TXDES7 |                         Transmit Time Stamp High [31:0]                              |
+*  ----------------------------------------------------------------------------------------------
+*/
+
+/* Bit definition of TXDES6 register */
+#define ETH_DMAPTPTXDESC_TXTSL  0xFFFFFFFFU  /*!< Transmit Time Stamp Low */
+
+/* Bit definition of TXDES7 register */
+#define ETH_DMAPTPTXDESC_TXTSH  0xFFFFFFFFU  /*!< Transmit Time Stamp High */
+
+/**
+  * @}
+  */
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
+  * @{
+  */
+
+/**
+  *DMA Rx Descriptor
+  *--------------------------------------------------------------------------------------------------------------------
+  *RXDES0 | OWN(31) |                                             Status [30:0]                                         |
+  *---------------------------------------------------------------------------------------------------------------------
+  *RXDES1 | CTRL(31) | Reserved[30:29] | Buffer2 Size[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 Size[12:0]          |
+  *---------------------------------------------------------------------------------------------------------------------
+  *RXDES2 |                                       Buffer1 Address [31:0]                                                |
+  *---------------------------------------------------------------------------------------------------------------------
+  *RXDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                            |
+  *---------------------------------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of RXDES0 register: DMA Rx descriptor status register
+  */
+#define ETH_DMARXDESC_OWN         0x80000000U   /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMARXDESC_ADDRF       0x40000000U   /*!< DA Filter Fail for the rx frame */
+#define ETH_DMARXDESC_FL          0x3FFF0000U   /*!< Receive descriptor frame length */
+#define ETH_DMARXDESC_ERRS        0x00008000U   /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARXDESC_DESERR      0x00004000U   /*!< Descriptor error: no more descriptors for receive frame */
+#define ETH_DMARXDESC_SADDRF      0x00002000U   /*!< SA Filter Fail for the received frame */
+#define ETH_DMARXDESC_LERR        0x00001000U   /*!< Frame size not matching with length field */
+#define ETH_DMARXDESC_OFERR       0x00000800U   /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARXDESC_VLANF       0x00000400U   /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARXDESC_FDES        0x00000200U   /*!< First descriptor of the frame */
+#define ETH_DMARXDESC_LDES        0x00000100U   /*!< Last descriptor of the frame */
+#define ETH_DMARXDESC_IPV4HCE     0x00000080U   /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
+#define ETH_DMARXDESC_LC          0x00000040U   /*!< Late collision occurred during reception */
+#define ETH_DMARXDESC_FT          0x00000020U   /*!< Frame type - Ethernet, otherwise 802.3 */
+#define ETH_DMARXDESC_RXWWTTO     0x00000010U   /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
+#define ETH_DMARXDESC_RERR        0x00000008U   /*!< Receive error: error reported by MII interface */
+#define ETH_DMARXDESC_DERR        0x00000004U   /*!< Dribble bit error: frame contains non int multiple of 8 bits */
+#define ETH_DMARXDESC_CERR        0x00000002U   /*!< CRC error */
+#define ETH_DMARXDESC_MAMPCE      0x00000001U   /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/**
+  * @brief  Bit definition of RXDES1 register
+  */
+#define ETH_DMARXDESC_DINTC  0x80000000U /*!< Disable Interrupt on Completion */
+#define ETH_DMARXDESC_RXBS2  0x1FFF0000U /*!< Receive Buffer2 Size */
+#define ETH_DMARXDESC_RXER   0x00008000U /*!< Receive End of Ring */
+#define ETH_DMARXDESC_RXCH   0x00004000U /*!< Second Address Chained */
+#define ETH_DMARXDESC_RXBS1  0x00001FFFU /*!< Receive Buffer1 Size */
+
+/**
+  * @brief  Bit definition of RXDES2 register
+  */
+#define ETH_DMARXDESC_B1AP  0xFFFFFFFFU /*!< Buffer1 Address Pointer */
+
+/**
+  * @brief  Bit definition of RXDES3 register
+  */
+#define ETH_DMARXDESC_B2AP  0xFFFFFFFFU /*!< Buffer2 Address Pointer */
+
+/**
+  *---------------------------------------------------------------------------------------------------------------------
+  *RXDES4 |                   Reserved[31:14]              |             Extended Status [13:0]                         |
+  *---------------------------------------------------------------------------------------------------------------------
+  *RXDES5 |                                            Reserved[31:0]                                                   |
+  *---------------------------------------------------------------------------------------------------------------------
+  *RXDES6 |                                       Receive Time Stamp Low [31:0]                                         |
+  *---------------------------------------------------------------------------------------------------------------------
+  *RXDES7 |                                       Receive Time Stamp High [31:0]                                        |
+  *---------------------------------------------------------------------------------------------------------------------
+*/
+
+/* Bit definition of RXDES4 register */
+#define ETH_DMAPTPRXDESC_PTPV     0x00002000U                           /*!< PTP Version */
+#define ETH_DMAPTPRXDESC_PTPFT    0x00001000U                           /*!< PTP Frame Type */
+#define ETH_DMAPTPRXDESC_PTPMT    0x00000F00U                           /*!< PTP Message Type */
+#define ETH_DMAPTPRXDESC_PTPMT_SYNC                      0x00000100U    /*!< SYNC message (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP                  0x00000200U    /*!< FollowUp message (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ                  0x00000300U    /*!< DelayReq message (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP                 0x00000400U    /*!< DelayResp message (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE        0x00000500U    /*!< PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG          0x00000600U    /*!< PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U    /*!< PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
+#define ETH_DMAPTPRXDESC_IPV6P    0x00000080U                           /*!< IPv6 Packet Received */
+#define ETH_DMAPTPRXDESC_IPV4P    0x00000040U                           /*!< IPv4 Packet Received */
+#define ETH_DMAPTPRXDESC_IPCBP    0x00000020U                           /*!< IP Checksum Bypassed */
+#define ETH_DMAPTPRXDESC_IPPERR   0x00000010U                           /*!< IP Payload Error */
+#define ETH_DMAPTPRXDESC_IPHERR   0x00000008U                           /*!< IP Header Error */
+#define ETH_DMAPTPRXDESC_IPPT     0x00000007U                           /*!< IP Payload Type */
+#define ETH_DMAPTPRXDESC_IPPT_UDP                 0x00000001U           /*!< UDP payload encapsulated in the IP datagram */
+#define ETH_DMAPTPRXDESC_IPPT_TCP                 0x00000002U           /*!< TCP payload encapsulated in the IP datagram */
+#define ETH_DMAPTPRXDESC_IPPT_ICMP                0x00000003U           /*!< ICMP payload encapsulated in the IP datagram */
+
+/* Bit definition of RXDES6 register */
+#define ETH_DMAPTPRXDESC_RXTSL  0xFFFFFFFFU  /*!< Receive Time Stamp Low */
+
+/* Bit definition of RXDES7 register */
+#define ETH_DMAPTPRXDESC_RXTSH  0xFFFFFFFFU  /*!< Receive Time Stamp High */
+/**
+  * @}
+  */
+
+
+/** @addtogroup ETH_Macros Macros
+  *@{
+  */
+
+/* ETH Frames defines */
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE  /*!< buffer size for receive */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE  /*!< buffer size for transmit */
+#define ETH_RXBUFNB                    (5U)                /*!< 5 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB                    (5U)                /*!< 5 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* ETH_Buffers_setting ETH Buffers setting */
+#define ETH_MAX_PACKET_SIZE       1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER                14U   /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC                   4U    /*!< Ethernet CRC */
+#define ETH_EXTRA                 2U    /*!< Extra bytes in some cases */
+#define ETH_VLAN_TAG              4U    /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_ETH_PAYLOAD       46U   /*!< Minimum Ethernet payload size */
+#define ETH_MAX_ETH_PAYLOAD       1500U /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD   9000U /*!< Jumbo frame payload size */
+
+/**
+*  Ethernet driver receive buffers are organized in a chained linked-list, when
+*  an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
+*  to the driver receive buffers memory.
+*
+*  Depending on the size of the received ethernet packet and the size of
+*  each ethernet driver receive buffer, the received packet can take one or more
+*  ethernet driver receive buffer.
+*
+*  In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
+*  and the total count of the driver receive buffers ETH_RXBUFNB.
+*
+*  The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
+*  example, they can be reconfigured in the application layer to fit the application
+*  needs
+*/
+
+/** Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
+*   packet
+*/
+#ifndef ETH_RX_BUF_SIZE
+#define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
+#ifndef ETH_RXBUFNB
+#define ETH_RXBUFNB             5U  /*!< 5 Rx buffers of size ETH_RX_BUF_SIZE */
+#endif
+
+/**
+*  Ethernet driver transmit buffers are organized in a chained linked-list, when
+*  an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
+*  driver transmit buffers memory to the TxFIFO.
+*
+*  Depending on the size of the Ethernet packet to be transmitted and the size of
+*  each ethernet driver transmit buffer, the packet to be transmitted can take
+*  one or more ethernet driver transmit buffer.
+*
+*  In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
+*  and the total count of the driver transmit buffers ETH_TXBUFNB.
+*
+*  The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
+*  example, they can be reconfigured in the application layer to fit the application
+*  needs
+*/
+
+/** Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
+*   packet
+*/
+#ifndef ETH_TX_BUF_SIZE
+#define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
+#ifndef ETH_TXBUFNB
+#define ETH_TXBUFNB             5U  /*!< 5  Tx buffers of size ETH_TX_BUF_SIZE */
+#endif
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_ADDR_HBASE   (ETH_MAC_BASE + 0x40)      /*!< ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE    (ETH_MAC_BASE + 0x44)     /*!< ETHERNET MAC address low offset */
+
+/* ETHERNET Errors */
+#define  ETH_SUCCESS            1U
+#define  ETH_ERROR              0U
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define  ETH_DMATXDESC_COLLISION_COUNTSHIFT        3U
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           16U
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           16U
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           16U
+
+/* ETHERNET DMA Rx descriptors Frame length Shift */
+#define  ETH_DMARXDESC_FRAMELENGTHSHIFT            16U
+
+/* ETHERNET MACMIIAR register Mask */
+#define ETH_MACMIIAR_CR_MASK    0xFFFFFFE3U
+
+/* ETHERNET MACCR register Mask */
+#define ETH_MACCR_CLEAR_MASK    0xFF20010FU
+
+/* ETHERNET MACFCR register Mask */
+#define ETH_MACFCR_CLEAR_MASK   0x0000FF41U
+
+/* ETHERNET DMAOMR register Mask */
+#define ETH_DMAOMR_CLEAR_MASK   0xF8DE3F23U
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH      8U
+
+/* ETHERNET Missed frames counter Shift */
+#define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17U
+
+/* PHY registers defines */
+
+/* PHY Read write Timeouts */
+#define PHY_READ_TIMEOUT                ((uint32_t)0x0004FFFF)
+#define PHY_WRITE_TIMEOUT               ((uint32_t)0x0004FFFF)
+
+/* PHY Register address */
+#define PHY_BCR                                      0         /*!< Transceiver Basic Control Register */
+#define PHY_BSR                                      1         /*!< Transceiver Basic Status Register */
+#define PHY_SR                                       16        /*!< Transceiver Status Register for dp83848 */
+
+/* PHY Status Register (PHYSTS), address 0x10 */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)     /*!< for dp83848 ((uint16_t)0x0010) */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)     /*!< for dp83848 ((uint16_t)0x0004) */
+
+/* PHY basic status register */
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)     /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)     /*!< Valid link established */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)     /*!< Jabber condition detected */
+
+/* PHY basic Control register */
+#define PHY_RESET                       ((uint16_t)0x8000)     /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)     /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)     /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)     /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)     /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)     /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)     /*!< Enable auto-negotiation function */
+#define PHY_RESTAET_AUTONEGOTIATION     ((uint16_t)0x0200)     /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)     /*!< Select the power down mode */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)     /*!< Isolate PHY from MII */
+
+/* PHY Delay */
+#define PHY_RESET_DELAY                 ((uint32_t)0x000FFFFF) /*!< PHY reset delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00FFFFFF) /*!< PHY configuration delay */
+/* Delay to wait when writing to some Ethernet registers */
+#define ETH_REG_WRITE_DELAY             ((uint32_t)0x0000FFFF)
+
+/* Ethernet MAC MII Address Clock Range*/
+#define ETH_MACMIIAR_CR_DIV42   ((uint8_t)0x00)                 /*!< HCLK:60-100 MHz; MDC clock = HCLK/42 */
+#define ETH_MACMIIAR_CR_DIV62   ((uint8_t)0x01)                 /*!< HCLK:100-150 MHz; MDC clock = HCLK/62 */
+#define ETH_MACMIIAR_CR_DIV16   ((uint8_t)0x02)                 /*!< HCLK:20-35 MHz; MDC clock = HCLK/16 */
+#define ETH_MACMIIAR_CR_DIV26   ((uint8_t)0x03)                 /*!< HCLK:35-60 MHz; MDC clock = HCLK/26 */
+#define ETH_MACMIIAR_CR_DIV102  ((uint8_t)0x04)                 /*!< HCLK:150-168 MHz; MDC clock = HCLK/102 */
+
+/**@} end of group ETH_Macros */
+
+
+/** @addtogroup ETH_Structure Data Structure
+  @{
+*/
+
+/**
+ * @brief    ETH MAC Config structure types
+ */
+typedef struct
+{
+    /* MAC Configuration */
+    ETH_AUTONEGOTIATION_T           autoNegotiation;            /*!< Selects or not the AutoNegotiation mode for the external PHY
+                                                                    The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+                                                                    and the mode (half/full-duplex) */
+
+    ETH_WATCHDOG_T                  watchDog;                   /*!< Selects or not the Watchdog timer
+                                                                    When enabled, the MAC allows no more then 2048 bytes to be received.
+                                                                    When disabled, the MAC can receive up to 16384 bytes. */
+
+    ETH_JABBER_T                    jabber;                     /*!< Selects or not Jabber timer
+                                                                    When enabled, the MAC allows no more then 2048 bytes to be sent.
+                                                                    When disabled, the MAC can send up to 16384 bytes. */
+    ETH_INTERFRAMEGAP_T             interFrameGap;              /*!< Selects the minimum IFG between frames during transmission */
+
+    ETH_CARRIERSENCE_T              carrierSense;               /*!< Selects or not the Carrier Sense */
+
+    ETH_SPEED_T                     speed;                      /*!< Sets the Ethernet speed: 10/100 Mbps */
+
+    ETH_RECEIVEOWN_T                receiveOwn;                 /*!< Selects or not the ReceiveOwn
+                                                                    ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+                                                                    in Half-Duplex mode */
+
+    ETH_LOOPBACKMODE_T              loopbackMode;               /*!< Selects or not the internal MAC MII Loopback mode */
+
+    ETH_MODE_T                      mode;                       /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */
+
+    ETH_CHECKSUMOFFLAOD_T           checksumOffload;            /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. */
+
+    ETH_RETRYTRANSMISSION_T         retryTransmission;          /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
+                                                                    when a collision occurs (Half-Duplex mode) */
+
+    ETH_AUTOMATICPADCRCSTRIP_T      automaticPadCRCStrip;       /*!< Selects or not the Automatic MAC Pad/CRC Stripping */
+
+    ETH_BACKOFFLIMIT_T              backOffLimit;               /*!< Selects the BackOff limit value */
+
+    ETH_DEFFERRALCHECK_T            deferralCheck;              /*!< Selects or not the deferral check function (Half-Duplex mode) */
+
+    ETH_RECEIVEAll_T                receiveAll;                 /*!< Selects or not all frames reception by the MAC (No filtering) */
+
+    ETH_SOURCEADDRFILTER_T          sourceAddrFilter;           /*!< Selects the Source Address Filter mode */
+
+    ETH_PASSCONTROLFRAMES_T         passControlFrames;          /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) */
+
+    ETH_BROADCASTFRAMESRECEPTION_T  broadcastFramesReception;   /*!< Selects or not the reception of Broadcast Frames */
+
+    ETH_DESTINATIONADDRFILTER_T     destinationAddrFilter;      /*!< Sets the destination filter mode for both unicast and multicast frames */
+
+    ETH_PROMISCUOUS_MODE_T          promiscuousMode;            /*!< Selects or not the Promiscuous Mode */
+
+    ETH_MULTICASTFRAMESFILTER_T     multicastFramesFilter;      /*!< Selects the Multicast Frames filter mode */
+
+    ETH_UNICASTFRAMESFILTER_T       unicastFramesFilter;        /*!< Selects the Unicast Frames filter mode */
+
+
+    uint32_t                        hashTableHigh;              /*!< This field holds the higher 32 bits of Hash table. */
+
+    uint32_t                        hashTableLow;               /*!< This field holds the lower 32 bits of Hash table. */
+
+    uint32_t                        pauseTime;                  /*!< This field holds the (value<=0xFFFF) to be used in the Pause Time */
+
+    ETH_ZEROQUANTAPAUSE_T           zeroQuantaPause;            /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames */
+
+    ETH_PAUSELOWTHRESHOLD_T         pauseLowThreshold;          /*!< This field configures the threshold of the PAUSE to be checked for
+                                                                    automatic retransmission of PAUSE Frame */
+
+    ETH_UNICASTPAUSEFRAMEDETECT_T   unicastPauseFrameDetect;    /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
+                                                                    unicast address and unique multicast address) */
+
+    ETH_RECEIVEFLOWCONTROL_T        receiveFlowControl;         /*!< Enables or disables the MAC to decode the received Pause frame and
+                                                                    disable its transmitter for a specified time (Pause Time) */
+
+    ETH_TRANSMITFLOWCONTROL_T       transmitFlowControl;        /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+                                                                    or the MAC back-pressure operation (Half-Duplex mode) */
+
+    ETH_VLANTAGCOMPARISON_T         VLANTagComparison;          /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+                                                                    comparison and filtering */
+
+    uint32_t                        VLANTagIdentifier;          /*!< Holds the (value <=0xFFFF) VLAN tag identifier for receive frames */
+
+    /* DMA Configuration */
+    ETH_DROPTCPIPCHECKSUMERRORFRAME_T   dropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames */
+
+    ETH_RECEIVESTOREFORWARD_T           receiveStoreForward;         /*!< Enables or disables the Receive store and forward mode */
+
+    ETH_FLUSHRECEIVEDFRAME_T            flushReceivedFrame;          /*!< Enables or disables the flushing of received frames */
+
+    ETH_TRANSMITSTOREFORWARD_T          transmitStoreForward;        /*!< Enables or disables Transmit store and forward mode */
+
+    ETH_TRANSMITTHRESHOLDCONTROL_T      transmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control */
+
+    ETH_FORWARDERRORFRAMES_T            forwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames */
+
+    ETH_FORWARDUNDERSIZEDGOODFRAMES_T   forwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+                                                                        and length less than 64 bytes) including pad-bytes and CRC) */
+
+    ETH_RECEIVEDTHRESHOLDCONTROL_T      receiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO */
+
+    ETH_SECONDFRAMEOPERARTE_T           secondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
+                                                                        frame of Transmit data even before obtaining the status for the first frame. */
+
+    ETH_ADDRESSALIGNEDBEATS_T           addressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats */
+
+    ETH_FIXEDBURST_T                    fixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers */
+
+    ETH_RXDMABURSTLENGTH_T              rxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction */
+
+    ETH_TXDMABURSTLENGTH_T              txDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction */
+
+    uint32_t                            descriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) (value <= 0x1F) */
+
+    ETH_DMAARBITRATION_T                DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration */
+} ETH_Config_T;
+
+/**
+  * @brief  ETH DMA Descriptors data structure types
+  */
+typedef struct
+{
+    __IO uint32_t   Status;                            /*!< Status */
+    uint32_t        ControlBufferSize;                 /*!< Control and Buffer1, Buffer2 lengths */
+    uint32_t        Buffer1Addr;                       /*!< Buffer1 address pointer */
+    uint32_t        Buffer2NextDescAddr;               /*!< Buffer2 or next descriptor address pointer */
+    /* Enhanced ETHERNET DMA PTP Descriptors */
+} ETH_DMADescConfig_T;
+
+/**
+  * @brief  ETH DMA Descriptors data structure types
+  */
+typedef struct
+{
+    uint32_t        length;                 /*!< Data length */
+    uint32_t        buffer;                 /*!< Data buffer */
+    __IO ETH_DMADescConfig_T* descriptor;   /*!< DMA descriptor */
+} ETH_Frame_T;
+
+/**
+  * @brief  ETH DMA Descriptors Received Frame Informations structure types
+  */
+typedef struct
+{
+    __IO ETH_DMADescConfig_T*   FS_RxDesc;              /*!< First Segment Rx Desc */
+    __IO ETH_DMADescConfig_T*   LS_RxDesc;              /*!< Last Segment Rx Desc */
+    __IO uint32_t               segCount;               /*!< Segment count */
+} ETH_DMARxFrameInformations;
+
+/**@} end of group ETH_Structure*/
+
+/** @defgroup ETH_Functions
+  @{
+*/
+
+/* ETH Configuration */
+void ETH_Reset(void);
+void ETH_ConfigStructInit(ETH_Config_T* ethConfig);
+uint32_t ETH_Config(ETH_Config_T* ethConfig, uint16_t addr);
+void ETH_SoftwareReset(void);
+uint8_t ETH_ReadSoftwareReset(void);
+void ETH_Start(void);
+void ETH_Stop(void);
+uint32_t ETH_ReadRxPacketSize(ETH_DMADescConfig_T* DMARxDesc);
+
+/* PHY */
+uint16_t ETH_ReadPHYRegister(uint16_t addr, uint16_t reg);
+uint32_t ETH_WritePHYRegister(uint16_t addr, uint16_t reg, uint16_t data);
+uint32_t ETH_EnablePHYLoopBack(uint16_t addr);
+uint32_t ETH_DisablePHYLoopBack(uint16_t addr);
+
+/* MAC */
+void ETH_EnableMACTransmission(void);
+void ETH_DisableMACTransmission(void);
+void ETH_EnableMACReceiver(void);
+void ETH_DisableMACReceiver(void);
+uint8_t ETH_ReadFlowControlBusyStatus(void);
+void ETH_SetPauseControlFrame(void);
+void ETH_EnableBackPressureActivation(void);
+void ETH_DisableBackPressureActivation(void);
+uint8_t ETH_ReadMACFlagStatus(ETH_MAC_FLAG_T flag);
+void ETH_EnableMACInterrupt(uint32_t interrupt);
+void ETH_DisableMACInterrupt(uint32_t interrupt);
+void ETH_ConfigMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t* addr);
+void ETH_ReadMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t* addr);
+void ETH_EnableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr);
+void ETH_DisableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr);
+void ETH_ConfigMACAddressFilter(ETH_MAC_ADDRESS_T macAddr, ETH_MAC_ADDRESSFILTER_T filter);
+void ETH_ConfigMACAddressMaskBytesFilter(ETH_MAC_ADDRESS_T macAddr, uint32_t maskByte);
+
+/* DMA descriptors */
+void ETH_ConfigDMARxDescChain(ETH_DMADescConfig_T* DMARxDescTab, uint8_t* rxBuff, uint32_t rxBuffcount);
+void ETH_ConfigDMATxDescChain(ETH_DMADescConfig_T* DMATxDescTab, uint8_t* txBuff, uint32_t txBuffcount);
+uint32_t ETH_CheckReceivedFrame(void);
+uint32_t ETH_Transmit_Descriptors(u16 frameLength);
+ETH_Frame_T ETH_ReadReceivedFrame(void);
+uint8_t ETH_ReadDMATxDescFlagStatus(ETH_DMADescConfig_T* DMATxDesc, ETH_DMATXDESC_FLAG_T flag);
+uint32_t ETH_ReadDMATxDescCollisionCount(ETH_DMADescConfig_T* DMATxDesc);
+void ETH_ConfigDMATxDescOwnBit(ETH_DMADescConfig_T* DMATxDesc);
+void ETH_EnableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T* DMATxDesc);
+void ETH_DisableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T* DMATxDesc);
+void ETH_ConfigDMATxDescFrameSegment(ETH_DMADescConfig_T* DMATxDesc, ETH_DMATXDESC_SEGMENTS_T frameSegment);
+void ETH_ConfigDMATxDescChecksumInsertion(ETH_DMADescConfig_T* DMATxDesc, ETH_DMATXDESC_CHECKSUMB_T checksum);
+void ETH_EnableDMATxDescCRC(ETH_DMADescConfig_T* DMATxDesc);
+void ETH_DisableDMATxDescCRC(ETH_DMADescConfig_T* DMATxDesc);
+void ETH_EnableDMATxDescSecondAddressChained(ETH_DMADescConfig_T* DMATxDesc);
+void ETH_DisableDMATxDescSecondAddressChained(ETH_DMADescConfig_T* DMATxDesc);
+void ETH_EnableDMATxDescShortFramePadding(ETH_DMADescConfig_T* DMATxDesc);
+void ETH_DisableDMATxDescShortFramePadding(ETH_DMADescConfig_T* DMATxDesc);
+void ETH_ConfigDMATxDescBufferSize(ETH_DMADescConfig_T* DMATxDesc, uint32_t bufferSize1, uint32_t bufferSize2);
+uint8_t ETH_ReadDMARxDescFlagStatus(ETH_DMADescConfig_T* DMARxDesc, ETH_DMARXDESC_FLAG_T flag);
+
+void ETH_ConfigDMARxDescOwnBit(ETH_DMADescConfig_T* DMARxDesc);
+uint32_t ETH_ReadDMARxDescFrameLength(ETH_DMADescConfig_T* DMARxDesc);
+void ETH_EnableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T* DMARxDesc);
+void ETH_DisableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T* DMATxDesc);
+uint32_t ETH_ReadDMARxDescBufferSize(ETH_DMADescConfig_T* DMARxDesc, ETH_DMARXDESC_BUFFER_T buffer);
+ETH_Frame_T ETH_ReadReceivedFrameInterrupt(void);
+
+/* DMA */
+uint8_t ETH_ReadDMAFlagStatus(ETH_DMA_FLAG_T flag);
+void ETH_ClearDMAFlag(uint32_t flag);
+uint8_t ETH_ReadDMAIntFlag(ETH_DMA_INT_T flag);
+void ETH_ClearDMAIntFlag(uint32_t flag);
+uint32_t ETH_ReadTransmitProcessState(void);
+uint32_t ETH_ReadReceiveProcessState(void);
+void ETH_FlushTransmitFIFO(void);
+uint8_t ETH_ReadFlushTransmitFIFOStatus(void);
+void ETH_EnableDMATransmission(void);
+void ETH_DisableDMATransmission(void);
+void ETH_EnableDMAReceiver(void);
+void ETH_DisableDMAReceiver(void);
+void ETH_EnableDMAInterrupt(uint32_t interrupt);
+void ETH_DisableDMAInterrupt(uint32_t interrupt);
+uint8_t ETH_ReadDMAOverflowStatus(ETH_DMA_OVERFLOW_T overflow);
+uint32_t ETH_ReadRxOverflowMissedFrameCounter(void);
+uint32_t ETH_ReadBufferUnavailableMissedFrameCounter(void);
+uint32_t ETH_ReadCurrentTxDescStartAddress(void);
+uint32_t ETH_ReadCurrentRxDescStartAddress(void);
+uint32_t ETH_ReadCurrentTxBufferAddress(void);
+uint32_t ETH_ReadCurrentRxBufferAddress(void);
+void ETH_ResetDMATransmission(void);
+void ETH_ResetDMAReception(void);
+
+/* PMT */
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
+void ETH_EnableGlobalUnicastWakeUp(void);
+void ETH_DisableGlobalUnicastWakeUp(void);
+uint8_t ETH_ReadPMTFlagStatus(ETH_PMT_FLAG_T flag);
+void ETH_EnableWakeUpFrameDetection(void);
+void ETH_DisableWakeUpFrameDetection(void);
+void ETH_EnableMagicPacketDetection(void);
+void ETH_DisableMagicPacketDetection(void);
+void ETH_EnablePowerDown(void);
+void ETH_DisablePowerDown(void);
+
+/* MMC */
+void ETH_EnableMMCCounterFreeze(void);
+void ETH_DisableMMCCounterFreeze(void);
+void ETH_EnableMMCResetOnRead(void);
+void ETH_DisableMMCResetOnRead(void);
+void ETH_EnableMMCCounterRollover(void);
+void ETH_DisableMMCCounterRollover(void);
+void ETH_ResetMMCCounters(void);
+void ETH_EnableMMCInterrupt(uint32_t interrupt);
+void ETH_DisableMMCInterrupt(uint32_t interrupt);
+uint8_t ETH_ReadMMCIntFlag(uint32_t flag);
+uint32_t ETH_ReadMMCRegister(ETH_MMC_REG_T MMCReg);
+
+/**@} end of group ETH_Functions */
+/**@} end of group ETH_Driver */
+/**@} end of group APM32F10x_ETHDriver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APM32F10x_ETH_H */

project_0/libraries/APM32F10x_Library/APM32F10x_ETH_Driver/src/apm32f10x_eth.c

@@ -0,0 +1,2203 @@
+/*!
+ * @file        apm32f10x_eth.c
+ *
+ * @brief       This file provides all the ETH firmware functions
+ *
+ * @version     V1.0.3
+ *
+ * @date        2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2021-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+#if defined(APM32F10X_CL)
+
+#include "apm32f10x_eth.h"
+#include "apm32f10x_rcm.h"
+
+/** @addtogroup APM32F10x_ETHDriver
+  @{
+*/
+
+/** @defgroup ETH_Driver
+  * @brief ETH driver modules
+  @{
+*/
+
+#if defined   (__CC_ARM) /*!< ARM Compiler */
+    __align(4)
+    ETH_DMADescConfig_T  DMARxDscrTab[ETH_RXBUFNB]; /*!< Ethernet Rx MA Descriptor */
+    __align(4)
+    ETH_DMADescConfig_T  DMATxDscrTab[ETH_TXBUFNB]; /*!< Ethernet Tx DMA Descriptor */
+    __align(4)
+    uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE];  /*!< Ethernet Receive Buffer */
+    __align(4)
+    uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE];  /*!< Ethernet Transmit Buffer */
+
+#elif defined ( __ICCARM__ )
+
+    ETH_DMADescConfig_T  DMARxDscrTab[ETH_RXBUFNB]; /*!< Ethernet Rx MA Descriptor */
+    ETH_DMADescConfig_T  DMATxDscrTab[ETH_TXBUFNB]; /*!< Ethernet Tx DMA Descriptor */
+    uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE];  /*!< Ethernet Receive Buffer */
+    uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE];  /*!< Ethernet Transmit Buffer */
+
+#elif defined (__GNUC__) /*!< GNU Compiler */
+ETH_DMADescConfig_T  DMARxDscrTab[ETH_RXBUFNB] __attribute__ ((aligned (4))); /*!< Ethernet Rx MA Descriptor */
+ETH_DMADescConfig_T  DMATxDscrTab[ETH_TXBUFNB] __attribute__ ((aligned (4))); /*!< Ethernet Tx DMA Descriptor */
+uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__ ((aligned (4)));  /*!< Ethernet Receive Buffer */
+uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__ ((aligned (4)));  /*!< Ethernet Transmit Buffer */
+
+#endif
+
+/** @defgroup Global_Definition
+  @{
+*/
+
+/* Global pointers on Tx and Rx descriptor used to transmit and receive descriptors */
+__IO ETH_DMADescConfig_T*  DMATxDescToSet;
+__IO ETH_DMADescConfig_T*  DMARxDescToGet;
+
+/* Structure used to hold the last received packet descriptors info */
+ETH_DMARxFrameInformations      RxFrameDescriptor;
+__IO ETH_DMARxFrameInformations* DMARxFraminfos;
+__IO uint32_t FrameRxindex;
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Functions
+  @{
+*/
+
+/*!
+ * @brief  Inserts a delay time.
+ *
+ * @param  count: specifies the delay time length.
+ *
+ * @retval None
+ */
+static void ETH_Delay(__IO uint32_t count)
+{
+    __IO uint32_t i = 0;
+    for (i = count; i != 0; i--)
+    {
+    }
+}
+
+/* ETH Configuration */
+
+/*!
+ * @brief  Reset ETH peripheral registers to their default reset values.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_Reset(void)
+{
+    RCM_EnableAHBPeriphReset(RCM_AHB_PERIPH_ETH_MAC);
+
+    RCM_DisableAHBPeriphReset(RCM_AHB_PERIPH_ETH_MAC);
+}
+
+/*!
+ * @brief  Config ETH_Config_T member with its default value.
+ *
+ * @param  ethConfig: pointer to a ETH_Config_T structure which will be initialized.
+ *
+ * @retval None
+ */
+void ETH_ConfigStructInit(ETH_Config_T* ethConfig)
+{
+    /* MAC Configuration */
+    ethConfig->autoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
+    ethConfig->watchDog = ETH_WATCHDOG_ENABLE;
+    ethConfig->jabber = ETH_JABBER_ENABLE;
+    ethConfig->interFrameGap = ETH_INTERFRAMEGAP_96BIT;
+    ethConfig->carrierSense = ETH_CARRIERSENCE_ENABLE;
+    ethConfig->speed = ETH_SPEED_100M;
+    ethConfig->receiveOwn = ETH_RECEIVEOWN_ENABLE;
+    ethConfig->loopbackMode = ETH_LOOPBACKMODE_DISABLE;
+    ethConfig->mode = ETH_MODE_FULLDUPLEX;
+    ethConfig->checksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
+    ethConfig->retryTransmission = ETH_RETRYTRANSMISSION_ENABLE;
+    ethConfig->automaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
+    ethConfig->backOffLimit = ETH_BACKOFFLIMIT_10;
+    ethConfig->deferralCheck = ETH_DEFFERRALCHECK_DISABLE;
+    ethConfig->receiveAll = ETH_RECEIVEAll_DISABLE;
+    ethConfig->sourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
+    ethConfig->passControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
+    ethConfig->broadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_DISABLE;
+    ethConfig->destinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
+    ethConfig->promiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
+    ethConfig->multicastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
+    ethConfig->unicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
+    ethConfig->hashTableHigh = 0x0000;
+    ethConfig->hashTableLow = 0x0000;
+    ethConfig->pauseTime = 0x0000;
+    ethConfig->zeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
+    ethConfig->pauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
+    ethConfig->unicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
+    ethConfig->receiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
+    ethConfig->transmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
+    ethConfig->VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
+    ethConfig->VLANTagIdentifier = 0x0000;
+    /* DMA Configuration */
+    ethConfig->dropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE;
+    ethConfig->receiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
+    ethConfig->flushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
+    ethConfig->transmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
+    ethConfig->transmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
+    ethConfig->forwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
+    ethConfig->forwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
+    ethConfig->receiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
+    ethConfig->secondFrameOperate = ETH_SECONDFRAMEOPERARTE_DISABLE;
+    ethConfig->addressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
+    ethConfig->fixedBurst = ETH_FIXEDBURST_ENABLE;
+    ethConfig->rxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
+    ethConfig->txDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
+    ethConfig->descriptorSkipLength = 0x00;
+    ethConfig->DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
+}
+
+/*!
+ * @brief  Config the ETH peripheral parameters in the ethConfig.
+ *
+ * @param  ethConfig: pointer to a ETH_Config_T structure.
+ *
+ * @param  addr: external PHY address
+ *
+ * @retval ETH_ERROR: Ethernet initialization error
+ *         ETH_SUCCESS: Ethernet initialization success
+ */
+uint32_t ETH_Config(ETH_Config_T* ethConfig, uint16_t addr)
+{
+    uint32_t regValue = 0;
+    uint32_t hclk = 60000000;
+    __IO uint32_t timeout = 0, err = ETH_SUCCESS;
+
+    hclk = RCM_ReadHCLKFreq();
+
+    if ((hclk >= 20000000) && (hclk <= 35000000))
+    {
+        ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV16;
+    }
+    else if ((hclk >= 35000000) && (hclk < 60000000))
+    {
+        ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV26;
+    }
+    else if ((hclk >= 60000000) && (hclk < 100000000))
+    {
+        ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV42;
+    }
+    else if ((hclk >= 100000000) && (hclk < 150000000))
+    {
+        ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV62;
+    }
+    else
+    {
+        ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV102;
+    }
+
+    /* PHY initialization and configuration */
+    if (!(ETH_WritePHYRegister(addr, PHY_BCR, PHY_RESET)))
+    {
+        /* Return ERROR in case of write timeout */
+        err = ETH_ERROR;
+        goto error;
+    }
+
+    ETH_Delay(PHY_RESET_DELAY);
+
+    if (ethConfig->autoNegotiation == ETH_AUTONEGOTIATION_ENABLE)
+    {
+        /* Wait for linked status */
+        do
+        {
+            timeout++ ;
+        }
+        while (!(ETH_ReadPHYRegister(addr, PHY_BSR) & PHY_LINKED_STATUS) && (timeout < PHY_READ_TIMEOUT));
+
+        /* Return ERROR in case of timeout */
+        if (timeout == PHY_READ_TIMEOUT)
+        {
+            err = ETH_ERROR;
+            goto error;
+        }
+
+        timeout = 0;
+        /* Enable Auto-Negotiation */
+        if (!(ETH_WritePHYRegister(addr, PHY_BCR, PHY_AUTONEGOTIATION)))
+        {
+            /* Return ERROR in case of write timeout */
+            err = ETH_ERROR;
+        }
+
+        /* Wait until the auto-negotiation will be completed */
+        do
+        {
+            timeout++;
+        }
+        while (!(ETH_ReadPHYRegister(addr, PHY_BSR) & PHY_AUTONEGO_COMPLETE) && (timeout < (uint32_t)PHY_READ_TIMEOUT));
+
+        /* Return ERROR in case of timeout */
+        if (timeout == PHY_READ_TIMEOUT)
+        {
+            err = ETH_ERROR;
+            goto error;
+        }
+
+        timeout = 0;
+        /* Read the result of the auto-negotiation */
+        regValue = ETH_ReadPHYRegister(addr, PHY_SR);
+
+        if ((regValue & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
+        {
+            ethConfig->mode = ETH_MODE_FULLDUPLEX;
+        }
+        else
+        {
+            ethConfig->mode = ETH_MODE_HALFDUPLEX;
+        }
+        if (regValue & PHY_SPEED_STATUS)
+        {
+            ethConfig->speed = ETH_SPEED_10M;
+        }
+        else
+        {
+            ethConfig->speed = ETH_SPEED_100M;
+        }
+    }
+    else
+    {
+        if (!ETH_WritePHYRegister(addr, PHY_BCR, ((uint16_t)(ethConfig->speed << 8) |
+                                  (uint16_t)(ethConfig->mode  << 13))))
+        {
+            err = ETH_ERROR;
+        }
+
+        ETH_Delay(PHY_CONFIG_DELAY);
+    }
+error:
+    if (err == ETH_ERROR)
+    {
+        ethConfig->speed = ETH_SPEED_100M;
+        ethConfig->mode = ETH_MODE_FULLDUPLEX;
+    }
+
+    /* ETHERNET MAC_CFG Configuration */
+    ETH->CFG_B.WDTDIS = ethConfig->watchDog;
+    ETH->CFG_B.JDIS   = ethConfig->jabber;
+    ETH->CFG_B.IFG    = ethConfig->interFrameGap;
+    ETH->CFG_B.DISCRS = ethConfig->carrierSense;
+    ETH->CFG_B.SSEL   = ethConfig->speed;
+    ETH->CFG_B.DISRXO = ethConfig->receiveOwn;
+    ETH->CFG_B.LBM    = ethConfig->loopbackMode;
+    ETH->CFG_B.DM     = ethConfig->mode;
+    ETH->CFG_B.IPC    = ethConfig->checksumOffload;
+    ETH->CFG_B.DISR   = ethConfig->retryTransmission;
+    ETH->CFG_B.ACS    = ethConfig->automaticPadCRCStrip;
+    ETH->CFG_B.BL     = ethConfig->backOffLimit;
+    ETH->CFG_B.DC     = ethConfig->deferralCheck;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+
+    /* ETHERNET MAC_FRAF Configuration */
+    ETH->FRAF_B.RXA    = ethConfig->receiveAll;
+    ETH->FRAF         |= ethConfig->sourceAddrFilter;
+    ETH->FRAF_B.PCTRLF = ethConfig->passControlFrames;
+    ETH->FRAF_B.DISBF  = ethConfig->broadcastFramesReception;
+    ETH->FRAF_B.DAIF   = ethConfig->destinationAddrFilter;
+    ETH->FRAF_B.PR     = ethConfig->promiscuousMode;
+    ETH->FRAF         |= ethConfig->multicastFramesFilter;
+    ETH->FRAF         |= ethConfig->unicastFramesFilter;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+
+    /* ETHERNET MAC_HTH/HTL Configuration */
+    ETH->HTH = ethConfig->hashTableHigh;
+    ETH->HTL = ethConfig->hashTableLow;
+
+    /* ETHERNET MAC_FCTRL Configuration */
+    ETH->FCTRL_B.PT        = ethConfig->pauseTime;
+    ETH->FCTRL_B.ZQPDIS    = ethConfig->zeroQuantaPause;
+    ETH->FCTRL_B.PTSEL     = ethConfig->pauseLowThreshold;
+    ETH->FCTRL_B.UNPFDETE  = ethConfig->unicastPauseFrameDetect;
+    ETH->FCTRL_B.RXFCTRLEN = ethConfig->receiveFlowControl;
+    ETH->FCTRL_B.TXFCTRLEN = ethConfig->transmitFlowControl;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+
+    /* ETHERNET MAC_VLANT Configuration */
+    ETH->VLANT_B.VLANTCOMP = ethConfig->VLANTagComparison;
+    ETH->VLANT_B.VLANTID   = ethConfig->VLANTagIdentifier;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+
+    /* ETHERNET DMA_OPMOD Configuration */
+    ETH->DMAOPMOD_B.DISDT    = ethConfig->dropTCPIPChecksumErrorFrame;
+    ETH->DMAOPMOD_B.RXSF     = ethConfig->receiveStoreForward;
+    ETH->DMAOPMOD_B.DISFRXF  = ethConfig->flushReceivedFrame;
+    ETH->DMAOPMOD_B.TXSF     = ethConfig->transmitStoreForward;
+    ETH->DMAOPMOD_B.TXTHCTRL = ethConfig->transmitThresholdControl;
+    ETH->DMAOPMOD_B.FERRF    = ethConfig->forwardErrorFrames;
+    ETH->DMAOPMOD_B.FUF      = ethConfig->forwardUndersizedGoodFrames;
+    ETH->DMAOPMOD_B.RXTHCTRL = ethConfig->receiveThresholdControl;
+    ETH->DMAOPMOD_B.OSECF    = ethConfig->secondFrameOperate;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+
+    /* ETHERNET DMA_BMOD Configuration */
+    ETH->DMABMOD = RESET;
+    ETH->DMABMOD_B.AAL = ethConfig->addressAlignedBeats;
+    ETH->DMABMOD_B.FB = ethConfig->fixedBurst;
+    ETH->DMABMOD |= ethConfig->rxDMABurstLength;
+    ETH->DMABMOD |= ethConfig->txDMABurstLength;
+    ETH->DMABMOD_B.DSL = ethConfig->descriptorSkipLength;
+    ETH->DMABMOD |= ethConfig->DMAArbitration;
+    ETH->DMABMOD_B.USP = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+
+    if (err == ETH_SUCCESS)
+    {
+        return ETH_SUCCESS;
+    }
+    else
+    {
+        return ETH_ERROR;
+    }
+}
+
+/*!
+ * @brief  Resets all MAC subsystem internal registers and logic.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_SoftwareReset(void)
+{
+    ETH->DMABMOD_B.SWR = SET;
+}
+
+/*!
+ * @brief  Read the ETH software reset bit.
+ *
+ * @param  None
+ *
+ * @retval SET or RESET.
+ */
+uint8_t ETH_ReadSoftwareReset(void)
+{
+    return ETH->DMABMOD_B.SWR;
+}
+
+/*!
+ * @brief     Enables ETH MAC and DMA reception/transmission
+ *
+ * @param     None
+ *
+ * @retval    None
+ */
+void ETH_Start(void)
+{
+    ETH_EnableMACTransmission();
+    ETH_EnableMACReceiver();
+    ETH_FlushTransmitFIFO();
+    ETH_EnableDMATransmission();
+    ETH_EnableDMAReceiver();
+}
+
+/*!
+ * @brief     Disables ETH MAC and DMA reception/transmission
+ *
+ * @param     None
+ *
+ * @retval    None
+ */
+void ETH_Stop(void)
+{
+    ETH_DisableDMATransmission();
+    ETH_DisableDMAReceiver();
+    ETH_DisableMACReceiver();
+    ETH_FlushTransmitFIFO();
+    ETH_DisableMACTransmission();
+}
+
+/*!
+ * @brief  Read the size of the received packet.
+ *
+ * @param  None
+ *
+ * @retval frameLength: received packet size
+ */
+uint32_t ETH_ReadRxPacketSize(ETH_DMADescConfig_T* DMARxDesc)
+{
+    uint32_t frameLength = 0;
+    if (((DMARxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) &&
+            ((DMARxDesc->Status & ETH_DMARXDESC_ERRS)  == (uint32_t)RESET) &&
+            ((DMARxDesc->Status & ETH_DMARXDESC_LDES)  != (uint32_t)RESET))
+    {
+        frameLength =  ETH_ReadDMARxDescFrameLength(DMARxDesc);
+    }
+    return frameLength;
+}
+
+/* PHY functions */
+
+/*!
+ * @brief  Read a PHY register
+ *
+ * @param  addr: PHY device address
+ *               This parameter can be one of the following values: 0,..,31
+ *
+ * @param  reg:  PHY register
+ *               This parameter can be one of the following values:
+ *               @arg PHY_BCR : Transceiver Basic Control Register
+ *               @arg PHY_BSR : Transceiver Basic Status Register
+ *               @arg PHY_SR  :  Transceiver Status Register
+ *
+ * @retval ETH_ERROR: in case of timeout
+ *         MAC DATA register value: Data read from the selected PHY register
+ */
+uint16_t ETH_ReadPHYRegister(uint16_t addr, uint16_t reg)
+{
+    __IO uint32_t timeout = 0;
+
+    ETH->ADDR_B.PA = addr;
+    ETH->ADDR_B.MR = reg;
+    ETH->ADDR_B.MW = RESET;
+    ETH->ADDR_B.MB = SET;
+    /* Check for the Busy flag */
+    do
+    {
+        timeout++ ;
+    }
+    while ((ETH->ADDR_B.MB == SET) && (timeout < PHY_READ_TIMEOUT));
+    /* Return ERROR in case of timeout */
+    if (timeout == PHY_READ_TIMEOUT)
+    {
+        return ETH_ERROR;
+    }
+    /* Return data register value */
+    return (uint16_t)(ETH->DATA);
+}
+
+/*!
+ * @brief  Write to a PHY register
+ *
+ * @param  addr: PHY device address
+ *               This parameter can be one of the following values: 0,..,31
+
+ * @param  reg:  PHY register
+ *               This parameter can be one of the following values:
+ *               @arg PHY_BCR : Transceiver Basic Control Register
+
+ * @param  data: the data to write
+ *
+ * @retval ETH_ERROR: write timeout
+ *         ETH_SUCCESS: write success
+ */
+uint32_t ETH_WritePHYRegister(uint16_t addr, uint16_t reg, uint16_t data)
+{
+    __IO uint32_t timeout = 0;
+
+    ETH->DATA = data;
+    ETH->ADDR_B.PA = addr;
+    ETH->ADDR_B.MR = reg;
+    ETH->ADDR_B.MW = SET;
+    ETH->ADDR_B.MB = SET;
+
+    /* Check for the Busy flag */
+    do
+    {
+        timeout++ ;
+    }
+    while ((ETH->ADDR_B.MB == SET) && (timeout < PHY_WRITE_TIMEOUT));
+    /* Return ERROR in case of timeout */
+    if (timeout == PHY_WRITE_TIMEOUT)
+    {
+        return ETH_ERROR;
+    }
+    /* Return data register value */
+    return ETH_SUCCESS;
+}
+
+/*!
+ * @brief  Enable the PHY loopBack mode.
+ *
+ * @param  addr: PHY device address
+ *               This parameter can be one of the following values: 0,..,31
+ *
+ * @retval ETH_ERROR or ETH_SUCCESS
+ */
+uint32_t ETH_EnablePHYLoopBack(uint16_t addr)
+{
+    uint16_t temp = 0;
+
+    temp = ETH_ReadPHYRegister(addr, PHY_BCR);
+    temp |= PHY_LOOPBACK;
+
+    if (ETH_WritePHYRegister(addr, PHY_BCR, temp) == SET)
+    {
+        return ETH_SUCCESS;
+    }
+    else
+    {
+        return ETH_ERROR;
+    }
+}
+
+/*!
+ * @brief  Disable the PHY loopBack mode.
+ *
+ * @param  addr: PHY device address
+ *               This parameter can be one of the following values: 0,..,31
+ *
+ * @retval ETH_ERROR or ETH_SUCCESS
+ */
+uint32_t ETH_DisablePHYLoopBack(uint16_t addr)
+{
+    uint16_t temp = 0;
+
+    temp = ETH_ReadPHYRegister(addr, PHY_BCR);
+    temp &= ((uint16_t)~PHY_LOOPBACK);
+
+    if (ETH_WritePHYRegister(addr, PHY_BCR, temp) == SET)
+    {
+        return ETH_SUCCESS;
+    }
+    else
+    {
+        return ETH_ERROR;
+    }
+}
+
+/* MAC functions */
+
+/*!
+ * @brief  Enable the MAC transmission.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_EnableMACTransmission(void)
+{
+    ETH->CFG_B.TXEN = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Disable the MAC transmission.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_DisableMACTransmission(void)
+{
+    ETH->CFG_B.TXEN = RESET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Enable the MAC receiver.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_EnableMACReceiver(void)
+{
+    ETH->CFG_B.RXEN = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Disable the MAC receiver.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_DisableMACReceiver(void)
+{
+    ETH->CFG_B.RXEN = RESET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Read the ETH flow control busy status
+ *
+ * @param  None
+ *
+ * @retval SET or RESET
+ */
+uint8_t ETH_ReadFlowControlBusyStatus(void)
+{
+    return ETH->FCTRL_B.FCTRLB;
+}
+
+/*!
+ * @brief  Set a Pause Control Frame (Full-duplex only).
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_SetPauseControlFrame(void)
+{
+    ETH->FCTRL_B.FCTRLB = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Enable the MAC Back Pressure operation activation (Half-duplex only).
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_EnableBackPressureActivation(void)
+{
+    ETH->FCTRL_B.FCTRLB = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Disable the MAC Back Pressure operation activation (Half-duplex only).
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_DisableBackPressureActivation(void)
+{
+    ETH->FCTRL_B.FCTRLB = RESET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Read the specified ETH MAC flag
+ *
+ * @param  flag: Ethernet MAC flag:
+ *         This parameter can be one of the following values:
+ *           @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag
+ *           @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
+ *           @arg ETH_MAC_FLAG_MMCR : MMC receive flag
+ *           @arg ETH_MAC_FLAG_MMC  : MMC flag
+ *           @arg ETH_MAC_FLAG_PMT  : PMT flag
+ *
+ * @retval SET or RESET.
+ */
+uint8_t ETH_ReadMACFlagStatus(ETH_MAC_FLAG_T flag)
+{
+    return (ETH->ISTS & flag) ? SET : RESET;
+}
+
+/*!
+ * @brief  Enable the specified ETH MAC interrupts.
+ *
+ * @param  interrupt: Ethernet MAC interrupt flag:
+ *         This parameter can be any combination of the following values:
+ *           @arg ETH_MAC_INT_TST : Time stamp trigger interrupt
+ *           @arg ETH_MAC_INT_PMT : PMT interrupt
+ *
+ * @retval None
+ */
+void ETH_EnableMACInterrupt(uint32_t interrupt)
+{
+    ETH->IMASK |= interrupt;
+}
+
+/*!
+ * @brief  Disable the specified ETH MAC interrupts.
+ *
+ * @param  interrupt: Ethernet MAC interrupt flag:
+ *         This parameter can be any combination of the following values:
+ *           @arg ETH_MAC_INT_TST : Time stamp trigger interrupt
+ *           @arg ETH_MAC_INT_PMT : PMT interrupt
+ *
+ * @retval None
+ */
+void ETH_DisableMACInterrupt(uint32_t interrupt)
+{
+    ETH->IMASK &= (~(uint32_t)interrupt);
+}
+
+/*!
+ * @brief  Config the MAC address.
+ *
+ * @param  macAddr: The MAC address.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_MAC_ADDRESS0 : MAC Address0
+ *           @arg ETH_MAC_ADDRESS1 : MAC Address1
+ *           @arg ETH_MAC_ADDRESS2 : MAC Address2
+ *           @arg ETH_MAC_ADDRESS3 : MAC Address3
+ *
+ * @param  addr: Pointer on MAC address buffer data (6 bytes).
+ *
+ * @retval None
+ */
+void ETH_ConfigMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t* addr)
+{
+    uint32_t temp;
+
+    temp = ((uint32_t)addr[5] << 8) | (uint32_t)addr[4];
+    (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) = temp;
+
+    temp = ((uint32_t)addr[3] << 24) | ((uint32_t)addr[2] << 16) | ((uint32_t)addr[1] << 8) | addr[0];
+    (*(__IO uint32_t*)(ETH_MAC_ADDR_LBASE + macAddr)) = temp;
+}
+
+/*!
+ * @brief  Read the MAC address.
+ *
+ * @param  macAddr: The MAC address.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_MAC_ADDRESS0 : MAC Address0
+ *           @arg ETH_MAC_ADDRESS1 : MAC Address1
+ *           @arg ETH_MAC_ADDRESS2 : MAC Address2
+ *           @arg ETH_MAC_ADDRESS3 : MAC Address3
+ *
+ * @param  addr: Pointer on MAC address buffer data (6 bytes).
+ *
+ * @retval None
+ */
+void ETH_ReadMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t* addr)
+{
+    uint32_t temp;
+
+    temp = (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr));
+
+    addr[5] = ((temp >> 8) & 0xFF);
+    addr[4] = (temp & 0xFF);
+
+    temp = (*(__IO uint32_t*)(ETH_MAC_ADDR_LBASE + macAddr));
+    addr[3] = ((temp >> 24) & 0xFF);
+    addr[2] = ((temp >> 16) & 0xFF);
+    addr[1] = ((temp >> 8)  & 0xFF);
+    addr[0] = (temp & 0xFF);
+}
+
+/*!
+ * @brief  Enable address filters module uses the MAC address for perfect filtering.
+ *
+ * @param  macAddr: The MAC address.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_MAC_ADDRESS1 : MAC Address1
+ *           @arg ETH_MAC_ADDRESS2 : MAC Address2
+ *           @arg ETH_MAC_ADDRESS3 : MAC Address3
+ *
+ * @retval None
+ */
+void ETH_EnableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr)
+{
+    __IO uint32_t temp = 0;
+    (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) |= BIT31;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+    (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) = temp;
+}
+
+/*!
+ * @brief  Disable address filters module uses the MAC address for perfect filtering.
+ *
+ * @param  macAddr: The MAC address.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_MAC_ADDRESS1 : MAC Address1
+ *           @arg ETH_MAC_ADDRESS2 : MAC Address2
+ *           @arg ETH_MAC_ADDRESS3 : MAC Address3
+ *
+ * @retval None
+ */
+void ETH_DisableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr)
+{
+    __IO uint32_t temp = 0;
+    (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) &= (~BIT31);
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+    (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) = temp;
+}
+
+/*!
+ * @brief  Config the filter type for the MAC address
+ *
+ * @param  macAddr: The MAC address.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_MAC_ADDRESS1 : MAC Address1
+ *           @arg ETH_MAC_ADDRESS2 : MAC Address2
+ *           @arg ETH_MAC_ADDRESS3 : MAC Address3
+ *
+ * @param  filter: Comparison with the SA/DA fields of the received frame.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_MAC_ADDRESSFILTER_SA : MAC Address is used to compare with the
+ *                                           SA fields of the received frame.
+ *           @arg ETH_MAC_ADDRESSFILTER_DA : MAC Address is used to compare with the
+ *                                           DA fields of the received frame.
+ * @retval None
+ */
+void ETH_ConfigMACAddressFilter(ETH_MAC_ADDRESS_T macAddr, ETH_MAC_ADDRESSFILTER_T filter)
+{
+    if (filter == ETH_MAC_ADDRESSFILTER_SA)
+    {
+        (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) |= ETH_MAC_ADDRESSFILTER_SA;
+    }
+    else
+    {
+        (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) |= ETH_MAC_ADDRESSFILTER_DA;
+    }
+
+}
+
+/*!
+ * @brief  Config the filter type for the ETH MAC address.
+ *
+ * @param  macAddr: The MAC address.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_MAC_ADDRESS1 : MAC Address1
+ *           @arg ETH_MAC_ADDRESS2 : MAC Address2
+ *           @arg ETH_MAC_ADDRESS3 : MAC Address3
+ *
+ * @param  MaskByte: specifies the used address bytes for comparison
+ *         This parameter can be any combination of the following values:
+ *           @arg ETH_MAC_ADDRESSMASK_BYTE6 : Mask MAC Address high reg bits [15:8].
+ *           @arg ETH_MAC_ADDRESSMASK_BYTE5 : Mask MAC Address high reg bits [7:0].
+ *           @arg ETH_MAC_ADDRESSMASK_BYTE4 : Mask MAC Address low reg bits [31:24].
+ *           @arg ETH_MAC_ADDRESSMASK_BYTE3 : Mask MAC Address low reg bits [23:16].
+ *           @arg ETH_MAC_ADDRESSMASK_BYTE2 : Mask MAC Address low reg bits [15:8].
+ *           @arg ETH_MAC_ADDRESSMASK_BYTE1 : Mask MAC Address low reg bits [7:0].
+ *
+ * @retval None
+ */
+void ETH_ConfigMACAddressMaskBytesFilter(ETH_MAC_ADDRESS_T macAddr, uint32_t maskByte)
+{
+    __IO uint32_t temp = 0;
+
+    (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) &= (~(uint32_t)0x3F000000);
+
+    temp = (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr));
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+    (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) = temp;
+
+    /* Set the selected Filter mask bytes */
+    (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) |= maskByte;
+
+    temp = (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr));
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+    (*(__IO uint32_t*)(ETH_MAC_ADDR_HBASE + macAddr)) = temp;
+}
+
+/* DMA Descriptors functions */
+
+/*!
+ * @brief  Config the DMA Rx descriptors in chain mode.
+ *
+ * @param  DMARxDescTab: Pointer on the first Rx desc list
+ *
+ * @param  rxBuff: Pointer on the first RxBuffer list
+ *
+ * @param  rxBuffcount: Number of the used Rx desc in the list
+ *
+ * @retval None
+ */
+void ETH_ConfigDMARxDescChain(ETH_DMADescConfig_T* DMARxDescTab, uint8_t* rxBuff, uint32_t rxBuffcount)
+{
+    uint32_t i = 0;
+    ETH_DMADescConfig_T* DMARxDesc;
+    DMARxDescToGet = DMARxDescTab;
+
+    for (i = 0; i < rxBuffcount; i++)
+    {
+        DMARxDesc = DMARxDescTab + i;
+        DMARxDesc->Status = ETH_DMARXDESC_OWN;
+        DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RXCH | ETH_RX_BUF_SIZE;
+        DMARxDesc->Buffer1Addr = (uint32_t)(&rxBuff[i * ETH_RX_BUF_SIZE]);
+        if (i < (rxBuffcount - 1))
+        {
+            DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1);
+        }
+        else
+        {
+            DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
+        }
+    }
+
+
+    ETH->DMARXDLADDR = (uint32_t) DMARxDescTab;
+    DMARxFraminfos = &RxFrameDescriptor;
+}
+
+/*!
+ * @brief  Initializes the DMA Tx descriptors in chain mode.
+ *
+ * @param  DMATxDescTab: Pointer on the first Tx desc list
+ *
+ * @param  txBuff: Pointer on the first TxBuffer list
+ *
+ * @param  txBuffcount: Number of the used Tx desc in the list
+ *
+ * @retval None
+  */
+void ETH_ConfigDMATxDescChain(ETH_DMADescConfig_T* DMATxDescTab, uint8_t* txBuff, uint32_t txBuffcount)
+{
+    uint32_t i = 0;
+    ETH_DMADescConfig_T* DMATxDesc;
+    DMATxDescToSet = DMATxDescTab;
+
+    for (i = 0; i < txBuffcount; i++)
+    {
+        DMATxDesc = DMATxDescTab + i;
+        DMATxDesc->Status = ETH_DMATXDESC_TXCH;
+        DMATxDesc->Buffer1Addr = (uint32_t)(&txBuff[i * ETH_TX_BUF_SIZE]);
+        if (i < (txBuffcount - 1))
+        {
+            DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1);
+        }
+        else
+        {
+            DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab);
+        }
+    }
+
+    ETH->DMATXDLADDR = (uint32_t) DMATxDescTab;
+}
+
+/*!
+ * @brief  This function polls for a frame receiver
+ *
+ * @param  None
+ *
+ * @retval Returns 1 when a frame is received, 0 if none.
+ */
+uint32_t ETH_CheckReceivedFrame(void)
+{
+    if (((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) &&
+            ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET))
+    {
+        DMARxFraminfos->segCount++;
+        if (DMARxFraminfos->segCount == 1)
+        {
+            DMARxFraminfos->FS_RxDesc = DMARxDescToGet;
+        }
+        DMARxFraminfos->LS_RxDesc = DMARxDescToGet;
+        return 1;
+    }
+    else if (((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) &&
+             ((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET) &&
+             ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET))
+    {
+        DMARxFraminfos->FS_RxDesc = DMARxDescToGet;
+        DMARxFraminfos->LS_RxDesc = NULL;
+        DMARxFraminfos->segCount  = 1;
+        DMARxDescToGet = (ETH_DMADescConfig_T*)(DMARxDescToGet->Buffer2NextDescAddr);
+    }
+    else if (((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) &&
+             ((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) == (uint32_t)RESET) &&
+             ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET))
+    {
+        (DMARxFraminfos->segCount) ++;
+        DMARxDescToGet = (ETH_DMADescConfig_T*)(DMARxDescToGet->Buffer2NextDescAddr);
+    }
+    return 0;
+}
+
+/*!
+ * @brief  Prepares DMA Tx descriptors to transmit an ethernet frame
+ *
+ * @param  FrameLength : length of the frame to send
+ *
+ * @retval ETH_ERROR or ETH_SUCCESS
+ */
+uint32_t ETH_Transmit_Descriptors(u16 frameLength)
+{
+    uint32_t count = 0, size = 0, i = 0;
+    __IO ETH_DMADescConfig_T*  DMATxDesc;
+
+    if ((DMATxDescToSet->Status & ETH_DMATXDESC_OWN) == SET)
+    {
+        return ETH_ERROR;
+    }
+
+    DMATxDesc = DMATxDescToSet;
+
+    if (frameLength > ETH_TX_BUF_SIZE)
+    {
+        count = frameLength / ETH_TX_BUF_SIZE;
+        if (frameLength % ETH_TX_BUF_SIZE) count++;
+    }
+    else count = 1;
+
+    if (count == 1)
+    {
+        DMATxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;
+        DMATxDesc->ControlBufferSize = (frameLength & ETH_DMATXDESC_TXBS1);
+        DMATxDesc->Status |= ETH_DMATXDESC_OWN;
+        DMATxDesc = (ETH_DMADescConfig_T*)(DMATxDesc->Buffer2NextDescAddr);
+    }
+    else
+    {
+        for (i = 0; i < count; i++)
+        {
+            DMATxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
+
+            if (i == 0)
+            {
+                DMATxDesc->Status |= ETH_DMATXDESC_FS;
+            }
+            DMATxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TXBS1);
+
+            if (i == (count - 1))
+            {
+                DMATxDesc->Status |= ETH_DMATXDESC_LS;
+                size = frameLength - (count - 1) * ETH_TX_BUF_SIZE;
+                DMATxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TXBS1);
+            }
+
+            DMATxDesc->Status |= ETH_DMATXDESC_OWN;
+            DMATxDesc = (ETH_DMADescConfig_T*)(DMATxDesc->Buffer2NextDescAddr);
+        }
+    }
+    DMATxDescToSet = DMATxDesc;
+
+    if (ETH->DMASTS_B.TXBU == SET)
+    {
+        ETH->DMASTS = BIT2;
+        ETH->DMATXPD = 0;
+    }
+
+    return ETH_SUCCESS;
+}
+
+/*!
+ * @brief  Read the received frame.
+ *
+ * @param  none
+ *
+ * @retval Structure of type ETH_Frame_T
+ */
+ETH_Frame_T ETH_ReadReceivedFrame(void)
+{
+    uint32_t frameLength = 0;
+    ETH_Frame_T frame = {0, 0, 0};
+
+    frameLength = ((DMARxDescToGet->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
+    frame.length = frameLength;
+
+    frame.descriptor = DMARxFraminfos->FS_RxDesc;
+    frame.buffer = (DMARxFraminfos->FS_RxDesc)->Buffer1Addr;
+    DMARxDescToGet = (ETH_DMADescConfig_T*)(DMARxDescToGet->Buffer2NextDescAddr);
+
+    return (frame);
+}
+
+/*!
+ * @brief  Read ETH DMA Tx Descriptor flag.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @param  flag: Specifies the flag to check.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_DMATXDESC_OWN   : Descriptor is owned by DMA engine
+ *           @arg ETH_DMATXDESC_INTC  : Interrupt on completion
+ *           @arg ETH_DMATXDESC_LS    : Last Segment
+ *           @arg ETH_DMATXDESC_FS    : First Segment
+ *           @arg ETH_DMATXDESC_DISC  : Disable CRC
+ *           @arg ETH_DMATXDESC_DISP  : Disable Pad
+ *           @arg ETH_DMATXDESC_TXTSEN: Transmit Time Stamp Enable
+ *           @arg ETH_DMATXDESC_TXENDR: Transmit End of Ring
+ *           @arg ETH_DMATXDESC_TXCH  : Second Address Chained
+ *           @arg ETH_DMATXDESC_TXTSS : Tx Time Stamp Status
+ *           @arg ETH_DMATXDESC_IHERR : IP Header Error
+ *           @arg ETH_DMATXDESC_ERRS  : Error summary
+ *           @arg ETH_DMATXDESC_JTO   : Jabber Timeout
+ *           @arg ETH_DMATXDESC_FF    : Frame Flushed: DMA/MTL flushed the frame due to SW flush
+ *           @arg ETH_DMATXDESC_IPERR : Payload Checksum Error
+ *           @arg ETH_DMATXDESC_LSC   : Loss of Carrier: carrier lost during transmission
+ *           @arg ETH_DMATXDESC_NC    : No Carrier: no carrier signal from the transceiver
+ *           @arg ETH_DMATXDESC_LC    : Late Collision: transmission aborted due to collision
+ *           @arg ETH_DMATXDESC_EC    : Excessive Collision: transmission aborted after 16 collisions
+ *           @arg ETH_DMATXDESC_VLANF : VLAN Frame
+ *           @arg ETH_DMATXDESC_CCNT  : Collision Count
+ *           @arg ETH_DMATXDESC_EDEF  : Excessive Deferral
+ *           @arg ETH_DMATXDESC_UFERR : Underflow Error: late data arrival from the memory
+ *           @arg ETH_DMATXDESC_DEF   : Deferred Bit
+ *
+ * @retval SET or RESET.
+ */
+uint8_t ETH_ReadDMATxDescFlagStatus(ETH_DMADescConfig_T* DMATxDesc, ETH_DMATXDESC_FLAG_T flag)
+{
+    return (DMATxDesc->Status & flag) ? SET : RESET;
+}
+
+/*!
+ * @brief  Returns ETH DMA Tx Descriptor collision count.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @retval The Transmit descriptor collision counter value.
+ */
+uint32_t ETH_ReadDMATxDescCollisionCount(ETH_DMADescConfig_T* DMATxDesc)
+{
+    return ((DMATxDesc->Status & ETH_DMATXDESC_CCNT) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT);
+}
+
+/*!
+ * @brief  Config the ETH DMA Tx Descriptor Own bit.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @retval None
+ */
+void ETH_ConfigDMATxDescOwnBit(ETH_DMADescConfig_T* DMATxDesc)
+{
+    DMATxDesc->Status |= ETH_DMATXDESC_OWN;
+}
+
+/*!
+ * @brief  Enable the ETH DMA Tx Descriptor Transmit interrupt.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @retval None
+ */
+void ETH_EnableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T* DMATxDesc)
+{
+    DMATxDesc->Status |= ETH_DMATXDESC_INTC;
+}
+
+/*!
+ * @brief  Disable the ETH DMA Tx Descriptor Transmit interrupt.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @retval None
+ */
+void ETH_DisableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T* DMATxDesc)
+{
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_INTC);
+}
+
+/*!
+ * @brief  Config Tx descriptor as last or first segment
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @param  frameSegment: Tx desc contain last or first segment.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_DMATXDESC_LASTSEGMENTS : Actual Tx desc contain last segment
+ *           @arg ETH_DMATXDESC_FIRSTSEGMENT : Actual Tx desc contain first segment
+ *
+ * @retval None
+ */
+void ETH_ConfigDMATxDescFrameSegment(ETH_DMADescConfig_T* DMATxDesc, ETH_DMATXDESC_SEGMENTS_T frameSegment)
+{
+    DMATxDesc->Status |= frameSegment;
+}
+/*!
+ * @brief  Config ETH DMA Tx Desc Checksum Insertion.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @param  checksum: specifies is the DMA Tx desc checksum insertion.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_DMATXDESC_CHECKSUMBYPASS              : Checksum bypass
+ *           @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER          : IPv4 header checksum
+ *           @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT   : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
+ *           @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL      : TCP/UDP/ICMP checksum fully in hardware including pseudo header
+ *
+ * @retval None
+ */
+void ETH_ConfigDMATxDescChecksumInsertion(ETH_DMADescConfig_T* DMATxDesc, ETH_DMATXDESC_CHECKSUMB_T checksum)
+{
+    DMATxDesc->Status |= checksum;
+}
+
+/*!
+ * @brief  Enable the DMA Tx Desc CRC.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @retval None
+ */
+void ETH_EnableDMATxDescCRC(ETH_DMADescConfig_T* DMATxDesc)
+{
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_DISC);
+}
+
+/*!
+ * @brief  Disable the DMA Tx Desc CRC.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @retval None
+ */
+void ETH_DisableDMATxDescCRC(ETH_DMADescConfig_T* DMATxDesc)
+{
+    DMATxDesc->Status |= ETH_DMATXDESC_DISC;
+}
+
+/*!
+ * @brief  Enable the DMA Tx Desc second address chained.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @retval None
+ */
+void ETH_EnableDMATxDescSecondAddressChained(ETH_DMADescConfig_T* DMATxDesc)
+{
+    DMATxDesc->Status |= ETH_DMATXDESC_TXCH;
+}
+
+/*!
+ * @brief  Disable the DMA Tx Desc second address chained.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @retval None
+ */
+void ETH_DisableDMATxDescSecondAddressChained(ETH_DMADescConfig_T* DMATxDesc)
+{
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_TXCH);
+}
+
+/*!
+ * @brief  Enable the DMA Tx Desc padding for frame shorter than 64 bytes.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @retval None
+ */
+void ETH_EnableDMATxDescShortFramePadding(ETH_DMADescConfig_T* DMATxDesc)
+{
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_DISP);
+}
+
+/*!
+ * @brief  Disable the DMA Tx Desc padding for frame shorter than 64 bytes.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @retval None
+ */
+void ETH_DisableDMATxDescShortFramePadding(ETH_DMADescConfig_T* DMATxDesc)
+{
+    DMATxDesc->Status |= ETH_DMATXDESC_DISP;
+}
+
+/*!
+ * @brief  Config the ETH DMA Tx Desc buffer1 and buffer2 sizes.
+ *
+ * @param  DMATxDesc: pointer on a DMA Tx descriptor
+ *
+ * @param  bufferSize1: specifies the Tx desc buffer1 size.
+ *
+ * @param  bufferSize2: specifies the Tx desc buffer2 size.
+ *
+ * @retval None
+ */
+void ETH_ConfigDMATxDescBufferSize(ETH_DMADescConfig_T* DMATxDesc, uint32_t bufferSize1, uint32_t bufferSize2)
+{
+    DMATxDesc->ControlBufferSize |= (bufferSize1 | (bufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT));
+}
+
+/*!
+ * @brief  Checks whether the specified ETHERNET Rx Desc flag is set or not.
+ *
+ * @param  DMARxDesc: pointer on a DMA Rx descriptor
+
+ * @param  flag: specifies the flag to check.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_DMARXDESC_OWN    :    Descriptor is owned by DMA engine
+ *           @arg ETH_DMARXDESC_ADDRF  :    DA Filter Fail for the rx frame
+ *           @arg ETH_DMARXDESC_ERRS   :    Error summary
+ *           @arg ETH_DMARXDESC_DESERR :    Descriptor error: no more descriptors for receive frame
+ *           @arg ETH_DMARXDESC_SADDRF :    SA Filter Fail for the received frame
+ *           @arg ETH_DMARXDESC_LERR   :    Frame size not matching with length field
+ *           @arg ETH_DMARXDESC_OFERR  :    Overflow Error: Frame was damaged due to buffer overflow
+ *           @arg ETH_DMARXDESC_VLANF  :    VLAN Tag: received frame is a VLAN frame
+ *           @arg ETH_DMARXDESC_FDES   :    First descriptor of the frame
+ *           @arg ETH_DMARXDESC_LDES   :    Last descriptor of the frame
+ *           @arg ETH_DMARXDESC_IPV4HCE:    IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error
+ *           @arg ETH_DMARXDESC_LC     :    Late collision occurred during reception
+ *           @arg ETH_DMARXDESC_FT     :    Frame type - Ethernet, otherwise 802.3
+ *           @arg ETH_DMARXDESC_RXWDTTO:    Receive Watchdog Timeout: watchdog timer expired during reception
+ *           @arg ETH_DMARXDESC_RERR   :    Receive error: error reported by MII interface
+ *           @arg ETH_DMARXDESC_DERR   :    Dribble bit error: frame contains non int multiple of 8 bits
+ *           @arg ETH_DMARXDESC_CERR   :    CRC error
+ *           @arg ETH_DMARXDESC_MAMPCE :    Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
+ *
+ * @retval SET or RESET.
+ */
+uint8_t ETH_ReadDMARxDescFlagStatus(ETH_DMADescConfig_T* DMARxDesc, ETH_DMARXDESC_FLAG_T flag)
+{
+    return (DMARxDesc->Status & flag) ? SET : RESET;
+}
+
+/*!
+ * @brief  Config the ETH DMA Rx Desc Own bit.
+ *
+ * @param  DMARxDesc: pointer on a DMA Rx descriptor
+ *
+ * @retval None
+ */
+void ETH_ConfigDMARxDescOwnBit(ETH_DMADescConfig_T* DMARxDesc)
+{
+    DMARxDesc->Status |= ETH_DMARXDESC_OWN;
+}
+
+/*!
+ * @brief  Returns the ETH DMA Rx descriptor frame length.
+ *
+ * @param  DMARxDesc: pointer on a DMA Rx descriptor
+ *
+ * @retval The Rx descriptor received frame length.
+ */
+uint32_t ETH_ReadDMARxDescFrameLength(ETH_DMADescConfig_T* DMARxDesc)
+{
+    return ((DMARxDesc->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT);
+}
+
+/*!
+ * @brief  Enable the ETH DMA Rx Desc receive interrupt.
+ *
+ * @param  DMARxDesc: pointer on a DMA Rx descriptor
+ *
+ * @retval None
+ */
+void ETH_EnableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T* DMARxDesc)
+{
+    DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARXDESC_DINTC);
+}
+
+/*!
+ * @brief  Disable the ETH DMA Rx Desc receive interrupt.
+ *
+ * @param  DMARxDesc: pointer on a DMA Rx descriptor
+ *
+ * @retval None
+ */
+void ETH_DisableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T* DMARxDesc)
+{
+    DMARxDesc->ControlBufferSize |= ETH_DMARXDESC_DINTC;
+}
+
+/*!
+ * @brief  Returns the ETH DMA Rx Desc buffer size.
+ *
+ * @param  DMARxDesc: pointer on a DMA Rx descriptor
+ *
+ * @param  buffer: specifies the DMA Rx Desc buffer.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
+ *           @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2
+ *
+ * @retval The Receive descriptor frame length.
+ */
+uint32_t ETH_ReadDMARxDescBufferSize(ETH_DMADescConfig_T* DMARxDesc, ETH_DMARXDESC_BUFFER_T buffer)
+{
+    if (buffer == ETH_DMARXDESC_BUFFER1)
+    {
+        return (DMARxDesc->ControlBufferSize & ETH_DMARXDESC_RXBS1);
+    }
+    else
+    {
+        return ((DMARxDesc->ControlBufferSize & ETH_DMARXDESC_RXBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT);
+    }
+}
+
+/*!
+ * @brief  Read frame using DMA Receive interrupt.
+ *         it allows scanning of Rx descriptors to get the the receive frame
+ *
+ * @param  None
+ *
+ * @retval Structure of type ETH_Frame_T
+ */
+ETH_Frame_T ETH_ReadReceivedFrameInterrupt(void)
+{
+    __IO uint32_t count = 0;
+    ETH_Frame_T frame = {0, 0, 0};
+
+    while (((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (count < ETH_RXBUFNB))
+    {
+        count ++;
+
+        if (((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET) &&
+                ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET))
+        {
+            DMARxFraminfos->FS_RxDesc = DMARxDescToGet;
+            DMARxFraminfos->segCount = 1;
+            DMARxDescToGet = (ETH_DMADescConfig_T*)(DMARxDescToGet->Buffer2NextDescAddr);
+        }
+        else if (((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) == (uint32_t)RESET) &&
+                 ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET))
+        {
+            (DMARxFraminfos->segCount) ++;
+            DMARxDescToGet = (ETH_DMADescConfig_T*)(DMARxDescToGet->Buffer2NextDescAddr);
+        }
+        else
+        {
+            DMARxFraminfos->LS_RxDesc = DMARxDescToGet;
+            (DMARxFraminfos->segCount)++;
+
+            if ((DMARxFraminfos->segCount) == 1)
+                DMARxFraminfos->FS_RxDesc = DMARxDescToGet;
+
+            frame.length = ((DMARxDescToGet->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
+
+            if (DMARxFraminfos->segCount > 1)
+            {
+                frame.buffer = (DMARxFraminfos->FS_RxDesc)->Buffer1Addr;
+            }
+            else
+            {
+                frame.buffer = DMARxDescToGet->Buffer1Addr;
+            }
+
+            frame.descriptor = DMARxFraminfos->FS_RxDesc;
+            DMARxDescToGet = (ETH_DMADescConfig_T*)(DMARxDescToGet->Buffer2NextDescAddr);
+
+            return (frame);
+        }
+    }
+    return (frame);
+}
+
+/* DMA functions */
+
+/*!
+ * @brief  Read the ETH DMA flag.
+ *
+ * @param  flag: specifies the flag to check.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_DMA_FLAG_TST                  : Time-stamp trigger flag
+ *           @arg ETH_DMA_FLAG_PMT                  : PMT flag
+ *           @arg ETH_DMA_FLAG_MMC                  : MMC flag
+ *           @arg ETH_DMA_FLAG_DATATRANSFERERROR    : Error bits 0-data buffer, 1-desc. access
+ *           @arg ETH_DMA_FLAG_READWRITEERROR       : Error bits 0-write trnsf, 1-read transfr
+ *           @arg ETH_DMA_FLAG_ACCESSERROR          : Error bits 0-Rx DMA, 1-Tx DMA
+ *           @arg ETH_DMA_FLAG_NIS                  : Normal interrupt summary flag
+ *           @arg ETH_DMA_FLAG_AIS                  : Abnormal interrupt summary flag
+ *           @arg ETH_DMA_FLAG_ER                   : Early receive flag
+ *           @arg ETH_DMA_FLAG_FBE                  : Fatal bus error flag
+ *           @arg ETH_DMA_FLAG_ET                   : Early transmit flag
+ *           @arg ETH_DMA_FLAG_RWT                  : Receive watchdog timeout flag
+ *           @arg ETH_DMA_FLAG_RPS                  : Receive process stopped flag
+ *           @arg ETH_DMA_FLAG_RBU                  : Receive buffer unavailable flag
+ *           @arg ETH_DMA_FLAG_RX                   : Receive flag
+ *           @arg ETH_DMA_FLAG_TU                   : Underflow flag
+ *           @arg ETH_DMA_FLAG_RO                   : Overflow flag
+ *           @arg ETH_DMA_FLAG_TJT                  : Transmit jabber timeout flag
+ *           @arg ETH_DMA_FLAG_TBU                  : Transmit buffer unavailable flag
+ *           @arg ETH_DMA_FLAG_TPS                  : Transmit process stopped flag
+ *           @arg ETH_DMA_FLAG_TX                   : Transmit flag
+ *
+ * @retval SET or RESET.
+ */
+uint8_t ETH_ReadDMAFlagStatus(ETH_DMA_FLAG_T flag)
+{
+    return (ETH->DMASTS & flag) ? SET : RESET;
+}
+
+/*!
+ * @brief  Clears the ETH DMA flag.
+ *
+ * @param  flag: specifies the flag to clear.
+ *         This parameter can be any combination of the following values:
+ *           @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
+ *           @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
+ *           @arg ETH_DMA_FLAG_ER  : Early receive flag
+ *           @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
+ *           @arg ETH_DMA_FLAG_ET  : Early transmit flag
+ *           @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
+ *           @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
+ *           @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
+ *           @arg ETH_DMA_FLAG_RX  : Receive flag
+ *           @arg ETH_DMA_FLAG_TU  : Transmit Underflow flag
+ *           @arg ETH_DMA_FLAG_RO  : Receive Overflow flag
+ *           @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
+ *           @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
+ *           @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
+ *           @arg ETH_DMA_FLAG_TX  : Transmit flag
+ *
+ * @retval None
+ */
+void ETH_ClearDMAFlag(uint32_t flag)
+{
+    ETH->DMASTS = flag;
+}
+
+/*!
+ * @brief  Read the ETH DMA interrupt flag.
+ *
+ * @param  flag: specifies the interrupt source to check.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_DMA_INT_TST : Time-stamp trigger interrupt
+ *           @arg ETH_DMA_INT_PMT : PMT interrupt
+ *           @arg ETH_DMA_INT_MMC : MMC interrupt
+ *           @arg ETH_DMA_INT_NIS : Normal interrupt summary
+ *           @arg ETH_DMA_INT_AIS : Abnormal interrupt summary
+ *           @arg ETH_DMA_INT_ER  : Early receive interrupt
+ *           @arg ETH_DMA_INT_FBE : Fatal bus error interrupt
+ *           @arg ETH_DMA_INT_ET  : Early transmit interrupt
+ *           @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt
+ *           @arg ETH_DMA_INT_RPS : Receive process stopped interrupt
+ *           @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt
+ *           @arg ETH_DMA_INT_RX  : Receive interrupt
+ *           @arg ETH_DMA_INT_TU  : Underflow interrupt
+ *           @arg ETH_DMA_INT_RO  : Overflow interrupt
+ *           @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt
+ *           @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt
+ *           @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt
+ *           @arg ETH_DMA_INT_TX  : Transmit interrupt
+ *
+ * @retval SET or RESET.
+ */
+uint8_t ETH_ReadDMAIntFlag(ETH_DMA_INT_T flag)
+{
+    return (ETH->DMASTS & flag) ? SET : RESET;
+}
+
+/*!
+ * @brief  Clears the ETH DMA interrupt flag.
+ *
+ * @param  flag: specifies the interrupt flag to clear.
+ *         This parameter can be any combination of the following values:
+ *           @arg ETH_DMA_INT_NIS : Normal interrupt summary
+ *           @arg ETH_DMA_INT_AIS : Abnormal interrupt summary
+ *           @arg ETH_DMA_INT_ER  : Early receive interrupt
+ *           @arg ETH_DMA_INT_FBE : Fatal bus error interrupt
+ *           @arg ETH_DMA_INT_ET  : Early transmit interrupt
+ *           @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt
+ *           @arg ETH_DMA_INT_RPS : Receive process stopped interrupt
+ *           @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt
+ *           @arg ETH_DMA_INT_RX  : Receive interrupt
+ *           @arg ETH_DMA_INT_TU  : Transmit Underflow interrupt
+ *           @arg ETH_DMA_INT_RO  : Receive Overflow interrupt
+ *           @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt
+ *           @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt
+ *           @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt
+ *           @arg ETH_DMA_INT_TX  : Transmit interrupt
+ *
+ * @retval None
+ */
+void ETH_ClearDMAIntFlag(uint32_t flag)
+{
+    ETH->DMASTS = flag;
+}
+
+/*!
+ * @brief  Returns the ETH DMA Transmit Process State.
+ *
+ * @param  None
+
+ * @retval The new ETH DMA Transmit Process State:
+ *         This can be one of the following values:
+ *           - ETH_DMA_TRANSMITPROCESS_STOPPED   : Stopped - Reset or Stop Tx Command issued
+ *           - ETH_DMA_TRANSMITPROCESS_FETCHING  : Running - fetching the Tx descriptor
+ *           - ETH_DMA_TRANSMITPROCESS_WAITING   : Running - waiting for status
+ *           - ETH_DMA_TRANSMITPROCESS_READING   : Running - reading the data from host memory
+ *           - ETH_DMA_TRANSMITPROCESS_SUSPENDED : Suspended - Tx Descriptor unavailable
+ *           - ETH_DMA_TRANSMITPROCESS_CLOSING   : Running - closing Rx descriptor
+ */
+uint32_t ETH_ReadTransmitProcessState(void)
+{
+    return ((uint32_t)(ETH->DMASTS & BIT0) ? SET : RESET);
+}
+
+/*!
+ * @brief  Returns the ETH DMA Receive Process State.
+ *
+ * @param  None
+ *
+ * @retval The new ETH DMA Receive Process State:
+ *         This can be one of the following values:
+ *           - ETH_DMA_RECEIVEPROCESS_STOPPED   : Stopped - Reset or Stop Rx Command issued
+ *           - ETH_DMA_RECEIVEPROCESS_FETCHING  : Running - fetching the Rx descriptor
+ *           - ETH_DMA_RECEIVEPROCESS_WAITING   : Running - waiting for packet
+ *           - ETH_DMA_RECEIVEPROCESS_SUSPENDED : Suspended - Rx Descriptor unavailable
+ *           - ETH_DMA_RECEIVEPROCESS_CLOSING   : Running - closing descriptor
+ *           - ETH_DMA_RECEIVEPROCESS_QUEUING   : Running - queuing the receive frame into host memory
+ */
+uint32_t ETH_ReadReceiveProcessState(void)
+{
+    return ((uint32_t)(ETH->DMASTS & BIT6) ? SET : RESET);
+}
+
+/*!
+ * @brief  Flush the ETH transmit FIFO.
+ *
+ * @param  None
+ *
+ * @retval None
+  */
+void ETH_FlushTransmitFIFO(void)
+{
+    ETH->DMAOPMOD_B.FTXF = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Read the ETH flush transmit FIFO status.
+ *
+ * @param  None
+ *
+ * @retval SET or RESET.
+ */
+uint8_t ETH_ReadFlushTransmitFIFOStatus(void)
+{
+    return ETH->DMAOPMOD_B.FTXF;
+}
+
+/*!
+ * @brief  Enable the DMA transmission.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_EnableDMATransmission(void)
+{
+    ETH->DMAOPMOD_B.STTX = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Disable the DMA transmission.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_DisableDMATransmission(void)
+{
+    ETH->DMAOPMOD_B.STTX = RESET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Enable the DMA receiver.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_EnableDMAReceiver(void)
+{
+    ETH->DMAOPMOD_B.STRX = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Disable the DMA receiver.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_DisableDMAReceiver(void)
+{
+    ETH->DMAOPMOD_B.STRX = RESET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Enable the ETH DMA interrupts.
+ *
+ * @param  interrupt: specifies the ETH DMA interrupt sources.
+ *         This parameter can be any combination of the following values:
+ *           @arg ETH_DMA_INT_NIS : Normal interrupt summary
+ *           @arg ETH_DMA_INT_AIS : Abnormal interrupt summary
+ *           @arg ETH_DMA_INT_ER  : Early receive interrupt
+ *           @arg ETH_DMA_INT_FBE : Fatal bus error interrupt
+ *           @arg ETH_DMA_INT_ET  : Early transmit interrupt
+ *           @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt
+ *           @arg ETH_DMA_INT_RPS : Receive process stopped interrupt
+ *           @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt
+ *           @arg ETH_DMA_INT_RX  : Receive interrupt
+ *           @arg ETH_DMA_INT_TU  : Underflow interrupt
+ *           @arg ETH_DMA_INT_RO  : Overflow interrupt
+ *           @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt
+ *           @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt
+ *           @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt
+ *           @arg ETH_DMA_INT_TX  : Transmit interrupt
+ *
+ * @retval None
+ */
+void ETH_EnableDMAInterrupt(uint32_t interrupt)
+{
+    ETH->DMAINTEN |= interrupt;
+}
+
+/*!
+ * @brief  Disable the ETH DMA interrupts.
+ *
+ * @param  interrupt: specifies the ETH DMA interrupt sources.
+ *         This parameter can be any combination of the following values:
+ *           @arg ETH_DMA_INT_NIS : Normal interrupt summary
+ *           @arg ETH_DMA_INT_AIS : Abnormal interrupt summary
+ *           @arg ETH_DMA_INT_ER  : Early receive interrupt
+ *           @arg ETH_DMA_INT_FBE : Fatal bus error interrupt
+ *           @arg ETH_DMA_INT_ET  : Early transmit interrupt
+ *           @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt
+ *           @arg ETH_DMA_INT_RPS : Receive process stopped interrupt
+ *           @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt
+ *           @arg ETH_DMA_INT_RX  : Receive interrupt
+ *           @arg ETH_DMA_INT_TU  : Underflow interrupt
+ *           @arg ETH_DMA_INT_RO  : Overflow interrupt
+ *           @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt
+ *           @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt
+ *           @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt
+ *           @arg ETH_DMA_INT_TX  : Transmit interrupt
+ *
+ * @retval None
+ */
+void ETH_DisableDMAInterrupt(uint32_t interrupt)
+{
+    ETH->DMAINTEN &= ((uint32_t)~interrupt);
+}
+
+/*!
+ * @brief  Read the ETH DMA overflow flag.
+ *
+ * @param  overflow: specifies the DMA overflow flag to check.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER        : Overflow for FIFO Overflows Counter
+ *           @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER   : Overflow for Buffer Unavailable Missed Frame Counter
+ *
+ * @retval SET or RESET.
+ */
+uint8_t ETH_ReadDMAOverflowStatus(ETH_DMA_OVERFLOW_T overflow)
+{
+    return (ETH->DMAMFABOCNT & overflow) ? SET : RESET;
+}
+
+/*!
+ * @brief  Read the ETH DMA Rx Overflow Missed Frame Counter value.
+ *
+ * @param  None
+ *
+ * @retval The value of Rx overflow Missed Frame Counter.
+ */
+uint32_t ETH_ReadRxOverflowMissedFrameCounter(void)
+{
+    return (uint32_t)(ETH->DMAMFABOCNT_B.AMISFCNT);
+}
+
+/*!
+ * @brief  Read the ETH DMA Buffer Unavailable Missed Frame Counter value.
+ *
+ * @param  None
+ *
+ * @retval The value of Buffer unavailable Missed Frame Counter.
+ */
+uint32_t ETH_ReadBufferUnavailableMissedFrameCounter(void)
+{
+    return (uint32_t)(ETH->DMAMFABOCNT_B.MISFCNT);
+}
+
+/*!
+ * @brief  Read the ETH DMA DMAHTXD register value.
+ *
+ * @param  None
+ *
+ * @retval The value of the current Tx desc start address.
+ */
+uint32_t ETH_ReadCurrentTxDescStartAddress(void)
+{
+    return ((uint32_t)(ETH->DMAHTXD));
+}
+
+/*!
+ * @brief  Read the ETHERNET DMA DMAHRXD register value.
+ *
+ * @param  None
+ *
+ * @retval The value of the current Rx desc start address.
+ */
+uint32_t ETH_ReadCurrentRxDescStartAddress(void)
+{
+    return ((uint32_t)(ETH->DMAHRXD));
+}
+
+/*!
+ * @brief  Read the ETH DMA DMAHTXBADDR register value.
+ *
+ * @param  None
+ *
+ * @retval The value of the current transmit descriptor data buffer address.
+ */
+uint32_t ETH_ReadCurrentTxBufferAddress(void)
+{
+    return ((uint32_t)(ETH->DMAHTXBADDR));
+}
+
+/*!
+ * @brief  Read the ETH DMA DMAHRXBADDR register value.
+ *
+ * @param  None
+ *
+ * @retval The value of the current receive descriptor data buffer address.
+ */
+uint32_t ETH_ReadCurrentRxBufferAddress(void)
+{
+    return ((uint32_t)(ETH->DMAHRXBADDR));
+}
+
+/*!
+ * @brief  Reset the DMA Transmission by writing to the DmaTxPollDemand register
+ *
+ * @param  None
+
+ * @retval None.
+ */
+void ETH_ResetDMATransmission(void)
+{
+    ETH->DMATXPD = 0;
+}
+
+/*!
+ * @brief  Reset the DMA Transmission by writing to the DmaRxPollDemand register
+ *
+ * @param  None
+ *
+ * @retval None.
+ */
+void ETH_ResetDMAReception(void)
+{
+    ETH->DMARXPD = 0;
+}
+
+/** Power Management(PMT) functions */
+
+/*!
+ * @brief  Reset Wakeup frame filter register pointer.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
+{
+    ETH->PMTCTRLSTS_B.WKUPFRST = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Enable any unicast packet filtered by the MAC address
+ *         recognition to be a wake-up frame.
+ *
+ * @retval None
+ */
+void ETH_EnableGlobalUnicastWakeUp(void)
+{
+    ETH->PMTCTRLSTS_B.GUN = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Disable any unicast packet filtered by the MAC address
+ *         recognition to be a wake-up frame.
+ *
+ * @retval None
+ */
+void ETH_DisableGlobalUnicastWakeUp(void)
+{
+    ETH->PMTCTRLSTS_B.GUN = RESET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Read the ETH PMT flag.
+ *
+ * @param  flag: specifies the flag to check.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
+ *           @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received
+ *           @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
+ *
+ * @retval SET or RESET.
+ */
+uint8_t ETH_ReadPMTFlagStatus(ETH_PMT_FLAG_T flag)
+{
+    return (ETH->PMTCTRLSTS & flag) ? SET : RESET;
+}
+
+/*!
+ * @brief  Enable the MAC Wake-Up Frame Detection.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_EnableWakeUpFrameDetection(void)
+{
+    ETH->PMTCTRLSTS_B.WKUPFEN = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Disable the MAC Wake-Up Frame Detection.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_DisableWakeUpFrameDetection(void)
+{
+    ETH->PMTCTRLSTS_B.WKUPFEN = RESET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Enable the MAC Magic Packet Detection.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_EnableMagicPacketDetection(void)
+{
+    ETH->PMTCTRLSTS_B.MPEN = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Disable the MAC Magic Packet Detection.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_DisableMagicPacketDetection(void)
+{
+    ETH->PMTCTRLSTS_B.MPEN = RESET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Enable the MAC Power Down.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_EnablePowerDown(void)
+{
+    ETH->PMTCTRLSTS_B.PD = SET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Disable the MAC Power Down.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_DisablePowerDown(void)
+{
+    ETH->PMTCTRLSTS_B.PD = RESET;
+    ETH_Delay(ETH_REG_WRITE_DELAY);
+}
+
+/*!
+ * @brief  Enable the MMC Counter Freeze.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_EnableMMCCounterFreeze(void)
+{
+    ETH->CTRL_B.MCNTF = SET;
+}
+
+/*!
+ * @brief  Disable the MMC Counter Freeze.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_DisableMMCCounterFreeze(void)
+{
+    ETH->CTRL_B.MCNTF = RESET;
+}
+
+/*!
+ * @brief  Enable the MMC Reset On Read.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_EnableMMCResetOnRead(void)
+{
+    ETH->CTRL_B.RSTOR = SET;
+}
+
+/*!
+ * @brief  Disable the MMC Reset On Read.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_DisableMMCResetOnRead(void)
+{
+    ETH->CTRL_B.RSTOR = RESET;
+}
+
+/*!
+ * @brief  Enble the MMC Counter Stop Rollover.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_EnableMMCCounterRollover(void)
+{
+    ETH->CTRL_B.CNTSTOPRO = RESET;
+}
+
+/*!
+ * @brief  Disable the MMC Counter Stop Rollover.
+ *
+ * @param  None
+ *
+ * @retval None
+ */
+void ETH_DisableMMCCounterRollover(void)
+{
+    ETH->CTRL_B.CNTSTOPRO = SET;
+}
+
+/**
+  * @brief  Resets the MMC Counters.
+  * @param  None
+  * @retval None
+  */
+void ETH_ResetMMCCounters(void)
+{
+    ETH->CTRL_B.CNTRST = SET;
+}
+
+/*!
+ * @brief  Enable the ETH MMC interrupts.
+ *
+ * @param  interrupt: specifies the ETH MMC interrupt sources.
+ *         This parameter can be any combination of Tx interrupt or
+ *         any combination of Rx interrupt (but not both)of the following values:
+ *           @arg ETH_MMC_INT_TGF   : When Tx good frame counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_RFAE  : When Rx alignment error counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_RFCE  : When Rx crc error counter reaches half the maximum value
+ *
+ * @retval None
+ */
+void ETH_EnableMMCInterrupt(uint32_t interrupt)
+{
+    if ((interrupt & 0x10000000) == SET)
+    {
+        ETH->RXINTMASK &= (~(uint32_t)interrupt);
+    }
+    else
+    {
+        ETH->TXINTMASK &= (~(uint32_t)interrupt);
+    }
+}
+
+/*!
+ * @brief  Disable the ETH MMC interrupts.
+ *
+ * @param  interrupt: specifies the ETH MMC interrupt sources.
+ *         This parameter can be any combination of Tx interrupt or
+ *         any combination of Rx interrupt (but not both)of the following values:
+ *           @arg ETH_MMC_INT_TGF   : When Tx good frame counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_RFAE  : When Rx alignment error counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_RFCE  : When Rx crc error counter reaches half the maximum value
+ *
+ * @retval None
+ */
+void ETH_DisableMMCInterrupt(uint32_t interrupt)
+{
+    if ((interrupt & 0x10000000) == SET)
+    {
+        ETH->RXINTMASK |= interrupt;
+    }
+    else
+    {
+        ETH->TXINTMASK |= interrupt;
+    }
+}
+
+/*!
+ * @brief  Read the ETH MMC interrupt flag.
+ *
+ * @param  flag: specifies the ETH MMC interrupt.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_MMC_INT_TGF   : When Tx good frame counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_RFAE  : When Rx alignment error counter reaches half the maximum value
+ *           @arg ETH_MMC_INT_RFCE  : When Rx crc error counter reaches half the maximum value
+ *
+ * @retval SET or RESET.
+ */
+uint8_t ETH_ReadMMCIntFlag(uint32_t flag)
+{
+    if ((flag & 0x10000000) == SET)
+    {
+        return ((((ETH->RXINT & flag) != RESET)) && ((ETH->RXINTMASK & flag) == RESET));
+    }
+    else
+    {
+        return ((((ETH->TXINT & flag) != RESET)) && ((ETH->TXINTMASK & flag) == RESET));
+    }
+}
+
+/*!
+ * @brief  Read the ETH MMC register value.
+ *
+ * @param  MMCReg: specifies the ETH MMC register.
+ *         This parameter can be one of the following values:
+ *           @arg ETH_MMC_CTRL      : MMC CTRL register
+ *           @arg ETH_MMC_RXINT     : MMC RXINT register
+ *           @arg ETH_MMC_TXINT     : MMC TXINT register
+ *           @arg ETH_MMC_RXINTMASK : MMC RXINTMASK register
+ *           @arg ETH_MMC_TXINTMASK : MMC TXINTMASK register
+ *           @arg ETH_MMC_TXGFSCCNT : MMC TXGFSCCNT register
+ *           @arg ETH_MMC_TXGFMCCNT : MMC TXGFMCCNT register
+ *           @arg ETH_MMC_TXGFCNT   : MMC TXGFCNT register
+ *           @arg ETH_MMC_RXFCECNT  : MMC RXFCECNT register
+ *           @arg ETH_MMC_RXFAECNT  : MMC RXFAECNT register
+ *           @arg ETH_MMC_RXGUNCNT  : MMC RXGUNCNT register
+ *
+ * @retval Return ETH MMC Register value.
+ */
+uint32_t ETH_ReadMMCRegister(ETH_MMC_REG_T MMCReg)
+{
+    return (*(__IO uint32_t*)(ETH_MAC_BASE + MMCReg));
+}
+
+#endif
+
+/**@} end of group ETH_Functions */
+/**@} end of group ETH_Driver */
+/**@} end of group APM32F10x_ETHDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the ADC firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,17 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_ADC_H
 #define __APM32F10X_ADC_H
 
+/* Includes */
+#include "apm32f10x.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +41,33 @@ extern "C" {
   @{
 */
 
-/** @addtogroup ADC_Enumerations Enumerations
+
+/** @defgroup ADC_Macros
+  @{
+*/
+
+/* ADC_IJD Offset */
+#define INJDATA_OFFSET          ((uint8_t)0x28)
+
+/* ADC_RDG register address */
+#define RDG_ADDRESS             ((uint32_t)0x4001244C)
+
+/* INJSEQ register config */
+#define INJSEQ_SET_INJSEQC      ((uint32_t)0x0000001F)
+#define INJSEQ_SET_INJSEQLEN    ((uint32_t)0x00300000)
+
+/* SMPTIM register SET */
+#define SMPCYCCFG_SET_SMPTIM1   ((uint32_t)0x00000007)
+#define SMPCYCCFG_SET_SMPTIM2   ((uint32_t)0x00000007)
+
+/* REGSEQ register SET  */
+#define REGSEQC_SET_REGSEQ3     ((uint32_t)0x0000001F)
+#define REGSEQC_SET_REGSEQ2     ((uint32_t)0x0000001F)
+#define REGSEQC_SET_REGSEQ1     ((uint32_t)0x0000001F)
+
+/**@} end of group ADC_Macros*/
+
+/** @defgroup ADC_Enumerations
   @{
 */
 
@@ -49,16 +76,16 @@ extern "C" {
  */
 typedef enum
 {
-    ADC_MODE_INDEPENDENT              = ((uint32_t)0x00000000), //!< Independent mode
-    ADC_MODE_REG_INJEC_SIMULT         = ((uint32_t)0x00010000), //!< Combined regular simultaneous and injected simultaneous mode
-    ADC_MODE_REG_SIMULT_ALTER_TRIG    = ((uint32_t)0x00020000), //!< Combined regular simultaneous and alternate trigger mode
-    ADC_MODE_INJEC_SIMULT_FAST_TNTERL = ((uint32_t)0x00030000), //!< Combined injected simultaneous and fast interleaved mode
-    ADC_MODE_INJEC_SIMULT_SLOW_INTERL = ((uint32_t)0x00040000), //!< Combined injected simultaneous and slow interleaved mode
-    ADC_MODE_INJEC_SIMULT             = ((uint32_t)0x00050000), //!< Injected simultaneous mode
-    ADC_MODE_REG_SIMULT               = ((uint32_t)0x00060000), //!< Regular simultaneous mode
-    ADC_MODE_FAST_INTERL              = ((uint32_t)0x00070000), //!< Fast interleaved mode
-    ADC_MODE_SLOW_INTERL              = ((uint32_t)0x00080000), //!< Slow interleaved mode
-    ADC_MODE_ALTER_TRIG               = ((uint32_t)0x00090000)  //!< Alternate trigger mode
+    ADC_MODE_INDEPENDENT              = ((uint32_t)0x00000000), /*!< Independent mode */
+    ADC_MODE_REG_INJEC_SIMULT         = ((uint32_t)0x00010000), /*!< Combined regular simultaneous and injected simultaneous mode */
+    ADC_MODE_REG_SIMULT_ALTER_TRIG    = ((uint32_t)0x00020000), /*!< Combined regular simultaneous and alternate trigger mode */
+    ADC_MODE_INJEC_SIMULT_FAST_TNTERL = ((uint32_t)0x00030000), /*!< Combined injected simultaneous and fast interleaved mode */
+    ADC_MODE_INJEC_SIMULT_SLOW_INTERL = ((uint32_t)0x00040000), /*!< Combined injected simultaneous and slow interleaved mode */
+    ADC_MODE_INJEC_SIMULT             = ((uint32_t)0x00050000), /*!< Injected simultaneous mode */
+    ADC_MODE_REG_SIMULT               = ((uint32_t)0x00060000), /*!< Regular simultaneous mode */
+    ADC_MODE_FAST_INTERL              = ((uint32_t)0x00070000), /*!< Fast interleaved mode */
+    ADC_MODE_SLOW_INTERL              = ((uint32_t)0x00080000), /*!< Slow interleaved mode */
+    ADC_MODE_ALTER_TRIG               = ((uint32_t)0x00090000)  /*!< Alternate trigger mode */
 } ADC_MODE_T;
 
 /**
@@ -71,7 +98,7 @@ typedef enum
     ADC_EXT_TRIG_CONV_TMR2_CC2        = ((uint32_t)0x00060000),
     ADC_EXT_TRIG_CONV_TMR3_TRGO       = ((uint32_t)0x00080000),
     ADC_EXT_TRIG_CONV_TMR4_CC4        = ((uint32_t)0x000A0000),
-    ADC_EXT_TRIG_CONV_EINT9_T8_TRGO   = ((uint32_t)0x000C0000),
+    ADC_EXT_TRIG_CONV_EINT11_T8_TRGO  = ((uint32_t)0x000C0000),
     ADC_EXT_TRIG_CONV_TMR1_CC3        = ((uint32_t)0x00040000),
     ADC_EXT_TRIG_CONV_None            = ((uint32_t)0x000E0000),
 
@@ -139,19 +166,19 @@ typedef enum
  */
 typedef enum
 {
-    /** for ADC1 and ADC2 */
+    /* for ADC1 and ADC2 */
     ADC_EXT_TRIG_INJEC_CONV_TMR2_TRGO       = ((uint8_t)0x02),
     ADC_EXT_TRIG_INJEC_CONV_TMR2_CC1        = ((uint8_t)0x03),
     ADC_EXT_TRIG_INJEC_CONV_TMR3_CC4        = ((uint8_t)0x04),
     ADC_EXT_TRIG_INJEC_CONV_TMR4_TRGO       = ((uint8_t)0x05),
     ADC_EXT_TRIG_INJEC_CONV_EINT15_T8_CC4   = ((uint8_t)0x06),
 
-    /** for ADC1, ADC2 and ADC3 */
+    /* for ADC1, ADC2 and ADC3 */
     ADC_EXT_TRIG_INJEC_CONV_TMR1_TRGO       = ((uint8_t)0x00),
     ADC_EXT_TRIG_INJEC_CONV_TMR1_CC4        = ((uint8_t)0x01),
     ADC_EXT_TRIG_INJEC_CONV_NONE            = ((uint8_t)0x07),
 
-    /** for ADC3 only */
+    /* for ADC3 only */
     ADC_EXT_TRIG_INJEC_CONV_TMR4_CC3        = ((uint8_t)0x02),
     ADC_EXT_TRIG_INJEC_CONV_TMR8_CC2        = ((uint8_t)0x03),
     ADC_EXT_TRIG_INJEC_CONV_TMR8_CC4        = ((uint8_t)0x04),
@@ -189,9 +216,9 @@ typedef enum
  */
 typedef enum
 {
-    ADC_INT_AWD    = ((uint16_t)0x0140), //!<  Analog Watchdog interrupt
-    ADC_INT_EOC    = ((uint16_t)0x0220), //!<  End Of Conversion interrupt
-    ADC_INT_INJEOC = ((uint16_t)0x0480)  //!<  Injected Channel End Of Conversion interrupt
+    ADC_INT_AWD    = ((uint16_t)0x0140), /*!<  Analog Watchdog interrupt */
+    ADC_INT_EOC    = ((uint16_t)0x0220), /*!<  End Of Conversion interrupt */
+    ADC_INT_INJEOC = ((uint16_t)0x0480)  /*!<  Injected Channel End Of Conversion interrupt */
 } ADC_INT_T;
 
 /**
@@ -199,43 +226,16 @@ typedef enum
  */
 typedef enum
 {
-    ADC_FLAG_AWD    = ((uint8_t)0x01), //!<  Analog Watchdog event occur flag
-    ADC_FLAG_EOC    = ((uint8_t)0x02), //!<  End Of Conversion flag
-    ADC_FLAG_INJEOC = ((uint8_t)0x04), //!<  Injected Channel End Of Conversion flag
-    ADC_FLAG_INJCS  = ((uint8_t)0x08), //!<  Injected Channel Conversion Start flag
-    ADC_FLAG_REGCS  = ((uint8_t)0x10)  //!<  Regular Channel Conversion Start flag
+    ADC_FLAG_AWD    = ((uint8_t)0x01), /*!<  Analog Watchdog event occur flag */
+    ADC_FLAG_EOC    = ((uint8_t)0x02), /*!<  End Of Conversion flag */
+    ADC_FLAG_INJEOC = ((uint8_t)0x04), /*!<  Injected Channel End Of Conversion flag */
+    ADC_FLAG_INJCS  = ((uint8_t)0x08), /*!<  Injected Channel Conversion Start flag */
+    ADC_FLAG_REGCS  = ((uint8_t)0x10)  /*!<  Regular Channel Conversion Start flag */
 } ADC_FLAG_T;
 
 /**@} end of group ADC_Enumerations*/
 
-
-/** @addtogroup ADC_Macros Macros
-  @{
-*/
-
-/** ADC_IJD Offset */
-#define INJDATA_OFFSET          ((uint8_t)0x28)
-
-/** ADC_RDG register address */
-#define RDG_ADDRESS             ((uint32_t)0x4001244C)
-
-/** INJSEQ register config */
-#define INJSEQ_SET_INJSEQC      ((uint32_t)0x0000001F)
-#define INJSEQ_SET_INJSEQLEN    ((uint32_t)0x00300000)
-
-/** SMPTIM register SET */
-#define SMPCYCCFG_SET_SMPTIM1   ((uint32_t)0x00000007)
-#define SMPCYCCFG_SET_SMPTIM2   ((uint32_t)0x00000007)
-
-/** REGSEQ register SET  */
-#define REGSEQC_SET_REGSEQ3     ((uint32_t)0x0000001F)
-#define REGSEQC_SET_REGSEQ2     ((uint32_t)0x0000001F)
-#define REGSEQC_SET_REGSEQ1     ((uint32_t)0x0000001F)
-
-/**@} end of group ADC_Macros*/
-
-
-/** @addtogroup ADC_Structure Data Structure
+/** @defgroup ADC_Structures Structures
   @{
 */
 
@@ -245,102 +245,104 @@ typedef enum
 typedef struct
 {
     ADC_MODE_T          mode;
-    uint8_t             scanConvMode;       //!< This parameter can be ENABLE or DISABLE.
-    uint8_t             continuosConvMode;  //!< This parameter can be ENABLE or DISABLE.
+    uint8_t             scanConvMode;       /*!< This parameter can be ENABLE or DISABLE. */
+    uint8_t             continuosConvMode;  /*!< This parameter can be ENABLE or DISABLE. */
     ADC_EXT_TRIG_CONV_T externalTrigConv;
     ADC_DATA_ALIGN_T    dataAlign;
-    uint8_t             nbrOfChannel;       //!< This parameter must range from 1 to 16.
+    uint8_t             nbrOfChannel;       /*!< This parameter must range from 1 to 16. */
 } ADC_Config_T;
 
-/**@} end of group ADC_Structure*/
+/**@} end of group ADC_Structures*/
 
 
-/** @addtogroup ADC_Fuctions Fuctions
+/** @defgroup ADC_Functions Functions
   @{
 */
 
-/** ADC reset and common configuration */
-void ADC_Reset(ADC_T *adc);
-void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig);
-void ADC_ConfigStructInit(ADC_Config_T *adcConfig);
-void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
-void ADC_Enable(ADC_T *adc);
-void ADC_Disable(ADC_T *adc);
-
-/** ADC for DMA */
-void ADC_EnableDMA(ADC_T *adc);
-void ADC_DisableDMA(ADC_T *adc);
-
-/** ADC Calibration */
-void ADC_ResetCalibration(ADC_T *adc);
-uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc);
-void ADC_StartCalibration(ADC_T *adc);
-uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc);
-
-/** ADC software start conversion */
-void ADC_EnableSoftwareStartConv(ADC_T *adc);
-void ADC_DisableSoftwareStartConv(ADC_T *adc);
-uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc);
-
-/** ADC Discontinuous mode */
-void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number);
-void ADC_EnableDiscMode(ADC_T *adc);
-void ADC_DisableDiscMode(ADC_T *adc);
-
-/** ADC External trigger conversion */
-void ADC_EnableExternalTrigConv(ADC_T *adc);
-void ADC_DisableExternalTrigConv(ADC_T *adc);
-
-/** ADC Conversion result */
-uint16_t ADC_ReadConversionValue(ADC_T *adc);
-uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc);
-
-/** ADC Automatic injected group */
-void ADC_EnableAutoInjectedConv(ADC_T *adc);
-void ADC_DisableAutoInjectedConv(ADC_T *adc);
-void ADC_EnableInjectedDiscMode(ADC_T *adc);
-void ADC_DisableInjectedDiscMode(ADC_T *adc);
-
-/** ADC External trigger for injected channels conversion */
-void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv);
-void ADC_EnableExternalTrigInjectedConv(ADC_T *adc);
-void ADC_DisableExternalTrigInjectedConv(ADC_T *adc);
-
-/** ADC Start of the injected channels conversion */
-void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc);
-void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc);
-uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc);
-
-/** ADC injected channel */
-void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
-void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length);
-void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet);
-uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel);
-
-/** ADC analog watchdog */
-void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog);
-void ADC_DisableAnalogWatchdog(ADC_T *adc);
-void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint16_t lowThreshold);
-void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel);
-
-/** ADC temperature sensor */
-void ADC_EnableTempSensorVrefint(ADC_T *adc);
-void ADC_DisableTempSensorVrefint(ADC_T *adc);
-
-/** Interrupt and flag */
-void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt);
-void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt);
-uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag);
-void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag);
-uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag);
-void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag);
-
-/**@} end of group ADC_Fuctions*/
-/**@} end of group ADC_Driver*/
-/**@} end of group Peripherals_Library*/
+/* ADC reset and common configuration */
+void ADC_Reset(ADC_T* adc);
+void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig);
+void ADC_ConfigStructInit(ADC_Config_T* adcConfig);
+void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
+void ADC_Enable(ADC_T* adc);
+void ADC_Disable(ADC_T* adc);
+
+/* ADC for DMA */
+void ADC_EnableDMA(ADC_T* adc);
+void ADC_DisableDMA(ADC_T* adc);
+
+/* ADC Calibration */
+void ADC_ResetCalibration(ADC_T* adc);
+uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc);
+void ADC_StartCalibration(ADC_T* adc);
+uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc);
+
+/* ADC software start conversion */
+void ADC_EnableSoftwareStartConv(ADC_T* adc);
+void ADC_DisableSoftwareStartConv(ADC_T* adc);
+uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc);
+
+/* ADC Discontinuous mode */
+void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number);
+void ADC_EnableDiscMode(ADC_T* adc);
+void ADC_DisableDiscMode(ADC_T* adc);
+
+/* ADC External trigger conversion */
+void ADC_EnableExternalTrigConv(ADC_T* adc);
+void ADC_DisableExternalTrigConv(ADC_T* adc);
+
+/* ADC Conversion result */
+uint16_t ADC_ReadConversionValue(ADC_T* adc);
+uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc);
+
+/* ADC Automatic injected group */
+void ADC_EnableAutoInjectedConv(ADC_T* adc);
+void ADC_DisableAutoInjectedConv(ADC_T* adc);
+void ADC_EnableInjectedDiscMode(ADC_T* adc);
+void ADC_DisableInjectedDiscMode(ADC_T* adc);
+
+/* ADC External trigger for injected channels conversion */
+void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv);
+void ADC_EnableExternalTrigInjectedConv(ADC_T* adc);
+void ADC_DisableExternalTrigInjectedConv(ADC_T* adc);
+
+/* ADC Start of the injected channels conversion */
+void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc);
+void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc);
+uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc);
+
+/* ADC injected channel */
+void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
+void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length);
+void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet);
+uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel);
+
+/* ADC analog watchdog */
+void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog);
+void ADC_DisableAnalogWatchdog(ADC_T* adc);
+void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold);
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel);
+
+/* ADC temperature sensor */
+void ADC_EnableTempSensorVrefint(ADC_T* adc);
+void ADC_DisableTempSensorVrefint(ADC_T* adc);
+
+/* Interrupt and flag */
+void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt);
+void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt);
+uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag);
+void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag);
+uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T flag);
+void ADC_ClearIntFlag(ADC_T* adc, uint16_t flag);
+
+
 
 #ifdef __cplusplus
 }
+
+/**@} end of group ADC_Functions*/
+/**@} end of group ADC_Driver*/
+/**@} end of group APM32F10x_StdPeriphDriver */
 #endif
 
-#endif /** __APM32F10X_ADC_H */
+#endif /* __APM32F10X_ADC_H */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the BAKPR firmware library.
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,13 +26,14 @@
 #ifndef __APM32F10X_BAKPR_H
 #define __APM32F10X_BAKPR_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +41,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup BAKPR_Enumerations Enumerations
+/** @defgroup BAKPR_Enumerations Enumerations
   @{
 */
 
@@ -116,11 +117,11 @@ typedef enum
 /**@} end of group BAKPR_Enumerations*/
 
 
-/** @addtogroup BAKPR_Fuctions Fuctions
+/** @defgroup BAKPR_Functions Functions
   @{
 */
 
-/** BAKPR reset and configuration */
+/* BAKPR reset and configuration */
 void BAKPR_Reset(void);
 void BAKPR_ConfigTamperPinLevel(BAKPR_TAMPER_PIN_LEVEL_T value);
 void BAKPR_EnableTamperPin(void);
@@ -130,7 +131,7 @@ void BAKPR_ConfigRTCCalibrationValue(uint8_t calibrationValue);
 void BAKPR_ConfigBackupRegister(BAKPR_DATA_T bakrData, uint16_t data);
 uint16_t BAKPR_ReadBackupRegister(BAKPR_DATA_T bakrData);
 
-/** Interrupts and flags */
+/* Interrupts and flags */
 void BAKPR_EnableInterrupt(void);
 void BAKPR_DisableInterrupt(void);
 uint8_t BAKPR_ReadStatusFlag(void);
@@ -138,9 +139,9 @@ void BAKPR_ClearStatusFlag(void);
 uint8_t BAKPR_ReadIntFlag(void);
 void BAKPR_ClearIntFlag(void);
 
-/**@} end of group BAKPR_Fuctions*/
-/**@} end of group BAKPR_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group BAKPR_Functions*/
+/**@} end of group BAKPR_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the CAN firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_CAN_H
 #define __APM32F10X_CAN_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +42,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup CAN_Enumerations Enumerations
+/** @defgroup CAN_Enumerations Enumerations
   @{
 */
 
@@ -49,10 +51,10 @@ extern "C" {
  */
 typedef enum
 {
-    CAN_MODE_NORMAL          = ((uint8_t)0x00),  //!< normal mode
-    CAN_MODE_LOOPBACK        = ((uint8_t)0x01),  //!< loopback mode
-    CAN_MODE_SILENT          = ((uint8_t)0x02),  //!< silent mode
-    CAN_MODE_SILENT_LOOPBACK = ((uint8_t)0x03)   //!< loopback combined with silent mode
+    CAN_MODE_NORMAL          = ((uint8_t)0x00),  /*!< normal mode */
+    CAN_MODE_LOOPBACK        = ((uint8_t)0x01),  /*!< loopback mode */
+    CAN_MODE_SILENT          = ((uint8_t)0x02),  /*!< silent mode */
+    CAN_MODE_SILENT_LOOPBACK = ((uint8_t)0x03)   /*!< loopback combined with silent mode */
 } CAN_MODE_T;
 
 /**
@@ -60,10 +62,10 @@ typedef enum
  */
 typedef enum
 {
-    CAN_SJW_1 = ((uint8_t)0x00),  //!< 1 time quantum
-    CAN_SJW_2 = ((uint8_t)0x01),  //!< 2 time quantum
-    CAN_SJW_3 = ((uint8_t)0x02),  //!< 3 time quantum
-    CAN_SJW_4 = ((uint8_t)0x03)   //!< 4 time quantum
+    CAN_SJW_1 = ((uint8_t)0x00),  /*!< 1 time quantum */
+    CAN_SJW_2 = ((uint8_t)0x01),  /*!< 2 time quantum */
+    CAN_SJW_3 = ((uint8_t)0x02),  /*!< 3 time quantum */
+    CAN_SJW_4 = ((uint8_t)0x03)   /*!< 4 time quantum */
 } CAN_SJW_T;
 
 /**
@@ -71,22 +73,22 @@ typedef enum
  */
 typedef enum
 {
-    CAN_TIME_SEGMENT1_1  = ((uint8_t)0x00),  //!< 1  time quanta
-    CAN_TIME_SEGMENT1_2  = ((uint8_t)0x01),  //!< 2  time quanta
-    CAN_TIME_SEGMENT1_3  = ((uint8_t)0x02),  //!< 3  time quanta
-    CAN_TIME_SEGMENT1_4  = ((uint8_t)0x03),  //!< 4  time quanta
-    CAN_TIME_SEGMENT1_5  = ((uint8_t)0x04),  //!< 5  time quanta
-    CAN_TIME_SEGMENT1_6  = ((uint8_t)0x05),  //!< 6  time quanta
-    CAN_TIME_SEGMENT1_7  = ((uint8_t)0x06),  //!< 7  time quanta
-    CAN_TIME_SEGMENT1_8  = ((uint8_t)0x07),  //!< 8  time quanta
-    CAN_TIME_SEGMENT1_9  = ((uint8_t)0x08),  //!< 9  time quanta
-    CAN_TIME_SEGMENT1_10 = ((uint8_t)0x09),  //!< 10 time quanta
-    CAN_TIME_SEGMENT1_11 = ((uint8_t)0x0A),  //!< 11 time quanta
-    CAN_TIME_SEGMENT1_12 = ((uint8_t)0x0B),  //!< 12 time quanta
-    CAN_TIME_SEGMENT1_13 = ((uint8_t)0x0C),  //!< 13 time quanta
-    CAN_TIME_SEGMENT1_14 = ((uint8_t)0x0D),  //!< 14 time quanta
-    CAN_TIME_SEGMENT1_15 = ((uint8_t)0x0E),  //!< 15 time quanta
-    CAN_TIME_SEGMENT1_16 = ((uint8_t)0x0F)   //!< 16 time quanta
+    CAN_TIME_SEGMENT1_1  = ((uint8_t)0x00),  /*!< 1  time quanta */
+    CAN_TIME_SEGMENT1_2  = ((uint8_t)0x01),  /*!< 2  time quanta */
+    CAN_TIME_SEGMENT1_3  = ((uint8_t)0x02),  /*!< 3  time quanta */
+    CAN_TIME_SEGMENT1_4  = ((uint8_t)0x03),  /*!< 4  time quanta */
+    CAN_TIME_SEGMENT1_5  = ((uint8_t)0x04),  /*!< 5  time quanta */
+    CAN_TIME_SEGMENT1_6  = ((uint8_t)0x05),  /*!< 6  time quanta */
+    CAN_TIME_SEGMENT1_7  = ((uint8_t)0x06),  /*!< 7  time quanta */
+    CAN_TIME_SEGMENT1_8  = ((uint8_t)0x07),  /*!< 8  time quanta */
+    CAN_TIME_SEGMENT1_9  = ((uint8_t)0x08),  /*!< 9  time quanta */
+    CAN_TIME_SEGMENT1_10 = ((uint8_t)0x09),  /*!< 10 time quanta */
+    CAN_TIME_SEGMENT1_11 = ((uint8_t)0x0A),  /*!< 11 time quanta */
+    CAN_TIME_SEGMENT1_12 = ((uint8_t)0x0B),  /*!< 12 time quanta */
+    CAN_TIME_SEGMENT1_13 = ((uint8_t)0x0C),  /*!< 13 time quanta */
+    CAN_TIME_SEGMENT1_14 = ((uint8_t)0x0D),  /*!< 14 time quanta */
+    CAN_TIME_SEGMENT1_15 = ((uint8_t)0x0E),  /*!< 15 time quanta */
+    CAN_TIME_SEGMENT1_16 = ((uint8_t)0x0F)   /*!< 16 time quanta */
 } CAN_TIME_SEGMENT1_T;
 
 /**
@@ -94,14 +96,14 @@ typedef enum
  */
 typedef enum
 {
-    CAN_TIME_SEGMENT2_1 = (uint8_t)0x00,     //!< 1  time quanta
-    CAN_TIME_SEGMENT2_2 = (uint8_t)0x01,     //!< 2  time quanta
-    CAN_TIME_SEGMENT2_3 = (uint8_t)0x02,     //!< 3  time quanta
-    CAN_TIME_SEGMENT2_4 = (uint8_t)0x03,     //!< 4  time quanta
-    CAN_TIME_SEGMENT2_5 = (uint8_t)0x04,     //!< 5  time quanta
-    CAN_TIME_SEGMENT2_6 = (uint8_t)0x05,     //!< 6  time quanta
-    CAN_TIME_SEGMENT2_7 = (uint8_t)0x06,     //!< 7  time quanta
-    CAN_TIME_SEGMENT2_8 = (uint8_t)0x07      //!< 8  time quanta
+    CAN_TIME_SEGMENT2_1 = (uint8_t)0x00,     /*!< 1  time quanta */
+    CAN_TIME_SEGMENT2_2 = (uint8_t)0x01,     /*!< 2  time quanta */
+    CAN_TIME_SEGMENT2_3 = (uint8_t)0x02,     /*!< 3  time quanta */
+    CAN_TIME_SEGMENT2_4 = (uint8_t)0x03,     /*!< 4  time quanta */
+    CAN_TIME_SEGMENT2_5 = (uint8_t)0x04,     /*!< 5  time quanta */
+    CAN_TIME_SEGMENT2_6 = (uint8_t)0x05,     /*!< 6  time quanta */
+    CAN_TIME_SEGMENT2_7 = (uint8_t)0x06,     /*!< 7  time quanta */
+    CAN_TIME_SEGMENT2_8 = (uint8_t)0x07      /*!< 8  time quanta */
 } CAN_TIME_SEGMENT2_T;
 
 /**
@@ -109,8 +111,8 @@ typedef enum
  */
 typedef enum
 {
-    CAN_FILTER_FIFO_0 = ((uint8_t)0x00),     //!< filter FIFO 0
-    CAN_FILTER_FIFO_1 = ((uint8_t)0x01)      //!< filter FIFO 1
+    CAN_FILTER_FIFO_0 = ((uint8_t)0x00),     /*!< filter FIFO 0 */
+    CAN_FILTER_FIFO_1 = ((uint8_t)0x01)      /*!< filter FIFO 1 */
 } CAN_FILTER_FIFO_T;
 
 /**
@@ -118,8 +120,8 @@ typedef enum
  */
 typedef enum
 {
-    CAN_FILTER_MODE_IDMASK = ((uint8_t)0x00),//!< identifier/mask mode
-    CAN_FILTER_MODE_IDLIST = ((uint8_t)0x01) //!< identifier list mode
+    CAN_FILTER_MODE_IDMASK = ((uint8_t)0x00),/*!< identifier/mask mode */
+    CAN_FILTER_MODE_IDLIST = ((uint8_t)0x01) /*!< identifier list mode */
 } CAN_FILTER_MODE_T;
 
 /**
@@ -127,8 +129,8 @@ typedef enum
  */
 typedef enum
 {
-    CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), //!< Two 16-bit filters
-    CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01)  //!< One 32-bit filter
+    CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), /*!< Two 16-bit filters */
+    CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01)  /*!< One 32-bit filter */
 } CAN_FILTER_SCALE_T;
 
 /**
@@ -136,8 +138,8 @@ typedef enum
  */
 typedef enum
 {
-    CAN_TYPEID_STD = ((uint32_t)0x00000000), //!< Standard Id
-    CAN_TYPEID_EXT = ((uint32_t)0x00000004)  //!< Extended Id
+    CAN_TYPEID_STD = ((uint32_t)0x00000000), /*!< Standard Id */
+    CAN_TYPEID_EXT = ((uint32_t)0x00000004)  /*!< Extended Id */
 } CAN_TYPEID_T;
 
 /**
@@ -145,8 +147,8 @@ typedef enum
  */
 typedef enum
 {
-    CAN_RTXR_DATA   = ((uint32_t)0x00000000), //!< Data frame
-    CAN_RTXR_REMOTE = ((uint32_t)0x00000002)  //!< Remote frame
+    CAN_RTXR_DATA   = ((uint32_t)0x00000000), /*!< Data frame */
+    CAN_RTXR_REMOTE = ((uint32_t)0x00000002)  /*!< Remote frame */
 } CAN_RTXR_T;
 
 /**
@@ -154,9 +156,9 @@ typedef enum
  */
 typedef enum
 {
-    CAN_TX_MAILBIX_0 = ((uint8_t)0x00), //!< Tx mailbox0
-    CAN_TX_MAILBIX_1 = ((uint8_t)0x01), //!< Tx mailbox1
-    CAN_TX_MAILBIX_2 = ((uint8_t)0x02)  //!< Tx mailbox2
+    CAN_TX_MAILBIX_0 = ((uint8_t)0x00), /*!< Tx mailbox0 */
+    CAN_TX_MAILBIX_1 = ((uint8_t)0x01), /*!< Tx mailbox1 */
+    CAN_TX_MAILBIX_2 = ((uint8_t)0x02)  /*!< Tx mailbox2 */
 } CAN_TX_MAILBIX_T;
 
 /**
@@ -164,8 +166,8 @@ typedef enum
  */
 typedef enum
 {
-    CAN_RX_FIFO_0 = ((uint8_t)0x00), //!< receive FIFO 0
-    CAN_RX_FIFO_1 = ((uint8_t)0x01)  //!< receive FIFO 1
+    CAN_RX_FIFO_0 = ((uint8_t)0x00), /*!< receive FIFO 0 */
+    CAN_RX_FIFO_1 = ((uint8_t)0x01)  /*!< receive FIFO 1 */
 } CAN_RX_FIFO_T;
 
 /**
@@ -173,9 +175,9 @@ typedef enum
  */
 typedef enum
 {
-    CAN_OPERATING_MODE_INIT   = ((uint8_t)0x00), //!< Initialization mode
-    CAN_OPERATING_MODE_NORMAL = ((uint8_t)0x01), //!< Normal mode
-    CAN_OPERATING_MODE_SLEEP  = ((uint8_t)0x02)  //!< sleep mode
+    CAN_OPERATING_MODE_INIT   = ((uint8_t)0x00), /*!< Initialization mode */
+    CAN_OPERATING_MODE_NORMAL = ((uint8_t)0x01), /*!< Normal mode */
+    CAN_OPERATING_MODE_SLEEP  = ((uint8_t)0x02)  /*!< sleep mode */
 } CAN_OPERATING_MODE_T;
 
 /**
@@ -183,20 +185,20 @@ typedef enum
  */
 typedef enum
 {
-    CAN_INT_TXME   = ((uint32_t)0x00000001), //!< Transmit mailbox empty Interrupt
-    CAN_INT_F0MP   = ((uint32_t)0x00000002), //!< FIFO 0 message pending Interrupt
-    CAN_INT_F0FULL = ((uint32_t)0x00000004), //!< FIFO 0 full Interrupt
-    CAN_INT_F0OVR  = ((uint32_t)0x00000008), //!< FIFO 0 overrun Interrupt
-    CAN_INT_F1MP   = ((uint32_t)0x00000010), //!< FIFO 1 message pending Interrupt
-    CAN_INT_F1FULL = ((uint32_t)0x00000020), //!< FIFO 1 full Interrupt
-    CAN_INT_F1OVR  = ((uint32_t)0x00000040), //!< FIFO 1 overrun Interrupt
-    CAN_INT_ERRW   = ((uint32_t)0x00000100), //!< Error warning Interrupt
-    CAN_INT_ERRP   = ((uint32_t)0x00000200), //!< Error passive Interrupt
-    CAN_INT_BOF    = ((uint32_t)0x00000400), //!< Bus-off Interrupt
-    CAN_INT_LEC    = ((uint32_t)0x00000800), //!< Last error record code Interrupt
-    CAN_INT_ERR    = ((uint32_t)0x00008000), //!< Error Interrupt
-    CAN_INT_WUP    = ((uint32_t)0x00010000), //!< Wake-up Interrupt
-    CAN_INT_SLEEP  = ((uint32_t)0x00020000)  //!< Sleep acknowledge Interrupt
+    CAN_INT_TXME   = ((uint32_t)0x00000001), /*!< Transmit mailbox empty Interrupt */
+    CAN_INT_F0MP   = ((uint32_t)0x00000002), /*!< FIFO 0 message pending Interrupt */
+    CAN_INT_F0FULL = ((uint32_t)0x00000004), /*!< FIFO 0 full Interrupt */
+    CAN_INT_F0OVR  = ((uint32_t)0x00000008), /*!< FIFO 0 overrun Interrupt */
+    CAN_INT_F1MP   = ((uint32_t)0x00000010), /*!< FIFO 1 message pending Interrupt */
+    CAN_INT_F1FULL = ((uint32_t)0x00000020), /*!< FIFO 1 full Interrupt */
+    CAN_INT_F1OVR  = ((uint32_t)0x00000040), /*!< FIFO 1 overrun Interrupt */
+    CAN_INT_ERRW   = ((uint32_t)0x00000100), /*!< Error warning Interrupt */
+    CAN_INT_ERRP   = ((uint32_t)0x00000200), /*!< Error passive Interrupt */
+    CAN_INT_BOF    = ((uint32_t)0x00000400), /*!< Bus-off Interrupt */
+    CAN_INT_LEC    = ((uint32_t)0x00000800), /*!< Last error record code Interrupt */
+    CAN_INT_ERR    = ((uint32_t)0x00008000), /*!< Error Interrupt */
+    CAN_INT_WUP    = ((uint32_t)0x00010000), /*!< Wake-up Interrupt */
+    CAN_INT_SLEEP  = ((uint32_t)0x00020000)  /*!< Sleep acknowledge Interrupt */
 } CAN_INT_T;
 
 /**
@@ -205,28 +207,31 @@ typedef enum
 typedef enum
 {
     /** Error flag*/
-    CAN_FLAG_ERRW   = ((uint32_t)0x10F00001),  //!< Error Warning Flag
-    CAN_FLAG_ERRP   = ((uint32_t)0x10F00002),  //!< Error Passive Flag
-    CAN_FLAG_BOF    = ((uint32_t)0x10F00004),  //!< Bus-Off Flag
-    CAN_FLAG_LERRC  = ((uint32_t)0x30F00070),  //!< Last error record code Flag
+    CAN_FLAG_ERRW   = ((uint32_t)0x10F00001),  /*!< Error Warning Flag */
+    CAN_FLAG_ERRP   = ((uint32_t)0x10F00002),  /*!< Error Passive Flag */
+    CAN_FLAG_BOF    = ((uint32_t)0x10F00004),  /*!< Bus-Off Flag */
+    CAN_FLAG_LERRC  = ((uint32_t)0x30F00070),  /*!< Last error record code Flag */
     /** Operating Mode Flags */
-    CAN_FLAG_WUPI   = ((uint32_t)0x31000008),  //!< Wake up Flag
-    CAN_FLAG_SLEEP  = ((uint32_t)0x31000012),  //!< Sleep acknowledge Flag
+    CAN_FLAG_WUPI   = ((uint32_t)0x31000008),  /*!< Wake up Flag */
+    CAN_FLAG_SLEEP  = ((uint32_t)0x31000012),  /*!< Sleep acknowledge Flag */
     /** Receive Flags */
-    CAN_FLAG_F0MP   = ((uint32_t)0x12000003),  //!< FIFO 0 Message Pending Flag
-    CAN_FLAG_F0FULL = ((uint32_t)0x32000008),  //!< FIFO 0 Full Flag
-    CAN_FLAG_F0OVR  = ((uint32_t)0x32000010),  //!< FIFO 0 Overrun Flag
-    CAN_FLAG_F1MP   = ((uint32_t)0x14000003),  //!< FIFO 1 Message Pending Flag
-    CAN_FLAG_F1FULL = ((uint32_t)0x34000008),  //!< FIFO 1 Full Flag
-    CAN_FLAG_F1OVR  = ((uint32_t)0x34000010),  //!< FIFO 1 Overrun Flag
+    CAN_FLAG_F0MP   = ((uint32_t)0x12000003),  /*!< FIFO 0 Message Pending Flag */
+    CAN_FLAG_F0FULL = ((uint32_t)0x32000008),  /*!< FIFO 0 Full Flag */
+    CAN_FLAG_F0OVR  = ((uint32_t)0x32000010),  /*!< FIFO 0 Overrun Flag */
+    CAN_FLAG_F1MP   = ((uint32_t)0x14000003),  /*!< FIFO 1 Message Pending Flag */
+    CAN_FLAG_F1FULL = ((uint32_t)0x34000008),  /*!< FIFO 1 Full Flag */
+    CAN_FLAG_F1OVR  = ((uint32_t)0x34000010),  /*!< FIFO 1 Overrun Flag */
     /** Transmit Flags */
-    CAN_FLAG_REQC0  = ((uint32_t)0x38000001),  //!< Request MailBox0 Flag
-    CAN_FLAG_REQC1  = ((uint32_t)0x38000100),  //!< Request MailBox1 Flag
-    CAN_FLAG_REQC2  = ((uint32_t)0x38010000)   //!< Request MailBox2 Flag
+    CAN_FLAG_REQC0  = ((uint32_t)0x38000001),  /*!< Request MailBox0 Flag */
+    CAN_FLAG_REQC1  = ((uint32_t)0x38000100),  /*!< Request MailBox1 Flag */
+    CAN_FLAG_REQC2  = ((uint32_t)0x38010000)   /*!< Request MailBox2 Flag */
 } CAN_FLAG_T;
 
 /**@} end of group CAN_Enumerations*/
 
+/** @defgroup CAN_Structures Structures
+  @{
+*/
 
 /**
  * @brief    CAN Config structure definition
@@ -237,18 +242,18 @@ typedef enum
  */
 typedef struct
 {
-    uint8_t      autoBusOffManage;    //!< Enable or disable the automatic bus-off management.
-    uint8_t      autoWakeUpMode;      //!< Enable or disable the automatic wake-up mode.
-    uint8_t      nonAutoRetran;       //!< Enable or disable the non-automatic retransmission mode.
-    uint8_t      rxFIFOLockMode;      //!< Enable or disable the Receive FIFO Locked mode.
-    uint8_t      txFIFOPriority;      //!< Enable or disable the transmit FIFO priority.
-    CAN_MODE_T   mode;                //!< Specifies the CAN operating mode.
-    CAN_SJW_T    syncJumpWidth;       /** Specifies the maximum number of time quanta the CAN hardware
-                                       *  is allowed to lengthen or shorten a bit to perform resynchronization.
-                                       */
-    CAN_TIME_SEGMENT1_T timeSegment1; //!< Specifies the number of time quanta in Bit Segment 1.
-    CAN_TIME_SEGMENT2_T timeSegment2; //!< Specifies the number of time quanta in Bit Segment 2.
-    uint16_t            prescaler;    //!< Specifies the length of a time quantum. It can be 1 to 1024.
+    uint8_t      autoBusOffManage;    /*!< Enable or disable the automatic bus-off management. */
+    uint8_t      autoWakeUpMode;      /*!< Enable or disable the automatic wake-up mode. */
+    uint8_t      nonAutoRetran;       /*!< Enable or disable the non-automatic retransmission mode. */
+    uint8_t      rxFIFOLockMode;      /*!< Enable or disable the Receive FIFO Locked mode. */
+    uint8_t      txFIFOPriority;      /*!< Enable or disable the transmit FIFO priority. */
+    CAN_MODE_T   mode;                /*!< Specifies the CAN operating mode. */
+    CAN_SJW_T    syncJumpWidth;       /* Specifies the maximum number of time quanta the CAN hardware
+                                         is allowed to lengthen or shorten a bit to perform resynchronization.
+                                      */
+    CAN_TIME_SEGMENT1_T timeSegment1; /*!< Specifies the number of time quanta in Bit Segment 1. */
+    CAN_TIME_SEGMENT2_T timeSegment2; /*!< Specifies the number of time quanta in Bit Segment 2. */
+    uint16_t            prescaler;    /*!< Specifies the length of a time quantum. It can be 1 to 1024. */
 } CAN_Config_T;
 
 /**
@@ -256,12 +261,12 @@ typedef struct
  */
 typedef struct
 {
-    uint32_t            stdID;         //!< Specifies the standard identifier. It can be 0 to 0x7FF.
-    uint32_t            extID;         //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF.
+    uint32_t            stdID;         /*!< Specifies the standard identifier. It can be 0 to 0x7FF. */
+    uint32_t            extID;         /*!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF. */
     CAN_TYPEID_T        typeID;
     CAN_RTXR_T          remoteTxReq;
-    uint8_t             dataLengthCode;//!< Specifies the data length code.       It can be 0 to 8.
-    uint8_t             data[8];       //!< Specifies the data to be transmitted. It can be 0 to 0xFF.
+    uint8_t             dataLengthCode;/*!< Specifies the data length code.       It can be 0 to 8. */
+    uint8_t             data[8];       /*!< Specifies the data to be transmitted. It can be 0 to 0xFF. */
 } CAN_TxMessage_T;
 
 /**
@@ -269,13 +274,13 @@ typedef struct
  */
 typedef struct
 {
-    uint32_t            stdID;           //!< Specifies the standard identifier. It can be 0 to 0x7FF.
-    uint32_t            extID;           //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF.
+    uint32_t            stdID;           /*!< Specifies the standard identifier. It can be 0 to 0x7FF. */
+    uint32_t            extID;           /*!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF. */
     uint32_t            typeID;
     uint32_t            remoteTxReq;
-    uint8_t             dataLengthCode;  //!< Specifies the data length code.       It can be 0 to 8.
-    uint8_t             data[8];         //!< Specifies the data to be transmitted. It can be 0 to 0xFF.
-    uint8_t             filterMatchIndex;//!< Specifies the filter match index.     It can be 0 to 0xFF.
+    uint8_t             dataLengthCode;  /*!< Specifies the data length code.       It can be 0 to 8. */
+    uint8_t             data[8];         /*!< Specifies the data to be transmitted. It can be 0 to 0xFF. */
+    uint8_t             filterMatchIndex;/*!< Specifies the filter match index.     It can be 0 to 0xFF. */
 } CAN_RxMessage_T;
 
 /**
@@ -283,64 +288,68 @@ typedef struct
  */
 typedef struct
 {
-    uint8_t             filterNumber;      //!< Specifies the filter number. It can be 0 to 13.
-    uint16_t            filterIdHigh;      //!< Specifies the filter identification number.It can be 0 to 0xFFFF.
-    uint16_t            filterIdLow;       //!< Specifies the filter identification number.It can be 0 to 0xFFFF.
-    uint16_t            filterMaskIdHigh;  //!< Specifies the filter mask identification.  It can be 0 to 0xFFFF.
-    uint16_t            filterMaskIdLow;   //!< Specifies the filter mask identification.  It can be 0 to 0xFFFF.
-    uint16_t            filterActivation;  //!< Specifies the filter Activation. It can be ENABLE or DISABLE.
+    uint8_t             filterNumber;      /*!< Specifies the filter number. It can be 0 to 13. */
+    uint16_t            filterIdHigh;      /*!< Specifies the filter identification number.It can be 0 to 0xFFFF. */
+    uint16_t            filterIdLow;       /*!< Specifies the filter identification number.It can be 0 to 0xFFFF. */
+    uint16_t            filterMaskIdHigh;  /*!< Specifies the filter mask identification.  It can be 0 to 0xFFFF. */
+    uint16_t            filterMaskIdLow;   /*!< Specifies the filter mask identification.  It can be 0 to 0xFFFF. */
+    uint16_t            filterActivation;  /*!< Specifies the filter Activation. It can be ENABLE or DISABLE. */
     CAN_FILTER_FIFO_T   filterFIFO;
     CAN_FILTER_MODE_T   filterMode;
     CAN_FILTER_SCALE_T  filterScale;
 } CAN_FilterConfig_T;
 
-/**@} end of group CAN_Structure*/
+/**@} end of group CAN_Structures*/
 
 
-/** @addtogroup CAN_Fuctions Fuctions
+/** @defgroup CAN_Functions Functions
   @{
 */
 
-/** CAN reset and configuration */
-void CAN_Reset(CAN_T *can);
-uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig);
-void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig);
-void CAN_ConfigStructInit(CAN_Config_T *canConfig);
-void CAN_EnableDBGFreeze(CAN_T *can);
-void CAN_DisableDBGFreeze(CAN_T *can);
-void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum);
-
-/** CAN frames transmit */
-uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage);
-uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox);
-void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox);
-
-/** CAN frames receive */
-void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMessage);
-void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber);
-uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber);
-
-/** CAN operation modes */
-uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode);
-uint8_t CAN_SleepMode(CAN_T *can);
-uint8_t CAN_WakeUpMode(CAN_T *can);
-
-/** CAN bus error management */
-uint8_t CAN_ReadLastErrorCode(CAN_T *can);
-uint8_t CAN_ReadRxErrorCounter(CAN_T *can);
-uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can);
-
-/** CAN interrupt and flag */
-void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupt);
-void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupt);
-uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag);
-void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag);
-uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag);
-void CAN_ClearIntFlag(CAN_T *can, CAN_INT_T flag);
-
-/**@} end of group CAN_Fuctions*/
-/**@} end of group CAN_Driver*/
-/**@} end of group Peripherals_Library*/
+/* CAN reset and configuration */
+void CAN_Reset(CAN_T* can);
+uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig);
+#if defined(APM32F10X_CL)
+void CAN_ConfigFilter(CAN_FilterConfig_T* filterConfig);
+void CAN_SlaveStartBank(uint8_t bankNum);
+#else
+void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig);
+#endif
+void CAN_ConfigStructInit(CAN_Config_T* canConfig);
+void CAN_EnableDBGFreeze(CAN_T* can);
+void CAN_DisableDBGFreeze(CAN_T* can);
+
+/* CAN frames transmit */
+uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage);
+uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
+void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
+
+/* CAN frames receive */
+void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMessage);
+void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
+uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
+
+/* CAN operation modes */
+uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode);
+uint8_t CAN_SleepMode(CAN_T* can);
+uint8_t CAN_WakeUpMode(CAN_T* can);
+
+/* CAN bus error management */
+uint8_t CAN_ReadLastErrorCode(CAN_T* can);
+uint8_t CAN_ReadRxErrorCounter(CAN_T* can);
+uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can);
+
+/* CAN interrupt and flag */
+void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupt);
+void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupt);
+uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag);
+void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag);
+uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag);
+void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag);
+
+/**@} end of group CAN_Functions*/
+/**@} end of group CAN_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the CRC firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,13 +26,14 @@
 #ifndef __APM32F10X_CRC_H
 #define __APM32F10X_CRC_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,27 +41,26 @@ extern "C" {
   @{
 */
 
-/** @addtogroup CRC_Fuctions Fuctions
+/** @defgroup CRC_Functions Functions
   @{
 */
 
-/** Reset DATA */
+/* Reset DATA */
 void CRC_ResetDATA(void);
 
-/** Operation functions */
+/* Operation functions */
 uint32_t CRC_CalculateCRC(uint32_t data);
-uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen);
+uint32_t CRC_CalculateBlockCRC(uint32_t* buf, uint32_t bufLen);
 uint32_t CRC_ReadCRC(void);
 void CRC_WriteIDRegister(uint8_t inData);
 uint8_t CRC_ReadIDRegister(void);
 
-/**@} end of group CRC_Fuctions*/
-/**@} end of group CRC_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group CRC_Functions*/
+/**@} end of group CRC_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }
 #endif
 
 #endif /* __APM32F10X_CRC_H */
-

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the DAC firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,13 +26,14 @@
 #ifndef __APM32F10X_DAC_H
 #define __APM32F10X_DAC_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +41,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup DAC_Enumerations Enumerations
+/** @defgroup DAC_Enumerations Enumerations
   @{
 */
 
@@ -84,31 +85,31 @@ typedef enum
  */
 typedef enum
 {
-    DAC_LFSR_MASK_BIT11_1  = 0x00000000, //!< Mask bit[11:1] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_2  = 0x00000100, //!< Mask bit[11:2] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_3  = 0x00000200, //!< Mask bit[11:3] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_4  = 0x00000300, //!< Mask bit[11:4] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_5  = 0x00000400, //!< Mask bit[11:5] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_6  = 0x00000500, //!< Mask bit[11:6] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_7  = 0x00000600, //!< Mask bit[11:7] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_8  = 0x00000700, //!< Mask bit[11:8] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_9  = 0x00000800, //!< Mask bit[11:9] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11_10 = 0x00000900, //!< Mask bit[11:10] of LFSR for noise wave generation
-    DAC_LFSR_MASK_BIT11    = 0x00000A00, //!< Mask bit11 of LFSR for noise wave generation
-    DAC_LFSR_MASK_NONE     = 0x00000B00, //!< Mask none bit of LFSR for noise wave generation
-
-    DAC_TRIANGLE_AMPLITUDE_1    = 0x00000000, //!< Triangle amplitude equal to 1
-    DAC_TRIANGLE_AMPLITUDE_3    = 0x00000100, //!< Triangle amplitude equal to 3
-    DAC_TRIANGLE_AMPLITUDE_7    = 0x00000200, //!< Triangle amplitude equal to 7
-    DAC_TRIANGLE_AMPLITUDE_15   = 0x00000300, //!< Triangle amplitude equal to 15
-    DAC_TRIANGLE_AMPLITUDE_31   = 0x00000400, //!< Triangle amplitude equal to 31
-    DAC_TRIANGLE_AMPLITUDE_63   = 0x00000500, //!< Triangle amplitude equal to 63
-    DAC_TRIANGLE_AMPLITUDE_127  = 0x00000600, //!< Triangle amplitude equal to 127
-    DAC_TRIANGLE_AMPLITUDE_255  = 0x00000700, //!< Triangle amplitude equal to 255
-    DAC_TRIANGLE_AMPLITUDE_511  = 0x00000800, //!< Triangle amplitude equal to 511
-    DAC_TRIANGLE_AMPLITUDE_1023 = 0x00000900, //!< Triangle amplitude equal to 1023
-    DAC_TRIANGLE_AMPLITUDE_2047 = 0x00000A00, //!< Triangle amplitude equal to 2047
-    DAC_TRIANGLE_AMPLITUDE_4095 = 0x00000B00  //!< Triangle amplitude equal to 4095
+    DAC_LFSR_MASK_BIT11_1  = 0x00000000, /*!< Mask bit[11:1] of LFSR for noise wave generation */
+    DAC_LFSR_MASK_BIT11_2  = 0x00000100, /*!< Mask bit[11:2] of LFSR for noise wave generation */
+    DAC_LFSR_MASK_BIT11_3  = 0x00000200, /*!< Mask bit[11:3] of LFSR for noise wave generation */
+    DAC_LFSR_MASK_BIT11_4  = 0x00000300, /*!< Mask bit[11:4] of LFSR for noise wave generation */
+    DAC_LFSR_MASK_BIT11_5  = 0x00000400, /*!< Mask bit[11:5] of LFSR for noise wave generation */
+    DAC_LFSR_MASK_BIT11_6  = 0x00000500, /*!< Mask bit[11:6] of LFSR for noise wave generation */
+    DAC_LFSR_MASK_BIT11_7  = 0x00000600, /*!< Mask bit[11:7] of LFSR for noise wave generation */
+    DAC_LFSR_MASK_BIT11_8  = 0x00000700, /*!< Mask bit[11:8] of LFSR for noise wave generation */
+    DAC_LFSR_MASK_BIT11_9  = 0x00000800, /*!< Mask bit[11:9] of LFSR for noise wave generation */
+    DAC_LFSR_MASK_BIT11_10 = 0x00000900, /*!< Mask bit[11:10] of LFSR for noise wave generation */
+    DAC_LFSR_MASK_BIT11    = 0x00000A00, /*!< Mask bit11 of LFSR for noise wave generation */
+    DAC_LFSR_MASK_NONE     = 0x00000B00, /*!< Mask none bit of LFSR for noise wave generation */
+
+    DAC_TRIANGLE_AMPLITUDE_1    = 0x00000000, /*!< Triangle amplitude equal to 1 */
+    DAC_TRIANGLE_AMPLITUDE_3    = 0x00000100, /*!< Triangle amplitude equal to 3 */
+    DAC_TRIANGLE_AMPLITUDE_7    = 0x00000200, /*!< Triangle amplitude equal to 7 */
+    DAC_TRIANGLE_AMPLITUDE_15   = 0x00000300, /*!< Triangle amplitude equal to 15 */
+    DAC_TRIANGLE_AMPLITUDE_31   = 0x00000400, /*!< Triangle amplitude equal to 31 */
+    DAC_TRIANGLE_AMPLITUDE_63   = 0x00000500, /*!< Triangle amplitude equal to 63 */
+    DAC_TRIANGLE_AMPLITUDE_127  = 0x00000600, /*!< Triangle amplitude equal to 127 */
+    DAC_TRIANGLE_AMPLITUDE_255  = 0x00000700, /*!< Triangle amplitude equal to 255 */
+    DAC_TRIANGLE_AMPLITUDE_511  = 0x00000800, /*!< Triangle amplitude equal to 511 */
+    DAC_TRIANGLE_AMPLITUDE_1023 = 0x00000900, /*!< Triangle amplitude equal to 1023 */
+    DAC_TRIANGLE_AMPLITUDE_2047 = 0x00000A00, /*!< Triangle amplitude equal to 2047 */
+    DAC_TRIANGLE_AMPLITUDE_4095 = 0x00000B00  /*!< Triangle amplitude equal to 4095 */
 } DAC_MASK_AMPLITUDE_SEL_T;
 
 /**
@@ -133,7 +134,7 @@ typedef enum
 /**@} end of group DAC_Enumerations*/
 
 
-/** @addtogroup DAC_Structure Data Structure
+/** @defgroup DAC_Structures Structures
   @{
 */
 
@@ -148,45 +149,45 @@ typedef struct
     DAC_MASK_AMPLITUDE_SEL_T    maskAmplitudeSelect;
 } DAC_Config_T;
 
-/**@} end of group DAC_Structure*/
+/**@} end of group DAC_Structures*/
 
 
-/** @addtogroup DAC_Fuctions Fuctions
+/** @defgroup DAC_Functions Functions
   @{
 */
 
-/** DAC Reset and Configuration */
+/* DAC Reset and Configuration */
 void DAC_Reset(void);
-void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig);
-void DAC_ConfigStructInit(DAC_Config_T *dacConfig);
+void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig);
+void DAC_ConfigStructInit(DAC_Config_T* dacConfig);
 void DAC_Enable(DAC_CHANNEL_T channel);
 void DAC_Disable(DAC_CHANNEL_T channel);
 
-/** DAC channel for DAM */
+/* DAC channel for DAM */
 void DAC_DMA_Enable(DAC_CHANNEL_T channel);
 void DAC_DMA_Disable(DAC_CHANNEL_T channel);
 
-/** DAC channel software trigger */
+/* DAC channel software trigger */
 void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel);
 void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel);
 void DAC_EnableDualSoftwareTrigger(void);
 void DAC_DisableDualSoftwareTrigger(void);
 
-/** DAC channel wave generation */
+/* DAC channel wave generation */
 void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave);
 void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave);
 
-/** DAC set channel data */
+/* DAC set channel data */
 void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data);
 void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data);
 void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1);
 
-/** DAC read data output value */
+/* DAC read data output value */
 uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel);
 
-/**@} end of group DAC_Fuctions*/
-/**@} end of group DAC_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group DAC_Functions*/
+/**@} end of group DAC_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the DBUGMCU firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_DBGMCU_H
 #define __APM32F10X_DBGMCU_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,10 +42,13 @@ extern "C" {
   @{
 */
 
-/** @addtogroup DBGMCU_Enumerations Enumerations
+/** @defgroup DBGMCU_Enumerations Enumerations
   @{
 */
 
+/**
+ * @brief DBGMCU_STOP description
+ */
 enum
 {
     DBGMCU_SLEEP                = ((uint32_t)0x00000001),
@@ -77,7 +82,7 @@ enum
 /**@} end of group DBGMCU_Enumerations*/
 
 
-/** @addtogroup DBGMCU_Fuctions Fuctions
+/** @defgroup DBGMCU_Functions Functions
   @{
 */
 
@@ -86,9 +91,9 @@ uint32_t DBGMCU_ReadREVID(void);
 void DBGMCU_Enable(uint32_t periph);
 void DBGMCU_Disable(uint32_t periph);
 
-/**@} end of group DBGMCU_Fuctions*/
-/**@} end of group DBGMCU_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group DBGMCU_Functions*/
+/**@} end of group DBGMCU_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the DMA firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,13 +26,14 @@
 #ifndef __APM32F10X_DMA_H
 #define __APM32F10X_DMA_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +41,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup DMA_Enumerations Enumerations
+/** @defgroup DMA_Enumerations Enumerations
   @{
 */
 
@@ -245,7 +246,7 @@ typedef enum
 /**@} end of group DMA_Enumerations*/
 
 
-/** @addtogroup DMA_Structure Data Structure
+/** @defgroup DMA_Structures Structures
   @{
 */
 
@@ -267,35 +268,35 @@ typedef struct
     DMA_M2MEN_T                M2M;
 } DMA_Config_T;
 
-/**@} end of group DMA_Structure*/
+/**@} end of group DMA_Structures*/
 
 
-/** @addtogroup DMA_Fuctions Fuctions
+/** @defgroup DMA_Functions Functions
   @{
 */
 
-/** Reset and configuration */
-void DMA_Reset(DMA_Channel_T *channel);
-void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig);
-void DMA_ConfigStructInit(DMA_Config_T *dmaConfig);
-void DMA_Enable(DMA_Channel_T *channel);
-void DMA_Disable(DMA_Channel_T *channel);
+/* Reset and configuration */
+void DMA_Reset(DMA_Channel_T* channel);
+void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig);
+void DMA_ConfigStructInit(DMA_Config_T* dmaConfig);
+void DMA_Enable(DMA_Channel_T* channel);
+void DMA_Disable(DMA_Channel_T* channel);
 
-/** Data number */
-void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber);
-uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel);
+/* Data number */
+void DMA_ConfigDataNumber(DMA_Channel_T* channel, uint16_t dataNumber);
+uint16_t DMA_ReadDataNumber(DMA_Channel_T* channel);
 
-/** Interrupt and flag */
-void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt);
-void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt);
+/* Interrupt and flag */
+void DMA_EnableInterrupt(DMA_Channel_T* channel, uint32_t interrupt);
+void DMA_DisableInterrupt(DMA_Channel_T* channel, uint32_t interrupt);
 uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag);
 void DMA_ClearStatusFlag(uint32_t flag);
 uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag);
 void DMA_ClearIntFlag(uint32_t flag);
 
-/**@} end of group DMA_Fuctions*/
-/**@} end of group DMA_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group DMA_Functions*/
+/**@} end of group DMA_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the prototypes,enumeration and macros for the DMC peripheral
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,13 +26,14 @@
 #ifndef __APM32F10X_DMC_H
 #define __APM32F10X_DMC_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,11 +41,10 @@ extern "C" {
   @{
 */
 
-/** @addtogroup DMC_Enumerations Enumerations
+/** @defgroup DMC_Enumerations Enumerations
   @{
 */
 
-
 /**
  * @brief   Bank Address Width
  */
@@ -261,8 +261,8 @@ typedef enum
  */
 typedef enum
 {
-    DMC_REFRESH_ROW_ONE,        //!< Refresh one row
-    DMC_REFRESH_ROW_ALL,        //!< Refresh all row
+    DMC_REFRESH_ROW_ONE,        /*!< Refresh one row */
+    DMC_REFRESH_ROW_ALL,        /*!< Refresh all row */
 } DMC_REFRESH_T;
 
 /**
@@ -270,8 +270,8 @@ typedef enum
  */
 typedef enum
 {
-    DMC_PRECHARGE_IM,        //!< Immediate precharge
-    DMC_PRECHARGE_DELAY,     //!< Delayed precharge
+    DMC_PRECHARGE_IM,        /*!< Immediate precharge */
+    DMC_PRECHARGE_DELAY,     /*!< Delayed precharge */
 } DMC_PRECHARE_T;
 
 /**
@@ -286,7 +286,7 @@ typedef enum
 /**@} end of group DMC_Enumerations*/
 
 
-/** @addtogroup DMC_Structure Data Structure
+/** @defgroup DMC_Structures Structures
   @{
 */
 
@@ -295,15 +295,15 @@ typedef enum
  */
 typedef struct
 {
-    uint32_t    latencyCAS  : 2;       //!< DMC_CAS_LATENCY_T
-    uint32_t    tRAS        : 4;       //!< DMC_RAS_MINIMUM_T
-    uint32_t    tRCD        : 3;       //!< DMC_DELAY_TIME_T
-    uint32_t    tRP         : 3;       //!< DMC_PRECHARGE_T
-    uint32_t    tWR         : 2;       //!< DMC_NEXT_PRECHARGE_T
-    uint32_t    tARP        : 4;       //!< DMC_AUTO_REFRESH_T
-    uint32_t    tCMD        : 4;       //!< DMC_ATA_CMD_T
-    uint32_t    tXSR        : 9;       //!< auto-refresh commands, can be 0x000 to 0x1FF
-    uint16_t    tRFP        : 16;      //!< Refresh period, can be 0x0000 to 0xFFFF
+    uint32_t    latencyCAS  : 2;       /*!< DMC_CAS_LATENCY_T */
+    uint32_t    tRAS        : 4;       /*!< DMC_RAS_MINIMUM_T */
+    uint32_t    tRCD        : 3;       /*!< DMC_DELAY_TIME_T */
+    uint32_t    tRP         : 3;       /*!< DMC_PRECHARGE_T */
+    uint32_t    tWR         : 2;       /*!< DMC_NEXT_PRECHARGE_T */
+    uint32_t    tARP        : 4;       /*!< DMC_AUTO_REFRESH_T */
+    uint32_t    tCMD        : 4;       /*!< DMC_ATA_CMD_T */
+    uint32_t    tXSR        : 9;       /*!< auto-refresh commands, can be 0x000 to 0x1FF */
+    uint16_t    tRFP        : 16;      /*!< Refresh period, can be 0x0000 to 0xFFFF */
 } DMC_TimingConfig_T;
 
 /**
@@ -311,50 +311,50 @@ typedef struct
  */
 typedef struct
 {
-    DMC_MEMORY_SIZE_T       memorySize;    //!< Memory size(byte)
-    DMC_BANK_WIDTH_T        bankWidth;     //!< Number of bank bits
-    DMC_ROW_WIDTH_T         rowWidth;      //!< Number of row address bits
-    DMC_COL_WIDTH_T         colWidth;      //!< Number of col address bits
-    DMC_CLK_PHASE_T         clkPhase;      //!< Clock phase
-    DMC_TimingConfig_T      timing;        //!< Timing
+    DMC_MEMORY_SIZE_T       memorySize;    /*!< Memory size(byte) */
+    DMC_BANK_WIDTH_T        bankWidth;     /*!< Number of bank bits */
+    DMC_ROW_WIDTH_T         rowWidth;      /*!< Number of row address bits */
+    DMC_COL_WIDTH_T         colWidth;      /*!< Number of col address bits */
+    DMC_CLK_PHASE_T         clkPhase;      /*!< Clock phase */
+    DMC_TimingConfig_T      timing;        /*!< Timing */
 } DMC_Config_T;
 
-/**@} end of group DMC_Structure*/
+/**@} end of group DMC_Structures*/
 
 
-/** @addtogroup DMC_Fuctions Fuctions
+/** @defgroup DMC_Functions Functions
   @{
 */
 
-/** Enable / Disable */
+/* Enable / Disable */
 void DMC_Enable(void);
 void DMC_Disable(void);
 void DMC_EnableInit(void);
 
-/** Global config */
-void DMC_Config(DMC_Config_T *dmcConfig);
-void DMC_ConfigStructInit(DMC_Config_T *dmcConfig);
+/* Global config */
+void DMC_Config(DMC_Config_T* dmcConfig);
+void DMC_ConfigStructInit(DMC_Config_T* dmcConfig);
 
-/** Address */
+/* Address */
 void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth);
 void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth);
 
-/** Timing */
-void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig);
-void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig);
+/* Timing */
+void DMC_ConfigTiming(DMC_TimingConfig_T* timingConfig);
+void DMC_ConfigTimingStructInit(DMC_TimingConfig_T* timingConfig);
 void DMC_ConfigStableTimePowerup(uint16_t stableTime);
 void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num);
 void DMC_ConfigRefreshPeriod(uint16_t period);
 
-/** Refresh mode */
+/* Refresh mode */
 void DMC_EixtSlefRefreshMode(void);
 void DMC_EnterSlefRefreshMode(void);
 
-/** Accelerate Module */
+/* Accelerate Module */
 void DMC_EnableAccelerateModule(void);
 void DMC_DisableAccelerateModule(void);
 
-/** Config */
+/* Config */
 void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num);
 void DMC_EnableUpdateMode(void);
 void DMC_EnterPowerdownMode(void);
@@ -365,12 +365,12 @@ void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize);
 void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase);
 void DMC_ConfigWRAPB(DMC_WRPB_T burst);
 
-/** read flag */
+/* read flag */
 uint8_t DMC_ReadSelfRefreshStatus(void);
 
-/**@} end of group DMC_Fuctions*/
+/**@} end of group DMC_Functions*/
 /**@} end of group DMC_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group APM32F10x_StdPeriphDriver*/
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the EINT firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_EINT_H
 #define __APM32F10X_EINT_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +42,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup EINT_Enumerations Enumerations
+/** @defgroup EINT_Enumerations Enumerations
   @{
 */
 
@@ -65,32 +67,32 @@ typedef enum
 
 typedef enum
 {
-    EINT_LINENONE = 0x00000,  //!<No interrupt selected >
-    EINT_LINE_0   = 0x00001,  //!< External interrupt line 0
-    EINT_LINE_1   = 0x00002,  //!< External interrupt line 1
-    EINT_LINE_2   = 0x00004,  //!< External interrupt line 2
-    EINT_LINE_3   = 0x00008,  //!< External interrupt line 3
-    EINT_LINE_4   = 0x00010,  //!< External interrupt line 4
-    EINT_LINE_5   = 0x00020,  //!< External interrupt line 5
-    EINT_LINE_6   = 0x00040,  //!< External interrupt line 6
-    EINT_LINE_7   = 0x00080,  //!< External interrupt line 7
-    EINT_LINE_8   = 0x00100,  //!< External interrupt line 8
-    EINT_LINE_9   = 0x00200,  //!< External interrupt line 9
-    EINT_LINE_10  = 0x00400,  //!< External interrupt line 10
-    EINT_LINE_11  = 0x00800,  //!< External interrupt line 11
-    EINT_LINE_12  = 0x01000,  //!< External interrupt line 12
-    EINT_LINE_13  = 0x02000,  //!< External interrupt line 13
-    EINT_LINE_14  = 0x04000,  //!< External interrupt line 14
-    EINT_LINE_15  = 0x08000,  //!< External interrupt line 15
-    EINT_LINE_16  = 0x10000,  //!< External interrupt line 16 Connected to the PVD Output
-    EINT_LINE_17  = 0x20000,  //!< External interrupt line 17 Connected to the RTC Alarm event
-    EINT_LINE_18  = 0x40000,  //!< External interrupt line 18 Connected to the USB Device
+    EINT_LINENONE = 0x00000,  /*!<No interrupt selected > */
+    EINT_LINE_0   = 0x00001,  /*!< External interrupt line 0 */
+    EINT_LINE_1   = 0x00002,  /*!< External interrupt line 1 */
+    EINT_LINE_2   = 0x00004,  /*!< External interrupt line 2 */
+    EINT_LINE_3   = 0x00008,  /*!< External interrupt line 3 */
+    EINT_LINE_4   = 0x00010,  /*!< External interrupt line 4 */
+    EINT_LINE_5   = 0x00020,  /*!< External interrupt line 5 */
+    EINT_LINE_6   = 0x00040,  /*!< External interrupt line 6 */
+    EINT_LINE_7   = 0x00080,  /*!< External interrupt line 7 */
+    EINT_LINE_8   = 0x00100,  /*!< External interrupt line 8 */
+    EINT_LINE_9   = 0x00200,  /*!< External interrupt line 9 */
+    EINT_LINE_10  = 0x00400,  /*!< External interrupt line 10 */
+    EINT_LINE_11  = 0x00800,  /*!< External interrupt line 11 */
+    EINT_LINE_12  = 0x01000,  /*!< External interrupt line 12 */
+    EINT_LINE_13  = 0x02000,  /*!< External interrupt line 13 */
+    EINT_LINE_14  = 0x04000,  /*!< External interrupt line 14 */
+    EINT_LINE_15  = 0x08000,  /*!< External interrupt line 15 */
+    EINT_LINE_16  = 0x10000,  /*!< External interrupt line 16 Connected to the PVD Output */
+    EINT_LINE_17  = 0x20000,  /*!< External interrupt line 17 Connected to the RTC Alarm event */
+    EINT_LINE_18  = 0x40000,  /*!< External interrupt line 18 Connected to the USB Device */
 } EINT_LINE_T;
 
 /**@} end of group EINT_Enumerations*/
 
 
-/** @addtogroup EINT_Structure Data Structure
+/** @defgroup EINT_Structures Structures
   @{
 */
 
@@ -105,31 +107,31 @@ typedef struct
     uint8_t         lineCmd;
 } EINT_Config_T;
 
-/**@} end of group EINT_Structure*/
+/**@} end of group EINT_Structures*/
 
 
-/** @addtogroup EINT_Fuctions Fuctions
+/** @defgroup EINT_Functions Functions
   @{
 */
 
-/** Reset and configuration */
+/* Reset and configuration */
 void EINT_Reset(void);
-void EINT_Config(EINT_Config_T *eintConfig);
-void EINT_ConfigStructInit(EINT_Config_T *eintConfig);
+void EINT_Config(EINT_Config_T* eintConfig);
+void EINT_ConfigStructInit(EINT_Config_T* eintConfig);
 
-/** Interrupt and flag */
+/* Interrupt and flag */
 void EINT_SelectSWInterrupt(uint32_t line);
 uint8_t EINT_ReadStatusFlag(EINT_LINE_T line);
 void EINT_ClearStatusFlag(uint32_t line);
 uint8_t EINT_ReadIntFlag(EINT_LINE_T line);
 void EINT_ClearIntFlag(uint32_t line);
 
-/**@} end of group EINT_Fuctions*/
-/**@} end of group EINT_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group EINT_Functions*/
+/**@} end of group EINT_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver*/
 
-#ifdef __cplusplus
+#ifdef __APM32F10X_cplusplus
 }
 #endif
 
-#endif /* __APM32F10XEINT_H */
+#endif /* __EINT_H */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h

@@ -27,7 +27,7 @@
 #define __APM32F10X_EMMC_H
 
 #ifdef __cplusplus
-extern "C" {
+  extern "C" {
 #endif
 
 #include "apm32f10x.h"
@@ -276,8 +276,8 @@ typedef struct
     EMMC_WAITE_SIGNAL_T         waiteSignal;
     EMMC_EXTENDEN_MODE_T        extendedMode;
     EMMC_WRITE_BURST_T          writeBurst;
-    EMMC_NORSRAMTimingConfig_T   *readWriteTimingStruct;
-    EMMC_NORSRAMTimingConfig_T   *writeTimingStruct;
+    EMMC_NORSRAMTimingConfig_T*   readWriteTimingStruct;
+    EMMC_NORSRAMTimingConfig_T*   writeTimingStruct;
 } EMMC_NORSRAMConfig_T;
 
 /**
@@ -303,8 +303,8 @@ typedef struct
     EMMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize;
     uint32_t                  TCLRSetupTime;
     uint32_t                  TARSetupTime;
-    EMMC_NAND_PCCARDTimingConfig_T *commonSpaceTimingStruct;
-    EMMC_NAND_PCCARDTimingConfig_T *attributeSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
 } EMMC_NANDConfig_T;
 
 /**
@@ -315,9 +315,9 @@ typedef struct
     EMMC_WAIT_FEATURE_T waitFeature;
     uint32_t            TCLRSetupTime;
     uint32_t            TARSetupTime;
-    EMMC_NAND_PCCARDTimingConfig_T *commonSpaceTimingStruct;
-    EMMC_NAND_PCCARDTimingConfig_T *attributeSpaceTimingStruct;
-    EMMC_NAND_PCCARDTimingConfig_T *IOSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct;
 } EMMC_PCCARDConfig_T;
 
 /**@} end of group EMMC_Structure*/
@@ -332,12 +332,12 @@ void EMMC_ResetNAND(EMMC_BANK_NAND_T bank);
 void EMMC_ResetPCCard(void);
 
 /** EMMC Configuration */
-void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig);
-void EMMC_ConfigNAND(EMMC_NANDConfig_T *emmcNANDConfig);
-void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T *emmcPCCardConfig);
-void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig);
-void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T *emmcNANDConfig);
-void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T *emmcPCCardConfig);
+void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
+void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig);
+void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig);
+void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
+void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig);
+void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig);
 
 /** EMMC bank control */
 void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank);

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the FMC firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_FMC_H
 #define __APM32F10X_FMC_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +42,86 @@ extern "C" {
   @{
 */
 
-/** @addtogroup FMC_Enumerations Enumerations
+/** @defgroup FMC_Macros Macros
+  @{
+*/
+
+/* Macros description */
+
+/* Values for APM32 Low and Medium density devices */
+#define FLASH_WRP_PAGE_0_3               ((uint32_t)BIT0) /*!< Write protection of page 0 to 3 */
+#define FLASH_WRP_PAGE_4_7               ((uint32_t)BIT1) /*!< Write protection of page 4 to 7 */
+#define FLASH_WRP_PAGE_8_11              ((uint32_t)BIT2) /*!< Write protection of page 8 to 11 */
+#define FLASH_WRP_PAGE_12_15             ((uint32_t)BIT3) /*!< Write protection of page 12 to 15 */
+#define FLASH_WRP_PAGE_16_19             ((uint32_t)BIT4) /*!< Write protection of page 16 to 19 */
+#define FLASH_WRP_PAGE_20_23             ((uint32_t)BIT5) /*!< Write protection of page 20 to 23 */
+#define FLASH_WRP_PAGE_24_27             ((uint32_t)BIT6) /*!< Write protection of page 24 to 27 */
+#define FLASH_WRP_PAGE_28_31             ((uint32_t)BIT7) /*!< Write protection of page 28 to 31 */
+
+/* Values for APM32 Medium-density devices */
+#define FLASH_WRP_PAGE_32_35             ((uint32_t)BIT8)  /*!< Write protection of page 32 to 35 */
+#define FLASH_WRP_PAGE_36_39             ((uint32_t)BIT9)  /*!< Write protection of page 36 to 39 */
+#define FLASH_WRP_PAGE_40_43             ((uint32_t)BIT10) /*!< Write protection of page 40 to 43 */
+#define FLASH_WRP_PAGE_44_47             ((uint32_t)BIT11) /*!< Write protection of page 44 to 47 */
+#define FLASH_WRP_PAGE_48_51             ((uint32_t)BIT12) /*!< Write protection of page 48 to 51 */
+#define FLASH_WRP_PAGE_52_55             ((uint32_t)BIT13) /*!< Write protection of page 52 to 55 */
+#define FLASH_WRP_PAGE_56_59             ((uint32_t)BIT14) /*!< Write protection of page 56 to 59 */
+#define FLASH_WRP_PAGE_60_63             ((uint32_t)BIT15) /*!< Write protection of page 60 to 63 */
+#define FLASH_WRP_PAGE_64_67             ((uint32_t)BIT16) /*!< Write protection of page 64 to 67 */
+#define FLASH_WRP_PAGE_68_71             ((uint32_t)BIT17) /*!< Write protection of page 68 to 71 */
+#define FLASH_WRP_PAGE_72_75             ((uint32_t)BIT18) /*!< Write protection of page 72 to 75 */
+#define FLASH_WRP_PAGE_76_79             ((uint32_t)BIT19) /*!< Write protection of page 76 to 79 */
+#define FLASH_WRP_PAGE_80_83             ((uint32_t)BIT20) /*!< Write protection of page 80 to 83 */
+#define FLASH_WRP_PAGE_84_87             ((uint32_t)BIT21) /*!< Write protection of page 84 to 87 */
+#define FLASH_WRP_PAGE_88_91             ((uint32_t)BIT22) /*!< Write protection of page 88 to 91 */
+#define FLASH_WRP_PAGE_92_95             ((uint32_t)BIT23) /*!< Write protection of page 92 to 95 */
+#define FLASH_WRP_PAGE_96_99             ((uint32_t)BIT24) /*!< Write protection of page 96 to 99 */
+#define FLASH_WRP_PAGE_100_103           ((uint32_t)BIT25) /*!< Write protection of page 100 to 103 */
+#define FLASH_WRP_PAGE_104_107           ((uint32_t)BIT26) /*!< Write protection of page 104 to 107 */
+#define FLASH_WRP_PAGE_108_111           ((uint32_t)BIT27) /*!< Write protection of page 108 to 111 */
+#define FLASH_WRP_PAGE_112_115           ((uint32_t)BIT28) /*!< Write protection of page 112 to 115 */
+#define FLASH_WRP_PAGE_116_119           ((uint32_t)BIT29) /*!< Write protection of page 116 to 119 */
+#define FLASH_WRP_PAGE_120_123           ((uint32_t)BIT30) /*!< Write protection of page 120 to 123 */
+#define FLASH_WRP_PAGE_124_127           ((uint32_t)BIT31) /*!< Write protection of page 124 to 127 */
+
+/* Values only for APM32 High-density devices */
+#define FLASH_WRP_PAGE_0_1             ((uint32_t)BIT0)  /*!< Write protection of page 0 to 1 */
+#define FLASH_WRP_PAGE_2_3             ((uint32_t)BIT1)  /*!< Write protection of page 2 to 3 */
+#define FLASH_WRP_PAGE_4_5             ((uint32_t)BIT2)  /*!< Write protection of page 4 to 5 */
+#define FLASH_WRP_PAGE_6_7             ((uint32_t)BIT3)  /*!< Write protection of page 6 to 7 */
+#define FLASH_WRP_PAGE_8_9             ((uint32_t)BIT4)  /*!< Write protection of page 8 to 9 */
+#define FLASH_WRP_PAGE_10_11           ((uint32_t)BIT5)  /*!< Write protection of page 10 to 11 */
+#define FLASH_WRP_PAGE_12_13           ((uint32_t)BIT6)  /*!< Write protection of page 12 to 13 */
+#define FLASH_WRP_PAGE_14_15           ((uint32_t)BIT7)  /*!< Write protection of page 14 to 15 */
+#define FLASH_WRP_PAGE_16_17           ((uint32_t)BIT8)  /*!< Write protection of page 16 to 17 */
+#define FLASH_WRP_PAGE_18_19           ((uint32_t)BIT9)  /*!< Write protection of page 18 to 19 */
+#define FLASH_WRP_PAGE_20_21           ((uint32_t)BIT10) /*!< Write protection of page 20 to 21 */
+#define FLASH_WRP_PAGE_22_23           ((uint32_t)BIT11) /*!< Write protection of page 22 to 23 */
+#define FLASH_WRP_PAGE_24_25           ((uint32_t)BIT12) /*!< Write protection of page 24 to 25 */
+#define FLASH_WRP_PAGE_26_27           ((uint32_t)BIT13) /*!< Write protection of page 26 to 27 */
+#define FLASH_WRP_PAGE_28_29           ((uint32_t)BIT14) /*!< Write protection of page 28 to 29 */
+#define FLASH_WRP_PAGE_30_31           ((uint32_t)BIT15) /*!< Write protection of page 30 to 31 */
+#define FLASH_WRP_PAGE_32_33           ((uint32_t)BIT16) /*!< Write protection of page 32 to 33 */
+#define FLASH_WRP_PAGE_34_35           ((uint32_t)BIT17) /*!< Write protection of page 34 to 35 */
+#define FLASH_WRP_PAGE_36_37           ((uint32_t)BIT18) /*!< Write protection of page 36 to 37 */
+#define FLASH_WRP_PAGE_38_39           ((uint32_t)BIT19) /*!< Write protection of page 38 to 39 */
+#define FLASH_WRP_PAGE_40_41           ((uint32_t)BIT20) /*!< Write protection of page 40 to 41 */
+#define FLASH_WRP_PAGE_42_43           ((uint32_t)BIT21) /*!< Write protection of page 42 to 43 */
+#define FLASH_WRP_PAGE_44_45           ((uint32_t)BIT22) /*!< Write protection of page 44 to 45 */
+#define FLASH_WRP_PAGE_46_47           ((uint32_t)BIT23) /*!< Write protection of page 46 to 47 */
+#define FLASH_WRP_PAGE_48_49           ((uint32_t)BIT24) /*!< Write protection of page 48 to 49 */
+#define FLASH_WRP_PAGE_50_51           ((uint32_t)BIT25) /*!< Write protection of page 50 to 51 */
+#define FLASH_WRP_PAGE_52_53           ((uint32_t)BIT26) /*!< Write protection of page 52 to 53 */
+#define FLASH_WRP_PAGE_54_55           ((uint32_t)BIT27) /*!< Write protection of page 54 to 55 */
+#define FLASH_WRP_PAGE_56_57           ((uint32_t)BIT28) /*!< Write protection of page 56 to 57 */
+#define FLASH_WRP_PAGE_58_59           ((uint32_t)BIT29) /*!< Write protection of page 58 to 59 */
+#define FLASH_WRP_PAGE_60_61           ((uint32_t)BIT30) /*!< Write protection of page 60 to 61 */
+#define FLASH_WRP_PAGE_62_127          ((uint32_t)BIT31) /*!< Write protection of page 62 to 127 */
+#define FMC_WRP_PAGE_ALL               ((uint32_t)0xFFFFFFFF) /*!< Write protection of page all */
+
+/**@} end of group FMC_Macros*/
+
+/** @defgroup FMC_Enumerations Enumerations
   @{
 */
 
@@ -59,11 +140,11 @@ typedef enum
  */
 typedef enum
 {
-    FMC_STATUS_BUSY = 1,   //!< flash busy
-    FMC_STATUS_ERROR_PG,   //!< flash programming error
-    FMC_STATUS_ERROR_WRP,  //!< flash write protection error
-    FMC_STATUS_COMPLETE,   //!< flash operation complete
-    FMC_STATUS_TIMEOUT     //!< flash time out
+    FMC_STATUS_BUSY = 1,   /*!< flash busy */
+    FMC_STATUS_ERROR_PG,   /*!< flash programming error */
+    FMC_STATUS_ERROR_WRP,  /*!< flash write protection error */
+    FMC_STATUS_COMPLETE,   /*!< flash operation complete */
+    FMC_STATUS_TIMEOUT     /*!< flash time out */
 } FMC_STATUS_T;
 
 /**
@@ -107,95 +188,16 @@ typedef enum
  */
 typedef enum
 {
-    FMC_FLAG_BUSY = 0x00000001,  //!< FMC Busy flag
-    FMC_FLAG_OC   = 0x00000020,  //!< FMC End of Operation flag
-    FMC_FLAG_PE   = 0x00000004,  //!< FMC Program error flag
-    FMC_FLAG_WPE  = 0x00000010,  //!< FMC Write protected error flag
-    FMC_FLAG_OBE  = 0x10000001,  //!< FMC Option Byte error flag
+    FMC_FLAG_BUSY = 0x00000001,  /*!< FMC Busy flag */
+    FMC_FLAG_OC   = 0x00000020,  /*!< FMC End of Operation flag */
+    FMC_FLAG_PE   = 0x00000004,  /*!< FMC Program error flag */
+    FMC_FLAG_WPE  = 0x00000010,  /*!< FMC Write protected error flag */
+    FMC_FLAG_OBE  = 0x10000001,  /*!< FMC Option Byte error flag */
 } FMC_FLAG_T;
 
 /**@} end of group FMC_Enumerations*/
 
-/** @addtogroup FMC_Macros Macros
-  @{
-*/
-
-/** Macros description */
-
-/** Values for APM32 Low and Medium density devices */
-#define FLASH_WRP_PAGE_0_3               ((uint32_t)BIT0) //!< Write protection of page 0 to 3
-#define FLASH_WRP_PAGE_4_7               ((uint32_t)BIT1) //!< Write protection of page 4 to 7
-#define FLASH_WRP_PAGE_8_11              ((uint32_t)BIT2) //!< Write protection of page 8 to 11
-#define FLASH_WRP_PAGE_12_15             ((uint32_t)BIT3) //!< Write protection of page 12 to 15
-#define FLASH_WRP_PAGE_16_19             ((uint32_t)BIT4) //!< Write protection of page 16 to 19
-#define FLASH_WRP_PAGE_20_23             ((uint32_t)BIT5) //!< Write protection of page 20 to 23
-#define FLASH_WRP_PAGE_24_27             ((uint32_t)BIT6) //!< Write protection of page 24 to 27
-#define FLASH_WRP_PAGE_28_31             ((uint32_t)BIT7) //!< Write protection of page 28 to 31
-
-/** Values for APM32 Medium-density devices */
-#define FLASH_WRP_PAGE_32_35             ((uint32_t)BIT8)  //!< Write protection of page 32 to 35
-#define FLASH_WRP_PAGE_36_39             ((uint32_t)BIT9)  //!< Write protection of page 36 to 39
-#define FLASH_WRP_PAGE_40_43             ((uint32_t)BIT10) //!< Write protection of page 40 to 43
-#define FLASH_WRP_PAGE_44_47             ((uint32_t)BIT11) //!< Write protection of page 44 to 47
-#define FLASH_WRP_PAGE_48_51             ((uint32_t)BIT12) //!< Write protection of page 48 to 51
-#define FLASH_WRP_PAGE_52_55             ((uint32_t)BIT13) //!< Write protection of page 52 to 55
-#define FLASH_WRP_PAGE_56_59             ((uint32_t)BIT14) //!< Write protection of page 56 to 59
-#define FLASH_WRP_PAGE_60_63             ((uint32_t)BIT15) //!< Write protection of page 60 to 63
-#define FLASH_WRP_PAGE_64_67             ((uint32_t)BIT16) //!< Write protection of page 64 to 67
-#define FLASH_WRP_PAGE_68_71             ((uint32_t)BIT17) //!< Write protection of page 68 to 71
-#define FLASH_WRP_PAGE_72_75             ((uint32_t)BIT18) //!< Write protection of page 72 to 75
-#define FLASH_WRP_PAGE_76_79             ((uint32_t)BIT19) //!< Write protection of page 76 to 79
-#define FLASH_WRP_PAGE_80_83             ((uint32_t)BIT20) //!< Write protection of page 80 to 83
-#define FLASH_WRP_PAGE_84_87             ((uint32_t)BIT21) //!< Write protection of page 84 to 87
-#define FLASH_WRP_PAGE_88_91             ((uint32_t)BIT22) //!< Write protection of page 88 to 91
-#define FLASH_WRP_PAGE_92_95             ((uint32_t)BIT23) //!< Write protection of page 92 to 95
-#define FLASH_WRP_PAGE_96_99             ((uint32_t)BIT24) //!< Write protection of page 96 to 99
-#define FLASH_WRP_PAGE_100_103           ((uint32_t)BIT25) //!< Write protection of page 100 to 103
-#define FLASH_WRP_PAGE_104_107           ((uint32_t)BIT26) //!< Write protection of page 104 to 107
-#define FLASH_WRP_PAGE_108_111           ((uint32_t)BIT27) //!< Write protection of page 108 to 111
-#define FLASH_WRP_PAGE_112_115           ((uint32_t)BIT28) //!< Write protection of page 112 to 115
-#define FLASH_WRP_PAGE_116_119           ((uint32_t)BIT29) //!< Write protection of page 116 to 119
-#define FLASH_WRP_PAGE_120_123           ((uint32_t)BIT30) //!< Write protection of page 120 to 123
-#define FLASH_WRP_PAGE_124_127           ((uint32_t)BIT31) //!< Write protection of page 124 to 127
-
-/** Values only for APM32 High-density devices */
-#define FLASH_WRP_PAGE_0_1             ((uint32_t)BIT0)  //!< Write protection of page 0 to 1
-#define FLASH_WRP_PAGE_2_3             ((uint32_t)BIT1)  //!< Write protection of page 2 to 3
-#define FLASH_WRP_PAGE_4_5             ((uint32_t)BIT2)  //!< Write protection of page 4 to 5
-#define FLASH_WRP_PAGE_6_7             ((uint32_t)BIT3)  //!< Write protection of page 6 to 7
-#define FLASH_WRP_PAGE_8_9             ((uint32_t)BIT4)  //!< Write protection of page 8 to 9
-#define FLASH_WRP_PAGE_10_11           ((uint32_t)BIT5)  //!< Write protection of page 10 to 11
-#define FLASH_WRP_PAGE_12_13           ((uint32_t)BIT6)  //!< Write protection of page 12 to 13
-#define FLASH_WRP_PAGE_14_15           ((uint32_t)BIT7)  //!< Write protection of page 14 to 15
-#define FLASH_WRP_PAGE_16_17           ((uint32_t)BIT8)  //!< Write protection of page 16 to 17
-#define FLASH_WRP_PAGE_18_19           ((uint32_t)BIT9)  //!< Write protection of page 18 to 19
-#define FLASH_WRP_PAGE_20_21           ((uint32_t)BIT10) //!< Write protection of page 20 to 21
-#define FLASH_WRP_PAGE_22_23           ((uint32_t)BIT11) //!< Write protection of page 22 to 23
-#define FLASH_WRP_PAGE_24_25           ((uint32_t)BIT12) //!< Write protection of page 24 to 25
-#define FLASH_WRP_PAGE_26_27           ((uint32_t)BIT13) //!< Write protection of page 26 to 27
-#define FLASH_WRP_PAGE_28_29           ((uint32_t)BIT14) //!< Write protection of page 28 to 29
-#define FLASH_WRP_PAGE_30_31           ((uint32_t)BIT15) //!< Write protection of page 30 to 31
-#define FLASH_WRP_PAGE_32_33           ((uint32_t)BIT16) //!< Write protection of page 32 to 33
-#define FLASH_WRP_PAGE_34_35           ((uint32_t)BIT17) //!< Write protection of page 34 to 35
-#define FLASH_WRP_PAGE_36_37           ((uint32_t)BIT18) //!< Write protection of page 36 to 37
-#define FLASH_WRP_PAGE_38_39           ((uint32_t)BIT19) //!< Write protection of page 38 to 39
-#define FLASH_WRP_PAGE_40_41           ((uint32_t)BIT20) //!< Write protection of page 40 to 41
-#define FLASH_WRP_PAGE_42_43           ((uint32_t)BIT21) //!< Write protection of page 42 to 43
-#define FLASH_WRP_PAGE_44_45           ((uint32_t)BIT22) //!< Write protection of page 44 to 45
-#define FLASH_WRP_PAGE_46_47           ((uint32_t)BIT23) //!< Write protection of page 46 to 47
-#define FLASH_WRP_PAGE_48_49           ((uint32_t)BIT24) //!< Write protection of page 48 to 49
-#define FLASH_WRP_PAGE_50_51           ((uint32_t)BIT25) //!< Write protection of page 50 to 51
-#define FLASH_WRP_PAGE_52_53           ((uint32_t)BIT26) //!< Write protection of page 52 to 53
-#define FLASH_WRP_PAGE_54_55           ((uint32_t)BIT27) //!< Write protection of page 54 to 55
-#define FLASH_WRP_PAGE_56_57           ((uint32_t)BIT28) //!< Write protection of page 56 to 57
-#define FLASH_WRP_PAGE_58_59           ((uint32_t)BIT29) //!< Write protection of page 58 to 59
-#define FLASH_WRP_PAGE_60_61           ((uint32_t)BIT30) //!< Write protection of page 60 to 61
-#define FLASH_WRP_PAGE_62_127          ((uint32_t)BIT31) //!< Write protection of page 62 to 127
-#define FMC_WRP_PAGE_ALL               ((uint32_t)0xFFFFFFFF) //!< Write protection of page all */
-
-/**@} end of group FMC_Macros*/
-
-/** @addtogroup FMC_Structure Data Structure
+/** @defgroup FMC_Structures Structures
   @{
 */
 
@@ -211,52 +213,52 @@ typedef struct
 
 /**@} end of group FMC_Structure*/
 
-/** @addtogroup FMC_Fuctions Fuctions
+/** @defgroup FMC_Functions Functions
   @{
 */
 
-/** Initialization and Configuration */
+/* Initialization and Configuration */
 void FMC_ConfigLatency(FMC_LATENCY_T latency);
 void FMC_EnableHalfCycleAccess(void);
 void FMC_DisableHalfCycleAccess(void);
 void FMC_EnablePrefetchBuffer(void);
 void FMC_DisablePrefetchBuffer(void);
 
-/** Lock management */
+/* Lock management */
 void FMC_Unlock(void);
 void FMC_Lock(void);
 
-/** Erase management */
+/* Erase management */
 FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr);
 FMC_STATUS_T FMC_EraseAllPage(void);
 FMC_STATUS_T FMC_EraseOptionBytes(void);
 
-/** Read Write management */
+/* Read Write management */
 FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data);
 FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data);
 FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data);
 FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page);
 FMC_STATUS_T FMC_EnableReadOutProtection(void);
 FMC_STATUS_T FMC_DisableReadOutProtection(void);
-FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T *userConfig);
+FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig);
 uint32_t FMC_ReadUserOptionByte(void);
 uint32_t FMC_ReadOptionByteWriteProtection(void);
 uint8_t FMC_GetReadProtectionStatus(void);
 uint8_t FMC_ReadPrefetchBufferStatus(void);
 
-/** Interrupts and flags */
+/* Interrupts and flags */
 void FMC_EnableInterrupt(FMC_INT_T interrupt);
 void FMC_DisableInterrupt(FMC_INT_T interrupt);
 uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag);
 void FMC_ClearStatusFlag(uint32_t flag);
 
-/** Status management */
+/* Status management */
 FMC_STATUS_T FMC_ReadStatus(void);
 FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut);
 
-/**@} end of group FMC_Fuctions*/
+/**@} end of group FMC_Functions*/
 /**@} end of group FMC_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group APM32F10x_StdPeriphDriver*/
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the GPIO firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_GPIO_H
 #define __APM32F10X_GPIO_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +42,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup GPIO_Enumerations Enumerations
+/** @defgroup GPIO_Enumerations Enumerations
   @{
 */
 
@@ -50,7 +52,7 @@ extern "C" {
 typedef enum
 {
     GPIO_SPEED_10MHz = 1,
-    GPIO_SPEED_20MHz,
+    GPIO_SPEED_2MHz,
     GPIO_SPEED_50MHz
 } GPIO_SPEED_T;
 
@@ -59,14 +61,14 @@ typedef enum
  */
 typedef enum
 {
-    GPIO_MODE_ANALOG      = 0x0,   //!< Analog mode
-    GPIO_MODE_IN_FLOATING = 0x04,  //!< Floating input
-    GPIO_MODE_IN_PD       = 0x28,  //!< Input with pull-down
-    GPIO_MODE_IN_PU       = 0x48,  //!< Input with pull-up
-    GPIO_MODE_OUT_PP      = 0x80,  //!< General purpose output push-pull
-    GPIO_MODE_OUT_OD      = 0x84,  //!< General purpose output Open-drain
-    GPIO_MODE_AF_PP       = 0x88,  //!< Alternate function output Push-pull
-    GPIO_MODE_AF_OD       = 0x8C,  //!< Alternate function output Open-drain
+    GPIO_MODE_ANALOG      = 0x0,   /*!< Analog mode */
+    GPIO_MODE_IN_FLOATING = 0x04,  /*!< Floating input */
+    GPIO_MODE_IN_PD       = 0x28,  /*!< Input with pull-down */
+    GPIO_MODE_IN_PU       = 0x48,  /*!< Input with pull-up */
+    GPIO_MODE_OUT_PP      = 0x80,  /*!< General purpose output push-pull */
+    GPIO_MODE_OUT_OD      = 0x84,  /*!< General purpose output Open-drain */
+    GPIO_MODE_AF_PP       = 0x88,  /*!< Alternate function output Push-pull */
+    GPIO_MODE_AF_OD       = 0x8C,  /*!< Alternate function output Open-drain */
 } GPIO_MODE_T;
 
 /**
@@ -140,6 +142,7 @@ typedef enum
     GPIO_NO_REMAP_TMR5CH4_LSI   = 0x00001010,
     GPIO_REMAP_TMR5CH4_LSI      = 0x00001011,
 
+#if !defined(APM32F10X_CL)
     GPIO_NO_REMAP_ADC1_ETRGINJ  = 0x00001110,
     GPIO_REMAP_ADC1_ETRGINJ     = 0x00001111,
 
@@ -152,9 +155,15 @@ typedef enum
     GPIO_NO_REMAP_ADC2_ETRGREG  = 0x00001410,
     GPIO_REMAP_ADC2_ETRGREG     = 0x00001411,
 
+    GPIO_NO_REMAP_ETH           = 0x00001510,
+    GPIO_REMAP_ETH              = 0x00001511,
+
     GPIO_NO_REMAP_CAN2          = 0x00001610,
     GPIO_REMAP_CAN2             = 0x00001611,
 
+    GPIO_REMAP_MII              = 0x00001710,
+    GPIO_REMAP_RMII             = 0x00001711,
+
     GPIO_NO_REMAP_SWJ           = 0x00001870,
     GPIO_REMAP_SWJ_NOJTRST      = 0x00001871,
     GPIO_REMAP_SWJ_JTAGDISABLE  = 0x00001872,
@@ -162,6 +171,31 @@ typedef enum
 
     GPIO_NO_REMAP_EMMC_NADV     = 0x00010A10,
     GPIO_REMAP_EMMC_NADV        = 0x00010A11,
+
+#else /* APM32F10X_CL */
+    GPIO_NO_REMAP_ETH_MAC       = 0x00001510,
+    GPIO_REMAP_ETH_MAC          = 0x00001511,
+
+    GPIO_NO_REMAP_CAN2          = 0x00001610,
+    GPIO_REMAP_CAN2             = 0x00001611,
+
+    GPIO_REMAP_MACEISEL_MII     = 0x00001710,
+    GPIO_REMAP_MACEISEL_RMII    = 0x00001711,
+
+    GPIO_NO_REMAP_SWJ           = 0x00001870,
+    GPIO_REMAP_SWJ_NOJTRST      = 0x00001871,
+    GPIO_REMAP_SWJ_JTAGDISABLE  = 0x00001872,
+    GPIO_REMAP_SWJ_DISABLE      = 0x00001874,
+
+    GPIO_NO_REMAP_SPI3          = 0x00001C10,
+    GPIO_REMAP_SPI3             = 0x00001C11,
+
+    GPIO_NO_REMAP_TMR2ITR1      = 0x00001D10,
+    GPIO_REMAP_TMR2ITR1         = 0x00001D11,
+
+    GPIO_NO_REMAP_PTP_PPS       = 0x00001E10,
+    GPIO_REMAP_PTP_PPS          = 0x00001E11,
+#endif
 } GPIO_REMAP_T;
 
 /**
@@ -204,7 +238,7 @@ typedef enum
 /**@} end of group GPIO_Enumerations*/
 
 
-/** @addtogroup GPIO_Structure Data Structure
+/** @defgroup GPIO_Structures Structures
   @{
 */
 
@@ -218,41 +252,41 @@ typedef struct
     GPIO_MODE_T      mode;
 } GPIO_Config_T;
 
-/**@} end of group GPIO_Structure*/
+/**@} end of group GPIO_Structures*/
 
-/** @addtogroup GPIO_Fuctions Fuctions
+/** @defgroup GPIO_Functions Functions
   @{
 */
 
-/** Reset and common Configuration */
-void GPIO_Reset(GPIO_T *port);
+/* Reset and common Configuration */
+void GPIO_Reset(GPIO_T* port);
 void GPIO_AFIOReset(void);
-void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig);
-void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig);
-
-/** Read */
-uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin);
-uint16_t GPIO_ReadInputPort(GPIO_T *port);
-uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin);
-uint16_t GPIO_ReadOutputPort(GPIO_T *port);
-
-/** Write */
-void GPIO_SetBit(GPIO_T *port, uint16_t pin);
-void GPIO_ResetBit(GPIO_T *port, uint16_t pin);
-void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue);
-void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal);
-
-/** GPIO Configuration */
-void GPIO_ConfigPinLock(GPIO_T *port, uint16_t pin);
+void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig);
+void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig);
+
+/* Read */
+uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin);
+uint16_t GPIO_ReadInputPort(GPIO_T* port);
+uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin);
+uint16_t GPIO_ReadOutputPort(GPIO_T* port);
+
+/* Write */
+void GPIO_SetBit(GPIO_T* port, uint16_t pin);
+void GPIO_ResetBit(GPIO_T* port, uint16_t pin);
+void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue);
+void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal);
+
+/* GPIO Configuration */
+void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin);
 void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
 void GPIO_EnableEventOutput(void);
 void GPIO_DisableEventOutput(void);
 void GPIO_ConfigPinRemap(GPIO_REMAP_T remap);
 void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
 
-/**@} end of group GPIO_Fuctions*/
-/**@} end of group GPIO_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group GPIO_Functions*/
+/**@} end of group GPIO_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver*/
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_i2c.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the I2C firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_I2C_H
 #define __APM32F10X_I2C_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +42,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup I2C_Enumerations Enumerations
+/** @defgroup I2C_Enumerations Enumerations
   @{
 */
 
@@ -150,58 +152,56 @@ typedef enum
  */
 typedef enum
 {
-    /** I2C Master Events */
-    /** Event 5: Communication start event */
-    I2C_EVENT_MASTER_MODE_SELECT                       = 0x00030001,  //!< BUSBSYFLG, MSFLG and STARTFLG flag
-
-    /**
-     * Event 6: 7-bit Address Acknowledge
-     *          in case of master receiver
-     */
-    I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED         = 0x00070082,  //!< BUSBSYFLG, MSFLG, ADDRFLG, TXBEFLG and TRFLG flags */
-    I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED            = 0x00030002,  //!< BUSBSYFLG, MSFLG and ADDRFLG flags */
-    /**
-     * Event 9: Master has sent the first byte
-     *          in 10-bit address mode
-     */
-    I2C_EVENT_MASTER_MODE_ADDRESS10                    = 0x00030008,  //!< BUSBSYFLG, MSFLG and ADDR10FLG flags */
-
-    /** Master RECEIVER mode */
-    /** Event 7 */
-    I2C_EVENT_MASTER_BYTE_RECEIVED                     = 0x00030040,  //!< BUSBSYFLG, MSFLG and RXBNEFLG flags */
-
-    /** Master TRANSMITTER mode */
-    /** Event 8 */
-    I2C_EVENT_MASTER_BYTE_TRANSMITTING                 = 0x00070080,  //!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG flags */
-    /** Event 8_2 */
-    I2C_EVENT_MASTER_BYTE_TRANSMITTED                  = 0x00070084,  //!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG and BTCFLG flags */
-
-
-    /** EV1 (all the events below are variants of EV1) */
-    /** 1, Case of One Single Address managed by the slave */
-    I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED           = 0x00020002, //!< BUSBSYFLG and ADDRFLG flags */
-    I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED        = 0x00060082, //!< TRFLG, BUSBSYFLG, TXBEFLG and ADDRFLG flags */
-
-    /** 2, Case of Dual address managed by the slave */
-    I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED     = 0x00820000, //!< DUALF and BUSBSYFLG flags */
-    I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED  = 0x00860080, //!< DUALF, TRFLG, BUSBSYFLG and TXBEFLG flags */
-
-    /** 3, Case of General Call enabled for the slave */
-    I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED         = 0x00120000, //!< GENCALL and BUSBSYFLG flags */
-
-
-    /** Slave RECEIVER mode */
-    /** EV2 */
-    I2C_EVENT_SLAVE_BYTE_RECEIVED                      = 0x00020040, //!< BUSBSYFLG and RXBNEFLG flags */
-    /** EV4  */
-    I2C_EVENT_SLAVE_STOP_DETECTED                      = 0x00000010, //!< STOPFLG flag */
-
-    /** Slave TRANSMITTER mode */
-    /** EV3 */
-    I2C_EVENT_SLAVE_BYTE_TRANSMITTED                   = 0x00060084, //!< TRFLG, BUSBSYFLG, TXBEFLG and BTCFLG flags */
-    I2C_EVENT_SLAVE_BYTE_TRANSMITTING                  = 0x00060080, //!< TRFLG, BUSBSYFLG and TXBEFLG flags */
-    /** EV3_2 */
-    I2C_EVENT_SLAVE_ACK_FAILURE                        = 0x00000400, //!< AEFLG flag */
+    /* I2C Master Events */
+    /* Event 5: Communication start event */
+    I2C_EVENT_MASTER_MODE_SELECT                       = 0x00030001,  /*!< BUSBSYFLG, MSFLG and STARTFLG flag */
+
+    /* Event 6: 7-bit Address Acknowledge
+       in case of master receiver
+    */
+    I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED         = 0x00070082,  /*!< BUSBSYFLG, MSFLG, ADDRFLG, TXBEFLG and TRFLG flags */
+    I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED            = 0x00030002,  /*!< BUSBSYFLG, MSFLG and ADDRFLG flags */
+    /* Event 9: Master has sent the first byte
+       in 10-bit address mode
+    */
+    I2C_EVENT_MASTER_MODE_ADDRESS10                    = 0x00030008,  /*!< BUSBSYFLG, MSFLG and ADDR10FLG flags */
+
+    /* Master RECEIVER mode */
+    /* Event 7 */
+    I2C_EVENT_MASTER_BYTE_RECEIVED                     = 0x00030040,  /*!< BUSBSYFLG, MSFLG and RXBNEFLG flags */
+
+    /* Master TRANSMITTER mode */
+    /* Event 8 */
+    I2C_EVENT_MASTER_BYTE_TRANSMITTING                 = 0x00070080,  /*!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG flags */
+    /* Event 8_2 */
+    I2C_EVENT_MASTER_BYTE_TRANSMITTED                  = 0x00070084,  /*!< TRFLG, BUSBSYFLG, MSFLG, TXBEFLG and BTCFLG flags */
+
+
+    /* EV1 (all the events below are variants of EV1) */
+    /* 1, Case of One Single Address managed by the slave */
+    I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED           = 0x00020002, /*!< BUSBSYFLG and ADDRFLG flags */
+    I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED        = 0x00060082, /*!< TRFLG, BUSBSYFLG, TXBEFLG and ADDRFLG flags */
+
+    /* 2, Case of Dual address managed by the slave */
+    I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED     = 0x00820000, /*!< DUALF and BUSBSYFLG flags */
+    I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED  = 0x00860080, /*!< DUALF, TRFLG, BUSBSYFLG and TXBEFLG flags */
+
+    /* 3, Case of General Call enabled for the slave */
+    I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED         = 0x00120000, /*!< GENCALL and BUSBSYFLG flags */
+
+
+    /* Slave RECEIVER mode */
+    /* EV2 */
+    I2C_EVENT_SLAVE_BYTE_RECEIVED                      = 0x00020040, /*!< BUSBSYFLG and RXBNEFLG flags */
+    /* EV4  */
+    I2C_EVENT_SLAVE_STOP_DETECTED                      = 0x00000010, /*!< STOPFLG flag */
+
+    /* Slave TRANSMITTER mode */
+    /* EV3 */
+    I2C_EVENT_SLAVE_BYTE_TRANSMITTED                   = 0x00060084, /*!< TRFLG, BUSBSYFLG, TXBEFLG and BTCFLG flags */
+    I2C_EVENT_SLAVE_BYTE_TRANSMITTING                  = 0x00060080, /*!< TRFLG, BUSBSYFLG and TXBEFLG flags */
+    /* EV3_2 */
+    I2C_EVENT_SLAVE_ACK_FAILURE                        = 0x00000400, /*!< AEFLG flag */
 } I2C_EVENT_T;
 
 /**
@@ -209,7 +209,7 @@ typedef enum
  */
 typedef enum
 {
-    /** STS2 register flags */
+    /* STS2 register flags */
     I2C_FLAG_DUALADDR,
     I2C_FLAG_SMMHADDR,
     I2C_FLAG_SMBDADDR,
@@ -218,7 +218,7 @@ typedef enum
     I2C_FLAG_BUSBSY,
     I2C_FLAG_MS,
 
-    /** STS1 register flags */
+    /* STS1 register flags */
     I2C_FLAG_SMBALT,
     I2C_FLAG_TTE,
     I2C_FLAG_PECE,
@@ -258,7 +258,7 @@ typedef enum
 
 /**@} end of group I2C_Enumerations*/
 
-/** @addtogroup I2C_Structure Data Structure
+/** @defgroup I2C_Structures Structures
   @{
 */
 
@@ -275,71 +275,71 @@ typedef struct
     I2C_ACK_ADDRESS_T   ackAddress;
 } I2C_Config_T;
 
-/**@} end of group I2C_Structure*/
+/**@} end of group I2C_Structures*/
 
 
-/** @addtogroup I2C_Fuctions Fuctions
+/** @defgroup I2C_Functions Functions
   @{
 */
 
-/** I2C reset and configuration */
-void I2C_Reset(I2C_T *i2c);
-void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig);
-void I2C_ConfigStructInit(I2C_Config_T *i2cConfig);
-void I2C_Enable(I2C_T *i2c);
-void I2C_Disable(I2C_T *i2c);
-void I2C_EnableGenerateStart(I2C_T *i2c);
-void I2C_DisableGenerateStart(I2C_T *i2c);
-void I2C_EnableGenerateStop(I2C_T *i2c);
-void I2C_DisableGenerateStop(I2C_T *i2c);
-void I2C_EnableAcknowledge(I2C_T *i2c);
-void I2C_DisableAcknowledge(I2C_T *i2c);
-void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address);
-void I2C_EnableDualAddress(I2C_T *i2c);
-void I2C_DisableDualAddress(I2C_T *i2c);
-void I2C_EnableGeneralCall(I2C_T *i2c);
-void I2C_DisableGeneralCall(I2C_T *i2c);
-
-/** Transmit Configuration */
-void I2C_TxData(I2C_T *i2c, uint8_t data);
-uint8_t I2C_RxData(I2C_T *i2c);
-void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction);
-uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister);
-void I2C_EnableSoftwareReset(I2C_T *i2c);
-void I2C_DisableSoftwareReset(I2C_T *i2c);
-void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition);
-void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState);
-void I2C_EnablePECTransmit(I2C_T *i2c);
-void I2C_DisablePECTransmit(I2C_T *i2c);
-void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition);
-void I2C_EnablePEC(I2C_T *i2c);
-void I2C_DisablePEC(I2C_T *i2c);
-uint8_t I2C_ReadPEC(I2C_T *i2c);
-void I2C_EnableARP(I2C_T *i2c);
-void I2C_DisableARP(I2C_T *i2c);
-void I2C_EnableStretchClock(I2C_T *i2c);
-void I2C_DisableStretchClock(I2C_T *i2c);
-void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle);
-
-/** DMA */
-void I2C_EnableDMA(I2C_T *i2c);
-void I2C_DisableDMA(I2C_T *i2c);
-void I2C_EnableDMALastTransfer(I2C_T *i2c);
-void I2C_DisableDMALastTransfer(I2C_T *i2c);
-
-/** Interrupts and flags */
-void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt);
-void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt);
-uint8_t  I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent);
-uint32_t I2C_ReadLastEvent(I2C_T *i2c);
-uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag);
-void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag);
-uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag);
-void I2C_ClearIntFlag(I2C_T *i2c, uint32_t flag);
-
-/**@} end of group I2C_Fuctions*/
+/* I2C reset and configuration */
+void I2C_Reset(I2C_T* i2c);
+void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig);
+void I2C_ConfigStructInit(I2C_Config_T* i2cConfig);
+void I2C_Enable(I2C_T* i2c);
+void I2C_Disable(I2C_T* i2c);
+void I2C_EnableGenerateStart(I2C_T* i2c);
+void I2C_DisableGenerateStart(I2C_T* i2c);
+void I2C_EnableGenerateStop(I2C_T* i2c);
+void I2C_DisableGenerateStop(I2C_T* i2c);
+void I2C_EnableAcknowledge(I2C_T* i2c);
+void I2C_DisableAcknowledge(I2C_T* i2c);
+void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address);
+void I2C_EnableDualAddress(I2C_T* i2c);
+void I2C_DisableDualAddress(I2C_T* i2c);
+void I2C_EnableGeneralCall(I2C_T* i2c);
+void I2C_DisableGeneralCall(I2C_T* i2c);
+
+/* Transmit Configuration */
+void I2C_TxData(I2C_T* i2c, uint8_t data);
+uint8_t I2C_RxData(I2C_T* i2c);
+void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction);
+uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister);
+void I2C_EnableSoftwareReset(I2C_T* i2c);
+void I2C_DisableSoftwareReset(I2C_T* i2c);
+void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition);
+void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState);
+void I2C_EnablePECTransmit(I2C_T* i2c);
+void I2C_DisablePECTransmit(I2C_T* i2c);
+void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition);
+void I2C_EnablePEC(I2C_T* i2c);
+void I2C_DisablePEC(I2C_T* i2c);
+uint8_t I2C_ReadPEC(I2C_T* i2c);
+void I2C_EnableARP(I2C_T* i2c);
+void I2C_DisableARP(I2C_T* i2c);
+void I2C_EnableStretchClock(I2C_T* i2c);
+void I2C_DisableStretchClock(I2C_T* i2c);
+void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle);
+
+/* DMA */
+void I2C_EnableDMA(I2C_T* i2c);
+void I2C_DisableDMA(I2C_T* i2c);
+void I2C_EnableDMALastTransfer(I2C_T* i2c);
+void I2C_DisableDMALastTransfer(I2C_T* i2c);
+
+/* Interrupts and flags */
+void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt);
+void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt);
+uint8_t  I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent);
+uint32_t I2C_ReadLastEvent(I2C_T* i2c);
+uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
+void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag);
+uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag);
+void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag);
+
+/**@} end of group I2C_Functions*/
 /**@} end of group I2C_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group APM32F10x_StdPeriphDriver*/
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_iwdt.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the IWDT firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_IWDT_H
 #define __APM32F10X_IWDT_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +42,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup IWDT_Enumerations Enumerations
+/** @defgroup IWDT_Enumerations Enumerations
   @{
 */
 
@@ -88,32 +90,32 @@ typedef enum
 /**@} end of group IWDT_Enumerations*/
 
 
-/** @addtogroup IWDT_Fuctions Fuctions
+/** @defgroup IWDT_Functions Functions
   @{
 */
 
-/** Enable IWDT */
+/* Enable IWDT */
 void IWDT_Enable(void);
 
-/** Refresh IWDT */
+/* Refresh IWDT */
 void IWDT_Refresh(void);
 
-/** Counter reload */
+/* Counter reload */
 void IWDT_ConfigReload(uint16_t reload);
 
-/** Divider */
+/* Divider */
 void IWDT_ConfigDivider(uint8_t div);
 
-/** Write Access */
+/* Write Access */
 void IWDT_EnableWriteAccess(void);
 void IWDT_DisableWriteAccess(void);
 
-/** flag */
+/* flag */
 uint8_t IWDT_ReadStatusFlag(uint16_t flag);
 
-/**@} end of group IWDT_Fuctions*/
-/**@} end of group IWDT_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group IWDT_Functions*/
+/**@} end of group IWDT_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver*/
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_misc.h

@@ -4,9 +4,9 @@
  * @brief       This file provides all the miscellaneous firmware functions.
  *             Include NVIC,SystemTick and Power management.
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -16,7 +16,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -24,16 +24,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_MISC_H
 #define __APM32F10X_MISC_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -41,7 +43,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup MISC_Enumerations Enumerations
+/** @defgroup MISC_Enumerations Enumerations
   @{
 */
 
@@ -69,11 +71,11 @@ typedef enum
  */
 typedef enum
 {
-    NVIC_PRIORITY_GROUP_0 = 0x700,  //!< 0 bits for pre-emption priority,4 bits for subpriority
-    NVIC_PRIORITY_GROUP_1 = 0x600,  //!< 1 bits for pre-emption priority,3 bits for subpriority
-    NVIC_PRIORITY_GROUP_2 = 0x500,  //!< 2 bits for pre-emption priority,2 bits for subpriority
-    NVIC_PRIORITY_GROUP_3 = 0x400,  //!< 3 bits for pre-emption priority,1 bits for subpriority
-    NVIC_PRIORITY_GROUP_4 = 0x300   //!< 4 bits for pre-emption priority,0 bits for subpriority
+    NVIC_PRIORITY_GROUP_0 = 0x700,  /*!< 0 bits for pre-emption priority,4 bits for subpriority */
+    NVIC_PRIORITY_GROUP_1 = 0x600,  /*!< 1 bits for pre-emption priority,3 bits for subpriority */
+    NVIC_PRIORITY_GROUP_2 = 0x500,  /*!< 2 bits for pre-emption priority,2 bits for subpriority */
+    NVIC_PRIORITY_GROUP_3 = 0x400,  /*!< 3 bits for pre-emption priority,1 bits for subpriority */
+    NVIC_PRIORITY_GROUP_4 = 0x300   /*!< 4 bits for pre-emption priority,0 bits for subpriority */
 } NVIC_PRIORITY_GROUP_T;
 
 /**
@@ -88,28 +90,28 @@ typedef enum
 /**@} end of group MISC_Enumerations*/
 
 
-/** @addtogroup MISC_Fuctions Fuctions
+/** @defgroup MISC_Functions Functions
   @{
 */
 
-/** NVIC */
+/* NVIC */
 void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup);
 void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority);
 void NVIC_DisableIRQRequest(IRQn_Type irq);
 
-/** Vector Table */
+/* Vector Table */
 void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset);
 
-/** Power */
+/* Power */
 void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode);
 void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode);
 
-/** Systick */
+/* Systick */
 void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource);
 
-/**@} end of group MISC_Fuctions*/
+/**@} end of group MISC_Functions*/
 /**@} end of group MISC_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group APM32F10x_StdPeriphDriver*/
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_pmu.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the PMU firmware library.
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_PMU_H
 #define __APM32F10X_PMU_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +42,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup PMU_Enumerations Enumerations
+/** @defgroup PMU_Enumerations Enumerations
   @{
 */
 
@@ -49,14 +51,14 @@ extern "C" {
  */
 typedef enum
 {
-    PMU_PVD_LEVEL_2V2    = 0x00,    //!< PVD detection level set to 2.2V
-    PMU_PVD_LEVEL_2V3    = 0x01,    //!< PVD detection level set to 2.3V
-    PMU_PVD_LEVEL_2V4    = 0x02,    //!< PVD detection level set to 2.4V
-    PMU_PVD_LEVEL_2V5    = 0x03,    //!< PVD detection level set to 2.5V
-    PMU_PVD_LEVEL_2V6    = 0x04,    //!< PVD detection level set to 2.6V
-    PMU_PVD_LEVEL_2V7    = 0x05,    //!< PVD detection level set to 2.7V
-    PMU_PVD_LEVEL_2V8    = 0x06,    //!< PVD detection level set to 2.8V
-    PMU_PVD_LEVEL_2V9    = 0x07,    //!< PVD detection level set to 2.9V
+    PMU_PVD_LEVEL_2V2    = 0x00,    /*!< PVD detection level set to 2.2V */
+    PMU_PVD_LEVEL_2V3    = 0x01,    /*!< PVD detection level set to 2.3V */
+    PMU_PVD_LEVEL_2V4    = 0x02,    /*!< PVD detection level set to 2.4V */
+    PMU_PVD_LEVEL_2V5    = 0x03,    /*!< PVD detection level set to 2.5V */
+    PMU_PVD_LEVEL_2V6    = 0x04,    /*!< PVD detection level set to 2.6V */
+    PMU_PVD_LEVEL_2V7    = 0x05,    /*!< PVD detection level set to 2.7V */
+    PMU_PVD_LEVEL_2V8    = 0x06,    /*!< PVD detection level set to 2.8V */
+    PMU_PVD_LEVEL_2V9    = 0x07,    /*!< PVD detection level set to 2.9V */
 } PMU_PVD_LEVEL_T;
 
 /**
@@ -90,14 +92,14 @@ typedef enum
 /**@} end of group PMU_Enumerations*/
 
 
-/** @addtogroup PMU_Fuctions Fuctions
+/** @addtogroup PMU_Functions Functions
   @{
 */
 
-/** PMU Reset */
+/* PMU Reset */
 void PMU_Reset(void);
 
-/** Configuration and Operation modes */
+/* Configuration and Operation modes */
 void PMU_EnableBackupAccess(void);
 void PMU_DisableBackupAccess(void);
 void PMU_EnablePVD(void);
@@ -108,13 +110,13 @@ void PMU_DisableWakeUpPin(void);
 void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry);
 void PMU_EnterSTANDBYMode(void);
 
-/** flags */
+/* flags */
 uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag);
 void PMU_ClearStatusFlag(PMU_FLAG_T flag);
 
-/**@} end of group PMU_Fuctions*/
-/**@} end of group PMU_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group PMU_Functions*/
+/**@} end of group PMU_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver*/
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_qspi.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the prototypes,enumeration and macros for the QSPI peripheral
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_QSPI_H
 #define __APM32F10X_QSPI_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +42,42 @@ extern "C" {
   @{
 */
 
-/** @addtogroup QSPI_Enumerations Enumerations
+/** @defgroup QSPI_Macros Macros
+  @{
+*/
+
+/* CTRL1 register reset value */
+#define QSPI_CTRL1_RESET_VALUE      ((uint32_t)0x4007)
+/* CTRL2 register reset value */
+#define QSPI_CTRL2_RESET_VALUE      ((uint32_t)0x00)
+/* SSIEN register reset value */
+#define QSPI_SSIEN_RESET_VALUE      ((uint32_t)0x00)
+/* SLAEN register reset value */
+#define QSPI_SLAEN_RESET_VALUE      ((uint32_t)0x00)
+/* BR register reset value */
+#define QSPI_BR_RESET_VALUE         ((uint32_t)0x00)
+/* TFTL register reset value */
+#define QSPI_TFTL_RESET_VALUE       ((uint32_t)0x00)
+/* RFTL register reset value */
+#define QSPI_RFTL_RESET_VALUE       ((uint32_t)0x00)
+/* TFL register reset value */
+#define QSPI_TFL_RESET_VALUE        ((uint32_t)0x00)
+/* RFL register reset value */
+#define QSPI_RFL_RESET_VALUE        ((uint32_t)0x00)
+/* STS register reset value */
+#define QSPI_STS_RESET_VALUE        ((uint32_t)0x06)
+/* INTEN register reset value */
+#define QSPI_INTEN_RESET_VALUE      ((uint32_t)0x7F)
+/* RSD register reset value */
+#define QSPI_RSD_RESET_VALUE        ((uint32_t)0x00)
+/* CTRL3 register reset value */
+#define QSPI_CTRL3_RESET_VALUE      ((uint32_t)0x200)
+/* IOSW register reset value */
+#define QSPI_IOSW_RESET_VALUE       ((uint32_t)0x00)
+
+/**@} end of group QSPI_Macros*/
+
+/** @defgroup QSPI_Enumerations Enumerations
   @{
 */
 
@@ -49,9 +86,9 @@ extern "C" {
  */
 typedef enum
 {
-    QSPI_FRF_STANDARD,              //!< Standard mode
-    QSPI_FRF_DUAL,                  //!< Dual SPI
-    QSPI_FRF_QUAD                   //!< QUAD SPI
+    QSPI_FRF_STANDARD,              /*!< Standard mode */
+    QSPI_FRF_DUAL,                  /*!< Dual SPI */
+    QSPI_FRF_QUAD                   /*!< QUAD SPI */
 } QSPI_FRF_T;
 
 /**
@@ -59,10 +96,10 @@ typedef enum
  */
 typedef enum
 {
-    QSPI_TRANS_MODE_TX_RX,          //!< TX and RX mode
-    QSPI_TRANS_MODE_TX,             //!< TX mode only
-    QSPI_TRANS_MODE_RX,             //!< RX mode only
-    QSPI_TRANS_MODE_EEPROM_READ     //!< EEPROM read mode
+    QSPI_TRANS_MODE_TX_RX,          /*!< TX and RX mode */
+    QSPI_TRANS_MODE_TX,             /*!< TX mode only */
+    QSPI_TRANS_MODE_RX,             /*!< RX mode only */
+    QSPI_TRANS_MODE_EEPROM_READ     /*!< EEPROM read mode */
 } QSPI_TRANS_MODE_T;
 
 /**
@@ -124,12 +161,12 @@ typedef enum
  */
 typedef enum
 {
-    QSPI_FLAG_BUSY      = BIT0,     //!< Busy flag
-    QSPI_FLAG_TFNF      = BIT1,     //!< TX FIFO not full flag
-    QSPI_FLAG_TFE       = BIT2,     //!< TX FIFO empty flag
-    QSPI_FLAG_RFNE      = BIT3,     //!< RX FIFO not empty flag
-    QSPI_FLAG_RFF       = BIT4,     //!< RX FIFO full flag
-    QSPI_FLAG_DCE       = BIT6      //!< Data collision error
+    QSPI_FLAG_BUSY      = BIT0,     /*!< Busy flag */
+    QSPI_FLAG_TFNF      = BIT1,     /*!< TX FIFO not full flag */
+    QSPI_FLAG_TFE       = BIT2,     /*!< TX FIFO empty flag */
+    QSPI_FLAG_RFNE      = BIT3,     /*!< RX FIFO not empty flag */
+    QSPI_FLAG_RFF       = BIT4,     /*!< RX FIFO full flag */
+    QSPI_FLAG_DCE       = BIT6      /*!< Data collision error */
 } QSPI_FLAG_T;
 
 /**
@@ -137,12 +174,12 @@ typedef enum
  */
 typedef enum
 {
-    QSPI_INT_TFE        = BIT0,     //!< TX FIFO empty interrupt
-    QSPI_INT_TFO        = BIT1,     //!< TX FIFO overflow interrupt
-    QSPI_INT_RFU        = BIT2,     //!< RX FIFO underflow interrupt
-    QSPI_INT_RFO        = BIT3,     //!< RX FIFO overflow interrupt
-    QSPI_INT_RFF        = BIT4,     //!< RX FIFO full interrupt
-    QSPI_INT_MST        = BIT5      //!< Master interrupt
+    QSPI_INT_TFE        = BIT0,     /*!< TX FIFO empty interrupt */
+    QSPI_INT_TFO        = BIT1,     /*!< TX FIFO overflow interrupt */
+    QSPI_INT_RFU        = BIT2,     /*!< RX FIFO underflow interrupt */
+    QSPI_INT_RFO        = BIT3,     /*!< RX FIFO overflow interrupt */
+    QSPI_INT_RFF        = BIT4,     /*!< RX FIFO full interrupt */
+    QSPI_INT_MST        = BIT5      /*!< Master interrupt */
 } QSPI_INT_T;
 
 /**
@@ -150,12 +187,12 @@ typedef enum
  */
 typedef enum
 {
-    QSPI_INT_FLAG_TFE   = BIT0,     //!< TX FIFO empty interrupt flag
-    QSPI_INT_FLAG_TFO   = BIT1,     //!< TX FIFO overflow interrupt flag
-    QSPI_INT_FLAG_RFU   = BIT2,     //!< RX FIFO underflow interrupt flag
-    QSPI_INT_FLAG_RFO   = BIT3,     //!< RX FIFO overflow interrupt flag
-    QSPI_INT_FLAG_RFF   = BIT4,     //!< RX FIFO full interrupt flag
-    QSPI_INT_FLAG_MST   = BIT5      //!< Master interrupt flag
+    QSPI_INT_FLAG_TFE   = BIT0,     /*!< TX FIFO empty interrupt flag */
+    QSPI_INT_FLAG_TFO   = BIT1,     /*!< TX FIFO overflow interrupt flag */
+    QSPI_INT_FLAG_RFU   = BIT2,     /*!< RX FIFO underflow interrupt flag */
+    QSPI_INT_FLAG_RFO   = BIT3,     /*!< RX FIFO overflow interrupt flag */
+    QSPI_INT_FLAG_RFF   = BIT4,     /*!< RX FIFO full interrupt flag */
+    QSPI_INT_FLAG_MST   = BIT5      /*!< Master interrupt flag */
 } QSPI_INT_FLAG_T;
 
 /**
@@ -222,130 +259,93 @@ typedef enum
 
 /**@} end of group QSPI_Enumerations*/
 
-/** @addtogroup QSPI_Macros Macros
-  @{
-*/
-
-/** CTRL1 register reset value */
-#define QSPI_CTRL1_RESET_VALUE      ((uint32_t)0x4007)
-/** CTRL2 register reset value */
-#define QSPI_CTRL2_RESET_VALUE      ((uint32_t)0x00)
-/** SSIEN register reset value */
-#define QSPI_SSIEN_RESET_VALUE      ((uint32_t)0x00)
-/** SLAEN register reset value */
-#define QSPI_SLAEN_RESET_VALUE      ((uint32_t)0x00)
-/** BR register reset value */
-#define QSPI_BR_RESET_VALUE         ((uint32_t)0x00)
-/** TFTL register reset value */
-#define QSPI_TFTL_RESET_VALUE       ((uint32_t)0x00)
-/** RFTL register reset value */
-#define QSPI_RFTL_RESET_VALUE       ((uint32_t)0x00)
-/** TFL register reset value */
-#define QSPI_TFL_RESET_VALUE        ((uint32_t)0x00)
-/** RFL register reset value */
-#define QSPI_RFL_RESET_VALUE        ((uint32_t)0x00)
-/** STS register reset value */
-#define QSPI_STS_RESET_VALUE        ((uint32_t)0x06)
-/** INTEN register reset value */
-#define QSPI_INTEN_RESET_VALUE      ((uint32_t)0x7F)
-/** RSD register reset value */
-#define QSPI_RSD_RESET_VALUE        ((uint32_t)0x00)
-/** CTRL3 register reset value */
-#define QSPI_CTRL3_RESET_VALUE      ((uint32_t)0x200)
-/** IOSW register reset value */
-#define QSPI_IOSW_RESET_VALUE       ((uint32_t)0x00)
-
-/**@} end of group QSPI_Macros*/
-
-
-/** @addtogroup QSPI_Structure Data Structure
+/** @defgroup QSPI_Structure Data Structure
   @{
 */
 typedef struct
 {
-    QSPI_SST_T       selectSlaveToggle; //!< Slave Select Toggle
-    QSPI_FRF_T       frameFormat;       //!< Frame format
-    uint16_t         clockDiv;          //!< Clock divider
-    QSPI_CLKPOL_T    clockPolarity;     //!< Clock polarity
-    QSPI_CLKPHA_T    clockPhase;        //!< Clock phase
-    QSPI_DFS_T       dataFrameSize;     //!< Data frame size
+    QSPI_SST_T       selectSlaveToggle; /*!< Slave Select Toggle */
+    QSPI_FRF_T       frameFormat;       /*!< Frame format */
+    uint16_t         clockDiv;          /*!< Clock divider */
+    QSPI_CLKPOL_T    clockPolarity;     /*!< Clock polarity */
+    QSPI_CLKPHA_T    clockPhase;        /*!< Clock phase */
+    QSPI_DFS_T       dataFrameSize;     /*!< Data frame size */
 } QSPI_Config_T;
 
 /**@} end of group QSPI_Structure*/
 
-
-/** @addtogroup QSPI_Fuctions Fuctions
+/** @defgroup QSPI_Functions Functions
   @{
 */
 
-/** Reset */
+/* Reset */
 void QSPI_Reset(void);
 
-/** Configuration */
-void QSPI_Config(QSPI_Config_T *qspiConfig);
-void QSPI_ConfigStructInit(QSPI_Config_T *qspiConfig);
+/* Configuration */
+void QSPI_Config(QSPI_Config_T* qspiConfig);
+void QSPI_ConfigStructInit(QSPI_Config_T* qspiConfig);
 
-/** Data frame size, frame number, frame format */
+/* Data frame size, frame number, frame format */
 void QSPI_ConfigFrameNum(uint16_t num);
 void QSPI_ConfigDataFrameSize(QSPI_DFS_T dfs);
 void QSPI_ConfigFrameFormat(QSPI_FRF_T frameFormat);
 
-/** Disable or Enable */
+/* Disable or Enable */
 void QSPI_Enable(void);
 void QSPI_Disable(void);
 
-/** TX and RX FIFO */
+/* TX and RX FIFO */
 uint8_t QSPI_ReadTxFifoDataNum(void);
 uint8_t QSPI_ReadRxFifoDataNum(void);
 void QSPI_ConfigRxFifoThreshold(uint8_t threshold);
 void QSPI_ConfigTxFifoThreshold(uint8_t threshold);
 void QSPI_ConfigTxFifoEmptyThreshold(uint8_t threshold);
 
-/** RX Sample */
+/* RX Sample */
 void QSPI_ConfigRxSampleEdge(QSPI_RSE_T rse);
 void QSPI_ConfigRxSampleDelay(uint8_t delay);
 
-/** Clock stretch */
+/* Clock stretch */
 void QSPI_EnableClockStretch(void);
 void QSPI_DisableClockStretch(void);
 
-/** Instruction, address, Wait cycle */
+/* Instruction, address, Wait cycle */
 void QSPI_ConfigInstLen(QSPI_INST_LEN_T len);
 void QSPI_ConfigAddrLen(QSPI_ADDR_LEN_T len);
 void QSPI_ConfigInstAddrType(QSPI_INST_ADDR_TYPE_T type);
 void QSPI_ConfigWaitCycle(uint8_t cycle);
 
-/** IO */
+/* IO */
 void QSPI_OpenIO(void);
 void QSPI_CloseIO(void);
 
-/** Transmission mode */
+/* Transmission mode */
 void QSPI_ConfigTansMode(QSPI_TRANS_MODE_T mode);
 
-/** Rx and Tx data */
+/* Rx and Tx data */
 uint32_t QSPI_RxData(void);
 void QSPI_TxData(uint32_t data);
 
-/** Slave */
+/* Slave */
 void QSPI_EnableSlave(void);
 void QSPI_DisableSlave(void);
 
-/** Interrupt */
+/* Interrupt */
 void QSPI_EnableInterrupt(uint32_t interrupt);
 void QSPI_DisableInterrupt(uint32_t interrupt);
 
-/** Flag */
+/* Flag */
 uint8_t QSPI_ReadStatusFlag(QSPI_FLAG_T flag);
 void QSPI_ClearStatusFlag(void);
 uint8_t QSPI_ReadIntFlag(QSPI_INT_FLAG_T flag);
 void QSPI_ClearIntFlag(uint32_t flag);
 
-/**@} end of group QSPI_Fuctions*/
+/**@} end of group QSPI_Functions*/
 /**@} end of group QSPI_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group APM32F10x_StdPeriphDriver*/
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif  /* __APM32F10X_QSPI_H_ */
+#endif /* __APM32F10X_QSPI_H */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rcm.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the RCM firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_RCM_H
 #define __APM32F10X_RCM_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +42,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup RCM_Enumerations Enumerations
+/** @defgroup RCM_Enumerations Enumerations
   @{
 */
 
@@ -59,6 +61,15 @@ typedef enum
  */
 typedef enum
 {
+#if defined(APM32F10X_CL)
+    RCM_PLLMF_4 = 2,
+    RCM_PLLMF_5,
+    RCM_PLLMF_6,
+    RCM_PLLMF_7,
+    RCM_PLLMF_8,
+    RCM_PLLMF_9,
+    RCM_PLLMF_6_5 = 13,
+#else
     RCM_PLLMF_2,
     RCM_PLLMF_3,
     RCM_PLLMF_4,
@@ -74,8 +85,41 @@ typedef enum
     RCM_PLLMF_14,
     RCM_PLLMF_15,
     RCM_PLLMF_16
+#endif
 } RCM_PLLMF_T;
 
+/**
+ * @brief   PLL2 multiplication factor
+ */
+typedef enum
+{
+    RCM_PLL2MF_8  = 6,
+    RCM_PLL2MF_9  = 7,
+    RCM_PLL2MF_10 = 8,
+    RCM_PLL2MF_11 = 9,
+    RCM_PLL2MF_12 = 10,
+    RCM_PLL2MF_13 = 11,
+    RCM_PLL2MF_14 = 12,
+    RCM_PLL2MF_16 = 14,
+    RCM_PLL2MF_20 = 15
+} RCM_PLL2MF_T;
+
+/**
+ * @brief   PLL3 multiplication factor
+ */
+typedef enum
+{
+    RCM_PLL3MF_8  = 6,
+    RCM_PLL3MF_9  = 7,
+    RCM_PLL3MF_10 = 8,
+    RCM_PLL3MF_11 = 9,
+    RCM_PLL3MF_12 = 10,
+    RCM_PLL3MF_13 = 11,
+    RCM_PLL3MF_14 = 12,
+    RCM_PLL3MF_16 = 14,
+    RCM_PLL3MF_20 = 15
+} RCM_PLL3MF_T;
+
 /**
  * @brief   System clock select
  */
@@ -86,6 +130,64 @@ typedef enum
     RCM_SYSCLK_SEL_PLL
 } RCM_SYSCLK_SEL_T;
 
+#if defined(APM32F10X_CL)
+/**
+ * @brief   PLLPSC1 Source
+ */
+typedef enum
+{
+    RCM_PLLPSC1_SRC_HSE,
+    RCM_PLLPSC1_SRC_PLL2
+} RCM_PLLPSC1_SRC_T;
+
+/**
+ * @brief   PLLPSC1 divider Number
+ */
+typedef enum
+{
+    RCM_PLLPSC1_DIV_1,
+    RCM_PLLPSC1_DIV_2,
+    RCM_PLLPSC1_DIV_3,
+    RCM_PLLPSC1_DIV_4,
+    RCM_PLLPSC1_DIV_5,
+    RCM_PLLPSC1_DIV_6,
+    RCM_PLLPSC1_DIV_7,
+    RCM_PLLPSC1_DIV_8,
+    RCM_PLLPSC1_DIV_9,
+    RCM_PLLPSC1_DIV_10,
+    RCM_PLLPSC1_DIV_11,
+    RCM_PLLPSC1_DIV_12,
+    RCM_PLLPSC1_DIV_13,
+    RCM_PLLPSC1_DIV_14,
+    RCM_PLLPSC1_DIV_15,
+    RCM_PLLPSC1_DIV_16
+} RCM_PLLPSC1_DIV_T;
+
+/**
+ * @brief   PLLPSC2 divider Number
+ */
+typedef enum
+{
+    RCM_PLLPSC2_DIV_1,
+    RCM_PLLPSC2_DIV_2,
+    RCM_PLLPSC2_DIV_3,
+    RCM_PLLPSC2_DIV_4,
+    RCM_PLLPSC2_DIV_5,
+    RCM_PLLPSC2_DIV_6,
+    RCM_PLLPSC2_DIV_7,
+    RCM_PLLPSC2_DIV_8,
+    RCM_PLLPSC2_DIV_9,
+    RCM_PLLPSC2_DIV_10,
+    RCM_PLLPSC2_DIV_11,
+    RCM_PLLPSC2_DIV_12,
+    RCM_PLLPSC2_DIV_13,
+    RCM_PLLPSC2_DIV_14,
+    RCM_PLLPSC2_DIV_15,
+    RCM_PLLPSC2_DIV_16
+} RCM_PLLPSC2_DIV_T;
+
+#endif
+
 /**
  * @brief   AHB divider Number
  */
@@ -122,9 +224,18 @@ typedef enum
     RCM_USB_DIV_1_5,
     RCM_USB_DIV_1,
     RCM_USB_DIV_2,
-    RCM_USB_DIV_2_5 //!< (Only for High-density devices for APM32F103xx)
+    RCM_USB_DIV_2_5  /*!< (Only for High-density devices for APM32F103xx) */
 } RCM_USB_DIV_T;
 
+/**
+ * @brief   OTG FS divider Number
+ */
+typedef enum
+{
+    RCM_OTGFS_DIV_1_5,
+    RCM_OTGFS_DIV_1
+} RCM_OTGFS_DIV_T;
+
 /**
  * @brief   FPU divider Number
  */
@@ -155,6 +266,24 @@ typedef enum
     RCM_LSE_BYPASS
 } RCM_LSE_T;
 
+/**
+ * @brief   I2S2 clock select
+ */
+typedef enum
+{
+    RCM_I2S2CLK_SYSCLK,
+    RCM_I2S2CLK_DOUBLE_PLL3
+} RCM_I2S2CLK_T;
+
+/**
+ * @brief   I2S3 clock select
+ */
+typedef enum
+{
+    RCM_I2S3CLK_SYSCLK,
+    RCM_I2S3CLK_DOUBLE_PLL3
+} RCM_I2S3CLK_T;
+
 /**
  * @brief   RTC clock select
  */
@@ -174,7 +303,13 @@ typedef enum
     RCM_MCOCLK_SYSCLK,
     RCM_MCOCLK_HSI,
     RCM_MCOCLK_HSE,
-    RCM_MCOCLK_PLLCLK_DIV_2
+    RCM_MCOCLK_PLLCLK_DIV_2,
+#if defined(APM32F10X_CL)
+    RCM_MCOCLK_PLL2CLK = 8,
+    RCM_MCOCLK_PLL3CLK_DIV_2,
+    RCM_MCOCLK_OSCCLK,
+    RCM_MCOCLK_PLL3CLK
+#endif
 } RCM_MCOCLK_T;
 
 /**
@@ -183,8 +318,12 @@ typedef enum
 typedef enum
 {
     RCM_PLLSEL_HSI_DIV_2 = 0,
+#if defined(APM32F10X_CL)
+    RCM_PLLSEL_PREDIV1   = 1,
+#else
     RCM_PLLSEL_HSE       = 1,
     RCM_PLLSEL_HSE_DIV2  = 3,
+#endif /* APM32F10X_CL */
 } RCM_PLLSEL_T;
 
 /**
@@ -192,12 +331,14 @@ typedef enum
  */
 typedef enum
 {
-    RCM_INT_LSIRDY  = BIT0,  //!< LSI ready interrupt
-    RCM_INT_LSERDY  = BIT1,  //!< LSE ready interrupt
-    RCM_INT_HSIRDY  = BIT2,  //!< HSI ready interrupt
-    RCM_INT_HSERDY  = BIT3,  //!< HSE ready interrupt
-    RCM_INT_PLLRDY  = BIT4,  //!< PLL ready interrupt
-    RCM_INT_CSS     = BIT7   //!< Clock security system interrupt
+    RCM_INT_LSIRDY  = BIT0,  /*!< LSI ready interrupt */
+    RCM_INT_LSERDY  = BIT1,  /*!< LSE ready interrupt */
+    RCM_INT_HSIRDY  = BIT2,  /*!< HSI ready interrupt */
+    RCM_INT_HSERDY  = BIT3,  /*!< HSE ready interrupt */
+    RCM_INT_PLLRDY  = BIT4,  /*!< PLL ready interrupt */
+    RCM_INT_PLL2RDY = BIT5,  /*!< PLL2 ready interrupt */
+    RCM_INT_PLL3RDY = BIT6,  /*!< PLL3 ready interrupt */
+    RCM_INT_CSS     = BIT7   /*!< Clock security system interrupt */
 } RCM_INT_T;
 
 /**
@@ -205,15 +346,19 @@ typedef enum
  */
 typedef enum
 {
-    RCM_AHB_PERIPH_DMA1 = BIT0,
-    RCM_AHB_PERIPH_DMA2 = BIT1,
-    RCM_AHB_PERIPH_SRAM = BIT2,
-    RCM_AHB_PERIPH_FPU  = BIT3,
-    RCM_AHB_PERIPH_FMC  = BIT4,
-    RCM_AHB_PERIPH_QSPI = BIT5,
-    RCM_AHB_PERIPH_CRC  = BIT6,
-    RCM_AHB_PERIPH_EMMC = BIT8,
-    RCM_AHB_PERIPH_SDIO = BIT10
+    RCM_AHB_PERIPH_DMA1       = BIT0,
+    RCM_AHB_PERIPH_DMA2       = BIT1,
+    RCM_AHB_PERIPH_SRAM       = BIT2,
+    RCM_AHB_PERIPH_FPU        = BIT3,
+    RCM_AHB_PERIPH_FMC        = BIT4,
+    RCM_AHB_PERIPH_QSPI       = BIT5,
+    RCM_AHB_PERIPH_CRC        = BIT6,
+    RCM_AHB_PERIPH_EMMC       = BIT8,
+    RCM_AHB_PERIPH_SDIO       = BIT10,
+    RCM_AHB_PERIPH_OTG_FS     = BIT12,
+    RCM_AHB_PERIPH_ETH_MAC    = BIT14,
+    RCM_AHB_PERIPH_ETH_MAC_TX = BIT15,
+    RCM_AHB_PERIPH_ETH_MAC_RX = BIT16
 } RCM_AHB_PERIPH_T;
 
 /**
@@ -271,51 +416,63 @@ typedef enum
  */
 typedef enum
 {
-    RCM_FLAG_HSIRDY  = 0x001,   //!< HSI Ready Flag
-    RCM_FLAG_HSERDY  = 0x011,   //!< HSE Ready Flag
-    RCM_FLAG_PLLRDY  = 0x019,   //!< PLL Ready Flag
-    RCM_FLAG_LSERDY  = 0x101,   //!< LSE Ready Flag
-    RCM_FLAG_LSIRDY  = 0x201,   //!< LSI Ready Flag
-    RCM_FLAG_PINRST  = 0x21A,   //!< PIN reset flag
-    RCM_FLAG_PORRST  = 0x21B,   //!< POR/PDR reset flag
-    RCM_FLAG_SWRST   = 0x21C,   //!< Software reset flag
-    RCM_FLAG_IWDTRST = 0x21D,   //!< Independent watchdog reset flag
-    RCM_FLAG_WWDTRST = 0x21E,   //!< Window watchdog reset flag
-    RCM_FLAG_LPRRST  = 0x21F    //!< Low-power reset flag
+    RCM_FLAG_HSIRDY  = 0x001,   /*!< HSI Ready Flag */
+    RCM_FLAG_HSERDY  = 0x011,   /*!< HSE Ready Flag */
+    RCM_FLAG_PLLRDY  = 0x019,   /*!< PLL Ready Flag */
+    RCM_FLAG_PLL2RDY = 0x01B,   /*!< PLL2 Ready Flag */
+    RCM_FLAG_PLL3RDY = 0x01D,   /*!< PLL3 Ready Flag */
+    RCM_FLAG_LSERDY  = 0x101,   /*!< LSE Ready Flag */
+    RCM_FLAG_LSIRDY  = 0x201,   /*!< LSI Ready Flag */
+    RCM_FLAG_PINRST  = 0x21A,   /*!< PIN reset flag */
+    RCM_FLAG_PORRST  = 0x21B,   /*!< POR/PDR reset flag */
+    RCM_FLAG_SWRST   = 0x21C,   /*!< Software reset flag */
+    RCM_FLAG_IWDTRST = 0x21D,   /*!< Independent watchdog reset flag */
+    RCM_FLAG_WWDTRST = 0x21E,   /*!< Window watchdog reset flag */
+    RCM_FLAG_LPRRST  = 0x21F    /*!< Low-power reset flag */
 } RCM_FLAG_T;
 
-/**@} end of group RCM_Enumerations*/
+/**@} end of group RCM_Enumerations */
 
 
-/** @addtogroup RCM_Fuctions Fuctions
+/** @defgroup RCM_Functions Functions
   @{
 */
 
-/** Function description */
+/* Function description */
 
-/** RCM Reset */
+/* RCM Reset */
 void RCM_Reset(void);
 
-/** HSE clock */
+/* HSE clock */
 void RCM_ConfigHSE(RCM_HSE_T state);
 uint8_t RCM_WaitHSEReady(void);
 
-/** HSI clock */
+/* HSI clock */
 void RCM_ConfigHSITrim(uint8_t HSITrim);
 void RCM_EnableHSI(void);
 void RCM_DisableHSI(void);
 
-/** LSE and LSI clock */
+/* LSE and LSI clock */
 void RCM_ConfigLSE(RCM_LSE_T state);
 void RCM_EnableLSI(void);
 void RCM_DisableLSI(void);
 
-/** PLL clock */
+/* PLL clock */
 void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf);
 void RCM_EnablePLL(void);
 void RCM_DisablePLL(void);
+#if defined(APM32F10X_CL)
+void RCM_EnablePLL2(void);
+void RCM_DisablePLL2(void);
+void RCM_EnablePLL3(void);
+void RCM_DisablePLL3(void);
+void RCM_ConfigPLLPSC1(RCM_PLLPSC1_SRC_T pllPsc1Src,  RCM_PLLPSC1_DIV_T pllPsc1);
+void RCM_ConfigPLLPSC2(RCM_PLLPSC2_DIV_T pllpsc2);
+void RCM_ConfigPLL2(RCM_PLL2MF_T pll2Mf);
+void RCM_ConfigPLL3(RCM_PLL3MF_T pll3Mf);
+#endif
 
-/** Clock Security System */
+/* Clock Security System */
 void RCM_EnableCSS(void);
 void RCM_DisableCSS(void);
 
@@ -323,26 +480,32 @@ void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock);
 void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect);
 RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void);
 
-/** Config clock prescaler of AHB, APB1, APB2, USB and ADC */
+/* Config clock prescaler of AHB, APB1, APB2, USB and ADC */
 void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv);
 void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div);
 void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div);
+#if defined(APM32F10X_CL)
+void RCM_ConfigI2S2CLK(RCM_I2S2CLK_T i2s2ClkSelect);
+void RCM_ConfigI2S3CLK(RCM_I2S2CLK_T i2s3ClkSelect);
+void RCM_ConfigOTGFSCLK(RCM_OTGFS_DIV_T OTGDiv);
+#else
 void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv);
 void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv);
+#endif
 void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv);
 
-/** RTC clock */
+/* RTC clock */
 void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect);
 void RCM_EnableRTCCLK(void);
 void RCM_DisableRTCCLK(void);
 
-/** Reads the clock frequency */
+/* Reads the clock frequency */
 uint32_t RCM_ReadSYSCLKFreq(void);
 uint32_t RCM_ReadHCLKFreq(void);
-void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2);
+void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2);
 uint32_t RCM_ReadADCCLKFreq(void);
 
-/** Enable or disable Periph Clock */
+/* Enable or disable Periph Clock */
 void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph);
 void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph);
 void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph);
@@ -350,17 +513,21 @@ void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph);
 void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph);
 void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph);
 
-/** Enable or disable Periph Reset */
+/* Enable or disable Periph Reset */
+#if defined(APM32F10X_CL)
+void RCM_EnableAHBPeriphReset(uint32_t AHBPeriph);
+void RCM_DisableAHBPeriphReset(uint32_t AHBPeriph);
+#endif
 void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph);
 void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph);
 void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph);
 void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph);
 
-/** Backup domain reset */
+/* Backup domain reset */
 void RCM_EnableBackupReset(void);
 void RCM_DisableBackupReset(void);
 
-/** Interrupts and flags */
+/* Interrupts and flags */
 void RCM_EnableInterrupt(uint32_t interrupt);
 void RCM_DisableInterrupt(uint32_t interrupt);
 uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag);
@@ -368,9 +535,9 @@ void RCM_ClearStatusFlag(void);
 uint8_t RCM_ReadIntFlag(RCM_INT_T flag);
 void RCM_ClearIntFlag(uint32_t flag);
 
-/**@} end of group RCM_Fuctions*/
-/**@} end of group RCM_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group RCM_Functions */
+/**@} end of group RCM_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the RTC firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_RTC_H
 #define __APM32F10X_RTC_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,47 +42,46 @@ extern "C" {
   @{
 */
 
-/** @addtogroup RTC_Enumerations Enumerations
+/** @defgroup RTC_Enumerations Enumerations
   @{
 */
 
 typedef enum
 {
-    RTC_FLAG_OC    = 0x0020,    //!< RTC Operation Complete flag
-    RTC_FLAG_RSYNC = 0x0008,    //!< Registers Synchronized flag
-    RTC_FLAG_OVR   = 0x0004,    //!< Overflow flag
-    RTC_FLAG_ALR   = 0x0002,    //!< Alarm flag
-    RTC_FLAG_SEC   = 0x0001     //!< Second flag
+    RTC_FLAG_OC    = 0x0020,    /*!< RTC Operation Complete flag */
+    RTC_FLAG_RSYNC = 0x0008,    /*!< Registers Synchronized flag */
+    RTC_FLAG_OVR   = 0x0004,    /*!< Overflow flag */
+    RTC_FLAG_ALR   = 0x0002,    /*!< Alarm flag */
+    RTC_FLAG_SEC   = 0x0001     /*!< Second flag */
 } RTC_FLAG_T;
 
 typedef enum
 {
-    RTC_INT_OVR = 0x0004,       //!< Overflow interrupt
-    RTC_INT_ALR = 0x0002,       //!< Alarm interrupt
-    RTC_INT_SEC = 0x0001        //!< Second interrupt
+    RTC_INT_OVR = 0x0004,       /*!< Overflow interrupt */
+    RTC_INT_ALR = 0x0002,       /*!< Alarm interrupt */
+    RTC_INT_SEC = 0x0001        /*!< Second interrupt */
 } RTC_INT_T;
 
-/**@} end of group RTC_Enumerations*/
-
+/**@} end of group RTC_Enumerations */
 
-/** @addtogroup RTC_Fuctions Fuctions
+/** @defgroup RTC_Functions Functions
   @{
 */
 
-/** Operation modes */
+/* Operation modes */
 void RTC_EnableConfigMode(void);
 void RTC_DisableConfigMode(void);
 
-/** Configuration */
+/* Configuration */
 uint32_t RTC_ReadCounter(void);
 void RTC_ConfigCounter(uint32_t value);
 void RTC_ConfigPrescaler(uint32_t value);
 void RTC_ConfigAlarm(uint32_t value);
 uint32_t RTC_ReadDivider(void);
 void RTC_WaitForLastTask(void);
-void RTC_WaitForSynchor(void);
+void RTC_WaitForSynchro(void);
 
-/** Interrupts and flags */
+/* Interrupts and flags */
 void RTC_EnableInterrupt(uint16_t interrupt);
 void RTC_DisableInterrupt(uint16_t interrupt);
 uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag);
@@ -88,9 +89,9 @@ void RTC_ClearStatusFlag(uint16_t flag);
 uint8_t RTC_ReadIntFlag(RTC_INT_T flag);
 void RTC_ClearIntFlag(uint16_t flag);
 
-/**@} end of group RTC_Fuctions*/
-/**@} end of group RTC_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group RTC_Functions */
+/**@} end of group RTC_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sci2c.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the prototypes,enumeration and macros for the SCI2C(I2C3, I2C4) peripheral
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_SCI2C_H
 #define __APM32F10X_SCI2C_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +42,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup SCI2C_Enumerations Enumerations
+/** @defgroup SCI2C_Enumerations Enumerations
   @{
 */
 
@@ -103,21 +105,21 @@ typedef enum
  */
 typedef enum
 {
-    SCI2C_INT_RFU       = BIT0,         //!< Rx FIFO underflow interrupt
-    SCI2C_INT_RFO       = BIT1,         //!< Rx FIFO onverflow interrupt
-    SCI2C_INT_RFF       = BIT2,         //!< Rx FIFO full interrupt
-    SCI2C_INT_TFO       = BIT3,         //!< Tx FIFO onverflow interrupt
-    SCI2C_INT_TFE       = BIT4,         //!< Tx FIFO empty interrupt
-    SCI2C_INT_RR        = BIT5,         //!< Read request interrupt
-    SCI2C_INT_TA        = BIT6,         //!< Tx abort interrupt
-    SCI2C_INT_RD        = BIT7,         //!< Read done interrupt
-    SCI2C_INT_ACT       = BIT8,         //!< Activity interrupt
-    SCI2C_INT_STPD      = BIT9,         //!< Stop detect interrupt
-    SCI2C_INT_STAD      = BIT10,        //!< Start detect interrupt
-    SCI2C_INT_GC        = BIT11,        //!< Gernal call interrupt
-    SCI2C_INT_RSTAD     = BIT12,        //!< Restart detect interrupt
-    SCI2C_INT_MOH       = BIT13,        //!< Master on hold interrupt
-    SCI2C_INT_ALL       = BIT15         //!< All interrupt
+    SCI2C_INT_RFU       = BIT0,         /*!< Rx FIFO underflow interrupt */
+    SCI2C_INT_RFO       = BIT1,         /*!< Rx FIFO onverflow interrupt */
+    SCI2C_INT_RFF       = BIT2,         /*!< Rx FIFO full interrupt */
+    SCI2C_INT_TFO       = BIT3,         /*!< Tx FIFO onverflow interrupt */
+    SCI2C_INT_TFE       = BIT4,         /*!< Tx FIFO empty interrupt */
+    SCI2C_INT_RR        = BIT5,         /*!< Read request interrupt */
+    SCI2C_INT_TA        = BIT6,         /*!< Tx abort interrupt */
+    SCI2C_INT_RD        = BIT7,         /*!< Read done interrupt */
+    SCI2C_INT_ACT       = BIT8,         /*!< Activity interrupt */
+    SCI2C_INT_STPD      = BIT9,         /*!< Stop detect interrupt */
+    SCI2C_INT_STAD      = BIT10,        /*!< Start detect interrupt */
+    SCI2C_INT_GC        = BIT11,        /*!< Gernal call interrupt */
+    SCI2C_INT_RSTAD     = BIT12,        /*!< Restart detect interrupt */
+    SCI2C_INT_MOH       = BIT13,        /*!< Master on hold interrupt */
+    SCI2C_INT_ALL       = BIT15         /*!< All interrupt */
 } SCI2C_INT_T;
 
 /**
@@ -125,16 +127,16 @@ typedef enum
  */
 typedef enum
 {
-    SCI2C_FLAG_ACT      = BIT0,         //!< Activity flag
-    SCI2C_FLAG_TFNF     = BIT1,         //!< Tx FIFO not full flag
-    SCI2C_FLAG_TFE      = BIT2,         //!< Tx FIFO empty flag
-    SCI2C_FLAG_RFNE     = BIT3,         //!< Rx FIFO not empty flag
-    SCI2C_FLAG_RFF      = BIT4,         //!< Rx FIFO full flag
-    SCI2C_FLAG_MA       = BIT5,         //!< Master activity flag
-    SCI2C_FLAG_SA       = BIT6,         //!< Slave activity flag
-    SCI2C_FLAG_I2CEN    = BIT8 | BIT0,  //!< I2C enable flag
-    SCI2C_FLAG_SDWB     = BIT8 | BIT1,  //!< Slave disable while busy flag
-    SCI2C_FLAG_SRDL     = BIT8 | BIT2   //!< Slave receive data lost flag
+    SCI2C_FLAG_ACT      = BIT0,         /*!< Activity flag */
+    SCI2C_FLAG_TFNF     = BIT1,         /*!< Tx FIFO not full flag */
+    SCI2C_FLAG_TFE      = BIT2,         /*!< Tx FIFO empty flag */
+    SCI2C_FLAG_RFNE     = BIT3,         /*!< Rx FIFO not empty flag */
+    SCI2C_FLAG_RFF      = BIT4,         /*!< Rx FIFO full flag */
+    SCI2C_FLAG_MA       = BIT5,         /*!< Master activity flag */
+    SCI2C_FLAG_SA       = BIT6,         /*!< Slave activity flag */
+    SCI2C_FLAG_I2CEN    = BIT8 | BIT0,  /*!< I2C enable flag */
+    SCI2C_FLAG_SDWB     = BIT8 | BIT1,  /*!< Slave disable while busy flag */
+    SCI2C_FLAG_SRDL     = BIT8 | BIT2   /*!< Slave receive data lost flag */
 } SCI2C_FLAG_T;
 
 /**
@@ -142,22 +144,22 @@ typedef enum
  */
 typedef enum
 {
-    SCI2C_TAS_AD7NA     = BIT0,         //!< 7 bit address mode NACK
-    SCI2C_TAS_AD10FBNA  = BIT1,         //!< 10 bit address mode first byte NACK
-    SCI2C_TAS_AD10SBNA  = BIT2,         //!< 10 bit address mode second byte NACK
-    SCI2C_TAS_TDNA      = BIT3,         //!< Tx data NACK
-    SCI2C_TAS_GCNA      = BIT4,         //!< Gernal call NACK
-    SCI2C_TAS_GCR       = BIT5,         //!< Gernal call read
-    SCI2C_TAS_HSAD      = BIT6,         //!< High speed ack detected
-    SCI2C_TAS_SNR       = BIT7,         //!< Start byte no restart
-    SCI2C_TAS_RNR10B    = BIT8,         //!< Read 10bit address mode when restart disable
-    SCI2C_TAS_MSTDIS    = BIT9,         //!< Master disable
-    SCI2C_TAS_ARBLOST   = BIT10,        //!< Arbitration lost
-    SCI2C_TAS_LFTF      = BIT11,        //!< Slave flush tx FIFO
-    SCI2C_TAS_SAL       = BIT12,        //!< Slave arbitration lost
-    SCI2C_TAS_SRI       = BIT13,        //!< Slave read done
-    SCI2C_TAS_USRARB    = BIT14,        //!< User abort
-    SCI2C_TAS_FLUCNT    = BIT15         //!< Tx flush counter
+    SCI2C_TAS_AD7NA     = BIT0,         /*!< 7 bit address mode NACK */
+    SCI2C_TAS_AD10FBNA  = BIT1,         /*!< 10 bit address mode first byte NACK */
+    SCI2C_TAS_AD10SBNA  = BIT2,         /*!< 10 bit address mode second byte NACK */
+    SCI2C_TAS_TDNA      = BIT3,         /*!< Tx data NACK */
+    SCI2C_TAS_GCNA      = BIT4,         /*!< Gernal call NACK */
+    SCI2C_TAS_GCR       = BIT5,         /*!< Gernal call read */
+    SCI2C_TAS_HSAD      = BIT6,         /*!< High speed ack detected */
+    SCI2C_TAS_SNR       = BIT7,         /*!< Start byte no restart */
+    SCI2C_TAS_RNR10B    = BIT8,         /*!< Read 10bit address mode when restart disable */
+    SCI2C_TAS_MSTDIS    = BIT9,         /*!< Master disable */
+    SCI2C_TAS_ARBLOST   = BIT10,        /*!< Arbitration lost */
+    SCI2C_TAS_LFTF      = BIT11,        /*!< Slave flush tx FIFO */
+    SCI2C_TAS_SAL       = BIT12,        /*!< Slave arbitration lost */
+    SCI2C_TAS_SRI       = BIT13,        /*!< Slave read done */
+    SCI2C_TAS_USRARB    = BIT14,        /*!< User abort */
+    SCI2C_TAS_FLUCNT    = BIT15         /*!< Tx flush counter */
 } SCI2C_TAS_T;
 
 /**
@@ -169,15 +171,13 @@ typedef enum
     SCI2C_DMA_TX = BIT1,
 } SCI2C_DMA_T;
 
-/**@} end of group SCI2C_Enumerations*/
+/**@} end of group SCI2C_Enumerations */
 
-
-/** @addtogroup SCI2C_Macros Macros
+/** @defgroup SCI2C_Macros Macros
   @{
 */
 
-/** Macros description */
-
+/* Macros description */
 #define SCI2C_CTRL1_RESET_VALUE     ((uint32_t)0x3E)
 #define SCI2C_TARADDR_RESET_VALUE   ((uint32_t)0x1055)
 #define SCI2C_SLAADDR_RESET_VALUE   ((uint32_t)0x55)
@@ -206,117 +206,116 @@ typedef enum
 #define SCI2C_HSSSL_RESET_VALUE     ((uint32_t)0x01)
 
 #define SCI2C_FIFO_DEPTH            (0X08)
-/**@} end of group SCI2C_Macros*/
 
+/**@} end of group SCI2C_Macros */
 
-/** @addtogroup SCI2C_Structure Data Structure
+/** @defgroup SCI2C_Structures Structures
   @{
 */
 
 /**
- * @brief Struct description
+ * @brief Structure description
  */
 typedef struct
 {
-    uint16_t            slaveAddr;        //!< Slave address.
-    SCI2C_MODE_T        mode;             //!< Specifies mode, master mode or slave mode
-    SCI2C_SPEED_T       speed;            //!< Specifies speed. Standard speed, fast speed or high speed.
-    uint16_t            clkLowPeriod;     //!< SCL high period
-    uint16_t            clkHighPeriod;    //!< SCL low period
-    uint8_t             rxFifoThreshold;  //!< Rx FIFO threshold
-    uint8_t             txFifoThreshold;  //!< Tx FIFO threshold
-    SCI2C_RESTART_T     restart;          //!< Enable or disable restart
-    SCI2C_ADDR_MODE_T   addrMode;         //!< Address mode. 7-bit or 10-bit mode.
+    uint16_t            slaveAddr;        /*!< Slave address. */
+    SCI2C_MODE_T        mode;             /*!< Specifies mode, master mode or slave mode */
+    SCI2C_SPEED_T       speed;            /*!< Specifies speed. Standard speed, fast speed or high speed. */
+    uint16_t            clkLowPeriod;     /*!< SCL high period */
+    uint16_t            clkHighPeriod;    /*!< SCL low period */
+    uint8_t             rxFifoThreshold;  /*!< Rx FIFO threshold */
+    uint8_t             txFifoThreshold;  /*!< Tx FIFO threshold */
+    SCI2C_RESTART_T     restart;          /*!< Enable or disable restart */
+    SCI2C_ADDR_MODE_T   addrMode;         /*!< Address mode. 7-bit or 10-bit mode. */
 } SCI2C_Config_T;
 
-/**@} end of group SCI2C_Structure*/
-
+/**@} end of group SCI2C_Structure */
 
-/** @addtogroup SCI2C_Fuctions Fuctions
+/** @defgroup SCI2C_Functions Functions
   @{
 */
 
-/** Reset */
-void SCI2C_Reset(SCI2C_T *i2c);
-
-/** Configuration */
-void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig);
-void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig);
-
-/** Stop detect */
-void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c);
-void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c);
-void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c);
-void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c);
-
-/** Restart */
-void SCI2C_EnableRestart(SCI2C_T *i2c);
-void SCI2C_DisableRestart(SCI2C_T *i2c);
-
-/** Speed */
-void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed);
-
-/** Address */
-void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr);
-void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr);
-
-/** Master mode and slave mode */
-void SCI2C_EnableMasterMode(SCI2C_T *i2c);
-void SCI2C_DisableMasterMode(SCI2C_T *i2c);
-void SCI2C_EnableSlaveMode(SCI2C_T *i2c);
-void SCI2C_DisableSlaveMode(SCI2C_T *i2c);
-void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code);
-
-/** Data */
-void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir);
-void SCI2C_TxData(SCI2C_T *i2c, uint8_t data);
-uint8_t SCI2C_RxData(SCI2C_T *i2c);
-void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data);
-
-/** Rx and Tx FIFO */
-uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c);
-uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c);
-void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold);
-void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold);
-
-/** I2C Enable, disable, abort, block */
-void SCI2C_Enable(SCI2C_T *i2c);
-void SCI2C_Disable(SCI2C_T *i2c);
-void SCI2C_Abort(SCI2C_T *i2c);
-void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable);
-
-/** SCL and SDA */
-void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod);
-void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold);
-void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay);
-
-/** ACK and NACK */
-void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable);
-void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable);
-
-/** Abort */
-uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c);
-
-/** DMA */
-void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma);
-void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma);
-void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt);
-void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt);
-
-/** Spike suppression limit */
-void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit);
-
-/** Ingerrupt and flag */
-uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag);
-void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag);
-uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag);
-uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag);
-void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt);
-void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt);
-
-/**@} end of group SCI2C_Fuctions*/
-/**@} end of group SCI2C_Driver*/
-/**@} end of group Peripherals_Library*/
+/* Reset */
+void SCI2C_Reset(SCI2C_T* i2c);
+
+/* Configuration */
+void SCI2C_Config(SCI2C_T* i2c, SCI2C_Config_T* sci2cConfig);
+void SCI2C_ConfigStructInit(SCI2C_Config_T* sci2cConfig);
+
+/* Stop detect */
+void SCI2C_EnableStopDetectAddressed(SCI2C_T* i2c);
+void SCI2C_DisableStopDetectAddressed(SCI2C_T* i2c);
+void SCI2C_EnableStopDetectMasterActivity(SCI2C_T* i2c);
+void SCI2C_DisableStopDetectMasterActivity(SCI2C_T* i2c);
+
+/* Restart */
+void SCI2C_EnableRestart(SCI2C_T* i2c);
+void SCI2C_DisableRestart(SCI2C_T* i2c);
+
+/* Speed */
+void SCI2C_ConfigSpeed(SCI2C_T* i2c, SCI2C_SPEED_T speed);
+
+/* Address */
+void SCI2C_ConfigMasterAddr(SCI2C_T* i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr);
+void SCI2C_ConfigSlaveAddr(SCI2C_T* i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr);
+
+/* Master mode and slave mode */
+void SCI2C_EnableMasterMode(SCI2C_T* i2c);
+void SCI2C_DisableMasterMode(SCI2C_T* i2c);
+void SCI2C_EnableSlaveMode(SCI2C_T* i2c);
+void SCI2C_DisableSlaveMode(SCI2C_T* i2c);
+void SCI2C_ConfigMasterCode(SCI2C_T* i2c, uint8_t code);
+
+/* Data */
+void SCI2C_ConfigDataDir(SCI2C_T* i2c, SCI2C_DATA_DIR_T dir);
+void SCI2C_TxData(SCI2C_T* i2c, uint8_t data);
+uint8_t SCI2C_RxData(SCI2C_T* i2c);
+void SCI2C_ConfigDataRegister(SCI2C_T* i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data);
+
+/* Rx and Tx FIFO */
+uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T* i2c);
+uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T* i2c);
+void SCI2C_ConfigRxFifoThreshold(SCI2C_T* i2c, uint8_t threshold);
+void SCI2C_ConfigTxFifoThreshold(SCI2C_T* i2c, uint8_t threshold);
+
+/* I2C Enable, disable, abort, block */
+void SCI2C_Enable(SCI2C_T* i2c);
+void SCI2C_Disable(SCI2C_T* i2c);
+void SCI2C_Abort(SCI2C_T* i2c);
+void SCI2C_BlockTxCmd(SCI2C_T* i2c, uint8_t enable);
+
+/* SCL and SDA */
+void SCI2C_ConfigClkPeriod(SCI2C_T* i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod);
+void SCI2C_ConfigSDAHoldTime(SCI2C_T* i2c, uint16_t txHold, uint8_t rxHold);
+void SCI2C_ConfigSDADelayTime(SCI2C_T* i2c, uint8_t delay);
+
+/* ACK and NACK */
+void SCI2C_GernalCallAck(SCI2C_T* i2c, uint8_t enable);
+void SCI2C_SlaveDataNackOnly(SCI2C_T* i2c, uint8_t enable);
+
+/* Abort */
+uint32_t SCI2C_ReadTxAbortSource(SCI2C_T* i2c);
+
+/* DMA */
+void SCI2C_EnableDMA(SCI2C_T* i2c, SCI2C_DMA_T dma);
+void SCI2C_DisableDMA(SCI2C_T* i2c, SCI2C_DMA_T dma);
+void SCI2C_ConfigDMATxDataLevel(SCI2C_T* i2c, uint8_t cnt);
+void SCI2C_ConfigDMARxDataLevel(SCI2C_T* i2c, uint8_t cnt);
+
+/* Spike suppression limit */
+void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T* i2c, SCI2C_SPEED_T speed, uint8_t limit);
+
+/* Ingerrupt and flag */
+uint8_t SCI2C_ReadStatusFlag(SCI2C_T* i2c, SCI2C_FLAG_T flag);
+void SCI2C_ClearIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag);
+uint8_t SCI2C_ReadIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag);
+uint8_t SCI2C_ReadRawIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag);
+void SCI2C_EnableInterrupt(SCI2C_T* i2c, uint16_t interrupt);
+void SCI2C_DisableInterrupt(SCI2C_T* i2c, uint16_t interrupt);
+
+/**@} end of group SCI2C_Functions */
+/**@} end of group SCI2C_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_sdio.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the SDIO firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_SDIO_H
 #define __APM32F10X_SDIO_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +42,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup SDIO_Enumerations Enumerations
+/** @defgroup SDIO_Enumerations Enumerations
   @{
 */
 
@@ -259,73 +261,73 @@ typedef enum
     SDIO_READ_WAIT_MODE_DATA2 = 0x00000000
 } SDIO_READ_WAIT_MODE_T;
 
-/**@} end of group SDIO_Enumerations*/
+/**@} end of group SDIO_Enumerations */
 
 
-/** @addtogroup SDIO_Macros Macros
+/** @defgroup SDIO_Macros Macros
   @{
 */
 
-/** ------------ SDIO registers bit address in the alias region ----------- */
+/* ------------ SDIO registers bit address in the alias region ----------- */
 #define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
 
-/** --- CLKCTRL Register ---*/
+/* --- CLKCTRL Register --- */
 
-/** Alias word address of CLKEN bit */
+/* Alias word address of CLKEN bit */
 #define CLKCTRL_OFFSET            (SDIO_OFFSET + 0x04)
 #define CLKEN_BitNumber            0x08
 #define CLKCTRL_CLKEN_BB          (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BitNumber * 4))
 
-/** --- CMD Register ---*/
+/* --- CMD Register --- */
 
-/** Alias word address of SDIOSC bit */
+/* Alias word address of SDIOSC bit */
 #define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
 #define SDIOSC_BitNumber           0x0B
 #define CMD_SDIOSC_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSC_BitNumber * 4))
 
-/** Alias word address of CMDCPEN bit */
+/* Alias word address of CMDCPEN bit */
 #define CMDCPEN_BitNumber          0x0C
 #define CMD_CMDCPEN_BB            (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (CMDCPEN_BitNumber * 4))
 
-/** Alias word address of INTEN bit */
+/* Alias word address of INTEN bit */
 #define INTEN_BitNumber            0x0D
 #define CMD_INTEN_BB              (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (INTEN_BitNumber * 4))
 
-/** Alias word address of ATACMD bit */
+/* Alias word address of ATACMD bit */
 #define ATACMD_BitNumber           0x0E
 #define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
 
-/** --- DCTRL Register ---*/
+/* --- DCTRL Register --- */
 
-/** Alias word address of DMAEN bit */
+/* Alias word address of DMAEN bit */
 #define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
 #define DMAEN_BitNumber            0x03
 #define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
 
-/** Alias word address of RWSTR bit */
+/* Alias word address of RWSTR bit */
 #define RWSTR_BitNumber            0x08
 #define DCTRL_RWSTR_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTR_BitNumber * 4))
 
-/** Alias word address of RWSTOP bit */
+/* Alias word address of RWSTOP bit */
 #define RWSTOP_BitNumber           0x09
 #define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
 
-/** Alias word address of RDWAIT bit */
+/* Alias word address of RDWAIT bit */
 #define RDWAIT_BitNumber           0x0A
 #define DCTRL_RDWAIT_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RDWAIT_BitNumber * 4))
 
-/** Alias word address of SDIOF bit */
+/* Alias word address of SDIOF bit */
 #define SDIOF_BitNumber            0x0B
 #define DCTRL_SDIOF_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOF_BitNumber * 4))
 
-/**@} end of group SDIO_Macros*/
+/**@} end of group SDIO_Macros */
 
-/** @addtogroup SDIO_Structure Data Structure
+/** @defgroup SDIO_Structures Structures
   @{
 */
 
 /**
- * @brief    SDIO Config structure definition
+ * @brief    SDIO Configure structure definition
  */
 typedef struct
 {
@@ -338,7 +340,7 @@ typedef struct
 } SDIO_Config_T;
 
 /**
- * @brief    SDIO CMD Config structure definition
+ * @brief    SDIO CMD Configure structure definition
  */
 typedef struct
 {
@@ -350,7 +352,7 @@ typedef struct
 } SDIO_CmdConfig_T;
 
 /**
- * @brief    SDIO Data Config structure definition
+ * @brief    SDIO Data Configure structure definition
  */
 typedef struct
 {
@@ -362,41 +364,40 @@ typedef struct
     SDIO_DPSM_T                  DPSM;
 } SDIO_DataConfig_T;
 
-/**@} end of group SDIO_Structure*/
-
+/**@} end of group SDIO_Structures */
 
-/** @addtogroup SDIO_Fuctions Fuctions
+/** @defgroup SDIO_Functions Functions
   @{
 */
 
-/** SDIO reset and configuration */
+/* SDIO reset and configuration */
 void SDIO_Reset(void);
-void SDIO_Config(SDIO_Config_T *sdioConfig);
-void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig);
+void SDIO_Config(SDIO_Config_T* sdioConfig);
+void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig);
 void SDIO_EnableClock(void);
 void SDIO_DisableClock(void);
 void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState);
 uint32_t SDIO_ReadPowerState(void);
 
-/** DMA */
+/* DMA */
 void SDIO_EnableDMA(void);
 void SDIO_DisableDMA(void);
 
-/** Command */
-void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig);
-void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdconfig);
+/* Command */
+void SDIO_TxCommand(SDIO_CmdConfig_T* cmdConfig);
+void SDIO_TxCommandStructInit(SDIO_CmdConfig_T* cmdconfig);
 uint8_t SDIO_ReadCommandResponse(void);
 uint32_t SDIO_ReadResponse(SDIO_RES_T res);
 
-/** SDIO data configuration */
-void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig);
-void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig);
+/* SDIO data configuration */
+void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig);
+void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig);
 uint32_t SDIO_ReadDataCounter(void);
 void SDIO_WriteData(uint32_t data);
 uint32_t SDIO_ReadData(void);
 uint32_t SDIO_ReadFIFOCount(void);
 
-/** SDIO mode */
+/* SDIO mode */
 void SDIO_EnableStartReadWait(void);
 void SDIO_DisableStartReadWait(void);
 void SDIO_EnableStopReadWait(void);
@@ -413,7 +414,7 @@ void SDIO_DisableCEATAInterrupt(void);
 void SDIO_EnableTxCEATA(void);
 void SDIO_DisableTxCEATA(void);
 
-/** Interrupt and flags */
+/* Interrupt and flags */
 void SDIO_EnableInterrupt(uint32_t interrupt);
 void SDIO_DisableInterrupt(uint32_t interrupt);
 uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag);
@@ -421,12 +422,12 @@ void SDIO_ClearStatusFlag(uint32_t flag);
 uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag);
 void SDIO_ClearIntFlag(uint32_t flag);
 
-/**@} end of group SDIO_Fuctions*/
-/**@} end of group SDIO_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group SDIO_Functions */
+/**@} end of group SDIO_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __APM32F10X_SDIO_H */
+#endif /*__APM32F10X_SDIO_H */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_smc.h

@@ -0,0 +1,370 @@
+/*!
+ * @file        apm32f10x_smc.h
+ *
+ * @brief       This file contains all the functions prototypes for the SMC firmware library
+ *
+ * @version     V1.0.4
+ *
+ * @date        2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+/* Define to prevent recursive inclusion */
+#ifndef __APM32F10X_SMC_H
+#define __APM32F10X_SMC_H
+
+/* Includes */
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup APM32F10x_StdPeriphDriver
+  @{
+*/
+
+/** @addtogroup SMC_Driver SMC Driver
+  @{
+*/
+
+/** @defgroup SMC_Enumerations Enumerations
+  @{
+*/
+
+/**
+ * @brief SMC NORSRAM_Bank
+ */
+typedef enum
+{
+    SMC_BANK1_NORSRAM_1 = 0x00000000,
+    SMC_BANK1_NORSRAM_2 = 0x00000002,
+    SMC_BANK1_NORSRAM_3 = 0x00000004,
+    SMC_BANK1_NORSRAM_4 = 0x00000006
+} SMC_BANK1_NORSRAM_T;
+
+/**
+ * @brief SMC NAND and PC Card Bank
+ */
+typedef enum
+{
+    SMC_BANK2_NAND   = 0x00000010,
+    SMC_BANK3_NAND   = 0x00000100,
+    SMC_BANK4_PCCARD = 0x00001000
+} SMC_BANK_NAND_T;
+
+/**
+ * @brief SMC_Data_Address_Bus_Multiplexing
+ */
+typedef enum
+{
+    SMC_DATA_ADDRESS_MUX_DISABLE = 0x00000000,
+    SMC_DATA_ADDRESS_MUX_ENABLE  = 0x00000002
+} SMC_DATA_ADDRESS_MUX_T;
+
+/**
+ * @brief SMC_Memory_Type
+ */
+typedef enum
+{
+    SMC_MEMORY_TYPE_SRAM  = 0x00000000,
+    SMC_MEMORY_TYPE_PSRAM = 0x00000004,
+    SMC_MEMORY_TYPE_NOR   = 0x00000008
+} SMC_MEMORY_TYPE_T;
+
+/**
+ * @brief SMC_Data_Width
+ */
+typedef enum
+{
+    SMC_MEMORY_DATA_WIDTH_8BIT  = 0x00000000,
+    SMC_MEMORY_DATA_WIDTH_16BIT = 0x00000010
+} SMC_MEMORY_DATA_WIDTH_T;
+
+/**
+ * @brief SMC_Burst_Access_Mode
+ */
+typedef enum
+{
+    SMC_BURST_ACCESS_MODE_DISABLE = 0x00000000,
+    SMC_BURST_ACCESS_MODE_ENABLE  = 0x00000100
+} SMC_BURST_ACCESS_MODE_T;
+
+/**
+ * @brief SMC_AsynchronousWait
+ */
+typedef enum
+{
+    SMC_ASYNCHRONOUS_WAIT_DISABLE = 0x00000000,
+    SMC_ASYNCHRONOUS_WAIT_ENABLE  = 0x00008000
+} SMC_ASYNCHRONOUS_WAIT_T;
+
+/**
+ * @brief SMC_Wait_Signal_Polarity
+ */
+typedef enum
+{
+    SMC_WAIT_SIGNAL_POLARITY_LOW  = 0x00000000,
+    SMC_WAIT_SIGNAL_POLARITY_HIGH = 0x00000200
+} SMC_WAIT_SIGNAL_POLARITY_T;
+
+/**
+ * @brief SMC_Wrap_Mode
+ */
+typedef enum
+{
+    SMC_WRAP_MODE_DISABLE = 0x00000000,
+    SMC_WRAP_MODE_ENABLE  = 0x00000400
+} SMC_WRAP_MODE_T;
+
+/**
+ * @brief SMC_Wait_Timing
+ */
+typedef enum
+{
+    SMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT = 0x00000000,
+    SMC_WAIT_SIGNAL_ACTIVE_DURING_WAIT = 0x00000800
+} SMC_WAIT_SIGNAL_ACTIVE_T;
+
+/**
+ * @brief SMC_Write_Operation
+ */
+typedef enum
+{
+    SMC_WRITE_OPERATION_DISABLE = 0x00000000,
+    SMC_WRITE_OPERATION_ENABLE  = 0x00001000
+} SMC_WRITE_OPERATION_T;
+
+/**
+ * @brief SMC_Wait_Signal
+ */
+typedef enum
+{
+    SMC_WAITE_SIGNAL_DISABLE = 0x00000000,
+    SMC_WAITE_SIGNAL_ENABLE  = 0x00002000
+} SMC_WAITE_SIGNAL_T;
+
+/**
+ * @brief SMC_Extended_Mode
+ */
+typedef enum
+{
+    SMC_EXTENDEN_MODE_DISABLE = 0x00000000,
+    SMC_EXTENDEN_MODE_ENABLE  = 0x00004000
+} SMC_EXTENDEN_MODE_T;
+
+/**
+ * @brief SMC_Write_Burst
+ */
+typedef enum
+{
+    SMC_WRITE_BURST_DISABLE = 0x00000000,
+    SMC_WRITE_BURST_ENABLE  = 0x00080000
+} SMC_WRITE_BURST_T;
+
+/**
+ * @brief   SMC_WAIT_FEATURE
+ */
+typedef enum
+{
+    SMC_WAIT_FEATURE_DISABLE = 0x00000000,
+    SMC_WAIT_FEATURE_ENABLE  = 0x00000002
+} SMC_WAIT_FEATURE_T;
+
+/**
+ * @brief SMC_ECC
+ */
+typedef enum
+{
+    SMC_ECC_DISABLE = 0x00000000,
+    SMC_ECC_ENABLE  = 0x00000040
+} SMC_ECC_T;
+
+/**
+ * @brief SMC_ECC_Page_Size
+ */
+typedef enum
+{
+    SMC_ECC_PAGE_SIZE_BYTE_256  = 0x00000000,
+    SMC_ECC_PAGE_SIZE_BYTE_512  = 0x00020000,
+    SMC_ECC_PAGE_SIZE_BYTE_1024 = 0x00040000,
+    SMC_ECC_PAGE_SIZE_BYTE_2048 = 0x00060000,
+    SMC_ECC_PAGE_SIZE_BYTE_4096 = 0x00080000,
+    SMC_ECC_PAGE_SIZE_BYTE_8192 = 0x000A0000
+} SMC_ECC_PAGE_SIZE_BYTE_T;
+
+/**
+ * @brief SMC_Access_Mode
+ */
+typedef enum
+{
+    SMC_ACCESS_MODE_A = 0x00000000,
+    SMC_ACCESS_MODE_B = 0x10000000,
+    SMC_ACCESS_MODE_C = 0x20000000,
+    SMC_ACCESS_MODE_D = 0x30000000
+} SMC_ACCESS_MODE_T;
+
+/**
+ * @brief  SMC_Interrupt_sources
+ */
+typedef enum
+{
+    SMC_INT_EDGE_RISING  = 0x00000008,
+    SMC_INT_LEVEL_HIGH   = 0x00000010,
+    SMC_INT_EDGE_FALLING = 0x00000020
+} SMC_INT_T;
+
+/**
+ * @brief  SMC_Flags
+ */
+typedef enum
+{
+    SMC_FLAG_EDGE_RISING  = 0x00000001,
+    SMC_FLAG_LEVEL_HIGH   = 0x00000002,
+    SMC_FLAG_EDGE_FALLING = 0x00000004,
+    SMC_FLAG_FIFO_EMPTY   = 0x00000040
+} SMC_FLAG_T;
+
+/**@} end of group SMC_Enumerations */
+
+/** @defgroup SMC_Structures Structures
+  @{
+*/
+
+/**
+ * @brief Timing parameters for NOR/SRAM Banks
+ */
+typedef struct
+{
+    uint32_t           addressSetupTime;
+    uint32_t           addressHodeTime;
+    uint32_t           dataSetupTime;
+    uint32_t           busTurnaroundTime;
+    uint32_t           clockDivision;
+    uint32_t           dataLatency;
+    SMC_ACCESS_MODE_T accessMode;
+} SMC_NORSRAMTimingConfig_T;
+
+/**
+ * @brief SMC NOR/SRAM Configure structure
+ */
+typedef struct
+{
+    SMC_BANK1_NORSRAM_T        bank;
+    SMC_DATA_ADDRESS_MUX_T     dataAddressMux;
+    SMC_MEMORY_TYPE_T          memoryType;
+    SMC_MEMORY_DATA_WIDTH_T    memoryDataWidth;
+    SMC_BURST_ACCESS_MODE_T    burstAcceesMode;
+    SMC_ASYNCHRONOUS_WAIT_T    asynchronousWait;
+    SMC_WAIT_SIGNAL_POLARITY_T waitSignalPolarity;
+    SMC_WRAP_MODE_T            wrapMode;
+    SMC_WAIT_SIGNAL_ACTIVE_T   waitSignalActive;
+    SMC_WRITE_OPERATION_T      writeOperation;
+    SMC_WAITE_SIGNAL_T         waiteSignal;
+    SMC_EXTENDEN_MODE_T        extendedMode;
+    SMC_WRITE_BURST_T          writeBurst;
+    SMC_NORSRAMTimingConfig_T*   readWriteTimingStruct;
+    SMC_NORSRAMTimingConfig_T*   writeTimingStruct;
+} SMC_NORSRAMConfig_T;
+
+/**
+ * @brief Timing parameters for NAND and PCCARD Banks
+ */
+typedef struct
+{
+    uint32_t setupTime;
+    uint32_t waitSetupTime;
+    uint32_t holdSetupTime;
+    uint32_t HiZSetupTime;
+} SMC_NAND_PCCARDTimingConfig_T;
+
+/**
+ * @brief SMC NAND Configure structure
+ */
+typedef struct
+{
+    SMC_BANK_NAND_T          bank;
+    SMC_WAIT_FEATURE_T       waitFeature;
+    SMC_MEMORY_DATA_WIDTH_T  memoryDataWidth;
+    SMC_ECC_T                ECC;
+    SMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize;
+    uint32_t                  TCLRSetupTime;
+    uint32_t                  TARSetupTime;
+    SMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
+    SMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
+} SMC_NANDConfig_T;
+
+/**
+ * @brief SMC PCCARD Configure structure
+ */
+typedef struct
+{
+    SMC_WAIT_FEATURE_T waitFeature;
+    uint32_t            TCLRSetupTime;
+    uint32_t            TARSetupTime;
+    SMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
+    SMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
+    SMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct;
+} SMC_PCCARDConfig_T;
+
+/**@} end of group SMC_Structures */
+
+/** @defgroup SMC_Functions Functions
+  @{
+*/
+
+/* SMC reset */
+void SMC_ResetNORSRAM(SMC_BANK1_NORSRAM_T bank);
+void SMC_ResetNAND(SMC_BANK_NAND_T bank);
+void SMC_ResetPCCard(void);
+
+/* SMC Configuration */
+void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig);
+void SMC_ConfigNAND(SMC_NANDConfig_T* smcNANDConfig);
+void SMC_ConfigPCCard(SMC_PCCARDConfig_T* smcPCCardConfig);
+void SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T* smcNORSRAMConfig);
+void SMC_ConfigNANDStructInit(SMC_NANDConfig_T* smcNANDConfig);
+void SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T* smcPCCardConfig);
+
+/* SMC bank control */
+void SMC_EnableNORSRAM(SMC_BANK1_NORSRAM_T bank);
+void SMC_DisableNORSRAM(SMC_BANK1_NORSRAM_T bank);
+void SMC_EnableNAND(SMC_BANK_NAND_T bank);
+void SMC_DisableNAND(SMC_BANK_NAND_T bank);
+void SMC_EnablePCCARD(void);
+void SMC_DisablePCCARD(void);
+void SMC_EnableNANDECC(SMC_BANK_NAND_T bank);
+void SMC_DisableNANDECC(SMC_BANK_NAND_T bank);
+uint32_t SMC_ReadECC(SMC_BANK_NAND_T bank);
+
+/* Interrupt and flag */
+void SMC_EnableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt);
+void SMC_DisableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt);
+uint8_t SMC_ReadStatusFlag(SMC_BANK_NAND_T bank, SMC_FLAG_T flag);
+void SMC_ClearStatusFlag(SMC_BANK_NAND_T bank, uint32_t flag);
+uint8_t SMC_ReadIntFlag(SMC_BANK_NAND_T bank, SMC_INT_T flag);
+void SMC_ClearIntFlag(SMC_BANK_NAND_T bank, uint32_t flag);
+
+/**@} end of group SMC_Functions */
+/**@} end of group SMC_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APM32F10X_SMC_H */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_spi.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the SPI firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_SPI_H
 #define __APM32F10X_SPI_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,7 +42,7 @@ extern "C" {
   @{
 */
 
-/** @addtogroup SPI_Enumerations Enumerations
+/** @defgroup SPI_Enumerations Enumerations
   @{
 */
 
@@ -243,7 +245,7 @@ typedef enum
 /**@} end of group SPI_Enumerations*/
 
 
-/** @addtogroup SPI_Structure Data Structure
+/** @addtogroup SPI_Structures Structures
   @{
 */
 
@@ -276,55 +278,55 @@ typedef struct
     I2S_CLKPOL_T        polarity;
 } I2S_Config_T;
 
-/**@} end of group SPI_Structure*/
+/**@} end of group SPI_Structures */
 
-/** @addtogroup SPI_Fuctions Fuctions
+/** @defgroup SPI_Functions Functions
   @{
 */
 
-/** Reset and Configuration */
-void SPI_I2S_Reset(SPI_T *spi);
-void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig);
-void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig);
-void SPI_ConfigStructInit(SPI_Config_T *spiConfig);
-void I2S_ConfigStructInit(I2S_Config_T *i2sConfig);
-void SPI_Enable(SPI_T *spi);
-void SPI_Disable(SPI_T *spi);
-void I2S_Enable(SPI_T *spi);
-void I2S_Disable(SPI_T *spi);
-
-void SPI_I2S_TxData(SPI_T *spi, uint16_t data);
-uint16_t SPI_I2S_RxData(SPI_T *spi);
-void SPI_SetSoftwareNSS(SPI_T *spi);
-void SPI_ResetSoftwareNSS(SPI_T *spi);
-void SPI_EnableSSOutput(SPI_T *spi);
-void SPI_DisableSSOutput(SPI_T *spi);
-void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length);
-
-/** DMA */
-void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq);
-void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq);
-
-/** CRC */
-void SPI_TxCRC(SPI_T *spi);
-void SPI_EnableCRC(SPI_T *spi);
-void SPI_DisableCRC(SPI_T *spi);
-uint16_t SPI_ReadTxCRC(SPI_T *spi);
-uint16_t SPI_ReadRxCRC(SPI_T *spi);
-uint16_t SPI_ReadCRCPolynomial(SPI_T *spi);
-void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction);
-
-/** Interrupts and flag */
-void SPI_I2S_EnableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt);
-void SPI_I2S_DisableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt);
-uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag);
-void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag);
-uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag);
-void SPI_I2S_ClearIntFlag(SPI_T *spi, SPI_I2S_INT_T flag);
-
-/**@} end of group SPI_Fuctions*/
-/**@} end of group SPI_Driver*/
-/**@} end of group Peripherals_Library*/
+/* Reset and Configuration */
+void SPI_I2S_Reset(SPI_T* spi);
+void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig);
+void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig);
+void SPI_ConfigStructInit(SPI_Config_T* spiConfig);
+void I2S_ConfigStructInit(I2S_Config_T* i2sConfig);
+void SPI_Enable(SPI_T* spi);
+void SPI_Disable(SPI_T* spi);
+void I2S_Enable(SPI_T* spi);
+void I2S_Disable(SPI_T* spi);
+
+void SPI_I2S_TxData(SPI_T* spi, uint16_t data);
+uint16_t SPI_I2S_RxData(SPI_T* spi);
+void SPI_SetSoftwareNSS(SPI_T* spi);
+void SPI_ResetSoftwareNSS(SPI_T* spi);
+void SPI_EnableSSOutput(SPI_T* spi);
+void SPI_DisableSSOutput(SPI_T* spi);
+void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length);
+
+/* DMA */
+void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq);
+void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq);
+
+/* CRC */
+void SPI_TxCRC(SPI_T* spi);
+void SPI_EnableCRC(SPI_T* spi);
+void SPI_DisableCRC(SPI_T* spi);
+uint16_t SPI_ReadTxCRC(SPI_T* spi);
+uint16_t SPI_ReadRxCRC(SPI_T* spi);
+uint16_t SPI_ReadCRCPolynomial(SPI_T* spi);
+void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction);
+
+/* Interrupts and flag */
+void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt);
+void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt);
+uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
+void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag);
+uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag);
+void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag);
+
+/**@} end of group SPI_Functions */
+/**@} end of group SPI_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_tmr.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the TMR firmware library.
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,31 +15,33 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
  *  and limitations under the License.
  */
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_TMR_H
 #define __APM32F10X_TMR_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
-/** @addtogroup TMR_Driver  TMR Driver
+/** @addtogroup TMR_Driver TMR Driver
   @{
 */
 
-/** @addtogroup TMR_Enumerations Enumerations
+/** @defgroup TMR_Enumerations Enumerations
   @{
 */
 
@@ -480,26 +482,26 @@ typedef enum
     TMR_FLAG_CC4RC   = 0x1000
 } TMR_FLAG_T;
 
-/**@} end of group TMR_Enumerations*/
+/**@} end of group TMR_Enumerations */
 
-/** @addtogroup TMR_Structure Data Structure
+/** @defgroup TMR_Structures Structures
   @{
 */
 
 /**
- * @brief    TMR Config struct definition
+ * @brief    TMR Base Configure structure definition
  */
 typedef struct
 {
     TMR_COUNTER_MODE_T     countMode;
     TMR_CLOCK_DIV_T        clockDivision;
-    uint16_t               period;            //!< This must between 0x0000 and 0xFFFF
-    uint16_t               division;          //!< This must between 0x0000 and 0xFFFF
-    uint8_t                repetitionCounter; //!< This must between 0x00 and 0xFF, only for TMR1 and TMR8.
+    uint16_t               period;            /*!< This must between 0x0000 and 0xFFFF */
+    uint16_t               division;          /*!< This must between 0x0000 and 0xFFFF */
+    uint8_t                repetitionCounter; /*!< This must between 0x00 and 0xFF, only for TMR1 and TMR8. */
 } TMR_BaseConfig_T; ;
 
 /**
- * @brief    TMR Config struct definition
+ * @brief    TMR Output Compare Configure structure definition
  */
 typedef struct
 {
@@ -510,7 +512,7 @@ typedef struct
     TMR_OC_NPOLARITY_T     nPolarity;
     TMR_OC_IDLE_STATE_T    idleState;
     TMR_OC_NIDLE_STATE_T   nIdleState;
-    uint16_t               pulse;     //!< This must between 0x0000 and 0xFFFF
+    uint16_t               pulse;     /*!< This must between 0x0000 and 0xFFFF */
 } TMR_OCConfig_T;
 
 /**
@@ -528,7 +530,7 @@ typedef struct
 } TMR_BDTConfig_T;
 
 /**
- * @brief    TMR Input Capture Config struct definition
+ * @brief    TMR Input Capture Configure structure definition
  */
 typedef struct
 {
@@ -536,135 +538,137 @@ typedef struct
     TMR_IC_POLARITY_T      polarity;
     TMR_IC_SELECTION_T     selection;
     TMR_IC_PSC_T           prescaler;
-    uint16_t               filter;    //!< This must between 0x00 and 0x0F
+    uint16_t               filter;    /*!< This must between 0x00 and 0x0F */
 } TMR_ICConfig_T;
 
-/**@} end of group TMR_Structure*/
+/**@} end of group TMR_Structures */
 
-/** @addtogroup  TMR_Fuctions Fuctions
+/** @defgroup  TMR_Functions Functions
   @{
 */
 
-/** Reset and Configuration */
-void TMR_Reset(TMR_T *tmr);
-void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig);
-void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
-void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
-void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
-void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig);
-void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig);
-void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig);
-void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig);
-void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig);
-void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig);
-void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig);
-void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode);
-void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision);
-void TMR_Enable(TMR_T *tmr);
-void TMR_Disable(TMR_T *tmr);
-
-/** PWM Configuration */
-void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig);
-void TMR_EnablePWMOutputs(TMR_T *tmr);
-void TMR_DisablePWMOutputs(TMR_T *tmr);
-
-/** DMA */
-void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
-void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource);
-void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource);
-
-/** Configuration */
-void TMR_ConfigInternalClock(TMR_T *tmr);
-void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource);
-void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource,
+/* Reset and Configuration */
+void TMR_Reset(TMR_T* tmr);
+void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig);
+void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OCConfig);
+void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OCConfig);
+void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OCConfig);
+void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OCConfig);
+void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig);
+void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig);
+void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig);
+void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig);
+void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig);
+void TMR_ConfigBDTStructInit(TMR_BDTConfig_T* BDTConfig);
+void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode);
+void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision);
+void TMR_Enable(TMR_T* tmr);
+void TMR_Disable(TMR_T* tmr);
+
+/* PWM Configuration */
+void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig);
+void TMR_EnablePWMOutputs(TMR_T* tmr);
+void TMR_DisablePWMOutputs(TMR_T* tmr);
+
+/* DMA */
+void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
+void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource);
+void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource);
+
+/* Configuration */
+void TMR_ConfigInternalClock(TMR_T* tmr);
+void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource);
+void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
                                  TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
-void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
+void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
                              TMR_EXTTRG_POL_T polarity, uint16_t filter);
-void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
+void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
                              TMR_EXTTRG_POL_T polarity, uint16_t filter);
-void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
+void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
                    TMR_EXTTRG_POL_T polarity, uint16_t filter);
-void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode);
-void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode);
-void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
-void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
+void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode);
+void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode);
+void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
+void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
                                TMR_IC_POLARITY_T IC2Polarity);
-void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
-void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
-void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
-void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction);
-void TMR_EnableAutoReload(TMR_T *tmr);
-void TMR_DisableAutoReload(TMR_T *tmr);
-void TMR_EnableSelectCOM(TMR_T *tmr);
-void TMR_DisableSelectCOM(TMR_T *tmr);
-void TMR_EnableCCDMA(TMR_T *tmr);
-void TMR_DisableCCDMA(TMR_T *tmr);
-void TMR_EnableCCPreload(TMR_T *tmr);
-void TMR_DisableCCPreload(TMR_T *tmr);
-void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
-void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
-void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
-void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload);
-void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
-void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
-void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
-void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast);
-void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
-void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
-void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
-void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear);
-void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
-void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity);
-void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
-void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity);
-void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
-void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T OCNPolarity);
-void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T OCPolarity);
-void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
-void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
-void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
-void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel);
-void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
-void TMR_EnableUpdate(TMR_T *tmr);
-void TMR_DisableUpdate(TMR_T *tmr);
-void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource);
-void TMR_EnableHallSensor(TMR_T *tmr);
-void TMR_DisableHallSensor(TMR_T *tmr);
-void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource);
-void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode);
-void TMR_EnableMasterSlaveMode(TMR_T *tmr);
-void TMR_DisableMasterSlaveMode(TMR_T *tmr);
-void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter);
-void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload);
-void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1);
-void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2);
-void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3);
-void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4);
-void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
-void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
-void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
-void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler);
-uint16_t TMR_ReadCaputer1(TMR_T *tmr);
-uint16_t TMR_ReadCaputer2(TMR_T *tmr);
-uint16_t TMR_ReadCaputer3(TMR_T *tmr);
-uint16_t TMR_ReadCaputer4(TMR_T *tmr);
-uint16_t TMR_ReadCounter(TMR_T *tmr);
-uint16_t TMR_ReadPrescaler(TMR_T *tmr);
-
-/** Interrupts and Event */
-void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt);
-void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt);
-void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources);
-
-/** flags */
-uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag);
-void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag);
-uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag);
-void TMR_ClearIntFlag(TMR_T *tmr, uint16_t flag);
-
-/**@} end of group TMR_Fuctions*/
-/**@} end of group TMR_Driver*/
-/**@} end of group Peripherals_Library*/
+void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction);
+void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction);
+void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction);
+void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction);
+void TMR_EnableAutoReload(TMR_T* tmr);
+void TMR_DisableAutoReload(TMR_T* tmr);
+void TMR_EnableSelectCOM(TMR_T* tmr);
+void TMR_DisableSelectCOM(TMR_T* tmr);
+void TMR_EnableCCDMA(TMR_T* tmr);
+void TMR_DisableCCDMA(TMR_T* tmr);
+void TMR_EnableCCPreload(TMR_T* tmr);
+void TMR_DisableCCPreload(TMR_T* tmr);
+void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
+void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
+void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
+void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
+void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
+void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
+void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
+void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
+void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
+void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
+void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
+void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
+void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
+void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
+void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
+void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
+void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
+void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
+void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
+void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel);
+void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel);
+void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel);
+void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel);
+void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
+void TMR_EnableUpdate(TMR_T* tmr);
+void TMR_DisableUpdate(TMR_T* tmr);
+void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource);
+void TMR_EnableHallSensor(TMR_T* tmr);
+void TMR_DisableHallSensor(TMR_T* tmr);
+
+void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource);
+void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode);
+void TMR_EnableMasterSlaveMode(TMR_T* tmr);
+void TMR_DisableMasterSlaveMode(TMR_T* tmr);
+void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter);
+void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload);
+void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1);
+void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2);
+void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3);
+void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4);
+void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
+void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
+void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
+void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
+
+uint16_t TMR_ReadCaputer1(TMR_T* tmr);
+uint16_t TMR_ReadCaputer2(TMR_T* tmr);
+uint16_t TMR_ReadCaputer3(TMR_T* tmr);
+uint16_t TMR_ReadCaputer4(TMR_T* tmr);
+uint16_t TMR_ReadCounter(TMR_T* tmr);
+uint16_t TMR_ReadPrescaler(TMR_T* tmr);
+
+/* Interrupts and Event */
+void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt);
+void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt);
+void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources);
+
+/* flags */
+uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag);
+void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag);
+uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag);
+void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag);
+
+/**@} end of group TMR_Functions */
+/**@} end of group TMR_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_usart.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the USART firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,16 +23,18 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_USART_H
 #define __APM32F10X_USART_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -40,12 +42,12 @@ extern "C" {
   @{
 */
 
-/** @addtogroup USART_Enumerations Enumerations
+/** @defgroup USART_Enumerations Enumerations
   @{
 */
 
 /**
- * @brief   USART Word Length define
+ * @brief   USART Word Length definition
  */
 typedef enum
 {
@@ -54,7 +56,7 @@ typedef enum
 } USART_WORD_LEN_T;
 
 /**
- * @brief   USART Stop bits define
+ * @brief   USART Stop bits definition
  */
 typedef enum
 {
@@ -65,7 +67,7 @@ typedef enum
 } USART_STOP_BIT_T;
 
 /**
- * @brief   USART Parity define
+ * @brief   USART Parity definition
  */
 typedef enum
 {
@@ -75,7 +77,7 @@ typedef enum
 } USART_PARITY_T;
 
 /**
- * @brief   USART mode define
+ * @brief   USART mode definition
  */
 typedef enum
 {
@@ -85,7 +87,7 @@ typedef enum
 } USART_MODE_T;
 
 /**
- * @brief   USART hardware flow control define
+ * @brief   USART hardware flow control definition
  */
 typedef enum
 {
@@ -105,7 +107,7 @@ typedef enum
 } USART_CLKEN_T;
 
 /**
- * @brief   USART Clock polarity define
+ * @brief   USART Clock polarity definition
  */
 typedef enum
 {
@@ -114,7 +116,7 @@ typedef enum
 } USART_CLKPOL_T;
 
 /**
- * @brief   USART Clock phase define
+ * @brief   USART Clock phase definition
  */
 typedef enum
 {
@@ -123,7 +125,7 @@ typedef enum
 } USART_CLKPHA_T;
 
 /**
- * @brief   USART Last bit clock pulse enable
+ * @brief   USART Last bit clock pulse definition
  */
 typedef enum
 {
@@ -187,7 +189,7 @@ typedef enum
 } USART_IRDALP_T;
 
 /**
- * @brief   USART flag define
+ * @brief   USART flag definition
  */
 typedef enum
 {
@@ -203,105 +205,105 @@ typedef enum
     USART_FLAG_PE        = 0x0001
 } USART_FLAG_T;
 
-/**@} end of group USART_Enumerations*/
+/**@} end of group USART_Enumerations */
 
-/** @addtogroup USART_Structure Data Structure
+/** @defgroup USART_Structures Structures
   @{
 */
 
 /**
- * @brief   USART Config struct definition
+ * @brief   USART Configure structure definition
  */
 typedef struct
 {
-    uint32_t                  baudRate;          //!< Specifies the baud rate
-    USART_WORD_LEN_T          wordLength;        //!< Specifies the word length
-    USART_STOP_BIT_T          stopBits;          //!< Specifies the stop bits
-    USART_PARITY_T            parity;            //!< Specifies the parity
-    USART_MODE_T              mode;              //!< Specifies the mode
-    USART_HARDWARE_FLOW_T     hardwareFlow;      //!< Specifies the hardware flow control
+    uint32_t                  baudRate;          /*!< Specifies the baud rate */
+    USART_WORD_LEN_T          wordLength;        /*!< Specifies the word length */
+    USART_STOP_BIT_T          stopBits;          /*!< Specifies the stop bits */
+    USART_PARITY_T            parity;            /*!< Specifies the parity */
+    USART_MODE_T              mode;              /*!< Specifies the mode */
+    USART_HARDWARE_FLOW_T     hardwareFlow;      /*!< Specifies the hardware flow control */
 } USART_Config_T;
 
 /**
- * @brief   USART synchronous communication clock config struct definition
+ * @brief   USART synchronous communication clock configure structure definition
  */
 typedef struct
 {
-    USART_CLKEN_T             clock;             //!< Enable or Disable Clock
-    USART_CLKPOL_T            polarity;          //!< Specifies the clock polarity
-    USART_CLKPHA_T            phase;             //!< Specifies the clock phase
-    USART_LBCP_T              lastBit;           //!< Enable or Disable last bit clock
+    USART_CLKEN_T             clock;             /*!< Enable or Disable Clock */
+    USART_CLKPOL_T            polarity;          /*!< Specifies the clock polarity */
+    USART_CLKPHA_T            phase;             /*!< Specifies the clock phase */
+    USART_LBCP_T              lastBit;           /*!< Enable or Disable last bit clock */
 } USART_ClockConfig_T;
 
-/**@} end of group USART_Structure*/
+/**@} end of group USART_Structures */
 
-/** @addtogroup USART_Fuctions Fuctions
+/** @defgroup USART_Functions Functions
   @{
 */
 
-/** USART Reset and Configuration */
-void USART_Reset(USART_T *usart);
-void USART_Config(USART_T *uart, USART_Config_T *usartConfig);
-void USART_ConfigStructInit(USART_Config_T *usartConfig);
-void USART_Address(USART_T *usart, uint8_t address);
-void USART_Enable(USART_T *usart);
-void USART_Disable(USART_T *usart);
-
-/** Clock communication */
-void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig);
-void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig);
-
-/** DMA mode */
-void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq);
-void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq);
-
-/** Mute mode */
-void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup);
-void USART_EnableMuteMode(USART_T *usart);
-void USART_DisableMuteMode(USART_T *usart);
-
-/** LIN mode */
-void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length);
-void USART_EnableLIN(USART_T *usart);
-void USART_DisableLIN(USART_T *usart);
-
-/** Transmit and receive */
-void USART_EnableTx(USART_T *usart);
-void USART_DisableTx(USART_T *usart);
-void USART_EnableRx(USART_T *usart);
-void USART_DisableRx(USART_T *usart);
-void USART_TxData(USART_T *usart, uint16_t data);
-uint16_t USART_RxData(USART_T *usart);
-void USART_TxBreak(USART_T *usart);
-
-/** Smartcard mode */
-void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime);
-void USART_ConfigPrescaler(USART_T *usart, uint8_t div);
-void USART_EnableSmartCard(USART_T *usart);
-void USART_DisableSmartCard(USART_T *usart);
-void USART_EnableSmartCardNACK(USART_T *usart);
-void USART_DisableSmartCardNACK(USART_T *usart);
-
-/** Half-duplex mode  */
-void USART_EnableHalfDuplex(USART_T *usart);
-void USART_DisableHalfDuplex(USART_T *usart);
-
-/** IrDA mode */
-void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode);
-void USART_EnableIrDA(USART_T *usart);
-void USART_DisableIrDA(USART_T *usart);
-
-/** Interrupt and flag */
-void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt);
-void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt);
-uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag);
-void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag);
-uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag);
-void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag);
-
-/**@} end of group USART_Fuctions*/
-/**@} end of group USART_Driver*/
-/**@} end of group Peripherals_Library*/
+/* USART Reset and Configuration */
+void USART_Reset(USART_T* usart);
+void USART_Config(USART_T* uart, USART_Config_T* usartConfig);
+void USART_ConfigStructInit(USART_Config_T* usartConfig);
+void USART_Address(USART_T* usart, uint8_t address);
+void USART_Enable(USART_T* usart);
+void USART_Disable(USART_T* usart);
+
+/* Clock communication */
+void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig);
+void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig);
+
+/* DMA mode */
+void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq);
+void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq);
+
+/* Mute mode */
+void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup);
+void USART_EnableMuteMode(USART_T* usart);
+void USART_DisableMuteMode(USART_T* usart);
+
+/* LIN mode */
+void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length);
+void USART_EnableLIN(USART_T* usart);
+void USART_DisableLIN(USART_T* usart);
+
+/* Transmit and receive */
+void USART_EnableTx(USART_T* usart);
+void USART_DisableTx(USART_T* usart);
+void USART_EnableRx(USART_T* usart);
+void USART_DisableRx(USART_T* usart);
+void USART_TxData(USART_T* usart, uint16_t data);
+uint16_t USART_RxData(USART_T* usart);
+void USART_TxBreak(USART_T* usart);
+
+/* Smartcard mode */
+void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime);
+void USART_ConfigPrescaler(USART_T* usart, uint8_t div);
+void USART_EnableSmartCard(USART_T* usart);
+void USART_DisableSmartCard(USART_T* usart);
+void USART_EnableSmartCardNACK(USART_T* usart);
+void USART_DisableSmartCardNACK(USART_T* usart);
+
+/* Half-duplex mode  */
+void USART_EnableHalfDuplex(USART_T* usart);
+void USART_DisableHalfDuplex(USART_T* usart);
+
+/* IrDA mode */
+void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode);
+void USART_EnableIrDA(USART_T* usart);
+void USART_DisableIrDA(USART_T* usart);
+
+/* Interrupt and flag */
+void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt);
+void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt);
+uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag);
+void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag);
+uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag);
+void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag);
+
+/**@} end of group USART_Functions */
+/**@} end of group USART_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_wwdt.h

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions prototypes for the WWDT firmware library
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,29 +23,31 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __APM32F10X_WWDT_H
 #define __APM32F10X_WWDT_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "apm32f10x.h"
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
-/** @addtogroup WWDT_Driver  WWDT Driver
+/** @addtogroup WWDT_Driver WWDT Driver
   @{
 */
 
-/** @addtogroup  WWDT_Enumerations Enumerations
+/** @defgroup  WWDT_Enumerations Enumerations
   @{
 */
 
 /**
- * @brief    WWDT Timebase(Prescaler) define
+ * @brief    WWDT Timebase(Prescaler) definition
  */
 typedef enum
 {
@@ -55,35 +57,35 @@ typedef enum
     WWDT_TIME_BASE_8 = 0x00000180
 } WWDT_TIME_BASE_T;
 
-/**@} end of group WWDT_Enumerations*/
+/**@} end of group WWDT_Enumerations */
 
-/** @addtogroup  WWDT_Fuctions Fuctions
+/** @defgroup  WWDT_Functions Functions
   @{
 */
 
-/** WWDT reset */
+/* WWDT reset */
 void WWDT_Reset(void);
 
-/** Config WWDT Timebase */
+/* Configure WWDT Timebase */
 void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase);
 
-/** Config Window Data */
+/* Configure Window Data */
 void WWDT_ConfigWindowData(uint8_t windowData);
 
-/** Config Couter */
+/* Configure Couter */
 void WWDT_ConfigCounter(uint8_t counter);
 
-/** Enable WWDT and Early Wakeup interrupt */
+/* Enable WWDT and Early Wakeup interrupt */
 void WWDT_EnableEWI(void);
 void WWDT_Enable(uint8_t count);
 
-/** Read Flag and Clear Flag */
+/* Read Flag and Clear Flag */
 uint8_t WWDT_ReadFlag(void);
 void WWDT_ClearFlag(void);
 
-/**@} end of group WWDT_Fuctions*/
-/**@} end of group WWDT_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group WWDT_Functions */
+/**@} end of group WWDT_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */
 
 #ifdef __cplusplus
 }

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the ADC firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,15 +26,16 @@
 #include "apm32f10x_adc.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup ADC_Driver ADC Driver
+  * @brief ADC driver modules
   @{
 */
 
-/** @addtogroup ADC_Fuctions Fuctions
+/** @defgroup ADC_Functions Functions
   @{
 */
 
@@ -47,7 +48,7 @@
  *
  * @note        adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_Reset(ADC_T *adc)
+void ADC_Reset(ADC_T* adc)
 {
     if (adc == ADC1)
     {
@@ -77,7 +78,7 @@ void ADC_Reset(ADC_T *adc)
  *
  * @note        adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig)
+void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig)
 {
     uint32_t reg;
 
@@ -107,7 +108,7 @@ void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig)
  *
  * @retval      None
  */
-void ADC_ConfigStructInit(ADC_Config_T *adcConfig)
+void ADC_ConfigStructInit(ADC_Config_T* adcConfig)
 {
     adcConfig->mode = ADC_MODE_INDEPENDENT;
     adcConfig->scanConvMode = DISABLE;
@@ -126,7 +127,7 @@ void ADC_ConfigStructInit(ADC_Config_T *adcConfig)
  *
  * @note        adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_Enable(ADC_T *adc)
+void ADC_Enable(ADC_T* adc)
 {
     adc->CTRL2_B.ADCEN = BIT_SET;
 }
@@ -140,7 +141,7 @@ void ADC_Enable(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_Disable(ADC_T *adc)
+void ADC_Disable(ADC_T* adc)
 {
     adc->CTRL2_B.ADCEN = BIT_RESET;
 }
@@ -154,7 +155,7 @@ void ADC_Disable(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableDMA(ADC_T *adc)
+void ADC_EnableDMA(ADC_T* adc)
 {
     adc->CTRL2_B.DMAEN = BIT_SET;
 }
@@ -168,7 +169,7 @@ void ADC_EnableDMA(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableDMA(ADC_T *adc)
+void ADC_DisableDMA(ADC_T* adc)
 {
     adc->CTRL2_B.DMAEN = BIT_RESET;
 }
@@ -182,7 +183,7 @@ void ADC_DisableDMA(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ResetCalibration(ADC_T *adc)
+void ADC_ResetCalibration(ADC_T* adc)
 {
     adc->CTRL2_B.CALRST = BIT_SET;
 }
@@ -196,7 +197,7 @@ void ADC_ResetCalibration(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc)
+uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc)
 {
     uint8_t ret;
     ret = (adc->CTRL2_B.CALRST) ? BIT_SET : BIT_RESET;
@@ -212,7 +213,7 @@ uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_StartCalibration(ADC_T *adc)
+void ADC_StartCalibration(ADC_T* adc)
 {
     adc->CTRL2_B.CAL = BIT_SET;
 }
@@ -226,7 +227,7 @@ void ADC_StartCalibration(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc)
+uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc)
 {
     uint8_t ret;
     ret = (adc->CTRL2_B.CAL) ? BIT_SET : BIT_RESET;
@@ -242,7 +243,7 @@ uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableSoftwareStartConv(ADC_T *adc)
+void ADC_EnableSoftwareStartConv(ADC_T* adc)
 {
     adc->CTRL2 |= 0x00500000;
 }
@@ -256,7 +257,7 @@ void ADC_EnableSoftwareStartConv(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableSoftwareStartConv(ADC_T *adc)
+void ADC_DisableSoftwareStartConv(ADC_T* adc)
 {
     adc->CTRL2 &= 0xFFAFFFFF;
 }
@@ -270,7 +271,7 @@ void ADC_DisableSoftwareStartConv(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc)
+uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc)
 {
     uint8_t ret;
     ret = (adc->CTRL2_B.REGSWSC) ? BIT_SET : BIT_RESET;
@@ -289,7 +290,7 @@ uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number)
+void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number)
 {
     adc->CTRL1_B.DISCNUMCFG |= number - 1;
 }
@@ -303,7 +304,7 @@ void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableDiscMode(ADC_T *adc)
+void ADC_EnableDiscMode(ADC_T* adc)
 {
     adc->CTRL1_B.REGDISCEN = BIT_SET;
 }
@@ -317,7 +318,7 @@ void ADC_EnableDiscMode(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableDiscMode(ADC_T *adc)
+void ADC_DisableDiscMode(ADC_T* adc)
 {
     adc->CTRL1_B.REGDISCEN = BIT_RESET;
 }
@@ -366,7 +367,7 @@ void ADC_DisableDiscMode(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
+void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
 {
     uint32_t temp1 = 0;
     uint32_t temp2 = 0;
@@ -427,7 +428,7 @@ void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableExternalTrigConv(ADC_T *adc)
+void ADC_EnableExternalTrigConv(ADC_T* adc)
 {
     adc->CTRL2_B.REGEXTTRGEN = BIT_SET;
 }
@@ -441,7 +442,7 @@ void ADC_EnableExternalTrigConv(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableExternalTrigConv(ADC_T *adc)
+void ADC_DisableExternalTrigConv(ADC_T* adc)
 {
     adc->CTRL2_B.REGEXTTRGEN = BIT_RESET;
 }
@@ -455,7 +456,7 @@ void ADC_DisableExternalTrigConv(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint16_t ADC_ReadConversionValue(ADC_T *adc)
+uint16_t ADC_ReadConversionValue(ADC_T* adc)
 {
     return (uint16_t) adc->REGDATA;
 }
@@ -469,9 +470,9 @@ uint16_t ADC_ReadConversionValue(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc)
+uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc)
 {
-    return (*(__IOM uint32_t *) RDG_ADDRESS);
+    return (*(__IOM uint32_t*) RDG_ADDRESS);
 }
 
 /*!
@@ -483,7 +484,7 @@ uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableAutoInjectedConv(ADC_T *adc)
+void ADC_EnableAutoInjectedConv(ADC_T* adc)
 {
     adc->CTRL1_B.INJGACEN = BIT_SET;
 }
@@ -497,7 +498,7 @@ void ADC_EnableAutoInjectedConv(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableAutoInjectedConv(ADC_T *adc)
+void ADC_DisableAutoInjectedConv(ADC_T* adc)
 {
     adc->CTRL1_B.INJGACEN = BIT_RESET;
 }
@@ -511,7 +512,7 @@ void ADC_DisableAutoInjectedConv(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableInjectedDiscMode(ADC_T *adc)
+void ADC_EnableInjectedDiscMode(ADC_T* adc)
 {
     adc->CTRL1_B.INJDISCEN = BIT_SET;
 }
@@ -525,7 +526,7 @@ void ADC_EnableInjectedDiscMode(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableInjectedDiscMode(ADC_T *adc)
+void ADC_DisableInjectedDiscMode(ADC_T* adc)
 {
     adc->CTRL1_B.INJDISCEN = BIT_RESET;
 }
@@ -558,7 +559,7 @@ void ADC_DisableInjectedDiscMode(ADC_T *adc)
  *
  * @note    adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv)
+void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv)
 {
     adc->CTRL2_B.INJGEXTTRGSEL = RESET;
     adc->CTRL2_B.INJGEXTTRGSEL |= extTrigInjecConv;
@@ -573,7 +574,7 @@ void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T ex
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableExternalTrigInjectedConv(ADC_T *adc)
+void ADC_EnableExternalTrigInjectedConv(ADC_T* adc)
 {
     adc->CTRL2_B.INJEXTTRGEN = BIT_SET;
 }
@@ -587,7 +588,7 @@ void ADC_EnableExternalTrigInjectedConv(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableExternalTrigInjectedConv(ADC_T *adc)
+void ADC_DisableExternalTrigInjectedConv(ADC_T* adc)
 {
     adc->CTRL2_B.INJEXTTRGEN = BIT_RESET;
 }
@@ -601,7 +602,7 @@ void ADC_DisableExternalTrigInjectedConv(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc)
+void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc)
 {
     adc->CTRL2_B.INJEXTTRGEN = BIT_SET;
     adc->CTRL2_B.INJSWSC = BIT_SET;
@@ -616,7 +617,7 @@ void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc)
+void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc)
 {
     adc->CTRL2_B.INJEXTTRGEN = BIT_RESET;
     adc->CTRL2_B.INJSWSC = BIT_RESET;
@@ -631,7 +632,7 @@ void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc)
+uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc)
 {
     uint8_t ret;
     ret = (adc->CTRL2_B.INJSWSC) ? BIT_SET : BIT_RESET;
@@ -682,7 +683,7 @@ uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
+void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
 {
     uint32_t temp1 = 0;
     uint32_t temp2 = 0;
@@ -726,7 +727,7 @@ void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_
  *
  * @note     adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length)
+void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length)
 {
     adc->INJSEQ_B.INJSEQLEN = RESET;
     adc->INJSEQ_B.INJSEQLEN |= length - 1;
@@ -751,14 +752,14 @@ void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length)
  *
  * @note      adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet)
+void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet)
 {
     __IOM uint32_t tmp = 0;
 
     tmp = (uint32_t)adc;
     tmp += channel;
 
-    *(__IOM uint32_t *) tmp = (uint32_t)offSet;
+    *(__IOM uint32_t*) tmp = (uint32_t)offSet;
 }
 
 /*!
@@ -777,14 +778,14 @@ void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t
  *
  * @note      adc can be ADC1, ADC2 or ADC3.
  */
-uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel)
+uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel)
 {
     __IOM uint32_t temp = 0;
 
     temp = (uint32_t)adc;
     temp += channel + INJDATA_OFFSET;
 
-    return (uint16_t)(*(__IOM uint32_t *)  temp);
+    return (uint16_t)(*(__IOM uint32_t*)  temp);
 }
 
 /*!
@@ -806,7 +807,7 @@ uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog)
+void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog)
 {
     adc->CTRL1 &= 0xFF3FFDFF;
     adc->CTRL1 |= analogWatchdog;
@@ -821,7 +822,7 @@ void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableAnalogWatchdog(ADC_T *adc)
+void ADC_DisableAnalogWatchdog(ADC_T* adc)
 {
     adc->CTRL1 &= 0xFF3FFDFF;
 }
@@ -841,7 +842,7 @@ void ADC_DisableAnalogWatchdog(ADC_T *adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint16_t lowThreshold)
+void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold)
 {
     adc->AWDHT = highThreshold;
     adc->AWDLT = lowThreshold;
@@ -877,7 +878,7 @@ void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel)
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel)
 {
     adc->CTRL1_B.AWDCHSEL = BIT_RESET;
     adc->CTRL1 |= channel;
@@ -892,7 +893,7 @@ void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableTempSensorVrefint(ADC_T *adc)
+void ADC_EnableTempSensorVrefint(ADC_T* adc)
 {
     adc->CTRL2_B.TSVREFEN = BIT_SET;
 }
@@ -906,7 +907,7 @@ void ADC_EnableTempSensorVrefint(ADC_T *adc)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableTempSensorVrefint(ADC_T *adc)
+void ADC_DisableTempSensorVrefint(ADC_T* adc)
 {
     adc->CTRL2_B.TSVREFEN = BIT_RESET;
 }
@@ -926,7 +927,7 @@ void ADC_DisableTempSensorVrefint(ADC_T *adc)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt)
+void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt)
 {
     uint8_t mask;
 
@@ -949,7 +950,7 @@ void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt)
+void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt)
 {
     uint8_t mask;
 
@@ -974,7 +975,7 @@ void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt)
  *
  * @note      adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag)
+uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag)
 {
     return (adc->STS & flag) ? SET : RESET;
 }
@@ -996,7 +997,7 @@ uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag)
  *
  * @note      adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag)
+void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag)
 {
     adc->STS = ~(uint32_t)flag;
 }
@@ -1016,7 +1017,7 @@ void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag)
+uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T flag)
 {
     uint8_t bitStatus = RESET;
     uint32_t itmask = 0;
@@ -1051,7 +1052,7 @@ uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag)
+void ADC_ClearIntFlag(ADC_T* adc, uint16_t flag)
 {
     uint8_t mask = 0;
 
@@ -1059,6 +1060,6 @@ void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag)
     adc->STS = ~(uint32_t)mask;
 }
 
-/**@} end of group ADC_Fuctions*/
-/**@} end of group ADC_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group ADC_Functions */
+/**@} end of group ADC_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the BAKPR firmware functions.
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,15 +26,16 @@
 #include "apm32f10x_bakpr.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
-/** @addtogroup BAKPR_Driver ADC Driver
+/** @addtogroup BAKPR_Driver BAKPR Driver
+  * @brief BAKPR driver modules
   @{
 */
 
-/** @addtogroup BAKPR_Fuctions Fuctions
+/** @defgroup BAKPR_Functions Functions
   @{
 */
 
@@ -177,7 +178,7 @@ void BAKPR_ConfigBackupRegister(BAKPR_DATA_T bakrData, uint16_t data)
     tmp = (uint32_t)BAKPR_BASE;
     tmp += bakrData;
 
-    *(__IOM uint32_t *) tmp = data;
+    *(__IOM uint32_t*) tmp = data;
 }
 
 /*!
@@ -195,7 +196,7 @@ uint16_t BAKPR_ReadBackupRegister(BAKPR_DATA_T bakrData)
     tmp = (uint32_t)BAKPR_BASE;
     tmp += bakrData;
 
-    return (*(__IOM uint32_t *) tmp);
+    return (*(__IOM uint32_t*) tmp);
 }
 
 /*!
@@ -246,6 +247,6 @@ void BAKPR_ClearIntFlag(void)
     BAKPR->CSTS_B.TICLR = BIT_SET;
 }
 
-/**@} end of group BAKPR_Fuctions*/
+/**@} end of group BAKPR_Functions*/
 /**@} end of group BAKPR_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the CAN firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,15 +26,16 @@
 #include "apm32f10x_can.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup CAN_Driver CAN Driver
+  * @brief CAN driver modules
   @{
 */
 
-/** @addtogroup CAN_Fuctions Fuctions
+/** @defgroup CAN_Functions Functions
   @{
 */
 
@@ -47,7 +48,7 @@
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_Reset(CAN_T *can)
+void CAN_Reset(CAN_T* can)
 {
     if (can == CAN1)
     {
@@ -72,22 +73,22 @@ void CAN_Reset(CAN_T *can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
+uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
 {
     uint8_t  initStatus = ERROR;
     uint32_t wait_ack = 0x00000000;
 
-    /** Exit from sleep mode */
+    /* Exit from sleep mode */
     can->MCTRL_B.SLEEPREQ = BIT_RESET;
-    /** Request initialisation */
+    /* Request initialisation */
     can->MCTRL_B.INITREQ = BIT_SET;
 
-    /** Wait the acknowledge */
+    /* Wait the acknowledge */
     while (((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF))
     {
         wait_ack++;
     }
-    /** Check acknowledge */
+    /* Check acknowledge */
     if (((can->MSTS_B.INITFLG) != BIT_SET))
     {
         initStatus = ERROR;
@@ -139,7 +140,7 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
             can->MCTRL_B.TXFPCFG = BIT_RESET;
         }
 
-        /** Set the bit timing register */
+        /* Set the bit timing register */
         can->BITTIM &= (uint32_t)0x3fffffff;
         can->BITTIM |= (uint32_t)canConfig->mode << 30;
         can->BITTIM_B.RSYNJW  = canConfig->syncJumpWidth;
@@ -147,16 +148,16 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
         can->BITTIM_B.TIMSEG2 = canConfig->timeSegment2;
         can->BITTIM_B.BRPSC   = canConfig->prescaler - 1;
 
-        /** Request leave initialisation */
+        /* Request leave initialisation */
         can->MCTRL_B.INITREQ = BIT_RESET;
 
         wait_ack = 0;
-        /** Wait the acknowledge */
+        /* Wait the acknowledge */
         while (((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF))
         {
             wait_ack++;
         }
-        /** Check acknowledge */
+        /* Check acknowledge */
         if (((can->MSTS_B.INITFLG) != BIT_RESET))
         {
             initStatus = ERROR;
@@ -169,6 +170,92 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
     return initStatus;
 }
 
+#if defined(APM32F10X_CL)
+/*!
+ * @brief     Congig the CAN peripheral according to the specified parameters in the filterConfig.
+ *
+ * @param     filterConfig :Point to a CAN_FilterConfig_T structure.
+ *
+ * @retval    None
+ *
+ * @note      This function is for CAN1 and CAN2.
+ */
+void CAN_ConfigFilter(CAN_FilterConfig_T* filterConfig)
+{
+    CAN1->FCTRL_B.FINITEN = BIT_SET;
+
+    CAN1->FACT &= ~(1 << filterConfig->filterNumber);
+
+    /* Filter Scale */
+    if (filterConfig->filterScale == CAN_FILTER_SCALE_16BIT)
+    {
+        /* 16-bit scale for the filter */
+        CAN1->FSCFG &= ~(1 << filterConfig->filterNumber);
+
+        CAN1->sFilterRegister[filterConfig->filterNumber].FBANK1 =
+            ((0x0000FFFF & filterConfig->filterMaskIdLow) << 16) |
+            (0x0000FFFF & filterConfig->filterIdLow);
+
+        CAN1->sFilterRegister[filterConfig->filterNumber].FBANK2 =
+            ((0x0000FFFF & filterConfig->filterMaskIdHigh) << 16) |
+            (0x0000FFFF & filterConfig->filterIdHigh);
+    }
+
+    if (filterConfig->filterScale == CAN_FILTER_SCALE_32BIT)
+    {
+        CAN1->FSCFG |= (1 << filterConfig->filterNumber);
+
+        CAN1->sFilterRegister[filterConfig->filterNumber].FBANK1 =
+            ((0x0000FFFF & filterConfig->filterIdHigh) << 16) |
+            (0x0000FFFF & filterConfig->filterIdLow);
+
+        CAN1->sFilterRegister[filterConfig->filterNumber].FBANK2 =
+            ((0x0000FFFF & filterConfig->filterMaskIdHigh) << 16) |
+            (0x0000FFFF & filterConfig->filterMaskIdLow);
+    }
+
+    /* Filter Mode */
+    if (filterConfig->filterMode == CAN_FILTER_MODE_IDMASK)
+    {
+        CAN1->FMCFG &= ~(1 << filterConfig->filterNumber);
+    }
+    else
+    {
+        CAN1->FMCFG |= (1 << filterConfig->filterNumber);
+    }
+
+    /* Filter FIFO assignment */
+    if (filterConfig->filterFIFO == CAN_FILTER_FIFO_0)
+    {
+        CAN1->FFASS &= ~(1 << filterConfig->filterNumber);
+    }
+    if (filterConfig->filterFIFO == CAN_FILTER_FIFO_1)
+    {
+        CAN1->FFASS |= (1 << filterConfig->filterNumber);
+    }
+
+    /* Filter activation */
+    if (filterConfig->filterActivation == ENABLE)
+    {
+        CAN1->FACT |= (1 << filterConfig->filterNumber);
+    }
+    CAN1->FCTRL_B.FINITEN = BIT_RESET;
+}
+
+/*!
+ * @brief     Select the start bank filter for slave CAN.
+ *
+ * @param     bankNum: the start slave bank filter from 1..27.
+ *
+ * @retval    None
+ */
+void CAN_SlaveStartBank(uint8_t bankNum)
+{
+    CAN1->FCTRL_B.FINITEN = SET;
+    CAN1->FCTRL_B.CAN2BN  = bankNum;
+    CAN1->FCTRL_B.FINITEN = RESET;
+}
+#else
 /*!
  * @brief     Congig the CAN peripheral according to the specified parameters in the filterConfig.
  *
@@ -180,16 +267,16 @@ uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig)
+void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig)
 {
     can->FCTRL_B.FINITEN = BIT_SET;
 
     can->FACT &= ~(1 << filterConfig->filterNumber);
 
-    /** Filter Scale */
+    /* Filter Scale */
     if (filterConfig->filterScale == CAN_FILTER_SCALE_16BIT)
     {
-        /** 16-bit scale for the filter */
+        /* 16-bit scale for the filter */
         can->FSCFG &= ~(1 << filterConfig->filterNumber);
 
         can->sFilterRegister[filterConfig->filterNumber].FBANK1 =
@@ -214,7 +301,7 @@ void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig)
             (0x0000FFFF & filterConfig->filterMaskIdLow);
     }
 
-    /** Filter Mode */
+    /* Filter Mode */
     if (filterConfig->filterMode == CAN_FILTER_MODE_IDMASK)
     {
         can->FMCFG &= ~(1 << filterConfig->filterNumber);
@@ -224,7 +311,7 @@ void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig)
         can->FMCFG |= (1 << filterConfig->filterNumber);
     }
 
-    /** Filter FIFO assignment */
+    /* Filter FIFO assignment */
     if (filterConfig->filterFIFO == CAN_FILTER_FIFO_0)
     {
         can->FFASS &= ~(1 << filterConfig->filterNumber);
@@ -234,13 +321,14 @@ void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig)
         can->FFASS |= (1 << filterConfig->filterNumber);
     }
 
-    /** Filter activation */
+    /* Filter activation */
     if (filterConfig->filterActivation == ENABLE)
     {
         can->FACT |= (1 << filterConfig->filterNumber);
     }
     can->FCTRL_B.FINITEN = BIT_RESET;
 }
+#endif
 
 /*!
  * @brief     Initialize a CAN_Config_T structure with the initial value.
@@ -251,7 +339,7 @@ void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ConfigStructInit(CAN_Config_T *canConfig)
+void CAN_ConfigStructInit(CAN_Config_T* canConfig)
 {
     canConfig->autoBusOffManage = DISABLE;
     canConfig->autoWakeUpMode   = DISABLE;
@@ -274,7 +362,7 @@ void CAN_ConfigStructInit(CAN_Config_T *canConfig)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_EnableDBGFreeze(CAN_T *can)
+void CAN_EnableDBGFreeze(CAN_T* can)
 {
     can->MCTRL_B.DBGFRZE = ENABLE;
 }
@@ -288,25 +376,11 @@ void CAN_EnableDBGFreeze(CAN_T *can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_DisableDBGFreeze(CAN_T *can)
+void CAN_DisableDBGFreeze(CAN_T* can)
 {
     can->MCTRL_B.DBGFRZE = DISABLE;
 }
 
-/*!
- * @brief     Select the start bank filter for slave CAN.
- *
- * @param     bankNum: the start slave bank filter from 1..27.
- *
- * @retval    None
- */
-void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum)
-{
-    can->FCTRL_B.FINITEN = SET;
-    can->FCTRL_B.CAN2BN  = bankNum;
-    can->FCTRL_B.FINITEN = RESET;
-}
-
 /*!
  * @brief     Initiates the transmission of a message.
  *
@@ -318,11 +392,11 @@ void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage)
+uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage)
 {
     uint8_t transmit_milbox = 0;
 
-    /** Select one empty transmit mailbox */
+    /* Select one empty transmit mailbox */
     if ((can->TXSTS & 0x04000000) == 0x04000000)
     {
         transmit_milbox = 0;
@@ -340,7 +414,7 @@ uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage)
         return 3;  //!< No mailbox is empty
     }
 
-    /** Set up the Id */
+    /* Set up the Id */
     can->sTxMailBox[transmit_milbox].TXMID &= 0x00000001;
     if (TxMessage->typeID == CAN_TYPEID_STD)
     {
@@ -351,17 +425,17 @@ uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage)
         can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->extID << 3) | (TxMessage->typeID) | (TxMessage->remoteTxReq);
     }
 
-    /** Set up the TXDLEN */
+    /* Set up the TXDLEN */
     TxMessage->dataLengthCode &= 0x0F;
     can->sTxMailBox[transmit_milbox].TXDLEN &= (uint32_t)0xFFFFFFF0;
     can->sTxMailBox[transmit_milbox].TXDLEN |= TxMessage->dataLengthCode;
 
-    /** Set up the data field */
+    /* Set up the data field */
     can->sTxMailBox[transmit_milbox].TXMDL = ((uint32_t)TxMessage->data[3] << 24) | ((uint32_t)TxMessage->data[2] << 16)
             | ((uint32_t)TxMessage->data[1] << 8) | ((uint32_t)TxMessage->data[0]);
     can->sTxMailBox[transmit_milbox].TXMDH = ((uint32_t)TxMessage->data[7] << 24) | ((uint32_t)TxMessage->data[6] << 16)
             | ((uint32_t)TxMessage->data[5] << 8) | ((uint32_t)TxMessage->data[4]);
-    /** Request transmission */
+    /* Request transmission */
     can->sTxMailBox[transmit_milbox].TXMID |= 0x00000001;
 
     return transmit_milbox;
@@ -380,54 +454,54 @@ uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
+uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
 {
     uint32_t state = 0;
 
     switch (TxMailbox)
     {
-    case (CAN_TX_MAILBIX_0):
-        state =   can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000);
-        break;
-    case (CAN_TX_MAILBIX_1):
-        state =   can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000);
-        break;
-    case (CAN_TX_MAILBIX_2):
-        state =   can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000);
-        break;
-    default:
-        state = 0;
-        break;
+        case (CAN_TX_MAILBIX_0):
+            state =   can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000);
+            break;
+        case (CAN_TX_MAILBIX_1):
+            state =   can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000);
+            break;
+        case (CAN_TX_MAILBIX_2):
+            state =   can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000);
+            break;
+        default:
+            state = 0;
+            break;
     }
     switch (state)
     {
-    /** Transmit pending  */
-    case (0x0):
-        state = 2;
-        break;
-    /** Transmit failed  */
-    case (0x00000001 | 0x04000000):
-        state = 0;
-        break;
-    case (0x00000100 | 0x08000000):
-        state = 0;
-        break;
-    case (0x00010000 | 0x10000000):
-        state = 0;
-        break;
-    /** Transmit succeeded  */
-    case (0x00000001 | 0x00000002 | 0x04000000):
-        state = 1;
-        break;
-    case (0x00000100 | 0x00000200 | 0x08000000):
-        state = 1;
-        break;
-    case (0x00010000 | 0x00020000 | 0x10000000):
-        state = 1;
-        break;
-    default:
-        state = 0;
-        break;
+        /* Transmit pending  */
+        case (0x0):
+            state = 2;
+            break;
+        /* Transmit failed  */
+        case (0x00000001 | 0x04000000):
+            state = 0;
+            break;
+        case (0x00000100 | 0x08000000):
+            state = 0;
+            break;
+        case (0x00010000 | 0x10000000):
+            state = 0;
+            break;
+        /* Transmit succeeded  */
+        case (0x00000001 | 0x00000002 | 0x04000000):
+            state = 1;
+            break;
+        case (0x00000100 | 0x00000200 | 0x08000000):
+            state = 1;
+            break;
+        case (0x00010000 | 0x00020000 | 0x10000000):
+            state = 1;
+            break;
+        default:
+            state = 0;
+            break;
     }
     return (uint8_t) state;
 }
@@ -447,21 +521,21 @@ uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
+void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
 {
     switch (TxMailbox)
     {
-    case CAN_TX_MAILBIX_0:
-        can->TXSTS_B.ABREQFLG0 = BIT_SET;
-        break;
-    case CAN_TX_MAILBIX_1:
-        can->TXSTS_B.ABREQFLG1 = BIT_SET;
-        break;
-    case CAN_TX_MAILBIX_2:
-        can->TXSTS_B.ABREQFLG2 = BIT_SET;
-        break;
-    default:
-        break;
+        case CAN_TX_MAILBIX_0:
+            can->TXSTS_B.ABREQFLG0 = BIT_SET;
+            break;
+        case CAN_TX_MAILBIX_1:
+            can->TXSTS_B.ABREQFLG1 = BIT_SET;
+            break;
+        case CAN_TX_MAILBIX_2:
+            can->TXSTS_B.ABREQFLG2 = BIT_SET;
+            break;
+        default:
+            break;
     }
 }
 
@@ -481,9 +555,9 @@ void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMessage)
+void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMessage)
 {
-    /** Get the Id */
+    /* Get the Id */
     RxMessage->typeID = ((uint8_t)0x04 & (can->sRxMailBox[FIFONumber].RXMID));
     if (RxMessage->typeID == CAN_TYPEID_STD)
     {
@@ -497,7 +571,7 @@ void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMess
     RxMessage->remoteTxReq = can->sRxMailBox[FIFONumber].RXMID_B.RFTXREQ;
     RxMessage->dataLengthCode = can->sRxMailBox[FIFONumber].RXDLEN_B.DLCODE;
     RxMessage->filterMatchIndex = can->sRxMailBox[FIFONumber].RXDLEN_B.FMIDX;
-    /** Get the data field */
+    /* Get the data field */
     RxMessage->data[0] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE0;
     RxMessage->data[1] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE1;
     RxMessage->data[2] = can->sRxMailBox[FIFONumber].RXMDL_B.DATABYTE2;
@@ -531,7 +605,7 @@ void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMess
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
+void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
 {
     if (FIFONumber == CAN_RX_FIFO_0)
     {
@@ -557,7 +631,7 @@ void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
+uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
 {
     if (FIFONumber == CAN_RX_FIFO_0)
     {
@@ -586,7 +660,7 @@ uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode)
+uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode)
 {
     uint8_t states = 0;
     uint32_t time_out = 0x0000FFFF;
@@ -651,7 +725,7 @@ uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_SleepMode(CAN_T *can)
+uint8_t CAN_SleepMode(CAN_T* can)
 {
     can->MCTRL_B.SLEEPREQ = BIT_SET;
     can->MCTRL_B.INITREQ = BIT_RESET;
@@ -674,7 +748,7 @@ uint8_t CAN_SleepMode(CAN_T *can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_WakeUpMode(CAN_T *can)
+uint8_t CAN_WakeUpMode(CAN_T* can)
 {
     uint32_t time_out = 0x0000FFFF;
 
@@ -699,7 +773,7 @@ uint8_t CAN_WakeUpMode(CAN_T *can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadLastErrorCode(CAN_T *can)
+uint8_t CAN_ReadLastErrorCode(CAN_T* can)
 {
     return can->ERRSTS_B.LERRC;
 }
@@ -713,7 +787,7 @@ uint8_t CAN_ReadLastErrorCode(CAN_T *can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadRxErrorCounter(CAN_T *can)
+uint8_t CAN_ReadRxErrorCounter(CAN_T* can)
 {
     return can->ERRSTS_B.RXERRCNT;
 }
@@ -727,7 +801,7 @@ uint8_t CAN_ReadRxErrorCounter(CAN_T *can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can)
+uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can)
 {
     return can->ERRSTS_B.TXERRCNT;
 }
@@ -758,7 +832,7 @@ uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupts)
+void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts)
 {
     can->INTEN |= interrupts;
 }
@@ -789,7 +863,7 @@ void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupts)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupts)
+void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts)
 {
     can->INTEN &= ~interrupts;
 }
@@ -821,7 +895,7 @@ void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupts)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag)
+uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
 {
     uint8_t status = 0;
 
@@ -905,11 +979,11 @@ uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag)
+void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag)
 {
     uint32_t flagtmp = 0;
 
-    /** ERRSTS register */
+    /* ERRSTS register */
     if (flag == 0x30F00070)
     {
         can->ERRSTS = RESET;
@@ -962,7 +1036,7 @@ void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag)
+uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag)
 {
     uint8_t status = 0;
 
@@ -970,53 +1044,53 @@ uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag)
     {
         switch (flag)
         {
-        case CAN_INT_TXME:
-            status = can->TXSTS_B.REQCFLG0;
-            status |= can->TXSTS_B.REQCFLG1;
-            status |= can->TXSTS_B.REQCFLG2;
-            break;
-        case CAN_INT_F0MP:
-            status = can->RXF0_B.FMNUM0;
-            break;
-        case CAN_INT_F0FULL:
-            status = can->RXF0_B.FFULLFLG0;
-            break;
-        case CAN_INT_F0OVR:
-            status = can->RXF0_B.FOVRFLG0;
-            break;
-        case CAN_INT_F1MP:
-            status = can->RXF1_B.FMNUM1;
-            break;
-        case CAN_INT_F1FULL:
-            status = can->RXF1_B.FFULLFLG1;
-            break;
-        case CAN_INT_F1OVR:
-            status = can->RXF1_B.FOVRFLG1;
-            break;
-        case CAN_INT_WUP:
-            status = can->MSTS_B.WUPIFLG;
-            break;
-        case CAN_INT_SLEEP:
-            status = can->MSTS_B.SLEEPIFLG;
-            break;
-        case CAN_INT_ERRW:
-            status = can->ERRSTS_B.ERRWFLG;
-            break;
-        case CAN_INT_ERRP:
-            status = can->ERRSTS_B.ERRPFLG;
-            break;
-        case CAN_INT_BOF:
-            status = can->ERRSTS_B.BOFLG;
-            break;
-        case CAN_INT_LEC:
-            status = can->ERRSTS_B.LERRC;
-            break;
-        case CAN_INT_ERR:
-            status = can->MSTS_B.ERRIFLG;
-            break;
-        default:
-            status = RESET;
-            break;
+            case CAN_INT_TXME:
+                status = can->TXSTS_B.REQCFLG0;
+                status |= can->TXSTS_B.REQCFLG1;
+                status |= can->TXSTS_B.REQCFLG2;
+                break;
+            case CAN_INT_F0MP:
+                status = can->RXF0_B.FMNUM0;
+                break;
+            case CAN_INT_F0FULL:
+                status = can->RXF0_B.FFULLFLG0;
+                break;
+            case CAN_INT_F0OVR:
+                status = can->RXF0_B.FOVRFLG0;
+                break;
+            case CAN_INT_F1MP:
+                status = can->RXF1_B.FMNUM1;
+                break;
+            case CAN_INT_F1FULL:
+                status = can->RXF1_B.FFULLFLG1;
+                break;
+            case CAN_INT_F1OVR:
+                status = can->RXF1_B.FOVRFLG1;
+                break;
+            case CAN_INT_WUP:
+                status = can->MSTS_B.WUPIFLG;
+                break;
+            case CAN_INT_SLEEP:
+                status = can->MSTS_B.SLEEPIFLG;
+                break;
+            case CAN_INT_ERRW:
+                status = can->ERRSTS_B.ERRWFLG;
+                break;
+            case CAN_INT_ERRP:
+                status = can->ERRSTS_B.ERRPFLG;
+                break;
+            case CAN_INT_BOF:
+                status = can->ERRSTS_B.BOFLG;
+                break;
+            case CAN_INT_LEC:
+                status = can->ERRSTS_B.LERRC;
+                break;
+            case CAN_INT_ERR:
+                status = can->MSTS_B.ERRIFLG;
+                break;
+            default:
+                status = RESET;
+                break;
         }
     }
     else
@@ -1050,55 +1124,55 @@ uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ClearIntFlag(CAN_T *can, CAN_INT_T flag)
+void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag)
 {
     switch (flag)
     {
-    case CAN_INT_TXME:
-        can->TXSTS_B.REQCFLG0 = BIT_SET;
-        can->TXSTS_B.REQCFLG1 = BIT_SET;
-        can->TXSTS_B.REQCFLG2 = BIT_SET;
-        break;
-    case CAN_INT_F0FULL:
-        can->RXF0_B.FFULLFLG0 = BIT_SET;
-        break;
-    case CAN_INT_F0OVR:
-        can->RXF0_B.FOVRFLG0  = BIT_SET;
-        break;
-    case CAN_INT_F1FULL:
-        can->RXF1_B.FFULLFLG1 = BIT_SET;
-        break;
-    case CAN_INT_F1OVR:
-        can->RXF1_B.FOVRFLG1  = BIT_SET;
-        break;
-    case CAN_INT_WUP:
-        can->MSTS_B.WUPIFLG   = BIT_SET;
-        break;
-    case CAN_INT_SLEEP:
-        can->MSTS_B.SLEEPIFLG = BIT_SET;
-        break;
-    case CAN_INT_ERRW:
-        can->MSTS_B.ERRIFLG = BIT_SET;
-        break;
-    case CAN_INT_ERRP:
-        can->MSTS_B.ERRIFLG = BIT_SET;
-        break;
-    case CAN_INT_BOF:
-        can->MSTS_B.ERRIFLG = BIT_SET;
-        break;
-    case CAN_INT_LEC:
-        can->ERRSTS_B.LERRC = BIT_RESET;
-        can->MSTS_B.ERRIFLG = BIT_SET;
-        break;
-    case CAN_INT_ERR:
-        can->ERRSTS_B.LERRC = BIT_RESET;
-        can->MSTS_B.ERRIFLG = BIT_SET;
-        break;
-    default:
-        break;
+        case CAN_INT_TXME:
+            can->TXSTS_B.REQCFLG0 = BIT_SET;
+            can->TXSTS_B.REQCFLG1 = BIT_SET;
+            can->TXSTS_B.REQCFLG2 = BIT_SET;
+            break;
+        case CAN_INT_F0FULL:
+            can->RXF0_B.FFULLFLG0 = BIT_SET;
+            break;
+        case CAN_INT_F0OVR:
+            can->RXF0_B.FOVRFLG0  = BIT_SET;
+            break;
+        case CAN_INT_F1FULL:
+            can->RXF1_B.FFULLFLG1 = BIT_SET;
+            break;
+        case CAN_INT_F1OVR:
+            can->RXF1_B.FOVRFLG1  = BIT_SET;
+            break;
+        case CAN_INT_WUP:
+            can->MSTS_B.WUPIFLG   = BIT_SET;
+            break;
+        case CAN_INT_SLEEP:
+            can->MSTS_B.SLEEPIFLG = BIT_SET;
+            break;
+        case CAN_INT_ERRW:
+            can->MSTS_B.ERRIFLG = BIT_SET;
+            break;
+        case CAN_INT_ERRP:
+            can->MSTS_B.ERRIFLG = BIT_SET;
+            break;
+        case CAN_INT_BOF:
+            can->MSTS_B.ERRIFLG = BIT_SET;
+            break;
+        case CAN_INT_LEC:
+            can->ERRSTS_B.LERRC = BIT_RESET;
+            can->MSTS_B.ERRIFLG = BIT_SET;
+            break;
+        case CAN_INT_ERR:
+            can->ERRSTS_B.LERRC = BIT_RESET;
+            can->MSTS_B.ERRIFLG = BIT_SET;
+            break;
+        default:
+            break;
     }
 }
 
-/**@} end of group CAN_Fuctions*/
-/**@} end of group CAN_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group CAN_Functions */
+/**@} end of group CAN_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the CRC firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -25,15 +25,16 @@
 
 #include "apm32f10x_crc.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup CRC_Driver CRC Driver
+  * @brief CRC driver modules
   @{
 */
 
-/** @addtogroup CRC_Fuctions Fuctions
+/** @defgroup CRC_Functions Functions
   @{
 */
 
@@ -73,7 +74,7 @@ uint32_t CRC_CalculateCRC(uint32_t data)
  *
  * @retval    A 32-bit CRC value
  */
-uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen)
+uint32_t CRC_CalculateBlockCRC(uint32_t* buf, uint32_t bufLen)
 {
     while (bufLen--)
     {
@@ -119,6 +120,6 @@ uint8_t CRC_ReadIDRegister(void)
     return (CRC->INDATA);
 }
 
-/**@} end of group CRC_Fuctions*/
+/**@} end of group CRC_Functions*/
 /**@} end of group CRC_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the DAC firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,15 +26,16 @@
 #include "apm32f10x_dac.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup DAC_Driver DAC Driver
+  * @brief DAC driver modules
   @{
 */
 
-/** @addtogroup DAC_Fuctions Fuctions
+/** @defgroup DAC_Functions Functions
   @{
 */
 
@@ -63,7 +64,7 @@ void DAC_Reset(void)
  *
  * @retval       None
  */
-void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig)
+void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig)
 {
     uint32_t tmp1 = 0, tmp2 = 0;
 
@@ -88,15 +89,15 @@ void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig)
  *
  * @retval       None
  */
-void DAC_ConfigStructInit(DAC_Config_T *dacConfig)
+void DAC_ConfigStructInit(DAC_Config_T* dacConfig)
 {
-    /** Initialize the DAC_Trigger member */
+    /* Initialize the DAC_Trigger member */
     dacConfig->trigger = DAC_TRIGGER_NONE;
-    /** Initialize the DAC_WaveGeneration member */
+    /* Initialize the DAC_WaveGeneration member */
     dacConfig->waveGeneration = DAC_WAVE_GENERATION_NONE;
-    /** Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+    /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
     dacConfig->maskAmplitudeSelect = DAC_LFSR_MASK_BIT11_1;
-    /** Initialize the DAC_OutputBuffer member */
+    /* Initialize the DAC_OutputBuffer member */
     dacConfig->outputBuffer = DAC_OUTPUT_BUFFER_ENBALE;
 }
 
@@ -321,8 +322,8 @@ void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data)
     tmp = (uint32_t)DAC_BASE;
     tmp += 0x00000008 + align;
 
-    /** Set the DAC channel1 selected data holding register */
-    *(__IO uint32_t *) tmp = data;
+    /* Set the DAC channel1 selected data holding register */
+    *(__IO uint32_t*) tmp = data;
 }
 
 /*!
@@ -345,8 +346,8 @@ void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data)
     tmp = (uint32_t)DAC_BASE;
     tmp += 0x00000014 + align;
 
-    /** Set the DAC channel1 selected data holding register */
-    *(__IO uint32_t *) tmp = data;
+    /* Set the DAC channel1 selected data holding register */
+    *(__IO uint32_t*) tmp = data;
 }
 
 /*!
@@ -368,7 +369,7 @@ void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1
 {
     uint32_t data = 0, tmp = 0;
 
-    /** Calculate and set dual DAC data holding register value */
+    /* Calculate and set dual DAC data holding register value */
     if (align == DAC_ALIGN_8BIT_R)
     {
         data = ((uint32_t)data2 << 8) | data1;
@@ -381,8 +382,8 @@ void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1
     tmp = (uint32_t)DAC_BASE;
     tmp += 0x00000020 + align;
 
-    /** Set the dual DAC selected data holding register */
-    *(__IO uint32_t *)tmp = data;
+    /* Set the dual DAC selected data holding register */
+    *(__IO uint32_t*)tmp = data;
 }
 
 /*!
@@ -402,10 +403,10 @@ uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel)
     tmp = (uint32_t) DAC_BASE ;
     tmp += 0x0000002C + ((uint32_t)channel >> 2);
 
-    /** Returns the DAC channel data output register value */
-    return (uint16_t)(*(__IO uint32_t *) tmp);
+    /* Returns the DAC channel data output register value */
+    return (uint16_t)(*(__IO uint32_t*) tmp);
 }
 
-/**@} end of group DAC_Fuctions*/
+/**@} end of group DAC_Functions*/
 /**@} end of group DAC_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the DEBUG firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -25,15 +25,16 @@
 
 #include "apm32f10x_dbgmcu.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup DBGMCU_Driver DBGMCU Driver
+  * @brief DBGMCU driver modules
   @{
 */
 
-/** @addtogroup DBGMCU_Fuctions Fuctions
+/** @defgroup DBGMCU_Functions Functions
   @{
 */
 
@@ -141,6 +142,6 @@ void DBGMCU_Disable(uint32_t periph)
     DBGMCU->CFG &= ~periph;
 }
 
-/**@} end of group DBGMCU_Fuctions*/
-/**@} end of group DBGMCU_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group DBGMCU_Functions*/
+/**@} end of group DBGMCU_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the DMA firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -25,15 +25,16 @@
 
 #include "apm32f10x_dma.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup DMA_Driver DMA Driver
+  * @brief DMA driver modules
   @{
 */
 
-/** @addtogroup DMA_Fuctions Fuctions
+/** @defgroup DMA_Functions Functions
   @{
 */
 
@@ -46,7 +47,7 @@
  *
  * @note      DMA2 Channel only for APM32 High density devices.
  */
-void DMA_Reset(DMA_Channel_T *channel)
+void DMA_Reset(DMA_Channel_T* channel)
 {
     channel->CHCFG_B.CHEN = BIT_RESET;
     channel->CHCFG = 0;
@@ -115,7 +116,7 @@ void DMA_Reset(DMA_Channel_T *channel)
  *
  * @note      DMA2 Channel only for APM32 High density devices.
  */
-void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig)
+void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig)
 {
     channel->CHCFG_B.DIRCFG = dmaConfig->dir;
     channel->CHCFG_B.CIRMODE = dmaConfig->loopMode;
@@ -138,7 +139,7 @@ void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig)
  *
  * @retval    None
  */
-void DMA_ConfigStructInit(DMA_Config_T *dmaConfig)
+void DMA_ConfigStructInit(DMA_Config_T* dmaConfig)
 {
     dmaConfig->peripheralBaseAddr = 0;
     dmaConfig->memoryBaseAddr = 0;
@@ -162,7 +163,7 @@ void DMA_ConfigStructInit(DMA_Config_T *dmaConfig)
  *
  * @note      DMA2 Channel only for APM32 High density devices.
  */
-void DMA_Enable(DMA_Channel_T *channel)
+void DMA_Enable(DMA_Channel_T* channel)
 {
     channel->CHCFG_B.CHEN = ENABLE;
 }
@@ -176,7 +177,7 @@ void DMA_Enable(DMA_Channel_T *channel)
  *
  * @note      DMA2 Channel only for APM32 High density devices.
  */
-void DMA_Disable(DMA_Channel_T *channel)
+void DMA_Disable(DMA_Channel_T* channel)
 {
     channel->CHCFG_B.CHEN = DISABLE;
 }
@@ -192,7 +193,7 @@ void DMA_Disable(DMA_Channel_T *channel)
  *
  * @note      DMA2 Channel only for APM32 High density devices.
  */
-void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber)
+void DMA_ConfigDataNumber(DMA_Channel_T* channel, uint16_t dataNumber)
 {
     channel->CHNDATA = dataNumber;
 }
@@ -206,7 +207,7 @@ void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber)
  *
  * @note      DMA2 Channel only for APM32 High density devices.
  */
-uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel)
+uint16_t DMA_ReadDataNumber(DMA_Channel_T* channel)
 {
     return channel->CHNDATA;
 }
@@ -226,7 +227,7 @@ uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel)
  *
  * @note      DMA2 Channel only for APM32 High density devices.
  */
-void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt)
+void DMA_EnableInterrupt(DMA_Channel_T* channel, uint32_t interrupt)
 {
     channel->CHCFG |= interrupt;
 }
@@ -246,7 +247,7 @@ void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt)
  *
  * @note      DMA2 Channel only for APM32 High density devices.
  */
-void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt)
+void DMA_DisableInterrupt(DMA_Channel_T* channel, uint32_t interrupt)
 {
     channel->CHCFG &= ~interrupt;
 }
@@ -491,6 +492,7 @@ uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag)
         }
     }
 }
+
 /*!
  * @brief     Clears the specified DMA Channel's interrupts.
  *
@@ -562,6 +564,6 @@ void DMA_ClearIntFlag(uint32_t flag)
     }
 }
 
-/**@} end of group DMA_Fuctions*/
+/**@} end of group DMA_Functions*/
 /**@} end of group DMA_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions for the DMC controler peripheral
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,15 +26,16 @@
 #ifdef APM32F10X_HD
 #include "apm32f10x_dmc.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
-/** @addtogroup DMC_Driver  DMC Driver
+/** @addtogroup DMC_Driver DMC Driver
+  * @brief DMC driver modules
   @{
 */
 
-/** @addtogroup  DMC_Fuctions Fuctions
+/** @defgroup  DMC_Functions Functions
   @{
 */
 
@@ -45,7 +46,7 @@
  *
  * @retval      None
  */
-void DMC_Config(DMC_Config_T *dmcConfig)
+void DMC_Config(DMC_Config_T* dmcConfig)
 {
     DMC->SW_B.MCSW = 1;
     while (!DMC->CTRL1_B.INIT);
@@ -73,7 +74,7 @@ void DMC_Config(DMC_Config_T *dmcConfig)
  *
  * @retval      None
  */
-void DMC_ConfigStructInit(DMC_Config_T *dmcConfig)
+void DMC_ConfigStructInit(DMC_Config_T* dmcConfig)
 {
     dmcConfig->bankWidth   = DMC_BANK_WIDTH_2;
     dmcConfig->clkPhase    = DMC_CLK_PHASE_REVERSE;
@@ -91,7 +92,7 @@ void DMC_ConfigStructInit(DMC_Config_T *dmcConfig)
  *
  * @retval      None
  */
-void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig)
+void DMC_ConfigTiming(DMC_TimingConfig_T* timingConfig)
 {
     DMC->TIM0_B.RASMINTSEL = timingConfig->tRAS;
     DMC->TIM0_B.DTIMSEL    = timingConfig->tRCD;
@@ -116,7 +117,7 @@ void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig)
  *
  * @retval      None
  */
-void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig)
+void DMC_ConfigTimingStructInit(DMC_TimingConfig_T* timingConfig)
 {
     timingConfig->latencyCAS = DMC_CAS_LATENCY_3;
     timingConfig->tARP = DMC_AUTO_REFRESH_10;
@@ -457,8 +458,9 @@ void DMC_ConfigWRAPB(DMC_WRPB_T burst)
     DMC->CTRL2_B.WRPBSEL = burst;
 }
 
+/**@} end of group DMC_Functions*/
+/**@} end of group DMC_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver*/
+
 #endif //defined APM32F10X_HD
 
-/**@} end of group DMC_Fuctions*/
-/**@} end of group DMC_Driver*/
-/**@} end of group Peripherals_Library*/

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the EINT firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -25,15 +25,16 @@
 
 #include "apm32f10x_eint.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup EINT_Driver EINT Driver
+  * @brief EINT driver modules
   @{
 */
 
-/** @addtogroup EINT_Fuctions Fuctions
+/** @defgroup EINT_Functions Functions
   @{
 */
 
@@ -60,7 +61,7 @@ void EINT_Reset(void)
  *
  * @retval       None
  */
-void EINT_Config(EINT_Config_T *eintConfig)
+void EINT_Config(EINT_Config_T* eintConfig)
 {
     uint32_t temp = 0;
     temp = (uint32_t)EINT_BASE;
@@ -71,7 +72,7 @@ void EINT_Config(EINT_Config_T *eintConfig)
         EINT->EMASK &= ~eintConfig->line;
 
         temp += eintConfig->mode;
-        *(__IOM uint32_t *) temp |= eintConfig->line;
+        *(__IOM uint32_t*) temp |= eintConfig->line;
 
         EINT->RTEN &= ~eintConfig->line;
         EINT->FTEN &= ~eintConfig->line;
@@ -86,14 +87,14 @@ void EINT_Config(EINT_Config_T *eintConfig)
             temp = (uint32_t)EINT_BASE;
             temp += eintConfig->trigger;
 
-            *(__IOM uint32_t *) temp |= eintConfig->line;
+            *(__IOM uint32_t*) temp |= eintConfig->line;
         }
     }
     else
     {
         temp += eintConfig->mode;
 
-        *(__IOM uint32_t *) temp &= ~eintConfig->line;
+        *(__IOM uint32_t*) temp &= ~eintConfig->line;
     }
 }
 
@@ -104,7 +105,7 @@ void EINT_Config(EINT_Config_T *eintConfig)
  *
  * @retval       None
  */
-void EINT_ConfigStructInit(EINT_Config_T *eintConfig)
+void EINT_ConfigStructInit(EINT_Config_T* eintConfig)
 {
     eintConfig->line = EINT_LINENONE;
     eintConfig->mode = EINT_MODE_INTERRUPT;
@@ -200,6 +201,6 @@ void EINT_ClearIntFlag(uint32_t line)
     EINT->IPEND = line;
 }
 
-/**@} end of group EINT_Fuctions*/
-/**@} end of group EINT_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group EINT_Functions*/
+/**@} end of group EINT_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver*/

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the FMC firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,10 +23,11 @@
  *  and limitations under the License.
  */
 
+/* Includes */
 #include "apm32f10x_fmc.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -34,7 +35,7 @@
   @{
 */
 
-/** @addtogroup FMC_Fuctions Fuctions
+/** @defgroup FMC_Functions Functions
   @{
 */
 
@@ -257,7 +258,7 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
     {
         FMC->CTRL2_B.PG = BIT_SET;
 
-        *(__IOM uint16_t *)address = data;
+        *(__IOM uint16_t*)address = data;
 
         status = FMC_WaitForLastOperation(0x000B0000);
 
@@ -265,7 +266,7 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
         {
             temp = address + 2;
 
-            *(__IOM uint16_t *) temp = data >> 16;
+            *(__IOM uint16_t*) temp = data >> 16;
 
             status = FMC_WaitForLastOperation(0x000B0000);
             FMC->CTRL2_B.PG = BIT_RESET;
@@ -309,7 +310,7 @@ FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data)
     if (status == FMC_STATUS_COMPLETE)
     {
         FMC->CTRL2_B.PG = BIT_SET;
-        *(__IOM uint16_t *)address = data;
+        *(__IOM uint16_t*)address = data;
         status = FMC_WaitForLastOperation(0x000B0000);
         FMC->CTRL2_B.PG = BIT_RESET;
     }
@@ -346,7 +347,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data)
         FMC->OBKEY = 0xCDEF89AB;
 
         FMC->CTRL2_B.OBP = BIT_SET;
-        *(__IOM uint16_t *)address = data;
+        *(__IOM uint16_t*)address = data;
         status = FMC_WaitForLastOperation(0x000B0000);
         if (status == FMC_STATUS_TIMEOUT)
         {
@@ -361,11 +362,11 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data)
  *
  * @param     page:the address of the pages to be write protection
  *                This parameter can be any combination of the following values:
- *                 for APM32F10X_LD ：
+ *                 for APM32F10X_LD :
  *                    @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_28_31
- *                 for APM32F10X_MD ：
+ *                 for APM32F10X_MD :
  *                    @arg FLASH_WRP_PAGE_0_3 to FLASH_WRP_PAGE_124_127
- *                 for APM32F10X_HD ：
+ *                 for APM32F10X_HD :
  *                    @arg FLASH_WRP_PAGE_0_1 to FLASH_WRP_PAGE_60_61 or FLASH_WRP_PAGE_62_127
  *                 @arg FMC_WRP_PAGE_ALL
  *
@@ -454,7 +455,7 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void)
         {
             FMC->CTRL2_B.OBE = BIT_RESET;
             FMC->CTRL2_B.OBP = BIT_SET;
-            OB->RDP = 0x00A5;
+            OB->RDP = 0x00;
 
             status = FMC_WaitForLastOperation(0x000B0000);
 
@@ -501,7 +502,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
         {
             FMC->CTRL2_B.OBE = BIT_RESET;
             FMC->CTRL2_B.OBP = BIT_SET;
-            OB->RDP = 0x00;
+            OB->RDP = 0xA5;
 
             status = FMC_WaitForLastOperation(0x000B0000);
 
@@ -529,7 +530,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
  *                 @arg FMC_STATUS_COMPLETE
  *                 @arg FMC_STATUS_TIMEOUT
  */
-FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T *userConfig)
+FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig)
 {
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
@@ -763,6 +764,6 @@ FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut)
     return status;
 }
 
-/**@} end of group FMC_Fuctions*/
+/**@} end of group FMC_Functions*/
 /**@} end of group FMC_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group APM32F10x_StdPeriphDriver*/

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the GPIO firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,10 +23,11 @@
  *  and limitations under the License.
  */
 
+/* Includes */
 #include "apm32f10x_gpio.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -34,7 +35,7 @@
   @{
 */
 
-/** @addtogroup GPIO_Fuctions Fuctions
+/** @defgroup GPIO_Functions Functions
   @{
 */
 
@@ -46,7 +47,7 @@
  *
  * @retval    None
  */
-void GPIO_Reset(GPIO_T *port)
+void GPIO_Reset(GPIO_T* port)
 {
     RCM_APB2_PERIPH_T APB2Periph;
 
@@ -106,7 +107,7 @@ void GPIO_AFIOReset(void)
  *
  * @retval    None
  */
-void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig)
+void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig)
 {
     uint8_t i;
     uint32_t mode;
@@ -181,10 +182,10 @@ void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig)
  *
  * @retval    None
  */
-void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig)
+void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig)
 {
     gpioConfig->pin  = GPIO_PIN_ALL;
-    gpioConfig->speed = GPIO_SPEED_20MHz;
+    gpioConfig->speed = GPIO_SPEED_2MHz;
     gpioConfig->mode = GPIO_MODE_IN_FLOATING;
 }
 
@@ -199,7 +200,7 @@ void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig)
  *
  * @retval    The input port pin value
  */
-uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin)
+uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin)
 {
     uint8_t ret;
 
@@ -216,7 +217,7 @@ uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin)
  *
  * @retval    GPIO input data port value
  */
-uint16_t GPIO_ReadInputPort(GPIO_T *port)
+uint16_t GPIO_ReadInputPort(GPIO_T* port)
 {
     return ((uint16_t)port->IDATA);
 }
@@ -232,7 +233,7 @@ uint16_t GPIO_ReadInputPort(GPIO_T *port)
  *
  * @retval    The output port pin value
  */
-uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin)
+uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin)
 {
 
     uint8_t ret;
@@ -250,7 +251,7 @@ uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin)
  *
  * @retval    output data port value
  */
-uint16_t GPIO_ReadOutputPort(GPIO_T *port)
+uint16_t GPIO_ReadOutputPort(GPIO_T* port)
 {
     return ((uint16_t)port->ODATA);
 }
@@ -266,7 +267,7 @@ uint16_t GPIO_ReadOutputPort(GPIO_T *port)
  *
  * @retval    None
  */
-void GPIO_SetBit(GPIO_T *port, uint16_t pin)
+void GPIO_SetBit(GPIO_T* port, uint16_t pin)
 {
     port->BSC = (uint32_t)pin;
 }
@@ -282,7 +283,7 @@ void GPIO_SetBit(GPIO_T *port, uint16_t pin)
  *
  * @retval    None
  */
-void GPIO_ResetBit(GPIO_T *port, uint16_t pin)
+void GPIO_ResetBit(GPIO_T* port, uint16_t pin)
 {
     port->BC = (uint32_t)pin;
 }
@@ -304,7 +305,7 @@ void GPIO_ResetBit(GPIO_T *port, uint16_t pin)
  *
  * @retval    None
  */
-void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal)
+void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal)
 {
     if (bitVal != BIT_RESET)
     {
@@ -326,7 +327,7 @@ void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal)
  *
  * @retval    None
  */
-void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue)
+void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue)
 {
     port->ODATA = (uint32_t)portValue;
 }
@@ -342,20 +343,20 @@ void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue)
  *
  * @retval    None
  */
-void GPIO_ConfigPinLock(GPIO_T *port, uint16_t pin)
+void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin)
 {
     uint32_t val = 0x00010000;
 
     val  |= pin;
-    /** Set LCKK bit */
+    /* Set LCKK bit */
     port->LOCK = val ;
-    /** Reset LCKK bit */
+    /* Reset LCKK bit */
     port->LOCK =  pin;
-    /** Set LCKK bit */
+    /* Set LCKK bit */
     port->LOCK = val;
-    /** Read LCKK bit*/
+    /* Read LCKK bit*/
     val = port->LOCK;
-    /** Read LCKK bit*/
+    /* Read LCKK bit*/
     val = port->LOCK;
 }
 
@@ -435,6 +436,24 @@ void GPIO_DisableEventOutput(void)
  *                    @arg GPIO_REMAP_PD01            : PD01 Alternate Function mapping
  *                    @arg GPIO_NO_REMAP_TMR5CH4_LSI  : No LSI connected to TIM5 Channel4 input capture for calibration
  *                    @arg GPIO_REMAP_TMR5CH4_LSI     : LSI connected to TIM5 Channel4 input capture for calibration
+ *                  Only For APM32F10X_CL devices(APM32F107xx and APM32F105xx):
+ *                    @arg GPIO_NO_REMAP_ETH_MAC      : No Ethernet MAC Alternate remapping
+ *                    @arg GPIO_REMAP_ETH_MAC         : Ethernet MAC Alternate remapping
+ *                    @arg GPIO_NO_REMAP_CAN2         : No CAN2 Alternate Function mapping
+ *                    @arg GPIO_REMAP_CAN2            : CAN2 Alternate Function mapping
+ *                    @arg GPIO_REMAP_MACEISEL_MII    : Ethernet MAC External Interface Select MII Interface
+ *                    @arg GPIO_REMAP_MACEISEL_RMII   : Ethernet MAC External Interface Select RMII Interface
+ *                    @arg GPIO_NO_REMAP_SPI3         : No SPI3 Alternate Function mapping
+ *                    @arg GPIO_REMAP_SPI3            : SPI3 Alternate Function mapping
+ *                    @arg GPIO_NO_REMAP_SWJ          : Full SWJ Enabled (JTAG-DP + SW-DP)
+ *                    @arg GPIO_REMAP_SWJ_NOJTRST     : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
+ *                    @arg GPIO_REMAP_SWJ_JTAGDISABLE : JTAG-DP Disabled and SW-DP Enabled
+ *                    @arg GPIO_REMAP_SWJ_DISABLE     : Full SWJ Disabled (JTAG-DP + SW-DP)
+ *                    @arg GPIO_NO_REMAP_TMR2ITR1     : No TMR2 ITR1 Alternate Function mapping
+ *                    @arg GPIO_REMAP_TMR2ITR1        : TMR2 ITR1 Alternate Function mapping
+ *                    @arg GPIO_NO_REMAP_PTP_PPS      : No Ethernet MAC PTP_PPS Alternate Function mapping
+ *                    @arg GPIO_REMAP_PTP_PPS         : Ethernet MAC PTP_PPS Alternate Function mapping
+ *                  For Other APM32F10X_HD/MD/LD devices:
  *                    @arg GPIO_NO_REMAP_ADC1_ETRGINJ : No ADC1 External Trigger Injected Conversion remapping
  *                    @arg GPIO_REMAP_ADC1_ETRGINJ    : ADC1 External Trigger Injected Conversion remapping
  *                    @arg GPIO_NO_REMAP_ADC1_ETRGREG : No ADC1 External Trigger Regular Conversion remapping
@@ -540,6 +559,6 @@ void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSou
     }
 }
 
-/**@} end of group GPIO_Fuctions*/
+/**@} end of group GPIO_Functions*/
 /**@} end of group GPIO_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group APM32F10x_StdPeriphDriver*/

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the I2C firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,10 +23,11 @@
  *  and limitations under the License.
  */
 
+/* Includes */
 #include "apm32f10x_i2c.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -34,7 +35,7 @@
   @{
 */
 
-/** @addtogroup I2C_Fuctions Fuctions
+/** @defgroup I2C_Functions Functions
   @{
 */
 
@@ -45,7 +46,7 @@
  *
  * @retval    None
  */
-void I2C_Reset(I2C_T *i2c)
+void I2C_Reset(I2C_T* i2c)
 {
     if (i2c == I2C1)
     {
@@ -68,20 +69,20 @@ void I2C_Reset(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig)
+void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
 {
     uint16_t tmpreg = 0, freqrange = 0;
     uint32_t PCLK1 = 8000000, PCLK2 = 0;
     uint16_t result = 0x04;
 
-    i2c->SWITCH = 0;
+    i2c->I2C_SWITCH = 0;
 
-    /** I2C CTRL2 Configuration */
+    /* I2C CTRL2 Configuration */
     RCM_ReadPCLKFreq(&PCLK1, &PCLK2);
     freqrange = PCLK1 / 1000000;
     i2c->CTRL2_B.CLKFCFG = freqrange;
 
-    /** I2C CLKCTRL Configuration */
+    /* I2C CLKCTRL Configuration */
     i2c->CTRL1_B.I2CEN = BIT_RESET;
 
     if (i2cConfig->clockSpeed <= 100000)
@@ -94,7 +95,7 @@ void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig)
         i2c->RISETMAX = freqrange + 1;
         tmpreg |= result;
     }
-    /** Configure speed in fast mode */
+    /* Configure speed in fast mode */
     else
     {
         if (i2cConfig->dutyCycle == I2C_DUTYCYCLE_2)
@@ -118,7 +119,7 @@ void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig)
     i2c->CLKCTRL = tmpreg;
     i2c->CTRL1_B.I2CEN = BIT_SET;
 
-    /** i2c CTRL1 Configuration  */
+    /* i2c CTRL1 Configuration  */
     i2c->CTRL1_B.ACKEN = BIT_RESET;
     i2c->CTRL1_B.SMBTCFG = BIT_RESET;
     i2c->CTRL1_B.SMBEN = BIT_RESET;
@@ -136,7 +137,7 @@ void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig)
  *
  * @retval    None
  */
-void I2C_ConfigStructInit(I2C_Config_T *i2cConfig)
+void I2C_ConfigStructInit(I2C_Config_T* i2cConfig)
 {
     i2cConfig->clockSpeed = 5000;
     i2cConfig->mode = I2C_MODE_I2C;
@@ -153,7 +154,7 @@ void I2C_ConfigStructInit(I2C_Config_T *i2cConfig)
  *
  * @retval    None
  */
-void I2C_Enable(I2C_T *i2c)
+void I2C_Enable(I2C_T* i2c)
 {
     i2c->CTRL1_B.I2CEN = ENABLE;
 }
@@ -165,7 +166,7 @@ void I2C_Enable(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_Disable(I2C_T *i2c)
+void I2C_Disable(I2C_T* i2c)
 {
     i2c->CTRL1_B.I2CEN = DISABLE;
 }
@@ -177,7 +178,7 @@ void I2C_Disable(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_EnableGenerateStart(I2C_T *i2c)
+void I2C_EnableGenerateStart(I2C_T* i2c)
 {
     i2c->CTRL1_B.START = BIT_SET;
 }
@@ -189,7 +190,7 @@ void I2C_EnableGenerateStart(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_DisableGenerateStart(I2C_T *i2c)
+void I2C_DisableGenerateStart(I2C_T* i2c)
 {
     i2c->CTRL1_B.START = BIT_RESET;
 }
@@ -201,7 +202,7 @@ void I2C_DisableGenerateStart(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_EnableGenerateStop(I2C_T *i2c)
+void I2C_EnableGenerateStop(I2C_T* i2c)
 {
     i2c->CTRL1_B.STOP = BIT_SET;
 }
@@ -213,7 +214,7 @@ void I2C_EnableGenerateStop(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_DisableGenerateStop(I2C_T *i2c)
+void I2C_DisableGenerateStop(I2C_T* i2c)
 {
     i2c->CTRL1_B.STOP = BIT_RESET;
 }
@@ -225,7 +226,7 @@ void I2C_DisableGenerateStop(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_EnableAcknowledge(I2C_T *i2c)
+void I2C_EnableAcknowledge(I2C_T* i2c)
 {
     i2c->CTRL1_B.ACKEN = ENABLE;
 }
@@ -237,7 +238,7 @@ void I2C_EnableAcknowledge(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_DisableAcknowledge(I2C_T *i2c)
+void I2C_DisableAcknowledge(I2C_T* i2c)
 {
     i2c->CTRL1_B.ACKEN = DISABLE;
 }
@@ -251,7 +252,7 @@ void I2C_DisableAcknowledge(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address)
+void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address)
 {
     i2c->SADDR2_B.ADDR2 = address;
 }
@@ -263,7 +264,7 @@ void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address)
  *
  * @retval    None
  */
-void I2C_EnableDualAddress(I2C_T *i2c)
+void I2C_EnableDualAddress(I2C_T* i2c)
 {
     i2c->SADDR2_B.ADDRNUM = ENABLE;
 }
@@ -275,7 +276,7 @@ void I2C_EnableDualAddress(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_DisableDualAddress(I2C_T *i2c)
+void I2C_DisableDualAddress(I2C_T* i2c)
 {
     i2c->SADDR2_B.ADDRNUM = DISABLE;
 }
@@ -287,7 +288,7 @@ void I2C_DisableDualAddress(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_EnableGeneralCall(I2C_T *i2c)
+void I2C_EnableGeneralCall(I2C_T* i2c)
 {
     i2c->CTRL1_B.SRBEN = ENABLE;
 }
@@ -299,7 +300,7 @@ void I2C_EnableGeneralCall(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_DisableGeneralCall(I2C_T *i2c)
+void I2C_DisableGeneralCall(I2C_T* i2c)
 {
     i2c->CTRL1_B.SRBEN = DISABLE;
 }
@@ -313,7 +314,7 @@ void I2C_DisableGeneralCall(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_TxData(I2C_T *i2c, uint8_t data)
+void I2C_TxData(I2C_T* i2c, uint8_t data)
 {
     i2c->DATA_B.DATA = data;
 }
@@ -325,7 +326,7 @@ void I2C_TxData(I2C_T *i2c, uint8_t data)
  *
  * @retval    received data
  */
-uint8_t I2C_RxData(I2C_T *i2c)
+uint8_t I2C_RxData(I2C_T* i2c)
 {
     return i2c->DATA_B.DATA;
 }
@@ -343,7 +344,7 @@ uint8_t I2C_RxData(I2C_T *i2c)
  *              @arg I2C_DIRECTION_RX: Receiver mode
  * @retval    None
  */
-void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction)
+void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction)
 {
     if (direction != I2C_DIRECTION_TX)
     {
@@ -375,32 +376,32 @@ void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction)
  *
  * @retval    The value of the read register
  */
-uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister)
+uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister)
 {
     switch (i2cRegister)
     {
-    case I2C_REGISTER_CTRL1:
-        return i2c->CTRL1;
-    case I2C_REGISTER_CTRL2:
-        return i2c->CTRL2;
-    case I2C_REGISTER_SADDR1:
-        return i2c->SADDR1;
-    case I2C_REGISTER_SADDR2:
-        return i2c->SADDR2;
-    case I2C_REGISTER_DATA:
-        return i2c->DATA;
-    case I2C_REGISTER_STS1:
-        return i2c->STS1;
-    case I2C_REGISTER_STS2:
-        return i2c->STS2;
-    case I2C_REGISTER_CLKCTRL:
-        return i2c->CLKCTRL;
-    case I2C_REGISTER_RISETMAX:
-        return i2c->RISETMAX;
-    case I2C_REGISTER_SWITCH:
-        return i2c->SWITCH;
-    default:
-        return 0;
+        case I2C_REGISTER_CTRL1:
+            return i2c->CTRL1;
+        case I2C_REGISTER_CTRL2:
+            return i2c->CTRL2;
+        case I2C_REGISTER_SADDR1:
+            return i2c->SADDR1;
+        case I2C_REGISTER_SADDR2:
+            return i2c->SADDR2;
+        case I2C_REGISTER_DATA:
+            return i2c->DATA;
+        case I2C_REGISTER_STS1:
+            return i2c->STS1;
+        case I2C_REGISTER_STS2:
+            return i2c->STS2;
+        case I2C_REGISTER_CLKCTRL:
+            return i2c->CLKCTRL;
+        case I2C_REGISTER_RISETMAX:
+            return i2c->RISETMAX;
+        case I2C_REGISTER_SWITCH:
+            return i2c->I2C_SWITCH;
+        default:
+            return 0;
     }
 }
 
@@ -411,7 +412,7 @@ uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister)
  *
  * @retval    None
  */
-void I2C_EnableSoftwareReset(I2C_T *i2c)
+void I2C_EnableSoftwareReset(I2C_T* i2c)
 {
     i2c->CTRL1_B.SWRST = ENABLE;
 }
@@ -423,7 +424,7 @@ void I2C_EnableSoftwareReset(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_DisableSoftwareReset(I2C_T *i2c)
+void I2C_DisableSoftwareReset(I2C_T* i2c)
 {
     i2c->CTRL1_B.SWRST = DISABLE;
 }
@@ -437,7 +438,7 @@ void I2C_DisableSoftwareReset(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition)
+void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition)
 {
     if (NACKPosition == I2C_NACK_POSITION_NEXT)
     {
@@ -460,7 +461,7 @@ void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition)
  *              @arg I2C_SMBUSALER_HIGH: SMBus Alert pin high
  * @retval    None
  */
-void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState)
+void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState)
 {
     if (SMBusState == I2C_SMBUSALER_LOW)
     {
@@ -479,7 +480,7 @@ void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState)
  *
  * @retval    None
  */
-void I2C_EnablePECTransmit(I2C_T *i2c)
+void I2C_EnablePECTransmit(I2C_T* i2c)
 {
     i2c->CTRL1_B.PEC = BIT_SET;
 }
@@ -491,7 +492,7 @@ void I2C_EnablePECTransmit(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_DisablePECTransmit(I2C_T *i2c)
+void I2C_DisablePECTransmit(I2C_T* i2c)
 {
     i2c->CTRL1_B.PEC = BIT_RESET;
 }
@@ -507,7 +508,7 @@ void I2C_DisablePECTransmit(I2C_T *i2c)
  *              @arg I2C_PEC_POSITION_CURRENT: indicates that current byte is PEC
  * @retval    None
  */
-void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition)
+void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition)
 {
     if (PECPosition == I2C_PEC_POSITION_NEXT)
     {
@@ -526,7 +527,7 @@ void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition)
  *
  * @retval    None
  */
-void I2C_EnablePEC(I2C_T *i2c)
+void I2C_EnablePEC(I2C_T* i2c)
 {
     i2c->CTRL1_B.PECEN = BIT_SET;
 }
@@ -538,7 +539,7 @@ void I2C_EnablePEC(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_DisablePEC(I2C_T *i2c)
+void I2C_DisablePEC(I2C_T* i2c)
 {
     i2c->CTRL1_B.PECEN = BIT_RESET;
 }
@@ -550,7 +551,7 @@ void I2C_DisablePEC(I2C_T *i2c)
  *
  * @retval    value of PEC
  */
-uint8_t I2C_ReadPEC(I2C_T *i2c)
+uint8_t I2C_ReadPEC(I2C_T* i2c)
 {
     return i2c->STS2_B.PECVALUE;
 }
@@ -562,7 +563,7 @@ uint8_t I2C_ReadPEC(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_EnableARP(I2C_T *i2c)
+void I2C_EnableARP(I2C_T* i2c)
 {
     i2c->CTRL1_B.ARPEN = BIT_SET;
 }
@@ -574,7 +575,7 @@ void I2C_EnableARP(I2C_T *i2c)
 *
 * @retval     None
 */
-void I2C_DisableARP(I2C_T *i2c)
+void I2C_DisableARP(I2C_T* i2c)
 {
     i2c->CTRL1_B.ARPEN = BIT_RESET;
 }
@@ -586,7 +587,7 @@ void I2C_DisableARP(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_EnableStretchClock(I2C_T *i2c)
+void I2C_EnableStretchClock(I2C_T* i2c)
 {
     i2c->CTRL1_B.CLKSTRETCHD = BIT_RESET;
 }
@@ -598,7 +599,7 @@ void I2C_EnableStretchClock(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_DisableStretchClock(I2C_T *i2c)
+void I2C_DisableStretchClock(I2C_T* i2c)
 {
     i2c->CTRL1_B.CLKSTRETCHD = BIT_SET;
 }
@@ -614,7 +615,7 @@ void I2C_DisableStretchClock(I2C_T *i2c)
  *              @arg I2C_DUTYCYCLE_2: I2C fast mode Tlow/Thigh = 2
  * @retval    None
  */
-void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle)
+void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle)
 {
     if (dutyCycle == I2C_DUTYCYCLE_16_9)
     {
@@ -633,7 +634,7 @@ void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle)
  *
  * @retval    None
  */
-void I2C_EnableDMA(I2C_T *i2c)
+void I2C_EnableDMA(I2C_T* i2c)
 {
     i2c->CTRL2_B.DMAEN = ENABLE;
 }
@@ -645,7 +646,7 @@ void I2C_EnableDMA(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_DisableDMA(I2C_T *i2c)
+void I2C_DisableDMA(I2C_T* i2c)
 {
     i2c->CTRL2_B.DMAEN = DISABLE;
 }
@@ -657,7 +658,7 @@ void I2C_DisableDMA(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_EnableDMALastTransfer(I2C_T *i2c)
+void I2C_EnableDMALastTransfer(I2C_T* i2c)
 {
     i2c->CTRL2_B.LTCFG = BIT_SET;
 }
@@ -669,7 +670,7 @@ void I2C_EnableDMALastTransfer(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_DisableDMALastTransfer(I2C_T *i2c)
+void I2C_DisableDMALastTransfer(I2C_T* i2c)
 {
     i2c->CTRL2_B.LTCFG = BIT_RESET;
 }
@@ -687,7 +688,7 @@ void I2C_DisableDMALastTransfer(I2C_T *i2c)
  *
  * @retval    None
  */
-void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt)
+void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt)
 {
     i2c->CTRL2 |= interrupt;
 }
@@ -705,7 +706,7 @@ void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt)
  *
  * @retval    None
  */
-void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt)
+void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt)
 {
     i2c->CTRL2 &= ~interrupt;
 }
@@ -736,7 +737,7 @@ void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt)
  *
  * @retval    Status: SUCCESS or ERROR
  */
-uint8_t  I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent)
+uint8_t  I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent)
 {
     uint32_t lastevent = 0;
     uint32_t flag1 = 0, flag2 = 0;
@@ -761,7 +762,7 @@ uint8_t  I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent)
  *
  * @retval    The last event
  */
-uint32_t I2C_ReadLastEvent(I2C_T *i2c)
+uint32_t I2C_ReadLastEvent(I2C_T* i2c)
 {
     uint32_t lastevent = 0;
     uint32_t flag1 = 0, flag2 = 0;
@@ -806,77 +807,77 @@ uint32_t I2C_ReadLastEvent(I2C_T *i2c)
  *
  * @retval    Status: flag SET or RESET
  */
-uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
+uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
 {
 
     uint8_t status = 0;
     switch (flag)
     {
-    case I2C_FLAG_DUALADDR:
-        status = i2c->STS2_B.DUALADDRFLG;
-        break;
-    case I2C_FLAG_SMMHADDR:
-        status = i2c->STS2_B.SMMHADDR;
-        break;
-    case I2C_FLAG_SMBDADDR:
-        status = i2c->STS2_B.SMBDADDRFLG;
-        break;
-    case I2C_FLAG_GENCALL:
-        status = i2c->STS2_B.GENCALLFLG;
-        break;
-    case I2C_FLAG_TR:
-        status = i2c->STS2_B.TRFLG;
-        break;
-    case I2C_FLAG_BUSBSY:
-        status = i2c->STS2_B.BUSBSYFLG;
-        break;
-    case I2C_FLAG_MS:
-        status = i2c->STS2_B.MSFLG;
-        break;
-    case I2C_FLAG_SMBALT:
-        status = i2c->STS1_B.SMBALTFLG;
-        break;
-    case I2C_FLAG_TTE:
-        status = i2c->STS1_B.TTEFLG;
-        break;
-    case I2C_FLAG_PECE:
-        status = i2c->STS1_B.PECEFLG;
-        break;
-    case  I2C_FLAG_OVRUR:
-        status = i2c->STS1_B.OVRURFLG;
-        break;
-    case I2C_FLAG_AE:
-        status = i2c->STS1_B.AEFLG;
-        break;
-    case I2C_FLAG_AL:
-        status = i2c->STS1_B.ALFLG;
-        break;
-    case I2C_FLAG_BERR:
-        status = i2c->STS1_B.BERRFLG;
-        break;
-    case I2C_FLAG_TXBE:
-        status = i2c->STS1_B.TXBEFLG;
-        break;
-    case I2C_FLAG_RXBNE:
-        status = i2c->STS1_B.RXBNEFLG;
-        break;
-    case I2C_FLAG_STOP:
-        status = i2c->STS1_B.STOPFLG;
-        break;
-    case I2C_FLAG_ADDR10:
-        status = i2c->STS1_B.ADDR10FLG;
-        break;
-    case I2C_FLAG_BTC:
-        status = i2c->STS1_B.BTCFLG;
-        break;
-    case I2C_FLAG_ADDR:
-        status = i2c->STS1_B.ADDRFLG;
-        break;
-    case I2C_FLAG_START:
-        status = i2c->STS1_B.STARTFLG;
-        break;
-    default:
-        break;
+        case I2C_FLAG_DUALADDR:
+            status = i2c->STS2_B.DUALADDRFLG;
+            break;
+        case I2C_FLAG_SMMHADDR:
+            status = i2c->STS2_B.SMMHADDR;
+            break;
+        case I2C_FLAG_SMBDADDR:
+            status = i2c->STS2_B.SMBDADDRFLG;
+            break;
+        case I2C_FLAG_GENCALL:
+            status = i2c->STS2_B.GENCALLFLG;
+            break;
+        case I2C_FLAG_TR:
+            status = i2c->STS2_B.TRFLG;
+            break;
+        case I2C_FLAG_BUSBSY:
+            status = i2c->STS2_B.BUSBSYFLG;
+            break;
+        case I2C_FLAG_MS:
+            status = i2c->STS2_B.MSFLG;
+            break;
+        case I2C_FLAG_SMBALT:
+            status = i2c->STS1_B.SMBALTFLG;
+            break;
+        case I2C_FLAG_TTE:
+            status = i2c->STS1_B.TTEFLG;
+            break;
+        case I2C_FLAG_PECE:
+            status = i2c->STS1_B.PECEFLG;
+            break;
+        case  I2C_FLAG_OVRUR:
+            status = i2c->STS1_B.OVRURFLG;
+            break;
+        case I2C_FLAG_AE:
+            status = i2c->STS1_B.AEFLG;
+            break;
+        case I2C_FLAG_AL:
+            status = i2c->STS1_B.ALFLG;
+            break;
+        case I2C_FLAG_BERR:
+            status = i2c->STS1_B.BERRFLG;
+            break;
+        case I2C_FLAG_TXBE:
+            status = i2c->STS1_B.TXBEFLG;
+            break;
+        case I2C_FLAG_RXBNE:
+            status = i2c->STS1_B.RXBNEFLG;
+            break;
+        case I2C_FLAG_STOP:
+            status = i2c->STS1_B.STOPFLG;
+            break;
+        case I2C_FLAG_ADDR10:
+            status = i2c->STS1_B.ADDR10FLG;
+            break;
+        case I2C_FLAG_BTC:
+            status = i2c->STS1_B.BTCFLG;
+            break;
+        case I2C_FLAG_ADDR:
+            status = i2c->STS1_B.ADDRFLG;
+            break;
+        case I2C_FLAG_START:
+            status = i2c->STS1_B.STARTFLG;
+            break;
+        default:
+            break;
     }
     return status;
 }
@@ -914,33 +915,33 @@ uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
  *              a read operation to I2C_STS1 register (I2C_ReadStatusFlag())
  *              followed by a write operation to I2C_DATA register (I2C_TxData()).
  */
-void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
+void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
 {
     switch (flag)
     {
-    case I2C_FLAG_SMBALT:
-        i2c->STS1_B.SMBALTFLG = BIT_RESET;
-        break;
-    case I2C_FLAG_TTE:
-        i2c->STS1_B.TTEFLG = BIT_RESET;
-        break;
-    case I2C_FLAG_PECE:
-        i2c->STS1_B.PECEFLG = BIT_RESET;
-        break;
-    case  I2C_FLAG_OVRUR:
-        i2c->STS1_B.OVRURFLG = BIT_RESET;
-        break;
-    case I2C_FLAG_AE:
-        i2c->STS1_B.AEFLG = BIT_RESET;
-        break;
-    case I2C_FLAG_AL:
-        i2c->STS1_B.ALFLG = BIT_RESET;
-        break;
-    case I2C_FLAG_BERR:
-        i2c->STS1_B.BERRFLG = BIT_RESET;
-        break;
-    default:
-        break;
+        case I2C_FLAG_SMBALT:
+            i2c->STS1_B.SMBALTFLG = BIT_RESET;
+            break;
+        case I2C_FLAG_TTE:
+            i2c->STS1_B.TTEFLG = BIT_RESET;
+            break;
+        case I2C_FLAG_PECE:
+            i2c->STS1_B.PECEFLG = BIT_RESET;
+            break;
+        case  I2C_FLAG_OVRUR:
+            i2c->STS1_B.OVRURFLG = BIT_RESET;
+            break;
+        case I2C_FLAG_AE:
+            i2c->STS1_B.AEFLG = BIT_RESET;
+            break;
+        case I2C_FLAG_AL:
+            i2c->STS1_B.ALFLG = BIT_RESET;
+            break;
+        case I2C_FLAG_BERR:
+            i2c->STS1_B.BERRFLG = BIT_RESET;
+            break;
+        default:
+            break;
     }
 }
 
@@ -968,7 +969,7 @@ void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
  *
  * @retval    Status: flag SET or RESET
  */
-uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag)
+uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag)
 {
     uint32_t enablestatus = 0;
 
@@ -1014,11 +1015,11 @@ uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag)
  *              a read operation to I2C_STS1 register (I2C_ReadIntFlag())
  *              followed by a write operation to I2C_DATA register (I2C_TxData()).
  */
-void I2C_ClearIntFlag(I2C_T *i2c, uint32_t flag)
+void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag)
 {
     i2c->STS1 = (uint16_t)~(flag & 0x00FFFFFF);
 }
 
-/**@} end of group I2C_Fuctions*/
+/**@} end of group I2C_Functions*/
 /**@} end of group I2C_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group APM32F10x_StdPeriphDriver*/

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the IWDT firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,9 +23,10 @@
  *  and limitations under the License.
  */
 
+/* Includes */
 #include "apm32f10x_iwdt.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -33,7 +34,7 @@
   @{
 */
 
-/** @addtogroup IWDT_Fuctions Fuctions
+/** @defgroup IWDT_Functions Functions
   @{
 */
 
@@ -143,6 +144,6 @@ uint8_t IWDT_ReadStatusFlag(uint16_t flag)
     return bitStatus;
 }
 
-/**@} end of group IWDT_Fuctions*/
-/**@} end of group IWDT_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group IWDT_Functions*/
+/**@} end of group IWDT_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver*/

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c

@@ -4,9 +4,9 @@
  * @brief       This file provides all the miscellaneous firmware functions.
  *             Include NVIC,SystemTick and Power management.
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -16,7 +16,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -24,9 +24,10 @@
  *  and limitations under the License.
  */
 
+/* Includes */
 #include "apm32f10x_misc.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
@@ -34,7 +35,7 @@
   @{
 */
 
-/** @addtogroup MISC_Macros Macros
+/** @defgroup MISC_Macros Macros
   @{
 */
 
@@ -43,7 +44,7 @@
 /**@} end of group MISC_Macros*/
 
 
-/** @addtogroup MISC_Fuctions Fuctions
+/** @defgroup MISC_Functions Functions
   @{
 */
 
@@ -82,42 +83,42 @@ void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t su
     uint32_t tempPriority, tempPrePri, tempSubPri;
     uint32_t priorityGrp;
 
-    /** Get priority group */
+    /* Get priority group */
     priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U;
 
-    /** get pre-emption priority and subpriority */
+    /* get pre-emption priority and subpriority */
     switch (priorityGrp)
     {
-    case NVIC_PRIORITY_GROUP_0:
-        tempPrePri = 0;
-        tempSubPri = 4;
-        break;
-
-    case NVIC_PRIORITY_GROUP_1:
-        tempPrePri = 1;
-        tempSubPri = 3;
-        break;
-
-    case NVIC_PRIORITY_GROUP_2:
-        tempPrePri = 2;
-        tempSubPri = 2;
-        break;
-
-    case NVIC_PRIORITY_GROUP_3:
-        tempPrePri = 3;
-        tempSubPri = 1;
-        break;
-
-    case NVIC_PRIORITY_GROUP_4:
-        tempPrePri = 4;
-        tempSubPri = 0;
-        break;
-
-    default:
-        NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0);
-        tempPrePri = 0;
-        tempSubPri = 4;
-        break;
+        case NVIC_PRIORITY_GROUP_0:
+            tempPrePri = 0;
+            tempSubPri = 4;
+            break;
+
+        case NVIC_PRIORITY_GROUP_1:
+            tempPrePri = 1;
+            tempSubPri = 3;
+            break;
+
+        case NVIC_PRIORITY_GROUP_2:
+            tempPrePri = 2;
+            tempSubPri = 2;
+            break;
+
+        case NVIC_PRIORITY_GROUP_3:
+            tempPrePri = 3;
+            tempSubPri = 1;
+            break;
+
+        case NVIC_PRIORITY_GROUP_4:
+            tempPrePri = 4;
+            tempSubPri = 0;
+            break;
+
+        default:
+            NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0);
+            tempPrePri = 0;
+            tempSubPri = 4;
+            break;
     }
 
     tempPrePri = 4 - tempPrePri;
@@ -127,7 +128,7 @@ void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t su
     tempPriority <<= 4;
     NVIC->IP[irq] = (uint8_t)tempPriority;
 
-    /** enable the selected IRQ */
+    /* enable the selected IRQ */
     NVIC->ISER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU);
 }
 
@@ -140,7 +141,7 @@ void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t su
  */
 void NVIC_DisableIRQRequest(IRQn_Type irq)
 {
-    /** disable the selected IRQ.*/
+    /* disable the selected IRQ.*/
     NVIC->ICER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU);
 }
 
@@ -215,6 +216,6 @@ void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource)
     }
 }
 
-/**@} end of group MISC_Fuctions*/
-/**@} end of group MISC_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group MISC_Functions*/
+/**@} end of group MISC_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver*/

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the PMU firmware functions.
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,18 +23,19 @@
  *  and limitations under the License.
  */
 
+/* Includes */
 #include "apm32f10x_pmu.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
-/** @addtogroup PMU_Driver  PMU Driver
+/** @addtogroup PMU_Driver PMU Driver
   @{
 */
 
-/** @addtogroup  PMU_Fuctions Fuctions
+/** @defgroup  PMU_Functions Functions
   @{
 */
 
@@ -102,7 +103,7 @@ void PMU_DisablePVD(void)
 /*!
  * @brief     Configure a voltage threshold detected by a power supply voltage detector (PVD).
  *
- * @param     level：specifies the PVD detection level
+ * @param     level£ºspecifies the PVD detection level
  *                   This parameter can be one of the following values:
  *                   @arg PMU_PVD_LEVEL_2V2 : Config PVD detection level to 2.2V
  *                   @arg PMU_PVD_LEVEL_2V3 : Config PVD detection level to 2.3V
@@ -118,9 +119,9 @@ void PMU_DisablePVD(void)
 void PMU_ConfigPVDLevel(PMU_PVD_LEVEL_T level)
 {
 
-    /** Clear PLS[7:5] bits */
+    /* Clear PLS[7:5] bits */
     PMU->CTRL_B.PLSEL = 0x0000;
-    /** Store the new value */
+    /* Store the new value */
     PMU->CTRL_B.PLSEL = level;
 }
 
@@ -165,26 +166,26 @@ void PMU_DisableWakeUpPin(void)
  */
 void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry)
 {
-    /** Clear PDDSCFG and LPDSCFG bits */
+    /* Clear PDDSCFG and LPDSCFG bits */
     PMU->CTRL_B.PDDSCFG = 0x00;
     PMU->CTRL_B.LPDSCFG = 0x00;
-    /** Set LPDSCFG bit according to regulator value */
+    /* Set LPDSCFG bit according to regulator value */
     PMU->CTRL_B.LPDSCFG = regulator;
-    /** Set Cortex System Control Register */
+    /* Set Cortex System Control Register */
     SCB->SCR |= (uint32_t)0x04;
-    /** Select STOP mode entry*/
+    /* Select STOP mode entry*/
     if (entry == PMU_STOP_ENTRY_WFI)
     {
-        /** Request Wait For Interrupt */
+        /* Request Wait For Interrupt */
         __WFI();
     }
     else
     {
-        /** Request Wait For Event */
+        /* Request Wait For Event */
         __WFE();
     }
 
-    /** Reset SLEEPDEEP bit of Cortex System Control Register */
+    /* Reset SLEEPDEEP bit of Cortex System Control Register */
     SCB->SCR &= (uint32_t)~((uint32_t)0x04);
 }
 
@@ -197,16 +198,16 @@ void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry)
  */
 void PMU_EnterSTANDBYMode(void)
 {
-    /** Clear Wake-up flag */
+    /* Clear Wake-up flag */
     PMU->CTRL_B.WUFLGCLR = BIT_SET;
-    /** Select STANDBY mode */
+    /* Select STANDBY mode */
     PMU->CTRL_B.PDDSCFG = BIT_SET;
-    /** Set Cortex System Control Register */
+    /* Set Cortex System Control Register */
     SCB->SCR |= (uint32_t)0x04;
 #if defined ( __CC_ARM   )
     __force_stores();
 #endif
-    /** Request Wait For Interrupt */
+    /* Request Wait For Interrupt */
     __WFI();
 
 }
@@ -214,7 +215,7 @@ void PMU_EnterSTANDBYMode(void)
 /*!
  * @brief     Read the specified PWR flag is set or not.
  *
- * @param     flag：Reads the status of specifies the flag.
+ * @param     flag£ºReads the status of specifies the flag.
  *                  This parameter can be one of the following values:
  *                    @arg PMU_FLAG_WUE : Wake Up flag
  *                    @arg PMU_FLAG_SB  : StandBy flag
@@ -244,7 +245,7 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag)
 /*!
  * @brief     Clears the PWR's pending flags.
  *
- * @param     flag：Clears the status of specifies the flag.
+ * @param     flag£ºClears the status of specifies the flag.
  *                  This parameter can be one of the following values:
  *                    @arg PMU_FLAG_WUE : Wake Up flag
  *                    @arg PMU_FLAG_SB  : StandBy flag
@@ -263,6 +264,6 @@ void PMU_ClearStatusFlag(PMU_FLAG_T flag)
     }
 }
 
-/**@} end of group PMU_Fuctions*/
-/**@} end of group PMU_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group PMU_Functions*/
+/**@} end of group PMU_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver*/

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions for the QSPI peripheral
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,18 +23,19 @@
  *  and limitations under the License.
  */
 
+/* Includes */
 #if defined (APM32F10X_MD) || defined (APM32F10X_LD)
 #include "apm32f10x_qspi.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
-/** @addtogroup QSPI_Driver  QSPI Driver
+/** @addtogroup QSPI_Driver QSPI Driver
   @{
 */
 
-/** @addtogroup QSPI_Fuctions Fuctions
+/** @defgroup QSPI_Functions Functions
   @{
 */
 
@@ -73,7 +74,7 @@ void QSPI_Reset(void)
  *
  * @retval      None
  */
-void QSPI_Config(QSPI_Config_T *qspiConfig)
+void QSPI_Config(QSPI_Config_T* qspiConfig)
 {
     QSPI->CTRL1_B.CPHA = qspiConfig->clockPhase;
     QSPI->CTRL1_B.CPOL = qspiConfig->clockPolarity;
@@ -91,7 +92,7 @@ void QSPI_Config(QSPI_Config_T *qspiConfig)
  *
  * @retval      None
  */
-void QSPI_ConfigStructInit(QSPI_Config_T *qspiConfig)
+void QSPI_ConfigStructInit(QSPI_Config_T* qspiConfig)
 {
     qspiConfig->clockPhase = QSPI_CLKPHA_2EDGE;
     qspiConfig->clockPolarity = QSPI_CLKPOL_LOW;
@@ -602,8 +603,8 @@ void QSPI_ClearIntFlag(uint32_t flag)
         dummy = QSPI->MIC;
     }
 }
-#endif //defined APM32F10X_MD/LD
 
-/**@} end of group QSPI_Fuctions*/
-/**@} end of group QSPI_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group QSPI_Functions*/
+/**@} end of group QSPI_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver*/
+#endif //defined APM32F10X_MD/LD

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the RCM firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -25,20 +25,21 @@
 
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup RCM_Driver RCM Driver
+  * @brief RCM driver modules
   @{
 */
 
-/** @addtogroup RCM_Fuctions Fuctions
+/** @defgroup RCM_Functions Functions
   @{
 */
 
 /*!
- * @brief     Resets the clock configuration to the default state
+ * @brief     Reset the clock configuration to the default state
  *
  * @param     None
  *
@@ -46,22 +47,40 @@
  */
 void RCM_Reset(void)
 {
-    /** Open HSI clock */
+    /* Open HSI clock */
     RCM->CTRL_B.HSIEN = BIT_SET;
-    /** Config HSI to system clock and Reset AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */
+    /* Configures HSI to system clock and Reset AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */
+#if defined(APM32F10X_CL)
+    RCM->CFG &= (uint32_t)0xF0FF0000;
+#else
     RCM->CFG &= (uint32_t)0xF8FF0000;
-    /** Reset HSEEN, CSSEN and PLLEN bits */
+#endif
+
+    /* Reset HSEEN, CSSEN and PLLEN bits */
     RCM->CTRL &= (uint32_t)0xFEF6FFFF;
-    /** Reset HSEBCFG bit */
+    /* Reset HSEBCFG bit */
     RCM->CTRL_B.HSEBCFG = BIT_RESET;
-    /** Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */
+    /* Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */
     RCM->CFG &= (uint32_t)0xFF00FFFF;
-    /** Disable all interrupts and clear pending bits */
+
+#if defined(APM32F10X_CL)
+    /* Reset PLL2EN and PLL3EN bits */
+    RCM->CTRL_B.PLL2EN = BIT_RESET;
+    RCM->CTRL_B.PLL3EN = BIT_RESET;
+
+    /* Disable all interrupts and clear pending bits  */
+    RCM->INT = 0x00FF0000;
+
+    /* Reset CFG2 register */
+    RCM->CFG2 = 0x00000000;
+#else
+    /* Disable all interrupts and clear pending bits */
     RCM->INT = 0x009F0000;
+#endif
 }
 
 /*!
- * @brief     Configs the HSE oscillator
+ * @brief     Configures the HSE oscillator
  *
  * @param     state: state of the HSE
  *                   This parameter can be one of the following values:
@@ -75,10 +94,10 @@ void RCM_Reset(void)
  */
 void RCM_ConfigHSE(RCM_HSE_T state)
 {
-    /** Reset HSEEN bit */
+    /* Reset HSEEN bit */
     RCM->CTRL_B.HSEEN = BIT_RESET;
 
-    /** Reset HSEBCFG bit */
+    /* Reset HSEBCFG bit */
     RCM->CTRL_B.HSEBCFG = BIT_RESET;
 
     if (state == RCM_HSE_OPEN)
@@ -93,7 +112,7 @@ void RCM_ConfigHSE(RCM_HSE_T state)
 }
 
 /*!
- * @brief     Waits for HSE to be ready
+ * @brief     Wait for HSE to be ready
  *
  * @param     None
  *
@@ -116,7 +135,7 @@ uint8_t RCM_WaitHSEReady(void)
 }
 
 /*!
- * @brief     Config HSI trimming value
+ * @brief     Configures HSI trimming value
  *
  * @param     HSITrim: HSI trimming value
  *                     This parameter must be a number between 0 and 0x1F.
@@ -183,7 +202,7 @@ void RCM_ConfigLSE(RCM_LSE_T state)
 }
 
 /*!
- * @brief     Enables the Internal Low Speed oscillator (LSI)
+ * @brief     Enable the Internal Low Speed oscillator (LSI)
  *
  * @param     None
  *
@@ -195,7 +214,7 @@ void RCM_EnableLSI(void)
 }
 
 /*!
- * @brief     Disables the Internal Low Speed oscillator (LSI)
+ * @brief     Disable the Internal Low Speed oscillator (LSI)
  *
  * @param     None
  *
@@ -207,16 +226,30 @@ void RCM_DisableLSI(void)
 }
 
 /*!
- * @brief     Configs the PLL clock source and multiplication factor
- *
- * @param     pllSelect:   PLL entry clock source select
- *                         This parameter can be one of the following values:
- *                         @arg RCM_PLLSEL_HSI_DIV_2: HSI clock divided by 2 selected as PLL clock source
- *                         @arg RCM_PLLSEL_HSE:       HSE clock selected as PLL clock source
- *                         @arg RCM_PLLSEL_HSE_DIV2:  HSE clock divided by 2 selected as PLL clock source
- *
- * @param     pllMf:       PLL multiplication factor
- *                         This parameter can be RCM_PLLMF_x where x can be a value from 2 to 16.
+ * @brief     Configures the PLL clock source and multiplication factor
+ *
+ * @param     pllSelect: PLL entry clock source select
+ *                       This parameter can be one of the following values:
+ *                       For APM32F105xx and APM32F107xx devices:
+ *                        @arg RCM_PLLSEL_HSI_DIV_2: HSI clock divided by 2 selected as PLL clock source
+ *                        @arg RCM_PLLSEL_PREDIV1  : PLL prescaler 1 clock selected as PLL clock source
+ *                       For other devices:
+ *                        @arg RCM_PLLSEL_HSI_DIV_2: HSI clock divided by 2 selected as PLL clock source
+ *                        @arg RCM_PLLSEL_HSE      : HSE clock selected as PLL clock source
+ *                        @arg RCM_PLLSEL_HSE_DIV2 : HSE clock divided by 2 selected as PLL clock source
+ *
+ * @param     pllMf:     PLL multiplication factor
+ *                       For APM32F105xx and APM32F107xx devices:
+ *                        This parameter can be one of the following values:
+ *                        @arg RCM_PLLMF_4  : PLL Multiplication Factor Configures to 4
+ *                        @arg RCM_PLLMF_5  : PLL Multiplication Factor Configures to 5
+ *                        @arg RCM_PLLMF_6  : PLL Multiplication Factor Configures to 6
+ *                        @arg RCM_PLLMF_7  : PLL Multiplication Factor Configures to 7
+ *                        @arg RCM_PLLMF_8  : PLL Multiplication Factor Configures to 8
+ *                        @arg RCM_PLLMF_9  : PLL Multiplication Factor Configures to 9
+ *                        @arg RCM_PLLMF_6_5: PLL Multiplication Factor Configures to 6.5
+ *                       For other devices:
+ *                        This parameter can be RCM_PLLMF_x where x can be a value from 2 to 16.
  *
  * @retval    None
  *
@@ -224,13 +257,16 @@ void RCM_DisableLSI(void)
  */
 void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf)
 {
-    RCM->CFG_B.PLLMULCFG = pllMf;
-    RCM->CFG_B.PLLSRCSEL = pllSelect & 0x01;
+    RCM->CFG_B.PLL1MULCFG = pllMf;
+    RCM->CFG_B.PLL1SRCSEL = pllSelect & 0x01;
+
+#ifndef APM32F10X_CL
     RCM->CFG_B.PLLHSEPSC = (pllSelect >> 1) & 0x01;
+#endif
 }
 
 /*!
- * @brief      Enables the PLL
+ * @brief      Enable the PLL
  *
  * @param      None
  *
@@ -238,23 +274,139 @@ void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf)
  */
 void RCM_EnablePLL(void)
 {
-    RCM->CTRL_B.PLLEN = BIT_SET;
+    RCM->CTRL_B.PLL1EN = BIT_SET;
 }
 
 /*!
-* @brief      Disable the PLL
-*
-* @param      None
-*
-* @retval     None
-*
-* @note       When PLL is not used as system clock, it can be stopped.
-*/
+ * @brief      Disable the PLL
+ *
+ * @param      None
+ *
+ * @retval     None
+ *
+ * @note       When PLL is not used as system clock, it can be stopped.
+ */
 void RCM_DisablePLL(void)
 {
-    RCM->CTRL_B.PLLEN = BIT_RESET;
+    RCM->CTRL_B.PLL1EN = BIT_RESET;
+}
+
+#if defined(APM32F10X_CL)
+/*!
+ * @brief      Enable the PLL2
+ *
+ * @param      None
+ *
+ * @retval     None
+ */
+void RCM_EnablePLL2(void)
+{
+    RCM->CTRL_B.PLL2EN = BIT_SET;
+}
+
+/*!
+ * @brief      Disable the PLL2
+ *
+ * @param      None
+ *
+ * @retval     None
+ */
+void RCM_DisablePLL2(void)
+{
+    RCM->CTRL_B.PLL2EN = BIT_RESET;
+}
+
+/*!
+ * @brief      Enable the PLL3
+ *
+ * @param      None
+ *
+ * @retval     None
+ */
+void RCM_EnablePLL3(void)
+{
+    RCM->CTRL_B.PLL3EN = BIT_SET;
+}
+
+/*!
+ * @brief      Disable the PLL3
+ *
+ * @param      None
+ *
+ * @retval     None
+ */
+void RCM_DisablePLL3(void)
+{
+    RCM->CTRL_B.PLL3EN = BIT_RESET;
+}
+
+/*!
+ * @brief     Configures the PLL prescaler 1 factor.
+ *
+ * @param     pllPsc1Src: PLL prescaler 1 source select
+ *                        This parameter can be one of the following values:
+ *                        @arg RCM_PLLPSC1_SRC_HSE : HSE clock selected as PLL prescaler 1 clock source
+ *                        @arg RCM_PLLPSC1_SRC_PLL2: PLL2 clock selected as PLL prescaler 1 clock source
+ *
+ * @param     pllPsc1: PLL prescaler 1 factor
+ *                     This parameter can be RCM_PLLPSC1_DIV_x where x can be a value from 1 to 16.
+ *
+ * @retval    None
+ *
+ * @note      PLL should be disabled while use this function.
+ */
+void RCM_ConfigPLLPSC1(RCM_PLLPSC1_SRC_T pllPsc1Src,  RCM_PLLPSC1_DIV_T pllPsc1)
+{
+    RCM->CFG2_B.PLLPSC1SRC = pllPsc1Src;
+    RCM->CFG2_B.PLLPSC1 = pllPsc1;
 }
 
+/*!
+ * @brief     Configures the PLL prescaler 2 factor.
+ *
+ * @param     pllpsc2: PLL prescaler 2 factor
+ *                     This parameter can be RCM_PLLPSC2_DIV_x where x can be a value from 1 to 16.
+ *
+ * @retval    None
+ *
+ * @note      PLL2 and PLL3 should be disabled while use this function.
+ */
+void RCM_ConfigPLLPSC2(RCM_PLLPSC2_DIV_T pllpsc2)
+{
+    RCM->CFG2_B.PLLPSC2 = pllpsc2;
+}
+
+/*!
+ * @brief     Configures the PLL2 clock multiplication factor
+ *
+ * @param     pll2Mf:  PLL2 multiplication factor
+ *                     This parameter can be RCM_PLL2MF_x where x can be a value from 8 to 14, and 16, 20.
+ *
+ * @retval    None
+ *
+ * @note      PLL2 should be disabled while use this function.
+ */
+void RCM_ConfigPLL2(RCM_PLL2MF_T pll2Mf)
+{
+    RCM->CFG2_B.PLL2MUL = pll2Mf;
+}
+
+/*!
+ * @brief     Configures the PLL3 clock multiplication factor
+ *
+ * @param     pll3Mf:  PLL3 multiplication factor
+ *                     This parameter can be RCM_PLL3MF_x where x can be a value from 8 to 14, and 16, 20.
+ *
+ * @retval    None
+ *
+ * @note      PLL3 should be disabled while use this function.
+ */
+void RCM_ConfigPLL3(RCM_PLL3MF_T pll3Mf)
+{
+    RCM->CFG2_B.PLL3MUL = pll3Mf;
+}
+#endif
+
 /*!
  * @brief     Enable the Clock Security System
  *
@@ -280,15 +432,20 @@ void RCM_DisableCSS(void)
 }
 
 /*!
- * @brief     Selects the MCO pin clock ouput source
+ * @brief     Select the MCO pin clock output source
  *
  * @param     mcoClock: specifies the clock source to output
  *                      This parameter can be one of the following values:
- *                      @arg RCM_MCOCLK_NO_CLOCK     : No clock selected.
- *                      @arg RCM_MCOCLK_SYSCLK       : System clock selected.
- *                      @arg RCM_MCOCLK_HSI          : HSI oscillator clock selected.
- *                      @arg RCM_MCOCLK_HSE          : HSE oscillator clock selected.
- *                      @arg RCM_MCOCLK_PLLCLK_DIV_2 : PLL clock divided by 2 selected.
+ *                       @arg RCM_MCOCLK_NO_CLOCK     : No clock selected.
+ *                       @arg RCM_MCOCLK_SYSCLK       : System clock selected.
+ *                       @arg RCM_MCOCLK_HSI          : HSI oscillator clock selected.
+ *                       @arg RCM_MCOCLK_HSE          : HSE oscillator clock selected.
+ *                       @arg RCM_MCOCLK_PLLCLK_DIV_2 : PLL clock divided by 2 selected.
+ *                      The following values is only for APM32F105xx or APM32F107xx:
+ *                       @arg RCM_MCOCLK_PLL2CLK       : PLL2 clock selected.
+ *                       @arg RCM_MCOCLK_PLL3CLK_DIV_2 : PLL3 clock divided by 2 selected.
+ *                       @arg RCM_MCOCLK_OSCCLK        : OSC clock selected.
+ *                       @arg RCM_MCOCLK_PLL3CLK       : PLL3 clock selected.
  *
  * @retval    None
  */
@@ -306,7 +463,7 @@ void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock)
  *                         @arg RCM_SYSCLK_SEL_HSE: HSE is selected as system clock source
  *                         @arg RCM_SYSCLK_SEL_PLL: PLL is selected as system clock source
  *
- * @retva    None
+ * @retval    None
  */
 void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect)
 {
@@ -314,7 +471,7 @@ void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect)
 }
 
 /*!
- * @brief     Returns the clock source which is used as system clock
+ * @brief     Return the clock source which is used as system clock
  *
  * @param     None
  *
@@ -326,7 +483,7 @@ RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void)
 }
 
 /*!
- * @brief     Configs the AHB clock prescaler.
+ * @brief     Configures the AHB clock prescaler.
  *
  * @param     AHBDiv : Specifies the AHB clock prescaler from the system clock.
  *                     This parameter can be one of the following values:
@@ -348,7 +505,7 @@ void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv)
 }
 
 /*!
- * @brief     Configs the APB1 clock prescaler.
+ * @brief     Configures the APB1 clock prescaler.
  *
  * @param     APB1Div: Specifies the APB1 clock prescaler from the AHB clock.
  *                     This parameter can be one of the following values:
@@ -366,7 +523,7 @@ void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div)
 }
 
 /*!
- * @brief     Configs the APB2 clock prescaler
+ * @brief     Configures the APB2 clock prescaler
  *
  * @param     APB2Div: Specifies the APB2 clock prescaler from the AHB clock.
  *                     This parameter can be one of the following values:
@@ -383,8 +540,58 @@ void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div)
     RCM->CFG_B.APB2PSC = APB2Div;
 }
 
+#if defined(APM32F10X_CL)
+/*!
+ * @brief     Configures the I2S2 clock source.
+ *
+ * @param     i2s2ClkSelect: specifies the I2S2 clock source.
+ *                           This parameter can be one of the following values:
+ *                           @arg RCM_I2S2CLK_SYSCLK     : I2S2CLK = System clock
+ *                           @arg RCM_I2S2CLK_DOUBLE_PLL3: I2S2CLK = Double PLL3 clock
+ *
+ * @retval    None
+ *
+ * @note      I2S2 clock source should be changed when I2S2 Clock is disabled.
+ */
+void RCM_ConfigI2S2CLK(RCM_I2S2CLK_T i2s2ClkSelect)
+{
+    RCM->CFG2_B.I2S2SRCSEL = i2s2ClkSelect;
+}
+
 /*!
- * @brief     Configs the USB clock prescaler
+ * @brief     Configures the I2S3 clock source.
+ *
+ * @param     i2s3ClkSelect: specifies the I2S3 clock source.
+ *                           This parameter can be one of the following values:
+ *                           @arg RCM_I2S3CLK_SYSCLK     : I2S3CLK = System clock
+ *                           @arg RCM_I2S3CLK_DOUBLE_PLL3: I2S3CLK = Double PLL3 clock
+ *
+ * @retval    None
+ *
+ * @note      I2S3 clock source should be changed when I2S3 Clock is disabled.
+ */
+void RCM_ConfigI2S3CLK(RCM_I2S2CLK_T i2s3ClkSelect)
+{
+    RCM->CFG2_B.I2S3SRCSEL = i2s3ClkSelect;
+}
+
+/*!
+ * @brief     Configures the OTG FS clock prescaler
+ *
+ * @param     OTGDiv: Specifies the OTG FS clock prescaler from the PLL clock.
+ *                     This parameter can be one of the following values:
+ *                     @arg RCM_OTGFS_DIV_1_5 : OTGFSCLK = PLL clock /1.5
+ *                     @arg RCM_OTGFS_DIV_1   : OTGFSCLK = PLL clock
+ *
+ * @retval    None
+ */
+void RCM_ConfigOTGFSCLK(RCM_OTGFS_DIV_T OTGDiv)
+{
+    RCM->CFG_B.OTGFSPSC = OTGDiv;
+}
+#else
+/*!
+ * @brief     Configures the USB clock prescaler
  *
  * @param     USBDiv: Specifies the USB clock prescaler from the PLL clock.
  *                     This parameter can be one of the following values:
@@ -401,7 +608,7 @@ void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv)
 }
 
 /*!
- * @brief     Configs the FPU clock prescaler
+ * @brief     Configures the FPU clock prescaler
  *
  * @param     FPUDiv: Specifies the FPU clock prescaler from the AHB clock.
  *                     This parameter can be one of the following values:
@@ -414,9 +621,11 @@ void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv)
 {
     RCM->CFG_B.FPUPSC = FPUDiv;
 }
+#endif
+
 
 /*!
- * @brief     Configs the ADC clock prescaler
+ * @brief     Configures the ADC clock prescaler
  *
  * @param     ADCDiv : Specifies the ADC clock prescaler from the APB2 clock.
  *                     This parameter can be one of the following values:
@@ -443,7 +652,7 @@ void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv)
  *
  * @retval    None
  *
- * @note      Once the RTC clock is configed it can't be changed unless reset the Backup domain.
+ * @note      Once the RTC clock is configured it can't be changed unless reset the Backup domain.
  */
 void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect)
 {
@@ -451,7 +660,7 @@ void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect)
 }
 
 /*!
- * @brief     Enables the RTC clock
+ * @brief     Enable the RTC clock
  *
  * @param     None
  *
@@ -463,7 +672,7 @@ void RCM_EnableRTCCLK(void)
 }
 
 /*!
- * @brief     Disables the RTC clock
+ * @brief     Disable the RTC clock
  *
  * @param     None
  *
@@ -475,7 +684,7 @@ void RCM_DisableRTCCLK(void)
 }
 
 /*!
- * @brief     Reads the frequency of SYSCLK
+ * @brief     Read the frequency of SYSCLK
  *
  * @param     None
  *
@@ -483,57 +692,102 @@ void RCM_DisableRTCCLK(void)
  */
 uint32_t RCM_ReadSYSCLKFreq(void)
 {
+#ifdef APM32F10X_CL
+    uint32_t sysClock, pllMull, pllSource, pll2Mull, pllPsc1, pllPsc2;
+#else
     uint32_t sysClock, pllMull, pllSource;
+#endif
 
-    /** get sys clock */
+    /* get sys clock */
     sysClock = RCM->CFG_B.SCLKSEL;
 
     switch (sysClock)
     {
-    /** sys clock is HSI */
-    case RCM_SYSCLK_SEL_HSI:
-        sysClock = HSI_VALUE;
-        break;
-
-    /** sys clock is HSE */
-    case RCM_SYSCLK_SEL_HSE:
-        sysClock = HSE_VALUE;
-        break;
-
-    /** sys clock is PLL */
-    case RCM_SYSCLK_SEL_PLL:
-        pllMull = RCM->CFG_B.PLLMULCFG + 2;
-        pllSource = RCM->CFG_B.PLLSRCSEL;
-
-        /** PLL entry clock source is HSE */
-        if (pllSource == BIT_SET)
-        {
-            sysClock = HSE_VALUE * pllMull;
+        /* sys clock is HSI */
+        case RCM_SYSCLK_SEL_HSI:
+            sysClock = HSI_VALUE;
+            break;
+
+        /* sys clock is HSE */
+        case RCM_SYSCLK_SEL_HSE:
+            sysClock = HSE_VALUE;
+            break;
+
+        /* sys clock is PLL */
+        case RCM_SYSCLK_SEL_PLL:
+#ifdef APM32F10X_CL
+            /* NOTE : PLL is the same as PLL1 */
+            pllSource = RCM->CFG_B.PLL1SRCSEL;
+
+            /* PLL entry clock source is HSE */
+            if (pllSource)
+            {
+                /* PLLPSC1 prescaler factor */
+                pllPsc1 = (RCM->CFG2_B.PLLPSC1 + 1);
+
+                /* PLL entry clock source is PLL2 */
+                if (RCM->CFG2_B.PLLPSC1SRC)
+                {
+                    pll2Mull = (RCM->CFG2_B.PLL2MUL != 15) ? (RCM->CFG2_B.PLL2MUL + 2) : 20;
+                    pllPsc2 = RCM->CFG2_B.PLLPSC2 + 1;
+
+                    pllSource = ((HSE_VALUE / pllPsc2) * pll2Mull) / pllPsc1;
+                }
+                /* PLL entry clock source is HSE */
+                else
+                {
+                    pllSource = HSE_VALUE / pllPsc1;
+                }
+            }
+            /* PLL entry clock source is HSI/2 */
+            else
+            {
+                pllSource = HSI_VALUE >> 1;
+            }
 
-            /** HSE clock divided by 2 */
-            if (pllSource == RCM->CFG_B.PLLHSEPSC)
+            pllMull = RCM->CFG_B.PLL1MULCFG;
+            if (pllMull == 13)
             {
-                sysClock >>= 1;
+                /* For 6.5 multiplication factor */
+                sysClock = pllSource * pllMull / 2;
             }
-        }
-        /** PLL entry clock source is HSI/2 */
-        else
-        {
-            sysClock = (HSI_VALUE >> 1) * pllMull;
-        }
+            else
+            {
+                sysClock = pllSource * (pllMull + 2);
+            }
+#else
+            pllMull = RCM->CFG_B.PLL1MULCFG + 2;
+            pllSource = RCM->CFG_B.PLL1SRCSEL;
 
-        break;
+            /* PLL entry clock source is HSE */
+            if (pllSource == BIT_SET)
+            {
+                sysClock = HSE_VALUE * pllMull;
 
-    default:
-        sysClock  = HSI_VALUE;
-        break;
+                /* HSE clock divided by 2 */
+                if (pllSource == RCM->CFG_B.PLLHSEPSC)
+                {
+                    sysClock >>= 1;
+                }
+            }
+            /* PLL entry clock source is HSI/2 */
+            else
+            {
+                sysClock = (HSI_VALUE >> 1) * pllMull;
+            }
+#endif
+            break;
+
+        default:
+            sysClock  = HSI_VALUE;
+            break;
     }
 
     return sysClock;
 }
 
 /*!
- * @brief     Reads the frequency of HCLK(AHB)
+ * @brief     Read the frequency of HCLK(AHB)
  *
  * @param     None
  *
@@ -553,7 +807,7 @@ uint32_t RCM_ReadHCLKFreq(void)
 }
 
 /*!
- * @brief     Reads the frequency of PCLK1 And PCLK2
+ * @brief     Read the frequency of PCLK1 And PCLK2
  *
  * @param     PCLK1 : Return the frequency of PCLK1
  *
@@ -561,7 +815,7 @@ uint32_t RCM_ReadHCLKFreq(void)
  *
  * @retval    None
  */
-void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2)
+void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2)
 {
     uint32_t hclk, divider;
     uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
@@ -582,7 +836,7 @@ void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2)
 }
 
 /*!
- * @brief     Reads the frequency of ADCCLK
+ * @brief     Read the frequency of ADCCLK
  *
  * @param     None
  *
@@ -595,7 +849,7 @@ uint32_t RCM_ReadADCCLKFreq(void)
 
     RCM_ReadPCLKFreq(NULL, &pclk2);
 
-    /** Get ADC CLK */
+    /* Get ADC CLK */
     divider = ADCPrescTable[RCM->CFG_B.ADCPSC];
     adcClk = pclk2 / divider;
 
@@ -603,19 +857,23 @@ uint32_t RCM_ReadADCCLKFreq(void)
 }
 
 /*!
- * @brief    Enables AHB peripheral clock.
+ * @brief    Enable AHB peripheral clock.
  *
  * @param    AHBPeriph : Enable the specifies clock of AHB peripheral.
  *                       This parameter can be any combination of the following values:
- *                       @arg RCM_AHB_PERIPH_DMA1 : Enable DMA1 clock
- *                       @arg RCM_AHB_PERIPH_DMA2 : Enable DMA2 clock (Only for High-density devices for APM32F103xx)
- *                       @arg RCM_AHB_PERIPH_SRAM : Enable SRAM clock
- *                       @arg RCM_AHB_PERIPH_FPU  : Enable FPU clock
- *                       @arg RCM_AHB_PERIPH_FMC  : Enable FMC clock
- *                       @arg RCM_AHB_PERIPH_QSPI : Enable QSPI clock
- *                       @arg RCM_AHB_PERIPH_CRC  : Enable CRC clock
- *                       @arg RCM_AHB_PERIPH_EMMC : Enable EMMC clock (Only for High-density devices for APM32F103xx)
- *                       @arg RCM_AHB_PERIPH_SDIO : Enable SDIO clock (Only for High-density devices for APM32F103xx)
+ *                       @arg RCM_AHB_PERIPH_DMA1       : Enable DMA1 clock
+ *                       @arg RCM_AHB_PERIPH_DMA2       : Enable DMA2 clock (Only for High-density devices for APM32F103xx)
+ *                       @arg RCM_AHB_PERIPH_SRAM       : Enable SRAM clock
+ *                       @arg RCM_AHB_PERIPH_FPU        : Enable FPU clock
+ *                       @arg RCM_AHB_PERIPH_FMC        : Enable FMC clock
+ *                       @arg RCM_AHB_PERIPH_QSPI       : Enable QSPI clock
+ *                       @arg RCM_AHB_PERIPH_CRC        : Enable CRC clock
+ *                       @arg RCM_AHB_PERIPH_EMMC       : Enable EMMC clock (Only for High-density devices for APM32F103xx)
+ *                       @arg RCM_AHB_PERIPH_SDIO       : Enable SDIO clock (Only for High-density devices for APM32F103xx)
+ *                       @arg RCM_AHB_PERIPH_OTG_FS     : Enable OTG FS clock (Only for APM32F105xx or APM32F107xx)
+ *                       @arg RCM_AHB_PERIPH_ETH_MAC    : Enable Ethernet MAC clock (Only for APM32F105xx or APM32F107xx)
+ *                       @arg RCM_AHB_PERIPH_ETH_MAC_TX : Enable Ethernet MAC TX clock (Only for APM32F105xx or APM32F107xx)
+ *                       @arg RCM_AHB_PERIPH_ETH_MAC_RX : Enable Ethernet MAC RX clock (Only for APM32F105xx or APM32F107xx)
  *
  * @retval   None
  */
@@ -627,17 +885,21 @@ void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph)
 /*!
  * @brief    Disable AHB peripheral clock.
  *
- * @param    AHBPeriph : Disable the specifies clock of AHB peripheral.
+ * @param    AHBPeriph : Enable the specifies clock of AHB peripheral.
  *                       This parameter can be any combination of the following values:
- *                       @arg RCM_AHB_PERIPH_DMA1 : Disable DMA1 clock
- *                       @arg RCM_AHB_PERIPH_DMA2 : Disable DMA2 clock (Only for High-density devices for APM32F103xx)
- *                       @arg RCM_AHB_PERIPH_SRAM : Disable SRAM clock
- *                       @arg RCM_AHB_PERIPH_FPU  : Disable FPU clock
- *                       @arg RCM_AHB_PERIPH_FMC  : Disable FMC clock
- *                       @arg RCM_AHB_PERIPH_QSPI : Disable QSPI clock
- *                       @arg RCM_AHB_PERIPH_CRC  : Disable CRC clock
- *                       @arg RCM_AHB_PERIPH_EMMC : Disable EMMC clock (Only for High-density devices for APM32F103xx)
- *                       @arg RCM_AHB_PERIPH_SDIO : Disable SDIO clock (Only for High-density devices for APM32F103xx)
+ *                       @arg RCM_AHB_PERIPH_DMA1       : Disable DMA1 clock
+ *                       @arg RCM_AHB_PERIPH_DMA2       : Disable DMA2 clock (Only for High-density devices for APM32F103xx)
+ *                       @arg RCM_AHB_PERIPH_SRAM       : Disable SRAM clock
+ *                       @arg RCM_AHB_PERIPH_FPU        : Disable FPU clock
+ *                       @arg RCM_AHB_PERIPH_FMC        : Disable FMC clock
+ *                       @arg RCM_AHB_PERIPH_QSPI       : Disable QSPI clock
+ *                       @arg RCM_AHB_PERIPH_CRC        : Disable CRC clock
+ *                       @arg RCM_AHB_PERIPH_EMMC       : Disable EMMC clock (Only for High-density devices for APM32F103xx)
+ *                       @arg RCM_AHB_PERIPH_SDIO       : Disable SDIO clock (Only for High-density devices for APM32F103xx)
+ *                       @arg RCM_AHB_PERIPH_OTG_FS     : Disable OTG FS clock (Only for APM32F105xx or APM32F107xx)
+ *                       @arg RCM_AHB_PERIPH_ETH_MAC    : Disable Ethernet MAC clock (Only for APM32F105xx or APM32F107xx)
+ *                       @arg RCM_AHB_PERIPH_ETH_MAC_TX : Disable Ethernet MAC TX clock (Only for APM32F105xx or APM32F107xx)
+ *                       @arg RCM_AHB_PERIPH_ETH_MAC_RX : Disable Ethernet MAC RX clock (Only for APM32F105xx or APM32F107xx)
  *
  * @retval   None
  */
@@ -770,6 +1032,36 @@ void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph)
     RCM->APB1CLKEN &= (uint32_t)~APB1Periph;
 }
 
+#if defined(APM32F10X_CL)
+/*!
+ * @brief    Enable AHB peripheral reset
+ *
+ * @param    AHBPeriph : Enable specifies AHB peripheral reset.
+ *                       This parameter can be any combination of the following values:
+ *                       @arg RCM_AHB_PERIPH_OTG_FS  : Enable OTG FS reset
+ *                       @arg RCM_AHB_PERIPH_ETH_MAC : Enable ETH MAC reset *
+ * @retval   None
+ */
+void RCM_EnableAHBPeriphReset(uint32_t AHBPeriph)
+{
+    RCM->AHBRST |= AHBPeriph;
+}
+
+/*!
+ * @brief    Disable AHB peripheral reset
+ *
+ * @param    AHBPeriph : Disable specifies AHB peripheral reset.
+ *                       This parameter can be any combination of the following values:
+ *                       @arg RCM_AHB_PERIPH_OTG_FS  : Disable OTG FS reset
+ *                       @arg RCM_AHB_PERIPH_ETH_MAC : Disable ETH MAC reset *
+ * @retval   None
+ */
+void RCM_DisableAHBPeriphReset(uint32_t AHBPeriph)
+{
+    RCM->AHBRST &= (uint32_t)~AHBPeriph;
+}
+#endif
+
 /*!
  * @brief    Enable High Speed APB (APB2) peripheral reset
  *
@@ -929,6 +1221,8 @@ void RCM_DisableBackupReset(void)
  *                        @arg RCM_INT_HSIRDY : HSI ready interrupt
  *                        @arg RCM_INT_HSERDY : HSE ready interrupt
  *                        @arg RCM_INT_PLLRDY : PLL ready interrupt
+ *                        @arg RCM_INT_PLL2RDY: PLL2 ready interrupt
+ *                        @arg RCM_INT_PLL3RDY: PLL3 ready interrupt
  *
  * @retval    None
  */
@@ -966,11 +1260,13 @@ void RCM_DisableInterrupt(uint32_t interrupt)
 /*!
  * @brief     Read the specified RCM flag status
  *
- * @param     flag : Returns specifies the flag status.
+ * @param     flag : Return specifies the flag status.
  *                   This parameter can be one of the following values:
  *                   @arg RCM_FLAG_HSIRDY  : HSI ready flag
  *                   @arg RCM_FLAG_HSERDY  : HSE ready flag
  *                   @arg RCM_FLAG_PLLRDY  : PLL ready flag
+ *                   @arg RCM_FLAG_PLL2RDY : PLL2 ready flag (Only for APM32F105xx or APM32F107xx)
+ *                   @arg RCM_FLAG_PLL3RDY : PLL3 ready flag (Only for APM32F105xx or APM32F107xx)
  *                   @arg RCM_FLAG_LSERDY  : LSE ready flag
  *                   @arg RCM_FLAG_LSIRDY  : LSI ready flag
  *                   @arg RCM_FLAG_PINRST  : NRST PIN Reset Occur Flag
@@ -992,20 +1288,20 @@ uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag)
 
     switch (reg)
     {
-    case 0:
-        reg = RCM->CTRL;
-        break;
+        case 0:
+            reg = RCM->CTRL;
+            break;
 
-    case 1:
-        reg = RCM->BDCTRL;
-        break;
+        case 1:
+            reg = RCM->BDCTRL;
+            break;
 
-    case 2:
-        reg = RCM->CSTS;
-        break;
+        case 2:
+            reg = RCM->CSTS;
+            break;
 
-    default:
-        break;
+        default:
+            break;
     }
 
     if (reg & bit)
@@ -1017,7 +1313,7 @@ uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag)
 }
 
 /*!
- * @brief     Clears all the RCM reset flags
+ * @brief     Clear all the RCM reset flags
  *
  * @param     None
  *
@@ -1033,33 +1329,37 @@ void RCM_ClearStatusFlag(void)
 }
 
 /*!
- * @brief     Reads the specified RCM interrupt Flag
+ * @brief     Read the specified RCM interrupt Flag
  *
- * @param     flag ：Reads specifies RCM interrupt flag.
+ * @param     flag ��Reads specifies RCM interrupt flag.
  *                   This parameter can be one of the following values:
  *                   @arg RCM_INT_LSIRDY : LSI ready interrupt flag
  *                   @arg RCM_INT_LSERDY : LSE ready interrupt flag
  *                   @arg RCM_INT_HSIRDY : HSI ready interrupt flag
  *                   @arg RCM_INT_HSERDY : HSE ready interrupt flag
  *                   @arg RCM_INT_PLLRDY : PLL ready interrupt flag
+ *                   @arg RCM_INT_PLL2RDY: PLL2 ready interrupt flag
+ *                   @arg RCM_INT_PLL3RDY: PLL3 ready interrupt flag
  *                   @arg RCM_INT_CSS    : Clock Security System interrupt flag
  *
  * @retval    The new state of intFlag (SET or RESET)
  */
 uint8_t RCM_ReadIntFlag(RCM_INT_T flag)
 {
-    return (RCM->INT &flag) ? SET : RESET;
+    return (RCM->INT& flag) ? SET : RESET;
 }
 
 /*!
- * @brief     Clears the interrupt flag
+ * @brief     Clear the interrupt flag
  *
- * @param     flag : Clears specifies interrupt flag.
+ * @param     flag : Clear specifies interrupt flag.
  *                   @arg RCM_INT_LSIRDY : Clear LSI ready interrupt flag
  *                   @arg RCM_INT_LSERDY : Clear LSE ready interrupt flag
  *                   @arg RCM_INT_HSIRDY : Clear HSI ready interrupt flag
  *                   @arg RCM_INT_HSERDY : Clear HSE ready interrupt flag
  *                   @arg RCM_INT_PLLRDY : Clear PLL ready interrupt flag
+ *                   @arg RCM_INT_PLL2RDY: Clear PLL2 ready interrupt flag
+ *                   @arg RCM_INT_PLL3RDY: Clear PLL3 ready interrupt flag
  *                   @arg RCM_INT_CSS    : Clear Clock Security System interrupt flag
  *
  * @retval    None
@@ -1072,6 +1372,6 @@ void RCM_ClearIntFlag(uint32_t flag)
     RCM->INT |= temp;
 }
 
-/**@} end of group RCM_Fuctions*/
-/**@} end of group RCM_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group RCM_Functions */
+/**@} end of group RCM_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the RTC firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,24 +15,26 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
  *  and limitations under the License.
  */
+
 #include "apm32f10x_rtc.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup RTC_Driver RTC Driver
+  * @brief RTC driver modules
   @{
 */
 
-/** @addtogroup RTC_Fuctions Fuctions
+/** @defgroup RTC_Functions Functions
   @{
 */
 
@@ -76,7 +78,7 @@ uint32_t RTC_ReadCounter(void)
 }
 
 /*!
- * @brief     Config the RTC counter value.
+ * @brief     Configures the RTC counter value.
  *
  * @param     value: RTC counter new value.
  *
@@ -91,7 +93,7 @@ void RTC_ConfigCounter(uint32_t value)
 }
 
 /*!
- * @brief     Config the RTC prescaler value.
+ * @brief     Configures the RTC prescaler value.
  *
  * @param     value: RTC prescaler new value.
  *
@@ -106,7 +108,7 @@ void RTC_ConfigPrescaler(uint32_t value)
 }
 
 /*!
- * @brief     Config the RTC alarm value.
+ * @brief     Configures the RTC alarm value.
  *
  * @param     value: RTC alarm new value.
  *
@@ -121,7 +123,7 @@ void RTC_ConfigAlarm(uint32_t value)
 }
 
 /*!
- * @brief     Reads the RTC divider value.
+ * @brief     Read the RTC divider value.
  *
  * @param     None
  *
@@ -150,13 +152,13 @@ void RTC_WaitForLastTask(void)
 }
 
 /*!
- * @brief     Waits until the RTC registers
+ * @brief     Waits until the RTC registers Synchronized.
  *
  * @param     None
  *
  * @retval    None
  */
-void RTC_WaitForSynchor(void)
+void RTC_WaitForSynchro(void)
 {
     RTC->CSTS_B.RSYNCFLG = BIT_RESET;
     while (RTC->CSTS_B.RSYNCFLG == BIT_RESET);
@@ -258,6 +260,6 @@ void RTC_ClearIntFlag(uint16_t flag)
     RTC->CSTS &= (uint32_t)~flag;
 }
 
-/**@} end of group RTC_Fuctions*/
-/**@} end of group RTC_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group RTC_Functions */
+/**@} end of group RTC_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions for the SCI2C peripheral
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,26 +26,27 @@
 #include "apm32f10x_sci2c.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup SCI2C_Driver SCI2C Driver
+  * @brief SCI2C driver modules
   @{
 */
 
-/** @addtogroup SCI2C_Fuctions Fuctions
+/** @defgroup SCI2C_Functions Functions
   @{
 */
 
 /*!
  * @brief       Set I2C peripheral registers to their default reset values
  *
- * @param       i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c: Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      None
  */
-void SCI2C_Reset(SCI2C_T *i2c)
+void SCI2C_Reset(SCI2C_T* i2c)
 {
     if (i2c == I2C3)
     {
@@ -64,7 +65,7 @@ void SCI2C_Reset(SCI2C_T *i2c)
 }
 
 /*!
- * @brief       Config the I2C peripheral according to the specified parameters in the sci2cConfig
+ * @brief       Configures the I2C peripheral according to the specified parameters in the sci2cConfig
  *
  * @param       i2c: Select the the I2C peripheral.It can be I2C3 or I2C4
  *
@@ -72,7 +73,7 @@ void SCI2C_Reset(SCI2C_T *i2c)
  *
  * @retval      None
  */
-void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig)
+void SCI2C_Config(SCI2C_T* i2c, SCI2C_Config_T* sci2cConfig)
 {
     i2c->SW = BIT_SET;
 
@@ -122,7 +123,7 @@ void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig)
  *
  * @retval      None
  */
-void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig)
+void SCI2C_ConfigStructInit(SCI2C_Config_T* sci2cConfig)
 {
     sci2cConfig->addrMode = SCI2C_ADDR_MODE_7BIT;
     sci2cConfig->slaveAddr = 0x55;
@@ -138,7 +139,7 @@ void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig)
 /*!
  * @brief       Read specified flag
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       flag:   Specifies the flag to be checked
  *                      The parameter can be one of following values:
@@ -155,7 +156,7 @@ void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig)
  *
  * @retval      The new state of flag (SET or RESET)
  */
-uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag)
+uint8_t SCI2C_ReadStatusFlag(SCI2C_T* i2c, SCI2C_FLAG_T flag)
 {
     uint8_t ret = RESET;
 
@@ -174,7 +175,7 @@ uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag)
 /*!
  * @brief       Read specified interrupt flag
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       flag:   Specifies the interrupt flag to be checked
  *                      The parameter can be one of following values:
@@ -195,7 +196,7 @@ uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag)
  *
  * @retval      The new state of flag (SET or RESET)
  */
-uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
+uint8_t SCI2C_ReadIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag)
 {
     uint8_t ret = RESET;
 
@@ -207,7 +208,7 @@ uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
 /*!
  * @brief       Clear specified interrupt flag
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       flag:   Specifies the interrupt flag to be checked
  *                      The parameter can be one of following values:
@@ -224,7 +225,7 @@ uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
  *                      @arg SCI2C_INT_ALL:    All interrupt flag
  * @retval      The new state of flag (SET or RESET)
  */
-void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
+void SCI2C_ClearIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag)
 {
     volatile uint32_t dummy = 0;
 
@@ -277,7 +278,7 @@ void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
 /*!
  * @brief       Read specified interrupt flag(Raw register)
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       flag:   Specifies the interrupt flag to be checked
  *                      The parameter can be one of following values:
@@ -298,7 +299,7 @@ void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
  *
  * @retval      The new state of flag (SET or RESET)
  */
-uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
+uint8_t SCI2C_ReadRawIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag)
 {
     uint8_t ret = RESET;
 
@@ -310,7 +311,7 @@ uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
 /*!
  * @brief       Enable the specified interrupts
  *
- * @param       i2c:        Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:        Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       interrupt:  Specifies the interrupt sources
  *                          The parameter can be any combination of following values:
@@ -331,7 +332,7 @@ uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
  *
  * @retval      None
  */
-void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt)
+void SCI2C_EnableInterrupt(SCI2C_T* i2c, uint16_t interrupt)
 {
     i2c->INTEN |= interrupt;
 }
@@ -339,7 +340,7 @@ void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt)
 /*!
  * @brief       Disable the specified interrupts
  *
- * @param       i2c:        Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:        Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       interrupt:  Specifies the interrupt sources
  *                          The parameter can be any combination of following values:
@@ -360,7 +361,7 @@ void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt)
  *
  * @retval      None
  */
-void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt)
+void SCI2C_DisableInterrupt(SCI2C_T* i2c, uint16_t interrupt)
 {
     i2c->INTEN &= ~interrupt;
 }
@@ -368,9 +369,9 @@ void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt)
 /*!
  * @brief       Enable stop detected only master in activity.
  *
- * @param       i2c:   Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:   Select the the I2C peripheral. It can be I2C3 or I2C4
  */
-void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c)
+void SCI2C_EnableStopDetectMasterActivity(SCI2C_T* i2c)
 {
     i2c->CTRL1_B.DSMA = BIT_SET;
 }
@@ -378,9 +379,9 @@ void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c)
 /*!
  * @brief       Disable stop detected only master in activity.
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  */
-void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c)
+void SCI2C_DisableStopDetectMasterActivity(SCI2C_T* i2c)
 {
     i2c->CTRL1_B.DSMA = BIT_RESET;
 }
@@ -388,9 +389,9 @@ void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c)
 /*!
  * @brief       Enable stop detected only address is matched in slave mode.
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  */
-void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c)
+void SCI2C_EnableStopDetectAddressed(SCI2C_T* i2c)
 {
     i2c->CTRL1_B.DSA = BIT_SET;
 }
@@ -398,9 +399,9 @@ void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c)
 /*!
  * @brief       Disable stop detected only address is matched in slave mode.
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  */
-void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c)
+void SCI2C_DisableStopDetectAddressed(SCI2C_T* i2c)
 {
     i2c->CTRL1_B.DSA = BIT_RESET;
 }
@@ -408,11 +409,11 @@ void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c)
 /*!
  * @brief       Enable restart
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      None
  */
-void SCI2C_EnableRestart(SCI2C_T *i2c)
+void SCI2C_EnableRestart(SCI2C_T* i2c)
 {
     i2c->CTRL1_B.RSTAEN = BIT_SET;
 }
@@ -420,19 +421,19 @@ void SCI2C_EnableRestart(SCI2C_T *i2c)
 /*!
  * @brief       Disable restart
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      None
  */
-void SCI2C_DisableRestart(SCI2C_T *i2c)
+void SCI2C_DisableRestart(SCI2C_T* i2c)
 {
     i2c->CTRL1_B.RSTAEN = BIT_RESET;
 }
 
 /*!
- * @brief       Config speed.
+ * @brief       Configures speed.
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       speed:  Specifies the speed.
  *                      @arg SCI2C_SPEED_STANDARD:  Standard speed.
@@ -441,15 +442,15 @@ void SCI2C_DisableRestart(SCI2C_T *i2c)
  *
  * @retval      None
  */
-void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed)
+void SCI2C_ConfigSpeed(SCI2C_T* i2c, SCI2C_SPEED_T speed)
 {
     i2c->CTRL1_B.SPD = speed;
 }
 
 /*!
- * @brief       Config master address.
+ * @brief       Configures master address.
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       mode:   Specifies the address mode.
  *                      @arg SCI2C_ADDR_MODE_7BIT:      7-bit address mode.
@@ -459,7 +460,7 @@ void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed)
  *
  * @retval      None
  */
-void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr)
+void SCI2C_ConfigMasterAddr(SCI2C_T* i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr)
 {
     i2c->TARADDR_B.MAM = mode;
     i2c->TARADDR_B.ADDR = addr;
@@ -467,7 +468,7 @@ void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr)
 
 
 /*!
- * @brief       Config slave address.
+ * @brief       Configures slave address.
  *
  * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
  *
@@ -479,7 +480,7 @@ void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr)
  *
  * @retval      None
  */
-void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr)
+void SCI2C_ConfigSlaveAddr(SCI2C_T* i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr)
 {
     i2c->CTRL1_B.SAM = mode;
     i2c->SLAADDR = addr;
@@ -488,11 +489,11 @@ void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr)
 /*!
  * @brief       Enable master mode
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      None
  */
-void SCI2C_EnableMasterMode(SCI2C_T *i2c)
+void SCI2C_EnableMasterMode(SCI2C_T* i2c)
 {
     i2c->CTRL1_B.MST = BIT_SET;
 }
@@ -500,11 +501,11 @@ void SCI2C_EnableMasterMode(SCI2C_T *i2c)
 /*!
  * @brief       Disable master mode
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      None
  */
-void SCI2C_DisableMasterMode(SCI2C_T *i2c)
+void SCI2C_DisableMasterMode(SCI2C_T* i2c)
 {
     i2c->CTRL1_B.MST = BIT_RESET;
 }
@@ -512,11 +513,11 @@ void SCI2C_DisableMasterMode(SCI2C_T *i2c)
 /*!
  * @brief       Enable slave mode
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      None
  */
-void SCI2C_EnableSlaveMode(SCI2C_T *i2c)
+void SCI2C_EnableSlaveMode(SCI2C_T* i2c)
 {
     i2c->CTRL1_B.SLADIS = BIT_RESET;
 }
@@ -524,11 +525,11 @@ void SCI2C_EnableSlaveMode(SCI2C_T *i2c)
 /*!
  * @brief       Disable slave mode
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      None
  */
-void SCI2C_DisableSlaveMode(SCI2C_T *i2c)
+void SCI2C_DisableSlaveMode(SCI2C_T* i2c)
 {
     i2c->CTRL1_B.SLADIS = BIT_SET;
 }
@@ -536,13 +537,13 @@ void SCI2C_DisableSlaveMode(SCI2C_T *i2c)
 /*!
  * @brief       Config master code
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       code:   Master code
  *
  * @retval      None
  */
-void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code)
+void SCI2C_ConfigMasterCode(SCI2C_T* i2c, uint8_t code)
 {
     i2c->HSMC = code;
 }
@@ -550,7 +551,7 @@ void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code)
 /*!
  * @brief       Config data direction
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       dir:    Data direction
  *                      @arg SCI2C_DATA_DIR_WRITE:  Write data
@@ -558,7 +559,7 @@ void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code)
  *
  * @retval      None
  */
-void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir)
+void SCI2C_ConfigDataDir(SCI2C_T* i2c, SCI2C_DATA_DIR_T dir)
 {
     i2c->DATA = (uint32_t)(dir << 8);
 }
@@ -566,13 +567,13 @@ void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir)
 /*!
  * @brief       Transmit data
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       data:   Data to be transmited
  *
  * @retval      None
  */
-void SCI2C_TxData(SCI2C_T *i2c, uint8_t data)
+void SCI2C_TxData(SCI2C_T* i2c, uint8_t data)
 {
     i2c->DATA_B.DATA = data;
 }
@@ -580,20 +581,20 @@ void SCI2C_TxData(SCI2C_T *i2c, uint8_t data)
 /*!
  * @brief       Returns the most recent received data
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      Received data
  *
  */
-uint8_t SCI2C_RxData(SCI2C_T *i2c)
+uint8_t SCI2C_RxData(SCI2C_T* i2c)
 {
     return (uint8_t)(i2c->DATA & 0XFF);
 }
 
 /*!
- * @brief       Config data register
+ * @brief       Configures data register
  *
- * @param       i2c:        Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:        Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       stop:       Enable or disable generate stop condition
  *
@@ -605,7 +606,7 @@ uint8_t SCI2C_RxData(SCI2C_T *i2c)
  *
  * @retval      None
  */
-void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data)
+void SCI2C_ConfigDataRegister(SCI2C_T* i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data)
 {
     i2c->DATA = (uint32_t)((stop << 9) | (dataDir << 8) | data);
 }
@@ -613,11 +614,11 @@ void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T
 /*!
  * @brief       Read Rx FIFO data number
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      None
  */
-uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c)
+uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T* i2c)
 {
     return (uint8_t)i2c->RFL;
 }
@@ -625,39 +626,39 @@ uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c)
 /*!
  * @brief       Read Tx FIFO data number
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      None
  */
-uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c)
+uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T* i2c)
 {
     return (uint8_t)i2c->TFL;
 }
 
 /*!
- * @brief       Config Rx FIFO threshold
+ * @brief       Configures Rx FIFO threshold
  *
- * @param       i2c:        Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:        Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       threshold:  FIFO threshold
  *
  * @retval      None
  */
-void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold)
+void SCI2C_ConfigRxFifoThreshold(SCI2C_T* i2c, uint8_t threshold)
 {
     i2c->RFT = threshold;
 }
 
 /*!
- * @brief       Config Tx FIFO threshold
+ * @brief       Configures Tx FIFO threshold
  *
- * @param       i2c:        Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:        Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       threshold:  FIFO threshold
  *
  * @retval      None
  */
-void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold)
+void SCI2C_ConfigTxFifoThreshold(SCI2C_T* i2c, uint8_t threshold)
 {
     i2c->TFT = threshold;
 }
@@ -665,12 +666,12 @@ void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold)
 /*!
  * @brief       Enable I2C peripheral
  *
- * @param       i2c:        Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:        Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      None
 
  */
-void SCI2C_Enable(SCI2C_T *i2c)
+void SCI2C_Enable(SCI2C_T* i2c)
 {
     i2c->CTRL2_B.I2CEN = BIT_SET;
 }
@@ -678,11 +679,11 @@ void SCI2C_Enable(SCI2C_T *i2c)
 /*!
  * @brief       Disable I2C peripheral
  *
- * @param       i2c:        Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:        Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      None
  */
-void SCI2C_Disable(SCI2C_T *i2c)
+void SCI2C_Disable(SCI2C_T* i2c)
 {
     i2c->CTRL2_B.I2CEN = BIT_RESET;
 }
@@ -690,11 +691,11 @@ void SCI2C_Disable(SCI2C_T *i2c)
 /*!
  * @brief       Abort I2C transmit
  *
- * @param       i2c:        Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:        Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      None
  */
-void SCI2C_Abort(SCI2C_T *i2c)
+void SCI2C_Abort(SCI2C_T* i2c)
 {
     i2c->CTRL2_B.ABR = BIT_SET;
 }
@@ -702,21 +703,21 @@ void SCI2C_Abort(SCI2C_T *i2c)
 /*!
  * @brief       Tx command block
  *
- * @param       i2c:        Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:        Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       enable:     ENABLE or DISABLE
  *
  * @retval      None
  */
-void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable)
+void SCI2C_BlockTxCmd(SCI2C_T* i2c, uint8_t enable)
 {
     i2c->CTRL2_B.TCB = enable;
 }
 
 /*!
- * @brief       Config SCL high and low period
+ * @brief       Configures SCL high and low period
  *
- * @param       i2c:        Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:        Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       speed:      Specifies the speed.
  *                          @arg SCI2C_SPEED_STANDARD:  Standard speed.
@@ -729,7 +730,7 @@ void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable)
  *
  * @retval      None
  */
-void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod)
+void SCI2C_ConfigClkPeriod(SCI2C_T* i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod)
 {
     if (speed == SCI2C_SPEED_STANDARD)
     {
@@ -749,9 +750,9 @@ void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPerio
 }
 
 /*!
- * @brief       Config SDA hold time length
+ * @brief       Configures SDA hold time length
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       txHold: Tx SDA hold time length
  *
@@ -759,22 +760,22 @@ void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPerio
  *
  * @retval      None
  */
-void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold)
+void SCI2C_ConfigSDAHoldTime(SCI2C_T* i2c, uint16_t txHold, uint8_t rxHold)
 {
     i2c->SDAHOLD_B.TXHOLD = txHold;
     i2c->SDAHOLD_B.RXHOLD = rxHold;
 }
 
 /*!
- * @brief       Config SDA delay time
+ * @brief       Configures SDA delay time
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       delay:  SDA delay time
  *
  * @retval      None
  */
-void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay)
+void SCI2C_ConfigSDADelayTime(SCI2C_T* i2c, uint8_t delay)
 {
     i2c->SDADLY = delay;
 }
@@ -782,13 +783,13 @@ void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay)
 /*!
  * @brief       Enable or disable generate gernal call ack
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       enable: SDA delay time
  *
  * @retval      None
  */
-void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable)
+void SCI2C_GernalCallAck(SCI2C_T* i2c, uint8_t enable)
 {
     i2c->GCA = enable;
 }
@@ -796,13 +797,13 @@ void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable)
 /*!
  * @brief       When received data no ack generated in slave mode.
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       enable: ENABLE or DISABLE
  *
  * @retval      None
  */
-void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable)
+void SCI2C_SlaveDataNackOnly(SCI2C_T* i2c, uint8_t enable)
 {
     i2c->SDNO = enable;
 }
@@ -810,11 +811,11 @@ void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable)
 /*!
  * @brief       Read Tx abort source
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @retval      Return Tx abort source
  */
-uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c)
+uint32_t SCI2C_ReadTxAbortSource(SCI2C_T* i2c)
 {
     return (uint32_t)i2c->TAS;
 }
@@ -822,7 +823,7 @@ uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c)
 /*!
  * @brief       Enable DMA
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       dma:    DMA requst source
  *                      @arg SCI2C_DMA_RX:  DMA RX channel
@@ -830,7 +831,7 @@ uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c)
  *
  * @retval      None
  */
-void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma)
+void SCI2C_EnableDMA(SCI2C_T* i2c, SCI2C_DMA_T dma)
 {
     i2c->DMACTRL |= dma;
 }
@@ -838,7 +839,7 @@ void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma)
 /*!
  * @brief       Disable DMA
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       dma:    DMA requst source
  *                      @arg SCI2C_DMA_RX:  DMA RX channel
@@ -846,43 +847,43 @@ void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma)
  *
  * @retval      None
  */
-void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma)
+void SCI2C_DisableDMA(SCI2C_T* i2c, SCI2C_DMA_T dma)
 {
     i2c->DMACTRL &= (uint32_t)~dma;
 }
 
 /*!
- * @brief       Config DMA Tx data level
+ * @brief       Configures DMA Tx data level
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       cnt:    DMA Tx data level
  *
  * @retval      None
  */
-void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt)
+void SCI2C_ConfigDMATxDataLevel(SCI2C_T* i2c, uint8_t cnt)
 {
     i2c->DTDL = cnt;
 }
 
 /*!
- * @brief       Config DMA Rx data level
+ * @brief       Configures DMA Rx data level
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       cnt:    DMA Rx data level
  *
  * @retval      None
  */
-void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt)
+void SCI2C_ConfigDMARxDataLevel(SCI2C_T* i2c, uint8_t cnt)
 {
     i2c->DRDL = cnt;
 }
 
 /*!
- * @brief       Config spike suppressio limit
+ * @brief       Configures spike suppressio limit
  *
- * @param       i2c:    Select the the I2C peripheral.It can be I2C3 or I2C4
+ * @param       i2c:    Select the the I2C peripheral. It can be I2C3 or I2C4
  *
  * @param       speed:  I2C speed mode
  *                      @arg SCI2C_SPEED_STANDARD:  Standard speed.
@@ -893,7 +894,7 @@ void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt)
  *
  * @retval      None
  */
-void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit)
+void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T* i2c, SCI2C_SPEED_T speed, uint8_t limit)
 {
     if (speed == SCI2C_SPEED_HIGH)
     {
@@ -905,6 +906,6 @@ void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_
     }
 }
 
-/**@} end of group SCI2C_Fuctions*/
-/**@} end of group SCI2C_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group SCI2C_Functions */
+/**@} end of group SCI2C_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c

@@ -1,11 +1,11 @@
 /*!
  * @file        apm32f10x_sdio.c
  *
- * @brief       This file provides all the SDIO firmware functions
+ * @brief     This file provides all the SDIO firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,24 +26,25 @@
 #include "apm32f10x_sdio.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup SDIO_Driver SDIO Driver
+  * @brief SDIO driver modules
   @{
 */
 
-/** @addtogroup SDIO_Fuctions Fuctions
+/** @defgroup SDIO_Functions Functions
   @{
 */
 
 /*!
- * @brief        Reset sdio peripheral registers to their default reset values
+ * @brief     Reset sdio peripheral registers to their default reset values
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_Reset(void)
 {
@@ -59,13 +60,13 @@ void SDIO_Reset(void)
 }
 
 /*!
- * @brief        Config the SDIO peripheral according to the specified parameters in the sdioConfig
+ * @brief     Configures the SDIO peripheral according to the specified parameters in the sdioConfig
  *
- * @param        sdioConfig: pointer to a SDIO_Config_T structure
+ * @param     sdioConfig: pointer to a SDIO_Config_T structure
  *
- * @retval       None
+ * @retval    None
  */
-void SDIO_Config(SDIO_Config_T *sdioConfig)
+void SDIO_Config(SDIO_Config_T* sdioConfig)
 {
     uint32_t tmp = 0;
 
@@ -79,13 +80,13 @@ void SDIO_Config(SDIO_Config_T *sdioConfig)
 }
 
 /*!
- * @brief        Fills each SDIO_Config_T member with its default value
+ * @brief     Fills each SDIO_Config_T member with its default value
  *
- * @param        sdioConfig: pointer to a SDIO_Config_T structure
+ * @param     sdioConfig: pointer to a SDIO_Config_T structure
  *
- * @retval       None
+ * @retval    None
  */
-void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig)
+void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig)
 {
     sdioConfig->clockDiv = 0x00;
     sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING;
@@ -96,33 +97,33 @@ void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig)
 }
 
 /*!
- * @brief        Enables the SDIO clock
+ * @brief     Enable the SDIO clock
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_EnableClock(void)
 {
-    *(__IO uint32_t *) CLKCTRL_CLKEN_BB = (uint32_t)SET;
+    *(__IO uint32_t*) CLKCTRL_CLKEN_BB = (uint32_t)SET;
 }
 
 /*!
- * @brief        Disables the SDIO clock
+ * @brief     Disable the SDIO clock
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_DisableClock(void)
 {
-    *(__IO uint32_t *) CLKCTRL_CLKEN_BB = (uint32_t)RESET;
+    *(__IO uint32_t*) CLKCTRL_CLKEN_BB = (uint32_t)RESET;
 }
 
 /*!
- * @brief        Sets the power status of the controller
+ * @brief     Set the power status of the controller
  *
- * @param        powerState: new state of the Power state
+ * @param     powerState: new state of the Power state
  *                     The parameter can be one of following values:
  *                     @arg SDIO_POWER_STATE_OFF
  *                     @arg SDIO_POWER_STATE_ON
@@ -135,13 +136,13 @@ void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState)
 }
 
 /*!
- * @brief        Reads the SDIO power state
+ * @brief     Read the SDIO power state
  *
- * @param        None
+ * @param     None
  *
- * @retval       The new state SDIO power
+ * @retval    The new state SDIO power
  *
- * @note         0x00:Power OFF, 0x02:Power UP, 0x03:Power ON
+ * @note      0x00:Power OFF, 0x02:Power UP, 0x03:Power ON
  */
 uint32_t SDIO_ReadPowerState(void)
 {
@@ -149,38 +150,38 @@ uint32_t SDIO_ReadPowerState(void)
 }
 
 /*!
- * @brief        Enables the SDIO DMA request
+ * @brief     Enable the SDIO DMA request
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_EnableDMA(void)
 {
-    *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)SET;
+    *(__IO uint32_t*) DCTRL_DMAEN_BB = (uint32_t)SET;
 }
 
 /*!
- * @brief        Disables the SDIO DMA request
+ * @brief     Disable the SDIO DMA request
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_DisableDMA(void)
 {
-    *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)RESET;
+    *(__IO uint32_t*) DCTRL_DMAEN_BB = (uint32_t)RESET;
 }
 
 /*!
- * @brief        Configs the SDIO Command and send the command
+ * @brief     Configures the SDIO Command and send the command
  *
- * @param        cmdConfig: pointer to a SDIO_CmdConfig_T structure
+ * @param     cmdConfig: pointer to a SDIO_CmdConfig_T structure
  *
- * @retval       None
+ * @retval    None
  *
  */
-void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig)
+void SDIO_TxCommand(SDIO_CmdConfig_T* cmdConfig)
 {
     uint32_t tmpreg = 0;
 
@@ -193,14 +194,14 @@ void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig)
 }
 
 /*!
- * @brief        Fills each SDIO_CMD_ConfigStruct_T member with its default value
+ * @brief     Fills each SDIO_CMD_ConfigStruct_T member with its default value
  *
- * @param        cmdConfig: pointer to a SDIO_CmdConfig_T structure
+ * @param     cmdConfig: pointer to a SDIO_CmdConfig_T structure
  *
- * @retval       None
+ * @retval    None
  *
  */
-void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdConfig)
+void SDIO_TxCommandStructInit(SDIO_CmdConfig_T* cmdConfig)
 {
     cmdConfig->argument = 0x00;
     cmdConfig->cmdIndex = 0x00;
@@ -210,11 +211,11 @@ void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdConfig)
 }
 
 /*!
- * @brief        Reads the SDIO command response
+ * @brief     Read the SDIO command response
  *
- * @param        None
+ * @param     None
  *
- * @retval       The command index of the last command response received
+ * @retval    The command index of the last command response received
  *
  */
 uint8_t SDIO_ReadCommandResponse(void)
@@ -223,16 +224,16 @@ uint8_t SDIO_ReadCommandResponse(void)
 }
 
 /*!
- * @brief        Reads the SDIO response
+ * @brief     Read the SDIO response
  *
- * @param        res:  Specifies the SDIO response register
+ * @param     res:  Specifies the SDIO response register
  *                     The parameter can be one of following values:
  *                     @arg SDIO_RES1: Response Register 1
  *                     @arg SDIO_RES2: Response Register 2
  *                     @arg SDIO_RES3: Response Register 3
  *                     @arg SDIO_RES4: Response Register 4
  *
- * @retval       The Corresponding response register value
+ * @retval    The Corresponding response register value
  */
 uint32_t SDIO_ReadResponse(SDIO_RES_T res)
 {
@@ -240,17 +241,17 @@ uint32_t SDIO_ReadResponse(SDIO_RES_T res)
 
     tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res;
 
-    return (*(__IO uint32_t *) tmp);
+    return (*(__IO uint32_t*) tmp);
 }
 
 /*!
- * @brief        Configs the SDIO Dataaccording to the specified parameters in the dataConfig
+ * @brief     Configures the SDIO Dataaccording to the specified parameters in the dataConfig
  *
- * @param        dataConfig: pointer to a SDIO_DataConfig_T structure
+ * @param     dataConfig: pointer to a SDIO_DataConfig_T structure
  *
- * @retval       None
+ * @retval    None
  */
-void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig)
+void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig)
 {
     uint32_t tmpreg = 0;
 
@@ -269,13 +270,13 @@ void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig)
 }
 
 /*!
- * @brief        Fills each SDIO_DataConfig_T member with its default value
+ * @brief     Fills each SDIO_DataConfig_T member with its default value
  *
- * @param        dataConfig: pointer to a SDIO_DataConfig_T structure
+ * @param     dataConfig: pointer to a SDIO_DataConfig_T structure
  *
- * @retval       None
+ * @retval    None
  */
-void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig)
+void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig)
 {
     dataConfig->dataTimeOut = 0xFFFFFFFF;
     dataConfig->dataLength = 0x00;
@@ -286,11 +287,11 @@ void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig)
 }
 
 /*!
- * @brief        Reads the SDIO Data counter
+ * @brief     Read the SDIO Data counter
  *
- * @param        None
+ * @param     None
  *
- * @retval       The SDIO Data counter value
+ * @retval    The SDIO Data counter value
  */
 uint32_t SDIO_ReadDataCounter(void)
 {
@@ -298,11 +299,11 @@ uint32_t SDIO_ReadDataCounter(void)
 }
 
 /*!
- * @brief       Write the SDIO Data
+ * @brief     Write the SDIO Data
  *
- * @param       Data：Write 32-bit data
+ * @param     Data: Write 32-bit data
  *
- * @retval      None
+ * @retval    None
  */
 void SDIO_WriteData(uint32_t data)
 {
@@ -310,11 +311,11 @@ void SDIO_WriteData(uint32_t data)
 }
 
 /*!
- * @brief       Reads the SDIO Data
+ * @brief     Read the SDIO Data
  *
- * @param       None
+ * @param     None
  *
- * @retval      The SDIO FIFO Data value
+ * @retval    The SDIO FIFO Data value
  */
 uint32_t SDIO_ReadData(void)
 {
@@ -322,11 +323,11 @@ uint32_t SDIO_ReadData(void)
 }
 
 /*!
- * @brief       Reads the SDIO FIFO count value
+ * @brief     Read the SDIO FIFO count value
  *
- * @param       None
+ * @param     None
  *
- * @retval      The SDIO FIFO count value
+ * @retval    The SDIO FIFO count value
  */
 uint32_t SDIO_ReadFIFOCount(void)
 {
@@ -334,217 +335,217 @@ uint32_t SDIO_ReadFIFOCount(void)
 }
 
 /*!
- * @brief        Enables SDIO start read wait
+ * @brief     Enable SDIO start read wait
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_EnableStartReadWait(void)
 {
-    *(__IO uint32_t *) DCTRL_RWSTR_BB = (uint32_t) SET;
+    *(__IO uint32_t*) DCTRL_RWSTR_BB = (uint32_t) SET;
 }
 
 /*!
- * @brief        Disables SDIO start read wait
+ * @brief     Disable SDIO start read wait
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_DisableStopReadWait(void)
 {
-    *(__IO uint32_t *) DCTRL_RWSTR_BB = (uint32_t) RESET;
+    *(__IO uint32_t*) DCTRL_RWSTR_BB = (uint32_t) RESET;
 }
 
 /*!
- * @brief        Enables SDIO stop read wait
+ * @brief     Enable SDIO stop read wait
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_EnableStopReadWait(void)
 {
-    *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) SET;
+    *(__IO uint32_t*) DCTRL_RWSTOP_BB = (uint32_t) SET;
 }
 
 /*!
- * @brief        Disables SDIO stop read wait
+ * @brief     Disable SDIO stop read wait
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_DisableStartReadWait(void)
 {
-    *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) RESET;
+    *(__IO uint32_t*) DCTRL_RWSTOP_BB = (uint32_t) RESET;
 }
 
 /*!
- * @brief        Sets the read wait interval
+ * @brief     Set the read wait interval
  *
- * @param        readWaitMode: SDIO read Wait Mode
+ * @param     readWaitMode: SDIO read Wait Mode
  *                     The parameter can be one of following values:
  *                     @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
  *                     @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
  *
- * @retval       None
+ * @retval    None
  *
  */
 void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode)
 {
-    *(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode;
+    *(__IO uint32_t*) DCTRL_RDWAIT_BB = readWaitMode;
 }
 /*!
- * @brief        Enables SDIO SD I/O Mode Operation
+ * @brief     Enable SDIO SD I/O Mode Operation
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_EnableSDIO(void)
 {
-    *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET;
+    *(__IO uint32_t*) DCTRL_SDIOF_BB = (uint32_t)SET;
 }
 
 /*!
- * @brief        Disables SDIO SD I/O Mode Operation
+ * @brief     Disable SDIO SD I/O Mode Operation
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_DisableSDIO(void)
 {
-    *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET;
+    *(__IO uint32_t*) DCTRL_SDIOF_BB = (uint32_t)RESET;
 }
 
 /*!
- * @brief        Ensables SDIO SD I/O Mode suspend command sending
+ * @brief     Enable SDIO SD I/O Mode suspend command sending
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_EnableTxSDIOSuspend(void)
 {
-    *(__IO uint32_t *) CMD_SDIOSC_BB = (uint32_t)SET;
+    *(__IO uint32_t*) CMD_SDIOSC_BB = (uint32_t)SET;
 }
 
 /*!
- * @brief        Disables SDIO SD I/O Mode suspend command sending
+ * @brief     Disable SDIO SD I/O Mode suspend command sending
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_DisableTxSDIOSuspend(void)
 {
-    *(__IO uint32_t *) CMD_SDIOSC_BB = (uint32_t)RESET;
+    *(__IO uint32_t*) CMD_SDIOSC_BB = (uint32_t)RESET;
 }
 
 /*!
- * @brief        Enables the command completion signal
+ * @brief     Enable the command completion signal
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_EnableCommandCompletion(void)
 {
-    *(__IO uint32_t *) CMD_CMDCPEN_BB = (uint32_t)SET;
+    *(__IO uint32_t*) CMD_CMDCPEN_BB = (uint32_t)SET;
 }
 
 /*!
- * @brief        Disables the command completion signal
+ * @brief     Disable the command completion signal
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_DisableCommandCompletion(void)
 {
-    *(__IO uint32_t *) CMD_CMDCPEN_BB = (uint32_t)RESET;
+    *(__IO uint32_t*) CMD_CMDCPEN_BB = (uint32_t)RESET;
 }
 
 /*!
- * @brief        Enables the CE-ATA interrupt
+ * @brief     Enable the CE-ATA interrupt
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_EnableCEATAInterrupt(void)
 {
-    *(__IO uint32_t *) CMD_INTEN_BB = (uint32_t)((~((uint32_t)SET)) & ((uint32_t)0x1));
+    *(__IO uint32_t*) CMD_INTEN_BB = (uint32_t)((~((uint32_t)SET)) & ((uint32_t)0x1));
 }
 
 /*!
- * @brief        Disables the CE-ATA interrupt
+ * @brief     Disable the CE-ATA interrupt
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_DisableCEATAInterrupt(void)
 {
-    *(__IO uint32_t *) CMD_INTEN_BB = (uint32_t)((~((uint32_t)RESET)) & ((uint32_t)0x1));
+    *(__IO uint32_t*) CMD_INTEN_BB = (uint32_t)((~((uint32_t)RESET)) & ((uint32_t)0x1));
 }
 
 /*!
- * @brief        Ensables Sends CE-ATA command
+ * @brief     Enable Sends CE-ATA command
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_EnableTxCEATA(void)
 {
-    *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)SET;
+    *(__IO uint32_t*) CMD_ATACMD_BB = (uint32_t)SET;
 }
 
 /*!
- * @brief        Disables Sends CE-ATA command
+ * @brief     Disable Sends CE-ATA command
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void SDIO_DisableTxCEATA(void)
 {
-    *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)RESET;
+    *(__IO uint32_t*) CMD_ATACMD_BB = (uint32_t)RESET;
 }
 
 /*!
- * @brief     Enables the specified SDIO interrupt
+ * @brief     Enable the specified SDIO interrupt
  *
  * @param     interrupt: Select the SDIO interrupt source
- *              The parameter can be any combination of following values:
- *              @arg SDIO_INT_COMRESP:  Command response received (CRC check failed) interrupt
- *              @arg SDIO_INT_DBDR:     Data block sent/received (CRC check failed) interrupt
- *              @arg SDIO_INT_CMDRESTO: Command response timeout interrupt
- *              @arg SDIO_INT_DATATO:   Data timeout interrupt
- *              @arg SDIO_INT_TXUDRER:  Transmit FIFO underrun error interrupt
- *              @arg SDIO_INT_RXOVRER:  Received FIFO overrun error interrupt
- *              @arg SDIO_INT_CMDRES:   Command response received (CRC check passed) interrupt
- *              @arg SDIO_INT_CMDSENT:  Command sent (no response required) interrupt
- *              @arg SDIO_INT_DATAEND:  Data end (data counter is zero) interrupt
- *              @arg SDIO_INT_SBE:      Start bit not detected on all data signals in wide bus mode interrupt
- *              @arg SDIO_INT_DBCP:     Data block sent/received (CRC check passed) interrupt
- *              @arg SDIO_INT_CMDACT:   Command transfer in progress interrupt
- *              @arg SDIO_INT_TXACT:    Data transmit in progress interrupt
- *              @arg SDIO_INT_RXACT:    Data receive in progress interrupt
- *              @arg SDIO_INT_TXFHF:    Transmit FIFO Half Empty interrupt
- *              @arg SDIO_INT_RXFHF:    Receive FIFO Half Full interrupt
- *              @arg SDIO_INT_TXFF:     Transmit FIFO full interrupt
- *              @arg SDIO_INT_RXFF:     Receive FIFO full interrupt
- *              @arg SDIO_INT_TXFE:     Transmit FIFO empty interrupt
- *              @arg SDIO_INT_RXFE:     Receive FIFO empty interrupt
- *              @arg SDIO_INT_TXDA:     Data available in transmit FIFO interrupt
- *              @arg SDIO_INT_RXDA:     Data available in receive FIFO interrupt
- *              @arg SDIO_INT_SDIOINT:  SD I/O interrupt received interrupt
- *              @arg SDIO_INT_ATAEND:   CE-ATA command completion signal received for CMD61 interrupt
+ *            The parameter can be any combination of following values:
+ *            @arg SDIO_INT_COMRESP:  Command response received (CRC check failed) interrupt
+ *            @arg SDIO_INT_DBDR:     Data block sent/received (CRC check failed) interrupt
+ *            @arg SDIO_INT_CMDRESTO: Command response timeout interrupt
+ *            @arg SDIO_INT_DATATO:   Data timeout interrupt
+ *            @arg SDIO_INT_TXUDRER:  Transmit FIFO underrun error interrupt
+ *            @arg SDIO_INT_RXOVRER:  Received FIFO overrun error interrupt
+ *            @arg SDIO_INT_CMDRES:   Command response received (CRC check passed) interrupt
+ *            @arg SDIO_INT_CMDSENT:  Command sent (no response required) interrupt
+ *            @arg SDIO_INT_DATAEND:  Data end (data counter is zero) interrupt
+ *            @arg SDIO_INT_SBE:      Start bit not detected on all data signals in wide bus mode interrupt
+ *            @arg SDIO_INT_DBCP:     Data block sent/received (CRC check passed) interrupt
+ *            @arg SDIO_INT_CMDACT:   Command transfer in progress interrupt
+ *            @arg SDIO_INT_TXACT:    Data transmit in progress interrupt
+ *            @arg SDIO_INT_RXACT:    Data receive in progress interrupt
+ *            @arg SDIO_INT_TXFHF:    Transmit FIFO Half Empty interrupt
+ *            @arg SDIO_INT_RXFHF:    Receive FIFO Half Full interrupt
+ *            @arg SDIO_INT_TXFF:     Transmit FIFO full interrupt
+ *            @arg SDIO_INT_RXFF:     Receive FIFO full interrupt
+ *            @arg SDIO_INT_TXFE:     Transmit FIFO empty interrupt
+ *            @arg SDIO_INT_RXFE:     Receive FIFO empty interrupt
+ *            @arg SDIO_INT_TXDA:     Data available in transmit FIFO interrupt
+ *            @arg SDIO_INT_RXDA:     Data available in receive FIFO interrupt
+ *            @arg SDIO_INT_SDIOINT:  SD I/O interrupt received interrupt
+ *            @arg SDIO_INT_ATAEND:   CE-ATA command completion signal received for CMD61 interrupt
  * @retval    None
  */
 void SDIO_EnableInterrupt(uint32_t interrupt)
@@ -553,34 +554,34 @@ void SDIO_EnableInterrupt(uint32_t interrupt)
 }
 
 /*!
- * @brief     Disables the specified SDIO interrupt
+ * @brief     Disable the specified SDIO interrupt
  *
  * @param     interrupt: Select the SDIO interrupt source
- *              The parameter can be any combination of following values:
- *              @arg SDIO_INT_COMRESP:  Command response received (CRC check failed) interrupt
- *              @arg SDIO_INT_DBDR:     Data block sent/received (CRC check failed) interrupt
- *              @arg SDIO_INT_CMDRESTO: Command response timeout interrupt
- *              @arg SDIO_INT_DATATO:   Data timeout interrupt
- *              @arg SDIO_INT_TXUDRER:  Transmit FIFO underrun error interrupt
- *              @arg SDIO_INT_RXOVRER:  Received FIFO overrun error interrupt
- *              @arg SDIO_INT_CMDRES:   Command response received (CRC check passed) interrupt
- *              @arg SDIO_INT_CMDSENT:  Command sent (no response required) interrupt
- *              @arg SDIO_INT_DATAEND:  Data end (data counter is zero) interrupt
- *              @arg SDIO_INT_SBE:      Start bit not detected on all data signals in wide bus mode interrupt
- *              @arg SDIO_INT_DBCP:     Data block sent/received (CRC check passed) interrupt
- *              @arg SDIO_INT_CMDACT:   Command transfer in progress interrupt
- *              @arg SDIO_INT_TXACT:    Data transmit in progress interrupt
- *              @arg SDIO_INT_RXACT:    Data receive in progress interrupt
- *              @arg SDIO_INT_TXFHF:    Transmit FIFO Half Empty interrupt
- *              @arg SDIO_INT_RXFHF:    Receive FIFO Half Full interrupt
- *              @arg SDIO_INT_TXFF:     Transmit FIFO full interrupt
- *              @arg SDIO_INT_RXFF:     Receive FIFO full interrupt
- *              @arg SDIO_INT_TXFE:     Transmit FIFO empty interrupt
- *              @arg SDIO_INT_RXFE:     Receive FIFO empty interrupt
- *              @arg SDIO_INT_TXDA:     Data available in transmit FIFO interrupt
- *              @arg SDIO_INT_RXDA:     Data available in receive FIFO interrupt
- *              @arg SDIO_INT_SDIOINT:  SD I/O interrupt received interrupt
- *              @arg SDIO_INT_ATAEND:   CE-ATA command completion signal received for CMD61 interrupt
+ *            The parameter can be any combination of following values:
+ *            @arg SDIO_INT_COMRESP:  Command response received (CRC check failed) interrupt
+ *            @arg SDIO_INT_DBDR:     Data block sent/received (CRC check failed) interrupt
+ *            @arg SDIO_INT_CMDRESTO: Command response timeout interrupt
+ *            @arg SDIO_INT_DATATO:   Data timeout interrupt
+ *            @arg SDIO_INT_TXUDRER:  Transmit FIFO underrun error interrupt
+ *            @arg SDIO_INT_RXOVRER:  Received FIFO overrun error interrupt
+ *            @arg SDIO_INT_CMDRES:   Command response received (CRC check passed) interrupt
+ *            @arg SDIO_INT_CMDSENT:  Command sent (no response required) interrupt
+ *            @arg SDIO_INT_DATAEND:  Data end (data counter is zero) interrupt
+ *            @arg SDIO_INT_SBE:      Start bit not detected on all data signals in wide bus mode interrupt
+ *            @arg SDIO_INT_DBCP:     Data block sent/received (CRC check passed) interrupt
+ *            @arg SDIO_INT_CMDACT:   Command transfer in progress interrupt
+ *            @arg SDIO_INT_TXACT:    Data transmit in progress interrupt
+ *            @arg SDIO_INT_RXACT:    Data receive in progress interrupt
+ *            @arg SDIO_INT_TXFHF:    Transmit FIFO Half Empty interrupt
+ *            @arg SDIO_INT_RXFHF:    Receive FIFO Half Full interrupt
+ *            @arg SDIO_INT_TXFF:     Transmit FIFO full interrupt
+ *            @arg SDIO_INT_RXFF:     Receive FIFO full interrupt
+ *            @arg SDIO_INT_TXFE:     Transmit FIFO empty interrupt
+ *            @arg SDIO_INT_RXFE:     Receive FIFO empty interrupt
+ *            @arg SDIO_INT_TXDA:     Data available in transmit FIFO interrupt
+ *            @arg SDIO_INT_RXDA:     Data available in receive FIFO interrupt
+ *            @arg SDIO_INT_SDIOINT:  SD I/O interrupt received interrupt
+ *            @arg SDIO_INT_ATAEND:   CE-ATA command completion signal received for CMD61 interrupt
  * @retval    None
  */
 void SDIO_DisableInterrupt(uint32_t interrupt)
@@ -589,34 +590,34 @@ void SDIO_DisableInterrupt(uint32_t interrupt)
 }
 
 /*!
- * @brief     Reads the specified SDIO flag
+ * @brief     Read the specified SDIO flag
  *
  * @param     flag: Select the flag to read
- *              The parameter can be one of following values:
- *              @arg SDIO_FLAG_COMRESP:  Command response received (CRC check failed) flag
- *              @arg SDIO_FLAG_DBDR:     Data block sent/received (CRC check failed) flag
- *              @arg SDIO_FLAG_CMDRESTO: Command response timeout flag
- *              @arg SDIO_FLAG_DATATO:   Data timeout flag
- *              @arg SDIO_FLAG_TXUDRER:  Transmit FIFO underrun error flag
- *              @arg SDIO_FLAG_RXOVRER:  Received FIFO overrun error flag
- *              @arg SDIO_FLAG_CMDRES:   Command response received (CRC check passed) flag
- *              @arg SDIO_FLAG_CMDSENT:  Command sent (no response required) flag
- *              @arg SDIO_FLAG_DATAEND:  Data end (data counter is zero) flag
- *              @arg SDIO_FLAG_SBE:      Start bit not detected on all data signals in wide bus mode flag
- *              @arg SDIO_FLAG_DBCP:     Data block sent/received (CRC check passed) flag
- *              @arg SDIO_FLAG_CMDACT:   Command transfer in progress flag
- *              @arg SDIO_FLAG_TXACT:    Data transmit in progress flag
- *              @arg SDIO_FLAG_RXACT:    Data receive in progress flag
- *              @arg SDIO_FLAG_TXFHF:    Transmit FIFO Half Empty flag
- *              @arg SDIO_FLAG_RXFHF:    Receive FIFO Half Full flag
- *              @arg SDIO_FLAG_TXFF:     Transmit FIFO full flag
- *              @arg SDIO_FLAG_RXFF:     Receive FIFO full flag
- *              @arg SDIO_FLAG_TXFE:     Transmit FIFO empty flag
- *              @arg SDIO_FLAG_RXFE:     Receive FIFO empty flag
- *              @arg SDIO_FLAG_TXDA:     Data available in transmit FIFO flag
- *              @arg SDIO_FLAG_RXDA:     Data available in receive FIFO flag
- *              @arg SDIO_FLAG_SDIOINT:  SD I/O interrupt received flag
- *              @arg SDIO_FLAG_ATAEND:   CE-ATA command completion signal received for CMD61 flag
+ *            The parameter can be one of following values:
+ *            @arg SDIO_FLAG_COMRESP:  Command response received (CRC check failed) flag
+ *            @arg SDIO_FLAG_DBDR:     Data block sent/received (CRC check failed) flag
+ *            @arg SDIO_FLAG_CMDRESTO: Command response timeout flag
+ *            @arg SDIO_FLAG_DATATO:   Data timeout flag
+ *            @arg SDIO_FLAG_TXUDRER:  Transmit FIFO underrun error flag
+ *            @arg SDIO_FLAG_RXOVRER:  Received FIFO overrun error flag
+ *            @arg SDIO_FLAG_CMDRES:   Command response received (CRC check passed) flag
+ *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required) flag
+ *            @arg SDIO_FLAG_DATAEND:  Data end (data counter is zero) flag
+ *            @arg SDIO_FLAG_SBE:      Start bit not detected on all data signals in wide bus mode flag
+ *            @arg SDIO_FLAG_DBCP:     Data block sent/received (CRC check passed) flag
+ *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress flag
+ *            @arg SDIO_FLAG_TXACT:    Data transmit in progress flag
+ *            @arg SDIO_FLAG_RXACT:    Data receive in progress flag
+ *            @arg SDIO_FLAG_TXFHF:    Transmit FIFO Half Empty flag
+ *            @arg SDIO_FLAG_RXFHF:    Receive FIFO Half Full flag
+ *            @arg SDIO_FLAG_TXFF:     Transmit FIFO full flag
+ *            @arg SDIO_FLAG_RXFF:     Receive FIFO full flag
+ *            @arg SDIO_FLAG_TXFE:     Transmit FIFO empty flag
+ *            @arg SDIO_FLAG_RXFE:     Receive FIFO empty flag
+ *            @arg SDIO_FLAG_TXDA:     Data available in transmit FIFO flag
+ *            @arg SDIO_FLAG_RXDA:     Data available in receive FIFO flag
+ *            @arg SDIO_FLAG_SDIOINT:  SD I/O interrupt received flag
+ *            @arg SDIO_FLAG_ATAEND:   CE-ATA command completion signal received for CMD61 flag
  *
  * @retval    SET or RESET
  */
@@ -626,23 +627,23 @@ uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag)
 }
 
 /*!
- * @brief     Clears the specified SDIO flag
+ * @brief     Clear the specified SDIO flag
  *
  * @param     flag: Select the flag to clear
- *              The parameter can be any combination of following values:
- *              @arg SDIO_FLAG_COMRESP:  Command response received (CRC check failed) flag
- *              @arg SDIO_FLAG_DBDR:     Data block sent/received (CRC check failed) flag
- *              @arg SDIO_FLAG_CMDRESTO: Command response timeout flag
- *              @arg SDIO_FLAG_DATATO:   Data timeout flag
- *              @arg SDIO_FLAG_TXUDRER:  Transmit FIFO underrun error flag
- *              @arg SDIO_FLAG_RXOVRER:  Received FIFO overrun error flag
- *              @arg SDIO_FLAG_CMDRES:   Command response received (CRC check passed) flag
- *              @arg SDIO_FLAG_CMDSENT:  Command sent (no response required) flag
- *              @arg SDIO_FLAG_DATAEND:  Data end (data counter is zero) flag
- *              @arg SDIO_FLAG_SBE:      Start bit not detected on all data signals in wide bus mode flag
- *              @arg SDIO_FLAG_DBCP:     Data block sent/received (CRC check passed) flag
- *              @arg SDIO_FLAG_SDIOINT:  SD I/O interrupt received flag
- *              @arg SDIO_FLAG_ATAEND:   CE-ATA command completion signal received for CMD61 flag
+ *            The parameter can be any combination of following values:
+ *            @arg SDIO_FLAG_COMRESP:  Command response received (CRC check failed) flag
+ *            @arg SDIO_FLAG_DBDR:     Data block sent/received (CRC check failed) flag
+ *            @arg SDIO_FLAG_CMDRESTO: Command response timeout flag
+ *            @arg SDIO_FLAG_DATATO:   Data timeout flag
+ *            @arg SDIO_FLAG_TXUDRER:  Transmit FIFO underrun error flag
+ *            @arg SDIO_FLAG_RXOVRER:  Received FIFO overrun error flag
+ *            @arg SDIO_FLAG_CMDRES:   Command response received (CRC check passed) flag
+ *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required) flag
+ *            @arg SDIO_FLAG_DATAEND:  Data end (data counter is zero) flag
+ *            @arg SDIO_FLAG_SBE:      Start bit not detected on all data signals in wide bus mode flag
+ *            @arg SDIO_FLAG_DBCP:     Data block sent/received (CRC check passed) flag
+ *            @arg SDIO_FLAG_SDIOINT:  SD I/O interrupt received flag
+ *            @arg SDIO_FLAG_ATAEND:   CE-ATA command completion signal received for CMD61 flag
  *
  * @retval    None
  */
@@ -652,34 +653,34 @@ void SDIO_ClearStatusFlag(uint32_t flag)
 }
 
 /*!
- * @brief     Reads the specified SDIO Interrupt flag
+ * @brief     Read the specified SDIO Interrupt flag
  *
  * @param     flag: Select the SDIO interrupt source
- *              The parameter can be one of following values:
- *              @arg SDIO_INT_COMRESP:  Command response received (CRC check failed) interrupt
- *              @arg SDIO_INT_DBDR:     Data block sent/received (CRC check failed) interrupt
- *              @arg SDIO_INT_CMDRESTO: Command response timeout interrupt
- *              @arg SDIO_INT_DATATO:   Data timeout interrupt
- *              @arg SDIO_INT_TXUDRER:  Transmit FIFO underrun error interrupt
- *              @arg SDIO_INT_RXOVRER:  Received FIFO overrun error interrupt
- *              @arg SDIO_INT_CMDRES:   Command response received (CRC check passed) interrupt
- *              @arg SDIO_INT_CMDSENT:  Command sent (no response required) interrupt
- *              @arg SDIO_INT_DATAEND:  Data end (data counter is zero) interrupt
- *              @arg SDIO_INT_SBE:      Start bit not detected on all data signals in wide bus mode interrupt
- *              @arg SDIO_INT_DBCP:     Data block sent/received (CRC check passed) interrupt
- *              @arg SDIO_INT_CMDACT:   Command transfer in progress interrupt
- *              @arg SDIO_INT_TXACT:    Data transmit in progress interrupt
- *              @arg SDIO_INT_RXACT:    Data receive in progress interrupt
- *              @arg SDIO_INT_TXFHF:    Transmit FIFO Half Empty interrupt
- *              @arg SDIO_INT_RXFHF:    Receive FIFO Half Full interrupt
- *              @arg SDIO_INT_TXFF:     Transmit FIFO full interrupt
- *              @arg SDIO_INT_RXFF:     Receive FIFO full interrupt
- *              @arg SDIO_INT_TXFE:     Transmit FIFO empty interrupt
- *              @arg SDIO_INT_RXFE:     Receive FIFO empty interrupt
- *              @arg SDIO_INT_TXDA:     Data available in transmit FIFO interrupt
- *              @arg SDIO_INT_RXDA:     Data available in receive FIFO interrupt
- *              @arg SDIO_INT_SDIOINT:  SD I/O interrupt received interrupt
- *              @arg SDIO_INT_ATAEND:   CE-ATA command completion signal received for CMD61 interrupt
+ *            The parameter can be one of following values:
+ *            @arg SDIO_INT_COMRESP:  Command response received (CRC check failed) interrupt
+ *            @arg SDIO_INT_DBDR:     Data block sent/received (CRC check failed) interrupt
+ *            @arg SDIO_INT_CMDRESTO: Command response timeout interrupt
+ *            @arg SDIO_INT_DATATO:   Data timeout interrupt
+ *            @arg SDIO_INT_TXUDRER:  Transmit FIFO underrun error interrupt
+ *            @arg SDIO_INT_RXOVRER:  Received FIFO overrun error interrupt
+ *            @arg SDIO_INT_CMDRES:   Command response received (CRC check passed) interrupt
+ *            @arg SDIO_INT_CMDSENT:  Command sent (no response required) interrupt
+ *            @arg SDIO_INT_DATAEND:  Data end (data counter is zero) interrupt
+ *            @arg SDIO_INT_SBE:      Start bit not detected on all data signals in wide bus mode interrupt
+ *            @arg SDIO_INT_DBCP:     Data block sent/received (CRC check passed) interrupt
+ *            @arg SDIO_INT_CMDACT:   Command transfer in progress interrupt
+ *            @arg SDIO_INT_TXACT:    Data transmit in progress interrupt
+ *            @arg SDIO_INT_RXACT:    Data receive in progress interrupt
+ *            @arg SDIO_INT_TXFHF:    Transmit FIFO Half Empty interrupt
+ *            @arg SDIO_INT_RXFHF:    Receive FIFO Half Full interrupt
+ *            @arg SDIO_INT_TXFF:     Transmit FIFO full interrupt
+ *            @arg SDIO_INT_RXFF:     Receive FIFO full interrupt
+ *            @arg SDIO_INT_TXFE:     Transmit FIFO empty interrupt
+ *            @arg SDIO_INT_RXFE:     Receive FIFO empty interrupt
+ *            @arg SDIO_INT_TXDA:     Data available in transmit FIFO interrupt
+ *            @arg SDIO_INT_RXDA:     Data available in receive FIFO interrupt
+ *            @arg SDIO_INT_SDIOINT:  SD I/O interrupt received interrupt
+ *            @arg SDIO_INT_ATAEND:   CE-ATA command completion signal received for CMD61 interrupt
  *
  * @retval    SET or RESET
  */
@@ -700,23 +701,23 @@ uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag)
 }
 
 /*!
- * @brief     Clears the specified SDIO Interrupt pending bits
+ * @brief     Clear the specified SDIO Interrupt pending bits
  *
  * @param     flag: Select the SDIO interrupt source
- *              The parameter can be any combination of following values:
- *              @arg SDIO_INT_COMRESP:  Command response received (CRC check failed) interrupt
- *              @arg SDIO_INT_DBDR:     Data block sent/received (CRC check failed) interrupt
- *              @arg SDIO_INT_CMDRESTO: Command response timeout interrupt
- *              @arg SDIO_INT_DATATO:   Data timeout interrupt
- *              @arg SDIO_INT_TXUDRER:  Transmit FIFO underrun error interrupt
- *              @arg SDIO_INT_RXOVRER:  Received FIFO overrun error interrupt
- *              @arg SDIO_INT_CMDRES:   Command response received (CRC check passed) interrupt
- *              @arg SDIO_INT_CMDSENT:  Command sent (no response required) interrupt
- *              @arg SDIO_INT_DATAEND:  Data end (data counter is zero) interrupt
- *              @arg SDIO_INT_SBE:      Start bit not detected on all data signals in wide bus mode interrupt
- *              @arg SDIO_INT_DBCP:     Data block sent/received (CRC check passed) interrupt
- *              @arg SDIO_INT_SDIOINT:  SD I/O interrupt received interrupt
- *              @arg SDIO_INT_ATAEND:   CE-ATA command completion signal received for CMD61 interrupt
+ *            The parameter can be any combination of following values:
+ *            @arg SDIO_INT_COMRESP:  Command response received (CRC check failed) interrupt
+ *            @arg SDIO_INT_DBDR:     Data block sent/received (CRC check failed) interrupt
+ *            @arg SDIO_INT_CMDRESTO: Command response timeout interrupt
+ *            @arg SDIO_INT_DATATO:   Data timeout interrupt
+ *            @arg SDIO_INT_TXUDRER:  Transmit FIFO underrun error interrupt
+ *            @arg SDIO_INT_RXOVRER:  Received FIFO overrun error interrupt
+ *            @arg SDIO_INT_CMDRES:   Command response received (CRC check passed) interrupt
+ *            @arg SDIO_INT_CMDSENT:  Command sent (no response required) interrupt
+ *            @arg SDIO_INT_DATAEND:  Data end (data counter is zero) interrupt
+ *            @arg SDIO_INT_SBE:      Start bit not detected on all data signals in wide bus mode interrupt
+ *            @arg SDIO_INT_DBCP:     Data block sent/received (CRC check passed) interrupt
+ *            @arg SDIO_INT_SDIOINT:  SD I/O interrupt received interrupt
+ *            @arg SDIO_INT_ATAEND:   CE-ATA command completion signal received for CMD61 interrupt
  *
  * @retval    None
  */
@@ -725,6 +726,6 @@ void SDIO_ClearIntFlag(uint32_t flag)
     SDIO->ICF = flag;
 }
 
-/**@} end of group SDIO_Fuctions*/
-/**@} end of group SDIO_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group SDIO_Functions */
+/**@} end of group SDIO_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_smc.c

@@ -0,0 +1,747 @@
+/*!
+ * @file        apm32f10x_smc.c
+ *
+ * @brief       This file provides all the SMC firmware functions
+ *
+ * @version     V1.0.4
+ *
+ * @date        2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2020-2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+#include "apm32f10x_smc.h"
+#include "apm32f10x_rcm.h"
+
+/** @addtogroup APM32F10x_StdPeriphDriver
+  @{
+*/
+
+/** @addtogroup SMC_Driver SMC Driver
+  * @brief SMC driver modules
+  @{
+*/
+
+/** @defgroup SMC_Functions Functions
+  @{
+*/
+
+/*!
+ * @brief     Reset the EMMMC NOR/SRAM Banks registers
+ *
+ * @param     bank: Select the EMMMC Bank.
+ *                  The parameter can be one of following values:
+ *                  @arg SMC_BANK1_NORSRAM_1: SMC Bank1 NOR/SRAM1
+ *                  @arg SMC_BANK1_NORSRAM_2: SMC Bank1 NOR/SRAM2
+ *                  @arg SMC_BANK1_NORSRAM_3: SMC Bank1 NOR/SRAM3
+ *                  @arg SMC_BANK1_NORSRAM_4: SMC Bank1 NOR/SRAM4
+ *
+ * @retval    None
+ */
+void SMC_ResetNORSRAM(SMC_BANK1_NORSRAM_T bank)
+{
+    /* SMC_BANK1_NORSRAM_1 */
+    if (bank == SMC_BANK1_NORSRAM_1)
+    {
+        SMC_Bank1->SNCTRL_T[bank] = 0x000030DB;
+    }
+    /* SMC_BANK1_NORSRAM_2, SMC_BANK1_NORSRAM_3 or SMC_BANK1_NORSRAM_4 */
+    else
+    {
+        SMC_Bank1->SNCTRL_T[bank] = 0x000030D2;
+    }
+    SMC_Bank1->SNCTRL_T[bank + 1] = 0x0FFFFFFF;
+    SMC_Bank1E->WRTTIM[bank] = 0x0FFFFFFF;
+}
+
+/*!
+ * @brief     Reset the EMMMC NAND Banks registers
+ *
+ * @param     bank: Select the EMMMC Bank.
+ *                  The parameter can be one of following values:
+ *                  @arg SMC_BANK2_NAND: FSMC Bank2 NAND
+ *                  @arg SMC_BANK3_NAND: FSMC Bank3 NAND
+ *
+ * @retval    None
+ */
+void SMC_ResetNAND(SMC_BANK_NAND_T bank)
+{
+    if (bank == SMC_BANK2_NAND)
+    {
+        /* Set the SMC_Bank2 registers to their reset values */
+        SMC_Bank2->CTRL2   = 0x00000018;
+        SMC_Bank2->STSINT2 = 0x00000040;
+        SMC_Bank2->CMSTIM2 = 0xFCFCFCFC;
+        SMC_Bank2->AMSTIM2 = 0xFCFCFCFC;
+    }
+    /* SMC BANK3 NAND */
+    else
+    {
+        /* Set the SMC_Bank3 registers to their reset values */
+        SMC_Bank3->CTRL3   = 0x00000018;
+        SMC_Bank3->STSINT3 = 0x00000040;
+        SMC_Bank3->CMSTIM3 = 0xFCFCFCFC;
+        SMC_Bank3->AMSTIM3 = 0xFCFCFCFC;
+    }
+}
+
+/*!
+ * @brief     Reset the EMMMC PCCARD Banks registers
+ *
+ * @param     None
+ *
+ * @retval    None
+ */
+void SMC_ResetPCCard(void)
+{
+    /* Set the SMC_Bank4 registers to their reset values */
+    SMC_Bank4->CTRL4   = 0x00000018;
+    SMC_Bank4->STSINT4 = 0x00000040;
+    SMC_Bank4->CMSTIM4 = 0xFCFCFCFC;
+    SMC_Bank4->AMSTIM4 = 0xFCFCFCFC;
+    SMC_Bank4->IOSTIM4 = 0xFCFCFCFC;
+}
+
+/*!
+ * @brief     Configures the SMC NOR/SRAM Banks according to the specified parameters in the smcNORSRAMConfig.
+ *
+ * @param     smcNORSRAMConfig: Point to a SMC_NORSRAMConfig_T structure
+ *
+ * @retval    None
+ */
+void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
+{
+    /* Bank1 NOR/SRAM control register configuration */
+    SMC_Bank1->SNCTRL_T[smcNORSRAMConfig->bank] =
+        (uint32_t)smcNORSRAMConfig->dataAddressMux |
+        smcNORSRAMConfig->memoryType |
+        smcNORSRAMConfig->memoryDataWidth |
+        smcNORSRAMConfig->burstAcceesMode |
+        smcNORSRAMConfig->asynchronousWait |
+        smcNORSRAMConfig->waitSignalPolarity |
+        smcNORSRAMConfig->wrapMode |
+        smcNORSRAMConfig->waitSignalActive |
+        smcNORSRAMConfig->writeOperation |
+        smcNORSRAMConfig->waiteSignal |
+        smcNORSRAMConfig->extendedMode |
+        smcNORSRAMConfig->writeBurst;
+
+    if (smcNORSRAMConfig->memoryType == SMC_MEMORY_TYPE_NOR)
+    {
+        SMC_Bank1->SNCTRL_T[smcNORSRAMConfig->bank] |= 0x00000040;
+    }
+
+    /* Bank1 NOR/SRAM timing register configuration */
+    SMC_Bank1->SNCTRL_T[smcNORSRAMConfig->bank + 1] =
+        (uint32_t)smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime |
+        (smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime << 4) |
+        (smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime << 8) |
+        (smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime << 16) |
+        (smcNORSRAMConfig->readWriteTimingStruct->clockDivision << 20) |
+        (smcNORSRAMConfig->readWriteTimingStruct->dataLatency << 24) |
+        smcNORSRAMConfig->readWriteTimingStruct->accessMode;
+
+    /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+    if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
+    {
+        SMC_Bank1E->WRTTIM[smcNORSRAMConfig->bank] =
+            (uint32_t)smcNORSRAMConfig->writeTimingStruct->addressSetupTime |
+            (smcNORSRAMConfig->writeTimingStruct->addressHodeTime << 4) |
+            (smcNORSRAMConfig->writeTimingStruct->dataSetupTime << 8) |
+            (smcNORSRAMConfig->writeTimingStruct->clockDivision << 20) |
+            (smcNORSRAMConfig->writeTimingStruct->dataLatency << 24) |
+            smcNORSRAMConfig->writeTimingStruct->accessMode;
+    }
+    else
+    {
+        SMC_Bank1E->WRTTIM[smcNORSRAMConfig->bank] = 0x0FFFFFFF;
+    }
+}
+
+/*!
+ * @brief     Configures the SMC NAND Banks according to the specified parameters in the smcNANDConfig.
+ *
+ * @param     smcNANDConfig : Point to a SMC_NANDConfig_T structure.
+ *
+ * @retval    None
+ */
+void SMC_ConfigNAND(SMC_NANDConfig_T* smcNANDConfig)
+{
+    uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
+
+    /* Set the tmppcr value according to SMC_NANDInitStruct parameters */
+    tmppcr = (uint32_t)smcNANDConfig->waitFeature | 0x00000008 |
+             smcNANDConfig->memoryDataWidth |
+             smcNANDConfig->ECC |
+             smcNANDConfig->ECCPageSize |
+             (smcNANDConfig->TCLRSetupTime << 9) |
+             (smcNANDConfig->TARSetupTime << 13);
+
+    /* Set tmppmem value according to SMC_CommonSpaceTimingStructure parameters */
+    tmppmem = (uint32_t)smcNANDConfig->commonSpaceTimingStruct->setupTime |
+              (smcNANDConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
+              (smcNANDConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
+              (smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
+
+    /* Set tmppatt value according to SMC_AttributeSpaceTimingStructure parameters */
+    tmppatt = (uint32_t)smcNANDConfig->attributeSpaceTimingStruct->setupTime |
+              (smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
+              (smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
+              (smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
+
+    if (smcNANDConfig->bank == SMC_BANK2_NAND)
+    {
+        /* SMC_BANK2_NAND registers configuration */
+        SMC_Bank2->CTRL2 = tmppcr;
+        SMC_Bank2->CMSTIM2 = tmppmem;
+        SMC_Bank2->AMSTIM2 = tmppatt;
+    }
+    else
+    {
+        /* SMC_BANK3_NAND registers configuration */
+        SMC_Bank3->CTRL3 = tmppcr;
+        SMC_Bank3->CMSTIM3 = tmppmem;
+        SMC_Bank3->AMSTIM3 = tmppatt;
+    }
+
+}
+
+/*!
+ * @brief     Configures the SMC PCCARD according to the specified parameters in the smcPCCardConfig.
+ *
+ * @param     smcPCCardConfig: Point to a SMC_PCCARDConfig_T structure.
+ *
+ * @retval    None
+ */
+void SMC_ConfigPCCard(SMC_PCCARDConfig_T* smcPCCardConfig)
+{
+    /* Set the PCR4 register value according to SMC_PCCARDInitStruct parameters */
+    SMC_Bank4->CTRL4 = (uint32_t)smcPCCardConfig->waitFeature | SMC_MEMORY_DATA_WIDTH_16BIT |
+                       (smcPCCardConfig->TCLRSetupTime << 9) |
+                       (smcPCCardConfig->TARSetupTime << 13);
+
+    /* Set PMEM4 register value according to SMC_CommonSpaceTimingStructure parameters */
+    SMC_Bank4->CMSTIM4 = (uint32_t)smcPCCardConfig->commonSpaceTimingStruct->setupTime |
+                         (smcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
+                         (smcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
+                         (smcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
+
+    /* Set PATT4 register value according to SMC_AttributeSpaceTimingStructure parameters */
+    SMC_Bank4->AMSTIM4 = (uint32_t)smcPCCardConfig->attributeSpaceTimingStruct->setupTime |
+                         (smcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
+                         (smcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
+                         (smcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
+
+    /* Set PIO4 register value according to SMC_IOSpaceTimingStructure parameters */
+    SMC_Bank4->IOSTIM4 = (uint32_t)smcPCCardConfig->IOSpaceTimingStruct->setupTime |
+                         (smcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) |
+                         (smcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) |
+                         (smcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24);
+}
+
+/*!
+ * @brief     Fills each smcNORSRAMConfig member with its default value.
+ *
+ * @param     smcNORSRAMConfig : Point to a SMC_NORSRAMConfig_T structure.
+ *
+ * @retval    None
+ */
+void SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
+{
+    /* Reset NOR/SRAM Init structure parameters values */
+    smcNORSRAMConfig->bank = SMC_BANK1_NORSRAM_1;
+    smcNORSRAMConfig->dataAddressMux = SMC_DATA_ADDRESS_MUX_ENABLE;
+    smcNORSRAMConfig->memoryType = SMC_MEMORY_TYPE_SRAM;
+    smcNORSRAMConfig->memoryDataWidth = SMC_MEMORY_DATA_WIDTH_8BIT;
+    smcNORSRAMConfig->burstAcceesMode = SMC_BURST_ACCESS_MODE_DISABLE;
+    smcNORSRAMConfig->asynchronousWait = SMC_ASYNCHRONOUS_WAIT_DISABLE;
+    smcNORSRAMConfig->waitSignalPolarity = SMC_WAIT_SIGNAL_POLARITY_LOW;
+    smcNORSRAMConfig->wrapMode = SMC_WRAP_MODE_DISABLE;
+    smcNORSRAMConfig->waitSignalActive = SMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT;
+    smcNORSRAMConfig->writeOperation = SMC_WRITE_OPERATION_ENABLE;
+    smcNORSRAMConfig->waiteSignal = SMC_WAITE_SIGNAL_ENABLE;
+    smcNORSRAMConfig->extendedMode = SMC_EXTENDEN_MODE_DISABLE;
+    smcNORSRAMConfig->writeBurst = SMC_WRITE_BURST_DISABLE;
+    smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime = 0xF;
+    smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime = 0xF;
+    smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime = 0xFF;
+    smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime = 0xF;
+    smcNORSRAMConfig->readWriteTimingStruct->clockDivision = 0xF;
+    smcNORSRAMConfig->readWriteTimingStruct->dataLatency = 0xF;
+    smcNORSRAMConfig->readWriteTimingStruct->accessMode = SMC_ACCESS_MODE_A;
+    smcNORSRAMConfig->writeTimingStruct->addressSetupTime = 0xF;
+    smcNORSRAMConfig->writeTimingStruct->addressHodeTime = 0xF;
+    smcNORSRAMConfig->writeTimingStruct->dataSetupTime = 0xFF;
+    smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime = 0xF;
+    smcNORSRAMConfig->writeTimingStruct->clockDivision = 0xF;
+    smcNORSRAMConfig->writeTimingStruct->dataLatency = 0xF;
+    smcNORSRAMConfig->writeTimingStruct->accessMode = SMC_ACCESS_MODE_A;
+}
+
+/*!
+ * @brief     Fills each smcNANDConfig member with its default value.
+ *
+ * @param     smcNANDConfig : Point to a SMC_NANDConfig_T structure.
+ *
+ * @retval    None
+ */
+void SMC_ConfigNANDStructInit(SMC_NANDConfig_T* smcNANDConfig)
+{
+    /* Reset NAND Init structure parameters values */
+    smcNANDConfig->bank = SMC_BANK2_NAND;
+    smcNANDConfig->waitFeature = SMC_WAIT_FEATURE_DISABLE;
+    smcNANDConfig->memoryDataWidth = SMC_MEMORY_DATA_WIDTH_8BIT;
+    smcNANDConfig->ECC = SMC_ECC_DISABLE;
+    smcNANDConfig->ECCPageSize = SMC_ECC_PAGE_SIZE_BYTE_256;
+    smcNANDConfig->TCLRSetupTime = 0x0;
+    smcNANDConfig->TARSetupTime = 0x0;
+    smcNANDConfig->commonSpaceTimingStruct->setupTime = 0xFC;
+    smcNANDConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC;
+    smcNANDConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC;
+    smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC;
+    smcNANDConfig->attributeSpaceTimingStruct->setupTime = 0xFC;
+    smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC;
+    smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC;
+    smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC;
+}
+
+/*!
+ * @brief     Fills each smcPCCardConfig member with its default value.
+ *
+ * @param     smcPCCardConfig : Point to a SMC_PCCARDConfig_T structure.
+ *
+ * @retval    None
+ */
+void SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T* smcPCCardConfig)
+{
+    /* Reset PCCARD Init structure parameters values */
+    smcPCCardConfig->waitFeature = SMC_WAIT_FEATURE_DISABLE;
+    smcPCCardConfig->TCLRSetupTime = 0x0;
+    smcPCCardConfig->TARSetupTime = 0x0;
+    smcPCCardConfig->commonSpaceTimingStruct->setupTime = 0xFC;
+    smcPCCardConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC;
+    smcPCCardConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC;
+    smcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC;
+    smcPCCardConfig->attributeSpaceTimingStruct->setupTime = 0xFC;
+    smcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC;
+    smcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC;
+    smcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC;
+    smcPCCardConfig->IOSpaceTimingStruct->setupTime = 0xFC;
+    smcPCCardConfig->IOSpaceTimingStruct->waitSetupTime = 0xFC;
+    smcPCCardConfig->IOSpaceTimingStruct->holdSetupTime = 0xFC;
+    smcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime = 0xFC;
+}
+
+/*!
+ * @brief     Enable the specified NOR/SRAM Memory Bank.
+ *
+ * @param     bank: Select the EMMMC Bank.
+ *                  The parameter can be one of following values:
+ *                  @arg SMC_BANK1_NORSRAM_1: SMC Bank1 NOR/SRAM1
+ *                  @arg SMC_BANK1_NORSRAM_2: SMC Bank1 NOR/SRAM2
+ *                  @arg SMC_BANK1_NORSRAM_3: SMC Bank1 NOR/SRAM3
+ *                  @arg SMC_BANK1_NORSRAM_4: SMC Bank1 NOR/SRAM4
+ *
+ * @retval    None
+ */
+void SMC_EnableNORSRAM(SMC_BANK1_NORSRAM_T bank)
+{
+    SMC_Bank1->SNCTRL_T[bank] |= 0x00000001;
+}
+
+/*!
+ * @brief     Disable the specified NOR/SRAM Memory Bank.
+ *
+ * @param     bank: Select the EMMMC Bank.
+ *                  The parameter can be one of following values:
+ *                  @arg SMC_BANK1_NORSRAM_1: SMC Bank1 NOR/SRAM1
+ *                  @arg SMC_BANK1_NORSRAM_2: SMC Bank1 NOR/SRAM2
+ *                  @arg SMC_BANK1_NORSRAM_3: SMC Bank1 NOR/SRAM3
+ *                  @arg SMC_BANK1_NORSRAM_4: SMC Bank1 NOR/SRAM4
+ *
+ * @retval    None
+ */
+void SMC_DisableNORSRAM(SMC_BANK1_NORSRAM_T bank)
+{
+    SMC_Bank1->SNCTRL_T[bank] &= 0x000FFFFE;
+}
+
+/*!
+ * @brief     Enable the specified NAND Memory Bank.
+ *
+ * @param     bank: Select the EMMMC Bank.
+ *                  The parameter can be one of following values:
+ *                  @arg SMC_BANK2_NAND: FSMC Bank2 NAND
+ *                  @arg SMC_BANK3_NAND: FSMC Bank3 NAND
+ *
+ * @retval    None
+ */
+void SMC_EnableNAND(SMC_BANK_NAND_T bank)
+{
+    if (bank == SMC_BANK2_NAND)
+    {
+        SMC_Bank2->CTRL2_B.MBKEN = BIT_SET;
+    }
+    else
+    {
+        SMC_Bank3->CTRL3_B.MBKEN = BIT_SET;
+    }
+}
+
+/*!
+ * @brief     Disable the specified NAND Memory Bank.
+ *
+ * @param     bank: Select the EMMMC Bank.
+ *                  The parameter can be one of following values:
+ *                  @arg SMC_BANK2_NAND: FSMC Bank2 NAND
+ *                  @arg SMC_BANK3_NAND: FSMC Bank3 NAND
+ *
+ * @retval    None
+ */
+void SMC_DisableNAND(SMC_BANK_NAND_T bank)
+{
+    if (bank == SMC_BANK2_NAND)
+    {
+        SMC_Bank2->CTRL2_B.MBKEN = BIT_RESET;
+    }
+    else
+    {
+        SMC_Bank3->CTRL3_B.MBKEN = BIT_RESET;
+    }
+}
+
+/*!
+ * @brief     Enable the specified PC Card Memory Bank.
+ *
+ * @param     None
+ *
+ * @retval    None
+ */
+void SMC_EnablePCCARD(void)
+{
+    SMC_Bank4->CTRL4_B.MBKEN = BIT_SET;
+}
+
+/*!
+ * @brief     Disable the specified PC Card Memory Bank.
+ *
+ * @param     None
+ *
+ * @retval    None
+ */
+void SMC_DisablePCCARD(void)
+{
+    SMC_Bank4->CTRL4_B.MBKEN = BIT_RESET;
+}
+
+/*!
+ * @brief     Enable the SMC NAND ECC feature.
+ *
+ * @param     bank: Select the EMMMC Bank.
+ *                  The parameter can be one of following values:
+ *                  @arg SMC_BANK2_NAND: FSMC Bank2 NAND
+ *                  @arg SMC_BANK3_NAND: FSMC Bank3 NAND
+ *
+ * @retval    None
+ */
+void SMC_EnableNANDECC(SMC_BANK_NAND_T bank)
+{
+    if (bank == SMC_BANK2_NAND)
+    {
+        SMC_Bank2->CTRL2 |= 0x00000040;
+    }
+    else
+    {
+        SMC_Bank3->CTRL3 |= 0x00000040;
+    }
+}
+
+/*!
+ * @brief     Disable the SMC Bank2 or Bank3 NAND ECC feature.
+ *
+ * @param     bank: Select the EMMMC Bank.
+ *                  The parameter can be one of following values:
+ *                  @arg SMC_BANK2_NAND: FSMC Bank2 NAND
+ *                  @arg SMC_BANK3_NAND: FSMC Bank3 NAND
+ *
+ * @retval    None
+ *
+ */
+void SMC_DisableNANDECC(SMC_BANK_NAND_T bank)
+{
+    if (bank == SMC_BANK2_NAND)
+    {
+        SMC_Bank2->CTRL2 &= 0x000FFFBF;
+    }
+    else
+    {
+        SMC_Bank3->CTRL3 &= 0x000FFFBF;
+    }
+}
+
+/*!
+ * @brief     Read the error correction code register value.
+ *
+ * @param     bank: Select the EMMMC Bank.
+ *                  The parameter can be one of following values:
+ *                  @arg SMC_BANK2_NAND: FSMC Bank2 NAND
+ *                  @arg SMC_BANK3_NAND: FSMC Bank3 NAND
+ *
+ * @retval    The value of Error Correction Code (ECC).
+ */
+uint32_t  SMC_ReadECC(SMC_BANK_NAND_T bank)
+{
+    uint32_t eccval = 0x00000000;
+
+    if (bank == SMC_BANK2_NAND)
+    {
+        eccval = SMC_Bank2->ECCRS2;
+    }
+    else
+    {
+        eccval = SMC_Bank3->ECCRS3;
+    }
+    return eccval;
+}
+
+/*!
+ * @brief    Enable the specified SMC interrupts.
+ *
+ * @param    bank: Select the EMMMC Bank.
+ *                 The parameter can be one of following values:
+ *                 @arg SMC_BANK2_NAND  : FSMC Bank2 NAND
+ *                 @arg SMC_BANK3_NAND  : FSMC Bank3 NAND
+ *                 @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD
+ *
+ * @param    interrupt: Select the SMC interrupt sources.
+ *                      This parameter can be any combination of the following values:
+ *                      @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
+ *                      @arg SMC_INT_LEVEL_HIGH  : High level detection interrupt.
+ *                      @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt.
+ *
+ * @retval   None
+ */
+void SMC_EnableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt)
+{
+    if (bank == SMC_BANK2_NAND)
+    {
+        SMC_Bank2->STSINT2 |= interrupt;
+    }
+    else if (bank == SMC_BANK3_NAND)
+    {
+        SMC_Bank3->STSINT3 |= interrupt;
+    }
+    else
+    {
+        SMC_Bank4->STSINT4 |= interrupt;
+    }
+}
+
+/*!
+ * @brief    Enable the specified SMC interrupts.
+ *
+ * @param    bank: Select the EMMMC Bank.
+ *                 The parameter can be one of following values:
+ *                 @arg SMC_BANK2_NAND  : FSMC Bank2 NAND
+ *                 @arg SMC_BANK3_NAND  : FSMC Bank3 NAND
+ *                 @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD
+ *
+ * @param    interrupt: Select the SMC interrupt sources.
+ *                      This parameter can be any combination of the following values:
+ *                      @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
+ *                      @arg SMC_INT_LEVEL_HIGH  : High level edge detection interrupt.
+ *                      @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt.
+ *
+ * @retval   None
+ */
+void SMC_DisableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt)
+{
+    if (bank == SMC_BANK2_NAND)
+    {
+        SMC_Bank2->STSINT2 &= ~interrupt;
+    }
+    else if (bank == SMC_BANK3_NAND)
+    {
+        SMC_Bank3->STSINT3 &= ~interrupt;
+    }
+    else
+    {
+        SMC_Bank4->STSINT4 &= ~interrupt;
+    }
+}
+
+/*!
+ * @brief    Read the status of specified SMC flag.
+ *
+ * @param    bank: Select the EMMMC Bank.
+ *                 The parameter can be one of following values:
+ *                 @arg SMC_BANK2_NAND  : FSMC Bank2 NAND
+ *                 @arg SMC_BANK3_NAND  : FSMC Bank3 NAND
+ *                 @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD
+ *
+ * @param    flag: Select the SMC interrupt sources.
+ *                 This parameter can be one of the following values:
+ *                 @arg SMC_FLAG_EDGE_RISING : Rising egde detection Flag.
+ *                 @arg SMC_FLAG_LEVEL_HIGH  : High level detection Flag.
+ *                 @arg SMC_FLAG_EDGE_FALLING: Falling egde detection Flag.
+ *                 @arg SMC_FLAG_FIFO_EMPTY  : FIFO empty Flag.
+ *
+ * @retval    SET or RESET
+ *
+ */
+uint8_t SMC_ReadStatusFlag(SMC_BANK_NAND_T bank, SMC_FLAG_T flag)
+{
+    uint32_t tmpsr = 0x00000000;
+
+    if (bank == SMC_BANK2_NAND)
+    {
+        tmpsr = SMC_Bank2->STSINT2;
+    }
+    else if (bank == SMC_BANK3_NAND)
+    {
+        tmpsr = SMC_Bank3->STSINT3;
+    }
+    else
+    {
+        tmpsr = SMC_Bank4->STSINT4;
+    }
+    /* Get the flag status */
+    if ((tmpsr & flag) != RESET)
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/*!
+ * @brief    Clear the SMC's pending flags.
+ *
+ * @param    bank: Select the EMMMC Bank.
+ *                 The parameter can be one of following values:
+ *                 @arg SMC_BANK2_NAND  : FSMC Bank2 NAND
+ *                 @arg SMC_BANK3_NAND  : FSMC Bank3 NAND
+ *                 @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD
+ *
+ * @param    flag: Select the SMC interrupt sources.
+ *                 This parameter can be any combination of the following values:
+ *                 @arg SMC_FLAG_EDGE_RISING : Rising egde detection Flag.
+ *                 @arg SMC_FLAG_LEVEL_HIGH  : High level detection Flag.
+ *                 @arg SMC_FLAG_EDGE_FALLING: Falling egde detection Flag.
+ *
+ * @retval    None
+ */
+void SMC_ClearStatusFlag(SMC_BANK_NAND_T bank, uint32_t flag)
+{
+    if (bank == SMC_BANK2_NAND)
+    {
+        SMC_Bank2->STSINT2 &= ~flag;
+    }
+    else if (bank == SMC_BANK3_NAND)
+    {
+        SMC_Bank3->STSINT3 &= ~flag;
+    }
+    else
+    {
+        SMC_Bank4->STSINT4 &= ~flag;
+    }
+}
+
+/*!
+ * @brief    Read the specified SMC interrupt has occurred or not.
+ *
+ * @param    bank: Select the EMMMC Bank.
+ *                 The parameter can be one of following values:
+ *                 @arg SMC_BANK2_NAND  : FSMC Bank2 NAND
+ *                 @arg SMC_BANK3_NAND  : FSMC Bank3 NAND
+ *                 @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD
+ *
+ * @param    interrupt: Select the SMC interrupt source.
+ *                      This parameter can be one of the following values:
+ *                      @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
+ *                      @arg SMC_INT_LEVEL_HIGH  : High level edge detection interrupt.
+ *                      @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt.
+ *
+ * @retval   The status of specified SMC interrupt source.
+ */
+uint8_t SMC_ReadIntFlag(SMC_BANK_NAND_T bank, SMC_INT_T flag)
+{
+    uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
+
+    if (bank == SMC_BANK2_NAND)
+    {
+        tmpsr = SMC_Bank2->STSINT2;
+    }
+    else if (bank == SMC_BANK3_NAND)
+    {
+        tmpsr = SMC_Bank3->STSINT3;
+    }
+    else
+    {
+        tmpsr = SMC_Bank4->STSINT4;
+    }
+
+    itstatus = tmpsr & flag;
+    itenable = tmpsr & (flag >> 3);
+
+    if ((itstatus != RESET) && (itenable != RESET))
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/*!
+ * @brief    Clear the SMC's interrupt Flag.
+ *
+ * @param    bank: Select the EMMMC Bank.
+ *                 The parameter can be one of following values:
+ *                 @arg SMC_BANK2_NAND  : FSMC Bank2 NAND
+ *                 @arg SMC_BANK3_NAND  : FSMC Bank3 NAND
+ *                 @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD
+ *
+ * @param    interrupt: Select the SMC interrupt sources.
+ *                      This parameter can be any combination of the following values:
+ *                      @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
+ *                      @arg SMC_INT_LEVEL_HIGH  : High level edge detection interrupt.
+ *                      @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt.
+ *
+ * @retval   None
+ */
+void SMC_ClearIntFlag(SMC_BANK_NAND_T bank, uint32_t flag)
+{
+    if (bank == SMC_BANK2_NAND)
+    {
+        SMC_Bank2->STSINT2 &= ~(flag >> 3);
+    }
+    else if (bank == SMC_BANK3_NAND)
+    {
+        SMC_Bank3->STSINT3 &= ~(flag >> 3);
+    }
+    else
+    {
+        SMC_Bank4->STSINT4 &= ~(flag >> 3);
+    }
+}
+
+/**@} end of group SMC_Functions */
+/**@} end of group SMC_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the SPI firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,15 +26,16 @@
 #include "apm32f10x_spi.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup SPI_Driver SPI Driver
+  * @brief SPI driver modules
   @{
 */
 
-/** @addtogroup SPI_Fuctions Fuctions
+/** @defgroup SPI_Functions Functions
   @{
 */
 
@@ -45,7 +46,7 @@
  *
  * @retval    None
  */
-void SPI_I2S_Reset(SPI_T *spi)
+void SPI_I2S_Reset(SPI_T* spi)
 {
     if (spi == SPI1)
     {
@@ -65,7 +66,7 @@ void SPI_I2S_Reset(SPI_T *spi)
 }
 
 /*!
- * @brief     Config the SPI peripheral according to the specified parameters in the spiConfig
+ * @brief     Configures the SPI peripheral according to the specified parameters in the spiConfig
  *
  * @param     spi: The SPIx can be 1,2,3
  *
@@ -73,7 +74,7 @@ void SPI_I2S_Reset(SPI_T *spi)
  *
  * @retval    None
  */
-void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig)
+void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig)
 {
     spi->CTRL1 &= 0x3040;
     spi->CTRL1 |= (uint16_t)((uint32_t)spiConfig->direction | spiConfig->mode |
@@ -84,7 +85,7 @@ void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig)
 }
 
 /*!
- * @brief     Config the I2S peripheral according to the specified parameters in the spiConfig
+ * @brief     Configures the I2S peripheral according to the specified parameters in the spiConfig
  *
  * @param     spi: The SPIx can be 2,3
  *
@@ -92,13 +93,13 @@ void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig)
  *
  * @retval    None
  */
-void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig)
+void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
 {
     uint16_t i2sDiv = 2, i2sOdd = 0, packetSize = 1;
     uint32_t tmp = 0;
     uint32_t sysClock = 0;
 
-    /** Clear MODESEL, I2SEN, I2SMOD, PFSSEL, I2SSSEL, CPOL, DATALEN and CHLEN bits */
+    /* Clear MODESEL, I2SEN, I2SMOD, PFSSEL, I2SSSEL, CPOL, DATALEN and CHLEN bits */
     spi->I2SCFG &= 0xF040;
     spi->I2SPSC = 0x0002;
 
@@ -149,7 +150,7 @@ void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig)
                   (uint32_t)i2sConfig->length | \
                   (uint32_t)i2sConfig->polarity;
 
-    /** select I2S mode */
+    /* select I2S mode */
     spi->I2SCFG_B.MODESEL = BIT_SET;
 }
 
@@ -160,7 +161,7 @@ void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig)
  *
  * @retval    None
  */
-void SPI_ConfigStructInit(SPI_Config_T *spiConfig)
+void SPI_ConfigStructInit(SPI_Config_T* spiConfig)
 {
     spiConfig->direction = SPI_DIRECTION_2LINES_FULLDUPLEX;
     spiConfig->mode = SPI_MODE_SLAVE;
@@ -180,7 +181,7 @@ void SPI_ConfigStructInit(SPI_Config_T *spiConfig)
  *
  * @retval    None
  */
-void I2S_ConfigStructInit(I2S_Config_T *i2sConfig)
+void I2S_ConfigStructInit(I2S_Config_T* i2sConfig)
 {
     i2sConfig->mode = I2S_MODE_SLAVE_TX;
     i2sConfig->standard = I2S_STANDARD_PHILLIPS;
@@ -190,13 +191,13 @@ void I2S_ConfigStructInit(I2S_Config_T *i2sConfig)
     i2sConfig->polarity = I2S_CLKPOL_LOW;
 }
 /*!
- * @brief     Enables the specified SPI peripheral
+ * @brief     Enable the specified SPI peripheral
  *
  * @param     spi: The SPIx can be 1,2,3
  *
  * @retval    None
  */
-void SPI_Enable(SPI_T *spi)
+void SPI_Enable(SPI_T* spi)
 {
     spi->CTRL1_B.SPIEN = BIT_SET;
 }
@@ -208,19 +209,19 @@ void SPI_Enable(SPI_T *spi)
  *
  * @retval    None
  */
-void SPI_Disable(SPI_T *spi)
+void SPI_Disable(SPI_T* spi)
 {
     spi->CTRL1_B.SPIEN = BIT_RESET;
 }
 
 /*!
- * @brief     Enables the specified I2S peripheral
+ * @brief     Enable the specified I2S peripheral
  *
  * @param     spi: The I2S can be SPI2,SPI3
  *
  * @retval    None
  */
-void I2S_Enable(SPI_T *spi)
+void I2S_Enable(SPI_T* spi)
 {
     spi->I2SCFG_B.I2SEN = BIT_SET;
 }
@@ -232,23 +233,23 @@ void I2S_Enable(SPI_T *spi)
  *
  * @retval    None
  */
-void I2S_Disable(SPI_T *spi)
+void I2S_Disable(SPI_T* spi)
 {
     spi->I2SCFG_B.I2SEN = BIT_RESET;
 }
 
 /*!
- * @brief     Enables the SPIx/I2Sx DMA interface.
+ * @brief     Enable the SPIx/I2Sx DMA interface.
  *
  * @param     spi: The SPIx can be 1,2,3, When the I2S can be 2,3
  *
  * @param     dmaReq: specifies the SPI/I2S DMA transfer request
- *                     The parameter can be one of following values:
- *                     @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request
- *                     @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request
+ *                    The parameter can be one of following values:
+ *                    @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request
+ *                    @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request
  * @retval    None
  */
-void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
+void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
 {
     if (dmaReq == SPI_I2S_DMA_REQ_TX)
     {
@@ -261,17 +262,17 @@ void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
 }
 
 /*!
- * @brief     Disables the SPIx/I2Sx DMA interface.
+ * @brief     Disable the SPIx/I2Sx DMA interface.
  *
  * @param     spi: The SPIx can be 1,2,3, When the I2S can be 2,3
  *
  * @param     dmaReq: specifies the SPI/I2S DMA transfer request
- *                     The parameter can be one of following values:
- *                     @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request
- *                     @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request
+ *                    The parameter can be one of following values:
+ *                    @arg SPI_I2S_DMA_REQ_TX: Tx buffer DMA transfer request
+ *                    @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request
  * @retval    None
  */
-void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
+void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
 {
     if (dmaReq == SPI_I2S_DMA_REQ_TX)
     {
@@ -284,7 +285,7 @@ void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
 }
 
 /*!
- * @brief     Transmits a Data through the SPIx/I2Sx peripheral.
+ * @brief     Transmit a Data through the SPIx/I2Sx peripheral.
  *
  * @param     spi: The SPIx can be 1,2,3, When the I2S can be 2,3
  *
@@ -292,13 +293,13 @@ void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
  *
  * @retval    None
  */
-void SPI_I2S_TxData(SPI_T *spi, uint16_t data)
+void SPI_I2S_TxData(SPI_T* spi, uint16_t data)
 {
     spi->DATA = data;
 }
 
 /*!
- * @brief     Returns the most recent received data by the SPIx/I2Sx peripheral.
+ * @brief     Return the most recent received data by the SPIx/I2Sx peripheral.
  *
  * @param     spi: The SPIx can be 1,2,3, When the I2S can be 2,3
  *
@@ -306,7 +307,7 @@ void SPI_I2S_TxData(SPI_T *spi, uint16_t data)
  *
  * @retval    None
  */
-uint16_t SPI_I2S_RxData(SPI_T *spi)
+uint16_t SPI_I2S_RxData(SPI_T* spi)
 {
     return spi->DATA;
 }
@@ -318,7 +319,7 @@ uint16_t SPI_I2S_RxData(SPI_T *spi)
  *
  * @retval    None
  */
-void SPI_SetSoftwareNSS(SPI_T *spi)
+void SPI_SetSoftwareNSS(SPI_T* spi)
 {
     spi->CTRL1_B.ISSEL = BIT_SET;
 }
@@ -330,19 +331,19 @@ void SPI_SetSoftwareNSS(SPI_T *spi)
  *
  * @retval    None
  */
-void SPI_ResetSoftwareNSS(SPI_T *spi)
+void SPI_ResetSoftwareNSS(SPI_T* spi)
 {
     spi->CTRL1_B.ISSEL = BIT_RESET;
 }
 
 /*!
- * @brief     Enables the specified SPI SS output
+ * @brief     Enable the specified SPI SS output
  *
  * @param     spi: The SPIx can be 1,2,3
  *
  * @retval    None
  */
-void SPI_EnableSSOutput(SPI_T *spi)
+void SPI_EnableSSOutput(SPI_T* spi)
 {
     spi->CTRL2_B.SSOEN = BIT_SET;
 }
@@ -354,7 +355,7 @@ void SPI_EnableSSOutput(SPI_T *spi)
  *
  * @retval    None
  */
-void SPI_DisableSSOutput(SPI_T *spi)
+void SPI_DisableSSOutput(SPI_T* spi)
 {
     spi->CTRL2_B.SSOEN = BIT_RESET;
 }
@@ -371,7 +372,7 @@ void SPI_DisableSSOutput(SPI_T *spi)
  *
  * @retval    None
  */
-void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length)
+void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length)
 {
     spi->CTRL1_B.DFLSEL = BIT_RESET;
     spi->CTRL1 |= length;
@@ -384,19 +385,19 @@ void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length)
  *
  * @retval    None
  */
-void SPI_TxCRC(SPI_T *spi)
+void SPI_TxCRC(SPI_T* spi)
 {
     spi->CTRL1_B.CRCNXT = BIT_SET;
 }
 
 /*!
- * @brief     Enables the specified SPI CRC value calculation of the transferred bytes
+ * @brief     Enable the specified SPI CRC value calculation of the transferred bytes
  *
  * @param     spi: The SPIx can be 1,2,3
  *
  * @retval    None
  */
-void SPI_EnableCRC(SPI_T *spi)
+void SPI_EnableCRC(SPI_T* spi)
 {
     spi->CTRL1_B.CRCEN = BIT_SET;
 }
@@ -407,43 +408,43 @@ void SPI_EnableCRC(SPI_T *spi)
  * @param     spi: The SPIx can be 1,2,3
  *
  */
-void SPI_DisableCRC(SPI_T *spi)
+void SPI_DisableCRC(SPI_T* spi)
 {
     spi->CTRL1_B.CRCEN = BIT_RESET;
 }
 
 /*!
- * @brief     Reads the specified SPI transmit CRC register value
+ * @brief     Read the specified SPI transmit CRC register value
  *
  * @param     spi: The SPIx can be 1,2,3
  *
  * @retval    The SPI transmit CRC register value
  */
-uint16_t SPI_ReadTxCRC(SPI_T *spi)
+uint16_t SPI_ReadTxCRC(SPI_T* spi)
 {
     return spi->TXCRC_B.TXCRC;
 }
 
 /*!
- * @brief     Reads the specified SPI receive CRC register value
+ * @brief     Read the specified SPI receive CRC register value
  *
  * @param     spi: The SPIx can be 1,2,3
  *
  * @retval    The SPI receive CRC register value
  */
-uint16_t SPI_ReadRxCRC(SPI_T *spi)
+uint16_t SPI_ReadRxCRC(SPI_T* spi)
 {
     return spi->RXCRC_B.RXCRC;
 }
 
 /*!
- * @brief     Reads the specified SPI CRC Polynomial register value
+ * @brief     Read the specified SPI CRC Polynomial register value
  *
  * @param     spi: The SPIx can be 1,2,3
  *
  * @retval    The SPI CRC Polynomial register value
  */
-uint16_t SPI_ReadCRCPolynomial(SPI_T *spi)
+uint16_t SPI_ReadCRCPolynomial(SPI_T* spi)
 {
     return spi->CRCPOLY_B.CRCPOLY;
 }
@@ -454,12 +455,12 @@ uint16_t SPI_ReadCRCPolynomial(SPI_T *spi)
  * @param     spi: The SPIx can be 1,2,3
  *
  * @param     direction: Select the SPI data transfer direction
- *                     The parameter can be one of following values:
- *                     @arg SPI_DIRECTION_RX: Selects Rx receive direction
- *                     @arg SPI_DIRECTION_TX: Selects Tx transmission direction
+ *                       The parameter can be one of following values:
+ *                       @arg SPI_DIRECTION_RX: Selects Rx receive direction
+ *                       @arg SPI_DIRECTION_TX: Selects Tx transmission direction
  * @retval    None
  */
-void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction)
+void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction)
 {
     if (direction == SPI_DIRECTION_TX)
     {
@@ -472,58 +473,58 @@ void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction)
 }
 
 /*!
- * @brief     Enables the specified SPI/I2S interrupts.
+ * @brief     Enable the specified SPI/I2S interrupts.
  *
  * @param     spi: The SPIx can be 1,2,3, When the I2S can be 2,3
  *
  * @param     interrupt: specifies the TMR interrupts sources
- *                     The parameter can be one of following values:
- *                     @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt
- *                     @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt
- *                     @arg SPI_I2S_INT_ERR: Error interrupt
+ *                       The parameter can be one of following values:
+ *                       @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt
+ *                       @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt
+ *                       @arg SPI_I2S_INT_ERR: Error interrupt
  * @retval       None
  */
-void SPI_I2S_EnableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt)
+void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
 {
     spi->CTRL2 |= (interrupt >> 8);
 }
 
 /*!
- * @brief     Disables the specified SPI/I2S interrupts.
+ * @brief     Disable the specified SPI/I2S interrupts.
  *
  * @param     spi: The SPIx can be 1,2,3, When the I2S can be 2,3
  *
  * @param     interrupt: specifies the TMR interrupts sources
- *                     The parameter can be one of following values:
- *                     @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt
- *                     @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt
- *                     @arg SPI_I2S_INT_ERR: Error interrupt
+ *                       The parameter can be one of following values:
+ *                       @arg SPI_I2S_INT_TXBE: Tx buffer empty interrupt
+ *                       @arg SPI_I2S_INT_RXBNE: Rx buffer not empty interrupt
+ *                       @arg SPI_I2S_INT_ERR: Error interrupt
  * @retval    None
  */
-void SPI_I2S_DisableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt)
+void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
 {
     spi->CTRL2 &= ~(interrupt >> 8);
 }
 
 /*!
- * @brief     Checks whether the specified SPI/I2S flag is set or not.
+ * @brief     Check whether the specified SPI/I2S flag is set or not.
  *
  * @param     spi: The SPIx can be 1,2,3, When the I2S can be 2,3
  *
  * @param     flag: specifies the SPI/I2S flag to check
- *                     The parameter can be one of following values:
- *                     @arg SPI_FLAG_RXBNE: Receive buffer not empty flag
- *                     @arg SPI_FLAG_TXBE: Transmit buffer empty flag
- *                     @arg I2S_FLAG_SCHDIR: Side Channel flag
- *                     @arg I2S_FLAG_UDR: Underrun Error flag
- *                     @arg SPI_FLAG_CRCE: CRC Error flag
- *                     @arg SPI_FLAG_ME: Mode Error flag
- *                     @arg SPI_FLAG_OVR: Overrun flag
- *                     @arg SPI_FLAG_BSY: Busy flag
+ *                  The parameter can be one of following values:
+ *                  @arg SPI_FLAG_RXBNE: Receive buffer not empty flag
+ *                  @arg SPI_FLAG_TXBE: Transmit buffer empty flag
+ *                  @arg I2S_FLAG_SCHDIR: Side Channel flag
+ *                  @arg I2S_FLAG_UDR: Underrun Error flag
+ *                  @arg SPI_FLAG_CRCE: CRC Error flag
+ *                  @arg SPI_FLAG_ME: Mode Error flag
+ *                  @arg SPI_FLAG_OVR: Overrun flag
+ *                  @arg SPI_FLAG_BSY: Busy flag
  *
  * @retval     SET or RESET
  */
-uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
+uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
 {
     if ((spi->STS & flag) != RESET)
     {
@@ -536,11 +537,11 @@ uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
 }
 
 /*!
- * @brief     Clears the SPIx CRC Error flag
+ * @brief     Clear the SPIx CRC Error flag
  *
  * @param     spi: The SPIx can be 1,2,3
  *
- * @param     flag: only clears SPI_FLAG_CRCE(CRC Error flag)
+ * @param     flag: only Clear SPI_FLAG_CRCE(CRC Error flag)
  *
  * @retval    None
  *
@@ -553,28 +554,28 @@ uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
  *              a read/write operation to SPI_STS register (SPI_I2S_ReadStatusFlag())
  *              followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
  */
-void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
+void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
 {
     spi->STS_B.CRCEFLG = BIT_RESET;
 }
 
 /*!
- * @brief     Checks whether the specified SPI/I2S interrupt has occurred or not.
+ * @brief     Check whether the specified SPI/I2S interrupt has occurred or not.
  *
  * @param     spi: The SPIx can be 1,2,3, When the I2S can be 2,3
  *
  * @param     flag: specifies the SPI/I2S interrupt flag to check.
- *                     The parameter can be one of following values:
- *                     @arg SPI_I2S_INT_RXBNE: Receive buffer not empty interrupt flag
- *                     @arg SPI_I2S_INT_TXBE: Transmit buffer empty interrupt flag
- *                     @arg SPI_I2S_INT_OVR: Overrun interrupt flag
- *                     @arg SPI_INT_CRCE: CRC Error interrupt flag
- *                     @arg SPI_INT_ME:  Mode Error interrupt flag
- *                     @arg I2S_INT_UDR: Underrun Error interrupt flag
+ *                  The parameter can be one of following values:
+ *                  @arg SPI_I2S_INT_RXBNE: Receive buffer not empty interrupt flag
+ *                  @arg SPI_I2S_INT_TXBE: Transmit buffer empty interrupt flag
+ *                  @arg SPI_I2S_INT_OVR: Overrun interrupt flag
+ *                  @arg SPI_INT_CRCE: CRC Error interrupt flag
+ *                  @arg SPI_INT_ME:  Mode Error interrupt flag
+ *                  @arg I2S_INT_UDR: Underrun Error interrupt flag
  *
  * @retval       SET or RESET
  */
-uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
+uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
 {
     uint32_t intEnable;
     uint32_t intStatus;
@@ -591,11 +592,11 @@ uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
 }
 
 /*!
- * @brief     Clears the SPIx CRC Error interrupt flag
+ * @brief     Clear the SPIx CRC Error interrupt flag
  *
  * @param     spi: The SPIx can be 1,2,3
  *
- * @param     flag: only clears SPI_INT_CRCE(CRC Error interrupt flag)
+ * @param     flag: only Clear SPI_INT_CRCE(CRC Error interrupt flag)
  *
  * @retval    None
  *
@@ -608,11 +609,11 @@ uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
  *              a read/write operation to SPI_STS register (SPI_I2S_ReadIntFlag())
  *              followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
  */
-void SPI_I2S_ClearIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
+void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
 {
     spi->STS_B.CRCEFLG = BIT_RESET;
 }
 
-/**@} end of group SPI_Fuctions*/
-/**@} end of group SPI_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group SPI_Functions */
+/**@} end of group SPI_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file provides all the USART firmware functions
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,15 +26,16 @@
 #include "apm32f10x_usart.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
 /** @addtogroup USART_Driver USART Driver
+  * @brief USART driver modules
   @{
 */
 
-/** @addtogroup USART_Fuctions Fuctions
+/** @defgroup USART_Functions Functions
   @{
 */
 
@@ -47,7 +48,7 @@
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Reset(USART_T *usart)
+void USART_Reset(USART_T* usart)
 {
     if (USART1 == usart)
     {
@@ -77,7 +78,7 @@ void USART_Reset(USART_T *usart)
 }
 
 /*!
- * @brief     Config the USART peripheral according to the specified parameters in the usartConfig
+ * @brief     Configures the USART peripheral according to the specified parameters in the usartConfig
  *
  * @param     uart:         Select the USART or the UART peripheral
  *
@@ -87,7 +88,7 @@ void USART_Reset(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Config(USART_T *uart, USART_Config_T *usartConfig)
+void USART_Config(USART_T* uart, USART_Config_T* usartConfig)
 {
     uint32_t temp, fCLK, intDiv, fractionalDiv;
 
@@ -132,7 +133,7 @@ void USART_Config(USART_T *uart, USART_Config_T *usartConfig)
  *
  * @retval    None
  */
-void USART_ConfigStructInit(USART_Config_T *usartConfig)
+void USART_ConfigStructInit(USART_Config_T* usartConfig)
 {
     usartConfig->baudRate = 9600;
     usartConfig->wordLength = USART_WORD_LEN_8B;
@@ -143,17 +144,17 @@ void USART_ConfigStructInit(USART_Config_T *usartConfig)
 }
 
 /*!
- * @brief     Configuration communication clock
+ * @brief     Configures communication clock
  *
- * @param     usart:  Select the USART or the UART peripheral
+ * @param     usart: Select the USART or the UART peripheral
  *
- * @param     clockConfig:   Pointer to a USART_clockConfig_T structure
+ * @param     clockConfig: Pointer to a USART_clockConfig_T structure
  *
  * @retval    None
  *
  * @note      The usart can be USART1, USART2, USART3
  */
-void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig)
+void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig)
 {
     usart->CTRL2_B.CLKEN   = clockConfig->clock;
     usart->CTRL2_B.CPHA    = clockConfig->phase;
@@ -164,12 +165,12 @@ void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig)
 /*!
  * @brief     Fills each clockConfig member with its default value
  *
- * @param     clockConfig:   Pointer to a USART_clockConfig_T structure
+ * @param     clockConfig: Pointer to a USART_clockConfig_T structure
  *
  * @retval    None
  *
  */
-void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig)
+void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig)
 {
     clockConfig->clock     = USART_CLKEN_DISABLE;
     clockConfig->phase     = USART_CLKPHA_1EDGE;
@@ -178,15 +179,15 @@ void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig)
 }
 
 /*!
- * @brief     Enables the specified USART peripheral
+ * @brief     Enable the specified USART peripheral
  *
- * @param     usart:   Select the USART or the UART peripheral
+ * @param     usart: Select the USART or the UART peripheral
  *
  * @retval    None
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Enable(USART_T *usart)
+void USART_Enable(USART_T* usart)
 {
     usart->CTRL1_B.UEN = BIT_SET;
 }
@@ -194,23 +195,23 @@ void USART_Enable(USART_T *usart)
 /*!
  * @brief     Disable the specified USART peripheral
  *
- * @param     usart:   Select the USART or the UART peripheral
+ * @param     usart: Select the USART or the UART peripheral
  *
  * @retval    None
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Disable(USART_T *usart)
+void USART_Disable(USART_T* usart)
 {
     usart->CTRL1_B.UEN = BIT_RESET;
 }
 
 /*!
- * @brief     Enables the USART DMA interface
+ * @brief     Enable the USART DMA interface
  *
- * @param     usart:   Select the USART or the UART peripheral
+ * @param     usart: Select the USART or the UART peripheral
  *
- * @param     dmaReq:  Specifies the DMA request
+ * @param     dmaReq: Specifies the DMA request
  *                     This parameter can be one of the following values:
  *                     @arg USART_DMA_TX:     USART DMA receive request
  *                     @arg USART_DMA_RX:     USART DMA transmit request
@@ -220,7 +221,7 @@ void USART_Disable(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq)
+void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq)
 {
     usart->CTRL3 |= dmaReq;
 }
@@ -228,9 +229,9 @@ void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq)
 /*!
  * @brief     Disable the USART DMA interface
  *
- * @param     usart:   Select the USART or the UART peripheral
+ * @param     usart: Select the USART or the UART peripheral
  *
- * @param     dmaReq:  Specifies the DMA request
+ * @param     dmaReq: Specifies the DMA request
  *                     This parameter can be one of the following values:
  *                     @arg USART_DMA_TX:     USART DMA receive request
  *                     @arg USART_DMA_RX:     USART DMA transmit request
@@ -240,7 +241,7 @@ void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq)
+void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq)
 {
     usart->CTRL3 &= (uint32_t)~dmaReq;
 }
@@ -248,7 +249,7 @@ void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq)
 /*!
  * @brief     Configures the address of the USART node
  *
- * @param     usart:   Select the USART or the UART peripheral
+ * @param     usart: Select the USART or the UART peripheral
  *
  * @param     address: Indicates the address of the USART node
  *
@@ -256,7 +257,7 @@ void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Address(USART_T *usart, uint8_t address)
+void USART_Address(USART_T* usart, uint8_t address)
 {
     usart->CTRL2_B.ADDR = address;
 }
@@ -264,18 +265,18 @@ void USART_Address(USART_T *usart, uint8_t address)
 /*!
  * @brief     Selects the USART WakeUp method.
  *
- * @param     usart:  Select the USART or the UART peripheral
+ * @param     usart: Select the USART or the UART peripheral
  *
  * @param     wakeup: Specifies the selected USART auto baud rate method
- *                    This parameter can be one of the following values:
- *                    @arg USART_WAKEUP_IDLE_LINE:    WakeUp by an idle line detection
- *                    @arg USART_WAKEUP_ADDRESS_MARK: WakeUp by an address mark
+ *                   This parameter can be one of the following values:
+ *                   @arg USART_WAKEUP_IDLE_LINE:    WakeUp by an idle line detection
+ *                   @arg USART_WAKEUP_ADDRESS_MARK: WakeUp by an address mark
  *
  * @retval    None
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup)
+void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup)
 {
     usart->CTRL1_B.WUPMCFG = wakeup;
 }
@@ -289,7 +290,7 @@ void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableMuteMode(USART_T *usart)
+void USART_EnableMuteMode(USART_T* usart)
 {
     usart->CTRL1_B.RXMUTEEN = BIT_SET;
 }
@@ -303,13 +304,13 @@ void USART_EnableMuteMode(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableMuteMode(USART_T *usart)
+void USART_DisableMuteMode(USART_T* usart)
 {
     usart->CTRL1_B.RXMUTEEN = BIT_RESET;
 }
 
 /*!
- * @brief     Sets the USART LIN Break detection length
+ * @brief     Set the USART LIN Break detection length
  *
  * @param     usart:   Select the USART or the UART peripheral
  *
@@ -322,13 +323,13 @@ void USART_DisableMuteMode(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length)
+void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length)
 {
     usart->CTRL2_B.LBDLCFG = length;
 }
 
 /*!
- * @brief     Enables the USART LIN MODE
+ * @brief     Enable the USART LIN MODE
  *
  * @param     usart:   Select the USART or the UART peripheral
  *
@@ -336,7 +337,7 @@ void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableLIN(USART_T *usart)
+void USART_EnableLIN(USART_T* usart)
 {
     usart->CTRL2_B.LINMEN = BIT_SET;
 }
@@ -350,13 +351,13 @@ void USART_EnableLIN(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableLIN(USART_T *usart)
+void USART_DisableLIN(USART_T* usart)
 {
     usart->CTRL2_B.LINMEN = BIT_RESET;
 }
 
 /*!
- * @brief     Transmitter Enable
+ * @brief     Transmitter enable
  *
  * @param     usart: Select the USART or the UART peripheral
  *
@@ -364,13 +365,13 @@ void USART_DisableLIN(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableTx(USART_T *usart)
+void USART_EnableTx(USART_T* usart)
 {
     usart->CTRL1_B.TXEN = BIT_SET;
 }
 
 /*!
- * @brief     Transmitter Disable
+ * @brief     Transmitter disable
  *
  * @param     usart: Select the USART or the UART peripheral
  *
@@ -378,7 +379,7 @@ void USART_EnableTx(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableTx(USART_T *usart)
+void USART_DisableTx(USART_T* usart)
 {
     usart->CTRL1_B.TXEN = BIT_RESET;
 }
@@ -392,7 +393,7 @@ void USART_DisableTx(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableRx(USART_T *usart)
+void USART_EnableRx(USART_T* usart)
 {
     usart->CTRL1_B.RXEN = BIT_SET;
 }
@@ -406,7 +407,7 @@ void USART_EnableRx(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableRx(USART_T *usart)
+void USART_DisableRx(USART_T* usart)
 {
     usart->CTRL1_B.RXEN = BIT_RESET;
 }
@@ -416,19 +417,19 @@ void USART_DisableRx(USART_T *usart)
  *
  * @param     usart: Select the USART or the UART peripheral
  *
- * @param     data:  the data to transmit
+ * @param     data: the data to transmit
  *
  * @retval    None
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_TxData(USART_T *usart, uint16_t data)
+void USART_TxData(USART_T* usart, uint16_t data)
 {
     usart->DATA_B.DATA = data;
 }
 
 /*!
- * @brief     Returns the most recent received data
+ * @brief     Return the most recent received data
  *
  * @param     usart: Select the USART or the UART peripheral
  *
@@ -436,7 +437,7 @@ void USART_TxData(USART_T *usart, uint16_t data)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-uint16_t USART_RxData(USART_T *usart)
+uint16_t USART_RxData(USART_T* usart)
 {
     return (uint16_t)(usart->DATA_B.DATA);
 }
@@ -450,15 +451,15 @@ uint16_t USART_RxData(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_TxBreak(USART_T *usart)
+void USART_TxBreak(USART_T* usart)
 {
     usart->CTRL1_B.TXBF = BIT_SET;
 }
 
 /*!
- * @brief     Sets the specified USART guard time
+ * @brief     Set the specified USART guard time
  *
- * @param     usart:     Select the USART or the UART peripheral
+ * @param     usart: Select the USART or the UART peripheral
  *
  * @param     guardTime: Specifies the guard time
  *
@@ -466,29 +467,29 @@ void USART_TxBreak(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3
  */
-void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime)
+void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime)
 {
     usart->GTPSC_B.GRDT = guardTime;
 }
 
 /*!
- * @brief     Sets the system clock divider number
+ * @brief     Set the system clock divider number
  *
  * @param     usart: Select the USART or the UART peripheral
  *
- * @param     div:   specifies the divider number
+ * @param     div: specifies the divider number
  *
  * @retval    None
  *
  * @note      The usart can be USART1, USART2, USART3
  */
-void USART_ConfigPrescaler(USART_T *usart, uint8_t div)
+void USART_ConfigPrescaler(USART_T* usart, uint8_t div)
 {
     usart->GTPSC_B.PSC = div;
 }
 
 /*!
- * @brief     Enables the USART Smart Card mode
+ * @brief     Enable the USART Smart Card mode
  *
  * @param     usart: Select the USART or the UART peripheral
  *
@@ -496,7 +497,7 @@ void USART_ConfigPrescaler(USART_T *usart, uint8_t div)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_EnableSmartCard(USART_T *usart)
+void USART_EnableSmartCard(USART_T* usart)
 {
     usart->CTRL3_B.SCEN = BIT_SET;
 }
@@ -510,13 +511,13 @@ void USART_EnableSmartCard(USART_T *usart)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_DisableSmartCard(USART_T *usart)
+void USART_DisableSmartCard(USART_T* usart)
 {
     usart->CTRL3_B.SCEN = BIT_RESET;
 }
 
 /*!
- * @brief     Enables NACK transmission
+ * @brief     Enable NACK transmission
  *
  * @param     usart: Select the USART or the UART peripheral
  *
@@ -524,7 +525,7 @@ void USART_DisableSmartCard(USART_T *usart)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_EnableSmartCardNACK(USART_T *usart)
+void USART_EnableSmartCardNACK(USART_T* usart)
 {
     usart->CTRL3_B.SCNACKEN = BIT_SET;
 }
@@ -538,13 +539,13 @@ void USART_EnableSmartCardNACK(USART_T *usart)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_DisableSmartCardNACK(USART_T *usart)
+void USART_DisableSmartCardNACK(USART_T* usart)
 {
     usart->CTRL3_B.SCNACKEN = BIT_RESET;
 }
 
 /*!
- * @brief     Enables USART Half Duplex communication
+ * @brief     Enable USART Half Duplex communication
  *
  * @param     usart: Select the USART or the UART peripheral
  *
@@ -552,7 +553,7 @@ void USART_DisableSmartCardNACK(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableHalfDuplex(USART_T *usart)
+void USART_EnableHalfDuplex(USART_T* usart)
 {
     usart->CTRL3_B.HDEN = BIT_SET;
 }
@@ -566,7 +567,7 @@ void USART_EnableHalfDuplex(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableHalfDuplex(USART_T *usart)
+void USART_DisableHalfDuplex(USART_T* usart)
 {
     usart->CTRL3_B.HDEN = BIT_RESET;
 }
@@ -574,23 +575,23 @@ void USART_DisableHalfDuplex(USART_T *usart)
 /*!
  * @brief     Configures the USART's IrDA interface
  *
- * @param     usart:    Select the USART or the UART peripheral
+ * @param     usart: Select the USART or the UART peripheral
  *
  * @param     IrDAMode: Specifies the IrDA mode
- *                      This parameter can be one of the following values:
- *                      @arg USART_IRDALP_NORMAL:   Normal
- *                      @arg USART_IRDALP_LOWPOWER: Low-Power
+ *                     This parameter can be one of the following values:
+ *                     @arg USART_IRDALP_NORMAL:   Normal
+ *                     @arg USART_IRDALP_LOWPOWER: Low-Power
  * @retval    None
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode)
+void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode)
 {
     usart->CTRL3_B.IRLPEN = IrDAMode;
 }
 
 /*!
- * @brief     Enables the USART's IrDA interface
+ * @brief     Enable the USART's IrDA interface
  *
  * @param     usart: Select the USART or the UART peripheral
  *
@@ -598,7 +599,7 @@ void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableIrDA(USART_T *usart)
+void USART_EnableIrDA(USART_T* usart)
 {
     usart->CTRL3_B.IREN = BIT_SET;
 }
@@ -612,7 +613,7 @@ void USART_EnableIrDA(USART_T *usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableIrDA(USART_T *usart)
+void USART_DisableIrDA(USART_T* usart)
 {
     usart->CTRL3_B.IREN = BIT_RESET;
 }
@@ -620,24 +621,24 @@ void USART_DisableIrDA(USART_T *usart)
 /*!
  * @brief     Enable the specified USART interrupts
  *
- * @param     usart:     Select the USART or the UART peripheral
+ * @param     usart: Select the USART or the UART peripheral
  *
- * @param     interrupt:  Specifies the USART interrupts sources
- *                        The parameter can be one of following values:
- *                        @arg USART_INT_PE:    Parity error interrupt
- *                        @arg USART_INT_TXBE:  Tansmit data buffer empty interrupt
- *                        @arg USART_INT_TXC:   Transmission complete interrupt
- *                        @arg USART_INT_RXBNE: Receive data buffer not empty interrupt
- *                        @arg USART_INT_IDLE:  Idle line detection interrupt
- *                        @arg USART_INT_LBD:   LIN break detection interrupt
- *                        @arg USART_INT_CTS:   CTS change interrupt
- *                        @arg USART_INT_ERR:   Error interrupt(Frame error, noise error, overrun error)
+ * @param     interrupt: Specifies the USART interrupts sources
+ *                     The parameter can be one of following values:
+ *                     @arg USART_INT_PE:    Parity error interrupt
+ *                     @arg USART_INT_TXBE:  Tansmit data buffer empty interrupt
+ *                     @arg USART_INT_TXC:   Transmission complete interrupt
+ *                     @arg USART_INT_RXBNE: Receive data buffer not empty interrupt
+ *                     @arg USART_INT_IDLE:  Idle line detection interrupt
+ *                     @arg USART_INT_LBD:   LIN break detection interrupt
+ *                     @arg USART_INT_CTS:   CTS change interrupt
+ *                     @arg USART_INT_ERR:   Error interrupt(Frame error, noise error, overrun error)
  *
  * @retval    None
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt)
+void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt)
 {
     uint32_t temp;
 
@@ -660,26 +661,26 @@ void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt)
 }
 
 /*!
- * @brief     Disables the specified USART interrupts
+ * @brief     Disable the specified USART interrupts
  *
- * @param     usart:      Select the USART or the UART peripheral
+ * @param     usart: Select the USART or the UART peripheral
  *
- * @param     interrupt:  Specifies the USART interrupts sources
- *                        The parameter can be one of following values:
- *                        @arg USART_INT_PE:    Parity error interrupt
- *                        @arg USART_INT_TXBE:  Tansmit data buffer empty interrupt
- *                        @arg USART_INT_TXC:   Transmission complete interrupt
- *                        @arg USART_INT_RXBNE: Receive data buffer not empty interrupt
- *                        @arg USART_INT_IDLE:  Idle line detection interrupt
- *                        @arg USART_INT_LBD:   LIN break detection interrupt
- *                        @arg USART_INT_CTS:   CTS change interrupt
- *                        @arg USART_INT_ERR:   Error interrupt(Frame error, noise error, overrun error)
+ * @param     interrupt: Specifies the USART interrupts sources
+ *                     The parameter can be one of following values:
+ *                     @arg USART_INT_PE:    Parity error interrupt
+ *                     @arg USART_INT_TXBE:  Tansmit data buffer empty interrupt
+ *                     @arg USART_INT_TXC:   Transmission complete interrupt
+ *                     @arg USART_INT_RXBNE: Receive data buffer not empty interrupt
+ *                     @arg USART_INT_IDLE:  Idle line detection interrupt
+ *                     @arg USART_INT_LBD:   LIN break detection interrupt
+ *                     @arg USART_INT_CTS:   CTS change interrupt
+ *                     @arg USART_INT_ERR:   Error interrupt(Frame error, noise error, overrun error)
  *
  * @retval    None
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt)
+void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt)
 {
     uint32_t temp;
 
@@ -706,45 +707,45 @@ void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt)
  *
  * @param     usart: Select the USART or the UART peripheral
  *
- * @param     flag:  Specifies the flag to check
- *                   The parameter can be one of following values:
- *                   @arg USART_FLAG_CTS:    CTS Change flag (not available for UART4 and UART5)
- *                   @arg USART_FLAG_LBD:    LIN Break detection flag
- *                   @arg USART_FLAG_TXBE:   Transmit data buffer empty flag
- *                   @arg USART_FLAG_TXC:    Transmission Complete flag
- *                   @arg USART_FLAG_RXBNE:  Receive data buffer not empty flag
- *                   @arg USART_FLAG_IDLE:   Idle Line detection flag
- *                   @arg USART_FLAG_OVRE:   OverRun Error flag
- *                   @arg USART_FLAG_NE:     Noise Error flag
- *                   @arg USART_FLAG_FE:     Framing Error flag
- *                   @arg USART_FLAG_PE:     Parity Error flag
+ * @param     flag: Specifies the flag to check
+ *                     The parameter can be one of following values:
+ *                     @arg USART_FLAG_CTS:    CTS Change flag (not available for UART4 and UART5)
+ *                     @arg USART_FLAG_LBD:    LIN Break detection flag
+ *                     @arg USART_FLAG_TXBE:   Transmit data buffer empty flag
+ *                     @arg USART_FLAG_TXC:    Transmission Complete flag
+ *                     @arg USART_FLAG_RXBNE:  Receive data buffer not empty flag
+ *                     @arg USART_FLAG_IDLE:   Idle Line detection flag
+ *                     @arg USART_FLAG_OVRE:   OverRun Error flag
+ *                     @arg USART_FLAG_NE:     Noise Error flag
+ *                     @arg USART_FLAG_FE:     Framing Error flag
+ *                     @arg USART_FLAG_PE:     Parity Error flag
  *
  * @retval    The new state of flag (SET or RESET)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag)
+uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag)
 {
     return (usart->STS & flag) ? SET : RESET;
 }
 
 /*!
- * @brief     Clears the USARTx's pending flags
+ * @brief     Clear the USARTx's pending flags
  *
- * @param     usart:   Select the USART or the UART peripheral
+ * @param     usart: Select the USART or the UART peripheral
  *
- * @param     flag:  Specifies the flag to clear
- *                   The parameter can be one of following values:
- *                   @arg USART_FLAG_CTS:    CTS Change flag (not available for UART4 and UART5)
- *                   @arg USART_FLAG_LBD:    LIN Break detection flag
- *                   @arg USART_FLAG_TXC:    Transmission Complete flag
- *                   @arg USART_FLAG_RXBNE:  Receive data buffer not empty flag
+ * @param     flag: Specifies the flag to clear
+ *                     The parameter can be one of following values:
+ *                     @arg USART_FLAG_CTS:    CTS Change flag (not available for UART4 and UART5)
+ *                     @arg USART_FLAG_LBD:    LIN Break detection flag
+ *                     @arg USART_FLAG_TXC:    Transmission Complete flag
+ *                     @arg USART_FLAG_RXBNE:  Receive data buffer not empty flag
  *
  * @retval    None
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag)
+void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag)
 {
     usart->STS &= (uint32_t)~flag;
 }
@@ -755,23 +756,23 @@ void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag)
  * @param     usart: Select the USART or the UART peripheral
  *
  * @param     flag:  Specifies the USART interrupt source to check
- *                        The parameter can be one of following values:
- *                        @arg USART_INT_TXBE:  Tansmit data buffer empty interrupt
- *                        @arg USART_INT_TXC:   Transmission complete interrupt
- *                        @arg USART_INT_RXBNE: Receive data buffer not empty interrupt
- *                        @arg USART_INT_IDLE:  Idle line detection interrupt
- *                        @arg USART_INT_LBD:   LIN break detection interrupt
- *                        @arg USART_INT_CTS:   CTS change interrupt
- *                        @arg USART_INT_OVRE:  OverRun Error interruptpt
- *                        @arg USART_INT_NE:    Noise Error interrupt
- *                        @arg USART_INT_FE:    Framing Error interrupt
- *                        @arg USART_INT_PE:    Parity error interrupt
+ *                     The parameter can be one of following values:
+ *                     @arg USART_INT_TXBE:  Tansmit data buffer empty interrupt
+ *                     @arg USART_INT_TXC:   Transmission complete interrupt
+ *                     @arg USART_INT_RXBNE: Receive data buffer not empty interrupt
+ *                     @arg USART_INT_IDLE:  Idle line detection interrupt
+ *                     @arg USART_INT_LBD:   LIN break detection interrupt
+ *                     @arg USART_INT_CTS:   CTS change interrupt
+ *                     @arg USART_INT_OVRE:  OverRun Error interruptpt
+ *                     @arg USART_INT_NE:    Noise Error interrupt
+ *                     @arg USART_INT_FE:    Framing Error interrupt
+ *                     @arg USART_INT_PE:    Parity error interrupt
  *
  * @retval    The new state of flag (SET or RESET)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag)
+uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag)
 {
     uint32_t itFlag, srFlag;
 
@@ -801,22 +802,22 @@ uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag)
 }
 
 /*!
- * @brief     Clears the USART interrupt pending bits
+ * @brief     Clear the USART interrupt pending bits
  *
  * @param     usart: Select the USART or the UART peripheral
  *
- * @param     flag:  Specifies the interrupt pending bit to clear
- *                   The parameter can be one of following values:
- *                   @arg USART_INT_RXBNE: Receive data buffer not empty interrupt
- *                   @arg USART_INT_TXC:   Transmission complete interrupt
- *                   @arg USART_INT_LBD:   LIN break detection interrupt
- *                   @arg USART_INT_CTS:   CTS change interrupt
+ * @param     flag: Specifies the interrupt pending bit to clear
+ *                     The parameter can be one of following values:
+ *                     @arg USART_INT_RXBNE: Receive data buffer not empty interrupt
+ *                     @arg USART_INT_TXC:   Transmission complete interrupt
+ *                     @arg USART_INT_LBD:   LIN break detection interrupt
+ *                     @arg USART_INT_CTS:   CTS change interrupt
  *
  * @retval    None
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag)
+void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag)
 {
     uint32_t srFlag;
 
@@ -826,6 +827,6 @@ void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag)
     usart->STS &= (uint32_t)~srFlag;
 }
 
-/**@} end of group USART_Fuctions*/
-/**@} end of group USART_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group USART_Functions */
+/**@} end of group USART_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c

@@ -3,9 +3,9 @@
  *
  * @brief       This file contains all the functions for the WWDT peripheral
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -26,24 +26,25 @@
 #include "apm32f10x_wwdt.h"
 #include "apm32f10x_rcm.h"
 
-/** @addtogroup Peripherals_Library Standard Peripheral Library
+/** @addtogroup APM32F10x_StdPeriphDriver
   @{
 */
 
-/** @addtogroup WWDT_Driver  WWDT Driver
+/** @defgroup WWDT_Driver WWDT Driver
+  * @brief WWDT driver modules
   @{
 */
 
-/** @addtogroup  WWDT_Fuctions Fuctions
+/** @defgroup  WWDT_Functions Functions
   @{
 */
 
 /*!
- * @brief        Reset the WWDT peripheral registers
+ * @brief     Reset the WWDT peripheral registers
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void WWDT_Reset(void)
 {
@@ -52,16 +53,16 @@ void WWDT_Reset(void)
 }
 
 /*!
- * @brief        Config the WWDT Timebase
+ * @brief     Configures the WWDT Timebase
  *
- * @param        timebase: WWDT Prescaler
- *               The parameter can be one of following values:
- *               @arg WWDT_TIME_BASE_1:  WWDT counter clock = (PCLK1/4096)/1
- *               @arg WWDT_TIME_BASE_2:  WWDT counter clock = (PCLK1/4096)/2
- *               @arg WWDT_TIME_BASE_4:  WWDT counter clock = (PCLK1/4096)/4
- *               @arg WWDT_TIME_BASE_8:  WWDT counter clock = (PCLK1/4096)/8
+ * @param     timebase: WWDT Prescaler
+ *            The parameter can be one of following values:
+ *            @arg WWDT_TIME_BASE_1:  WWDT counter clock = (PCLK1/4096)/1
+ *            @arg WWDT_TIME_BASE_2:  WWDT counter clock = (PCLK1/4096)/2
+ *            @arg WWDT_TIME_BASE_4:  WWDT counter clock = (PCLK1/4096)/4
+ *            @arg WWDT_TIME_BASE_8:  WWDT counter clock = (PCLK1/4096)/8
  *
- * @retval       None
+ * @retval    None
  */
 void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase)
 {
@@ -73,13 +74,13 @@ void WWDT_ConfigTimebase(WWDT_TIME_BASE_T timeBase)
 }
 
 /*!
- * @brief        Config the WWDT Window data
+ * @brief     Configures the WWDT Window data
  *
- * @param        windowdata: window data which compare with the downcounter
+ * @param     windowdata: window data which compare with the downcounter
  *
- * @retval       None
+ * @retval    None
  *
- * @note         The windowdata must be lower than 0x80
+ * @note      The windowdata must be lower than 0x80
  */
 void WWDT_ConfigWindowData(uint8_t windowData)
 {
@@ -91,7 +92,7 @@ void WWDT_ConfigWindowData(uint8_t windowData)
 }
 
 /*!
- * @brief       Config the WWDT counter value
+ * @brief       Configures the WWDT counter value
  *
  * @param       counter: Specifies the watchdog counter value
  *
@@ -105,11 +106,11 @@ void WWDT_ConfigCounter(uint8_t counter)
 }
 
 /*!
- * @brief        Enable the WWDT Early Wakeup interrupt
+ * @brief     Enable the WWDT Early Wakeup interrupt
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void WWDT_EnableEWI(void)
 {
@@ -117,13 +118,13 @@ void WWDT_EnableEWI(void)
 }
 
 /*!
- * @brief        Enable WWDT and set the counter value
+ * @brief     Enable WWDT and set the counter value
  *
- * @param        counter: the window watchdog counter value
+ * @param     counter: the window watchdog counter value
  *
- * @retval       None
+ * @retval    None
  *
- * @note         The counter between 0x40 and 0x7F
+ * @note      The counter between 0x40 and 0x7F
  */
 void WWDT_Enable(uint8_t counter)
 {
@@ -131,11 +132,11 @@ void WWDT_Enable(uint8_t counter)
 }
 
 /*!
- * @brief        Read the Early Wakeup interrupt flag
+ * @brief     Read the Early Wakeup interrupt flag
  *
- * @param        None
+ * @param     None
  *
- * @retval       the state of the Early Wakeup interrupt flagte
+ * @retval    the state of the Early Wakeup interrupt flagte
  */
 uint8_t WWDT_ReadFlag(void)
 {
@@ -143,17 +144,17 @@ uint8_t WWDT_ReadFlag(void)
 }
 
 /*!
- * @brief        Clear the Early Wakeup interrupt flag
+ * @brief     Clear the Early Wakeup interrupt flag
  *
- * @param        None
+ * @param     None
  *
- * @retval       None
+ * @retval    None
  */
 void WWDT_ClearFlag(void)
 {
     WWDT->STS_B.EWIFLG = RESET;
 }
 
-/**@} end of group WWDT_Fuctions*/
-/**@} end of group WWDT_Driver*/
-/**@} end of group Peripherals_Library*/
+/**@} end of group WWDT_Functions */
+/**@} end of group WWDT_Driver */
+/**@} end of group APM32F10x_StdPeriphDriver */

project_0/libraries/APM32F10x_Library/CMSIS/Include/cmsis_armcc.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_armcc.h
  * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
- * @version  V5.0.4
- * @date     10. January 2018
+ * @version  V5.1.0
+ * @date     08. May 2019
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,78 +27,107 @@
 
 
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-    #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
 #endif
 
 /* CMSIS compiler control architecture macros */
 #if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
      (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
-#define __ARM_ARCH_6M__           1
+  #define __ARM_ARCH_6M__           1
 #endif
 
 #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
-    #define __ARM_ARCH_7M__           1
+  #define __ARM_ARCH_7M__           1
 #endif
 
 #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
-    #define __ARM_ARCH_7EM__          1
+  #define __ARM_ARCH_7EM__          1
 #endif
 
-/* __ARM_ARCH_8M_BASE__  not applicable */
-/* __ARM_ARCH_8M_MAIN__  not applicable */
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
 
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __ARM_FEATURE_DSP         1
+#endif
 
 /* CMSIS compiler specific defines */
 #ifndef   __ASM
-    #define __ASM                                  __asm
+  #define __ASM                                  __asm
 #endif
 #ifndef   __INLINE
-    #define __INLINE                               __inline
+  #define __INLINE                               __inline
 #endif
 #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static __inline
+  #define __STATIC_INLINE                        static __inline
 #endif
 #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   static __forceinline
+  #define __STATIC_FORCEINLINE                   static __forceinline
 #endif
 #ifndef   __NO_RETURN
-    #define __NO_RETURN                            __declspec(noreturn)
+  #define __NO_RETURN                            __declspec(noreturn)
 #endif
 #ifndef   __USED
-    #define __USED                                 __attribute__((used))
+  #define __USED                                 __attribute__((used))
 #endif
 #ifndef   __WEAK
-    #define __WEAK                                 __attribute__((weak))
+  #define __WEAK                                 __attribute__((weak))
 #endif
 #ifndef   __PACKED
-    #define __PACKED                               __attribute__((packed))
+  #define __PACKED                               __attribute__((packed))
 #endif
 #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        __packed struct
+  #define __PACKED_STRUCT                        __packed struct
 #endif
 #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         __packed union
+  #define __PACKED_UNION                         __packed union
 #endif
 #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
 #endif
 #ifndef   __UNALIGNED_UINT16_WRITE
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT16_READ
-    #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
 #endif
 #ifndef   __UNALIGNED_UINT32_WRITE
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT32_READ
-    #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
 #endif
 #ifndef   __ALIGNED
-    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
 #endif
 #ifndef   __RESTRICT
-    #define __RESTRICT                             __restrict
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __memory_changed()
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section("RESET")))
 #endif
 
 /* ###########################  Core Function Access  ########################### */
@@ -129,8 +158,8 @@
  */
 __STATIC_INLINE uint32_t __get_CONTROL(void)
 {
-    register uint32_t __regControl         __ASM("control");
-    return (__regControl);
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
 }
 
 
@@ -141,8 +170,8 @@ __STATIC_INLINE uint32_t __get_CONTROL(void)
  */
 __STATIC_INLINE void __set_CONTROL(uint32_t control)
 {
-    register uint32_t __regControl         __ASM("control");
-    __regControl = control;
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
 }
 
 
@@ -153,8 +182,8 @@ __STATIC_INLINE void __set_CONTROL(uint32_t control)
  */
 __STATIC_INLINE uint32_t __get_IPSR(void)
 {
-    register uint32_t __regIPSR          __ASM("ipsr");
-    return (__regIPSR);
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
 }
 
 
@@ -165,8 +194,8 @@ __STATIC_INLINE uint32_t __get_IPSR(void)
  */
 __STATIC_INLINE uint32_t __get_APSR(void)
 {
-    register uint32_t __regAPSR          __ASM("apsr");
-    return (__regAPSR);
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
 }
 
 
@@ -177,8 +206,8 @@ __STATIC_INLINE uint32_t __get_APSR(void)
  */
 __STATIC_INLINE uint32_t __get_xPSR(void)
 {
-    register uint32_t __regXPSR          __ASM("xpsr");
-    return (__regXPSR);
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
 }
 
 
@@ -189,8 +218,8 @@ __STATIC_INLINE uint32_t __get_xPSR(void)
  */
 __STATIC_INLINE uint32_t __get_PSP(void)
 {
-    register uint32_t __regProcessStackPointer  __ASM("psp");
-    return (__regProcessStackPointer);
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
 }
 
 
@@ -201,8 +230,8 @@ __STATIC_INLINE uint32_t __get_PSP(void)
  */
 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
 {
-    register uint32_t __regProcessStackPointer  __ASM("psp");
-    __regProcessStackPointer = topOfProcStack;
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
 }
 
 
@@ -213,8 +242,8 @@ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
  */
 __STATIC_INLINE uint32_t __get_MSP(void)
 {
-    register uint32_t __regMainStackPointer     __ASM("msp");
-    return (__regMainStackPointer);
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
 }
 
 
@@ -225,8 +254,8 @@ __STATIC_INLINE uint32_t __get_MSP(void)
  */
 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
 {
-    register uint32_t __regMainStackPointer     __ASM("msp");
-    __regMainStackPointer = topOfMainStack;
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
 }
 
 
@@ -237,8 +266,8 @@ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
  */
 __STATIC_INLINE uint32_t __get_PRIMASK(void)
 {
-    register uint32_t __regPriMask         __ASM("primask");
-    return (__regPriMask);
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
 }
 
 
@@ -249,8 +278,8 @@ __STATIC_INLINE uint32_t __get_PRIMASK(void)
  */
 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 {
-    register uint32_t __regPriMask         __ASM("primask");
-    __regPriMask = (priMask);
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
 }
 
 
@@ -280,8 +309,8 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
  */
 __STATIC_INLINE uint32_t  __get_BASEPRI(void)
 {
-    register uint32_t __regBasePri         __ASM("basepri");
-    return (__regBasePri);
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
 }
 
 
@@ -292,8 +321,8 @@ __STATIC_INLINE uint32_t  __get_BASEPRI(void)
  */
 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
 {
-    register uint32_t __regBasePri         __ASM("basepri");
-    __regBasePri = (basePri & 0xFFU);
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
 }
 
 
@@ -305,8 +334,8 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
  */
 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
 {
-    register uint32_t __regBasePriMax      __ASM("basepri_max");
-    __regBasePriMax = (basePri & 0xFFU);
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
 }
 
 
@@ -317,8 +346,8 @@ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
  */
 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
 {
-    register uint32_t __regFaultMask       __ASM("faultmask");
-    return (__regFaultMask);
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
 }
 
 
@@ -329,8 +358,8 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
  */
 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
-    register uint32_t __regFaultMask       __ASM("faultmask");
-    __regFaultMask = (faultMask & (uint32_t)1U);
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
 }
 
 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
@@ -346,10 +375,10 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    register uint32_t __regfpscr         __ASM("fpscr");
-    return (__regfpscr);
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
 #else
-    return (0U);
+   return(0U);
 #endif
 }
 
@@ -363,10 +392,10 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    register uint32_t __regfpscr         __ASM("fpscr");
-    __regfpscr = (fpscr);
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
 #else
-    (void)fpscr;
+  (void)fpscr;
 #endif
 }
 
@@ -462,8 +491,8 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
 {
-    rev16 r0, r0
-    bx lr
+  rev16 r0, r0
+  bx lr
 }
 #endif
 
@@ -477,8 +506,8 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
 {
-    revsh r0, r0
-    bx lr
+  revsh r0, r0
+  bx lr
 }
 #endif
 
@@ -511,22 +540,22 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in
  */
 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
      (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-#define __RBIT                          __rbit
+  #define __RBIT                          __rbit
 #else
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 {
-    uint32_t result;
-    uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
-
-    result = value;                      /* r will be reversed bits of v; first get LSB of v */
-    for (value >>= 1U; value != 0U; value >>= 1U)
-    {
-        result <<= 1U;
-        result |= value & 1U;
-        s--;
-    }
-    result <<= s;                        /* shift when v's highest bits are zero */
-    return result;
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
 }
 #endif
 
@@ -550,9 +579,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return             value of type uint8_t at (*ptr)
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-    #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
 #else
-    #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
 #endif
 
 
@@ -563,9 +592,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return        value of type uint16_t at (*ptr)
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-    #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
 #else
-    #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
 #endif
 
 
@@ -576,9 +605,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return        value of type uint32_t at (*ptr)
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-    #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
 #else
-    #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
 #endif
 
 
@@ -591,9 +620,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return          1  Function failed
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-    #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
 #else
-    #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 #endif
 
 
@@ -606,9 +635,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return          1  Function failed
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-    #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
 #else
-    #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 #endif
 
 
@@ -621,9 +650,9 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
   \return          1  Function failed
  */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-    #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
 #else
-    #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 #endif
 
 
@@ -664,8 +693,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
 {
-    rrx r0, r0
-    bx lr
+  rrx r0, r0
+  bx lr
 }
 #endif
 
@@ -735,20 +764,20 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
  */
 __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
 {
-    if ((sat >= 1U) && (sat <= 32U))
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
     {
-        const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-        const int32_t min = -1 - max ;
-        if (val > max)
-        {
-            return max;
-        }
-        else if (val < min)
-        {
-            return min;
-        }
+      return min;
     }
-    return val;
+  }
+  return val;
 }
 
 /**
@@ -760,25 +789,25 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint3
  */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
 {
-    if (sat <= 31U)
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
     {
-        const uint32_t max = ((1U << sat) - 1U);
-        if (val > (int32_t)max)
-        {
-            return max;
-        }
-        else if (val < 0)
-        {
-            return 0U;
-        }
+      return 0U;
     }
-    return (uint32_t)val;
+  }
+  return (uint32_t)val;
 }
 
 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
            (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+/**@}*/ /* end of group CMSIS_Core_InstructionInterface */
 
 
 /* ###################  Compiler specific Intrinsics  ########################### */
@@ -859,7 +888,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint
                                                       ((int64_t)(ARG3) << 32U)     ) >> 32U))
 
 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-/*@} end of group CMSIS_SIMD_intrinsics */
+/**@} end of group CMSIS_SIMD_intrinsics */
 
 
 #endif /* __CMSIS_ARMCC_H */

project_0/libraries/APM32F10x_Library/CMSIS/Include/cmsis_compiler.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_compiler.h
  * @brief    CMSIS compiler generic header file
- * @version  V5.0.4
- * @date     10. January 2018
+ * @version  V5.1.0
+ * @date     09. October 2018
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -31,243 +31,251 @@
  * Arm Compiler 4/5
  */
 #if   defined ( __CC_ARM )
-#include "cmsis_armcc.h"
+  #include "cmsis_armcc.h"
 
 
 /*
- * Arm Compiler 6 (armclang)
+ * Arm Compiler 6.6 LTM (armclang)
  */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#include "cmsis_armclang.h"
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
 
 
 /*
  * GNU Compiler
  */
 #elif defined ( __GNUC__ )
-#include "cmsis_gcc.h"
+  #include "cmsis_gcc.h"
 
 
 /*
  * IAR Compiler
  */
 #elif defined ( __ICCARM__ )
-#include <cmsis_iccarm.h>
+  #include <cmsis_iccarm.h>
 
 
 /*
  * TI Arm Compiler
  */
 #elif defined ( __TI_ARM__ )
-#include <cmsis_ccs.h>
+  #include <cmsis_ccs.h>
 
-#ifndef   __ASM
+  #ifndef   __ASM
     #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
+  #endif
+  #ifndef   __INLINE
     #define __INLINE                               inline
-#endif
-#ifndef   __STATIC_INLINE
+  #endif
+  #ifndef   __STATIC_INLINE
     #define __STATIC_INLINE                        static inline
-#endif
-#ifndef   __STATIC_FORCEINLINE
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
     #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-#endif
-#ifndef   __NO_RETURN
+  #endif
+  #ifndef   __NO_RETURN
     #define __NO_RETURN                            __attribute__((noreturn))
-#endif
-#ifndef   __USED
+  #endif
+  #ifndef   __USED
     #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
+  #endif
+  #ifndef   __WEAK
     #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
+  #endif
+  #ifndef   __PACKED
     #define __PACKED                               __attribute__((packed))
-#endif
-#ifndef   __PACKED_STRUCT
+  #endif
+  #ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        struct __attribute__((packed))
-#endif
-#ifndef   __PACKED_UNION
+  #endif
+  #ifndef   __PACKED_UNION
     #define __PACKED_UNION                         union __attribute__((packed))
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-struct __attribute__((packed)) T_UINT32
-{
-    uint32_t v;
-};
-#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
     #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-#ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
-#endif
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
 
 
 /*
  * TASKING Compiler
  */
 #elif defined ( __TASKING__ )
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
 
-#ifndef   __ASM
+  #ifndef   __ASM
     #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
+  #endif
+  #ifndef   __INLINE
     #define __INLINE                               inline
-#endif
-#ifndef   __STATIC_INLINE
+  #endif
+  #ifndef   __STATIC_INLINE
     #define __STATIC_INLINE                        static inline
-#endif
-#ifndef   __STATIC_FORCEINLINE
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
     #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-#endif
-#ifndef   __NO_RETURN
+  #endif
+  #ifndef   __NO_RETURN
     #define __NO_RETURN                            __attribute__((noreturn))
-#endif
-#ifndef   __USED
+  #endif
+  #ifndef   __USED
     #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
+  #endif
+  #ifndef   __WEAK
     #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
+  #endif
+  #ifndef   __PACKED
     #define __PACKED                               __packed__
-#endif
-#ifndef   __PACKED_STRUCT
+  #endif
+  #ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        struct __packed__
-#endif
-#ifndef   __PACKED_UNION
+  #endif
+  #ifndef   __PACKED_UNION
     #define __PACKED_UNION                         union __packed__
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-struct __packed__ T_UINT32
-{
-    uint32_t v;
-};
-#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
     #define __ALIGNED(x)              __align(x)
-#endif
-#ifndef   __RESTRICT
+  #endif
+  #ifndef   __RESTRICT
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
-#endif
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
 
 
 /*
  * COSMIC Compiler
  */
 #elif defined ( __CSMC__ )
-#include <cmsis_csm.h>
+   #include <cmsis_csm.h>
 
-#ifndef   __ASM
+ #ifndef   __ASM
     #define __ASM                                  _asm
-#endif
-#ifndef   __INLINE
+  #endif
+  #ifndef   __INLINE
     #define __INLINE                               inline
-#endif
-#ifndef   __STATIC_INLINE
+  #endif
+  #ifndef   __STATIC_INLINE
     #define __STATIC_INLINE                        static inline
-#endif
-#ifndef   __STATIC_FORCEINLINE
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
     #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-#endif
-#ifndef   __NO_RETURN
+  #endif
+  #ifndef   __NO_RETURN
     // NO RETURN is automatically detected hence no warning here
     #define __NO_RETURN
-#endif
-#ifndef   __USED
+  #endif
+  #ifndef   __USED
     #warning No compiler specific solution for __USED. __USED is ignored.
     #define __USED
-#endif
-#ifndef   __WEAK
+  #endif
+  #ifndef   __WEAK
     #define __WEAK                                 __weak
-#endif
-#ifndef   __PACKED
+  #endif
+  #ifndef   __PACKED
     #define __PACKED                               @packed
-#endif
-#ifndef   __PACKED_STRUCT
+  #endif
+  #ifndef   __PACKED_STRUCT
     #define __PACKED_STRUCT                        @packed struct
-#endif
-#ifndef   __PACKED_UNION
+  #endif
+  #ifndef   __PACKED_UNION
     #define __PACKED_UNION                         @packed union
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-@packed struct T_UINT32
-{
-    uint32_t v;
-};
-#define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-#define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-#define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-#define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-#define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
     #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
     #define __ALIGNED(x)
-#endif
-#ifndef   __RESTRICT
+  #endif
+  #ifndef   __RESTRICT
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
-#endif
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
 
 
 #else
-#error Unknown compiler.
+  #error Unknown compiler.
 #endif
 
 

project_0/libraries/APM32F10x_Library/CMSIS/Include/cmsis_version.h

@@ -23,9 +23,9 @@
  */
 
 #if   defined ( __ICCARM__ )
-    #pragma system_include         /* treat file as system include file for MISRA check */
+  #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
-    #pragma clang system_header   /* treat file as system include file */
+  #pragma clang system_header   /* treat file as system include file */
 #endif
 
 #ifndef __CMSIS_VERSION_H

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Include/system_apm32f10x.h

@@ -3,9 +3,9 @@
  *
  * @brief       CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,21 +23,40 @@
  *  and limitations under the License.
  */
 
+/* Define to prevent recursive inclusion */
 #ifndef __SYSTEM_APM32F10X_H
 #define __SYSTEM_APM32F10X_H
 
+/* Includes */
+#include "apm32f10x.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/** @addtogroup CMSIS
+  @{
+*/
+
+/** @addtogroup APM32F10x_System
+  @{
+*/
+
+/** @defgroup System_Variables
+  @{
+*/
+
 extern uint32_t SystemCoreClock;
 
 extern void SystemInit(void);
 extern void SystemCoreClockUpdate(void);
 
+/**@} end of group System_Functions */
+/**@} end of group APM32F10x_System */
+/**@} end of group CMSIS */
+
 #ifdef __cplusplus
 }
 #endif
 
 #endif /*__SYSTEM_APM32F10X_H */
-

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_cl.s

@@ -0,0 +1,365 @@
+;/*!
+; * @file        startup_apm32f10x_cl.s
+; *
+; * @brief       CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_cl
+; *
+; * @version     V1.0.0
+; *
+; * @date        2022-07-25
+; *
+; * @attention
+; *
+; *  Copyright (C) 2020-2022 Geehy Semiconductor
+; *
+; *  You may not use this file except in compliance with the
+; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+; *
+; *  The program is only for reference, which is distributed in the hope
+; *  that it will be useful and instructional for customers to develop
+; *  their software. Unless required by applicable law or agreed to in
+; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+; *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+; *  and limitations under the License.
+; */
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                 ; Top of Stack
+                DCD     Reset_Handler                ; Reset Handler
+                DCD     NMI_Handler                  ; NMI Handler
+                DCD     HardFault_Handler            ; Hard Fault Handler
+                DCD     MemManage_Handler            ; MPU Fault Handler
+                DCD     BusFault_Handler             ; Bus Fault Handler
+                DCD     UsageFault_Handler           ; Usage Fault Handler
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     SVC_Handler                  ; SVCall Handler
+                DCD     DebugMon_Handler             ; Debug Monitor Handler
+                DCD     0                            ; Reserved
+                DCD     PendSV_Handler               ; PendSV Handler
+                DCD     SysTick_Handler              ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDT_IRQHandler              ; Window Watchdog
+                DCD     PVD_IRQHandler               ; PVD through EINT Line detect
+                DCD     TAMPER_IRQHandler            ; Tamper
+                DCD     RTC_IRQHandler               ; RTC
+                DCD     FLASH_IRQHandler             ; Flash
+                DCD     RCM_IRQHandler               ; RCM
+                DCD     EINT0_IRQHandler             ; EINT Line 0
+                DCD     EINT1_IRQHandler             ; EINT Line 1
+                DCD     EINT2_IRQHandler             ; EINT Line 2
+                DCD     EINT3_IRQHandler             ; EINT Line 3
+                DCD     EINT4_IRQHandler             ; EINT Line 4
+                DCD     DMA1_Channel1_IRQHandler     ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler     ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler     ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler     ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler     ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler     ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler     ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler            ; ADC1 & ADC2
+                DCD     CAN1_TX_IRQHandler           ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler          ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler          ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler          ; CAN1 SCE
+                DCD     EINT9_5_IRQHandler           ; EINT Line 9..5
+                DCD     TMR1_BRK_IRQHandler          ; TMR1 Break
+                DCD     TMR1_UP_IRQHandler           ; TMR1 Update
+                DCD     TMR1_TRG_COM_IRQHandler      ; TMR1 Trigger and Commutation
+                DCD     TMR1_CC_IRQHandler           ; TMR1 Capture Compare
+                DCD     TMR2_IRQHandler              ; TMR2
+                DCD     TMR3_IRQHandler              ; TMR3
+                DCD     TMR4_IRQHandler              ; TMR4
+                DCD     I2C1_EV_IRQHandler           ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler           ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler           ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler           ; I2C2 Error
+                DCD     SPI1_IRQHandler              ; SPI1
+                DCD     SPI2_IRQHandler              ; SPI2
+                DCD     USART1_IRQHandler            ; USART1
+                DCD     USART2_IRQHandler            ; USART2
+                DCD     USART3_IRQHandler            ; USART3
+                DCD     EINT15_10_IRQHandler         ; EINT Line 15..10
+                DCD     RTCAlarm_IRQHandler          ; RTC Alarm through EINT Line
+                DCD     OTG_FS_WKUP_IRQHandler       ; USBD Wakeup from suspend
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     TMR5_IRQHandler              ; TMR5
+                DCD     SPI3_IRQHandler              ; SPI3
+                DCD     UART4_IRQHandler             ; UART4
+                DCD     UART5_IRQHandler             ; UART5
+                DCD     TMR6_IRQHandler              ; TMR6
+                DCD     TMR7_IRQHandler              ; TMR7
+                DCD     DMA2_Channel1_IRQHandler     ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler     ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler     ; DMA2 Channel3
+                DCD     DMA2_Channel4_IRQHandler     ; DMA2 Channel4
+                DCD     DMA2_Channel5_IRQHandler     ; DMA2 Channel5
+                DCD     ETH_IRQHandler               ; ETH
+                DCD     ETH_WKUP_IRQHandler          ; ETH Wake up
+                DCD     CAN2_TX_IRQHandler           ; CAN2 TX
+                DCD     CAN2_RX0_IRQHandler          ; CAN2 RX0
+                DCD     CAN2_RX1_IRQHandler          ; CAN2 RX1
+                DCD     CAN2_SCE_IRQHandler          ; CAN2 SCE
+                DCD     OTG_FS_IRQHandler            ; OTG FS
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler   PROC
+                EXPORT  Reset_Handler                [WEAK]
+                IMPORT  __main
+                IMPORT  SystemInit
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                  [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler            [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler            [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler             [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler           [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                  [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler             [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler               [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler              [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDT_IRQHandler              [WEAK]
+                EXPORT  PVD_IRQHandler               [WEAK]
+                EXPORT  TAMPER_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler             [WEAK]
+                EXPORT  RCM_IRQHandler               [WEAK]
+                EXPORT  EINT0_IRQHandler             [WEAK]
+                EXPORT  EINT1_IRQHandler             [WEAK]
+                EXPORT  EINT2_IRQHandler             [WEAK]
+                EXPORT  EINT3_IRQHandler             [WEAK]
+                EXPORT  EINT4_IRQHandler             [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler     [WEAK]
+                EXPORT  ADC1_2_IRQHandler            [WEAK]
+                EXPORT  CAN1_TX_IRQHandler           [WEAK]
+                EXPORT  CAN1_RX0_IRQHandler          [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler          [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler          [WEAK]
+                EXPORT  EINT9_5_IRQHandler           [WEAK]
+                EXPORT  TMR1_BRK_IRQHandler          [WEAK]
+                EXPORT  TMR1_UP_IRQHandler           [WEAK]
+                EXPORT  TMR1_TRG_COM_IRQHandler      [WEAK]
+                EXPORT  TMR1_CC_IRQHandler           [WEAK]
+                EXPORT  TMR2_IRQHandler              [WEAK]
+                EXPORT  TMR3_IRQHandler              [WEAK]
+                EXPORT  TMR4_IRQHandler              [WEAK]
+                EXPORT  I2C1_EV_IRQHandler           [WEAK]
+                EXPORT  I2C1_ER_IRQHandler           [WEAK]
+                EXPORT  I2C2_EV_IRQHandler           [WEAK]
+                EXPORT  I2C2_ER_IRQHandler           [WEAK]
+                EXPORT  SPI1_IRQHandler              [WEAK]
+                EXPORT  SPI2_IRQHandler              [WEAK]
+                EXPORT  USART1_IRQHandler            [WEAK]
+                EXPORT  USART2_IRQHandler            [WEAK]
+                EXPORT  USART3_IRQHandler            [WEAK]
+                EXPORT  EINT15_10_IRQHandler         [WEAK]
+                EXPORT  RTCAlarm_IRQHandler          [WEAK]
+                EXPORT  OTG_FS_WKUP_IRQHandler       [WEAK]
+                EXPORT  TMR5_IRQHandler              [WEAK]
+                EXPORT  SPI3_IRQHandler              [WEAK]
+                EXPORT  UART4_IRQHandler             [WEAK]
+                EXPORT  UART5_IRQHandler             [WEAK]
+                EXPORT  TMR6_IRQHandler              [WEAK]
+                EXPORT  TMR7_IRQHandler              [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler     [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler     [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler     [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler     [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler     [WEAK]
+                EXPORT  ETH_IRQHandler               [WEAK]
+                EXPORT  ETH_WKUP_IRQHandler          [WEAK]
+                EXPORT  CAN2_TX_IRQHandler           [WEAK]
+                EXPORT  CAN2_RX0_IRQHandler          [WEAK]
+                EXPORT  CAN2_RX1_IRQHandler          [WEAK]
+                EXPORT  CAN2_SCE_IRQHandler          [WEAK]
+                EXPORT  OTG_FS_IRQHandler            [WEAK]
+
+WWDT_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCM_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+EINT4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EINT9_5_IRQHandler
+TMR1_BRK_IRQHandler
+TMR1_UP_IRQHandler
+TMR1_TRG_COM_IRQHandler
+TMR1_CC_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+TMR4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EINT15_10_IRQHandler
+RTCAlarm_IRQHandler
+OTG_FS_WKUP_IRQHandler
+TMR5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TMR6_IRQHandler
+TMR7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+OTG_FS_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, = Heap_Mem
+                 LDR     R1, = (Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem  + Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;*******************************END OF FILE************************************
+

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s

@@ -3,9 +3,9 @@
 ; *
 ; * @brief       CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
 ; *
-; * @version     V1.0.2
+; * @version     V1.0.3
 ; *
-; * @date        2022-01-05
+; * @date        2022-07-25
 ; *
 ; * @attention
 ; *
@@ -15,7 +15,7 @@
 ; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
 ; *
 ; *  The program is only for reference, which is distributed in the hope
-; *  that it will be usefull and instructional for customers to develop
+; *  that it will be useful and instructional for customers to develop
 ; *  their software. Unless required by applicable law or agreed to in
 ; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
 ; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,339 +23,248 @@
 ; *  and limitations under the License.
 ; */
 
-;
-<h> Stack Configuration
-;
-<o> Stack Size(in Bytes) < 0x0 - 0xFFFFFFFF: 8 >
-;
-< / h >
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
 
 Stack_Size      EQU     0x00000400
 
-AREA    STACK, NOINIT, READWRITE, ALIGN = 3
-        Stack_Mem       SPACE   Stack_Size
-        __initial_sp
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
 
 
-        ;
-<h> Heap Configuration
-;
-<o>  Heap Size(in Bytes) < 0x0 - 0xFFFFFFFF: 8 >
-;
-< / h >
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
 
 Heap_Size       EQU     0x00000200
 
-AREA    HEAP, NOINIT, READWRITE, ALIGN = 3
-        __heap_base
-        Heap_Mem        SPACE   Heap_Size
-        __heap_limit
-
-        PRESERVE8
-        THUMB
-
-
-        ;
-Vector Table Mapped to Address 0 at Reset
-AREA    RESET, DATA, READONLY
-EXPORT  __Vectors
-EXPORT  __Vectors_End
-EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                 ;
-Top of Stack
-DCD     Reset_Handler                ;
-Reset Handler
-DCD     NMI_Handler                  ;
-NMI Handler
-DCD     HardFault_Handler            ;
-Hard Fault Handler
-DCD     MemManage_Handler            ;
-MPU Fault Handler
-DCD     BusFault_Handler             ;
-Bus Fault Handler
-DCD     UsageFault_Handler           ;
-Usage Fault Handler
-DCD     0                            ;
-Reserved
-DCD     0                            ;
-Reserved
-DCD     0                            ;
-Reserved
-DCD     0                            ;
-Reserved
-DCD     SVC_Handler                  ;
-SVCall Handler
-DCD     DebugMon_Handler             ;
-Debug Monitor Handler
-DCD     0                            ;
-Reserved
-DCD     PendSV_Handler               ;
-PendSV Handler
-DCD     SysTick_Handler              ;
-SysTick Handler
-
-;
-External Interrupts
-DCD     WWDT_IRQHandler              ;
-Window Watchdog
-DCD     PVD_IRQHandler               ;
-PVD through EINT Line detect
-DCD     TAMPER_IRQHandler            ;
-Tamper
-DCD     RTC_IRQHandler               ;
-RTC
-DCD     FLASH_IRQHandler             ;
-Flash
-DCD     RCM_IRQHandler               ;
-RCM
-DCD     EINT0_IRQHandler             ;
-EINT Line 0
-DCD     EINT1_IRQHandler             ;
-EINT Line 1
-DCD     EINT2_IRQHandler             ;
-EINT Line 2
-DCD     EINT3_IRQHandler             ;
-EINT Line 3
-DCD     EINT4_IRQHandler             ;
-EINT Line 4
-DCD     DMA1_Channel1_IRQHandler     ;
-DMA1 Channel 1
-DCD     DMA1_Channel2_IRQHandler     ;
-DMA1 Channel 2
-DCD     DMA1_Channel3_IRQHandler     ;
-DMA1 Channel 3
-DCD     DMA1_Channel4_IRQHandler     ;
-DMA1 Channel 4
-DCD     DMA1_Channel5_IRQHandler     ;
-DMA1 Channel 5
-DCD     DMA1_Channel6_IRQHandler     ;
-DMA1 Channel 6
-DCD     DMA1_Channel7_IRQHandler     ;
-DMA1 Channel 7
-DCD     ADC1_2_IRQHandler            ;
-ADC1 &ADC2
-DCD     USBD1_HP_CAN1_TX_IRQHandler  ;
-USBD1 High Priority or CAN1 TX
-DCD     USBD1_LP_CAN1_RX0_IRQHandler ;
-USBD1 Low  Priority or CAN1 RX0
-DCD     CAN1_RX1_IRQHandler          ;
-CAN1 RX1
-DCD     CAN1_SCE_IRQHandler          ;
-CAN1 SCE
-DCD     EINT9_5_IRQHandler           ;
-EINT Line 9..5
-DCD     TMR1_BRK_IRQHandler          ;
-TMR1 Break
-DCD     TMR1_UP_IRQHandler           ;
-TMR1 Update
-DCD     TMR1_TRG_COM_IRQHandler      ;
-TMR1 Trigger and Commutation
-DCD     TMR1_CC_IRQHandler           ;
-TMR1 Capture Compare
-DCD     TMR2_IRQHandler              ;
-TMR2
-DCD     TMR3_IRQHandler              ;
-TMR3
-DCD     TMR4_IRQHandler              ;
-TMR4
-DCD     I2C1_EV_IRQHandler           ;
-I2C1 Event
-DCD     I2C1_ER_IRQHandler           ;
-I2C1 Error
-DCD     I2C2_EV_IRQHandler           ;
-I2C2 Event
-DCD     I2C2_ER_IRQHandler           ;
-I2C2 Error
-DCD     SPI1_IRQHandler              ;
-SPI1
-DCD     SPI2_IRQHandler              ;
-SPI2
-DCD     USART1_IRQHandler            ;
-USART1
-DCD     USART2_IRQHandler            ;
-USART2
-DCD     USART3_IRQHandler            ;
-USART3
-DCD     EINT15_10_IRQHandler         ;
-EINT Line 15..10
-DCD     RTCAlarm_IRQHandler          ;
-RTC Alarm through EINT Line
-DCD     USBDWakeUp_IRQHandler        ;
-USBD Wakeup from suspend
-DCD     TMR8_BRK_IRQHandler          ;
-TMR8 Break
-DCD     TMR8_UP_IRQHandler           ;
-TMR8 Update
-DCD     TMR8_TRG_COM_IRQHandler      ;
-TMR8 Trigger and Commutation
-DCD     TMR8_CC_IRQHandler           ;
-TMR8 Capture Compare
-DCD     ADC3_IRQHandler              ;
-ADC3
-DCD     EMMC_IRQHandler              ;
-EMMC
-DCD     SDIO_IRQHandler              ;
-SDIO
-DCD     TMR5_IRQHandler              ;
-TMR5
-DCD     SPI3_IRQHandler              ;
-SPI3
-DCD     UART4_IRQHandler             ;
-UART4
-DCD     UART5_IRQHandler             ;
-UART5
-DCD     TMR6_IRQHandler              ;
-TMR6
-DCD     TMR7_IRQHandler              ;
-TMR7
-DCD     DMA2_Channel1_IRQHandler     ;
-DMA2 Channel1
-DCD     DMA2_Channel2_IRQHandler     ;
-DMA2 Channel2
-DCD     DMA2_Channel3_IRQHandler     ;
-DMA2 Channel3
-DCD     DMA2_Channel4_5_IRQHandler   ;
-DMA2 Channel4 &Channel5
-DCD     0                            ;
-Reserved
-DCD     USBD2_HP_CAN2_TX_IRQHandler  ;
-USBD2 High Priority or CAN2 TX
-DCD     USBD2_LP_CAN2_RX0_IRQHandler ;
-USBD2 Low  Priority or CAN2 RX0
-DCD     CAN2_RX1_IRQHandler          ;
-CAN2 RX1
-DCD     CAN2_SCE_IRQHandler          ;
-CAN2 SCE
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                 ; Top of Stack
+                DCD     Reset_Handler                ; Reset Handler
+                DCD     NMI_Handler                  ; NMI Handler
+                DCD     HardFault_Handler            ; Hard Fault Handler
+                DCD     MemManage_Handler            ; MPU Fault Handler
+                DCD     BusFault_Handler             ; Bus Fault Handler
+                DCD     UsageFault_Handler           ; Usage Fault Handler
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     SVC_Handler                  ; SVCall Handler
+                DCD     DebugMon_Handler             ; Debug Monitor Handler
+                DCD     0                            ; Reserved
+                DCD     PendSV_Handler               ; PendSV Handler
+                DCD     SysTick_Handler              ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDT_IRQHandler              ; Window Watchdog
+                DCD     PVD_IRQHandler               ; PVD through EINT Line detect
+                DCD     TAMPER_IRQHandler            ; Tamper
+                DCD     RTC_IRQHandler               ; RTC
+                DCD     FLASH_IRQHandler             ; Flash
+                DCD     RCM_IRQHandler               ; RCM
+                DCD     EINT0_IRQHandler             ; EINT Line 0
+                DCD     EINT1_IRQHandler             ; EINT Line 1
+                DCD     EINT2_IRQHandler             ; EINT Line 2
+                DCD     EINT3_IRQHandler             ; EINT Line 3
+                DCD     EINT4_IRQHandler             ; EINT Line 4
+                DCD     DMA1_Channel1_IRQHandler     ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler     ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler     ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler     ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler     ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler     ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler     ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler            ; ADC1 & ADC2
+                DCD     USBD1_HP_CAN1_TX_IRQHandler  ; USBD1 High Priority or CAN1 TX
+                DCD     USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler          ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler          ; CAN1 SCE
+                DCD     EINT9_5_IRQHandler           ; EINT Line 9..5
+                DCD     TMR1_BRK_IRQHandler          ; TMR1 Break
+                DCD     TMR1_UP_IRQHandler           ; TMR1 Update
+                DCD     TMR1_TRG_COM_IRQHandler      ; TMR1 Trigger and Commutation
+                DCD     TMR1_CC_IRQHandler           ; TMR1 Capture Compare
+                DCD     TMR2_IRQHandler              ; TMR2
+                DCD     TMR3_IRQHandler              ; TMR3
+                DCD     TMR4_IRQHandler              ; TMR4
+                DCD     I2C1_EV_IRQHandler           ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler           ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler           ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler           ; I2C2 Error
+                DCD     SPI1_IRQHandler              ; SPI1
+                DCD     SPI2_IRQHandler              ; SPI2
+                DCD     USART1_IRQHandler            ; USART1
+                DCD     USART2_IRQHandler            ; USART2
+                DCD     USART3_IRQHandler            ; USART3
+                DCD     EINT15_10_IRQHandler         ; EINT Line 15..10
+                DCD     RTCAlarm_IRQHandler          ; RTC Alarm through EINT Line
+                DCD     USBDWakeUp_IRQHandler        ; USBD Wakeup from suspend
+                DCD     TMR8_BRK_IRQHandler          ; TMR8 Break
+                DCD     TMR8_UP_IRQHandler           ; TMR8 Update
+                DCD     TMR8_TRG_COM_IRQHandler      ; TMR8 Trigger and Commutation
+                DCD     TMR8_CC_IRQHandler           ; TMR8 Capture Compare
+                DCD     ADC3_IRQHandler              ; ADC3
+                DCD     EMMC_IRQHandler              ; EMMC
+                DCD     SDIO_IRQHandler              ; SDIO
+                DCD     TMR5_IRQHandler              ; TMR5
+                DCD     SPI3_IRQHandler              ; SPI3
+                DCD     UART4_IRQHandler             ; UART4
+                DCD     UART5_IRQHandler             ; UART5
+                DCD     TMR6_IRQHandler              ; TMR6
+                DCD     TMR7_IRQHandler              ; TMR7
+                DCD     DMA2_Channel1_IRQHandler     ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler     ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler     ; DMA2 Channel3
+                DCD     DMA2_Channel4_5_IRQHandler   ; DMA2 Channel4 & Channel5
+                DCD     0                            ; Reserved
+                DCD     USBD2_HP_CAN2_TX_IRQHandler  ; USBD2 High Priority or CAN2 TX
+                DCD     USBD2_LP_CAN2_RX0_IRQHandler ; USBD2 Low  Priority or CAN2 RX0
+                DCD     CAN2_RX1_IRQHandler          ; CAN2 RX1
+                DCD     CAN2_SCE_IRQHandler          ; CAN2 SCE
 __Vectors_End
 
 __Vectors_Size  EQU  __Vectors_End - __Vectors
 
-AREA    | .text |, CODE, READONLY
+                AREA    |.text|, CODE, READONLY
 
-;
-Reset handler
+; Reset handler
 Reset_Handler   PROC
-EXPORT  Reset_Handler                [WEAK]
-IMPORT  __main
-IMPORT  SystemInit
-LDR     R0, = SystemInit
-              BLX     R0
-              LDR     R0, = __main
-                            BX      R0
-                            ENDP
-
-                            ;
-Dummy Exception Handlers(infinite loops which can be modified)
+                EXPORT  Reset_Handler                [WEAK]
+                IMPORT  __main
+                IMPORT  SystemInit
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
 
 NMI_Handler     PROC
-EXPORT  NMI_Handler                  [WEAK]
-B       .
-ENDP
+                EXPORT  NMI_Handler                  [WEAK]
+                B       .
+                ENDP
 HardFault_Handler\
-PROC
-EXPORT  HardFault_Handler            [WEAK]
-B       .
-ENDP
+                PROC
+                EXPORT  HardFault_Handler            [WEAK]
+                B       .
+                ENDP
 MemManage_Handler\
-PROC
-EXPORT  MemManage_Handler            [WEAK]
-B       .
-ENDP
+                PROC
+                EXPORT  MemManage_Handler            [WEAK]
+                B       .
+                ENDP
 BusFault_Handler\
-PROC
-EXPORT  BusFault_Handler             [WEAK]
-B       .
-ENDP
+                PROC
+                EXPORT  BusFault_Handler             [WEAK]
+                B       .
+                ENDP
 UsageFault_Handler\
-PROC
-EXPORT  UsageFault_Handler           [WEAK]
-B       .
-ENDP
+                PROC
+                EXPORT  UsageFault_Handler           [WEAK]
+                B       .
+                ENDP
 SVC_Handler     PROC
-EXPORT  SVC_Handler                  [WEAK]
-B       .
-ENDP
+                EXPORT  SVC_Handler                  [WEAK]
+                B       .
+                ENDP
 DebugMon_Handler\
-PROC
-EXPORT  DebugMon_Handler             [WEAK]
-B       .
-ENDP
+                PROC
+                EXPORT  DebugMon_Handler             [WEAK]
+                B       .
+                ENDP
 PendSV_Handler  PROC
-EXPORT  PendSV_Handler               [WEAK]
-B       .
-ENDP
+                EXPORT  PendSV_Handler               [WEAK]
+                B       .
+                ENDP
 SysTick_Handler PROC
-EXPORT  SysTick_Handler              [WEAK]
-B       .
-ENDP
+                EXPORT  SysTick_Handler              [WEAK]
+                B       .
+                ENDP
 
 Default_Handler PROC
 
-EXPORT  WWDT_IRQHandler              [WEAK]
-EXPORT  PVD_IRQHandler               [WEAK]
-EXPORT  TAMPER_IRQHandler            [WEAK]
-EXPORT  RTC_IRQHandler               [WEAK]
-EXPORT  FLASH_IRQHandler             [WEAK]
-EXPORT  RCM_IRQHandler               [WEAK]
-EXPORT  EINT0_IRQHandler             [WEAK]
-EXPORT  EINT1_IRQHandler             [WEAK]
-EXPORT  EINT2_IRQHandler             [WEAK]
-EXPORT  EINT3_IRQHandler             [WEAK]
-EXPORT  EINT4_IRQHandler             [WEAK]
-EXPORT  DMA1_Channel1_IRQHandler     [WEAK]
-EXPORT  DMA1_Channel2_IRQHandler     [WEAK]
-EXPORT  DMA1_Channel3_IRQHandler     [WEAK]
-EXPORT  DMA1_Channel4_IRQHandler     [WEAK]
-EXPORT  DMA1_Channel5_IRQHandler     [WEAK]
-EXPORT  DMA1_Channel6_IRQHandler     [WEAK]
-EXPORT  DMA1_Channel7_IRQHandler     [WEAK]
-EXPORT  ADC1_2_IRQHandler            [WEAK]
-EXPORT  USBD1_HP_CAN1_TX_IRQHandler  [WEAK]
-EXPORT  USBD1_LP_CAN1_RX0_IRQHandler [WEAK]
-EXPORT  CAN1_RX1_IRQHandler          [WEAK]
-EXPORT  CAN1_SCE_IRQHandler          [WEAK]
-EXPORT  EINT9_5_IRQHandler           [WEAK]
-EXPORT  TMR1_BRK_IRQHandler          [WEAK]
-EXPORT  TMR1_UP_IRQHandler           [WEAK]
-EXPORT  TMR1_TRG_COM_IRQHandler      [WEAK]
-EXPORT  TMR1_CC_IRQHandler           [WEAK]
-EXPORT  TMR2_IRQHandler              [WEAK]
-EXPORT  TMR3_IRQHandler              [WEAK]
-EXPORT  TMR4_IRQHandler              [WEAK]
-EXPORT  I2C1_EV_IRQHandler           [WEAK]
-EXPORT  I2C1_ER_IRQHandler           [WEAK]
-EXPORT  I2C2_EV_IRQHandler           [WEAK]
-EXPORT  I2C2_ER_IRQHandler           [WEAK]
-EXPORT  SPI1_IRQHandler              [WEAK]
-EXPORT  SPI2_IRQHandler              [WEAK]
-EXPORT  USART1_IRQHandler            [WEAK]
-EXPORT  USART2_IRQHandler            [WEAK]
-EXPORT  USART3_IRQHandler            [WEAK]
-EXPORT  EINT15_10_IRQHandler         [WEAK]
-EXPORT  RTCAlarm_IRQHandler          [WEAK]
-EXPORT  USBDWakeUp_IRQHandler        [WEAK]
-EXPORT  TMR8_BRK_IRQHandler          [WEAK]
-EXPORT  TMR8_UP_IRQHandler           [WEAK]
-EXPORT  TMR8_TRG_COM_IRQHandler      [WEAK]
-EXPORT  TMR8_CC_IRQHandler           [WEAK]
-EXPORT  ADC3_IRQHandler              [WEAK]
-EXPORT  EMMC_IRQHandler              [WEAK]
-EXPORT  SDIO_IRQHandler              [WEAK]
-EXPORT  TMR5_IRQHandler              [WEAK]
-EXPORT  SPI3_IRQHandler              [WEAK]
-EXPORT  UART4_IRQHandler             [WEAK]
-EXPORT  UART5_IRQHandler             [WEAK]
-EXPORT  TMR6_IRQHandler              [WEAK]
-EXPORT  TMR7_IRQHandler              [WEAK]
-EXPORT  DMA2_Channel1_IRQHandler     [WEAK]
-EXPORT  DMA2_Channel2_IRQHandler     [WEAK]
-EXPORT  DMA2_Channel3_IRQHandler     [WEAK]
-EXPORT  DMA2_Channel4_5_IRQHandler   [WEAK]
-EXPORT  USBD2_HP_CAN2_TX_IRQHandler  [WEAK]
-EXPORT  USBD2_LP_CAN2_RX0_IRQHandler [WEAK]
-EXPORT  CAN2_RX1_IRQHandler          [WEAK]
-EXPORT  CAN2_SCE_IRQHandler          [WEAK]
+                EXPORT  WWDT_IRQHandler              [WEAK]
+                EXPORT  PVD_IRQHandler               [WEAK]
+                EXPORT  TAMPER_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler             [WEAK]
+                EXPORT  RCM_IRQHandler               [WEAK]
+                EXPORT  EINT0_IRQHandler             [WEAK]
+                EXPORT  EINT1_IRQHandler             [WEAK]
+                EXPORT  EINT2_IRQHandler             [WEAK]
+                EXPORT  EINT3_IRQHandler             [WEAK]
+                EXPORT  EINT4_IRQHandler             [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler     [WEAK]
+                EXPORT  ADC1_2_IRQHandler            [WEAK]
+                EXPORT  USBD1_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USBD1_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler          [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler          [WEAK]
+                EXPORT  EINT9_5_IRQHandler           [WEAK]
+                EXPORT  TMR1_BRK_IRQHandler          [WEAK]
+                EXPORT  TMR1_UP_IRQHandler           [WEAK]
+                EXPORT  TMR1_TRG_COM_IRQHandler      [WEAK]
+                EXPORT  TMR1_CC_IRQHandler           [WEAK]
+                EXPORT  TMR2_IRQHandler              [WEAK]
+                EXPORT  TMR3_IRQHandler              [WEAK]
+                EXPORT  TMR4_IRQHandler              [WEAK]
+                EXPORT  I2C1_EV_IRQHandler           [WEAK]
+                EXPORT  I2C1_ER_IRQHandler           [WEAK]
+                EXPORT  I2C2_EV_IRQHandler           [WEAK]
+                EXPORT  I2C2_ER_IRQHandler           [WEAK]
+                EXPORT  SPI1_IRQHandler              [WEAK]
+                EXPORT  SPI2_IRQHandler              [WEAK]
+                EXPORT  USART1_IRQHandler            [WEAK]
+                EXPORT  USART2_IRQHandler            [WEAK]
+                EXPORT  USART3_IRQHandler            [WEAK]
+                EXPORT  EINT15_10_IRQHandler         [WEAK]
+                EXPORT  RTCAlarm_IRQHandler          [WEAK]
+                EXPORT  USBDWakeUp_IRQHandler        [WEAK]
+                EXPORT  TMR8_BRK_IRQHandler          [WEAK]
+                EXPORT  TMR8_UP_IRQHandler           [WEAK]
+                EXPORT  TMR8_TRG_COM_IRQHandler      [WEAK]
+                EXPORT  TMR8_CC_IRQHandler           [WEAK]
+                EXPORT  ADC3_IRQHandler              [WEAK]
+                EXPORT  EMMC_IRQHandler              [WEAK]
+                EXPORT  SDIO_IRQHandler              [WEAK]
+                EXPORT  TMR5_IRQHandler              [WEAK]
+                EXPORT  SPI3_IRQHandler              [WEAK]
+                EXPORT  UART4_IRQHandler             [WEAK]
+                EXPORT  UART5_IRQHandler             [WEAK]
+                EXPORT  TMR6_IRQHandler              [WEAK]
+                EXPORT  TMR7_IRQHandler              [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler     [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler     [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler     [WEAK]
+                EXPORT  DMA2_Channel4_5_IRQHandler   [WEAK]
+                EXPORT  USBD2_HP_CAN2_TX_IRQHandler  [WEAK]
+                EXPORT  USBD2_LP_CAN2_RX0_IRQHandler [WEAK]
+                EXPORT  CAN2_RX1_IRQHandler          [WEAK]
+                EXPORT  CAN2_SCE_IRQHandler          [WEAK]
 
 WWDT_IRQHandler
 PVD_IRQHandler
@@ -421,45 +330,39 @@ USBD2_HP_CAN2_TX_IRQHandler
 USBD2_LP_CAN2_RX0_IRQHandler
 CAN2_RX1_IRQHandler
 CAN2_SCE_IRQHandler
-B       .
+                B       .
 
-ENDP
+                ENDP
 
-ALIGN
+                ALIGN
 
-;
-*******************************************************************************
-;
-User Stack and Heap initialization
-;
-*******************************************************************************
-IF      :
-DEF:
-__MICROLIB
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
 
-EXPORT  __initial_sp
-EXPORT  __heap_base
-EXPORT  __heap_limit
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
 
-ELSE
+                 ELSE
 
-IMPORT  __use_two_region_memory
-EXPORT  __user_initial_stackheap
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
 
 __user_initial_stackheap
 
-LDR     R0, = Heap_Mem
-              LDR     R1, = (Stack_Mem + Stack_Size)
-                            LDR     R2, = (Heap_Mem  + Heap_Size)
-                                    LDR     R3, = Stack_Mem
-                                            BX      LR
+                 LDR     R0, = Heap_Mem
+                 LDR     R1, = (Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem  + Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
 
-                                            ALIGN
+                 ALIGN
 
-                                            ENDIF
+                 ENDIF
 
-                                            END
+                 END
 
-                                            ;
-*******************************END OF FILE ************************************
+;*******************************END OF FILE************************************
 

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_md.s

@@ -3,9 +3,9 @@
 ; *
 ; * @brief       CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_md
 ; *
-; * @version     V1.0.2
+; * @version     V1.0.3
 ; *
-; * @date        2022-01-05
+; * @date        2022-07-25
 ; *
 ; * @attention
 ; *
@@ -15,7 +15,7 @@
 ; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
 ; *
 ; *  The program is only for reference, which is distributed in the hope
-; *  that it will be usefull and instructional for customers to develop
+; *  that it will be useful and instructional for customers to develop
 ; *  their software. Unless required by applicable law or agreed to in
 ; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
 ; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,286 +23,213 @@
 ; *  and limitations under the License.
 ; */
 
-;
-<h> Stack Configuration
-;
-<o> Stack Size(in Bytes) < 0x0 - 0xFFFFFFFF: 8 >
-;
-< / h >
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
 
 Stack_Size      EQU     0x00000400
 
-AREA    STACK, NOINIT, READWRITE, ALIGN = 3
-        Stack_Mem       SPACE   Stack_Size
-        __initial_sp
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
 
 
-        ;
-<h> Heap Configuration
-;
-<o>  Heap Size(in Bytes) < 0x0 - 0xFFFFFFFF: 8 >
-;
-< / h >
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
 
 Heap_Size       EQU     0x00000200
 
-AREA    HEAP, NOINIT, READWRITE, ALIGN = 3
-        __heap_base
-        Heap_Mem        SPACE   Heap_Size
-        __heap_limit
-
-        PRESERVE8
-        THUMB
-
-
-        ;
-Vector Table Mapped to Address 0 at Reset
-AREA    RESET, DATA, READONLY
-EXPORT  __Vectors
-EXPORT  __Vectors_End
-EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                 ;
-Top of Stack
-DCD     Reset_Handler                ;
-Reset Handler
-DCD     NMI_Handler                  ;
-NMI Handler
-DCD     HardFault_Handler            ;
-Hard Fault Handler
-DCD     MemManage_Handler            ;
-MPU Fault Handler
-DCD     BusFault_Handler             ;
-Bus Fault Handler
-DCD     UsageFault_Handler           ;
-Usage Fault Handler
-DCD     0                            ;
-Reserved
-DCD     0                            ;
-Reserved
-DCD     0                            ;
-Reserved
-DCD     0                            ;
-Reserved
-DCD     SVC_Handler                  ;
-SVCall Handler
-DCD     DebugMon_Handler             ;
-Debug Monitor Handler
-DCD     0                            ;
-Reserved
-DCD     PendSV_Handler               ;
-PendSV Handler
-DCD     SysTick_Handler              ;
-SysTick Handler
-
-;
-External Interrupts
-DCD     WWDT_IRQHandler              ;
-Window Watchdog
-DCD     PVD_IRQHandler               ;
-PVD through EINT Line detect
-DCD     TAMPER_IRQHandler            ;
-Tamper
-DCD     RTC_IRQHandler               ;
-RTC
-DCD     FLASH_IRQHandler             ;
-Flash
-DCD     RCM_IRQHandler               ;
-RCM
-DCD     EINT0_IRQHandler             ;
-EINT Line 0
-DCD     EINT1_IRQHandler             ;
-EINT Line 1
-DCD     EINT2_IRQHandler             ;
-EINT Line 2
-DCD     EINT3_IRQHandler             ;
-EINT Line 3
-DCD     EINT4_IRQHandler             ;
-EINT Line 4
-DCD     DMA1_Channel1_IRQHandler     ;
-DMA1 Channel 1
-DCD     DMA1_Channel2_IRQHandler     ;
-DMA1 Channel 2
-DCD     DMA1_Channel3_IRQHandler     ;
-DMA1 Channel 3
-DCD     DMA1_Channel4_IRQHandler     ;
-DMA1 Channel 4
-DCD     DMA1_Channel5_IRQHandler     ;
-DMA1 Channel 5
-DCD     DMA1_Channel6_IRQHandler     ;
-DMA1 Channel 6
-DCD     DMA1_Channel7_IRQHandler     ;
-DMA1 Channel 7
-DCD     ADC1_2_IRQHandler            ;
-ADC1_2
-DCD     USBD1_HP_CAN1_TX_IRQHandler  ;
-USBD1 High Priority or CAN1 TX
-DCD     USBD1_LP_CAN1_RX0_IRQHandler ;
-USBD1 Low  Priority or CAN1 RX0
-DCD     CAN1_RX1_IRQHandler          ;
-CAN1 RX1
-DCD     CAN1_SCE_IRQHandler          ;
-CAN1 SCE
-DCD     EINT9_5_IRQHandler           ;
-EINT Line 9..5
-DCD     TMR1_BRK_IRQHandler          ;
-TMR1 Break
-DCD     TMR1_UP_IRQHandler           ;
-TMR1 Update
-DCD     TMR1_TRG_COM_IRQHandler      ;
-TMR1 Trigger and Commutation
-DCD     TMR1_CC_IRQHandler           ;
-TMR1 Capture Compare
-DCD     TMR2_IRQHandler              ;
-TMR2
-DCD     TMR3_IRQHandler              ;
-TMR3
-DCD     TMR4_IRQHandler              ;
-TMR4
-DCD     I2C1_EV_IRQHandler           ;
-I2C1 Event
-DCD     I2C1_ER_IRQHandler           ;
-I2C1 Error
-DCD     I2C2_EV_IRQHandler           ;
-I2C2 Event
-DCD     I2C2_ER_IRQHandler           ;
-I2C2 Error
-DCD     SPI1_IRQHandler              ;
-SPI1
-DCD     SPI2_IRQHandler              ;
-SPI2
-DCD     USART1_IRQHandler            ;
-USART1
-DCD     USART2_IRQHandler            ;
-USART2
-DCD     USART3_IRQHandler            ;
-USART3
-DCD     EINT15_10_IRQHandler         ;
-EINT Line 15..10
-DCD     RTCAlarm_IRQHandler          ;
-RTC Alarm through EINT Line
-DCD     USBDWakeUp_IRQHandler        ;
-USBD Wakeup from suspend
-DCD     FPU_IRQHandler               ;
-FPU
-DCD     QSPI_IRQHandler              ;
-QSPI
-DCD     USBD2_HP_IRQHandler          ;
-USBD2 High Priority
-DCD     USBD2_LP_IRQHandler          ;
-USBD2 Low Priority
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                 ; Top of Stack
+                DCD     Reset_Handler                ; Reset Handler
+                DCD     NMI_Handler                  ; NMI Handler
+                DCD     HardFault_Handler            ; Hard Fault Handler
+                DCD     MemManage_Handler            ; MPU Fault Handler
+                DCD     BusFault_Handler             ; Bus Fault Handler
+                DCD     UsageFault_Handler           ; Usage Fault Handler
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     SVC_Handler                  ; SVCall Handler
+                DCD     DebugMon_Handler             ; Debug Monitor Handler
+                DCD     0                            ; Reserved
+                DCD     PendSV_Handler               ; PendSV Handler
+                DCD     SysTick_Handler              ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDT_IRQHandler              ; Window Watchdog
+                DCD     PVD_IRQHandler               ; PVD through EINT Line detect
+                DCD     TAMPER_IRQHandler            ; Tamper
+                DCD     RTC_IRQHandler               ; RTC
+                DCD     FLASH_IRQHandler             ; Flash
+                DCD     RCM_IRQHandler               ; RCM
+                DCD     EINT0_IRQHandler             ; EINT Line 0
+                DCD     EINT1_IRQHandler             ; EINT Line 1
+                DCD     EINT2_IRQHandler             ; EINT Line 2
+                DCD     EINT3_IRQHandler             ; EINT Line 3
+                DCD     EINT4_IRQHandler             ; EINT Line 4
+                DCD     DMA1_Channel1_IRQHandler     ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler     ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler     ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler     ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler     ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler     ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler     ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler            ; ADC1_2
+                DCD     USBD1_HP_CAN1_TX_IRQHandler  ; USBD1 High Priority or CAN1 TX
+                DCD     USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler          ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler          ; CAN1 SCE
+                DCD     EINT9_5_IRQHandler           ; EINT Line 9..5
+                DCD     TMR1_BRK_IRQHandler          ; TMR1 Break
+                DCD     TMR1_UP_IRQHandler           ; TMR1 Update
+                DCD     TMR1_TRG_COM_IRQHandler      ; TMR1 Trigger and Commutation
+                DCD     TMR1_CC_IRQHandler           ; TMR1 Capture Compare
+                DCD     TMR2_IRQHandler              ; TMR2
+                DCD     TMR3_IRQHandler              ; TMR3
+                DCD     TMR4_IRQHandler              ; TMR4
+                DCD     I2C1_EV_IRQHandler           ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler           ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler           ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler           ; I2C2 Error
+                DCD     SPI1_IRQHandler              ; SPI1
+                DCD     SPI2_IRQHandler              ; SPI2
+                DCD     USART1_IRQHandler            ; USART1
+                DCD     USART2_IRQHandler            ; USART2
+                DCD     USART3_IRQHandler            ; USART3
+                DCD     EINT15_10_IRQHandler         ; EINT Line 15..10
+                DCD     RTCAlarm_IRQHandler          ; RTC Alarm through EINT Line
+                DCD     USBDWakeUp_IRQHandler        ; USBD Wakeup from suspend
+                DCD     FPU_IRQHandler               ; FPU
+                DCD     QSPI_IRQHandler              ; QSPI
+                DCD     USBD2_HP_IRQHandler          ; USBD2 High Priority
+                DCD     USBD2_LP_IRQHandler          ; USBD2 Low Priority
 __Vectors_End
 
 __Vectors_Size  EQU  __Vectors_End - __Vectors
 
-AREA    | .text |, CODE, READONLY
+                AREA    |.text|, CODE, READONLY
 
-;
-Reset handler
+; Reset handler
 Reset_Handler    PROC
-EXPORT  Reset_Handler               [WEAK]
-IMPORT  __main
-IMPORT  SystemInit
-LDR     R0, = SystemInit
-              BLX     R0
-              LDR     R0, = __main
-                            BX      R0
-                            ENDP
-
-                            ;
-Dummy Exception Handlers(infinite loops which can be modified)
+                 EXPORT  Reset_Handler               [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
 
 NMI_Handler     PROC
-EXPORT  NMI_Handler                  [WEAK]
-B       .
-ENDP
+                EXPORT  NMI_Handler                  [WEAK]
+                B       .
+                ENDP
 HardFault_Handler\
-PROC
-EXPORT  HardFault_Handler            [WEAK]
-B       .
-ENDP
+                PROC
+                EXPORT  HardFault_Handler            [WEAK]
+                B       .
+                ENDP
 MemManage_Handler\
-PROC
-EXPORT  MemManage_Handler            [WEAK]
-B       .
-ENDP
+                PROC
+                EXPORT  MemManage_Handler            [WEAK]
+                B       .
+                ENDP
 BusFault_Handler\
-PROC
-EXPORT  BusFault_Handler             [WEAK]
-B       .
-ENDP
+                PROC
+                EXPORT  BusFault_Handler             [WEAK]
+                B       .
+                ENDP
 UsageFault_Handler\
-PROC
-EXPORT  UsageFault_Handler           [WEAK]
-B       .
-ENDP
+                PROC
+                EXPORT  UsageFault_Handler           [WEAK]
+                B       .
+                ENDP
 SVC_Handler     PROC
-EXPORT  SVC_Handler                  [WEAK]
-B       .
-ENDP
+                EXPORT  SVC_Handler                  [WEAK]
+                B       .
+                ENDP
 DebugMon_Handler\
-PROC
-EXPORT  DebugMon_Handler             [WEAK]
-B       .
-ENDP
+                PROC
+                EXPORT  DebugMon_Handler             [WEAK]
+                B       .
+                ENDP
 PendSV_Handler  PROC
-EXPORT  PendSV_Handler               [WEAK]
-B       .
-ENDP
+                EXPORT  PendSV_Handler               [WEAK]
+                B       .
+                ENDP
 SysTick_Handler PROC
-EXPORT  SysTick_Handler              [WEAK]
-B       .
-ENDP
+                EXPORT  SysTick_Handler              [WEAK]
+                B       .
+                ENDP
 
 Default_Handler PROC
 
-EXPORT  WWDT_IRQHandler              [WEAK]
-EXPORT  PVD_IRQHandler               [WEAK]
-EXPORT  TAMPER_IRQHandler            [WEAK]
-EXPORT  RTC_IRQHandler               [WEAK]
-EXPORT  FLASH_IRQHandler             [WEAK]
-EXPORT  RCM_IRQHandler               [WEAK]
-EXPORT  EINT0_IRQHandler             [WEAK]
-EXPORT  EINT1_IRQHandler             [WEAK]
-EXPORT  EINT2_IRQHandler             [WEAK]
-EXPORT  EINT3_IRQHandler             [WEAK]
-EXPORT  EINT4_IRQHandler             [WEAK]
-EXPORT  DMA1_Channel1_IRQHandler     [WEAK]
-EXPORT  DMA1_Channel2_IRQHandler     [WEAK]
-EXPORT  DMA1_Channel3_IRQHandler     [WEAK]
-EXPORT  DMA1_Channel4_IRQHandler     [WEAK]
-EXPORT  DMA1_Channel5_IRQHandler     [WEAK]
-EXPORT  DMA1_Channel6_IRQHandler     [WEAK]
-EXPORT  DMA1_Channel7_IRQHandler     [WEAK]
-EXPORT  ADC1_2_IRQHandler            [WEAK]
-EXPORT  USBD1_HP_CAN1_TX_IRQHandler  [WEAK]
-EXPORT  USBD1_LP_CAN1_RX0_IRQHandler [WEAK]
-EXPORT  CAN1_RX1_IRQHandler          [WEAK]
-EXPORT  CAN1_SCE_IRQHandler          [WEAK]
-EXPORT  EINT9_5_IRQHandler           [WEAK]
-EXPORT  TMR1_BRK_IRQHandler          [WEAK]
-EXPORT  TMR1_UP_IRQHandler           [WEAK]
-EXPORT  TMR1_TRG_COM_IRQHandler      [WEAK]
-EXPORT  TMR1_CC_IRQHandler           [WEAK]
-EXPORT  TMR2_IRQHandler              [WEAK]
-EXPORT  TMR3_IRQHandler              [WEAK]
-EXPORT  TMR4_IRQHandler              [WEAK]
-EXPORT  I2C1_EV_IRQHandler           [WEAK]
-EXPORT  I2C1_ER_IRQHandler           [WEAK]
-EXPORT  I2C2_EV_IRQHandler           [WEAK]
-EXPORT  I2C2_ER_IRQHandler           [WEAK]
-EXPORT  SPI1_IRQHandler              [WEAK]
-EXPORT  SPI2_IRQHandler              [WEAK]
-EXPORT  USART1_IRQHandler            [WEAK]
-EXPORT  USART2_IRQHandler            [WEAK]
-EXPORT  USART3_IRQHandler            [WEAK]
-EXPORT  EINT15_10_IRQHandler         [WEAK]
-EXPORT  RTCAlarm_IRQHandler          [WEAK]
-EXPORT  USBDWakeUp_IRQHandler        [WEAK]
-EXPORT  FPU_IRQHandler               [WEAK]
-EXPORT  QSPI_IRQHandler              [WEAK]
-EXPORT  USBD2_HP_IRQHandler          [WEAK]
-EXPORT  USBD2_LP_IRQHandler          [WEAK]
+                EXPORT  WWDT_IRQHandler              [WEAK]
+                EXPORT  PVD_IRQHandler               [WEAK]
+                EXPORT  TAMPER_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler             [WEAK]
+                EXPORT  RCM_IRQHandler               [WEAK]
+                EXPORT  EINT0_IRQHandler             [WEAK]
+                EXPORT  EINT1_IRQHandler             [WEAK]
+                EXPORT  EINT2_IRQHandler             [WEAK]
+                EXPORT  EINT3_IRQHandler             [WEAK]
+                EXPORT  EINT4_IRQHandler             [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler     [WEAK]
+                EXPORT  ADC1_2_IRQHandler            [WEAK]
+                EXPORT  USBD1_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USBD1_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler          [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler          [WEAK]
+                EXPORT  EINT9_5_IRQHandler           [WEAK]
+                EXPORT  TMR1_BRK_IRQHandler          [WEAK]
+                EXPORT  TMR1_UP_IRQHandler           [WEAK]
+                EXPORT  TMR1_TRG_COM_IRQHandler      [WEAK]
+                EXPORT  TMR1_CC_IRQHandler           [WEAK]
+                EXPORT  TMR2_IRQHandler              [WEAK]
+                EXPORT  TMR3_IRQHandler              [WEAK]
+                EXPORT  TMR4_IRQHandler              [WEAK]
+                EXPORT  I2C1_EV_IRQHandler           [WEAK]
+                EXPORT  I2C1_ER_IRQHandler           [WEAK]
+                EXPORT  I2C2_EV_IRQHandler           [WEAK]
+                EXPORT  I2C2_ER_IRQHandler           [WEAK]
+                EXPORT  SPI1_IRQHandler              [WEAK]
+                EXPORT  SPI2_IRQHandler              [WEAK]
+                EXPORT  USART1_IRQHandler            [WEAK]
+                EXPORT  USART2_IRQHandler            [WEAK]
+                EXPORT  USART3_IRQHandler            [WEAK]
+                EXPORT  EINT15_10_IRQHandler         [WEAK]
+                EXPORT  RTCAlarm_IRQHandler          [WEAK]
+                EXPORT  USBDWakeUp_IRQHandler        [WEAK]
+                EXPORT  FPU_IRQHandler               [WEAK]
+                EXPORT  QSPI_IRQHandler              [WEAK]
+                EXPORT  USBD2_HP_IRQHandler          [WEAK]
+                EXPORT  USBD2_LP_IRQHandler          [WEAK]
 
 WWDT_IRQHandler
 PVD_IRQHandler
@@ -351,44 +278,38 @@ FPU_IRQHandler
 QSPI_IRQHandler
 USBD2_HP_IRQHandler
 USBD2_LP_IRQHandler
-B       .
+                B       .
 
-ENDP
+                ENDP
 
-ALIGN
+                ALIGN
 
-;
-*******************************************************************************
-;
-User Stack and Heap initialization
-;
-*******************************************************************************
-IF      :
-DEF:
-__MICROLIB
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
 
-EXPORT  __initial_sp
-EXPORT  __heap_base
-EXPORT  __heap_limit
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
 
-ELSE
+                 ELSE
 
-IMPORT  __use_two_region_memory
-EXPORT  __user_initial_stackheap
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
 
 __user_initial_stackheap
 
-LDR     R0, = Heap_Mem
-              LDR     R1, = (Stack_Mem + Stack_Size)
-                            LDR     R2, = (Heap_Mem  + Heap_Size)
-                                    LDR     R3, = Stack_Mem
-                                            BX      LR
+                 LDR     R0, = Heap_Mem
+                 LDR     R1, = (Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem  + Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
 
-                                            ALIGN
+                 ALIGN
 
-                                            ENDIF
+                 ENDIF
 
-                                            END
+                 END
 
-                                            ;
-*******************************END OF FILE ************************************
+;*******************************END OF FILE************************************

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xx4.ld

@@ -0,0 +1,164 @@
+/*!
+ * @file       gcc_APM32F10xx4.ld
+ *
+ * @brief      Linker script for APM32F10xx4 Device with
+ *             16KByte FLASH, 6KByte RAM
+ *
+ * @version    V1.0.0
+ *
+ * @date       2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Flash Configuration*/
+/* Flash Base Address */
+_rom_base = 0x8000000;
+/*Flash Size (in Bytes) */
+_rom_size = 0x0004000;
+
+/* Embedded RAM Configuration */
+/* RAM Base Address           */
+_ram_base = 0x20000000;
+/* RAM Size (in Bytes) */
+_ram_size = 0x00001800;
+
+/* Stack / Heap Configuration */
+_end_stack = 0x20001800;
+/* Heap Size (in Bytes) */
+_heap_size = 0x200;
+/* Stack Size (in Bytes) */
+_stack_size = 0x400;
+
+MEMORY
+{
+FLASH (rx)      : ORIGIN = _rom_base, LENGTH = _rom_size
+RAM (xrw)       : ORIGIN = _ram_base, LENGTH = _ram_size
+}
+
+SECTIONS
+{
+  .apm32_isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.apm32_isr_vector))
+    . = ALIGN(4);
+  } >FLASH
+
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)
+    *(.text*)
+    *(.glue_7)
+    *(.glue_7t)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;
+  } >FLASH
+
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)
+    *(.rodata*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  _start_address_init_data = LOADADDR(.data);
+
+  .data : 
+  {
+    . = ALIGN(4);
+    _start_address_data = .;
+    *(.data)
+    *(.data*)
+
+    . = ALIGN(4);
+    _end_address_data = .;
+  } >RAM AT> FLASH
+
+  
+  . = ALIGN(4);
+  .bss :
+  {
+
+    _start_address_bss = .;
+    __bss_start__ = _start_address_bss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _end_address_bss = .;
+    __bss_end__ = _end_address_bss;
+  } >RAM
+
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _heap_size;
+    . = . + _stack_size;
+    . = ALIGN(8);
+  } >RAM
+
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xx6.ld

@@ -0,0 +1,164 @@
+/*!
+ * @file       gcc_APM32F10xx6.ld
+ *
+ * @brief      Linker script for APM32F10xx6 Device with
+ *             32KByte FLASH, 10KByte RAM
+ *
+ * @version    V1.0.0
+ *
+ * @date       2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Flash Configuration*/
+/* Flash Base Address */
+_rom_base = 0x8000000;
+/*Flash Size (in Bytes) */
+_rom_size = 0x0008000;
+
+/* Embedded RAM Configuration */
+/* RAM Base Address           */
+_ram_base = 0x20000000;
+/* RAM Size (in Bytes) */
+_ram_size = 0x00002800;
+
+/* Stack / Heap Configuration */
+_end_stack = 0x20002800;
+/* Heap Size (in Bytes) */
+_heap_size = 0x200;
+/* Stack Size (in Bytes) */
+_stack_size = 0x400;
+
+MEMORY
+{
+FLASH (rx)      : ORIGIN = _rom_base, LENGTH = _rom_size
+RAM (xrw)       : ORIGIN = _ram_base, LENGTH = _ram_size
+}
+
+SECTIONS
+{
+  .apm32_isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.apm32_isr_vector))
+    . = ALIGN(4);
+  } >FLASH
+
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)
+    *(.text*)
+    *(.glue_7)
+    *(.glue_7t)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;
+  } >FLASH
+
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)
+    *(.rodata*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  _start_address_init_data = LOADADDR(.data);
+
+  .data : 
+  {
+    . = ALIGN(4);
+    _start_address_data = .;
+    *(.data)
+    *(.data*)
+
+    . = ALIGN(4);
+    _end_address_data = .;
+  } >RAM AT> FLASH
+
+  
+  . = ALIGN(4);
+  .bss :
+  {
+
+    _start_address_bss = .;
+    __bss_start__ = _start_address_bss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _end_address_bss = .;
+    __bss_end__ = _end_address_bss;
+  } >RAM
+
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _heap_size;
+    . = . + _stack_size;
+    . = ALIGN(8);
+  } >RAM
+
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xx8.ld

@@ -0,0 +1,164 @@
+/*!
+ * @file       gcc_APM32F10xx8.ld
+ *
+ * @brief      Linker script for APM32F103xE Device with
+ *             64KByte FLASH, 20KByte RAM
+ *
+ * @version    V1.0.0
+ *
+ * @date       2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Flash Configuration*/
+/* Flash Base Address */
+_rom_base = 0x8000000;
+/*Flash Size (in Bytes) */
+_rom_size = 0x0010000;
+
+/* Embedded RAM Configuration */
+/* RAM Base Address           */
+_ram_base = 0x20000000;
+/* RAM Size (in Bytes) */
+_ram_size = 0x00005000;
+
+/* Stack / Heap Configuration */
+_end_stack = 0x20005000;
+/* Heap Size (in Bytes) */
+_heap_size = 0x200;
+/* Stack Size (in Bytes) */
+_stack_size = 0x400;
+
+MEMORY
+{
+FLASH (rx)      : ORIGIN = _rom_base, LENGTH = _rom_size
+RAM (xrw)       : ORIGIN = _ram_base, LENGTH = _ram_size
+}
+
+SECTIONS
+{
+  .apm32_isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.apm32_isr_vector))
+    . = ALIGN(4);
+  } >FLASH
+
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)
+    *(.text*)
+    *(.glue_7)
+    *(.glue_7t)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;
+  } >FLASH
+
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)
+    *(.rodata*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  _start_address_init_data = LOADADDR(.data);
+
+  .data : 
+  {
+    . = ALIGN(4);
+    _start_address_data = .;
+    *(.data)
+    *(.data*)
+
+    . = ALIGN(4);
+    _end_address_data = .;
+  } >RAM AT> FLASH
+
+  
+  . = ALIGN(4);
+  .bss :
+  {
+
+    _start_address_bss = .;
+    __bss_start__ = _start_address_bss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _end_address_bss = .;
+    __bss_end__ = _end_address_bss;
+  } >RAM
+
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _heap_size;
+    . = . + _stack_size;
+    . = ALIGN(8);
+  } >RAM
+
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxB.ld

@@ -0,0 +1,164 @@
+/*!
+ * @file       gcc_APM32F10xxB.ld
+ *
+ * @brief      Linker script for APM32F10xxB Device with
+ *             128KByte FLASH, 20KByte RAM
+ *
+ * @version    V1.0.0
+ *
+ * @date       2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Flash Configuration*/
+/* Flash Base Address */
+_rom_base = 0x8000000;
+/*Flash Size (in Bytes) */
+_rom_size = 0x0020000;
+
+/* Embedded RAM Configuration */
+/* RAM Base Address           */
+_ram_base = 0x20000000;
+/* RAM Size (in Bytes) */
+_ram_size = 0x00005000;
+
+/* Stack / Heap Configuration */
+_end_stack = 0x20005000;
+/* Heap Size (in Bytes) */
+_heap_size = 0x200;
+/* Stack Size (in Bytes) */
+_stack_size = 0x400;
+
+MEMORY
+{
+FLASH (rx)      : ORIGIN = _rom_base, LENGTH = _rom_size
+RAM (xrw)       : ORIGIN = _ram_base, LENGTH = _ram_size
+}
+
+SECTIONS
+{
+  .apm32_isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.apm32_isr_vector))
+    . = ALIGN(4);
+  } >FLASH
+
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)
+    *(.text*)
+    *(.glue_7)
+    *(.glue_7t)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;
+  } >FLASH
+
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)
+    *(.rodata*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  _start_address_init_data = LOADADDR(.data);
+
+  .data : 
+  {
+    . = ALIGN(4);
+    _start_address_data = .;
+    *(.data)
+    *(.data*)
+
+    . = ALIGN(4);
+    _end_address_data = .;
+  } >RAM AT> FLASH
+
+  
+  . = ALIGN(4);
+  .bss :
+  {
+
+    _start_address_bss = .;
+    __bss_start__ = _start_address_bss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _end_address_bss = .;
+    __bss_end__ = _end_address_bss;
+  } >RAM
+
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _heap_size;
+    . = . + _stack_size;
+    . = ALIGN(8);
+  } >RAM
+
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxC.ld

@@ -0,0 +1,164 @@
+/*!
+ * @file       gcc_APM32F10xxC.ld
+ *
+ * @brief      Linker script for APM32F10xxC Device with
+ *             256KByte FLASH, 64KByte RAM
+ *
+ * @version    V1.0.0
+ *
+ * @date       2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Flash Configuration*/
+/* Flash Base Address */
+_rom_base = 0x8000000;
+/*Flash Size (in Bytes) */
+_rom_size = 0x0040000;
+
+/* Embedded RAM Configuration */
+/* RAM Base Address           */
+_ram_base = 0x20000000;
+/* RAM Size (in Bytes) */
+_ram_size = 0x00010000;
+
+/* Stack / Heap Configuration */
+_end_stack = 0x20010000;
+/* Heap Size (in Bytes) */
+_heap_size = 0x200;
+/* Stack Size (in Bytes) */
+_stack_size = 0x400;
+
+MEMORY
+{
+FLASH (rx)      : ORIGIN = _rom_base, LENGTH = _rom_size
+RAM (xrw)       : ORIGIN = _ram_base, LENGTH = _ram_size
+}
+
+SECTIONS
+{
+  .apm32_isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.apm32_isr_vector))
+    . = ALIGN(4);
+  } >FLASH
+
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)
+    *(.text*)
+    *(.glue_7)
+    *(.glue_7t)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;
+  } >FLASH
+
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)
+    *(.rodata*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  _start_address_init_data = LOADADDR(.data);
+
+  .data : 
+  {
+    . = ALIGN(4);
+    _start_address_data = .;
+    *(.data)
+    *(.data*)
+
+    . = ALIGN(4);
+    _end_address_data = .;
+  } >RAM AT> FLASH
+
+  
+  . = ALIGN(4);
+  .bss :
+  {
+
+    _start_address_bss = .;
+    __bss_start__ = _start_address_bss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _end_address_bss = .;
+    __bss_end__ = _end_address_bss;
+  } >RAM
+
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _heap_size;
+    . = . + _stack_size;
+    . = ALIGN(8);
+  } >RAM
+
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxD.ld

@@ -0,0 +1,164 @@
+/*!
+ * @file       gcc_APM32F10xxD.ld
+ *
+ * @brief      Linker script for APM32F10xxD Device with
+ *             384KByte FLASH, 64KByte RAM
+ *
+ * @version    V1.0.0
+ *
+ * @date       2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Flash Configuration*/
+/* Flash Base Address */
+_rom_base = 0x8000000;
+/*Flash Size (in Bytes) */
+_rom_size = 0x0080000;
+
+/* Embedded RAM Configuration */
+/* RAM Base Address           */
+_ram_base = 0x20000000;
+/* RAM Size (in Bytes) */
+_ram_size = 0x00010000;
+
+/* Stack / Heap Configuration */
+_end_stack = 0x20010000;
+/* Heap Size (in Bytes) */
+_heap_size = 0x200;
+/* Stack Size (in Bytes) */
+_stack_size = 0x400;
+
+MEMORY
+{
+FLASH (rx)      : ORIGIN = _rom_base, LENGTH = _rom_size
+RAM (xrw)       : ORIGIN = _ram_base, LENGTH = _ram_size
+}
+
+SECTIONS
+{
+  .apm32_isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.apm32_isr_vector))
+    . = ALIGN(4);
+  } >FLASH
+
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)
+    *(.text*)
+    *(.glue_7)
+    *(.glue_7t)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;
+  } >FLASH
+
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)
+    *(.rodata*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  _start_address_init_data = LOADADDR(.data);
+
+  .data : 
+  {
+    . = ALIGN(4);
+    _start_address_data = .;
+    *(.data)
+    *(.data*)
+
+    . = ALIGN(4);
+    _end_address_data = .;
+  } >RAM AT> FLASH
+
+  
+  . = ALIGN(4);
+  .bss :
+  {
+
+    _start_address_bss = .;
+    __bss_start__ = _start_address_bss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _end_address_bss = .;
+    __bss_end__ = _end_address_bss;
+  } >RAM
+
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _heap_size;
+    . = . + _stack_size;
+    . = ALIGN(8);
+  } >RAM
+
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/gcc_APM32F10xxE.ld

@@ -0,0 +1,164 @@
+/*!
+ * @file       gcc_APM32F10xxE.ld
+ *
+ * @brief      Linker script for APM32F10xxE Device with
+ *             512KByte FLASH, 128KByte RAM
+ *
+ * @version    V1.0.0
+ *
+ * @date       2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Flash Configuration*/
+/* Flash Base Address */
+_rom_base = 0x8000000;
+/*Flash Size (in Bytes) */
+_rom_size = 0x0080000;
+
+/* Embedded RAM Configuration */
+/* RAM Base Address           */
+_ram_base = 0x20000000;
+/* RAM Size (in Bytes) */
+_ram_size = 0x00020000;
+
+/* Stack / Heap Configuration */
+_end_stack = 0x20020000;
+/* Heap Size (in Bytes) */
+_heap_size = 0x200;
+/* Stack Size (in Bytes) */
+_stack_size = 0x400;
+
+MEMORY
+{
+FLASH (rx)      : ORIGIN = _rom_base, LENGTH = _rom_size
+RAM (xrw)       : ORIGIN = _ram_base, LENGTH = _ram_size
+}
+
+SECTIONS
+{
+  .apm32_isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.apm32_isr_vector))
+    . = ALIGN(4);
+  } >FLASH
+
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)
+    *(.text*)
+    *(.glue_7)
+    *(.glue_7t)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;
+  } >FLASH
+
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)
+    *(.rodata*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  _start_address_init_data = LOADADDR(.data);
+
+  .data : 
+  {
+    . = ALIGN(4);
+    _start_address_data = .;
+    *(.data)
+    *(.data*)
+
+    . = ALIGN(4);
+    _end_address_data = .;
+  } >RAM AT> FLASH
+
+  
+  . = ALIGN(4);
+  .bss :
+  {
+
+    _start_address_bss = .;
+    __bss_start__ = _start_address_bss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _end_address_bss = .;
+    __bss_end__ = _end_address_bss;
+  } >RAM
+
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _heap_size;
+    . = . + _stack_size;
+    . = ALIGN(8);
+  } >RAM
+
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_cl.S

@@ -0,0 +1,397 @@
+/*!
+ * @file       startup_apm32f103_hd.S
+ *
+ * @brief      CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f103_hd
+ *
+ * @version    V1.0.1
+ *
+ * @date       2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global g_apm32_Vectors
+.global Default_Handler
+
+.word _start_address_init_data
+.word _start_address_data
+.word _end_address_data
+.word _start_address_bss
+.word _end_address_bss
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+// Reset handler routine
+Reset_Handler:
+
+  ldr r0, =_start_address_data
+  ldr r1, =_end_address_data
+  ldr r2, =_start_address_init_data
+  movs r3, #0
+  b L_loop0_0
+
+L_loop0:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+L_loop0_0:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc L_loop0
+  
+  ldr r2, =_start_address_bss
+  ldr r4, =_end_address_bss
+  movs r3, #0
+  b L_loop1
+
+L_loop2:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+L_loop1:
+  cmp r2, r4
+  bcc L_loop2
+
+    bl  SystemInit
+    bl __libc_init_array
+  bl entry
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+// This is the code that gets called when the processor receives an unexpected interrupt.
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+L_Loop_infinite:
+  b L_Loop_infinite
+  .size Default_Handler, .-Default_Handler
+
+// The minimal vector table for a Cortex M3.
+   .section .isr_vector,"a",%progbits
+  .type g_apm32_Vectors, %object
+  .size g_apm32_Vectors, .-g_apm32_Vectors
+
+// Vector Table Mapped to Address 0 at Reset
+g_apm32_Vectors:
+
+  .word _end_stack                          // Top of Stack
+  .word Reset_Handler                       // Reset Handler
+  .word NMI_Handler                         // NMI Handler
+  .word HardFault_Handler                   // Hard Fault Handler
+  .word MemManage_Handler                   // MPU Fault Handler
+  .word BusFault_Handler                    // Bus Fault Handler
+  .word UsageFault_Handler                  // Usage Fault Handler
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word SVC_Handler                         // SVCall Handler
+  .word DebugMon_Handler                    // Debug Monitor Handler
+  .word 0                                   // Reserved
+  .word PendSV_Handler                      // PendSV Handler
+  .word SysTick_Handler                     // SysTick Handler
+  .word WWDT_IRQHandler                     // Window Watchdog
+  .word PVD_IRQHandler                      // PVD through EINT Line detect
+  .word TAMPER_IRQHandler                   // Tamper
+  .word RTC_IRQHandler                      // RTC
+  .word FLASH_IRQHandler                    // Flash
+  .word RCM_IRQHandler                      // RCM
+  .word EINT0_IRQHandler                    // EINT Line 0
+  .word EINT1_IRQHandler                    // EINT Line 1
+  .word EINT2_IRQHandler                    // EINT Line 2
+  .word EINT3_IRQHandler                    // EINT Line 3
+  .word EINT4_IRQHandler                    // EINT Line 4
+  .word DMA1_Channel1_IRQHandler            // DMA1 Channel 1
+  .word DMA1_Channel2_IRQHandler            // DMA1 Channel 2
+  .word DMA1_Channel3_IRQHandler            // DMA1 Channel 3
+  .word DMA1_Channel4_IRQHandler            // DMA1 Channel 4
+  .word DMA1_Channel5_IRQHandler            // DMA1 Channel 5
+  .word DMA1_Channel6_IRQHandler            // DMA1 Channel 6
+  .word DMA1_Channel7_IRQHandler            // DMA1 Channel 7
+  .word ADC1_2_IRQHandler                   // ADC1 & ADC2
+  .word CAN1_TX_IRQHandler                  // CAN1 TX
+  .word CAN1_RX0_IRQHandler                 // CAN1 RX0
+  .word CAN1_RX1_IRQHandler                 // CAN1 RX1
+  .word CAN1_SCE_IRQHandler                 // CAN1 SCE
+  .word EINT9_5_IRQHandler                  // EINT Line 9..5
+  .word TMR1_BRK_IRQHandler                 // TMR1 Break
+  .word TMR1_UP_IRQHandler                  // TMR1 Update
+  .word TMR1_TRG_COM_IRQHandler             // TMR1 Trigger and Commutation
+  .word TMR1_CC_IRQHandler                  // TMR1 Capture Compare
+  .word TMR2_IRQHandler                     // TMR2
+  .word TMR3_IRQHandler                     // TMR3
+  .word TMR4_IRQHandler                     // TMR4
+  .word I2C1_EV_IRQHandler                  // I2C1 Event
+  .word I2C1_ER_IRQHandler                  // I2C1 Error
+  .word I2C2_EV_IRQHandler                  // I2C2 Event
+  .word I2C2_ER_IRQHandler                  // I2C2 Error
+  .word SPI1_IRQHandler                     // SPI1
+  .word SPI2_IRQHandler                     // SPI2
+  .word USART1_IRQHandler                   // USART1
+  .word USART2_IRQHandler                   // USART2
+  .word USART3_IRQHandler                   // USART3
+  .word EINT15_10_IRQHandler                // EINT Line 15..10
+  .word RTCAlarm_IRQHandler                 // RTC Alarm through EINT Line
+  .word OTG_FS_WKUP_IRQHandler              // USBD Wakeup from suspend
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word TMR5_IRQHandler                     // TMR5
+  .word SPI3_IRQHandler                     // SPI3
+  .word UART4_IRQHandler                    // UART4
+  .word UART5_IRQHandler                    // UART5
+  .word TMR6_IRQHandler                     // TMR6
+  .word TMR7_IRQHandler                     // TMR7
+  .word DMA2_Channel1_IRQHandler            // DMA2 Channel1
+  .word DMA2_Channel2_IRQHandler            // DMA2 Channel2
+  .word DMA2_Channel3_IRQHandler            // DMA2 Channel3
+  .word DMA2_Channel4_IRQHandler            // DMA2 Channel4
+  .word DMA2_Channel5_IRQHandler            // DMA2 Channel5
+  .word ETH_IRQHandler                      // ETH
+  .word ETH_WKUP_IRQHandler                 // ETH Wake up
+  .word CAN2_TX_IRQHandler                  // CAN2 TX
+  .word CAN2_RX0_IRQHandler                 // CAN2 RX0
+  .word CAN2_RX1_IRQHandler                 // CAN2 RX1
+  .word CAN2_SCE_IRQHandler                 // CAN2 SCE
+  .word OTG_FS_IRQHandler                   // OTG FS
+
+// Default exception/interrupt handler
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WWDT_IRQHandler
+  .thumb_set WWDT_IRQHandler,Default_Handler
+
+  .weak PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak TAMPER_IRQHandler
+  .thumb_set TAMPER_IRQHandler,Default_Handler
+
+  .weak RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak RCM_IRQHandler
+  .thumb_set RCM_IRQHandler,Default_Handler
+
+  .weak EINT0_IRQHandler
+  .thumb_set EINT0_IRQHandler,Default_Handler
+
+  .weak EINT1_IRQHandler
+  .thumb_set EINT1_IRQHandler,Default_Handler
+
+  .weak EINT2_IRQHandler
+  .thumb_set EINT2_IRQHandler,Default_Handler
+
+  .weak EINT3_IRQHandler
+  .thumb_set EINT3_IRQHandler,Default_Handler
+
+  .weak EINT4_IRQHandler
+  .thumb_set EINT4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak ADC1_2_IRQHandler
+  .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+  .weak USBD_HP_CAN1_TX_IRQHandler
+  .thumb_set USBD_HP_CAN1_TX_IRQHandler,Default_Handler
+
+  .weak USBD_LP_CAN1_RX0_IRQHandler
+  .thumb_set USBD_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+  .weak CAN1_TX_IRQHandler
+  .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+  .weak CAN1_RX0_IRQHandler
+  .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+  .weak CAN1_RX1_IRQHandler
+  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+  .weak CAN1_SCE_IRQHandler
+  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+  .weak EINT9_5_IRQHandler
+  .thumb_set EINT9_5_IRQHandler,Default_Handler
+
+  .weak TMR1_BRK_IRQHandler
+  .thumb_set TMR1_BRK_IRQHandler,Default_Handler
+
+  .weak TMR1_UP_IRQHandler
+  .thumb_set TMR1_UP_IRQHandler,Default_Handler
+
+  .weak TMR1_TRG_COM_IRQHandler
+  .thumb_set TMR1_TRG_COM_IRQHandler,Default_Handler
+
+  .weak TMR1_CC_IRQHandler
+  .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+  .weak TMR2_IRQHandler
+  .thumb_set TMR2_IRQHandler,Default_Handler
+
+  .weak TMR3_IRQHandler
+  .thumb_set TMR3_IRQHandler,Default_Handler
+
+  .weak TMR4_IRQHandler
+  .thumb_set TMR4_IRQHandler,Default_Handler
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak EINT15_10_IRQHandler
+  .thumb_set EINT15_10_IRQHandler,Default_Handler
+
+  .weak RTCAlarm_IRQHandler
+  .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+  .weak OTG_FS_WKUP_IRQHandler
+  .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+  .weak TMR5_IRQHandler
+  .thumb_set TMR5_IRQHandler,Default_Handler
+
+  .weak SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak UART5_IRQHandler
+  .thumb_set UART5_IRQHandler,Default_Handler
+
+  .weak TMR6_IRQHandler
+  .thumb_set TMR6_IRQHandler,Default_Handler
+
+  .weak TMR7_IRQHandler
+  .thumb_set TMR7_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak ETH_IRQHandler
+  .thumb_set ETH_IRQHandler,Default_Handler
+
+  .weak ETH_WKUP_IRQHandler
+  .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+  .weak CAN2_TX_IRQHandler
+  .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+  .weak CAN2_RX0_IRQHandler
+  .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+  .weak CAN2_RX1_IRQHandler
+  .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+  .weak CAN2_SCE_IRQHandler
+  .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+  .weak OTG_FS_IRQHandler
+  .thumb_set OTG_FS_IRQHandler,Default_Handler

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s

@@ -1,281 +1,398 @@
-;/*!
-; * @file        startup_apm32f10x_hd.s
-; *
-; * @brief       CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
-; *
-; * @version     V1.0.0
-; *
-; * @date        2022-01-05
-; *
-; * @attention
-; *
-; *  Copyright (C) 2020-2022 Geehy Semiconductor
-; *
-; *  You may not use this file except in compliance with the
-; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
-; *
-; *  The program is only for reference, which is distributed in the hope
-; *  that it will be usefull and instructional for customers to develop
-; *  their software. Unless required by applicable law or agreed to in
-; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
-; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
-; *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
-; *  and limitations under the License.
-; */
-
-.syntax unified
-.cpu cortex - m3
-.fpu softvfp
-.thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-.section  .isr_vector, "a", % progbits
-.type  g_pfnVectors, % object
-
-g_pfnVectors:
-.word     _estack                           // Top of Stack
-.word     Reset_Handler                     // Reset Handler
-.word     NMI_Handler                       // NMI Handler
-.word     HardFault_Handler                 // Hard Fault Handler
-.word     MemManage_Handler                 // MPU Fault Handler
-.word     BusFault_Handler                  // Bus Fault Handler
-.word     UsageFault_Handler                // Usage Fault Handler
-.word     0                                 // Reserved
-.word     0                                 // Reserved
-.word     0                                 // Reserved
-.word     0                                 // Reserved
-.word     SVC_Handler                       // SVCall Handler
-.word     DebugMon_Handler                  // Debug Monitor Handler
-.word     0                                 // Reserved
-.word     PendSV_Handler                    // PendSV Handler
-.word     SysTick_Handler                   // SysTick Handler
-
-// external interrupts handler
-.word     WWDT_IRQHandler                    // Window Watchdog
-.word     PVD_IRQHandler                     // PVD through EINT Line detect
-.word     TAMPER_IRQHandler                  // Tamper
-.word     RTC_IRQHandler                     // RTC
-.word     FLASH_IRQHandler                   // Flash
-.word     RCM_IRQHandler                     // RCM
-.word     EINT0_IRQHandler                   // EINT Line 0
-.word     EINT1_IRQHandler                   // EINT Line 1
-.word     EINT2_IRQHandler                   // EINT Line 2
-.word     EINT3_IRQHandler                   // EINT Line 3
-.word     EINT4_IRQHandler                   // EINT Line 4
-.word     DMA1_Channel1_IRQHandler           // DMA1 Channel 1
-.word     DMA1_Channel2_IRQHandler           // DMA1 Channel 2
-.word     DMA1_Channel3_IRQHandler           // DMA1 Channel 3
-.word     DMA1_Channel4_IRQHandler           // DMA1 Channel 4
-.word     DMA1_Channel5_IRQHandler           // DMA1 Channel 5
-.word     DMA1_Channel6_IRQHandler           // DMA1 Channel 6
-.word     DMA1_Channel7_IRQHandler           // DMA1 Channel 7
-.word     ADC1_2_IRQHandler                  // ADC1 & ADC2
-.word     USBD1_HP_CAN1_TX_IRQHandler        // USBD1 High Priority or CAN1 TX
-.word     USBD1_LP_CAN1_RX0_IRQHandler       // USBD1 Low  Priority or CAN1 RX0
-.word     CAN1_RX1_IRQHandler                // CAN1 RX1
-.word     CAN1_SCE_IRQHandler                // CAN1 SCE
-.word     EINT9_5_IRQHandler                 // EINT Line 9..5
-.word     TMR1_BRK_IRQHandler                // TMR1 Break
-.word     TMR1_UP_IRQHandler                 // TMR1 Update
-.word     TMR1_TRG_COM_IRQHandler            // TMR1 Trigger and Commutation
-.word     TMR1_CC_IRQHandler                 // TMR1 Capture Compare
-.word     TMR2_IRQHandler                    // TMR2
-.word     TMR3_IRQHandler                    // TMR3
-.word     TMR4_IRQHandler                    // TMR4
-.word     I2C1_EV_IRQHandler                 // I2C1 Event
-.word     I2C1_ER_IRQHandler                 // I2C1 Error
-.word     I2C2_EV_IRQHandler                 // I2C2 Event
-.word     I2C2_ER_IRQHandler                 // I2C2 Error
-.word     SPI1_IRQHandler                    // SPI1
-.word     SPI2_IRQHandler                    // SPI2
-.word     USART1_IRQHandler                  // USART1
-.word     USART2_IRQHandler                  // USART2
-.word     USART3_IRQHandler                  // USART3
-.word     EINT15_10_IRQHandler               // EINT Line 15..10
-.word     RTCAlarm_IRQHandler                // RTC Alarm through EINT Line
-.word     USBDWakeUp_IRQHandler              // USBD Wakeup from suspend
-.word     TMR8_BRK_IRQHandler                // TMR8 Break
-.word     TMR8_UP_IRQHandler                 // TMR8 Update
-.word     TMR8_TRG_COM_IRQHandler            // TMR8 Trigger and Commutation
-.word     TMR8_CC_IRQHandler                 // TMR8 Capture Compare
-.word     ADC3_IRQHandler                    // ADC3
-.word     EMMC_IRQHandler                    // EMMC
-.word     SDIO_IRQHandler                    // SDIO
-.word     TMR5_IRQHandler                    // TMR5
-.word     SPI3_IRQHandler                    // SPI3
-.word     UART4_IRQHandler                   // UART4
-.word     UART5_IRQHandler                   // UART5
-.word     TMR6_IRQHandler                    // TMR6
-.word     TMR7_IRQHandler                    // TMR7
-.word     DMA2_Channel1_IRQHandler           // DMA2 Channel1
-.word     DMA2_Channel2_IRQHandler           // DMA2 Channel2
-.word     DMA2_Channel3_IRQHandler           // DMA2 Channel3
-.word     DMA2_Channel4_5_IRQHandler         // DMA2 Channel4 & Channel5
-.word     0                                  // Reserved
-.word     USBD2_HP_CAN2_TX_IRQHandler        // USBD2 High Priority or CAN2 TX
-.word     USBD2_LP_CAN2_RX0_IRQHandler       // USBD2 Low  Priority or CAN2 RX0
-.word     CAN2_RX1_IRQHandler                // CAN2 RX1
-.word     CAN2_SCE_IRQHandler                // CAN2 SCE
-
-.size  g_pfnVectors, . - g_pfnVectors
-
-.section  .text.Reset_Handler
-.weak  Reset_Handler
-.type  Reset_Handler, % function
+/*!
+ * @file       startup_apm32f103_hd.S
+ *
+ * @brief      CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f103_hd
+ *
+ * @version    V1.0.1
+ *
+ * @date       2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global g_apm32_Vectors
+.global Default_Handler
+
+.word _start_address_init_data
+.word _start_address_data
+.word _end_address_data
+.word _start_address_bss
+.word _end_address_bss
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+// Reset handler routine
 Reset_Handler:
-ldr r1, = _sidata
-          ldr r2, = _sdata
-                    ldr r3, = _edata
-
-                              subs r3, r2
-                              ble fill_bss_start
-
-                              loop_copy_data:
-                              subs r3, #4
-                              ldr r0, [r1, r3]
-                              str r0, [r2, r3]
-                              bgt loop_copy_data
-
-                              fill_bss_start:
-                              ldr r1, = __bss_start
-                                        ldr r2, = __bss_end
-                                                movs r0, 0
-                                                subs r2, r1
-                                                ble startup_enter
-
-                                                loop_fill_bss:
-                                                subs r2, #4
-                                                str r0, [r1, r2]
-                                                bgt loop_fill_bss
-
-                                                startup_enter:
-                                                bl SystemInit
-                                                bl entry
-
-                                                /* Exception Handlers */
-                                                .weak   NMI_Handler
-                                                .type   NMI_Handler, % function
-                                                NMI_Handler:
-                                                b       .
-                                                .size   NMI_Handler, . - NMI_Handler
-
-                                                .weak   MemManage_Handler
-                                                .type   MemManage_Handler, % function
-                                                MemManage_Handler:
-                                                b       .
-                                                .size   MemManage_Handler, . - MemManage_Handler
-
-                                                .weak   BusFault_Handler
-                                                .type   BusFault_Handler, % function
-                                                BusFault_Handler:
-                                                b       .
-                                                .size   BusFault_Handler, . - BusFault_Handler
-
-                                                .weak   UsageFault_Handler
-                                                .type   UsageFault_Handler, % function
-                                                UsageFault_Handler:
-                                                b       .
-                                                .size   UsageFault_Handler, . - UsageFault_Handler
-
-                                                .weak   SVC_Handler
-                                                .type   SVC_Handler, % function
-                                                SVC_Handler:
-                                                b       .
-                                                .size   SVC_Handler, . - SVC_Handler
-
-                                                .weak   DebugMon_Handler
-                                                .type   DebugMon_Handler, % function
-                                                DebugMon_Handler:
-                                                b       .
-                                                .size   DebugMon_Handler, . - DebugMon_Handler
-
-                                                .weak   PendSV_Handler
-                                                .type   PendSV_Handler, % function
-                                                PendSV_Handler:
-                                                b       .
-                                                .size   PendSV_Handler, . - PendSV_Handler
-
-                                                .weak   SysTick_Handler
-                                                .type   SysTick_Handler, % function
-                                                SysTick_Handler:
-                                                b       .
-                                                .size   SysTick_Handler, . - SysTick_Handler
-
-                                                /* IQR Handler */
-                                                .section  .text.Default_Handler, "ax", % progbits
-                                                .type  Default_Handler, % function
-                                                Default_Handler:
-                                                b  .
-                                                .size  Default_Handler, . - Default_Handler
-
-                                                .macro  IRQ handler
-                                                .weak   \handler
-                                                .set    \handler, Default_Handler
-                                                .endm
-
-                                                IRQ WWDT_IRQHandler
-                                                IRQ PVD_IRQHandler
-                                                IRQ TAMPER_IRQHandler
-                                                IRQ RTC_IRQHandler
-                                                IRQ FLASH_IRQHandler
-                                                IRQ RCM_IRQHandler
-                                                IRQ EINT0_IRQHandler
-                                                IRQ EINT1_IRQHandler
-                                                IRQ EINT2_IRQHandler
-                                                IRQ EINT3_IRQHandler
-                                                IRQ EINT4_IRQHandler
-                                                IRQ DMA1_Channel1_IRQHandler
-                                                IRQ DMA1_Channel2_IRQHandler
-                                                IRQ DMA1_Channel3_IRQHandler
-                                                IRQ DMA1_Channel4_IRQHandler
-                                                IRQ DMA1_Channel5_IRQHandler
-                                                IRQ DMA1_Channel6_IRQHandler
-                                                IRQ DMA1_Channel7_IRQHandler
-                                                IRQ ADC1_2_IRQHandler
-                                                IRQ USBD1_HP_CAN1_TX_IRQHandler
-                                                IRQ USBD1_LP_CAN1_RX0_IRQHandler
-                                                IRQ CAN1_RX1_IRQHandler
-                                                IRQ CAN1_SCE_IRQHandler
-                                                IRQ EINT9_5_IRQHandler
-                                                IRQ TMR1_BRK_IRQHandler
-                                                IRQ TMR1_UP_IRQHandler
-                                                IRQ TMR1_TRG_COM_IRQHandler
-                                                IRQ TMR1_CC_IRQHandler
-                                                IRQ TMR2_IRQHandler
-                                                IRQ TMR3_IRQHandler
-                                                IRQ TMR4_IRQHandler
-                                                IRQ I2C1_EV_IRQHandler
-                                                IRQ I2C1_ER_IRQHandler
-                                                IRQ I2C2_EV_IRQHandler
-                                                IRQ I2C2_ER_IRQHandler
-                                                IRQ SPI1_IRQHandler
-                                                IRQ SPI2_IRQHandler
-                                                IRQ USART1_IRQHandler
-                                                IRQ USART2_IRQHandler
-                                                IRQ USART3_IRQHandler
-                                                IRQ EINT15_10_IRQHandler
-                                                IRQ RTCAlarm_IRQHandler
-                                                IRQ USBDWakeUp_IRQHandler
-                                                IRQ TMR8_BRK_IRQHandler
-                                                IRQ TMR8_UP_IRQHandler
-                                                IRQ TMR8_TRG_COM_IRQHandler
-                                                IRQ TMR8_CC_IRQHandler
-                                                IRQ ADC3_IRQHandler
-                                                IRQ EMMC_IRQHandler
-                                                IRQ SDIO_IRQHandler
-                                                IRQ TMR5_IRQHandler
-                                                IRQ SPI3_IRQHandler
-                                                IRQ UART4_IRQHandler
-                                                IRQ UART5_IRQHandler
-                                                IRQ TMR6_IRQHandler
-                                                IRQ TMR7_IRQHandler
-                                                IRQ DMA2_Channel1_IRQHandler
-                                                IRQ DMA2_Channel2_IRQHandler
-                                                IRQ DMA2_Channel3_IRQHandler
-                                                IRQ DMA2_Channel4_5_IRQHandler
-                                                IRQ USBD2_HP_CAN2_TX_IRQHandler
-                                                IRQ USBD2_LP_CAN2_RX0_IRQHandler
-                                                IRQ CAN2_RX1_IRQHandler
-                                                IRQ CAN2_SCE_IRQHandler
+
+  ldr r0, =_start_address_data
+  ldr r1, =_end_address_data
+  ldr r2, =_start_address_init_data
+  movs r3, #0
+  b L_loop0_0
+
+L_loop0:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+L_loop0_0:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc L_loop0
+  
+  ldr r2, =_start_address_bss
+  ldr r4, =_end_address_bss
+  movs r3, #0
+  b L_loop1
+
+L_loop2:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+L_loop1:
+  cmp r2, r4
+  bcc L_loop2
+
+  bl  SystemInit
+  bl __libc_init_array
+  bl entry
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+// This is the code that gets called when the processor receives an unexpected interrupt.
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+L_Loop_infinite:
+  b L_Loop_infinite
+  .size Default_Handler, .-Default_Handler
+
+// The minimal vector table for a Cortex M3.
+   .section .isr_vector,"a",%progbits
+  .type g_apm32_Vectors, %object
+  .size g_apm32_Vectors, .-g_apm32_Vectors
+
+// Vector Table Mapped to Address 0 at Reset
+g_apm32_Vectors:
+
+  .word _end_stack                          // Top of Stack
+  .word Reset_Handler                       // Reset Handler
+  .word NMI_Handler                         // NMI Handler
+  .word HardFault_Handler                   // Hard Fault Handler
+  .word MemManage_Handler                   // MPU Fault Handler
+  .word BusFault_Handler                    // Bus Fault Handler
+  .word UsageFault_Handler                  // Usage Fault Handler
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word SVC_Handler                         // SVCall Handler
+  .word DebugMon_Handler                    // Debug Monitor Handler
+  .word 0                                   // Reserved
+  .word PendSV_Handler                      // PendSV Handler
+  .word SysTick_Handler                     // SysTick Handler
+  .word WWDT_IRQHandler                     // Window Watchdog
+  .word PVD_IRQHandler                      // PVD through EINT Line detect
+  .word TAMPER_IRQHandler                   // Tamper
+  .word RTC_IRQHandler                      // RTC
+  .word FLASH_IRQHandler                    // Flash
+  .word RCM_IRQHandler                      // RCM
+  .word EINT0_IRQHandler                    // EINT Line 0
+  .word EINT1_IRQHandler                    // EINT Line 1
+  .word EINT2_IRQHandler                    // EINT Line 2
+  .word EINT3_IRQHandler                    // EINT Line 3
+  .word EINT4_IRQHandler                    // EINT Line 4
+  .word DMA1_Channel1_IRQHandler            // DMA1 Channel 1
+  .word DMA1_Channel2_IRQHandler            // DMA1 Channel 2
+  .word DMA1_Channel3_IRQHandler            // DMA1 Channel 3
+  .word DMA1_Channel4_IRQHandler            // DMA1 Channel 4
+  .word DMA1_Channel5_IRQHandler            // DMA1 Channel 5
+  .word DMA1_Channel6_IRQHandler            // DMA1 Channel 6
+  .word DMA1_Channel7_IRQHandler            // DMA1 Channel 7
+  .word ADC1_2_IRQHandler                   // ADC1 & ADC2
+  .word USBD1_HP_CAN1_TX_IRQHandler          // USBD1 High Priority or CAN1 TX
+  .word USBD1_LP_CAN1_RX0_IRQHandler         // USBD1 Low  Priority or CAN1 RX0
+  .word CAN1_RX1_IRQHandler                 // CAN1 RX1
+  .word CAN1_SCE_IRQHandler                 // CAN1 SCE
+  .word EINT9_5_IRQHandler                  // EINT Line 9..5
+  .word TMR1_BRK_IRQHandler                 // TMR1 Break
+  .word TMR1_UP_IRQHandler                  // TMR1 Update
+  .word TMR1_TRG_COM_IRQHandler             // TMR1 Trigger and Commutation
+  .word TMR1_CC_IRQHandler                  // TMR1 Capture Compare
+  .word TMR2_IRQHandler                     // TMR2
+  .word TMR3_IRQHandler                     // TMR3
+  .word TMR4_IRQHandler                     // TMR4
+  .word I2C1_EV_IRQHandler                  // I2C1 Event
+  .word I2C1_ER_IRQHandler                  // I2C1 Error
+  .word I2C2_EV_IRQHandler                  // I2C2 Event
+  .word I2C2_ER_IRQHandler                  // I2C2 Error
+  .word SPI1_IRQHandler                     // SPI1
+  .word SPI2_IRQHandler                     // SPI2
+  .word USART1_IRQHandler                   // USART1
+  .word USART2_IRQHandler                   // USART2
+  .word USART3_IRQHandler                   // USART3
+  .word EINT15_10_IRQHandler                // EINT Line 15..10
+  .word RTCAlarm_IRQHandler                // RTC Alarm through EINT Line
+  .word USBDWakeUp_IRQHandler               // USBD Wakeup from suspend
+  .word TMR8_BRK_IRQHandler                 // TMR8 Break
+  .word TMR8_UP_IRQHandler                  // TMR8 Update
+  .word TMR8_TRG_COM_IRQHandler             // TMR8 Trigger and Commutation
+  .word TMR8_CC_IRQHandler                  // TMR8 Capture Compare
+  .word ADC3_IRQHandler                     // ADC3
+  .word FSMC_IRQHandler                     // EMMC
+  .word SDIO_IRQHandler                     // SDIO
+  .word TMR5_IRQHandler                     // TMR5
+  .word SPI3_IRQHandler                     // SPI3
+  .word UART4_IRQHandler                    // UART4
+  .word UART5_IRQHandler                    // UART5
+  .word TMR6_IRQHandler                     // TMR6
+  .word TMR7_IRQHandler                     // TMR7
+  .word DMA2_Channel1_IRQHandler            // DMA2 Channel1
+  .word DMA2_Channel2_IRQHandler            // DMA2 Channel2
+  .word DMA2_Channel3_IRQHandler            // DMA2 Channel3
+  .word DMA2_Channel4_5_IRQHandler          // DMA2 Channel4 & Channel5
+  .word 0                                   // Reserved
+  .word USBD2_HP_CAN2_TX_IRQHandler         // USBD2 High Priority or CAN2 TX
+  .word USBD2_LP_CAN2_RX0_IRQHandler        // USBD2 Low  Priority or CAN2 RX0
+  .word CAN2_RX1_IRQHandler                 // CAN2 RX1
+  .word CAN2_SCE_IRQHandler                 // CAN2 SCE
+
+// Default exception/interrupt handler
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WWDT_IRQHandler
+  .thumb_set WWDT_IRQHandler,Default_Handler
+
+  .weak PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak TAMPER_IRQHandler
+  .thumb_set TAMPER_IRQHandler,Default_Handler
+
+  .weak RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak RCM_IRQHandler
+  .thumb_set RCM_IRQHandler,Default_Handler
+
+  .weak EINT0_IRQHandler
+  .thumb_set EINT0_IRQHandler,Default_Handler
+
+  .weak EINT1_IRQHandler
+  .thumb_set EINT1_IRQHandler,Default_Handler
+
+  .weak EINT2_IRQHandler
+  .thumb_set EINT2_IRQHandler,Default_Handler
+
+  .weak EINT3_IRQHandler
+  .thumb_set EINT3_IRQHandler,Default_Handler
+
+  .weak EINT4_IRQHandler
+  .thumb_set EINT4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak ADC1_2_IRQHandler
+  .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+  .weak USBD1_HP_CAN1_TX_IRQHandler
+  .thumb_set USBD1_HP_CAN1_TX_IRQHandler,Default_Handler
+
+  .weak USBD1_LP_CAN1_RX0_IRQHandler
+  .thumb_set USBD1_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+  .weak CAN1_RX1_IRQHandler
+  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+  .weak CAN1_SCE_IRQHandler
+  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+  .weak EINT9_5_IRQHandler
+  .thumb_set EINT9_5_IRQHandler,Default_Handler
+
+  .weak TMR1_BRK_IRQHandler
+  .thumb_set TMR1_BRK_IRQHandler,Default_Handler
+
+  .weak TMR1_UP_IRQHandler
+  .thumb_set TMR1_UP_IRQHandler,Default_Handler
+
+  .weak TMR1_TRG_COM_IRQHandler
+  .thumb_set TMR1_TRG_COM_IRQHandler,Default_Handler
+
+  .weak TMR1_CC_IRQHandler
+  .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+  .weak TMR2_IRQHandler
+  .thumb_set TMR2_IRQHandler,Default_Handler
+
+  .weak TMR3_IRQHandler
+  .thumb_set TMR3_IRQHandler,Default_Handler
+
+  .weak TMR4_IRQHandler
+  .thumb_set TMR4_IRQHandler,Default_Handler
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak EINT15_10_IRQHandler
+  .thumb_set EINT15_10_IRQHandler,Default_Handler
+
+  .weak RTCAlarm_IRQHandler
+  .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+  .weak USBDWakeUp_IRQHandler
+  .thumb_set USBDWakeUp_IRQHandler,Default_Handler
+
+  .weak TMR8_BRK_IRQHandler
+  .thumb_set TMR8_BRK_IRQHandler,Default_Handler
+
+  .weak TMR8_UP_IRQHandler
+  .thumb_set TMR8_UP_IRQHandler,Default_Handler
+
+  .weak TMR8_TRG_COM_IRQHandler
+  .thumb_set TMR8_TRG_COM_IRQHandler,Default_Handler
+
+  .weak TMR8_CC_IRQHandler
+  .thumb_set TMR8_CC_IRQHandler,Default_Handler
+
+  .weak ADC3_IRQHandler
+  .thumb_set ADC3_IRQHandler,Default_Handler
+
+  .weak FSMC_IRQHandler
+  .thumb_set FSMC_IRQHandler,Default_Handler
+
+  .weak SDIO_IRQHandler
+  .thumb_set SDIO_IRQHandler,Default_Handler
+
+  .weak TMR5_IRQHandler
+  .thumb_set TMR5_IRQHandler,Default_Handler
+
+  .weak SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak UART5_IRQHandler
+  .thumb_set UART5_IRQHandler,Default_Handler
+
+  .weak TMR6_IRQHandler
+  .thumb_set TMR6_IRQHandler,Default_Handler
+
+  .weak TMR7_IRQHandler
+  .thumb_set TMR7_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel4_5_IRQHandler
+  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+  .weak USBD2_HP_CAN2_TX_IRQHandler
+  .thumb_set USBD2_HP_CAN2_TX_IRQHandler,Default_Handler
+
+  .weak USBD2_LP_CAN2_RX0_IRQHandler
+  .thumb_set USBD2_LP_CAN2_RX0_IRQHandler,Default_Handler
+
+  .weak CAN2_RX1_IRQHandler
+  .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+  .weak CAN2_SCE_IRQHandler
+  .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_md.s

@@ -1,246 +1,327 @@
-;/*!
-; * @file        startup_apm32f10x_hd.s
-; *
-; * @brief       CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f10x_hd
-; *
-; * @version     V1.0.0
-; *
-; * @date        2022-01-05
-; *
-; * @attention
-; *
-; *  Copyright (C) 2020-2022 Geehy Semiconductor
-; *
-; *  You may not use this file except in compliance with the
-; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
-; *
-; *  The program is only for reference, which is distributed in the hope
-; *  that it will be usefull and instructional for customers to develop
-; *  their software. Unless required by applicable law or agreed to in
-; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
-; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
-; *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
-; *  and limitations under the License.
-; */
-
-.syntax unified
-.cpu cortex - m3
-.fpu softvfp
-.thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-.section  .isr_vector, "a", % progbits
-.type  g_pfnVectors, % object
-
-g_pfnVectors:
-.word     _estack                           // Top of Stack
-.word     Reset_Handler                     // Reset Handler
-.word     NMI_Handler                       // NMI Handler
-.word     HardFault_Handler                 // Hard Fault Handler
-.word     MemManage_Handler                 // MPU Fault Handler
-.word     BusFault_Handler                  // Bus Fault Handler
-.word     UsageFault_Handler                // Usage Fault Handler
-.word     0                                 // Reserved
-.word     0                                 // Reserved
-.word     0                                 // Reserved
-.word     0                                 // Reserved
-.word     SVC_Handler                       // SVCall Handler
-.word     DebugMon_Handler                  // Debug Monitor Handler
-.word     0                                 // Reserved
-.word     PendSV_Handler                    // PendSV Handler
-.word     SysTick_Handler                   // SysTick Handler
-
-// external interrupts handler
-.word     WWDT_IRQHandler              // Window Watchdog
-.word     PVD_IRQHandler               // PVD through EINT Line detect
-.word     TAMPER_IRQHandler            // Tamper
-.word     RTC_IRQHandler               // RTC
-.word     FLASH_IRQHandler             // Flash
-.word     RCM_IRQHandler               // RCM
-.word     EINT0_IRQHandler             // EINT Line 0
-.word     EINT1_IRQHandler             // EINT Line 1
-.word     EINT2_IRQHandler             // EINT Line 2
-.word     EINT3_IRQHandler             // EINT Line 3
-.word     EINT4_IRQHandler             // EINT Line 4
-.word     DMA1_Channel1_IRQHandler     // DMA1 Channel 1
-.word     DMA1_Channel2_IRQHandler     // DMA1 Channel 2
-.word     DMA1_Channel3_IRQHandler     // DMA1 Channel 3
-.word     DMA1_Channel4_IRQHandler     // DMA1 Channel 4
-.word     DMA1_Channel5_IRQHandler     // DMA1 Channel 5
-.word     DMA1_Channel6_IRQHandler     // DMA1 Channel 6
-.word     DMA1_Channel7_IRQHandler     // DMA1 Channel 7
-.word     ADC1_2_IRQHandler            // ADC1_2
-.word     USBD1_HP_CAN1_TX_IRQHandler  // USBD1 High Priority or CAN1 TX
-.word     USBD1_LP_CAN1_RX0_IRQHandler // USBD1 Low  Priority or CAN1 RX0
-.word     CAN1_RX1_IRQHandler          // CAN1 RX1
-.word     CAN1_SCE_IRQHandler          // CAN1 SCE
-.word     EINT9_5_IRQHandler           // EINT Line 9..5
-.word     TMR1_BRK_IRQHandler          // TMR1 Break
-.word     TMR1_UP_IRQHandler           // TMR1 Update
-.word     TMR1_TRG_COM_IRQHandler      // TMR1 Trigger and Commutation
-.word     TMR1_CC_IRQHandler           // TMR1 Capture Compare
-.word     TMR2_IRQHandler              // TMR2
-.word     TMR3_IRQHandler              // TMR3
-.word     TMR4_IRQHandler              // TMR4
-.word     I2C1_EV_IRQHandler           // I2C1 Event
-.word     I2C1_ER_IRQHandler           // I2C1 Error
-.word     I2C2_EV_IRQHandler           // I2C2 Event
-.word     I2C2_ER_IRQHandler           // I2C2 Error
-.word     SPI1_IRQHandler              // SPI1
-.word     SPI2_IRQHandler              // SPI2
-.word     USART1_IRQHandler            // USART1
-.word     USART2_IRQHandler            // USART2
-.word     USART3_IRQHandler            // USART3
-.word     EINT15_10_IRQHandler         // EINT Line 15..10
-.word     RTCAlarm_IRQHandler          // RTC Alarm through EINT Line
-.word     USBDWakeUp_IRQHandler        // USBD Wakeup from suspend
-.word     FPU_IRQHandler               // FPU
-.word     QSPI_IRQHandler              // QSPI
-.word     USBD2_HP_IRQHandler          // USBD2 High Priority
-.word     USBD2_LP_IRQHandler          // USBD2 Low Priority
-
-.size  g_pfnVectors, . - g_pfnVectors
-
-.section  .text.Reset_Handler
-.weak  Reset_Handler
-.type  Reset_Handler, % function
+/*!
+ * @file       startup_apm32f103_hd.S
+ *
+ * @brief      CMSIS Cortex-M3 based Core Device Startup File for Device startup_apm32f103_hd
+ *
+ * @version    V1.0.1
+ *
+ * @date       2022-12-01
+ *
+ * @attention
+ *
+ *  Copyright (C) 2022 Geehy Semiconductor
+ *
+ *  You may not use this file except in compliance with the
+ *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+ *
+ *  The program is only for reference, which is distributed in the hope
+ *  that it will be useful and instructional for customers to develop
+ *  their software. Unless required by applicable law or agreed to in
+ *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+ *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+ *  and limitations under the License.
+ */
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global g_apm32_Vectors
+.global Default_Handler
+
+.word _start_address_init_data
+.word _start_address_data
+.word _end_address_data
+.word _start_address_bss
+.word _end_address_bss
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+// Reset handler routine
 Reset_Handler:
-ldr r1, = _sidata
-          ldr r2, = _sdata
-                    ldr r3, = _edata
-
-                              subs r3, r2
-                              ble fill_bss_start
-
-                              loop_copy_data:
-                              subs r3, #4
-                              ldr r0, [r1, r3]
-                              str r0, [r2, r3]
-                              bgt loop_copy_data
-
-                              fill_bss_start:
-                              ldr r1, = __bss_start
-                                        ldr r2, = __bss_end
-                                                movs r0, 0
-                                                subs r2, r1
-                                                ble startup_enter
-
-                                                loop_fill_bss:
-                                                subs r2, #4
-                                                str r0, [r1, r2]
-                                                bgt loop_fill_bss
-
-                                                startup_enter:
-                                                bl SystemInit
-                                                bl entry
-
-                                                /* Exception Handlers */
-                                                .weak   NMI_Handler
-                                                .type   NMI_Handler, % function
-                                                NMI_Handler:
-                                                b       .
-                                                .size   NMI_Handler, . - NMI_Handler
-
-                                                .weak   MemManage_Handler
-                                                .type   MemManage_Handler, % function
-                                                MemManage_Handler:
-                                                b       .
-                                                .size   MemManage_Handler, . - MemManage_Handler
-
-                                                .weak   BusFault_Handler
-                                                .type   BusFault_Handler, % function
-                                                BusFault_Handler:
-                                                b       .
-                                                .size   BusFault_Handler, . - BusFault_Handler
-
-                                                .weak   UsageFault_Handler
-                                                .type   UsageFault_Handler, % function
-                                                UsageFault_Handler:
-                                                b       .
-                                                .size   UsageFault_Handler, . - UsageFault_Handler
-
-                                                .weak   SVC_Handler
-                                                .type   SVC_Handler, % function
-                                                SVC_Handler:
-                                                b       .
-                                                .size   SVC_Handler, . - SVC_Handler
-
-                                                .weak   DebugMon_Handler
-                                                .type   DebugMon_Handler, % function
-                                                DebugMon_Handler:
-                                                b       .
-                                                .size   DebugMon_Handler, . - DebugMon_Handler
-
-                                                .weak   PendSV_Handler
-                                                .type   PendSV_Handler, % function
-                                                PendSV_Handler:
-                                                b       .
-                                                .size   PendSV_Handler, . - PendSV_Handler
-
-                                                .weak   SysTick_Handler
-                                                .type   SysTick_Handler, % function
-                                                SysTick_Handler:
-                                                b       .
-                                                .size   SysTick_Handler, . - SysTick_Handler
-
-                                                /* IQR Handler */
-                                                .section  .text.Default_Handler, "ax", % progbits
-                                                .type  Default_Handler, % function
-                                                Default_Handler:
-                                                b  .
-                                                .size  Default_Handler, . - Default_Handler
-
-                                                .macro  IRQ handler
-                                                .weak   \handler
-                                                .set    \handler, Default_Handler
-                                                .endm
-
-                                                IRQ WWDT_IRQHandler
-                                                IRQ PVD_IRQHandler
-                                                IRQ TAMPER_IRQHandler
-                                                IRQ RTC_IRQHandler
-                                                IRQ FLASH_IRQHandler
-                                                IRQ RCM_IRQHandler
-                                                IRQ EINT0_IRQHandler
-                                                IRQ EINT1_IRQHandler
-                                                IRQ EINT2_IRQHandler
-                                                IRQ EINT3_IRQHandler
-                                                IRQ EINT4_IRQHandler
-                                                IRQ DMA1_Channel1_IRQHandler
-                                                IRQ DMA1_Channel2_IRQHandler
-                                                IRQ DMA1_Channel3_IRQHandler
-                                                IRQ DMA1_Channel4_IRQHandler
-                                                IRQ DMA1_Channel5_IRQHandler
-                                                IRQ DMA1_Channel6_IRQHandler
-                                                IRQ DMA1_Channel7_IRQHandler
-                                                IRQ ADC1_2_IRQHandler
-                                                IRQ USBD1_HP_CAN1_TX_IRQHandler
-                                                IRQ USBD1_LP_CAN1_RX0_IRQHandler
-                                                IRQ CAN1_RX1_IRQHandler
-                                                IRQ CAN1_SCE_IRQHandler
-                                                IRQ EINT9_5_IRQHandler
-                                                IRQ TMR1_BRK_IRQHandler
-                                                IRQ TMR1_UP_IRQHandler
-                                                IRQ TMR1_TRG_COM_IRQHandler
-                                                IRQ TMR1_CC_IRQHandler
-                                                IRQ TMR2_IRQHandler
-                                                IRQ TMR3_IRQHandler
-                                                IRQ TMR4_IRQHandler
-                                                IRQ I2C1_EV_IRQHandler
-                                                IRQ I2C1_ER_IRQHandler
-                                                IRQ I2C2_EV_IRQHandler
-                                                IRQ I2C2_ER_IRQHandler
-                                                IRQ SPI1_IRQHandler
-                                                IRQ SPI2_IRQHandler
-                                                IRQ USART1_IRQHandler
-                                                IRQ USART2_IRQHandler
-                                                IRQ USART3_IRQHandler
-                                                IRQ EINT15_10_IRQHandler
-                                                IRQ RTCAlarm_IRQHandler
-                                                IRQ USBDWakeUp_IRQHandler
-                                                IRQ FPU_IRQHandler
-                                                IRQ QSPI_IRQHandler
-                                                IRQ USBD2_HP_IRQHandler
-                                                IRQ USBD2_LP_IRQHandler
+
+  ldr r0, =_start_address_data
+  ldr r1, =_end_address_data
+  ldr r2, =_start_address_init_data
+  movs r3, #0
+  b L_loop0_0
+
+L_loop0:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+L_loop0_0:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc L_loop0
+  
+  ldr r2, =_start_address_bss
+  ldr r4, =_end_address_bss
+  movs r3, #0
+  b L_loop1
+
+L_loop2:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+L_loop1:
+  cmp r2, r4
+  bcc L_loop2
+
+  bl  SystemInit
+  bl __libc_init_array
+  bl entry
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+// This is the code that gets called when the processor receives an unexpected interrupt.
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+L_Loop_infinite:
+  b L_Loop_infinite
+  .size Default_Handler, .-Default_Handler
+
+// The minimal vector table for a Cortex M3.
+   .section .isr_vector,"a",%progbits
+  .type g_apm32_Vectors, %object
+  .size g_apm32_Vectors, .-g_apm32_Vectors
+
+// Vector Table Mapped to Address 0 at Reset
+g_apm32_Vectors:
+
+  .word _end_stack                          // Top of Stack
+  .word Reset_Handler                       // Reset Handler
+  .word NMI_Handler                         // NMI Handler
+  .word HardFault_Handler                   // Hard Fault Handler
+  .word MemManage_Handler                   // MPU Fault Handler
+  .word BusFault_Handler                    // Bus Fault Handler
+  .word UsageFault_Handler                  // Usage Fault Handler
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word 0                                   // Reserved
+  .word SVC_Handler                         // SVCall Handler
+  .word DebugMon_Handler                    // Debug Monitor Handler
+  .word 0                                   // Reserved
+  .word PendSV_Handler                      // PendSV Handler
+  .word SysTick_Handler                     // SysTick Handler
+  .word WWDT_IRQHandler                     // Window Watchdog
+  .word PVD_IRQHandler                      // PVD through EINT Line detect
+  .word TAMPER_IRQHandler                   // Tamper
+  .word RTC_IRQHandler                      // RTC
+  .word FLASH_IRQHandler                    // Flash
+  .word RCM_IRQHandler                      // RCM
+  .word EINT0_IRQHandler                    // EINT Line 0
+  .word EINT1_IRQHandler                    // EINT Line 1
+  .word EINT2_IRQHandler                    // EINT Line 2
+  .word EINT3_IRQHandler                    // EINT Line 3
+  .word EINT4_IRQHandler                    // EINT Line 4
+  .word DMA1_Channel1_IRQHandler            // DMA1 Channel 1
+  .word DMA1_Channel2_IRQHandler            // DMA1 Channel 2
+  .word DMA1_Channel3_IRQHandler            // DMA1 Channel 3
+  .word DMA1_Channel4_IRQHandler            // DMA1 Channel 4
+  .word DMA1_Channel5_IRQHandler            // DMA1 Channel 5
+  .word DMA1_Channel6_IRQHandler            // DMA1 Channel 6
+  .word DMA1_Channel7_IRQHandler            // DMA1 Channel 7
+  .word ADC1_2_IRQHandler                   // ADC1_2
+  .word USBD1_HP_CAN1_TX_IRQHandler         // USBD1 High Priority or CAN1 TX
+  .word USBD1_LP_CAN1_RX0_IRQHandler        // USBD1 Low  Priority or CAN1 RX0
+  .word CAN1_RX1_IRQHandler                 // CAN1 RX1
+  .word CAN1_SCE_IRQHandler                 // CAN1 SCE
+  .word EINT9_5_IRQHandler                  // EINT Line 9..5
+  .word TMR1_BRK_IRQHandler                 // TMR1 Break
+  .word TMR1_UP_IRQHandler                  // TMR1 Update
+  .word TMR1_TRG_COM_IRQHandler             // TMR1 Trigger and Commutation
+  .word TMR1_CC_IRQHandler                  // TMR1 Capture Compare
+  .word TMR2_IRQHandler                     // TMR2
+  .word TMR3_IRQHandler                     // TMR3
+  .word TMR4_IRQHandler                     // TMR4
+  .word I2C1_EV_IRQHandler                  // I2C1 Event
+  .word I2C1_ER_IRQHandler                  // I2C1 Error
+  .word I2C2_EV_IRQHandler                  // I2C2 Event
+  .word I2C2_ER_IRQHandler                  // I2C2 Error
+  .word SPI1_IRQHandler                     // SPI1
+  .word SPI2_IRQHandler                     // SPI2
+  .word USART1_IRQHandler                   // USART1
+  .word USART2_IRQHandler                   // USART2
+  .word USART3_IRQHandler                   // USART3
+  .word EINT15_10_IRQHandler                // EINT Line 15..10
+  .word RTCAlarm_IRQHandler                 // RTC Alarm through EINT Line
+  .word USBDWakeUp_IRQHandler               // USBD Wakeup from suspend
+  .word FPU_IRQHandler                      // FPU
+  .word QSPI_IRQHandler                     // QSPI
+  .word USBD2_HP_IRQHandler                 // USBD2 High Priority
+  .word USBD2_LP_IRQHandler                 // USBD2 Low Priority
+// Default exception/interrupt handler
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WWDT_IRQHandler
+  .thumb_set WWDT_IRQHandler,Default_Handler
+
+  .weak PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak TAMPER_IRQHandler
+  .thumb_set TAMPER_IRQHandler,Default_Handler
+
+  .weak RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak RCM_IRQHandler
+  .thumb_set RCM_IRQHandler,Default_Handler
+
+  .weak EINT0_IRQHandler
+  .thumb_set EINT0_IRQHandler,Default_Handler
+
+  .weak EINT1_IRQHandler
+  .thumb_set EINT1_IRQHandler,Default_Handler
+
+  .weak EINT2_IRQHandler
+  .thumb_set EINT2_IRQHandler,Default_Handler
+
+  .weak EINT3_IRQHandler
+  .thumb_set EINT3_IRQHandler,Default_Handler
+
+  .weak EINT4_IRQHandler
+  .thumb_set EINT4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak ADC1_2_IRQHandler
+  .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+  .weak USBD1_HP_CAN1_TX_IRQHandler
+  .thumb_set USBD1_HP_CAN1_TX_IRQHandler,Default_Handler
+
+  .weak USBD1_LP_CAN1_RX0_IRQHandler
+  .thumb_set USBD1_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+  .weak CAN1_RX1_IRQHandler
+  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+  .weak CAN1_SCE_IRQHandler
+  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+  .weak EINT9_5_IRQHandler
+  .thumb_set EINT9_5_IRQHandler,Default_Handler
+
+  .weak TMR1_BRK_IRQHandler
+  .thumb_set TMR1_BRK_IRQHandler,Default_Handler
+
+  .weak TMR1_UP_IRQHandler
+  .thumb_set TMR1_UP_IRQHandler,Default_Handler
+
+  .weak TMR1_TRG_COM_IRQHandler
+  .thumb_set TMR1_TRG_COM_IRQHandler,Default_Handler
+
+  .weak TMR1_CC_IRQHandler
+  .thumb_set TMR1_CC_IRQHandler,Default_Handler
+
+  .weak TMR2_IRQHandler
+  .thumb_set TMR2_IRQHandler,Default_Handler
+
+  .weak TMR3_IRQHandler
+  .thumb_set TMR3_IRQHandler,Default_Handler
+
+  .weak TMR4_IRQHandler
+  .thumb_set TMR4_IRQHandler,Default_Handler
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak EINT15_10_IRQHandler
+  .thumb_set EINT15_10_IRQHandler,Default_Handler
+
+  .weak RTCAlarm_IRQHandler
+  .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+  .weak USBDWakeUp_IRQHandler
+  .thumb_set USBDWakeUp_IRQHandler,Default_Handler
+
+  .weak FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak QSPI_IRQHandler
+  .thumb_set QSPI_IRQHandler,Default_Handler
+
+  .weak USBD2_HP_IRQHandler
+  .thumb_set USBD2_HP_IRQHandler,Default_Handler
+
+  .weak USBD2_LP_IRQHandler
+  .thumb_set USBD2_LP_IRQHandler,Default_Handler

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_cl.s

@@ -0,0 +1,492 @@
+;/*!
+; * @file        startup_apm32f10x_cl.s
+; *
+; * @brief       CMSIS Cortex-M3 based Core Device Startup File for Device APM32F103
+; *
+; * @version     V1.0.0
+; *
+; * @date        2022-07-25
+; *
+; * @attention
+; *
+; *  Copyright (C) 2020-2022 Geehy Semiconductor
+; *
+; *  You may not use this file except in compliance with the
+; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
+; *
+; *  The program is only for reference, which is distributed in the hope
+; *  that it will be useful and instructional for customers to develop
+; *  their software. Unless required by applicable law or agreed to in
+; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
+; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
+; *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
+; *  and limitations under the License.
+; */
+
+    MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+                DCD     Reset_Handler                ; Reset Handler
+                DCD     NMI_Handler                  ; NMI Handler
+                DCD     HardFault_Handler            ; Hard Fault Handler
+                DCD     MemManage_Handler            ; MPU Fault Handler
+                DCD     BusFault_Handler             ; Bus Fault Handler
+                DCD     UsageFault_Handler           ; Usage Fault Handler
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     SVC_Handler                  ; SVCall Handler
+                DCD     DebugMon_Handler             ; Debug Monitor Handler
+                DCD     0                            ; Reserved
+                DCD     PendSV_Handler               ; PendSV Handler
+                DCD     SysTick_Handler              ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDT_IRQHandler              ; Window Watchdog
+                DCD     PVD_IRQHandler               ; PVD through EINT Line detect
+                DCD     TAMPER_IRQHandler            ; Tamper
+                DCD     RTC_IRQHandler               ; RTC
+                DCD     FLASH_IRQHandler             ; Flash
+                DCD     RCM_IRQHandler               ; RCM
+                DCD     EINT0_IRQHandler             ; EINT Line 0
+                DCD     EINT1_IRQHandler             ; EINT Line 1
+                DCD     EINT2_IRQHandler             ; EINT Line 2
+                DCD     EINT3_IRQHandler             ; EINT Line 3
+                DCD     EINT4_IRQHandler             ; EINT Line 4
+                DCD     DMA1_Channel1_IRQHandler     ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler     ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler     ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler     ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler     ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler     ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler     ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler            ; ADC1 & ADC2
+                DCD     CAN1_TX_IRQHandler           ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler          ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler          ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler          ; CAN1 SCE
+                DCD     EINT9_5_IRQHandler           ; EINT Line 9..5
+                DCD     TMR1_BRK_IRQHandler          ; TMR1 Break
+                DCD     TMR1_UP_IRQHandler           ; TMR1 Update
+                DCD     TMR1_TRG_COM_IRQHandler      ; TMR1 Trigger and Commutation
+                DCD     TMR1_CC_IRQHandler           ; TMR1 Capture Compare
+                DCD     TMR2_IRQHandler              ; TMR2
+                DCD     TMR3_IRQHandler              ; TMR3
+                DCD     TMR4_IRQHandler              ; TMR4
+                DCD     I2C1_EV_IRQHandler           ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler           ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler           ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler           ; I2C2 Error
+                DCD     SPI1_IRQHandler              ; SPI1
+                DCD     SPI2_IRQHandler              ; SPI2
+                DCD     USART1_IRQHandler            ; USART1
+                DCD     USART2_IRQHandler            ; USART2
+                DCD     USART3_IRQHandler            ; USART3
+                DCD     EINT15_10_IRQHandler         ; EINT Line 15..10
+                DCD     RTCAlarm_IRQHandler          ; RTC Alarm through EINT Line
+                DCD     OTG_FS_WKUP_IRQHandler       ; USBD Wakeup from suspend
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     TMR5_IRQHandler              ; TMR5
+                DCD     SPI3_IRQHandler              ; SPI3
+                DCD     UART4_IRQHandler             ; UART4
+                DCD     UART5_IRQHandler             ; UART5
+                DCD     TMR6_IRQHandler              ; TMR6
+                DCD     TMR7_IRQHandler              ; TMR7
+                DCD     DMA2_Channel1_IRQHandler     ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler     ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler     ; DMA2 Channel3
+                DCD     DMA2_Channel4_IRQHandler     ; DMA2 Channel4
+                DCD     DMA2_Channel5_IRQHandler     ; DMA2 Channel5
+                DCD     ETH_IRQHandler               ; ETH
+                DCD     ETH_WKUP_IRQHandler          ; ETH Wake up
+                DCD     CAN2_TX_IRQHandler           ; CAN2 TX
+                DCD     CAN2_RX0_IRQHandler          ; CAN2 RX0
+                DCD     CAN2_RX1_IRQHandler          ; CAN2 RX1
+                DCD     CAN2_SCE_IRQHandler          ; CAN2 SCE
+                DCD     OTG_FS_IRQHandler            ; OTG FS
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDT_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WWDT_IRQHandler
+        B WWDT_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+
+        PUBWEAK TAMPER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TAMPER_IRQHandler
+        B TAMPER_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCM_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RCM_IRQHandler
+        B RCM_IRQHandler
+
+        PUBWEAK EINT0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT0_IRQHandler
+        B EINT0_IRQHandler
+
+        PUBWEAK EINT1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT1_IRQHandler
+        B EINT1_IRQHandler
+
+        PUBWEAK EINT2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT2_IRQHandler
+        B EINT2_IRQHandler
+
+        PUBWEAK EINT3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT3_IRQHandler
+        B EINT3_IRQHandler
+
+        PUBWEAK EINT4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT4_IRQHandler
+        B EINT4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EINT9_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT9_5_IRQHandler
+        B EINT9_5_IRQHandler
+
+        PUBWEAK TMR1_BRK_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_BRK_IRQHandler
+        B TMR1_BRK_IRQHandler
+
+        PUBWEAK TMR1_UP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_UP_IRQHandler
+        B TMR1_UP_IRQHandler
+
+        PUBWEAK TMR1_TRG_COM_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_TRG_COM_IRQHandler
+        B TMR1_TRG_COM_IRQHandler
+
+        PUBWEAK TMR1_CC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_CC_IRQHandler
+        B TMR1_CC_IRQHandler
+
+        PUBWEAK TMR2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR2_IRQHandler
+        B TMR2_IRQHandler
+
+        PUBWEAK TMR3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR3_IRQHandler
+        B TMR3_IRQHandler
+
+        PUBWEAK TMR4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR4_IRQHandler
+        B TMR4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EINT15_10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT15_10_IRQHandler
+        B EINT15_10_IRQHandler
+
+        PUBWEAK RTCAlarm_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTCAlarm_IRQHandler
+        B RTCAlarm_IRQHandler
+
+        PUBWEAK OTG_FS_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_FS_WKUP_IRQHandler
+        B OTG_FS_WKUP_IRQHandler
+
+        PUBWEAK TMR5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR5_IRQHandler
+        B TMR5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TMR6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR6_IRQHandler
+        B TMR6_IRQHandler
+
+        PUBWEAK TMR7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR7_IRQHandler
+        B TMR7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK ETH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ETH_IRQHandler
+        B ETH_IRQHandler
+
+        PUBWEAK ETH_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ETH_WKUP_IRQHandler
+        B ETH_WKUP_IRQHandler
+
+        PUBWEAK CAN2_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_TX_IRQHandler
+        B CAN2_TX_IRQHandler
+
+        PUBWEAK CAN2_RX0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX0_IRQHandler
+        B CAN2_RX0_IRQHandler
+
+        PUBWEAK CAN2_RX1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX1_IRQHandler
+        B CAN2_RX1_IRQHandler
+
+        PUBWEAK CAN2_SCE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_SCE_IRQHandler
+        B CAN2_SCE_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_FS_IRQHandler
+        B OTG_FS_IRQHandler
+
+        END
+

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s

@@ -5,7 +5,7 @@
 ; *
 ; * @version     V1.0.0
 ; *
-; * @date        2022-01-05
+; * @date        2022-07-25
 ; *
 ; * @attention
 ; *
@@ -15,7 +15,7 @@
 ; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
 ; *
 ; *  The program is only for reference, which is distributed in the hope
-; *  that it will be usefull and instructional for customers to develop
+; *  that it will be useful and instructional for customers to develop
 ; *  their software. Unless required by applicable law or agreed to in
 ; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
 ; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,791 +23,482 @@
 ; *  and limitations under the License.
 ; */
 
-MODULE  ? cstartup
+    MODULE  ?cstartup
 
-;;
-Forward declaration of sections.
-SECTION CSTACK:
-DATA:
-NOROOT(3)
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
 
-SECTION .intvec:
-CODE:
-NOROOT(2)
+        SECTION .intvec:CODE:NOROOT(2)
 
 
-EXTERN  __iar_program_start
-EXTERN  SystemInit
-PUBLIC  __vector_table
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
 
-DATA
+        DATA
 
 __vector_table
-DCD     sfe(CSTACK)
-DCD     Reset_Handler                ;
-Reset Handler
-DCD     NMI_Handler                  ;
-NMI Handler
-DCD     HardFault_Handler            ;
-Hard Fault Handler
-DCD     MemManage_Handler            ;
-MPU Fault Handler
-DCD     BusFault_Handler             ;
-Bus Fault Handler
-DCD     UsageFault_Handler           ;
-Usage Fault Handler
-DCD     0                            ;
-Reserved
-DCD     0                            ;
-Reserved
-DCD     0                            ;
-Reserved
-DCD     0                            ;
-Reserved
-DCD     SVC_Handler                  ;
-SVCall Handler
-DCD     DebugMon_Handler             ;
-Debug Monitor Handler
-DCD     0                            ;
-Reserved
-DCD     PendSV_Handler               ;
-PendSV Handler
-DCD     SysTick_Handler              ;
-SysTick Handler
-
-;
-External Interrupts
-DCD     WWDT_IRQHandler              ;
-Window Watchdog
-DCD     PVD_IRQHandler               ;
-PVD through EINT Line detect
-DCD     TAMPER_IRQHandler            ;
-Tamper
-DCD     RTC_IRQHandler               ;
-RTC
-DCD     FLASH_IRQHandler             ;
-Flash
-DCD     RCM_IRQHandler               ;
-RCM
-DCD     EINT0_IRQHandler             ;
-EINT Line 0
-DCD     EINT1_IRQHandler             ;
-EINT Line 1
-DCD     EINT2_IRQHandler             ;
-EINT Line 2
-DCD     EINT3_IRQHandler             ;
-EINT Line 3
-DCD     EINT4_IRQHandler             ;
-EINT Line 4
-DCD     DMA1_Channel1_IRQHandler     ;
-DMA1 Channel 1
-DCD     DMA1_Channel2_IRQHandler     ;
-DMA1 Channel 2
-DCD     DMA1_Channel3_IRQHandler     ;
-DMA1 Channel 3
-DCD     DMA1_Channel4_IRQHandler     ;
-DMA1 Channel 4
-DCD     DMA1_Channel5_IRQHandler     ;
-DMA1 Channel 5
-DCD     DMA1_Channel6_IRQHandler     ;
-DMA1 Channel 6
-DCD     DMA1_Channel7_IRQHandler     ;
-DMA1 Channel 7
-DCD     ADC1_2_IRQHandler            ;
-ADC1 &ADC2
-DCD     USBD1_HP_CAN1_TX_IRQHandler  ;
-USBD1 High Priority or CAN1 TX
-DCD     USBD1_LP_CAN1_RX0_IRQHandler ;
-USBD1 Low  Priority or CAN1 RX0
-DCD     CAN1_RX1_IRQHandler          ;
-CAN1 RX1
-DCD     CAN1_SCE_IRQHandler          ;
-CAN1 SCE
-DCD     EINT9_5_IRQHandler           ;
-EINT Line 9..5
-DCD     TMR1_BRK_IRQHandler          ;
-TMR1 Break
-DCD     TMR1_UP_IRQHandler           ;
-TMR1 Update
-DCD     TMR1_TRG_COM_IRQHandler      ;
-TMR1 Trigger and Commutation
-DCD     TMR1_CC_IRQHandler           ;
-TMR1 Capture Compare
-DCD     TMR2_IRQHandler              ;
-TMR2
-DCD     TMR3_IRQHandler              ;
-TMR3
-DCD     TMR4_IRQHandler              ;
-TMR4
-DCD     I2C1_EV_IRQHandler           ;
-I2C1 Event
-DCD     I2C1_ER_IRQHandler           ;
-I2C1 Error
-DCD     I2C2_EV_IRQHandler           ;
-I2C2 Event
-DCD     I2C2_ER_IRQHandler           ;
-I2C2 Error
-DCD     SPI1_IRQHandler              ;
-SPI1
-DCD     SPI2_IRQHandler              ;
-SPI2
-DCD     USART1_IRQHandler            ;
-USART1
-DCD     USART2_IRQHandler            ;
-USART2
-DCD     USART3_IRQHandler            ;
-USART3
-DCD     EINT15_10_IRQHandler         ;
-EINT Line 15..10
-DCD     RTCAlarm_IRQHandler          ;
-RTC Alarm through EINT Line
-DCD     USBDWakeUp_IRQHandler        ;
-USBD Wakeup from suspend
-DCD     TMR8_BRK_IRQHandler          ;
-TMR8 Break
-DCD     TMR8_UP_IRQHandler           ;
-TMR8 Update
-DCD     TMR8_TRG_COM_IRQHandler      ;
-TMR8 Trigger and Commutation
-DCD     TMR8_CC_IRQHandler           ;
-TMR8 Capture Compare
-DCD     ADC3_IRQHandler              ;
-ADC3
-DCD     EMMC_IRQHandler              ;
-EMMC
-DCD     SDIO_IRQHandler              ;
-SDIO
-DCD     TMR5_IRQHandler              ;
-TMR5
-DCD     SPI3_IRQHandler              ;
-SPI3
-DCD     UART4_IRQHandler             ;
-UART4
-DCD     UART5_IRQHandler             ;
-UART5
-DCD     TMR6_IRQHandler              ;
-TMR6
-DCD     TMR7_IRQHandler              ;
-TMR7
-DCD     DMA2_Channel1_IRQHandler     ;
-DMA2 Channel1
-DCD     DMA2_Channel2_IRQHandler     ;
-DMA2 Channel2
-DCD     DMA2_Channel3_IRQHandler     ;
-DMA2 Channel3
-DCD     DMA2_Channel4_5_IRQHandler   ;
-DMA2 Channel4 &Channel5
-DCD     0                            ;
-Reserved
-DCD     USBD2_HP_CAN2_TX_IRQHandler  ;
-USBD2 High Priority or CAN2 TX
-DCD     USBD2_LP_CAN2_RX0_IRQHandler ;
-USBD2 Low  Priority or CAN2 RX0
-DCD     CAN2_RX1_IRQHandler          ;
-CAN2 RX1
-DCD     CAN2_SCE_IRQHandler          ;
-CAN2 SCE
+        DCD     sfe(CSTACK)
+                DCD     Reset_Handler                ; Reset Handler
+                DCD     NMI_Handler                  ; NMI Handler
+                DCD     HardFault_Handler            ; Hard Fault Handler
+                DCD     MemManage_Handler            ; MPU Fault Handler
+                DCD     BusFault_Handler             ; Bus Fault Handler
+                DCD     UsageFault_Handler           ; Usage Fault Handler
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     SVC_Handler                  ; SVCall Handler
+                DCD     DebugMon_Handler             ; Debug Monitor Handler
+                DCD     0                            ; Reserved
+                DCD     PendSV_Handler               ; PendSV Handler
+                DCD     SysTick_Handler              ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDT_IRQHandler              ; Window Watchdog
+                DCD     PVD_IRQHandler               ; PVD through EINT Line detect
+                DCD     TAMPER_IRQHandler            ; Tamper
+                DCD     RTC_IRQHandler               ; RTC
+                DCD     FLASH_IRQHandler             ; Flash
+                DCD     RCM_IRQHandler               ; RCM
+                DCD     EINT0_IRQHandler             ; EINT Line 0
+                DCD     EINT1_IRQHandler             ; EINT Line 1
+                DCD     EINT2_IRQHandler             ; EINT Line 2
+                DCD     EINT3_IRQHandler             ; EINT Line 3
+                DCD     EINT4_IRQHandler             ; EINT Line 4
+                DCD     DMA1_Channel1_IRQHandler     ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler     ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler     ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler     ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler     ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler     ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler     ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler            ; ADC1 & ADC2
+                DCD     USBD1_HP_CAN1_TX_IRQHandler  ; USBD1 High Priority or CAN1 TX
+                DCD     USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler          ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler          ; CAN1 SCE
+                DCD     EINT9_5_IRQHandler           ; EINT Line 9..5
+                DCD     TMR1_BRK_IRQHandler          ; TMR1 Break
+                DCD     TMR1_UP_IRQHandler           ; TMR1 Update
+                DCD     TMR1_TRG_COM_IRQHandler      ; TMR1 Trigger and Commutation
+                DCD     TMR1_CC_IRQHandler           ; TMR1 Capture Compare
+                DCD     TMR2_IRQHandler              ; TMR2
+                DCD     TMR3_IRQHandler              ; TMR3
+                DCD     TMR4_IRQHandler              ; TMR4
+                DCD     I2C1_EV_IRQHandler           ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler           ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler           ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler           ; I2C2 Error
+                DCD     SPI1_IRQHandler              ; SPI1
+                DCD     SPI2_IRQHandler              ; SPI2
+                DCD     USART1_IRQHandler            ; USART1
+                DCD     USART2_IRQHandler            ; USART2
+                DCD     USART3_IRQHandler            ; USART3
+                DCD     EINT15_10_IRQHandler         ; EINT Line 15..10
+                DCD     RTCAlarm_IRQHandler          ; RTC Alarm through EINT Line
+                DCD     USBDWakeUp_IRQHandler        ; USBD Wakeup from suspend
+                DCD     TMR8_BRK_IRQHandler          ; TMR8 Break
+                DCD     TMR8_UP_IRQHandler           ; TMR8 Update
+                DCD     TMR8_TRG_COM_IRQHandler      ; TMR8 Trigger and Commutation
+                DCD     TMR8_CC_IRQHandler           ; TMR8 Capture Compare
+                DCD     ADC3_IRQHandler              ; ADC3
+                DCD     EMMC_IRQHandler              ; EMMC
+                DCD     SDIO_IRQHandler              ; SDIO
+                DCD     TMR5_IRQHandler              ; TMR5
+                DCD     SPI3_IRQHandler              ; SPI3
+                DCD     UART4_IRQHandler             ; UART4
+                DCD     UART5_IRQHandler             ; UART5
+                DCD     TMR6_IRQHandler              ; TMR6
+                DCD     TMR7_IRQHandler              ; TMR7
+                DCD     DMA2_Channel1_IRQHandler     ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler     ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler     ; DMA2 Channel3
+                DCD     DMA2_Channel4_5_IRQHandler   ; DMA2 Channel4 & Channel5
+                DCD     0                            ; Reserved
+                DCD     USBD2_HP_CAN2_TX_IRQHandler  ; USBD2 High Priority or CAN2 TX
+                DCD     USBD2_LP_CAN2_RX0_IRQHandler ; USBD2 Low  Priority or CAN2 RX0
+                DCD     CAN2_RX1_IRQHandler          ; CAN2 RX1
+                DCD     CAN2_SCE_IRQHandler          ; CAN2 SCE
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
+;; Default interrupt handlers.
 ;;
-Default interrupt handlers.
-;;
-THUMB
+        THUMB
 
-PUBWEAK Reset_Handler
-SECTION .text:
-CODE:
-REORDER:
-NOROOT(2)
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
 Reset_Handler
-LDR     R0, = SystemInit
-              BLX     R0
-              LDR     R0, = __iar_program_start
-                            BX      R0
-
-                            PUBWEAK NMI_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            NMI_Handler
-                            B NMI_Handler
-
-                            PUBWEAK HardFault_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            HardFault_Handler
-                            B HardFault_Handler
-
-                            PUBWEAK MemManage_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            MemManage_Handler
-                            B MemManage_Handler
-
-                            PUBWEAK BusFault_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            BusFault_Handler
-                            B BusFault_Handler
-
-                            PUBWEAK UsageFault_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            UsageFault_Handler
-                            B UsageFault_Handler
-
-                            PUBWEAK SVC_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            SVC_Handler
-                            B SVC_Handler
-
-                            PUBWEAK DebugMon_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DebugMon_Handler
-                            B DebugMon_Handler
-
-                            PUBWEAK PendSV_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            PendSV_Handler
-                            B PendSV_Handler
-
-                            PUBWEAK SysTick_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            SysTick_Handler
-                            B SysTick_Handler
-
-                            PUBWEAK WWDT_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            WWDT_IRQHandler
-                            B WWDT_IRQHandler
-
-                            PUBWEAK PVD_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            PVD_IRQHandler
-                            B PVD_IRQHandler
-
-                            PUBWEAK TAMPER_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TAMPER_IRQHandler
-                            B TAMPER_IRQHandler
-
-                            PUBWEAK RTC_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            RTC_IRQHandler
-                            B RTC_IRQHandler
-
-                            PUBWEAK FLASH_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            FLASH_IRQHandler
-                            B FLASH_IRQHandler
-
-                            PUBWEAK RCM_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            RCM_IRQHandler
-                            B RCM_IRQHandler
-
-                            PUBWEAK EINT0_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT0_IRQHandler
-                            B EINT0_IRQHandler
-
-                            PUBWEAK EINT1_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT1_IRQHandler
-                            B EINT1_IRQHandler
-
-                            PUBWEAK EINT2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT2_IRQHandler
-                            B EINT2_IRQHandler
-
-                            PUBWEAK EINT3_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT3_IRQHandler
-                            B EINT3_IRQHandler
-
-                            PUBWEAK EINT4_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT4_IRQHandler
-                            B EINT4_IRQHandler
-
-                            PUBWEAK DMA1_Channel1_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel1_IRQHandler
-                            B DMA1_Channel1_IRQHandler
-
-                            PUBWEAK DMA1_Channel2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel2_IRQHandler
-                            B DMA1_Channel2_IRQHandler
-
-                            PUBWEAK DMA1_Channel3_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel3_IRQHandler
-                            B DMA1_Channel3_IRQHandler
-
-                            PUBWEAK DMA1_Channel4_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel4_IRQHandler
-                            B DMA1_Channel4_IRQHandler
-
-                            PUBWEAK DMA1_Channel5_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel5_IRQHandler
-                            B DMA1_Channel5_IRQHandler
-
-                            PUBWEAK DMA1_Channel6_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel6_IRQHandler
-                            B DMA1_Channel6_IRQHandler
-
-                            PUBWEAK DMA1_Channel7_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel7_IRQHandler
-                            B DMA1_Channel7_IRQHandler
-
-                            PUBWEAK ADC1_2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            ADC1_2_IRQHandler
-                            B ADC1_2_IRQHandler
-
-                            PUBWEAK USBD1_HP_CAN1_TX_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USBD1_HP_CAN1_TX_IRQHandler
-                            B USBD1_HP_CAN1_TX_IRQHandler
-
-                            PUBWEAK USBD1_LP_CAN1_RX0_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USBD1_LP_CAN1_RX0_IRQHandler
-                            B USBD1_LP_CAN1_RX0_IRQHandler
-
-                            PUBWEAK CAN1_RX1_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            CAN1_RX1_IRQHandler
-                            B CAN1_RX1_IRQHandler
-
-                            PUBWEAK CAN1_SCE_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            CAN1_SCE_IRQHandler
-                            B CAN1_SCE_IRQHandler
-
-                            PUBWEAK EINT9_5_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT9_5_IRQHandler
-                            B EINT9_5_IRQHandler
-
-                            PUBWEAK TMR1_BRK_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR1_BRK_IRQHandler
-                            B TMR1_BRK_IRQHandler
-
-                            PUBWEAK TMR1_UP_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR1_UP_IRQHandler
-                            B TMR1_UP_IRQHandler
-
-                            PUBWEAK TMR1_TRG_COM_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR1_TRG_COM_IRQHandler
-                            B TMR1_TRG_COM_IRQHandler
-
-                            PUBWEAK TMR1_CC_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR1_CC_IRQHandler
-                            B TMR1_CC_IRQHandler
-
-                            PUBWEAK TMR2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR2_IRQHandler
-                            B TMR2_IRQHandler
-
-                            PUBWEAK TMR3_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR3_IRQHandler
-                            B TMR3_IRQHandler
-
-                            PUBWEAK TMR4_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR4_IRQHandler
-                            B TMR4_IRQHandler
-
-                            PUBWEAK I2C1_EV_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            I2C1_EV_IRQHandler
-                            B I2C1_EV_IRQHandler
-
-                            PUBWEAK I2C1_ER_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            I2C1_ER_IRQHandler
-                            B I2C1_ER_IRQHandler
-
-                            PUBWEAK I2C2_EV_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            I2C2_EV_IRQHandler
-                            B I2C2_EV_IRQHandler
-
-                            PUBWEAK I2C2_ER_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            I2C2_ER_IRQHandler
-                            B I2C2_ER_IRQHandler
-
-                            PUBWEAK SPI1_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            SPI1_IRQHandler
-                            B SPI1_IRQHandler
-
-                            PUBWEAK SPI2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            SPI2_IRQHandler
-                            B SPI2_IRQHandler
-
-                            PUBWEAK USART1_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USART1_IRQHandler
-                            B USART1_IRQHandler
-
-                            PUBWEAK USART2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USART2_IRQHandler
-                            B USART2_IRQHandler
-
-                            PUBWEAK USART3_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USART3_IRQHandler
-                            B USART3_IRQHandler
-
-                            PUBWEAK EINT15_10_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT15_10_IRQHandler
-                            B EINT15_10_IRQHandler
-
-                            PUBWEAK RTCAlarm_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            RTCAlarm_IRQHandler
-                            B RTCAlarm_IRQHandler
-
-                            PUBWEAK USBDWakeUp_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USBDWakeUp_IRQHandler
-                            B USBDWakeUp_IRQHandler
-
-                            PUBWEAK TMR8_BRK_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR8_BRK_IRQHandler
-                            B TMR8_BRK_IRQHandler
-
-                            PUBWEAK TMR8_UP_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR8_UP_IRQHandler
-                            B TMR8_UP_IRQHandler
-
-                            PUBWEAK TMR8_TRG_COM_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR8_TRG_COM_IRQHandler
-                            B TMR8_TRG_COM_IRQHandler
-
-                            PUBWEAK TMR8_CC_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR8_CC_IRQHandler
-                            B TMR8_CC_IRQHandler
-
-                            PUBWEAK ADC3_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            ADC3_IRQHandler
-                            B ADC3_IRQHandler
-
-                            PUBWEAK EMMC_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EMMC_IRQHandler
-                            B EMMC_IRQHandler
-
-                            PUBWEAK SDIO_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            SDIO_IRQHandler
-                            B SDIO_IRQHandler
-
-                            PUBWEAK TMR5_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR5_IRQHandler
-                            B TMR5_IRQHandler
-
-                            PUBWEAK SPI3_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            SPI3_IRQHandler
-                            B SPI3_IRQHandler
-
-                            PUBWEAK UART4_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            UART4_IRQHandler
-                            B UART4_IRQHandler
-
-                            PUBWEAK UART5_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            UART5_IRQHandler
-                            B UART5_IRQHandler
-
-                            PUBWEAK TMR6_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR6_IRQHandler
-                            B TMR6_IRQHandler
-
-                            PUBWEAK TMR7_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR7_IRQHandler
-                            B TMR7_IRQHandler
-
-                            PUBWEAK DMA2_Channel1_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA2_Channel1_IRQHandler
-                            B DMA2_Channel1_IRQHandler
-
-                            PUBWEAK DMA2_Channel2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA2_Channel2_IRQHandler
-                            B DMA2_Channel2_IRQHandler
-
-                            PUBWEAK DMA2_Channel3_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA2_Channel3_IRQHandler
-                            B DMA2_Channel3_IRQHandler
-
-                            PUBWEAK DMA2_Channel4_5_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA2_Channel4_5_IRQHandler
-                            B DMA2_Channel4_5_IRQHandler
-
-                            PUBWEAK USBD2_HP_CAN2_TX_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USBD2_HP_CAN2_TX_IRQHandler
-                            B USBD2_HP_CAN2_TX_IRQHandler
-
-                            PUBWEAK USBD2_LP_CAN2_RX0_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USBD2_LP_CAN2_RX0_IRQHandler
-                            B USBD2_LP_CAN2_RX0_IRQHandler
-
-                            PUBWEAK CAN2_RX1_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            CAN2_RX1_IRQHandler
-                            B CAN2_RX1_IRQHandler
-
-                            PUBWEAK CAN2_SCE_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            CAN2_SCE_IRQHandler
-                            B CAN2_SCE_IRQHandler
-
-                            END
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDT_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WWDT_IRQHandler
+        B WWDT_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+
+        PUBWEAK TAMPER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TAMPER_IRQHandler
+        B TAMPER_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCM_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RCM_IRQHandler
+        B RCM_IRQHandler
+
+        PUBWEAK EINT0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT0_IRQHandler
+        B EINT0_IRQHandler
+
+        PUBWEAK EINT1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT1_IRQHandler
+        B EINT1_IRQHandler
+
+        PUBWEAK EINT2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT2_IRQHandler
+        B EINT2_IRQHandler
+
+        PUBWEAK EINT3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT3_IRQHandler
+        B EINT3_IRQHandler
+
+        PUBWEAK EINT4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT4_IRQHandler
+        B EINT4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK USBD1_HP_CAN1_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBD1_HP_CAN1_TX_IRQHandler
+        B USBD1_HP_CAN1_TX_IRQHandler
+
+        PUBWEAK USBD1_LP_CAN1_RX0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBD1_LP_CAN1_RX0_IRQHandler
+        B USBD1_LP_CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EINT9_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT9_5_IRQHandler
+        B EINT9_5_IRQHandler
+
+        PUBWEAK TMR1_BRK_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_BRK_IRQHandler
+        B TMR1_BRK_IRQHandler
+
+        PUBWEAK TMR1_UP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_UP_IRQHandler
+        B TMR1_UP_IRQHandler
+
+        PUBWEAK TMR1_TRG_COM_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_TRG_COM_IRQHandler
+        B TMR1_TRG_COM_IRQHandler
+
+        PUBWEAK TMR1_CC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_CC_IRQHandler
+        B TMR1_CC_IRQHandler
+
+        PUBWEAK TMR2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR2_IRQHandler
+        B TMR2_IRQHandler
+
+        PUBWEAK TMR3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR3_IRQHandler
+        B TMR3_IRQHandler
+
+        PUBWEAK TMR4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR4_IRQHandler
+        B TMR4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EINT15_10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT15_10_IRQHandler
+        B EINT15_10_IRQHandler
+
+        PUBWEAK RTCAlarm_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTCAlarm_IRQHandler
+        B RTCAlarm_IRQHandler
+
+        PUBWEAK USBDWakeUp_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBDWakeUp_IRQHandler
+        B USBDWakeUp_IRQHandler
+
+        PUBWEAK TMR8_BRK_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR8_BRK_IRQHandler
+        B TMR8_BRK_IRQHandler
+
+        PUBWEAK TMR8_UP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR8_UP_IRQHandler
+        B TMR8_UP_IRQHandler
+
+        PUBWEAK TMR8_TRG_COM_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR8_TRG_COM_IRQHandler
+        B TMR8_TRG_COM_IRQHandler
+
+        PUBWEAK TMR8_CC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR8_CC_IRQHandler
+        B TMR8_CC_IRQHandler
+
+        PUBWEAK ADC3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC3_IRQHandler
+        B ADC3_IRQHandler
+
+        PUBWEAK EMMC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EMMC_IRQHandler
+        B EMMC_IRQHandler
+
+        PUBWEAK SDIO_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SDIO_IRQHandler
+        B SDIO_IRQHandler
+
+        PUBWEAK TMR5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR5_IRQHandler
+        B TMR5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TMR6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR6_IRQHandler
+        B TMR6_IRQHandler
+
+        PUBWEAK TMR7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR7_IRQHandler
+        B TMR7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel4_5_IRQHandler
+        B DMA2_Channel4_5_IRQHandler
+
+        PUBWEAK USBD2_HP_CAN2_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBD2_HP_CAN2_TX_IRQHandler
+        B USBD2_HP_CAN2_TX_IRQHandler
+
+        PUBWEAK USBD2_LP_CAN2_RX0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBD2_LP_CAN2_RX0_IRQHandler
+        B USBD2_LP_CAN2_RX0_IRQHandler
+
+        PUBWEAK CAN2_RX1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX1_IRQHandler
+        B CAN2_RX1_IRQHandler
+
+        PUBWEAK CAN2_SCE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_SCE_IRQHandler
+        B CAN2_SCE_IRQHandler
+
+        END
 

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_md.s

@@ -5,7 +5,7 @@
 ; *
 ; * @version     V1.0.0
 ; *
-; * @date        2022-01-05
+; * @date        2022-07-25
 ; *
 ; * @attention
 ; *
@@ -15,7 +15,7 @@
 ; *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
 ; *
 ; *  The program is only for reference, which is distributed in the hope
-; *  that it will be usefull and instructional for customers to develop
+; *  that it will be useful and instructional for customers to develop
 ; *  their software. Unless required by applicable law or agreed to in
 ; *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
 ; *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,622 +23,382 @@
 ; *  and limitations under the License.
 ; */
 
-MODULE  ? cstartup
+    MODULE  ?cstartup
 
-;;
-Forward declaration of sections.
-SECTION CSTACK:
-DATA:
-NOROOT(3)
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
 
-SECTION .intvec:
-CODE:
-NOROOT(2)
+        SECTION .intvec:CODE:NOROOT(2)
 
 
-EXTERN  __iar_program_start
-EXTERN  SystemInit
-PUBLIC  __vector_table
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
 
-DATA
+        DATA
 
 __vector_table
-DCD     sfe(CSTACK)
-DCD     Reset_Handler                ;
-Reset Handler
-DCD     NMI_Handler                  ;
-NMI Handler
-DCD     HardFault_Handler            ;
-Hard Fault Handler
-DCD     MemManage_Handler            ;
-MPU Fault Handler
-DCD     BusFault_Handler             ;
-Bus Fault Handler
-DCD     UsageFault_Handler           ;
-Usage Fault Handler
-DCD     0                            ;
-Reserved
-DCD     0                            ;
-Reserved
-DCD     0                            ;
-Reserved
-DCD     0                            ;
-Reserved
-DCD     SVC_Handler                  ;
-SVCall Handler
-DCD     DebugMon_Handler             ;
-Debug Monitor Handler
-DCD     0                            ;
-Reserved
-DCD     PendSV_Handler               ;
-PendSV Handler
-DCD     SysTick_Handler              ;
-SysTick Handler
-
-;
-External Interrupts
-DCD     WWDT_IRQHandler              ;
-Window Watchdog
-DCD     PVD_IRQHandler               ;
-PVD through EINT Line detect
-DCD     TAMPER_IRQHandler            ;
-Tamper
-DCD     RTC_IRQHandler               ;
-RTC
-DCD     FLASH_IRQHandler             ;
-Flash
-DCD     RCM_IRQHandler               ;
-RCM
-DCD     EINT0_IRQHandler             ;
-EINT Line 0
-DCD     EINT1_IRQHandler             ;
-EINT Line 1
-DCD     EINT2_IRQHandler             ;
-EINT Line 2
-DCD     EINT3_IRQHandler             ;
-EINT Line 3
-DCD     EINT4_IRQHandler             ;
-EINT Line 4
-DCD     DMA1_Channel1_IRQHandler     ;
-DMA1 Channel 1
-DCD     DMA1_Channel2_IRQHandler     ;
-DMA1 Channel 2
-DCD     DMA1_Channel3_IRQHandler     ;
-DMA1 Channel 3
-DCD     DMA1_Channel4_IRQHandler     ;
-DMA1 Channel 4
-DCD     DMA1_Channel5_IRQHandler     ;
-DMA1 Channel 5
-DCD     DMA1_Channel6_IRQHandler     ;
-DMA1 Channel 6
-DCD     DMA1_Channel7_IRQHandler     ;
-DMA1 Channel 7
-DCD     ADC1_2_IRQHandler            ;
-ADC1 &ADC2
-DCD     USBD1_HP_CAN1_TX_IRQHandler  ;
-USBD1 High Priority or CAN1 TX
-DCD     USBD1_LP_CAN1_RX0_IRQHandler ;
-USBD1 Low  Priority or CAN1 RX0
-DCD     CAN1_RX1_IRQHandler          ;
-CAN1 RX1
-DCD     CAN1_SCE_IRQHandler          ;
-CAN1 SCE
-DCD     EINT9_5_IRQHandler           ;
-EINT Line 9..5
-DCD     TMR1_BRK_IRQHandler          ;
-TMR1 Break
-DCD     TMR1_UP_IRQHandler           ;
-TMR1 Update
-DCD     TMR1_TRG_COM_IRQHandler      ;
-TMR1 Trigger and Commutation
-DCD     TMR1_CC_IRQHandler           ;
-TMR1 Capture Compare
-DCD     TMR2_IRQHandler              ;
-TMR2
-DCD     TMR3_IRQHandler              ;
-TMR3
-DCD     TMR4_IRQHandler              ;
-TMR4
-DCD     I2C1_EV_IRQHandler           ;
-I2C1 Event
-DCD     I2C1_ER_IRQHandler           ;
-I2C1 Error
-DCD     I2C2_EV_IRQHandler           ;
-I2C2 Event
-DCD     I2C2_ER_IRQHandler           ;
-I2C2 Error
-DCD     SPI1_IRQHandler              ;
-SPI1
-DCD     SPI2_IRQHandler              ;
-SPI2
-DCD     USART1_IRQHandler            ;
-USART1
-DCD     USART2_IRQHandler            ;
-USART2
-DCD     USART3_IRQHandler            ;
-USART3
-DCD     EINT15_10_IRQHandler         ;
-EINT Line 15..10
-DCD     RTCAlarm_IRQHandler          ;
-RTC Alarm through EINT Line
-DCD     USBDWakeUp_IRQHandler        ;
-USBD Wakeup from suspend
-DCD     FPU_IRQHandler               ;
-FPU
-DCD     QSPI_IRQHandler              ;
-QSPI
-DCD     USBD2_HP_IRQHandler          ;
-USBD2 High Priority
-DCD     USBD2_LP_IRQHandler          ;
-USBD2 Low Priority
+        DCD     sfe(CSTACK)
+                DCD     Reset_Handler                ; Reset Handler
+                DCD     NMI_Handler                  ; NMI Handler
+                DCD     HardFault_Handler            ; Hard Fault Handler
+                DCD     MemManage_Handler            ; MPU Fault Handler
+                DCD     BusFault_Handler             ; Bus Fault Handler
+                DCD     UsageFault_Handler           ; Usage Fault Handler
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     0                            ; Reserved
+                DCD     SVC_Handler                  ; SVCall Handler
+                DCD     DebugMon_Handler             ; Debug Monitor Handler
+                DCD     0                            ; Reserved
+                DCD     PendSV_Handler               ; PendSV Handler
+                DCD     SysTick_Handler              ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDT_IRQHandler              ; Window Watchdog
+                DCD     PVD_IRQHandler               ; PVD through EINT Line detect
+                DCD     TAMPER_IRQHandler            ; Tamper
+                DCD     RTC_IRQHandler               ; RTC
+                DCD     FLASH_IRQHandler             ; Flash
+                DCD     RCM_IRQHandler               ; RCM
+                DCD     EINT0_IRQHandler             ; EINT Line 0
+                DCD     EINT1_IRQHandler             ; EINT Line 1
+                DCD     EINT2_IRQHandler             ; EINT Line 2
+                DCD     EINT3_IRQHandler             ; EINT Line 3
+                DCD     EINT4_IRQHandler             ; EINT Line 4
+                DCD     DMA1_Channel1_IRQHandler     ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler     ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler     ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler     ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler     ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler     ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler     ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler            ; ADC1 & ADC2
+                DCD     USBD1_HP_CAN1_TX_IRQHandler  ; USBD1 High Priority or CAN1 TX
+                DCD     USBD1_LP_CAN1_RX0_IRQHandler ; USBD1 Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler          ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler          ; CAN1 SCE
+                DCD     EINT9_5_IRQHandler           ; EINT Line 9..5
+                DCD     TMR1_BRK_IRQHandler          ; TMR1 Break
+                DCD     TMR1_UP_IRQHandler           ; TMR1 Update
+                DCD     TMR1_TRG_COM_IRQHandler      ; TMR1 Trigger and Commutation
+                DCD     TMR1_CC_IRQHandler           ; TMR1 Capture Compare
+                DCD     TMR2_IRQHandler              ; TMR2
+                DCD     TMR3_IRQHandler              ; TMR3
+                DCD     TMR4_IRQHandler              ; TMR4
+                DCD     I2C1_EV_IRQHandler           ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler           ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler           ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler           ; I2C2 Error
+                DCD     SPI1_IRQHandler              ; SPI1
+                DCD     SPI2_IRQHandler              ; SPI2
+                DCD     USART1_IRQHandler            ; USART1
+                DCD     USART2_IRQHandler            ; USART2
+                DCD     USART3_IRQHandler            ; USART3
+                DCD     EINT15_10_IRQHandler         ; EINT Line 15..10
+                DCD     RTCAlarm_IRQHandler          ; RTC Alarm through EINT Line
+                DCD     USBDWakeUp_IRQHandler        ; USBD Wakeup from suspend
+                DCD     FPU_IRQHandler               ; FPU
+                DCD     QSPI_IRQHandler              ; QSPI
+                DCD     USBD2_HP_IRQHandler          ; USBD2 High Priority
+                DCD     USBD2_LP_IRQHandler          ; USBD2 Low Priority
 __Vectors_End
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
+;; Default interrupt handlers.
 ;;
-Default interrupt handlers.
-;;
-THUMB
+        THUMB
 
-PUBWEAK Reset_Handler
-SECTION .text:
-CODE:
-REORDER:
-NOROOT(2)
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
 Reset_Handler
-LDR     R0, = SystemInit
-              BLX     R0
-              LDR     R0, = __iar_program_start
-                            BX      R0
-
-                            PUBWEAK NMI_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            NMI_Handler
-                            B NMI_Handler
-
-                            PUBWEAK HardFault_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            HardFault_Handler
-                            B HardFault_Handler
-
-                            PUBWEAK MemManage_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            MemManage_Handler
-                            B MemManage_Handler
-
-                            PUBWEAK BusFault_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            BusFault_Handler
-                            B BusFault_Handler
-
-                            PUBWEAK UsageFault_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            UsageFault_Handler
-                            B UsageFault_Handler
-
-                            PUBWEAK SVC_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            SVC_Handler
-                            B SVC_Handler
-
-                            PUBWEAK DebugMon_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DebugMon_Handler
-                            B DebugMon_Handler
-
-                            PUBWEAK PendSV_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            PendSV_Handler
-                            B PendSV_Handler
-
-                            PUBWEAK SysTick_Handler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            SysTick_Handler
-                            B SysTick_Handler
-
-                            PUBWEAK WWDT_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            WWDT_IRQHandler
-                            B WWDT_IRQHandler
-
-                            PUBWEAK PVD_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            PVD_IRQHandler
-                            B PVD_IRQHandler
-
-                            PUBWEAK TAMPER_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TAMPER_IRQHandler
-                            B TAMPER_IRQHandler
-
-                            PUBWEAK RTC_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            RTC_IRQHandler
-                            B RTC_IRQHandler
-
-                            PUBWEAK FLASH_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            FLASH_IRQHandler
-                            B FLASH_IRQHandler
-
-                            PUBWEAK RCM_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            RCM_IRQHandler
-                            B RCM_IRQHandler
-
-                            PUBWEAK EINT0_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT0_IRQHandler
-                            B EINT0_IRQHandler
-
-                            PUBWEAK EINT1_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT1_IRQHandler
-                            B EINT1_IRQHandler
-
-                            PUBWEAK EINT2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT2_IRQHandler
-                            B EINT2_IRQHandler
-
-                            PUBWEAK EINT3_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT3_IRQHandler
-                            B EINT3_IRQHandler
-
-                            PUBWEAK EINT4_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT4_IRQHandler
-                            B EINT4_IRQHandler
-
-                            PUBWEAK DMA1_Channel1_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel1_IRQHandler
-                            B DMA1_Channel1_IRQHandler
-
-                            PUBWEAK DMA1_Channel2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel2_IRQHandler
-                            B DMA1_Channel2_IRQHandler
-
-                            PUBWEAK DMA1_Channel3_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel3_IRQHandler
-                            B DMA1_Channel3_IRQHandler
-
-                            PUBWEAK DMA1_Channel4_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel4_IRQHandler
-                            B DMA1_Channel4_IRQHandler
-
-                            PUBWEAK DMA1_Channel5_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel5_IRQHandler
-                            B DMA1_Channel5_IRQHandler
-
-                            PUBWEAK DMA1_Channel6_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel6_IRQHandler
-                            B DMA1_Channel6_IRQHandler
-
-                            PUBWEAK DMA1_Channel7_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            DMA1_Channel7_IRQHandler
-                            B DMA1_Channel7_IRQHandler
-
-                            PUBWEAK ADC1_2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            ADC1_2_IRQHandler
-                            B ADC1_2_IRQHandler
-
-                            PUBWEAK USBD1_HP_CAN1_TX_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USBD1_HP_CAN1_TX_IRQHandler
-                            B USBD1_HP_CAN1_TX_IRQHandler
-
-                            PUBWEAK USBD1_LP_CAN1_RX0_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USBD1_LP_CAN1_RX0_IRQHandler
-                            B USBD1_LP_CAN1_RX0_IRQHandler
-
-                            PUBWEAK CAN1_RX1_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            CAN1_RX1_IRQHandler
-                            B CAN1_RX1_IRQHandler
-
-                            PUBWEAK CAN1_SCE_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            CAN1_SCE_IRQHandler
-                            B CAN1_SCE_IRQHandler
-
-                            PUBWEAK EINT9_5_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT9_5_IRQHandler
-                            B EINT9_5_IRQHandler
-
-                            PUBWEAK TMR1_BRK_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR1_BRK_IRQHandler
-                            B TMR1_BRK_IRQHandler
-
-                            PUBWEAK TMR1_UP_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR1_UP_IRQHandler
-                            B TMR1_UP_IRQHandler
-
-                            PUBWEAK TMR1_TRG_COM_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR1_TRG_COM_IRQHandler
-                            B TMR1_TRG_COM_IRQHandler
-
-                            PUBWEAK TMR1_CC_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR1_CC_IRQHandler
-                            B TMR1_CC_IRQHandler
-
-                            PUBWEAK TMR2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR2_IRQHandler
-                            B TMR2_IRQHandler
-
-                            PUBWEAK TMR3_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR3_IRQHandler
-                            B TMR3_IRQHandler
-
-                            PUBWEAK TMR4_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            TMR4_IRQHandler
-                            B TMR4_IRQHandler
-
-                            PUBWEAK I2C1_EV_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            I2C1_EV_IRQHandler
-                            B I2C1_EV_IRQHandler
-
-                            PUBWEAK I2C1_ER_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            I2C1_ER_IRQHandler
-                            B I2C1_ER_IRQHandler
-
-                            PUBWEAK I2C2_EV_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            I2C2_EV_IRQHandler
-                            B I2C2_EV_IRQHandler
-
-                            PUBWEAK I2C2_ER_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            I2C2_ER_IRQHandler
-                            B I2C2_ER_IRQHandler
-
-                            PUBWEAK SPI1_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            SPI1_IRQHandler
-                            B SPI1_IRQHandler
-
-                            PUBWEAK SPI2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            SPI2_IRQHandler
-                            B SPI2_IRQHandler
-
-                            PUBWEAK USART1_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USART1_IRQHandler
-                            B USART1_IRQHandler
-
-                            PUBWEAK USART2_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USART2_IRQHandler
-                            B USART2_IRQHandler
-
-                            PUBWEAK USART3_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USART3_IRQHandler
-                            B USART3_IRQHandler
-
-                            PUBWEAK EINT15_10_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            EINT15_10_IRQHandler
-                            B EINT15_10_IRQHandler
-
-                            PUBWEAK RTCAlarm_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            RTCAlarm_IRQHandler
-                            B RTCAlarm_IRQHandler
-
-                            PUBWEAK USBDWakeUp_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USBDWakeUp_IRQHandler
-                            B USBDWakeUp_IRQHandler
-
-                            PUBWEAK FPU_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            FPU_IRQHandler
-                            B FPU_IRQHandler
-
-                            PUBWEAK QSPI_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            QSPI_IRQHandler
-                            B QSPI_IRQHandler
-
-                            PUBWEAK USBD2_HP_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USBD2_HP_IRQHandler
-                            B USBD2_HP_IRQHandler
-
-                            PUBWEAK USBD2_LP_IRQHandler
-                            SECTION .text:
-                            CODE:
-                            REORDER:
-                            NOROOT(1)
-                            USBD2_LP_IRQHandler
-                            B USBD2_LP_IRQHandler
-
-
-                            END
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDT_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WWDT_IRQHandler
+        B WWDT_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+
+        PUBWEAK TAMPER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TAMPER_IRQHandler
+        B TAMPER_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCM_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RCM_IRQHandler
+        B RCM_IRQHandler
+
+        PUBWEAK EINT0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT0_IRQHandler
+        B EINT0_IRQHandler
+
+        PUBWEAK EINT1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT1_IRQHandler
+        B EINT1_IRQHandler
+
+        PUBWEAK EINT2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT2_IRQHandler
+        B EINT2_IRQHandler
+
+        PUBWEAK EINT3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT3_IRQHandler
+        B EINT3_IRQHandler
+
+        PUBWEAK EINT4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT4_IRQHandler
+        B EINT4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK USBD1_HP_CAN1_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBD1_HP_CAN1_TX_IRQHandler
+        B USBD1_HP_CAN1_TX_IRQHandler
+
+        PUBWEAK USBD1_LP_CAN1_RX0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBD1_LP_CAN1_RX0_IRQHandler
+        B USBD1_LP_CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EINT9_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT9_5_IRQHandler
+        B EINT9_5_IRQHandler
+
+        PUBWEAK TMR1_BRK_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_BRK_IRQHandler
+        B TMR1_BRK_IRQHandler
+
+        PUBWEAK TMR1_UP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_UP_IRQHandler
+        B TMR1_UP_IRQHandler
+
+        PUBWEAK TMR1_TRG_COM_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_TRG_COM_IRQHandler
+        B TMR1_TRG_COM_IRQHandler
+
+        PUBWEAK TMR1_CC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_CC_IRQHandler
+        B TMR1_CC_IRQHandler
+
+        PUBWEAK TMR2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR2_IRQHandler
+        B TMR2_IRQHandler
+
+        PUBWEAK TMR3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR3_IRQHandler
+        B TMR3_IRQHandler
+
+        PUBWEAK TMR4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR4_IRQHandler
+        B TMR4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EINT15_10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EINT15_10_IRQHandler
+        B EINT15_10_IRQHandler
+
+        PUBWEAK RTCAlarm_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTCAlarm_IRQHandler
+        B RTCAlarm_IRQHandler
+
+        PUBWEAK USBDWakeUp_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBDWakeUp_IRQHandler
+        B USBDWakeUp_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK QSPI_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+QSPI_IRQHandler
+        B QSPI_IRQHandler
+
+        PUBWEAK USBD2_HP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBD2_HP_IRQHandler
+        B USBD2_HP_IRQHandler
+
+        PUBWEAK USBD2_LP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBD2_LP_IRQHandler
+        B USBD2_LP_IRQHandler
+
+
+        END
 

project_0/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c

@@ -3,9 +3,9 @@
  *
  * @brief       CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
  *
- * @version     V1.0.2
+ * @version     V1.0.4
  *
- * @date        2022-01-05
+ * @date        2022-12-01
  *
  * @attention
  *
@@ -15,7 +15,7 @@
  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  *
  *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
+ *  that it will be useful and instructional for customers to develop
  *  their software. Unless required by applicable law or agreed to in
  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
@@ -23,12 +23,21 @@
  *  and limitations under the License.
  */
 
+/*Includes*/
 #include "apm32f10x.h"
 
-/*****************************************************************
- * If SYSCLK source is PLL,SystemCoreClock will contain the      *
- * HSE_VALUE or HSI_VALUE multiplied/divided by the PLL factors. *
-******************************************************************/
+/** @addtogroup CMSIS
+  @{
+*/
+
+/** @addtogroup APM32F10x_System
+  * @brief APM32F10x system configuration
+  @{
+*/
+
+/** @defgroup System_Macros
+  @{
+*/
 
 //#define SYSTEM_CLOCK_HSE    HSE_VALUE
 //#define SYSTEM_CLOCK_24MHz  (24000000)
@@ -38,10 +47,15 @@
 #define SYSTEM_CLOCK_72MHz  (72000000)
 //#define SYSTEM_CLOCK_96MHz  (96000000)
 
-
-/** #define VECT_TAB_SRAM */
+/* #define VECT_TAB_SRAM */
 #define VECT_TAB_OFFSET     0x00
 
+/**@} end of group System_Macros*/
+
+/** @defgroup System_Variables
+  @{
+*/
+
 #ifdef SYSTEM_CLOCK_HSE
     uint32_t SystemCoreClock         = SYSTEM_CLOCK_HSE;
 #elif defined SYSTEM_CLOCK_24MHz
@@ -58,6 +72,11 @@
     uint32_t SystemCoreClock         = SYSTEM_CLOCK_96MHz;
 #endif
 
+/**@} end of group System_Variables */
+
+/** @defgroup System_Functions
+  @{
+*/
 
 static void SystemClockConfig(void);
 
@@ -87,18 +106,34 @@ static void SystemClockConfig(void);
  */
 void SystemInit(void)
 {
-    /** Set HSIEN bit */
+    /* Set HSIEN bit */
     RCM->CTRL_B.HSIEN = BIT_SET;
-    /** Reset SCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */
-    RCM->CFG &= (uint32_t)0xF8FF0000;
-    /** Reset HSEEN, CSSEN and PLLEN bits */
-    RCM->CTRL &= (uint32_t)0xFEF6FFFF;
-    /** Reset HSEBCFG bit */
+
+#ifdef APM32F10X_CL
+    RCM->CFG &= (uint32_t) 0xF0FF0000;
+#else
+    /* Reset SCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */
+    RCM->CFG &= (uint32_t) 0xF8FF0000;
+#endif /* APM32F10X_CL */
+
+    /* Reset HSEEN, CSSEN and PLLEN bits */
+    RCM->CTRL &= (uint32_t) 0xFEF6FFFF;
+    /* Reset HSEBCFG bit */
     RCM->CTRL_B.HSEBCFG = BIT_RESET;
-    /** Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */
-    RCM->CFG &= (uint32_t)0xFF80FFFF;
-    /** Disable all interrupts and clear pending bits */
+    /* Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */
+    RCM->CFG &= (uint32_t) 0xFF80FFFF;
+
+#ifdef APM32F10X_CL
+    /* Reset PLL2ON and PLL3ON bits */
+    RCM->CTRL &= (uint32_t) 0xEBFFFFFF;
+    /* Disable all interrupts and clear pending bits  */
+    RCM->INT = 0x00FF0000;
+    /* Reset CFG2 register */
+    RCM->CFG2 = 0x00000000;
+#else
+    /* Disable all interrupts and clear pending bits */
     RCM->INT = 0x009F0000;
+#endif /* APM32F10X_CL */
 
     SystemClockConfig();
 
@@ -120,53 +155,98 @@ void SystemInit(void)
  */
 void SystemCoreClockUpdate(void)
 {
-    uint32_t sysClock, pllMull, pllSource, Prescaler;
-    uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+#ifdef APM32F10X_CL
+    uint32_t sysClock, pllMull, pllSource, pll2Mull, pllPsc1, pllPsc2;
+#else
+    uint32_t sysClock, pllMull, pllSource;
+#endif
 
-    sysClock = RCM->CFG_B.SCLKSELSTS;
+    /* get sys clock */
+    sysClock = RCM->CFG_B.SCLKSEL;
 
     switch (sysClock)
     {
-    /** sys clock is HSI */
-    case 0:
-        SystemCoreClock = HSI_VALUE;
-        break;
-
-    /** sys clock is HSE */
-    case 1:
-        SystemCoreClock = HSE_VALUE;
-        break;
-
-    /** sys clock is PLL */
-    case 2:
-        pllMull = RCM->CFG_B.PLLMULCFG + 2;
-        pllSource = RCM->CFG_B.PLLSRCSEL;
-
-        /** PLL entry clock source is HSE */
-        if (pllSource == BIT_SET)
-        {
-            SystemCoreClock = HSE_VALUE * pllMull;
+        /* sys clock is HSI */
+        case 0:
+            sysClock = HSI_VALUE;
+            break;
+
+        /* sys clock is HSE */
+        case 1:
+            sysClock = HSE_VALUE;
+            break;
+
+        /* sys clock is PLL */
+        case 2:
+#ifdef APM32F10X_CL
+            /* NOTE : PLL is the same as PLL1 */
+            pllSource = RCM->CFG_B.PLL1SRCSEL;
 
-            /** HSE clock divided by 2 */
-            if (pllSource == RCM->CFG_B.PLLHSEPSC)
+            /* PLL entry clock source is HSE */
+            if (pllSource)
             {
-                SystemCoreClock >>= 1;
+                /* PLLPSC1 prescaler factor */
+                pllPsc1 = (RCM->CFG2_B.PLLPSC1 + 1);
+
+                /* PLL entry clock source is PLL2 */
+                if (RCM->CFG2_B.PLLPSC1SRC)
+                {
+                    pll2Mull = (RCM->CFG2_B.PLL2MUL != 15) ? (RCM->CFG2_B.PLL2MUL + 2) : 20;
+                    pllPsc2 = RCM->CFG2_B.PLLPSC2 + 1;
+
+                    pllSource = ((HSE_VALUE / pllPsc2) * pll2Mull) / pllPsc1;
+                }
+                /* PLL entry clock source is HSE */
+                else
+                {
+                    pllSource = HSE_VALUE / pllPsc1;
+                }
             }
-        }
-        /** PLL entry clock source is HSI/2 */
-        else
-        {
-            SystemCoreClock = (HSI_VALUE >> 1) * pllMull;
-        }
-        break;
+            /* PLL entry clock source is HSI/2 */
+            else
+            {
+                pllSource = HSI_VALUE >> 1;
+            }
+
+            pllMull = RCM->CFG_B.PLL1MULCFG;
+            if (pllMull == 13)
+            {
+                /* For 6.5 multiplication factor */
+                sysClock = pllSource * pllMull / 2;
+            }
+            else
+            {
+                sysClock = pllSource * (pllMull + 2);
+            }
+#else
+            pllMull = RCM->CFG_B.PLL1MULCFG + 2;
+            pllSource = RCM->CFG_B.PLL1SRCSEL;
+
+            /* PLL entry clock source is HSE */
+            if (pllSource == BIT_SET)
+            {
+                sysClock = HSE_VALUE * pllMull;
+
+                /* HSE clock divided by 2 */
+                if (pllSource == RCM->CFG_B.PLLHSEPSC)
+                {
+                    sysClock >>= 1;
+                }
+            }
+            /* PLL entry clock source is HSI/2 */
+            else
+            {
+                sysClock = (HSI_VALUE >> 1) * pllMull;
+            }
+#endif
+            break;
 
-    default:
-        SystemCoreClock  = HSI_VALUE;
-        break;
+        default:
+            sysClock  = HSI_VALUE;
+            break;
     }
 
-    Prescaler = AHBPrescTable[RCM->CFG_B.AHBPSC];
-    SystemCoreClock >>= Prescaler;
+    SystemCoreClock = sysClock;
 }
 
 /*!
@@ -221,27 +301,42 @@ static void SystemClockHSE(void)
 
     if (RCM->CTRL_B.HSERDYFLG)
     {
-        /** Enable Prefetch Buffer */
+        /* Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /** Flash 0 wait state */
+
+#ifdef APM32F10X_CL
+
+        if (HSE_VALUE <= 24000000)
+        {
+            /* Flash 0 wait state */
+            FMC->CTRL1_B.WS = 0;
+        }
+        else
+        {
+            /* Flash 1 wait state */
+            FMC->CTRL1_B.WS = 1;
+        }
+
+#else
+        /* Flash 0 wait state */
         FMC->CTRL1_B.WS = 0;
+#endif /* APM32F10X_CL */
 
-        /** HCLK = SYSCLK */
+        /* HCLK = SYSCLK */
         RCM->CFG_B.AHBPSC = 0X00;
-        /** PCLK2 = HCLK */
+        /* PCLK2 = HCLK */
         RCM->CFG_B.APB2PSC = 0;
-        /** PCLK1 = HCLK */
+        /* PCLK1 = HCLK */
         RCM->CFG_B.APB1PSC = 0;
 
-        /** Select HSE as system clock source */
+        /* Select HSE as system clock source */
         RCM->CFG_B.SCLKSEL = 1;
 
-        /** Wait till HSE is used as system clock source */
+        /* Wait till HSE is used as system clock source */
         while (RCM->CFG_B.SCLKSELSTS != 0x01);
     }
 }
 
-
 #elif defined SYSTEM_CLOCK_24MHz
 /*!
  * @brief       Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers
@@ -267,31 +362,53 @@ static void SystemClock24M(void)
 
     if (RCM->CTRL_B.HSERDYFLG)
     {
-        /** Enable Prefetch Buffer */
+        /* Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /** Flash 0 wait state */
+        /* Flash 0 wait state */
         FMC->CTRL1_B.WS = 0;
 
-        /** HCLK = SYSCLK */
+        /* HCLK = SYSCLK */
         RCM->CFG_B.AHBPSC = 0X00;
-        /** PCLK2 = HCLK */
+        /* PCLK2 = HCLK */
         RCM->CFG_B.APB2PSC = 0;
-        /** PCLK1 = HCLK */
+        /* PCLK1 = HCLK */
         RCM->CFG_B.APB1PSC = 0;
 
-        /** PLL: (HSE / 2) * 6 */
-        RCM->CFG_B.PLLSRCSEL = 1;
+#ifdef APM32F10X_CL
+        /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */
+        /* PLL configuration: PLLCLK = (PLL2 / 10) * 6 = 24 MHz */
+
+        RCM->CFG2_B.PLLPSC2 = 4;
+        RCM->CFG2_B.PLL2MUL = 0x06;
+
+        RCM->CFG2_B.PLLPSC1SRC = 1;
+        RCM->CFG2_B.PLLPSC1 = 9;
+
+        /* Enable PLL2 */
+        RCM->CTRL_B.PLL2EN = 1;
+        /* Wait till PLL2 is ready */
+        while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET);
+
+        RCM->CFG_B.PLL1SRCSEL = 1;
+        RCM->CFG_B.PLL1MULCFG = 4;
+#else
+        /*  PLL configuration: PLLCLK = (HSE / 2) * 6 = 24 MHz */
+        /* PLL: (HSE / 2) * 6 */
+        RCM->CFG_B.PLL1SRCSEL = 1;
         RCM->CFG_B.PLLHSEPSC = 1;
-        RCM->CFG_B.PLLMULCFG = 4;
+        RCM->CFG_B.PLL1MULCFG = 4;
+#endif /* APM32F10X_CL */
+
+        /* Enable PLL */
+        RCM->CTRL_B.PLL1EN = 1;
 
-        /** Enable PLL */
-        RCM->CTRL_B.PLLEN = 1;
-        /** Wait PLL Ready */
-        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        /* Wait PLL Ready */
+        while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET);
 
-        /** Select PLL as system clock source */
+        /* Select PLL as system clock source */
         RCM->CFG_B.SCLKSEL = 2;
-        /** Wait till PLL is used as system clock source */
+
+        /* Wait till PLL is used as system clock source */
         while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
@@ -321,31 +438,53 @@ static void SystemClock36M(void)
 
     if (RCM->CTRL_B.HSERDYFLG)
     {
-        /** Enable Prefetch Buffer */
+        /* Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /** Flash 1 wait state */
+        /* Flash 1 wait state */
         FMC->CTRL1_B.WS = 1;
 
-        /** HCLK = SYSCLK */
+        /* HCLK = SYSCLK */
         RCM->CFG_B.AHBPSC = 0X00;
-        /** PCLK2 = HCLK */
+        /* PCLK2 = HCLK */
         RCM->CFG_B.APB2PSC = 0;
-        /** PCLK1 = HCLK */
+        /* PCLK1 = HCLK */
         RCM->CFG_B.APB1PSC = 0;
 
-        /** PLL: (HSE / 2) * 9 */
-        RCM->CFG_B.PLLSRCSEL = 1;
+#ifdef APM32F10X_CL
+        /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */
+        /* PLL configuration: PLLCLK = (PLL2 / 10) * 9 = 36 MHz */
+
+        RCM->CFG2_B.PLLPSC2 = 4;
+        RCM->CFG2_B.PLL2MUL = 0x06;
+
+        RCM->CFG2_B.PLLPSC1SRC = 1;
+        RCM->CFG2_B.PLLPSC1 = 9;
+
+        /* Enable PLL2 */
+        RCM->CTRL_B.PLL2EN = 1;
+        /* Wait till PLL2 is ready */
+        while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET);
+
+        RCM->CFG_B.PLL1SRCSEL = 1;
+        RCM->CFG_B.PLL1MULCFG = 7;
+#else
+        /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+        /* PLL: (HSE / 2) * 9 */
+        RCM->CFG_B.PLL1SRCSEL = 1;
         RCM->CFG_B.PLLHSEPSC = 1;
-        RCM->CFG_B.PLLMULCFG = 7;
+        RCM->CFG_B.PLL1MULCFG = 7;
+#endif
+
+        /* Enable PLL */
+        RCM->CTRL_B.PLL1EN = 1;
 
-        /** Enable PLL */
-        RCM->CTRL_B.PLLEN = 1;
-        /** Wait PLL Ready */
-        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        /* Wait PLL Ready */
+        while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET);
 
-        /** Select PLL as system clock source */
+        /* Select PLL as system clock source */
         RCM->CFG_B.SCLKSEL = 2;
-        /** Wait till PLL is used as system clock source */
+
+        /* Wait till PLL is used as system clock source */
         while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
@@ -375,30 +514,51 @@ static void SystemClock48M(void)
 
     if (RCM->CTRL_B.HSERDYFLG)
     {
-        /** Enable Prefetch Buffer */
+        /* Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /** Flash 1 wait state */
+        /* Flash 1 wait state */
         FMC->CTRL1_B.WS = 1;
 
-        /** HCLK = SYSCLK */
+        /* HCLK = SYSCLK */
         RCM->CFG_B.AHBPSC = 0X00;
-        /** PCLK2 = HCLK */
+        /* PCLK2 = HCLK */
         RCM->CFG_B.APB2PSC = 0;
-        /** PCLK1 = HCLK / 2 */
+        /* PCLK1 = HCLK / 2 */
         RCM->CFG_B.APB1PSC = 4;
 
-        /** PLL: HSE * 6 */
-        RCM->CFG_B.PLLSRCSEL = 1;
-        RCM->CFG_B.PLLMULCFG = 4;
+#ifdef APM32F10X_CL
+        /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */
+        /* PLL configuration: PLLCLK = (PLL2 / 5) * 6 = 48 MHz */
+
+        RCM->CFG2_B.PLLPSC2 = 4;
+        RCM->CFG2_B.PLL2MUL = 0x06;
+
+        RCM->CFG2_B.PLLPSC1SRC = 1;
+        RCM->CFG2_B.PLLPSC1 = 0x4;
+
+        /* Enable PLL2 */
+        RCM->CTRL_B.PLL2EN = 1;
+        /* Wait till PLL2 is ready */
+        while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET);
 
-        /** Enable PLL */
-        RCM->CTRL_B.PLLEN = 1;
-        /** Wait PLL Ready */
-        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        RCM->CFG_B.PLL1SRCSEL = 1;
+        RCM->CFG_B.PLL1MULCFG = 4;
+#else
+        /* PLL: HSE * 6 */
+        RCM->CFG_B.PLL1SRCSEL = 1;
+        RCM->CFG_B.PLL1MULCFG = 4;
+#endif
+
+        /* Enable PLL */
+        RCM->CTRL_B.PLL1EN = 1;
 
-        /** Select PLL as system clock source */
+        /* Wait PLL Ready */
+        while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET);
+
+        /* Select PLL as system clock source */
         RCM->CFG_B.SCLKSEL = 2;
-        /** Wait till PLL is used as system clock source */
+
+        /* Wait till PLL is used as system clock source */
         while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
@@ -428,30 +588,51 @@ static void SystemClock56M(void)
 
     if (RCM->CTRL_B.HSERDYFLG)
     {
-        /** Enable Prefetch Buffer */
+        /* Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /** Flash 2 wait state */
+        /* Flash 2 wait state */
         FMC->CTRL1_B.WS = 2;
 
-        /** HCLK = SYSCLK */
+        /* HCLK = SYSCLK */
         RCM->CFG_B.AHBPSC = 0X00;
-        /** PCLK2 = HCLK */
+        /* PCLK2 = HCLK */
         RCM->CFG_B.APB2PSC = 0;
-        /** PCLK1 = HCLK / 2 */
+        /* PCLK1 = HCLK / 2 */
         RCM->CFG_B.APB1PSC = 4;
 
-        /** PLL: HSE * 7 */
-        RCM->CFG_B.PLLSRCSEL = 1;
-        RCM->CFG_B.PLLMULCFG = 5;
+#ifdef APM32F10X_CL
+        /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */
+        /* PLL configuration: PLLCLK = (PLL2 / 5) * 7 = 56 MHz */
+
+        RCM->CFG2_B.PLLPSC2 = 4;
+        RCM->CFG2_B.PLL2MUL = 0x06;
 
-        /** Enable PLL */
-        RCM->CTRL_B.PLLEN = 1;
-        /** Wait PLL Ready */
-        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        RCM->CFG2_B.PLLPSC1SRC = 1;
+        RCM->CFG2_B.PLLPSC1 = 0x4;
 
-        /** Select PLL as system clock source */
+        /* Enable PLL2 */
+        RCM->CTRL_B.PLL2EN = 1;
+        /* Wait till PLL2 is ready */
+        while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET);
+
+        RCM->CFG_B.PLL1SRCSEL = 1;
+        RCM->CFG_B.PLL1MULCFG = 5;
+#else
+        /* PLL: HSE * 7 */
+        RCM->CFG_B.PLL1SRCSEL = 1;
+        RCM->CFG_B.PLL1MULCFG = 5;
+#endif
+
+        /* Enable PLL */
+        RCM->CTRL_B.PLL1EN = 1;
+
+        /* Wait PLL Ready */
+        while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET);
+
+        /* Select PLL as system clock source */
         RCM->CFG_B.SCLKSEL = 2;
-        /** Wait till PLL is used as system clock source */
+
+        /* Wait till PLL is used as system clock source */
         while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
@@ -481,30 +662,51 @@ static void SystemClock72M(void)
 
     if (RCM->CTRL_B.HSERDYFLG)
     {
-        /** Enable Prefetch Buffer */
+        /* Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /** Flash 2 wait state */
+        /* Flash 2 wait state */
         FMC->CTRL1_B.WS = 2;
 
-        /** HCLK = SYSCLK */
+        /* HCLK = SYSCLK */
         RCM->CFG_B.AHBPSC = 0X00;
-        /** PCLK2 = HCLK */
+        /* PCLK2 = HCLK */
         RCM->CFG_B.APB2PSC = 0;
-        /** PCLK1 = HCLK / 2 */
+        /* PCLK1 = HCLK / 2 */
         RCM->CFG_B.APB1PSC = 4;
 
-        /** PLL: HSE * 9 */
-        RCM->CFG_B.PLLSRCSEL = 1;
-        RCM->CFG_B.PLLMULCFG = 7;
+#ifdef APM32F10X_CL
+        /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz (HSE is 25MHz for APM32F10X_CL) */
+        /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */
+
+        RCM->CFG2_B.PLLPSC2 = 4;
+        RCM->CFG2_B.PLL2MUL = 0x06;
+
+        RCM->CFG2_B.PLLPSC1SRC = 1;
+        RCM->CFG2_B.PLLPSC1 = 0x4;
 
-        /** Enable PLL */
-        RCM->CTRL_B.PLLEN = 1;
-        /** Wait PLL Ready */
-        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        /* Enable PLL2 */
+        RCM->CTRL_B.PLL2EN = 1;
+        /* Wait till PLL2 is ready */
+        while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET);
+
+        RCM->CFG_B.PLL1SRCSEL = 1;
+        RCM->CFG_B.PLL1MULCFG = 7;
+#else
+        /* PLL: HSE * 9 */
+        RCM->CFG_B.PLL1SRCSEL = 1;
+        RCM->CFG_B.PLL1MULCFG = 7;
+#endif
 
-        /** Select PLL as system clock source */
+        /* Enable PLL */
+        RCM->CTRL_B.PLL1EN = 1;
+
+        /* Wait PLL Ready */
+        while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET);
+
+        /* Select PLL as system clock source */
         RCM->CFG_B.SCLKSEL = 2;
-        /** Wait till PLL is used as system clock source */
+
+        /* Wait till PLL is used as system clock source */
         while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 
@@ -535,32 +737,56 @@ static void SystemClock96M(void)
 
     if (RCM->CTRL_B.HSERDYFLG)
     {
-        /** Enable Prefetch Buffer */
+        /* Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
-        /** Flash 3 wait state */
+        /* Flash 3 wait state */
         FMC->CTRL1_B.WS = 3;
 
-        /** HCLK = SYSCLK */
+        /* HCLK = SYSCLK */
         RCM->CFG_B.AHBPSC = 0X00;
-        /** PCLK2 = HCLK */
+        /* PCLK2 = HCLK */
         RCM->CFG_B.APB2PSC = 0;
-        /** PCLK1 = HCLK / 2 */
+        /* PCLK1 = HCLK / 2 */
         RCM->CFG_B.APB1PSC = 4;
 
-        /** PLL: HSE * 12 */
-        RCM->CFG_B.PLLSRCSEL = 1;
-        RCM->CFG_B.PLLMULCFG = 10;
+#ifdef APM32F10X_CL
+        /* PLL2 configuration: PLL2CLK = (HSE / 5) * 12 = 60 MHz (HSE is 25MHz for APM32F10X_CL) */
+        /* PLL configuration: PLLCLK = (PLL2 / 5) * 8 = 96 MHz */
 
-        /** Enable PLL */
-        RCM->CTRL_B.PLLEN = 1;
-        /** Wait PLL Ready */
-        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        RCM->CFG2_B.PLLPSC2 = 4;
+        RCM->CFG2_B.PLL2MUL = 10;
 
-        /** Select PLL as system clock source */
+        RCM->CFG2_B.PLLPSC1SRC = 1;
+        RCM->CFG2_B.PLLPSC1 = 4;
+
+        /* Enable PLL2 */
+        RCM->CTRL_B.PLL2EN = 1;
+        /* Wait till PLL2 is ready */
+        while (RCM->CTRL_B.PLL2RDYFLG == BIT_RESET);
+
+        RCM->CFG_B.PLL1SRCSEL = 1;
+        RCM->CFG_B.PLL1MULCFG = 6;
+#else
+        /* PLL: HSE * 12 */
+        RCM->CFG_B.PLL1SRCSEL = 1;
+        RCM->CFG_B.PLL1MULCFG = 10;
+#endif
+
+        /* Enable PLL */
+        RCM->CTRL_B.PLL1EN = 1;
+
+        /* Wait PLL Ready */
+        while (RCM->CTRL_B.PLL1RDYFLG == BIT_RESET);
+
+        /* Select PLL as system clock source */
         RCM->CFG_B.SCLKSEL = 2;
-        /** Wait till PLL is used as system clock source */
+
+        /* Wait till PLL is used as system clock source */
         while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
 #endif
 
+/**@} end of group System_Functions */
+/**@} end of group APM32F10x_System */
+/**@} end of group CMSIS */

project_0/libraries/APM32F10x_Library/SConscript

@@ -30,14 +30,18 @@ if GetDepend(['RT_USING_SPI']):
 
 if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
     src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c']
-    
+
 if GetDepend(['RT_USING_WDT']):
     src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c']
     src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c']
-    
-path = [cwd + '/Device/Geehy/APM32F10x/Include', 
+
+if GetDepend(['BSP_USING_ETH']):
+    src += ['APM32F10x_ETH_Driver/src/apm32f10x_eth.c']
+
+path = [cwd + '/Device/Geehy/APM32F10x/Include',
     cwd + '/APM32F10x_StdPeriphDriver/inc',
-    cwd + '/CMSIS/Include']
+    cwd + '/CMSIS/Include',
+    cwd + '/APM32F10x_ETH_Driver/inc']
 
 CPPDEFINES = ['USE_STDPERIPH_DRIVER']
 group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)

project_0/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/inc/usbd_class_cdc.h

@@ -1,33 +0,0 @@
-/*!
- * @file        usbd_class_cdc.h
- *
- * @brief       CDC Class handler file head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __CDC_CLASS_
-#define __CDC_CLASS_
-
-#include "usbd_core.h"
-
-void USBD_ClassHandler(USBD_DevReqData_T *reqData);
-
-#endif

project_0/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/src/usbd_class_cdc.c

@@ -1,71 +0,0 @@
-/*!
- * @file        usbd_class_cdc.c
- *
- * @brief       CDC Class handler file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_class_cdc.h"
-
-static uint8_t cmdBuf[8] = {0};
-
-/*!
- * @brief       USB CDC Class request handler
- *
- * @param       reqData : point to USBD_DevReqData_T structure
- *
- * @retval      None
- */
-void USBD_ClassHandler(USBD_DevReqData_T *reqData)
-{
-    uint16_t length = ((uint16_t)reqData->byte.wLength[1] << 8) | \
-                      reqData->byte.wLength[0] ;
-
-    if (!length)
-    {
-        if (!reqData->byte.bmRequestType.bit.dir)
-        {
-            USBD_CtrlTxStatus();
-        }
-        else
-        {
-            USBD_CtrlRxStatus();
-        }
-    }
-    else
-    {
-        switch (reqData->byte.bRequest)
-        {
-
-        case 0x20:
-            USBD_CtrlOutData(cmdBuf, length);
-            break;
-        case 0x21:
-            USBD_CtrlInData(cmdBuf, length);
-            break;
-        case 0x22:
-            USBD_CtrlOutData(cmdBuf, length);
-            break;
-        default:
-            break;
-        }
-    }
-}

project_0/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/inc/usbd_class_hid.h

@@ -1,37 +0,0 @@
-/*!
- * @file        usbd_class_hid.h
- *
- * @brief       HID Class handler file head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_core.h"
-
-#define HID_CLASS_REQ_SET_PROTOCOL          0x0B
-#define HID_CLASS_REQ_GET_PROTOCOL          0x03
-
-#define HID_CLASS_REQ_SET_IDLE              0x0A
-#define HID_CLASS_REQ_GET_IDLE              0x02
-
-#define HID_CLASS_REQ_SET_REPORT            0x09
-#define HID_CLASS_REQ_GET_REPORT            0x01
-
-void USBD_ClassHandler(USBD_DevReqData_T *reqData);

project_0/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/src/usbd_class_hid.c

@@ -1,63 +0,0 @@
-/*!
- * @file        usbd_class_hid.c
- *
- * @brief       HID Class handler file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_class_hid.h"
-
-static uint8_t s_hidIdleState;
-static uint8_t s_hidProtocol;
-
-/*!
- * @brief       USB HID Class request handler
- *
- * @param       reqData : point to USBD_DevReqData_T structure
- *
- * @retval      None
- */
-void USBD_ClassHandler(USBD_DevReqData_T *reqData)
-{
-    switch (reqData->byte.bRequest)
-    {
-    case HID_CLASS_REQ_SET_IDLE:
-        s_hidIdleState = reqData->byte.wValue[1];
-        USBD_CtrlInData(NULL, 0);
-        break;
-
-    case HID_CLASS_REQ_GET_IDLE:
-        USBD_CtrlInData(&s_hidIdleState, 1);
-        break;
-
-    case HID_CLASS_REQ_SET_PROTOCOL:
-        s_hidProtocol = reqData->byte.wValue[0];
-        USBD_CtrlInData(NULL, 0);
-        break;
-
-    case HID_CLASS_REQ_GET_PROTOCOL:
-        USBD_CtrlInData(&s_hidProtocol, 1);
-        break;
-
-    default:
-        break;
-    }
-}

project_0/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_class_msc.h

@@ -1,37 +0,0 @@
-/*!
- * @file        usbd_class_msc.h
- *
- * @brief       MSC Class handler file head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __USBD_CLASS_MSC
-#define __USBD_CLASS_MSC
-
-#include "usbd_core.h"
-
-
-#define BOT_GET_MAX_LUN              0xFE
-#define BOT_RESET                    0xFF
-
-void USBD_MSC_ClassHandler(USBD_DevReqData_T *reqData);
-
-#endif

project_0/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_bot.h

@@ -1,106 +0,0 @@
-/*!
- * @file        usbd_msc_bot.h
- *
- * @brief       MSC BOT protocol core functions
- *
- * @version     V1.0.0
- *
- * @date        2021-12-25
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_core.h"
-
-#ifndef __USBD_MSC_BOT_H
-#define __USBD_MSC_BOT_H
-
-#define MSC_BOT_CBW_SIGNATURE             (uint32_t)(0x43425355)
-#define MSC_BOT_CBW_LENGTH                31
-
-#define MSC_BOT_CSW_SIGNATURE             (uint32_t)(0x53425355)
-#define MSC_BOT_CSW_LENGTH                13
-
-typedef enum
-{
-    BOT_STATE_IDLE,          //!< Idle state
-    BOT_STATE_DATA_OUT,      //!< Data Out state
-    BOT_STATE_DATA_IN,       //!< Data In state
-    BOT_STATE_LAST_DATA_IN,  //!< Last Data In Last
-    BOT_STATE_SEND_DATA      //!< Send Immediate data
-} BOT_STATE_T;
-
-typedef enum
-{
-    BOT_STATUS_NORMAL,
-    BOT_STATUS_RECOVERY,
-    BOT_STATUS_ERROR
-} BOT_STATUS_T;
-
-typedef enum
-{
-    BOT_CSW_STATUS_CMD_OK,
-    BOT_CSW_STATUS_CMD_FAIL,
-    BOT_CSW_STATUS_PHASE_ERROR
-} BOT_CSW_STATUS_T;
-
-
-/**
- * @brief   Command Block Wrapper
- */
-typedef struct
-{
-    uint32_t dSignature;
-    uint32_t dTag;
-    uint32_t dDataXferLen;
-    uint8_t  bmFlags;
-    uint8_t  bLUN;
-    uint8_t  bCBLen;
-    uint8_t  CB[16];
-} BOT_CBW_T;
-
-/**
- * @brief   Command Status Wrapper
- */
-typedef struct
-{
-    uint32_t dSignature;
-    uint32_t dTag;
-    uint32_t dDataResidue;
-    uint8_t  bStatus;
-} BOT_CSW_T;
-
-typedef struct
-{
-    uint8_t   state;
-    uint8_t   status;
-    uint16_t  dataLen;
-    BOT_CBW_T CBW;
-    BOT_CSW_T CSW;
-    uint8_t   data[MSC_MEDIA_PACKET];
-} BOT_Info_T;
-
-extern BOT_Info_T g_BOTInfo;
-
-void USBD_MSC_BOT_Reset(void);
-void USBD_MSC_BOT_Init(void);
-void USBD_MSC_BOT_OutData(uint8_t ep);
-void USBD_MSC_BOT_InData(uint8_t ep);
-void USBD_MSC_BOT_TxCSW(uint8_t cswStatus);
-void USBD_MSC_BOT_Stall(void);
-void USBD_MSV_BOT_ClearFeatureHandler(void);
-
-#endif

project_0/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_scsi.h

@@ -1,132 +0,0 @@
-/*!
- * @file        usbd_msc_scsi.h
- *
- * @brief       MSC scsi
- *
- * @version     V1.0.0
- *
- * @date        2021-12-25
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_core.h"
-#ifndef __USBD_MSC_SCSI_H_
-#define __USBD_MSC_SCSI_H_
-
-/**
- * @brief   SCSI function status
- */
-enum
-{
-    SCSI_OK,
-    SCSI_FAIL
-};
-
-/**
- * @brief   SCSI Sense Key
- */
-typedef enum
-{
-    SCSI_SKEY_NO_SENSE,
-    SCSI_SKEY_RECOVERED_ERROR,
-    SCSI_SKEY_NOT_READY,
-    SCSI_SKEY_MEDIUM_ERROR,
-    SCSI_SKEY_HARDWARE_ERROR,
-    SCSI_SKEY_ILLEGAL_REQUEST,
-    SCSI_SKEY_UNIT_ATTENTION,
-    SCSI_SKEY_DATA_PROTECT,
-    SCSI_SKEY_BLANK_CHECK,
-    SCSI_SKEY_VENDOR_SPECIFIC,
-    SCSI_SKEY_COPY_ABORTED,
-    SCSI_SKEY_ABORTED_COMMAND,
-    SCSI_SKEY_VOLUME_OVERFLOW = 13,
-    SCSI_SKEY_MISCOMPARE      = 14
-} SCSI_SKEY_T;
-
-/**
- * @brief   SCSI Sense
- */
-typedef struct
-{
-    uint8_t sensekey;
-    uint8_t ASC;
-    uint8_t ASCQ;
-} SCSI_Sense_T;
-
-
-#define SCSI_SENSE_LIST_NUMBER                      4
-#define SCSI_INQUIRY_LENGTH                         36
-
-/** SCSI Commands */
-#define SCSI_CMD_FORMAT_UNIT                        ((uint8_t)0x04)
-#define SCSI_CMD_INQUIRY                            ((uint8_t)0x12)
-#define SCSI_CMD_MODE_SELECT_6                      ((uint8_t)0x15)
-#define SCSI_CMD_MODE_SELECT_10                     ((uint8_t)0x55)
-#define SCSI_CMD_MODE_SENSE_6                       ((uint8_t)0x1A)
-#define SCSI_CMD_MODE_SENSE_10                      ((uint8_t)0x5A)
-#define SCSI_CMD_ALLOW_MEDIUM_REMOVAL               ((uint8_t)0x1E)
-#define SCSI_CMD_READ_6                             ((uint8_t)0x08)
-#define SCSI_CMD_READ_10                            ((uint8_t)0x28)
-#define SCSI_CMD_READ_12                            ((uint8_t)0xA8)
-#define SCSI_CMD_READ_16                            ((uint8_t)0x88)
-
-#define SCSI_CMD_READ_CAPACITY_10                   ((uint8_t)0x25)
-#define SCSI_CMD_READ_CAPACITY_16                   ((uint8_t)0x9E)
-
-#define SCSI_CMD_REQUEST_SENSE                      ((uint8_t)0x03)
-#define SCSI_CMD_START_STOP_UNIT                    ((uint8_t)0x1B)
-#define SCSI_CMD_TEST_UNIT_READY                    ((uint8_t)0x00)
-#define SCSI_CMD_WRITE6                             ((uint8_t)0x0A)
-#define SCSI_CMD_WRITE10                            ((uint8_t)0x2A)
-#define SCSI_CMD_WRITE12                            ((uint8_t)0xAA)
-#define SCSI_CMD_WRITE16                            ((uint8_t)0x8A)
-
-#define SCSI_CMD_VERIFY_10                          ((uint8_t)0x2F)
-#define SCSI_CMD_VERIFY_12                          ((uint8_t)0xAF)
-#define SCSI_CMD_VERIFY_16                          ((uint8_t)0x8F)
-
-#define SCSI_CMD_SEND_DIAGNOSTIC                    ((uint8_t)0x1D)
-#define SCSI_CMD_READ_FORMAT_CAPACITIES             ((uint8_t)0x23)
-
-
-#define SCSI_ASC_INVALID_CDB                         0x20
-#define SCSI_ASC_INVALID_FIELED_IN_COMMAND           0x24
-#define SCSI_ASC_PARAMETER_LIST_LENGTH_ERROR         0x1A
-#define SCSI_ASC_INVALID_FIELD_IN_PARAMETER_LIST     0x26
-#define SCSI_ASC_ADDRESS_OUT_OF_RANGE                0x21
-#define SCSI_ASC_MEDIUM_NOT_PRESENT                  0x3A
-#define SCSI_ASC_MEDIUM_HAVE_CHANGED                 0x28
-#define SCSI_ASC_WRITE_PROTECTED                     0x27
-#define SCSI_ASC_UNRECOVERED_READ_ERROR              0x11
-#define SCSI_ASC_WRITE_FAULT                         0x03
-
-#define SCSI_READ_FORMAT_CAPACITY_DATA_LEN           0x0C
-#define SCSI_READ_CAPACITY10_DATA_LEN                0x08
-#define SCSI_MODE_SENSE10_DATA_LEN                   0x08
-#define SCSI_MODE_SENSE6_DATA_LEN                    0x04
-#define SCSI_REQUEST_SENSE_DATA_LEN                  0x12
-#define SCSI_STANDARD_INQUIRY_DATA_LEN               0x24
-#define SCSI_BLKVFY                                  0x04
-
-extern SCSI_Sense_T g_scsiSense[SCSI_SENSE_LIST_NUMBER];
-extern uint8_t g_senseTxCnt;
-extern uint8_t g_sensePutCnt;
-
-uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t *cmd);
-void   SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ);
-
-#endif

project_0/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_class_msc.c

@@ -1,79 +0,0 @@
-/*!
- * @file        usbd_class_msc.c
- *
- * @brief       MSC Class file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_class_msc.h"
-#include "usbd_msc_bot.h"
-
-static uint8_t s_mscMaxLen = 0;
-
-/*!
- * @brief       USB MSC Class request handler
- *
- * @param       reqData : point to USBD_DevReqData_T structure
- *
- * @retval      None
- */
-void USBD_MSC_ClassHandler(USBD_DevReqData_T *reqData)
-{
-    uint16_t wValue = ((uint16_t)reqData->byte.wValue[1] << 8) | \
-                      reqData->byte.wValue[0];
-    uint16_t wLength = ((uint16_t)reqData->byte.wLength[1] << 8) | \
-                       reqData->byte.wLength[0];
-
-    switch (reqData->byte.bRequest)
-    {
-    case BOT_GET_MAX_LUN :
-        if ((wValue == 0) && (wLength == 1) && \
-                (reqData->byte.bmRequestType.bit.dir == 1))
-        {
-            s_mscMaxLen = STORAGE_MAX_LUN - 1;
-
-            USBD_CtrlInData(&s_mscMaxLen, 1);
-        }
-        else
-        {
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-        }
-        break;
-    case BOT_RESET :
-        if ((wValue == 0) && (wLength == 0) && \
-                (reqData->byte.bmRequestType.bit.dir == 0))
-        {
-            USBD_CtrlInData(NULL, 0);
-            /** Reset */
-            USBD_MSC_BOT_Reset();
-        }
-        else
-        {
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-        }
-
-        break;
-
-    default:
-        USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-        break;
-    }
-}

project_0/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_bot.c

@@ -1,242 +0,0 @@
-/*!
- * @file        usbd_msv_bot.c
- *
- * @brief       MSC BOT protocol core functions
- *
- * @version     V1.0.0
- *
- * @date        2021-12-25
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_msc_bot.h"
-#include "usbd_core.h"
-#include "usbd_storage_disk.h"
-#include "usbd_msc_scsi.h"
-
-BOT_Info_T g_BOTInfo;
-
-static void USBD_MSC_BOT_DecodeCBW(void);
-static void USBD_MSC_BOT_TxData(uint8_t *txBuf, uint16_t len);
-static void USBD_MSC_BOT_Stall(void);
-
-/*!
- * @brief       BOT Process Reset.
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_MSC_BOT_Reset(void)
-{
-    g_BOTInfo.state = BOT_STATE_IDLE;
-    g_BOTInfo.status = BOT_STATUS_RECOVERY;
-
-    USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH);
-}
-
-/*!
- * @brief       BOT Process initialization.
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_MSC_BOT_Init(void)
-{
-    g_BOTInfo.state = BOT_STATE_IDLE;
-    g_BOTInfo.status = BOT_STATUS_NORMAL;
-
-    g_storageCallBack.Init(0);
-
-    USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH);
-}
-
-/*!
- * @brief       Bulk OUT data handler.
- *
- * @param       ep : OUT endpoint
- *
- * @retval      None
- */
-void USBD_MSC_BOT_OutData(uint8_t ep)
-{
-    if (g_BOTInfo.state == BOT_STATE_IDLE)
-    {
-        USBD_MSC_BOT_DecodeCBW();
-    }
-    else if (g_BOTInfo.state == BOT_STATE_DATA_OUT)
-    {
-        if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
-        {
-            USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
-        }
-    }
-}
-
-/*!
- * @brief       Bulk IN data handler.
- *
- * @param       ep : IN endpoint
- *
- * @retval      None
- */
-void USBD_MSC_BOT_InData(uint8_t ep)
-{
-    if (g_BOTInfo.state == BOT_STATE_DATA_IN)
-    {
-        if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
-        {
-            USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
-        }
-    }
-    else if ((g_BOTInfo.state == BOT_STATE_SEND_DATA) || \
-             (g_BOTInfo.state == BOT_STATE_LAST_DATA_IN))
-    {
-        USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
-    }
-}
-
-/*!
- * @brief       Decode CBW.
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_MSC_BOT_DecodeCBW(void)
-{
-    uint32_t xferCnt = g_usbDev.outBuf[MSC_OUT_EP & 0x7f].xferCnt;
-
-    g_BOTInfo.CSW.dTag = g_BOTInfo.CBW.dTag;
-    g_BOTInfo.CSW.dDataResidue = g_BOTInfo.CBW.dDataXferLen;
-
-    if ((xferCnt != MSC_BOT_CBW_LENGTH) || \
-            (g_BOTInfo.CBW.dSignature != MSC_BOT_CBW_SIGNATURE) || \
-            (g_BOTInfo.CBW.bLUN > 1) || (g_BOTInfo.CBW.bCBLen < 1) || \
-            (g_BOTInfo.CBW.bCBLen > 16))
-    {
-        SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                          SCSI_ASC_INVALID_CDB, 0);
-
-        g_BOTInfo.status = BOT_STATUS_ERROR;
-    }
-    else
-    {
-        if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
-        {
-            USBD_MSC_BOT_Stall();
-        }
-        else if ((g_BOTInfo.state == BOT_STATE_IDLE) || \
-                 (g_BOTInfo.state == BOT_STATE_SEND_DATA))
-        {
-            if (g_BOTInfo.dataLen)
-            {
-                USBD_MSC_BOT_TxData(g_BOTInfo.data, g_BOTInfo.dataLen);
-            }
-            else
-            {
-                USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
-            }
-        }
-    }
-}
-
-/*!
- * @brief       MSC send data.
- *
- * @param       txBuf : buffer to send
- *
- * @param       len : buffer length
- *
- * @retval      None
- */
-static void USBD_MSC_BOT_TxData(uint8_t *txBuf, uint16_t len)
-{
-    len = USB_MIN(len, g_BOTInfo.CBW.dDataXferLen);
-
-    g_BOTInfo.CSW.dDataResidue -= len;
-    g_BOTInfo.CSW.bStatus = BOT_CSW_STATUS_CMD_OK;
-    g_BOTInfo.state = BOT_STATE_SEND_DATA;
-
-    USBD_TxData(MSC_IN_EP & 0x7f, txBuf, len);
-}
-
-/*!
- * @brief       Send CSW.
- *
- * @param       cswStatus : status of CSW
- *
- * @retval      None
- */
-void USBD_MSC_BOT_TxCSW(uint8_t cswStatus)
-{
-    g_BOTInfo.CSW.dSignature = MSC_BOT_CSW_SIGNATURE;
-    g_BOTInfo.CSW.bStatus = cswStatus;
-    g_BOTInfo.state = BOT_STATE_IDLE;
-
-    USBD_TxData(MSC_IN_EP & 0x7f, (uint8_t *)&g_BOTInfo.CSW,
-                MSC_BOT_CSW_LENGTH);
-
-    USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW,
-                MSC_BOT_CBW_LENGTH);
-}
-
-/*!
- * @brief       handler clearFeature in standard request.
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_MSV_BOT_ClearFeatureHandler(void)
-{
-    if (g_BOTInfo.status == BOT_STATUS_ERROR)
-    {
-        USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_NAK);
-        g_BOTInfo.status = BOT_STATUS_NORMAL;
-    }
-    else if (((g_usbDev.reqData.byte.wIndex[0] & 0x80) == 0x80) && \
-             g_BOTInfo.status != BOT_STATUS_RECOVERY)
-    {
-        USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
-    }
-}
-
-/*!
- * @brief       Stall MSC.
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_MSC_BOT_Stall(void)
-{
-    if ((g_BOTInfo.CBW.bmFlags == 0) && (g_BOTInfo.CBW.dDataXferLen != 0) && \
-            (g_BOTInfo.status == BOT_STATUS_NORMAL))
-    {
-        USBD_SetEPRxStatus(MSC_OUT_EP & 0x7f, USBD_EP_STATUS_STALL);
-    }
-
-    USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_STALL);
-
-    if (g_BOTInfo.status == BOT_STATUS_ERROR)
-    {
-        USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW,
-                    MSC_BOT_CBW_LENGTH);
-    }
-}