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@@ -40,6 +40,8 @@
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Adapted from u8x8_d_ssd1322.c with the command set of the SSD1320 controller
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"official" procedure is described here: https://github.com/olikraus/u8g2/wiki/internal
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+ NOTE: U8x8 does NOT work!
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+
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*/
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#include "u8x8.h"
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@@ -235,7 +237,7 @@ static const uint8_t u8x8_d_ssd1320_cs1_160x32_init_seq[] = {
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U8X8_C(0xc8), /* Set COM Output Scan Direction: normal mode CS1 */
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// U8X8_C(0xc0), /* Set COM Output Scan Direction: normal mode CS2 */
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-
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+
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U8X8_CA(0xd3, 0x72), /* CS1 */
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// U8X8_CA(0xd3, 0x92), /* CS2 */
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@@ -332,6 +334,45 @@ static const u8x8_display_info_t u8x8_d_ssd1320_cs1_160x132_display_info =
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/* pixel_height = */ 132
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};
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+
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+/* the following sequence will work, but requires contrast to be very high */
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+static const uint8_t u8x8_d_ssd1320_cs1_160x132_init_seq[] = {
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+
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+ U8X8_DLY(1),
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+ U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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+ U8X8_DLY(1),
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+
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+ U8X8_C(0xae), /* display off */
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+ U8X8_CA(0xd5, 0xC2), /* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */
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+ U8X8_CA(0xa8, 0x83), /* multiplex ratio 1/132 Duty */
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+ U8X8_CA(0xa2, 0x00), /* display start line */
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+
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+ U8X8_C(0xa0), /* Set Segment Re-Map: column address 0 mapped to SEG0 CS1 */
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+ // U8X8_C(0xa1), /* Set Segment Re-Map: column address 0 mapped to SEG0 CS2 */
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+
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+ U8X8_C(0xc8), /* Set COM Output Scan Direction: normal mode CS1 */
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+ // U8X8_C(0xc0), /* Set COM Output Scan Direction: normal mode CS2 */
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+
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+ U8X8_CA(0xd3, 0x0e), /* CS1 */
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+ // U8X8_CA(0xd3, 0x92), /* CS2 */
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+
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+ U8X8_CA(0xda, 0x12), /* Set SEG Pins Hardware Configuration: */
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+ U8X8_CA(0x81, 0x5a), /* contrast */
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+ U8X8_CA(0xd9, 0x22), /* Set Phase Length */
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+ U8X8_CA(0xdb, 0x30), /* VCOMH Deselect Level */
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+ U8X8_CA(0xad, 0x10), /* Internal IREF Enable */
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+ U8X8_CA(0x20, 0x00), /* Memory Addressing Mode: Horizontal */
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+ U8X8_CA(0x8d, 0x01), /* disable internal charge pump 1 */
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+ U8X8_CA(0xac, 0x00), /* disable internal charge pump 2 */
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+ U8X8_C(0xa4), /* display on */
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+ U8X8_C(0xa6), /* normal display */
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+
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+ U8X8_DLY(1), /* delay 2ms */
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+
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+ U8X8_END_TRANSFER(), /* disable chip */
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+ U8X8_END() /* end of sequence */
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+};
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+
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/*
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OLED_WR_Byte(0xae,OLED_CMD);//Display OFF
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OLED_WR_Byte(0xfd,OLED_CMD);//Set Command Lock
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@@ -348,8 +389,10 @@ OLED_WR_Byte(0xa2,OLED_CMD);//Set Display Start Line
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OLED_WR_Byte(0x00,OLED_CMD);
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OLED_WR_Byte(0xa4,OLED_CMD);//Resume to RAM content display
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OLED_WR_Byte(0xa6,OLED_CMD);//Set Normal Display
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+
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OLED_WR_Byte(0xa8,OLED_CMD);//Set MUX Ratio
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OLED_WR_Byte(0x83,OLED_CMD);//1/132 duty
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+
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OLED_WR_Byte(0xad,OLED_CMD);//Select external or internal IREF
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OLED_WR_Byte(0x10,OLED_CMD);
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OLED_WR_Byte(0xbc,OLED_CMD);//Set Pre-charge voltage
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@@ -372,36 +415,43 @@ OLED_WR_Byte(0xdb,OLED_CMD);//Set VCOMH
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OLED_WR_Byte(0x30,OLED_CMD);
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OLED_WR_Byte(0xaf,OLED_CMD);//Display on
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*/
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-
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-static const uint8_t u8x8_d_ssd1320_cs1_160x132_init_seq[] = {
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-
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+static const uint8_t u8x8_d_ssd1320_160x132_init_seq[] = {
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U8X8_DLY(1),
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_DLY(1),
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U8X8_C(0xae), /* display off */
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- U8X8_CA(0xd5, 0xC2), /* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */
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- U8X8_CA(0xa8, 0x83), /* multiplex ratio 1/132 Duty */
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- U8X8_CA(0xa2, 0x00), /* display start line */
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+ U8X8_CA(0xd5, 0xC2), /* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */
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+ U8X8_CA(0xa8, 0x83), /* multiplex ratio 1/132 Duty */
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+ U8X8_CA(0xa2, 0x00), /* display start line */
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U8X8_C(0xa0), /* Set Segment Re-Map: column address 0 mapped to SEG0 CS1 */
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- // U8X8_C(0xa1), /* Set Segment Re-Map: column address 0 mapped to SEG0 CS2 */
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+ // U8X8_C(0xa1), /* Set Segment Re-Map: column address 0 mapped to SEG0 CS2 */
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+
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+ U8X8_C(0xc8), /* Set COM Output Scan Direction: normal mode CS1 */
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+ // U8X8_C(0xc0), /* Set COM Output Scan Direction: normal mode CS2 */
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+
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+ U8X8_CA(0xad, 0x10), /* select Iref: 0x00 external (reset default), 0x10 internal */
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+ U8X8_CA(0xbc, 0x1e), /* pre-charge voltage level 0x00..0x1f, reset default: 0x1e */
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+ U8X8_C(0xbf), /* select linear LUT */
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+ U8X8_CA(0xd5, 0xc2), /* Bit 0..3: clock ratio 1, 2, 4, 8, ...256, reset=0x1, Bit 4..7: F_osc 0..15 */
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+ U8X8_CA(0xd9, 0x72), /* Set Phase 1&2 Length, Bit 0..3: Phase 1, Bit 4..7: Phase 2, reset default 0x72 */
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+ U8X8_CA(0xbd, 0x03), /* from the vendor init sequence */
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+ U8X8_CA(0xdb, 0x30), /* VCOMH Deselect Level */
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- U8X8_C(0xc8), /* Set COM Output Scan Direction: normal mode CS1 */
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- // U8X8_C(0xc0), /* Set COM Output Scan Direction: normal mode CS2 */
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U8X8_CA(0xd3, 0x0e), /* CS1 */
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// U8X8_CA(0xd3, 0x92), /* CS2 */
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- U8X8_CA(0xda, 0x12), /* Set SEG Pins Hardware Configuration: */
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- U8X8_CA(0x81, 0x5a), /* contrast */
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- U8X8_CA(0xd9, 0x22), /* Set Phase Length */
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- U8X8_CA(0xdb, 0x30), /* VCOMH Deselect Level */
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- U8X8_CA(0xad, 0x10), /* Internal IREF Enable */
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+ U8X8_CA(0xda, 0x12), /* Set SEG Pins Hardware Configuration: */
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+ U8X8_CA(0x81, 0x6b), /* contrast */
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+ //U8X8_CA(0xd9, 0x22), /* Set Phase Length */
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+ //U8X8_CA(0xdb, 0x30), /* VCOMH Deselect Level */
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+ //U8X8_CA(0xad, 0x10), /* Internal IREF Enable */
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U8X8_CA(0x20, 0x00), /* Memory Addressing Mode: Horizontal */
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- U8X8_CA(0x8d, 0x01), /* disable internal charge pump 1 */
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- U8X8_CA(0xac, 0x00), /* disable internal charge pump 2 */
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- U8X8_C(0xa4), /* display on */
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+ //U8X8_CA(0x8d, 0x01), /* unknown in SSD1320 datasheet, disable internal charge pump 1 */
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+ //U8X8_CA(0xac, 0x00), /* unknown in SSD1320 datasheet, disable internal charge pump 2 */
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+ U8X8_C(0xa4), /* display RAM on */
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U8X8_C(0xa6), /* normal display */
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U8X8_DLY(1), /* delay 2ms */
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@@ -410,18 +460,19 @@ static const uint8_t u8x8_d_ssd1320_cs1_160x132_init_seq[] = {
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U8X8_END() /* end of sequence */
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};
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-
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uint8_t u8x8_d_ssd1320_160x132(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
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{
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switch(msg)
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{
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case U8X8_MSG_DISPLAY_SETUP_MEMORY:
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u8x8_d_helper_display_setup_memory(u8x8, &u8x8_d_ssd1320_cs1_160x132_display_info);
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+
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break;
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case U8X8_MSG_DISPLAY_INIT:
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u8x8_d_helper_display_init(u8x8);
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- u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_cs1_160x132_init_seq);
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+ // u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_cs1_160x132_init_seq);
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+ u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_160x132_init_seq);
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break;
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case U8X8_MSG_DISPLAY_SET_FLIP_MODE:
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