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@@ -38,10 +38,10 @@
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@{
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*/
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-static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
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-static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
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-static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
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-static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
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+static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
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+static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
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+static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
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+static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
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/*!
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* @brief Deinitializes the TMRx peripheral registers to their default reset values.
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@@ -51,7 +51,7 @@ static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
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* @retval None
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*
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*/
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-void TMR_Reset(TMR_T *tmr)
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+void TMR_Reset(TMR_T* tmr)
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{
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if (tmr == TMR1)
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{
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@@ -104,12 +104,12 @@ void TMR_Reset(TMR_T *tmr)
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*
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* @retval None
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*/
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-void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig)
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+void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig)
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{
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uint16_t temp;
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if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
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- (tmr == TMR4) || (tmr == TMR5))
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+ (tmr == TMR4) || (tmr == TMR5))
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{
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temp = tmr->CTRL1;
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temp &= 0x038F;
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@@ -141,7 +141,7 @@ void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig)
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*
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* @retval None
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*/
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-void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
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+void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
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{
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tmr->CCEN_B.CC1EN = BIT_RESET;
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@@ -173,7 +173,7 @@ void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
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*
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* @retval None
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*/
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-void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
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+void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
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{
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tmr->CCEN_B.CC2EN = BIT_RESET;
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@@ -210,7 +210,7 @@ void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
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*
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* @retval None
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*/
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-void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
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+void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
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{
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tmr->CCEN_B.CC3EN = BIT_RESET;
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@@ -246,7 +246,7 @@ void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
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*
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* @retval None
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*/
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-void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
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+void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
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{
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tmr->CCEN_B.CC4EN = BIT_RESET;
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@@ -275,7 +275,7 @@ void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
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*
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* @retval None
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*/
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-void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig)
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+void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig)
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{
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if (ICConfig->channel == TMR_CHANNEL_1)
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{
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@@ -308,15 +308,15 @@ void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig)
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*
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* @retval None
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*/
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-void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig)
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+void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig)
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{
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- tmr->BDT = (BDTConfig->IMOS) << 10 | \
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- (BDTConfig->RMOS) << 11 | \
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- (BDTConfig->lockLevel) << 8 | \
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- (BDTConfig->deadTime) | \
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- (BDTConfig->BRKState) << 12 | \
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- (BDTConfig->BRKPolarity) << 13 | \
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- (BDTConfig->automaticOutput) << 14;
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+ tmr->BDT = (BDTConfig->IMOS)<<10 |\
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+ (BDTConfig->RMOS)<<11 |\
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+ (BDTConfig->lockLevel)<<8 |\
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+ (BDTConfig->deadTime) |\
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+ (BDTConfig->BRKState)<<12 |\
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+ (BDTConfig->BRKPolarity)<<13 |\
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+ (BDTConfig->automaticOutput)<<14;
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}
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/*!
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@@ -326,7 +326,7 @@ void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig)
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*
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* @retval None
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*/
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-void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig)
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+void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig)
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{
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baseConfig->period = 0xFFFF;
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baseConfig->division = 0x0000;
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@@ -342,7 +342,7 @@ void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig)
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*
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* @retval None
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*/
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-void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig)
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+void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig)
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{
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OCConfig->mode = TMR_OC_MODE_TMRING;
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OCConfig->outputState = TMR_OC_STATE_DISABLE;
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@@ -361,7 +361,7 @@ void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig)
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*
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* @retval None
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*/
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-void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig)
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+void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig)
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{
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ICConfig->channel = TMR_CHANNEL_1;
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ICConfig->polarity = TMR_IC_POLARITY_RISING;
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@@ -377,7 +377,7 @@ void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig)
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*
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* @retval None
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*/
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-void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig)
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+void TMR_ConfigBDTStructInit( TMR_BDTConfig_T* BDTConfig)
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{
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BDTConfig->RMOS = TMR_RMOS_STATE_DISABLE;
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BDTConfig->IMOS = TMR_IMOS_STATE_DISABLE;
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@@ -395,7 +395,7 @@ void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig)
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*
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* @retval None
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*/
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-void TMR_Enable(TMR_T *tmr)
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+void TMR_Enable(TMR_T* tmr)
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{
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tmr->CTRL1_B.CNTEN = ENABLE;
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}
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@@ -407,7 +407,7 @@ void TMR_Enable(TMR_T *tmr)
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*
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* @retval None
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*/
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-void TMR_Disable(TMR_T *tmr)
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+void TMR_Disable(TMR_T* tmr)
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{
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tmr->CTRL1_B.CNTEN = DISABLE;
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}
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@@ -421,7 +421,7 @@ void TMR_Disable(TMR_T *tmr)
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*
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* @retval None
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*/
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-void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig)
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+void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig)
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{
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uint16_t icpolarity = TMR_IC_POLARITY_RISING;
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uint16_t icselection = TMR_IC_SELECTION_DIRECT_TI;
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@@ -467,7 +467,7 @@ void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig)
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*
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* @retval None
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*/
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-void TMR_EnablePWMOutputs(TMR_T *tmr)
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+void TMR_EnablePWMOutputs(TMR_T* tmr)
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{
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tmr->BDT_B.MOEN = ENABLE;
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}
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@@ -479,7 +479,7 @@ void TMR_EnablePWMOutputs(TMR_T *tmr)
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*
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* @retval None
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*/
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-void TMR_DisablePWMOutputs(TMR_T *tmr)
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+void TMR_DisablePWMOutputs(TMR_T* tmr)
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{
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tmr->BDT_B.MOEN = DISABLE;
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}
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@@ -495,7 +495,7 @@ void TMR_DisablePWMOutputs(TMR_T *tmr)
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*
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* @retval None
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*/
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-void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength)
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+void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength)
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{
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tmr->DCTRL = (uint32_t)baseAddress | (uint32_t)burstLength;
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}
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@@ -517,7 +517,7 @@ void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T
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* @retval None
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*
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*/
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-void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource)
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+void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource)
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{
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tmr->DIEN |= dmaSource;
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}
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@@ -539,7 +539,7 @@ void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource)
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* @retval None
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*
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*/
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-void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource)
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+void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource)
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{
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tmr->DIEN &= ~dmaSource;
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}
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@@ -551,7 +551,7 @@ void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource)
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*
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* @retval None
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*/
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-void TMR_ConfigInternalClock(TMR_T *tmr)
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+void TMR_ConfigInternalClock(TMR_T* tmr)
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{
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tmr->SMCTRL_B.SMFSEL = DISABLE;
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}
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@@ -569,7 +569,7 @@ void TMR_ConfigInternalClock(TMR_T *tmr)
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* @arg TMR_TRIGGER_SOURCE_ITR3: TMR Internal Trigger 3
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* @retval None
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*/
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-void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource)
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+void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource)
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{
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TMR_SelectInputTrigger(tmr, triggerSource);
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tmr->SMCTRL_B.SMFSEL = 0x07;
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@@ -595,8 +595,8 @@ void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSour
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*
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* @retval None
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*/
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-void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource,
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- TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter)
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+void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
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+ TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter)
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{
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if (triggerSource == 0x06)
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{
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@@ -632,7 +632,7 @@ void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource,
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*
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* @retval None
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*/
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-void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
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+void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
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TMR_EXTTRG_POL_T polarity, uint16_t filter)
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{
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TMR_ConfigETR(tmr, prescaler, polarity, filter);
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@@ -662,7 +662,7 @@ void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
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*
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* @retval None
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*/
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-void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
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+void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
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TMR_EXTTRG_POL_T polarity, uint16_t filter)
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{
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TMR_ConfigETR(tmr, prescaler, polarity, filter);
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@@ -689,7 +689,7 @@ void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
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*
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* @retval None
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*/
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-void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
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+void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
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TMR_EXTTRG_POL_T polarity, uint16_t filter)
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{
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tmr->SMCTRL &= 0x00FF;
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@@ -711,7 +711,7 @@ void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
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* @arg TMR_PSC_RELOAD_IMMEDIATE: The Prescaler is loaded immediately
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* @retval None
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*/
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-void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode)
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+void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode)
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{
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tmr->PSC = prescaler;
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tmr->CEG_B.UEG = pscReloadMode;
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@@ -731,7 +731,7 @@ void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscRel
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* @arg TMR_COUNTER_MODE_CENTERALIGNED3: Timer Center Aligned Mode3
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* @retval None
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*/
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-void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode)
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+void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode)
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{
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tmr->CTRL1_B.CNTDIR = BIT_RESET;
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tmr->CTRL1_B.CAMSEL = BIT_RESET;
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@@ -756,7 +756,7 @@ void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode)
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*
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* @retval None
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*/
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-void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource)
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+void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource)
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{
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tmr->SMCTRL_B.TRGSEL = BIT_RESET;
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tmr->SMCTRL_B.TRGSEL = triggerSource;
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@@ -785,7 +785,7 @@ void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource)
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* @arg TMR_IC_POLARITY_FALLING: TMR IC polarity falling
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* @retval None
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*/
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-void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
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+void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
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TMR_IC_POLARITY_T IC2Polarity)
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{
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tmr->SMCTRL_B.SMFSEL = BIT_RESET;
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@@ -812,7 +812,7 @@ void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC
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* @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF
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* @retval None
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*/
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-void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
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+void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
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{
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tmr->CCM1_COMPARE_B.OC1MOD = BIT_RESET;
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tmr->CCM1_COMPARE_B.OC1MOD = forcesAction;
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@@ -829,7 +829,7 @@ void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
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* @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF
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* @retval None
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*/
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-void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
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+void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
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{
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tmr->CCM1_COMPARE_B.OC2MOD = BIT_RESET;
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tmr->CCM1_COMPARE_B.OC2MOD = forcesAction;
|
|
|
@@ -847,7 +847,7 @@ void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
|
|
|
+void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
|
|
|
{
|
|
|
tmr->CCM2_COMPARE_B.OC3MOD = BIT_RESET;
|
|
|
tmr->CCM2_COMPARE_B.OC3MOD = forcesAction;
|
|
|
@@ -865,7 +865,7 @@ void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
|
|
|
+void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
|
|
|
{
|
|
|
tmr->CCM2_COMPARE_B.OC4MOD = BIT_RESET;
|
|
|
tmr->CCM2_COMPARE_B.OC4MOD = forcesAction;
|
|
|
@@ -878,7 +878,7 @@ void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_EnableAutoReload(TMR_T *tmr)
|
|
|
+void TMR_EnableAutoReload(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->CTRL1_B.ARPEN = ENABLE;
|
|
|
}
|
|
|
@@ -890,7 +890,7 @@ void TMR_EnableAutoReload(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_DisableAutoReload(TMR_T *tmr)
|
|
|
+void TMR_DisableAutoReload(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->CTRL1_B.ARPEN = DISABLE;
|
|
|
}
|
|
|
@@ -902,7 +902,7 @@ void TMR_DisableAutoReload(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_EnableSelectCOM(TMR_T *tmr)
|
|
|
+void TMR_EnableSelectCOM(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->CTRL2_B.CCUSEL = ENABLE;
|
|
|
}
|
|
|
@@ -913,7 +913,7 @@ void TMR_EnableSelectCOM(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_DisableSelectCOM(TMR_T *tmr)
|
|
|
+void TMR_DisableSelectCOM(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->CTRL2_B.CCUSEL = DISABLE;
|
|
|
}
|
|
|
@@ -925,7 +925,7 @@ void TMR_DisableSelectCOM(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_EnableCCDMA(TMR_T *tmr)
|
|
|
+void TMR_EnableCCDMA(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->CTRL2_B.CCDSEL = ENABLE;
|
|
|
}
|
|
|
@@ -937,7 +937,7 @@ void TMR_EnableCCDMA(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_DisableCCDMA(TMR_T *tmr)
|
|
|
+void TMR_DisableCCDMA(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->CTRL2_B.CCDSEL = DISABLE;
|
|
|
}
|
|
|
@@ -949,7 +949,7 @@ void TMR_DisableCCDMA(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_EnableCCPreload(TMR_T *tmr)
|
|
|
+void TMR_EnableCCPreload(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->CTRL2_B.CCPEN = ENABLE;
|
|
|
}
|
|
|
@@ -961,7 +961,7 @@ void TMR_EnableCCPreload(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_DisableCCPreload(TMR_T *tmr)
|
|
|
+void TMR_DisableCCPreload(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->CTRL2_B.CCPEN = DISABLE;
|
|
|
}
|
|
|
@@ -977,7 +977,7 @@ void TMR_DisableCCPreload(TMR_T *tmr)
|
|
|
* @arg TMR_OC_PRELOAD_ENABLE
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
|
|
|
+void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
|
|
|
{
|
|
|
tmr->CCM1_COMPARE_B.OC1PEN = OCPreload;
|
|
|
}
|
|
|
@@ -993,7 +993,7 @@ void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
|
|
|
* @arg TMR_OC_PRELOAD_ENABLE
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
|
|
|
+void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
|
|
|
{
|
|
|
tmr->CCM1_COMPARE_B.OC2PEN = OCPreload;
|
|
|
}
|
|
|
@@ -1009,7 +1009,7 @@ void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
|
|
|
* @arg TMR_OC_PRELOAD_ENABLE
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
|
|
|
+void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
|
|
|
{
|
|
|
tmr->CCM2_COMPARE_B.OC3PEN = OCPreload;
|
|
|
}
|
|
|
@@ -1025,7 +1025,7 @@ void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
|
|
|
* @arg TMR_OC_PRELOAD_ENABLE
|
|
|
* @retval Nonee
|
|
|
*/
|
|
|
-void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
|
|
|
+void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
|
|
|
{
|
|
|
tmr->CCM2_COMPARE_B.OC4PEN = OCPreload;
|
|
|
}
|
|
|
@@ -1041,7 +1041,7 @@ void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
|
|
|
* @arg TMR_OC_FAST_ENABLE
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
|
|
|
+void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
|
|
|
{
|
|
|
tmr->CCM1_COMPARE_B.OC1FEN = OCFast;
|
|
|
}
|
|
|
@@ -1057,7 +1057,7 @@ void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
|
|
|
* @arg TMR_OC_FAST_ENABLE
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
|
|
|
+void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
|
|
|
{
|
|
|
tmr->CCM1_COMPARE_B.OC2FEN = OCFast;
|
|
|
}
|
|
|
@@ -1073,7 +1073,7 @@ void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
|
|
|
* @arg TMR_OC_FAST_ENABLE
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
|
|
|
+void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
|
|
|
{
|
|
|
tmr->CCM2_COMPARE_B.OC3FEN = OCFast;
|
|
|
}
|
|
|
@@ -1089,7 +1089,7 @@ void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
|
|
|
* @arg TMR_OC_FAST_ENABLE
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
|
|
|
+void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
|
|
|
{
|
|
|
tmr->CCM2_COMPARE_B.OC4FEN = OCFast;
|
|
|
}
|
|
|
@@ -1105,7 +1105,7 @@ void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
|
|
|
* @arg TMR_OC_CLEAR_ENABLE
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
|
|
|
+void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
|
|
|
{
|
|
|
tmr->CCM1_COMPARE_B.OC1CEN = OCClear;
|
|
|
}
|
|
|
@@ -1121,7 +1121,7 @@ void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
|
|
|
* @arg TMR_OC_CLEAR_ENABLE
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
|
|
|
+void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
|
|
|
{
|
|
|
tmr->CCM1_COMPARE_B.OC2CEN = OCClear;
|
|
|
}
|
|
|
@@ -1137,7 +1137,7 @@ void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
|
|
|
* @arg TMR_OC_CLEAR_ENABLE
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
|
|
|
+void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
|
|
|
{
|
|
|
tmr->CCM2_COMPARE_B.OC3CEN = OCClear;
|
|
|
}
|
|
|
@@ -1153,7 +1153,7 @@ void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
|
|
|
* @arg TMR_OC_CLEAR_ENABLE
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
|
|
|
+void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
|
|
|
{
|
|
|
tmr->CCM2_COMPARE_B.OC4CEN = OCClear;
|
|
|
}
|
|
|
@@ -1169,7 +1169,7 @@ void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
|
|
|
* @arg TMR_OC_POLARITY_LOW: Output Compare active low
|
|
|
* @retval Nonee
|
|
|
*/
|
|
|
-void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
|
|
|
+void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
|
|
|
{
|
|
|
tmr->CCEN_B.CC1POL = polarity;
|
|
|
}
|
|
|
@@ -1185,7 +1185,7 @@ void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
|
|
|
* @arg TMR_OC_NPOLARITY_LOW: Output Compare active low
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
|
|
|
+void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
|
|
|
{
|
|
|
tmr->CCEN_B.CC1NPOL = nPolarity;
|
|
|
}
|
|
|
@@ -1201,7 +1201,7 @@ void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
|
|
|
* @arg TMR_OC_POLARITY_LOW: Output Compare active low
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
|
|
|
+void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
|
|
|
{
|
|
|
tmr->CCEN_B.CC2POL = polarity;
|
|
|
}
|
|
|
@@ -1217,7 +1217,7 @@ void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
|
|
|
* @arg TMR_OC_NPOLARITY_LOW: Output Compare active low
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
|
|
|
+void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
|
|
|
{
|
|
|
tmr->CCEN_B.CC2NPOL = nPolarity;
|
|
|
}
|
|
|
@@ -1233,7 +1233,7 @@ void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
|
|
|
* @arg TMR_OC_POLARITY_LOW: Output Compare active low
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
|
|
|
+void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
|
|
|
{
|
|
|
tmr->CCEN_B.CC3POL = polarity;
|
|
|
}
|
|
|
@@ -1249,7 +1249,7 @@ void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
|
|
|
* @arg TMR_OC_NPOLARITY_LOW: Output Compare active low
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
|
|
|
+void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
|
|
|
{
|
|
|
tmr->CCEN_B.CC3NPOL = nPolarity;
|
|
|
}
|
|
|
@@ -1265,7 +1265,7 @@ void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
|
|
|
* @arg TMR_OC_POLARITY_LOW: Output Compare active low
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
|
|
|
+void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
|
|
|
{
|
|
|
tmr->CCEN_B.CC4POL = polarity;
|
|
|
}
|
|
|
@@ -1283,7 +1283,7 @@ void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
|
|
|
* @arg TMR_CHANNEL_4: Timer Channel 4
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
|
|
|
+void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
|
|
|
{
|
|
|
tmr->CCEN |= BIT_SET << channel;
|
|
|
}
|
|
|
@@ -1301,7 +1301,7 @@ void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
|
|
|
* @arg TMR_CHANNEL_4: Timer Channel 4
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
|
|
|
+void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
|
|
|
{
|
|
|
tmr->CCEN &= BIT_RESET << channel;
|
|
|
}
|
|
|
@@ -1318,7 +1318,7 @@ void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
|
|
|
* @arg TMR_CHANNEL_3: Timer Channel 3
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
|
|
|
+void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
|
|
|
{
|
|
|
tmr->CCEN |= 0x04 << channel;
|
|
|
}
|
|
|
@@ -1335,7 +1335,7 @@ void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
|
|
|
* @arg TMR_CHANNEL_3: Timer Channel 3
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
|
|
|
+void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
|
|
|
{
|
|
|
tmr->CCEN &= BIT_RESET << channel;
|
|
|
}
|
|
|
@@ -1364,7 +1364,7 @@ void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
|
|
|
* @arg TMR_OC_MODE_PWM2
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode)
|
|
|
+void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode)
|
|
|
{
|
|
|
tmr->CCEN &= BIT_RESET << channel;
|
|
|
|
|
|
@@ -1393,7 +1393,7 @@ void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_EnableUpdate(TMR_T *tmr)
|
|
|
+void TMR_EnableUpdate(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->CTRL1_B.UD = DISABLE;
|
|
|
}
|
|
|
@@ -1405,7 +1405,7 @@ void TMR_EnableUpdate(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_DisableUpdate(TMR_T *tmr)
|
|
|
+void TMR_DisableUpdate(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->CTRL1_B.UD = ENABLE;
|
|
|
}
|
|
|
@@ -1421,7 +1421,7 @@ void TMR_DisableUpdate(TMR_T *tmr)
|
|
|
* @arg TMR_UPDATE_SOURCE_REGULAR
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource)
|
|
|
+void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource)
|
|
|
{
|
|
|
if (updateSource != TMR_UPDATE_SOURCE_GLOBAL)
|
|
|
{
|
|
|
@@ -1440,7 +1440,7 @@ void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_EnableHallSensor(TMR_T *tmr)
|
|
|
+void TMR_EnableHallSensor(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->CTRL2_B.TI1SEL = ENABLE;
|
|
|
}
|
|
|
@@ -1452,7 +1452,7 @@ void TMR_EnableHallSensor(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_DisableHallSensor(TMR_T *tmr)
|
|
|
+void TMR_DisableHallSensor(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->CTRL2_B.TI1SEL = DISABLE;
|
|
|
}
|
|
|
@@ -1468,7 +1468,7 @@ void TMR_DisableHallSensor(TMR_T *tmr)
|
|
|
* @arg TMR_SPM_SINGLE
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode)
|
|
|
+void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode)
|
|
|
{
|
|
|
tmr->CTRL1_B.SPMEN = singlePulseMode;
|
|
|
}
|
|
|
@@ -1491,7 +1491,7 @@ void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode)
|
|
|
* @arg TMR_TRGO_SOURCE_OC4REF
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource)
|
|
|
+void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource)
|
|
|
{
|
|
|
tmr->CTRL2_B.MMSEL = TRGOSource;
|
|
|
}
|
|
|
@@ -1509,7 +1509,7 @@ void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource)
|
|
|
* @arg TMR_SLAVE_MODE_EXTERNAL1
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode)
|
|
|
+void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode)
|
|
|
{
|
|
|
tmr->SMCTRL_B.SMFSEL = slaveMode;
|
|
|
}
|
|
|
@@ -1521,7 +1521,7 @@ void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_EnableMasterSlaveMode(TMR_T *tmr)
|
|
|
+void TMR_EnableMasterSlaveMode(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->SMCTRL_B.MSMEN = ENABLE;
|
|
|
}
|
|
|
@@ -1533,7 +1533,7 @@ void TMR_EnableMasterSlaveMode(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_DisableMasterSlaveMode(TMR_T *tmr)
|
|
|
+void TMR_DisableMasterSlaveMode(TMR_T* tmr)
|
|
|
{
|
|
|
tmr->SMCTRL_B.MSMEN = DISABLE;
|
|
|
}
|
|
|
@@ -1547,7 +1547,7 @@ void TMR_DisableMasterSlaveMode(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter)
|
|
|
+void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter)
|
|
|
{
|
|
|
tmr->CNT = counter;
|
|
|
}
|
|
|
@@ -1561,7 +1561,7 @@ void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload)
|
|
|
+void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload)
|
|
|
{
|
|
|
tmr->AUTORLD = autoReload;
|
|
|
}
|
|
|
@@ -1575,7 +1575,7 @@ void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1)
|
|
|
+void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1)
|
|
|
{
|
|
|
tmr->CC1 = compare1;
|
|
|
}
|
|
|
@@ -1589,7 +1589,7 @@ void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2)
|
|
|
+void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2)
|
|
|
{
|
|
|
tmr->CC2 = compare2;
|
|
|
}
|
|
|
@@ -1603,7 +1603,7 @@ void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3)
|
|
|
+void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3)
|
|
|
{
|
|
|
tmr->CC3 = compare3;
|
|
|
}
|
|
|
@@ -1617,7 +1617,7 @@ void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4)
|
|
|
+void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4)
|
|
|
{
|
|
|
tmr->CC4 = compare4;
|
|
|
}
|
|
|
@@ -1635,7 +1635,7 @@ void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4)
|
|
|
* @arg TMR_IC_PSC_8: capture is done once every 8 events
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
|
|
|
+void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
|
|
|
{
|
|
|
tmr->CCM1_CAPTURE_B.IC1PSC = BIT_RESET;
|
|
|
tmr->CCM1_CAPTURE_B.IC1PSC = prescaler;
|
|
|
@@ -1653,7 +1653,7 @@ void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
|
|
|
* @arg TMR_IC_PSC_8: capture is done once every 8 events
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
|
|
|
+void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
|
|
|
{
|
|
|
tmr->CCM1_CAPTURE_B.IC2PSC = BIT_RESET;
|
|
|
tmr->CCM1_CAPTURE_B.IC2PSC = prescaler;
|
|
|
@@ -1672,7 +1672,7 @@ void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
|
|
|
* @arg TMR_IC_PSC_8: capture is done once every 8 events
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
|
|
|
+void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
|
|
|
{
|
|
|
tmr->CCM2_CAPTURE_B.IC3PSC = BIT_RESET;
|
|
|
tmr->CCM2_CAPTURE_B.IC3PSC = prescaler;
|
|
|
@@ -1691,7 +1691,7 @@ void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
|
|
|
* @arg TMR_IC_PSC_8: capture is done once every 8 events
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
|
|
|
+void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
|
|
|
{
|
|
|
tmr->CCM2_CAPTURE_B.IC4PSC = BIT_RESET;
|
|
|
tmr->CCM2_CAPTURE_B.IC4PSC = prescaler;
|
|
|
@@ -1709,7 +1709,7 @@ void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
|
|
|
* @arg TMR_CLOCK_DIV_4: TDTS = 4*Tck_tim
|
|
|
* @retval None
|
|
|
*/
|
|
|
-void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision)
|
|
|
+void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision)
|
|
|
{
|
|
|
tmr->CTRL1_B.CLKDIV = clockDivision;
|
|
|
}
|
|
|
@@ -1721,7 +1721,7 @@ void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision)
|
|
|
*
|
|
|
* @retval Capture Compare 1 Register value.
|
|
|
*/
|
|
|
-uint16_t TMR_ReadCaputer1(TMR_T *tmr)
|
|
|
+uint16_t TMR_ReadCaputer1(TMR_T* tmr)
|
|
|
{
|
|
|
return tmr->CC1;
|
|
|
}
|
|
|
@@ -1733,7 +1733,7 @@ uint16_t TMR_ReadCaputer1(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval Capture Compare 2 Register value.
|
|
|
*/
|
|
|
-uint16_t TMR_ReadCaputer2(TMR_T *tmr)
|
|
|
+uint16_t TMR_ReadCaputer2(TMR_T* tmr)
|
|
|
{
|
|
|
return tmr->CC2;
|
|
|
}
|
|
|
@@ -1745,7 +1745,7 @@ uint16_t TMR_ReadCaputer2(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval Capture Compare 3 Register value.
|
|
|
*/
|
|
|
-uint16_t TMR_ReadCaputer3(TMR_T *tmr)
|
|
|
+uint16_t TMR_ReadCaputer3(TMR_T* tmr)
|
|
|
{
|
|
|
return tmr->CC3;
|
|
|
}
|
|
|
@@ -1757,7 +1757,7 @@ uint16_t TMR_ReadCaputer3(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval Capture Compare 4 Register value.
|
|
|
*/
|
|
|
-uint16_t TMR_ReadCaputer4(TMR_T *tmr)
|
|
|
+uint16_t TMR_ReadCaputer4(TMR_T* tmr)
|
|
|
{
|
|
|
return tmr->CC4;
|
|
|
}
|
|
|
@@ -1769,7 +1769,7 @@ uint16_t TMR_ReadCaputer4(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval Counter Register value.
|
|
|
*/
|
|
|
-uint16_t TMR_ReadCounter(TMR_T *tmr)
|
|
|
+uint16_t TMR_ReadCounter(TMR_T* tmr)
|
|
|
{
|
|
|
return tmr->CNT;
|
|
|
}
|
|
|
@@ -1781,7 +1781,7 @@ uint16_t TMR_ReadCounter(TMR_T *tmr)
|
|
|
*
|
|
|
* @retval Prescaler Register value.
|
|
|
*/
|
|
|
-uint16_t TMR_ReadPrescaler(TMR_T *tmr)
|
|
|
+uint16_t TMR_ReadPrescaler(TMR_T* tmr)
|
|
|
{
|
|
|
return tmr->PSC;
|
|
|
}
|
|
|
@@ -1805,7 +1805,7 @@ uint16_t TMR_ReadPrescaler(TMR_T *tmr)
|
|
|
*
|
|
|
* @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
|
|
|
*/
|
|
|
-void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt)
|
|
|
+void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt)
|
|
|
{
|
|
|
tmr->DIEN |= interrupt;
|
|
|
}
|
|
|
@@ -1829,7 +1829,7 @@ void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt)
|
|
|
*
|
|
|
* @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
|
|
|
*/
|
|
|
-void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt)
|
|
|
+void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt)
|
|
|
{
|
|
|
tmr->DIEN &= ~interrupt;
|
|
|
}
|
|
|
@@ -1853,7 +1853,7 @@ void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt)
|
|
|
*
|
|
|
* @note TMR6 and TMR7 can only generate an TMR_EVENT_UPDATE.
|
|
|
*/
|
|
|
-void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources)
|
|
|
+void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources)
|
|
|
{
|
|
|
tmr->CEG = eventSources;
|
|
|
}
|
|
|
@@ -1881,7 +1881,7 @@ void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources)
|
|
|
*
|
|
|
* @note TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE.
|
|
|
*/
|
|
|
-uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag)
|
|
|
+uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag)
|
|
|
{
|
|
|
return (tmr->STS & flag) ? SET : RESET;
|
|
|
}
|
|
|
@@ -1909,7 +1909,7 @@ uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag)
|
|
|
*
|
|
|
* @note TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE.
|
|
|
*/
|
|
|
-void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag)
|
|
|
+void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag)
|
|
|
{
|
|
|
tmr->STS = ~flag;
|
|
|
}
|
|
|
@@ -1933,9 +1933,9 @@ void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag)
|
|
|
*
|
|
|
* @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
|
|
|
*/
|
|
|
-uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag)
|
|
|
+uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag)
|
|
|
{
|
|
|
- if (((tmr->STS & flag) != RESET) && ((tmr->DIEN & flag) != RESET))
|
|
|
+ if (((tmr->STS & flag) != RESET ) && ((tmr->DIEN & flag) != RESET))
|
|
|
{
|
|
|
return SET;
|
|
|
}
|
|
|
@@ -1964,7 +1964,7 @@ uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag)
|
|
|
*
|
|
|
* @note TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
|
|
|
*/
|
|
|
-void TMR_ClearIntFlag(TMR_T *tmr, uint16_t flag)
|
|
|
+void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag)
|
|
|
{
|
|
|
tmr->STS = ~flag;
|
|
|
}
|
|
|
@@ -1982,7 +1982,7 @@ void TMR_ClearIntFlag(TMR_T *tmr, uint16_t flag)
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
|
|
|
+static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
|
|
|
{
|
|
|
uint16_t tmpchctrl = 0;
|
|
|
|
|
|
@@ -1994,7 +1994,7 @@ static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
|
|
|
tmr->CCM1_CAPTURE_B.IC1F = ICfilter;
|
|
|
|
|
|
if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
|
|
|
- (tmr == TMR4) || (tmr == TMR5))
|
|
|
+ (tmr == TMR4) || (tmr == TMR5))
|
|
|
{
|
|
|
tmr->CCEN_B.CC1POL = BIT_RESET;
|
|
|
tmr->CCEN_B.CC1EN = BIT_SET;
|
|
|
@@ -2026,7 +2026,7 @@ static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
|
|
|
+static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
|
|
|
{
|
|
|
uint16_t tmpchctrl = 0;
|
|
|
|
|
|
@@ -2038,7 +2038,7 @@ static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
|
|
|
tmr->CCM1_CAPTURE_B.IC2F = ICfilter;
|
|
|
|
|
|
if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
|
|
|
- (tmr == TMR4) || (tmr == TMR5))
|
|
|
+ (tmr == TMR4) || (tmr == TMR5))
|
|
|
{
|
|
|
tmr->CCEN_B.CC2POL = BIT_RESET;
|
|
|
tmr->CCEN_B.CC2EN = BIT_SET;
|
|
|
@@ -2070,7 +2070,7 @@ static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
|
|
|
*
|
|
|
* @retval None
|
|
|
*/
|
|
|
-static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
|
|
|
+static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
|
|
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{
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uint16_t tmpchctrl = 0;
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@@ -2082,7 +2082,7 @@ static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
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tmr->CCM2_CAPTURE_B.IC3F = ICfilter;
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if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
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- (tmr == TMR4) || (tmr == TMR5))
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+ (tmr == TMR4) || (tmr == TMR5))
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{
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tmr->CCEN_B.CC3POL = BIT_RESET;
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tmr->CCEN_B.CC3EN = BIT_SET;
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@@ -2114,7 +2114,7 @@ static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uin
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*
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* @retval None
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*/
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-static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
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+static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
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{
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uint16_t tmpchctrl = 0;
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