[BSP] Add imx6sx

bsp/imx6sx/README.md

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+# i.MX6 SoloX
+
+Freescale's Smart Application Blueprint for Rapid Engineering (SABRE) board for smart devices
+
+Rev.B
+
+CPU: MCIMX6X4EVM10AB
+
+* ARM Cortex-A9 @ 1GHz
+* ARM Cortex-M4 @ 200MHz
+
+* Freescale PF0200 PMIC
+* 1GB DDR3
+* 32 MB x2 QuadSPI Flash
+
+* Freescale MMA8451 3-Axis Accelerometer
+* Freescale MAG3110 3D Magnetometer

bsp/imx6sx/cortex-a9/SConscript

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+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/imx6sx/cortex-a9/SConstruct

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+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-imx6.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+        CXX= rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT,has_libcpu=True)
+
+objs += SConscript('../iMX6_Platform_SDK/SConscript', variant_dir='build/iMX6_Platform_SDK/SConscript', duplicate=0)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/imx6sx/cortex-a9/applications/SConscript

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+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/imx6sx/cortex-a9/applications/application.c

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+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-11-20     Bernard    the first version
+ */
+
+#include <rtthread.h>
+#include <components.h>
+
+#include <sdk.h>
+#include <core/ccm_pll.h>
+
+void show_freq(void)
+{
+    rt_kprintf("CPU: %d MHz\n", get_main_clock(CPU_CLK)/1000000);
+    rt_kprintf("DDR: %d MHz\n", get_main_clock(MMDC_CH0_AXI_CLK)/1000000);
+    rt_kprintf("IPG: %d MHz\n", get_main_clock(IPG_CLK)/1000000);
+}
+
+void init_thread(void* parameter)
+{
+    rt_kprintf("Freescale i.MX6 Platform SDK %s\n", SDK_VERSION_STRING);
+    show_freq();
+
+    rt_components_init();
+}
+
+int rt_application_init()
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init", init_thread, RT_NULL,
+        1024, RT_THREAD_PRIORITY_MAX/3, 10);
+    if (tid != RT_NULL) rt_thread_startup(tid);
+
+    return 0;
+}

bsp/imx6sx/cortex-a9/applications/startup.c

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+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-12-05     Bernard      the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <board.h>
+
+extern int  rt_application_init(void);
+extern void rt_hw_board_init(void);
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    // platform_init();
+    // print_version();
+
+    /* initialzie hardware interrupt */
+    rt_hw_interrupt_init();
+
+    /* initialize board */
+    rt_hw_board_init();
+
+    /* show RT-Thread version */
+    rt_show_version();
+
+    /* initialize memory system */
+#ifdef RT_USING_HEAP
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+#endif
+
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
+
+    /* initialize timer and soft timer thread */
+    rt_system_timer_init();
+    rt_system_timer_thread_init();
+
+    /* initialize application */
+    rt_application_init();
+
+    /* initialize idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* invoke rtthread_startup */
+    rtthread_startup();
+
+    return 0;
+}

bsp/imx6sx/cortex-a9/board/SConscript

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+import copy
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/imx6sx/cortex-a9/board/audmux_iomux_config.c

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+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: audmux_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for audmux module.
+void audmux_iomux_config(void)
+{
+    // Config audmux.AUD5_RXD to pad DISP0_DATA19(U23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_WR(0x00000003);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR(0x0001B0B0);
+    // HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19(0x020E00DC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA19
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA19
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_SCLK
+    //     ALT3 (3) - Select instance: audmux signal: AUD5_RXD
+    //     ALT4 (4) - Select instance: audmux signal: AUD4_RXC
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO13
+    //     ALT7 (7) - Select instance: eim signal: EIM_CS3
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19_MUX_MODE_V(ALT3));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19(0x020E03F0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19_SRE_V(SLOW));
+    // Pad DISP0_DATA19 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT(0x020E07B0)
+    //   DAISY [0] - MUX Mode Select Field Reset: DISP0_DATA19_ALT3
+    //               Selecting Pads Involved in Daisy Chain.
+    //     DISP0_DATA19_ALT3 (0) - Select signal audmux AUD5_RXD as input from pad DISP0_DATA19(ALT3).
+    //     KEY_ROW1_ALT2 (1) - Select signal audmux AUD5_RXD as input from pad KEY_ROW1(ALT2).
+    HW_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_WR(
+            BF_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT_DAISY_V(DISP0_DATA19_ALT3));
+
+    // Config audmux.AUD5_TXC to pad DISP0_DATA16(T21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_WR(0x00000003);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR(0x0001B0B0);
+    // HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16(0x020E00D0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA16
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA16
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_MOSI
+    //     ALT3 (3) - Select instance: audmux signal: AUD5_TXC
+    //     ALT4 (4) - Select instance: sdma signal: SDMA_EXT_EVENT0
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO10
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE_V(ALT3));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16(0x020E03E4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE_V(SLOW));
+    // Pad DISP0_DATA16 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT(0x020E07C0)
+    //   DAISY [0] - MUX Mode Select Field Reset: DISP0_DATA16_ALT3
+    //               Selecting Pads Involved in Daisy Chain.
+    //     DISP0_DATA16_ALT3 (0) - Select signal audmux AUD5_TXC as input from pad DISP0_DATA16(ALT3).
+    //     KEY_COL0_ALT2 (1) - Select signal audmux AUD5_TXC as input from pad KEY_COL0(ALT2).
+    HW_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_WR(
+            BF_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_V(DISP0_DATA16_ALT3));
+
+    // Config audmux.AUD5_TXFS to pad DISP0_DATA18(V25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_WR(0x00000003);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR(0x0001B0B0);
+    // HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18(0x020E00D8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA18
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA18
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_SS0
+    //     ALT3 (3) - Select instance: audmux signal: AUD5_TXFS
+    //     ALT4 (4) - Select instance: audmux signal: AUD4_RXFS
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO12
+    //     ALT7 (7) - Select instance: eim signal: EIM_CS2
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18_MUX_MODE_V(ALT3));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18(0x020E03EC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18_SRE_V(SLOW));
+    // Pad DISP0_DATA18 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT(0x020E07C4)
+    //   DAISY [0] - MUX Mode Select Field Reset: DISP0_DATA18_ALT3
+    //               Selecting Pads Involved in Daisy Chain.
+    //     DISP0_DATA18_ALT3 (0) - Select signal audmux AUD5_TXFS as input from pad DISP0_DATA18(ALT3).
+    //     KEY_COL1_ALT2 (1) - Select signal audmux AUD5_TXFS as input from pad KEY_COL1(ALT2).
+    HW_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_WR(
+            BF_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_V(DISP0_DATA18_ALT3));
+
+    // Config audmux.AUD6_RXD to pad DI0_PIN04(P25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04(0x020E00AC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_PIN04
+    //     ALT1 (1) - Select instance: lcd signal: LCD_BUSY
+    //     ALT2 (2) - Select instance: audmux signal: AUD6_RXD
+    //     ALT3 (3) - Select instance: usdhc1 signal: SD1_WP
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO20
+    //     ALT8 (8) - Select instance: lcd signal: LCD_RESET
+    HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04(0x020E03C0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE_V(SLOW));
+
+    // Config audmux.AUD6_TXC to pad DI0_PIN15(N21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15(0x020E00A0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_PIN15
+    //     ALT1 (1) - Select instance: lcd signal: LCD_ENABLE
+    //     ALT2 (2) - Select instance: audmux signal: AUD6_TXC
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO17
+    //     ALT8 (8) - Select instance: lcd signal: LCD_RD_E
+    HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15(0x020E03B4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE_V(SLOW));
+
+    // Config audmux.AUD6_TXD to pad DI0_PIN02(N25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02(0x020E00A4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_PIN02
+    //     ALT1 (1) - Select instance: lcd signal: LCD_HSYNC
+    //     ALT2 (2) - Select instance: audmux signal: AUD6_TXD
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO18
+    //     ALT8 (8) - Select instance: lcd signal: LCD_RS
+    HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02(0x020E03B8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE_V(SLOW));
+
+    // Config audmux.AUD6_TXFS to pad DI0_PIN03(N20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03(0x020E00A8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_PIN03
+    //     ALT1 (1) - Select instance: lcd signal: LCD_VSYNC
+    //     ALT2 (2) - Select instance: audmux signal: AUD6_TXFS
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO19
+    //     ALT8 (8) - Select instance: lcd signal: LCD_CS
+    HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03(0x020E03BC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/ccm_iomux_config.c

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: ccm_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for ccm module.
+void ccm_iomux_config(void)
+{
+    // Config ccm.CCM_CLKO1 to pad GPIO00(T5)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO00(0x020E020C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ccm signal: CCM_CLKO1
+    //     ALT2 (2) - Select instance: kpp signal: KEY_COL5
+    //     ALT3 (3) - Select instance: asrc signal: ASRC_EXT_CLK
+    //     ALT4 (4) - Select instance: epit1 signal: EPIT1_OUT
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO00
+    //     ALT6 (6) - Select instance: usb signal: USB_H1_PWR
+    //     ALT7 (7) - Select instance: snvs signal: SNVS_VIO_5
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO00(0x020E05DC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/dcic_iomux_config.c

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: dcic_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsdcic.h"
+#include "io.h"
+#include <assert.h>
+
+void dcic_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_DCIC1:
+            return dcic1_iomux_config();
+
+        case HW_DCIC2:
+            return dcic2_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/ecspi1_iomux_config.c

@@ -0,0 +1,431 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: ecspi1_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for ecspi1 module.
+void ecspi1_iomux_config(void)
+{
+    // Config ecspi1.ECSPI1_MISO to pad EIM_DATA17(F21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR(0x0001B0B0);
+    // HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_WR(0x00000002);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17(0x020E0148)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA17
+    //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_MISO
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN06
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_PIXCLK
+    //     ALT4 (4) - Select instance: dcic1 signal: DCIC1_OUT
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO17
+    //     ALT6 (6) - Select instance: i2c3 signal: I2C3_SCL
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_VCOM0
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17(0x020E0518)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE_V(SLOW));
+    // Pad EIM_DATA17 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ECSPI1_MISO_SELECT_INPUT(0x020E07DC)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: CSI0_DATA06_ALT2
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     CSI0_DATA06_ALT2 (0) - Select signal ecspi1 ECSPI1_MISO as input from pad CSI0_DATA06(ALT2).
+    //     DISP0_DATA22_ALT2 (1) - Select signal ecspi1 ECSPI1_MISO as input from pad DISP0_DATA22(ALT2).
+    //     EIM_DATA17_ALT1 (2) - Select signal ecspi1 ECSPI1_MISO as input from pad EIM_DATA17(ALT1).
+    //     KEY_COL1_ALT0 (3) - Select signal ecspi1 ECSPI1_MISO as input from pad KEY_COL1(ALT0).
+    HW_IOMUXC_ECSPI1_MISO_SELECT_INPUT_WR(
+            BF_IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY_V(EIM_DATA17_ALT1));
+
+    // Config ecspi1.ECSPI1_MOSI to pad EIM_DATA18(D24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(0x0001B0B0);
+    // HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_WR(0x00000002);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18(0x020E014C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA18
+    //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_MOSI
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN07
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA17
+    //     ALT4 (4) - Select instance: ipu1 signal: IPU1_DI1_D0_CS
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO18
+    //     ALT6 (6) - Select instance: i2c3 signal: I2C3_SDA
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_VCOM1
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18(0x020E051C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE_V(SLOW));
+    // Pad EIM_DATA18 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ECSPI1_MOSI_SELECT_INPUT(0x020E07E0)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: CSI0_DATA05_ALT2
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     CSI0_DATA05_ALT2 (0) - Select signal ecspi1 ECSPI1_MOSI as input from pad CSI0_DATA05(ALT2).
+    //     DISP0_DATA21_ALT2 (1) - Select signal ecspi1 ECSPI1_MOSI as input from pad DISP0_DATA21(ALT2).
+    //     EIM_DATA18_ALT1 (2) - Select signal ecspi1 ECSPI1_MOSI as input from pad EIM_DATA18(ALT1).
+    //     KEY_ROW0_ALT0 (3) - Select signal ecspi1 ECSPI1_MOSI as input from pad KEY_ROW0(ALT0).
+    HW_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_WR(
+            BF_IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY_V(EIM_DATA18_ALT1));
+
+    // Config ecspi1.ECSPI1_RDY to pad GPIO19(P5)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_WR(0x00000004);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO19(0x020E0220)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: kpp signal: KEY_COL5
+    //     ALT1 (1) - Select instance: enet signal: ENET_1588_EVENT0_OUT
+    //     ALT2 (2) - Select instance: spdif signal: SPDIF_OUT
+    //     ALT3 (3) - Select instance: ccm signal: CCM_CLKO1
+    //     ALT4 (4) - Select instance: ecspi1 signal: ECSPI1_RDY
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO05
+    //     ALT6 (6) - Select instance: enet signal: ENET_TX_ER
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE_V(ALT4));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO19(0x020E05F0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE_V(SLOW));
+
+    // Config ecspi1.ECSPI1_SCLK to pad EIM_DATA16(C25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR(0x0001B0B0);
+    // HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_WR(0x00000002);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16(0x020E0144)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA16
+    //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_SCLK
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN05
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA18
+    //     ALT4 (4) - Select instance: hdmi signal: HDMI_TX_DDC_SDA
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO16
+    //     ALT6 (6) - Select instance: i2c2 signal: I2C2_SDA
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA10
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16(0x020E0514)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE_V(SLOW));
+    // Pad EIM_DATA16 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT(0x020E07D8)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: CSI0_DATA04_ALT2
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     CSI0_DATA04_ALT2 (0) - Select signal ecspi1 ECSPI1_SCLK as input from pad CSI0_DATA04(ALT2).
+    //     DISP0_DATA20_ALT2 (1) - Select signal ecspi1 ECSPI1_SCLK as input from pad DISP0_DATA20(ALT2).
+    //     EIM_DATA16_ALT1 (2) - Select signal ecspi1 ECSPI1_SCLK as input from pad EIM_DATA16(ALT1).
+    //     KEY_COL0_ALT0 (3) - Select signal ecspi1 ECSPI1_SCLK as input from pad KEY_COL0(ALT0).
+    HW_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_WR(
+            BF_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT_DAISY_V(EIM_DATA16_ALT1));
+
+    // Config ecspi1.ECSPI1_SS1 to pad EIM_DATA19(G21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR(0x0001B0B0);
+    // HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19(0x020E0150)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA19
+    //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_SS1
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN08
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA16
+    //     ALT4 (4) - Select instance: uart1 signal: UART1_CTS_B
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO19
+    //     ALT6 (6) - Select instance: epit1 signal: EPIT1_OUT
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA12
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19(0x020E0520)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE_V(SLOW));
+    // Pad EIM_DATA19 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ECSPI1_SS1_SELECT_INPUT(0x020E07E8)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: DISP0_DATA15_ALT2
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     DISP0_DATA15_ALT2 (0) - Select signal ecspi1 ECSPI1_SS1 as input from pad DISP0_DATA15(ALT2).
+    //     EIM_DATA19_ALT1 (1) - Select signal ecspi1 ECSPI1_SS1 as input from pad EIM_DATA19(ALT1).
+    //     KEY_COL2_ALT0 (2) - Select signal ecspi1 ECSPI1_SS1 as input from pad KEY_COL2(ALT0).
+    HW_IOMUXC_ECSPI1_SS1_SELECT_INPUT_WR(
+            BF_IOMUXC_ECSPI1_SS1_SELECT_INPUT_DAISY_V(EIM_DATA19_ALT1));
+}

bsp/imx6sx/cortex-a9/board/ecspi_iomux_config.c

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: ecspi_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsecspi.h"
+#include "io.h"
+#include <assert.h>
+
+void ecspi_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_ECSPI1:
+            return ecspi1_iomux_config();
+
+        case HW_ECSPI2:
+            return ecspi2_iomux_config();
+
+        case HW_ECSPI3:
+            return ecspi3_iomux_config();
+
+        case HW_ECSPI4:
+            return ecspi4_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/eim_iomux_config.c

@@ -0,0 +1,3060 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: eim_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for eim module.
+void eim_iomux_config(void)
+{
+    // Config eim.EIM_AD00 to pad EIM_AD00(L20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD00(0x020E0184)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD00
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA09
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA09
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO00
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG00
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCLK_N
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD00(0x020E0554)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE_V(FAST));
+
+    // Config eim.EIM_AD01 to pad EIM_AD01(J25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD01(0x020E0188)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD01
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA08
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA08
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO01
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG01
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDLE
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD01(0x020E0558)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE_V(FAST));
+
+    // Config eim.EIM_AD02 to pad EIM_AD02(L21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD02(0x020E01A4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD02
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA07
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA07
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO02
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG02
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_BDR0
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD02(0x020E0574)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE_V(FAST));
+
+    // Config eim.EIM_AD03 to pad EIM_AD03(K24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD03(0x020E01A8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD03
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA06
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA06
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO03
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG03
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_BDR1
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD03(0x020E0578)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE_V(FAST));
+
+    // Config eim.EIM_AD04 to pad EIM_AD04(L22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD04(0x020E01AC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD04
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA05
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA05
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO04
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG04
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE0
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD04(0x020E057C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE_V(FAST));
+
+    // Config eim.EIM_AD05 to pad EIM_AD05(L23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD05(0x020E01B0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD05
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA04
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA04
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO05
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG05
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE1
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD05(0x020E0580)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE_V(FAST));
+
+    // Config eim.EIM_AD06 to pad EIM_AD06(K25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD06(0x020E01B4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD06
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA03
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA03
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO06
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG06
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE2
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD06(0x020E0584)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE_V(FAST));
+
+    // Config eim.EIM_AD07 to pad EIM_AD07(L25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD07(0x020E01B8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD07
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA02
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA02
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO07
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG07
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE3
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD07(0x020E0588)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE_V(FAST));
+
+    // Config eim.EIM_AD08 to pad EIM_AD08(L24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD08(0x020E01BC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD08
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA01
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA01
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO08
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG08
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE4
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD08(0x020E058C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE_V(FAST));
+
+    // Config eim.EIM_AD09 to pad EIM_AD09(M21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD09(0x020E01C0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD09
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA00
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA00
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO09
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG09
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE5
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD09(0x020E0590)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE_V(FAST));
+
+    // Config eim.EIM_AD10 to pad EIM_AD10(M22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD10(0x020E018C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD10
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN15
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA_EN
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO10
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG10
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA01
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD10(0x020E055C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE_V(FAST));
+
+    // Config eim.EIM_AD11 to pad EIM_AD11(M20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD11(0x020E0190)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD11
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN02
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_HSYNC
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO11
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG11
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA03
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD11(0x020E0560)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE_V(FAST));
+
+    // Config eim.EIM_AD12 to pad EIM_AD12(M24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD12(0x020E0194)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD12
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN03
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_VSYNC
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO12
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG12
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA02
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD12(0x020E0564)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE_V(FAST));
+
+    // Config eim.EIM_AD13 to pad EIM_AD13(M23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD13(0x020E0198)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD13
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_D0_CS
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO13
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG13
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA13
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD13(0x020E0568)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE_V(FAST));
+
+    // Config eim.EIM_AD14 to pad EIM_AD14(N23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD14(0x020E019C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD14
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_D1_CS
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO14
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG14
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA14
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD14(0x020E056C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE_V(FAST));
+
+    // Config eim.EIM_AD15 to pad EIM_AD15(N24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_AD15(0x020E01A0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_AD15
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN01
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI1_PIN04
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO15
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG15
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA09
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_AD15(0x020E0570)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE_V(FAST));
+
+    // Config eim.EIM_ADDR16 to pad EIM_ADDR16(H25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16(0x020E0110)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_ADDR16
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_DISP_CLK
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_PIXCLK
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO22
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG16
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA00
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16(0x020E04E0)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE_V(FAST));
+
+    // Config eim.EIM_ADDR17 to pad EIM_ADDR17(G24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17(0x020E0114)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_ADDR17
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA12
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA12
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO21
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG17
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_STAT
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17(0x020E04E4)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE_V(FAST));
+
+    // Config eim.EIM_ADDR18 to pad EIM_ADDR18(J22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18(0x020E0118)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_ADDR18
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA13
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA13
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO20
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG18
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_CTRL0
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18(0x020E04E8)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE_V(FAST));
+
+    // Config eim.EIM_ADDR19 to pad EIM_ADDR19(G25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19(0x020E011C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_ADDR19
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA14
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA14
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO19
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG19
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_CTRL1
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19(0x020E04EC)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE_V(FAST));
+
+    // Config eim.EIM_ADDR20 to pad EIM_ADDR20(H22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20(0x020E0120)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_ADDR20
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA15
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA15
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO18
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG20
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_CTRL2
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20(0x020E04F0)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE_V(FAST));
+
+    // Config eim.EIM_ADDR21 to pad EIM_ADDR21(H23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21(0x020E0124)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_ADDR21
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA16
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA16
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO17
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG21
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_GDCLK
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21(0x020E04F4)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE_V(FAST));
+
+    // Config eim.EIM_ADDR22 to pad EIM_ADDR22(F24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22(0x020E0128)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_ADDR22
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA17
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA17
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO16
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG22
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_GDSP
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22(0x020E04F8)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE_V(FAST));
+
+    // Config eim.EIM_ADDR23 to pad EIM_ADDR23(J21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23(0x020E012C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_ADDR23
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA18
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA18
+    //     ALT4 (4) - Select instance: ipu1 signal: IPU1_SISG3
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO06
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG23
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_GDOE
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23(0x020E04FC)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE_V(FAST));
+
+    // Config eim.EIM_CS0 to pad EIM_CS0(H24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_CS0(0x020E013C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_CS0
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN05
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_SCLK
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO23
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA06
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_CS0(0x020E050C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE_V(FAST));
+
+    // Config eim.EIM_DATA16 to pad EIM_DATA16(C25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16(0x020E0144)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA16
+    //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_SCLK
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN05
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA18
+    //     ALT4 (4) - Select instance: hdmi signal: HDMI_TX_DDC_SDA
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO16
+    //     ALT6 (6) - Select instance: i2c2 signal: I2C2_SDA
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA10
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16(0x020E0514)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA17 to pad EIM_DATA17(F21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17(0x020E0148)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA17
+    //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_MISO
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN06
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_PIXCLK
+    //     ALT4 (4) - Select instance: dcic1 signal: DCIC1_OUT
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO17
+    //     ALT6 (6) - Select instance: i2c3 signal: I2C3_SCL
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_VCOM0
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17(0x020E0518)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA18 to pad EIM_DATA18(D24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18(0x020E014C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA18
+    //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_MOSI
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN07
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA17
+    //     ALT4 (4) - Select instance: ipu1 signal: IPU1_DI1_D0_CS
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO18
+    //     ALT6 (6) - Select instance: i2c3 signal: I2C3_SDA
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_VCOM1
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18(0x020E051C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA19 to pad EIM_DATA19(G21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19(0x020E0150)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA19
+    //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_SS1
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN08
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA16
+    //     ALT4 (4) - Select instance: uart1 signal: UART1_CTS_B
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO19
+    //     ALT6 (6) - Select instance: epit1 signal: EPIT1_OUT
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA12
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19(0x020E0520)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA20 to pad EIM_DATA20(G20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20(0x020E0154)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA20
+    //     ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_SS0
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN16
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA15
+    //     ALT4 (4) - Select instance: uart1 signal: UART1_RTS_B
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO20
+    //     ALT6 (6) - Select instance: epit2 signal: EPIT2_OUT
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20(0x020E0524)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA21 to pad EIM_DATA21(H20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21(0x020E0158)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA21
+    //     ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_SCLK
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN17
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA11
+    //     ALT4 (4) - Select instance: usb signal: USB_OTG_OC
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO21
+    //     ALT6 (6) - Select instance: i2c1 signal: I2C1_SCL
+    //     ALT7 (7) - Select instance: spdif signal: SPDIF_IN
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21(0x020E0528)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA22 to pad EIM_DATA22(E23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22(0x020E015C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA22
+    //     ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_MISO
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN01
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA10
+    //     ALT4 (4) - Select instance: usb signal: USB_OTG_PWR
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO22
+    //     ALT6 (6) - Select instance: spdif signal: SPDIF_OUT
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE6
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22(0x020E052C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA23 to pad EIM_DATA23(D25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23(0x020E0160)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA23
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI0_D0_CS
+    //     ALT2 (2) - Select instance: uart3 signal: UART3_CTS_B
+    //     ALT3 (3) - Select instance: uart1 signal: UART1_DCD_B
+    //     ALT4 (4) - Select instance: ipu1 signal: IPU1_CSI1_DATA_EN
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO23
+    //     ALT6 (6) - Select instance: ipu1 signal: IPU1_DI1_PIN02
+    //     ALT7 (7) - Select instance: ipu1 signal: IPU1_DI1_PIN14
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA11
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23(0x020E0530)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA24 to pad EIM_DATA24(F22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24(0x020E0164)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA24
+    //     ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_SS2
+    //     ALT2 (2) - Select instance: uart3 signal: UART3_TX_DATA
+    //     ALT3 (3) - Select instance: ecspi1 signal: ECSPI1_SS2
+    //     ALT4 (4) - Select instance: ecspi2 signal: ECSPI2_SS2
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO24
+    //     ALT6 (6) - Select instance: audmux signal: AUD5_RXFS
+    //     ALT7 (7) - Select instance: uart1 signal: UART1_DTR_B
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE7
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24(0x020E0534)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA25 to pad EIM_DATA25(G22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25(0x020E0168)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA25
+    //     ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_SS3
+    //     ALT2 (2) - Select instance: uart3 signal: UART3_RX_DATA
+    //     ALT3 (3) - Select instance: ecspi1 signal: ECSPI1_SS3
+    //     ALT4 (4) - Select instance: ecspi2 signal: ECSPI2_SS3
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO25
+    //     ALT6 (6) - Select instance: audmux signal: AUD5_RXC
+    //     ALT7 (7) - Select instance: uart1 signal: UART1_DSR_B
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE8
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25(0x020E0538)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA26 to pad EIM_DATA26(E24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26(0x020E016C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA26
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN11
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI0_DATA01
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA14
+    //     ALT4 (4) - Select instance: uart2 signal: UART2_TX_DATA
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO26
+    //     ALT6 (6) - Select instance: ipu1 signal: IPU1_SISG2
+    //     ALT7 (7) - Select instance: ipu1 signal: IPU1_DISP1_DATA22
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDOED
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26(0x020E053C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA27 to pad EIM_DATA27(E25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27(0x020E0170)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA27
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN13
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI0_DATA00
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA13
+    //     ALT4 (4) - Select instance: uart2 signal: UART2_RX_DATA
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO27
+    //     ALT6 (6) - Select instance: ipu1 signal: IPU1_SISG3
+    //     ALT7 (7) - Select instance: ipu1 signal: IPU1_DISP1_DATA23
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDOE
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27(0x020E0540)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA28 to pad EIM_DATA28(G23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28(0x020E0174)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA28
+    //     ALT1 (1) - Select instance: i2c1 signal: I2C1_SDA
+    //     ALT2 (2) - Select instance: ecspi4 signal: ECSPI4_MOSI
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA12
+    //     ALT4 (4) - Select instance: uart2 signal: UART2_CTS_B
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO28
+    //     ALT6 (6) - Select instance: ipu1 signal: IPU1_EXT_TRIG
+    //     ALT7 (7) - Select instance: ipu1 signal: IPU1_DI0_PIN13
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_CTRL3
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28(0x020E0544)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA29 to pad EIM_DATA29(J19)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29(0x020E0178)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA29
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN15
+    //     ALT2 (2) - Select instance: ecspi4 signal: ECSPI4_SS0
+    //     ALT4 (4) - Select instance: uart2 signal: UART2_RTS_B
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO29
+    //     ALT6 (6) - Select instance: ipu1 signal: IPU1_CSI1_VSYNC
+    //     ALT7 (7) - Select instance: ipu1 signal: IPU1_DI0_PIN14
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_WAKE
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29(0x020E0548)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA30 to pad EIM_DATA30(J20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30(0x020E017C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA30
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA21
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN11
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI0_DATA03
+    //     ALT4 (4) - Select instance: uart3 signal: UART3_CTS_B
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO30
+    //     ALT6 (6) - Select instance: usb signal: USB_H1_OC
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDOEZ
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30(0x020E054C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE_V(SLOW));
+
+    // Config eim.EIM_DATA31 to pad EIM_DATA31(H21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31(0x020E0180)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA31
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA20
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN12
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI0_DATA02
+    //     ALT4 (4) - Select instance: uart3 signal: UART3_RTS_B
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO31
+    //     ALT6 (6) - Select instance: usb signal: USB_H1_PWR
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCLK_P
+    //     ALT9 (9) - Select instance: eim signal: EIM_ACLK_FREERUN
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31(0x020E0550)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE_V(SLOW));
+
+    // Config eim.EIM_OE to pad EIM_OE(J24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_OE(0x020E01D8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_OE
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN07
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_MISO
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO25
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_IRQ
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_OE(0x020E05A8)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE_V(FAST));
+
+    // Config eim.EIM_RW to pad EIM_RW(K20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_RW(0x020E01DC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_RW
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN08
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_SS0
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO26
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG29
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA07
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_RW(0x020E05AC)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE_V(FAST));
+
+    // Config eim.EIM_WAIT to pad EIM_WAIT(M25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR(0x0000B060);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT(0x020E01E0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_WAIT
+    //     ALT1 (1) - Select instance: eim signal: EIM_DTACK_B
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO00
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG25
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT(0x020E05B0)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 50MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 60_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED_V(50MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE_V(60_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/enet_iomux_config.c

@@ -0,0 +1,1388 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: enet_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for enet module.
+void enet_iomux_config(void)
+{
+    // Config enet.ENET_MDC to pad KEY_COL2(W6)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR(0x00000004);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_COL2(0x020E024C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS1
+    //     ALT1 (1) - Select instance: enet signal: ENET_RX_DATA2
+    //     ALT2 (2) - Select instance: flexcan1 signal: FLEXCAN1_TX
+    //     ALT3 (3) - Select instance: kpp signal: KEY_COL2
+    //     ALT4 (4) - Select instance: enet signal: ENET_MDC
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO10
+    //     ALT6 (6) - Select instance: usb signal: USB_H1_PWR_CTL_WAKE
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_V(ALT4));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_COL2(0x020E0634)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE_V(SLOW));
+
+    // Config enet.ENET_MDIO to pad KEY_COL1(U7)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR(0x0001B0B0);
+    // HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_COL1(0x020E0248)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_MISO
+    //     ALT1 (1) - Select instance: enet signal: ENET_MDIO
+    //     ALT2 (2) - Select instance: audmux signal: AUD5_TXFS
+    //     ALT3 (3) - Select instance: kpp signal: KEY_COL1
+    //     ALT4 (4) - Select instance: uart5 signal: UART5_TX_DATA
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO08
+    //     ALT6 (6) - Select instance: usdhc1 signal: SD1_VSELECT
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_COL1(0x020E0630)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE_V(SLOW));
+    // Pad KEY_COL1 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT(0x020E0810)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_MDIO_ALT1
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_MDIO_ALT1 (0) - Select signal enet ENET_MDIO as input from pad ENET_MDIO(ALT1).
+    //     KEY_COL1_ALT1 (1) - Select signal enet ENET_MDIO as input from pad KEY_COL1(ALT1).
+    HW_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_WR(
+            BF_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT_DAISY_V(KEY_COL1_ALT1));
+
+    // Config enet.ENET_TX_CLK to pad ENET_REF_CLK(V22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR(0x0001A0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK(0x020E01F0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: enet signal: ENET_TX_CLK
+    //     ALT2 (2) - Select instance: esai signal: ESAI_RX_FS
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO23
+    //     ALT6 (6) - Select instance: spdif signal: SPDIF_SR_CLK
+    HW_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK(0x020E05C0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_PKE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK_SRE_V(SLOW));
+
+    // Config enet.RGMII_RD0 to pad RGMII_RD0(C24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_WR(0x0001B030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(0x00000000);
+    // HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0(0x020E02AC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: mipi_hsi signal: HSI_RX_READY
+    //     ALT1 (1) - Select instance: enet signal: RGMII_RD0
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO25
+    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0(0x020E0694)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
+    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //                           Note: The value of this field does not reflect the vaule of the
+    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM register.
+    //                Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM
+    //                register.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0768)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM(0x020E0788)
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT_V(DISABLED));
+    // Pad RGMII_RD0 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT(0x020E0818)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_RX_DATA0_ALT1
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_RX_DATA0_ALT1 (0) - Select signal enet ENET_RX_DATA0 as input from pad ENET_RX_DATA0(ALT1).
+    //     RGMII_RD0_ALT1 (1) - Select signal enet RGMII_RD0 as input from pad RGMII_RD0(ALT1).
+    HW_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_WR(
+            BF_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT_DAISY_V(RGMII_RD0_ALT1));
+
+    // Config enet.RGMII_RD1 to pad RGMII_RD1(B23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_WR(0x0001B030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(0x00000000);
+    // HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1(0x020E02B0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: mipi_hsi signal: HSI_TX_FLAG
+    //     ALT1 (1) - Select instance: enet signal: RGMII_RD1
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO27
+    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1(0x020E0698)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
+    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //                           Note: The value of this field does not reflect the vaule of the
+    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM register.
+    //                Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM
+    //                register.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0768)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM(0x020E0788)
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT_V(DISABLED));
+    // Pad RGMII_RD1 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT(0x020E081C)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_RX_DATA1_ALT1
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_RX_DATA1_ALT1 (0) - Select signal enet ENET_RX_DATA1 as input from pad ENET_RX_DATA1(ALT1).
+    //     RGMII_RD1_ALT1 (1) - Select signal enet RGMII_RD1 as input from pad RGMII_RD1(ALT1).
+    HW_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_WR(
+            BF_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT_DAISY_V(RGMII_RD1_ALT1));
+
+    // Config enet.RGMII_RD2 to pad RGMII_RD2(B24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_WR(0x0001B030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(0x00000000);
+    // HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2(0x020E02B4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: mipi_hsi signal: HSI_TX_DATA
+    //     ALT1 (1) - Select instance: enet signal: RGMII_RD2
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO28
+    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2(0x020E069C)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
+    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //                           Note: The value of this field does not reflect the vaule of the
+    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM register.
+    //                Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM
+    //                register.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0768)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM(0x020E0788)
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT_V(DISABLED));
+    // Pad RGMII_RD2 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT(0x020E0820)
+    //   DAISY [0] - MUX Mode Select Field Reset: KEY_COL2_ALT1
+    //               Selecting Pads Involved in Daisy Chain.
+    //     KEY_COL2_ALT1 (0) - Select signal enet ENET_RX_DATA2 as input from pad KEY_COL2(ALT1).
+    //     RGMII_RD2_ALT1 (1) - Select signal enet RGMII_RD2 as input from pad RGMII_RD2(ALT1).
+    HW_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_WR(
+            BF_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT_DAISY_V(RGMII_RD2_ALT1));
+
+    // Config enet.RGMII_RD3 to pad RGMII_RD3(D23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_WR(0x0001B030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(0x00000000);
+    // HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3(0x020E02B8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: mipi_hsi signal: HSI_TX_WAKE
+    //     ALT1 (1) - Select instance: enet signal: RGMII_RD3
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO29
+    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3(0x020E06A0)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
+    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //                           Note: The value of this field does not reflect the vaule of the
+    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM register.
+    //                Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM
+    //                register.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0768)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM(0x020E0788)
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT_V(DISABLED));
+    // Pad RGMII_RD3 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT(0x020E0824)
+    //   DAISY [0] - MUX Mode Select Field Reset: KEY_COL0_ALT1
+    //               Selecting Pads Involved in Daisy Chain.
+    //     KEY_COL0_ALT1 (0) - Select signal enet ENET_RX_DATA3 as input from pad KEY_COL0(ALT1).
+    //     RGMII_RD3_ALT1 (1) - Select signal enet RGMII_RD3 as input from pad RGMII_RD3(ALT1).
+    HW_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_WR(
+            BF_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT_DAISY_V(RGMII_RD3_ALT1));
+
+    // Config enet.RGMII_RXC to pad RGMII_RXC(B25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_WR(0x00013030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(0x00000000);
+    // HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC(0x020E02C0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usb signal: USB_H3_STROBE
+    //     ALT1 (1) - Select instance: enet signal: RGMII_RXC
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO30
+    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC(0x020E06A8)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
+    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //                           Note: The value of this field does not reflect the vaule of the
+    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM register.
+    //                Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM
+    //                register.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0768)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM(0x020E0788)
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT_V(DISABLED));
+    // Pad RGMII_RXC is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT(0x020E0814)
+    //   DAISY [0] - MUX Mode Select Field Reset: GPIO18_ALT1
+    //               Selecting Pads Involved in Daisy Chain.
+    //     GPIO18_ALT1 (0) - Select signal enet ENET_RX_CLK as input from pad GPIO18(ALT1).
+    //     RGMII_RXC_ALT1 (1) - Select signal enet RGMII_RXC as input from pad RGMII_RXC(ALT1).
+    HW_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_WR(
+            BF_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT_DAISY_V(RGMII_RXC_ALT1));
+
+    // Config enet.RGMII_RX_CTL to pad RGMII_RX_CTL(D22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_WR(0x00013030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(0x00000000);
+    // HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL(0x020E02BC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usb signal: USB_H3_DATA
+    //     ALT1 (1) - Select instance: enet signal: RGMII_RX_CTL
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO24
+    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL(0x020E06A4)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
+    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //                           Note: The value of this field does not reflect the vaule of the
+    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM register.
+    //                Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM
+    //                register.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0768)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM(0x020E0788)
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    HW_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM_ODT_V(DISABLED));
+    // Pad RGMII_RX_CTL is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT(0x020E0828)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_CRS_DV_ALT1
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_CRS_DV_ALT1 (0) - Select signal enet ENET_RX_EN as input from pad ENET_CRS_DV(ALT1).
+    //     RGMII_RX_CTL_ALT1 (1) - Select signal enet RGMII_RX_CTL as input from pad RGMII_RX_CTL(ALT1).
+    HW_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_WR(
+            BF_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT_DAISY_V(RGMII_RX_CTL_ALT1));
+
+    // Config enet.RGMII_TD0 to pad RGMII_TD0(C22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_WR(0x0001B030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0(0x020E02C4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: mipi_hsi signal: HSI_TX_READY
+    //     ALT1 (1) - Select instance: enet signal: RGMII_TD0
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO20
+    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0(0x020E06AC)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
+    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //                           Note: The value of this field does not reflect the vaule of the
+    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0768)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
+
+    // Config enet.RGMII_TD1 to pad RGMII_TD1(F20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_WR(0x0001B030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1(0x020E02C8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: mipi_hsi signal: HSI_RX_FLAG
+    //     ALT1 (1) - Select instance: enet signal: RGMII_TD1
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO21
+    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1(0x020E06B0)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
+    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //                           Note: The value of this field does not reflect the vaule of the
+    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0768)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
+
+    // Config enet.RGMII_TD2 to pad RGMII_TD2(E21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_WR(0x0001B030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2(0x020E02CC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: mipi_hsi signal: HSI_RX_DATA
+    //     ALT1 (1) - Select instance: enet signal: RGMII_TD2
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO22
+    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2(0x020E06B4)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
+    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //                           Note: The value of this field does not reflect the vaule of the
+    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0768)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
+
+    // Config enet.RGMII_TD3 to pad RGMII_TD3(A24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_WR(0x0001B030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3(0x020E02D0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: mipi_hsi signal: HSI_RX_WAKE
+    //     ALT1 (1) - Select instance: enet signal: RGMII_TD3
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO23
+    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3(0x020E06B8)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
+    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //                           Note: The value of this field does not reflect the vaule of the
+    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0768)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
+
+    // Config enet.RGMII_TXC to pad RGMII_TXC(D21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR(0x00013030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC(0x020E02D8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usb signal: USB_H2_DATA
+    //     ALT1 (1) - Select instance: enet signal: RGMII_TXC
+    //     ALT2 (2) - Select instance: spdif signal: SPDIF_EXT_CLK
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO19
+    //     ALT7 (7) - Select instance: xtalosc signal: XTALOSC_REF_CLK_24M
+    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC(0x020E06C0)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
+    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //                           Note: The value of this field does not reflect the vaule of the
+    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //                    NOTE: Read Only Field
+    //                    The value of this field is fixed and cannot be changed.
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0768)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
+
+    // Config enet.RGMII_TX_CTL to pad RGMII_TX_CTL(C23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_WR(0x00013030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(0x00080000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL(0x020E02D4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usb signal: USB_H2_STROBE
+    //     ALT1 (1) - Select instance: enet signal: RGMII_TX_CTL
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO26
+    //     ALT7 (7) - Select instance: enet signal: ENET_REF_CLK
+    HW_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL(0x020E06BC)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: RESERVED0
+    //                           NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //                           Note: The value of this field does not reflect the vaule of the
+    //                           IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //                    NOTE: Read Only Field
+    //                    The value of this field is fixed and cannot be changed.
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII(0x020E0768)
+    //   DDR_SEL_RGMII [19:18] - DDR Select Field Reset: 1P2V_IO
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     1P2V_IO (2) - 1.2V I/O interfaces including USB HSIC and MIPI_HSI. Provides calibrated drive strengths for signals ranging from 1.0V up to 1.3V.
+    //     1P5V_IO (3) - 1.5V I/O interfaces including ENET. Provides calibrated drive strengths for signals ranging from 1.3V to 2.5V.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII_DDR_SEL_RGMII_V(1P2V_IO));
+}

bsp/imx6sx/cortex-a9/board/epit_iomux_config.c

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: epit_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsepit.h"
+#include "io.h"
+#include <assert.h>
+
+void epit_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_EPIT1:
+            return epit1_iomux_config();
+
+        case HW_EPIT2:
+            return epit2_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/esai_iomux_config.c

@@ -0,0 +1,808 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: esai_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for esai module.
+void esai_iomux_config(void)
+{
+    // Config esai.ESAI_RX_CLK to pad ENET_MDIO(V23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR(0x0001B0B0);
+    // HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO(0x020E01EC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: enet signal: ENET_MDIO
+    //     ALT2 (2) - Select instance: esai signal: ESAI_RX_CLK
+    //     ALT4 (4) - Select instance: enet signal: ENET_1588_EVENT1_OUT
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO22
+    //     ALT6 (6) - Select instance: spdif signal: SPDIF_LOCK
+    HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO(0x020E05BC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO_SRE_V(SLOW));
+    // Pad ENET_MDIO is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ESAI_RX_CLK_SELECT_INPUT(0x020E083C)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_MDIO_ALT2
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_MDIO_ALT2 (0) - Select signal esai ESAI_RX_CLK as input from pad ENET_MDIO(ALT2).
+    //     GPIO01_ALT0 (1) - Select signal esai ESAI_RX_CLK as input from pad GPIO01(ALT0).
+    HW_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_WR(
+            BF_IOMUXC_ESAI_RX_CLK_SELECT_INPUT_DAISY_V(ENET_MDIO_ALT2));
+
+    // Config esai.ESAI_RX_FS to pad GPIO09(T2)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR(0x0001B0B0);
+    // HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO09(0x020E0240)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: esai signal: ESAI_RX_FS
+    //     ALT1 (1) - Select instance: wdog1 signal: WDOG1_B
+    //     ALT2 (2) - Select instance: kpp signal: KEY_COL6
+    //     ALT3 (3) - Select instance: ccm signal: CCM_REF_EN_B
+    //     ALT4 (4) - Select instance: pwm1 signal: PWM1_OUT
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO09
+    //     ALT6 (6) - Select instance: usdhc1 signal: SD1_WP
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO09_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO09_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO09_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO09(0x020E0610)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO09_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO09_SRE_V(SLOW));
+    // Pad GPIO09 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ESAI_RX_FS_SELECT_INPUT(0x020E082C)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_REF_CLK_ALT2
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_REF_CLK_ALT2 (0) - Select signal esai ESAI_RX_FS as input from pad ENET_REF_CLK(ALT2).
+    //     GPIO09_ALT0 (1) - Select signal esai ESAI_RX_FS as input from pad GPIO09(ALT0).
+    HW_IOMUXC_ESAI_RX_FS_SELECT_INPUT_WR(
+            BF_IOMUXC_ESAI_RX_FS_SELECT_INPUT_DAISY_V(GPIO09_ALT0));
+
+    // Config esai.ESAI_TX0 to pad GPIO17(R1)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR(0x0001B0B0);
+    // HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO17(0x020E0218)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: esai signal: ESAI_TX0
+    //     ALT1 (1) - Select instance: enet signal: ENET_1588_EVENT3_IN
+    //     ALT2 (2) - Select instance: ccm signal: CCM_PMIC_READY
+    //     ALT3 (3) - Select instance: sdma signal: SDMA_EXT_EVENT0
+    //     ALT4 (4) - Select instance: spdif signal: SPDIF_OUT
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO12
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO17_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO17_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO17(0x020E05E8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO17_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO17_SRE_V(SLOW));
+    // Pad GPIO17 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ESAI_SDO0_SELECT_INPUT(0x020E0844)
+    //   DAISY [0] - MUX Mode Select Field Reset: GPIO17_ALT0
+    //               Selecting Pads Involved in Daisy Chain.
+    //     GPIO17_ALT0 (0) - Select signal esai ESAI_TX0 as input from pad GPIO17(ALT0).
+    //     NAND_CS2_B_ALT2 (1) - Select signal esai ESAI_TX0 as input from pad NAND_CS2_B(ALT2).
+    HW_IOMUXC_ESAI_SDO0_SELECT_INPUT_WR(
+            BF_IOMUXC_ESAI_SDO0_SELECT_INPUT_DAISY_V(GPIO17_ALT0));
+
+    // Config esai.ESAI_TX1 to pad NAND_CS3_B(D16)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR(0x0001B0B0);
+    // HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B(0x020E0280)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_CE3_B
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG1
+    //     ALT2 (2) - Select instance: esai signal: ESAI_TX1
+    //     ALT3 (3) - Select instance: eim signal: EIM_ADDR26
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO16
+    //     ALT9 (9) - Select instance: i2c4 signal: I2C4_SDA
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B(0x020E0668)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B_SRE_V(SLOW));
+    // Pad NAND_CS3_B is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ESAI_SDO1_SELECT_INPUT(0x020E0848)
+    //   DAISY [0] - MUX Mode Select Field Reset: GPIO18_ALT0
+    //               Selecting Pads Involved in Daisy Chain.
+    //     GPIO18_ALT0 (0) - Select signal esai ESAI_TX1 as input from pad GPIO18(ALT0).
+    //     NAND_CS3_B_ALT2 (1) - Select signal esai ESAI_TX1 as input from pad NAND_CS3_B(ALT2).
+    HW_IOMUXC_ESAI_SDO1_SELECT_INPUT_WR(
+            BF_IOMUXC_ESAI_SDO1_SELECT_INPUT_DAISY_V(NAND_CS3_B_ALT2));
+
+    // Config esai.ESAI_TX2_RX3 to pad GPIO05(R4)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR(0x0001B0B0);
+    // HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO05(0x020E0230)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: esai signal: ESAI_TX2_RX3
+    //     ALT2 (2) - Select instance: kpp signal: KEY_ROW7
+    //     ALT3 (3) - Select instance: ccm signal: CCM_CLKO1
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO05
+    //     ALT6 (6) - Select instance: i2c3 signal: I2C3_SCL
+    //     ALT7 (7) - Select instance: arm signal: ARM_EVENTI
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO05_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO05_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO05_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO05(0x020E0600)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO05_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO05_SRE_V(SLOW));
+    // Pad GPIO05 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT(0x020E084C)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_TX_DATA1_ALT2
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_TX_DATA1_ALT2 (0) - Select signal esai ESAI_TX2_RX3 as input from pad ENET_TX_DATA1(ALT2).
+    //     GPIO05_ALT0 (1) - Select signal esai ESAI_TX2_RX3 as input from pad GPIO05(ALT0).
+    HW_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_WR(
+            BF_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT_DAISY_V(GPIO05_ALT0));
+
+    // Config esai.ESAI_TX3_RX2 to pad ENET_TX_EN(V21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR(0x0001B0B0);
+    // HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN(0x020E0200)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: enet signal: ENET_TX_EN
+    //     ALT2 (2) - Select instance: esai signal: ESAI_TX3_RX2
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO28
+    //     ALT9 (9) - Select instance: i2c4 signal: I2C4_SCL
+    HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN(0x020E05D0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN_SRE_V(SLOW));
+    // Pad ENET_TX_EN is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT(0x020E0850)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_TX_EN_ALT2
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_TX_EN_ALT2 (0) - Select signal esai ESAI_TX3_RX2 as input from pad ENET_TX_EN(ALT2).
+    //     GPIO16_ALT0 (1) - Select signal esai ESAI_TX3_RX2 as input from pad GPIO16(ALT0).
+    HW_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_WR(
+            BF_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT_DAISY_V(ENET_TX_EN_ALT2));
+
+    // Config esai.ESAI_TX4_RX1 to pad ENET_TX_DATA0(U20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR(0x0001B0B0);
+    // HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0(0x020E0204)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: enet signal: ENET_TX_DATA0
+    //     ALT2 (2) - Select instance: esai signal: ESAI_TX4_RX1
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO30
+    HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0(0x020E05D4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0_SRE_V(SLOW));
+    // Pad ENET_TX_DATA0 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT(0x020E0854)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_TX_DATA0_ALT2
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_TX_DATA0_ALT2 (0) - Select signal esai ESAI_TX4_RX1 as input from pad ENET_TX_DATA0(ALT2).
+    //     GPIO07_ALT0 (1) - Select signal esai ESAI_TX4_RX1 as input from pad GPIO07(ALT0).
+    HW_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_WR(
+            BF_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT_DAISY_V(ENET_TX_DATA0_ALT2));
+
+    // Config esai.ESAI_TX5_RX0 to pad ENET_MDC(V20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR(0x0001B0B0);
+    // HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_ENET_MDC(0x020E01E8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: mlb signal: MLB_DATA
+    //     ALT1 (1) - Select instance: enet signal: ENET_MDC
+    //     ALT2 (2) - Select instance: esai signal: ESAI_TX5_RX0
+    //     ALT4 (4) - Select instance: enet signal: ENET_1588_EVENT1_IN
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO31
+    HW_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_ENET_MDC(0x020E05B8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC_SRE_V(SLOW));
+    // Pad ENET_MDC is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT(0x020E0858)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_MDC_ALT2
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_MDC_ALT2 (0) - Select signal esai ESAI_TX5_RX0 as input from pad ENET_MDC(ALT2).
+    //     GPIO08_ALT0 (1) - Select signal esai ESAI_TX5_RX0 as input from pad GPIO08(ALT0).
+    HW_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_WR(
+            BF_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT_DAISY_V(ENET_MDC_ALT2));
+
+    // Config esai.ESAI_TX_CLK to pad ENET_CRS_DV(U21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR(0x0001B0B0);
+    // HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV(0x020E01E4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: enet signal: ENET_RX_EN
+    //     ALT2 (2) - Select instance: esai signal: ESAI_TX_CLK
+    //     ALT3 (3) - Select instance: spdif signal: SPDIF_EXT_CLK
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO25
+    HW_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV(0x020E05B4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV_SRE_V(SLOW));
+    // Pad ENET_CRS_DV is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ESAI_TX_CLK_SELECT_INPUT(0x020E0840)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_CRS_DV_ALT2
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_CRS_DV_ALT2 (0) - Select signal esai ESAI_TX_CLK as input from pad ENET_CRS_DV(ALT2).
+    //     GPIO06_ALT0 (1) - Select signal esai ESAI_TX_CLK as input from pad GPIO06(ALT0).
+    HW_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_WR(
+            BF_IOMUXC_ESAI_TX_CLK_SELECT_INPUT_DAISY_V(ENET_CRS_DV_ALT2));
+
+    // Config esai.ESAI_TX_FS to pad ENET_RX_DATA1(W22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR(0x0001B0B0);
+    // HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1(0x020E01FC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: mlb signal: MLB_SIG
+    //     ALT1 (1) - Select instance: enet signal: ENET_RX_DATA1
+    //     ALT2 (2) - Select instance: esai signal: ESAI_TX_FS
+    //     ALT4 (4) - Select instance: enet signal: ENET_1588_EVENT3_OUT
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO26
+    HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1(0x020E05CC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1_SRE_V(SLOW));
+    // Pad ENET_RX_DATA1 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_ESAI_TX_FS_SELECT_INPUT(0x020E0830)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_RX_DATA1_ALT2
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_RX_DATA1_ALT2 (0) - Select signal esai ESAI_TX_FS as input from pad ENET_RX_DATA1(ALT2).
+    //     GPIO02_ALT0 (1) - Select signal esai ESAI_TX_FS as input from pad GPIO02(ALT0).
+    HW_IOMUXC_ESAI_TX_FS_SELECT_INPUT_WR(
+            BF_IOMUXC_ESAI_TX_FS_SELECT_INPUT_DAISY_V(ENET_RX_DATA1_ALT2));
+}

bsp/imx6sx/cortex-a9/board/flexcan1_iomux_config.c

@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: flexcan1_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for flexcan1 module.
+void flexcan1_iomux_config(void)
+{
+    // Config flexcan1.FLEXCAN1_RX to pad KEY_ROW2(W4)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR(0x0001B0B0);
+    // HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2(0x020E0260)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS2
+    //     ALT1 (1) - Select instance: enet signal: ENET_TX_DATA2
+    //     ALT2 (2) - Select instance: flexcan1 signal: FLEXCAN1_RX
+    //     ALT3 (3) - Select instance: kpp signal: KEY_ROW2
+    //     ALT4 (4) - Select instance: usdhc2 signal: SD2_VSELECT
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO11
+    //     ALT6 (6) - Select instance: hdmi signal: HDMI_TX_CEC_LINE
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2(0x020E0648)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE_V(SLOW));
+    // Pad KEY_ROW2 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_FLEXCAN1_RX_SELECT_INPUT(0x020E07C8)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: GPIO08_ALT3
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     GPIO08_ALT3 (0) - Select signal flexcan1 FLEXCAN1_RX as input from pad GPIO08(ALT3).
+    //     KEY_ROW2_ALT2 (1) - Select signal flexcan1 FLEXCAN1_RX as input from pad KEY_ROW2(ALT2).
+    //     SD3_CLK_ALT2 (2) - Select signal flexcan1 FLEXCAN1_RX as input from pad SD3_CLK(ALT2).
+    HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR(
+            BF_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_V(KEY_ROW2_ALT2));
+
+    // Config flexcan1.FLEXCAN1_TX to pad KEY_COL2(W6)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_COL2(0x020E024C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS1
+    //     ALT1 (1) - Select instance: enet signal: ENET_RX_DATA2
+    //     ALT2 (2) - Select instance: flexcan1 signal: FLEXCAN1_TX
+    //     ALT3 (3) - Select instance: kpp signal: KEY_COL2
+    //     ALT4 (4) - Select instance: enet signal: ENET_MDC
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO10
+    //     ALT6 (6) - Select instance: usb signal: USB_H1_PWR_CTL_WAKE
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_COL2(0x020E0634)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/flexcan2_iomux_config.c

@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: flexcan2_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for flexcan2 module.
+void flexcan2_iomux_config(void)
+{
+    // Config flexcan2.FLEXCAN2_RX to pad KEY_ROW4(V5)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(0x0001B0B0);
+    // HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4(0x020E0268)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: flexcan2 signal: FLEXCAN2_RX
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG5
+    //     ALT2 (2) - Select instance: usb signal: USB_OTG_PWR
+    //     ALT3 (3) - Select instance: kpp signal: KEY_ROW4
+    //     ALT4 (4) - Select instance: uart5 signal: UART5_CTS_B
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO15
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4(0x020E0650)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE_V(SLOW));
+    // Pad KEY_ROW4 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_FLEXCAN2_RX_SELECT_INPUT(0x020E07CC)
+    //   DAISY [0] - MUX Mode Select Field Reset: KEY_ROW4_ALT0
+    //               Selecting Pads Involved in Daisy Chain.
+    //     KEY_ROW4_ALT0 (0) - Select signal flexcan2 FLEXCAN2_RX as input from pad KEY_ROW4(ALT0).
+    //     SD3_DATA1_ALT2 (1) - Select signal flexcan2 FLEXCAN2_RX as input from pad SD3_DATA1(ALT2).
+    HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(
+            BF_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_V(KEY_ROW4_ALT0));
+
+    // Config flexcan2.FLEXCAN2_TX to pad KEY_COL4(T6)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_COL4(0x020E0254)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: flexcan2 signal: FLEXCAN2_TX
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG4
+    //     ALT2 (2) - Select instance: usb signal: USB_OTG_OC
+    //     ALT3 (3) - Select instance: kpp signal: KEY_COL4
+    //     ALT4 (4) - Select instance: uart5 signal: UART5_RTS_B
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO14
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_COL4(0x020E063C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/flexcan_iomux_config.c

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: flexcan_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsflexcan.h"
+#include "io.h"
+#include <assert.h>
+
+void flexcan_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_FLEXCAN1:
+            return flexcan1_iomux_config();
+
+        case HW_FLEXCAN2:
+            return flexcan2_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/gpio1_iomux_config.c

@@ -0,0 +1,575 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: gpio1_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for gpio1 module.
+void gpio1_iomux_config(void)
+{
+    // Config gpio1.GPIO1_IO04 to pad GPIO04(R6)
+    // CAN1_NERR_B
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO04(0x020E022C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: esai signal: ESAI_TX_HF_CLK
+    //     ALT2 (2) - Select instance: kpp signal: KEY_COL7
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO04
+    //     ALT6 (6) - Select instance: usdhc2 signal: SD2_CD_B
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO04_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO04_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO04_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO04(0x020E05FC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO04_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO04_SRE_V(SLOW));
+
+    // Config gpio1.GPIO1_IO10 to pad SD2_CLK(C21)
+    // ESAI_INT
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD2_CLK(0x020E02F4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc2 signal: SD2_CLK
+    //     ALT2 (2) - Select instance: kpp signal: KEY_COL5
+    //     ALT3 (3) - Select instance: audmux signal: AUD4_RXFS
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO10
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD2_CLK(0x020E06DC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE_V(SLOW));
+
+    // Config gpio1.GPIO1_IO11 to pad SD2_CMD(F19)
+    // HOME
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD2_CMD(0x020E02F8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc2 signal: SD2_CMD
+    //     ALT2 (2) - Select instance: kpp signal: KEY_ROW5
+    //     ALT3 (3) - Select instance: audmux signal: AUD4_RXC
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO11
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD2_CMD(0x020E06E0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE_V(SLOW));
+
+    // Config gpio1.GPIO1_IO12 to pad SD2_DATA3(B22)
+    // BACK
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3(0x020E0308)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc2 signal: SD2_DATA3
+    //     ALT2 (2) - Select instance: kpp signal: KEY_COL6
+    //     ALT3 (3) - Select instance: audmux signal: AUD4_TXC
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO12
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3(0x020E06F0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE_V(SLOW));
+
+    // Config gpio1.GPIO1_IO13 to pad SD2_DATA2(A23)
+    // SDa_WP
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2(0x020E0304)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc2 signal: SD2_DATA2
+    //     ALT2 (2) - Select instance: eim signal: EIM_CS3
+    //     ALT3 (3) - Select instance: audmux signal: AUD4_TXD
+    //     ALT4 (4) - Select instance: kpp signal: KEY_ROW6
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO13
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2(0x020E06EC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE_V(SLOW));
+
+    // Config gpio1.GPIO1_IO14 to pad SD2_DATA1(E20)
+    // BOOT_COMPLETE
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1(0x020E0300)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc2 signal: SD2_DATA1
+    //     ALT2 (2) - Select instance: eim signal: EIM_CS2
+    //     ALT3 (3) - Select instance: audmux signal: AUD4_TXFS
+    //     ALT4 (4) - Select instance: kpp signal: KEY_COL7
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO14
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1(0x020E06E8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE_V(SLOW));
+
+    // Config gpio1.GPIO1_IO15 to pad SD2_DATA0(A22)
+    // I2CPORTEXP_RST_B
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0(0x020E02FC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc2 signal: SD2_DATA0
+    //     ALT3 (3) - Select instance: audmux signal: AUD4_RXD
+    //     ALT4 (4) - Select instance: kpp signal: KEY_ROW7
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO15
+    //     ALT6 (6) - Select instance: dcic2 signal: DCIC2_OUT
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0(0x020E06E4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE_V(SLOW));
+
+    // Config gpio1.GPIO1_IO27 to pad ENET_RX_DATA0(W21)
+    // VIDEO_ADC_INT_B
+    // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0(0x020E01F8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: enet signal: ENET_RX_DATA0
+    //     ALT2 (2) - Select instance: esai signal: ESAI_TX_HF_CLK
+    //     ALT3 (3) - Select instance: spdif signal: SPDIF_OUT
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO27
+    HW_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0(0x020E05C8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/gpio2_iomux_config.c

@@ -0,0 +1,506 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: gpio2_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for gpio2 module.
+void gpio2_iomux_config(void)
+{
+    // Config gpio2.GPIO2_IO11 to pad SD4_DATA3(A20)
+    // CAN2_NERR_B
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3(0x020E034C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA3
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO11
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3(0x020E0734)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE_V(SLOW));
+
+    // Config gpio2.GPIO2_IO12 to pad SD4_DATA4(E18)
+    // PROG
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4(0x020E0350)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA4
+    //     ALT2 (2) - Select instance: uart2 signal: UART2_RX_DATA
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO12
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4(0x020E0738)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE_V(SLOW));
+
+    // Config gpio2.GPIO2_IO15 to pad SD4_DATA7(D19)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7(0x020E035C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA7
+    //     ALT2 (2) - Select instance: uart2 signal: UART2_TX_DATA
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO15
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7(0x020E0744)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE_V(SLOW));
+
+    // Config gpio2.GPIO2_IO24 to pad EIM_CS1(J23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_CS1(0x020E0140)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_CS1
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN06
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_MOSI
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO24
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA08
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_CS1(0x020E0510)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_SRE_V(FAST));
+
+    // Config gpio2.GPIO2_IO27 to pad EIM_LBA(K22)
+    // GPS_INT_B
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_LBA(0x020E01D4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_LBA
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN17
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_SS1
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO27
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG26
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA04
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_LBA(0x020E05A4)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_SRE_V(FAST));
+
+    // Config gpio2.GPIO2_IO28 to pad EIM_EB0(K21)
+    // TOUCH_INT_B
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_EB0(0x020E01C4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_EB0
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA11
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA11
+    //     ALT4 (4) - Select instance: ccm signal: CCM_PMIC_READY
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO28
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG27
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_COM
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_EB0(0x020E0594)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_SRE_V(FAST));
+
+    // Config gpio2.GPIO2_IO29 to pad EIM_EB1(K23)
+    // COMPASS_INT
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_EB1(0x020E01C8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_EB1
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA10
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA10
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO29
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG28
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDSHR
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_EB1(0x020E0598)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_SRE_V(FAST));
+}

bsp/imx6sx/cortex-a9/board/gpio4_iomux_config.c

@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: gpio4_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for gpio4 module.
+void gpio4_iomux_config(void)
+{
+    // Config gpio4.GPIO4_IO05 to pad GPIO19(P5)
+    // RGMII_INT_B
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO19(0x020E0220)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: kpp signal: KEY_COL5
+    //     ALT1 (1) - Select instance: enet signal: ENET_1588_EVENT0_OUT
+    //     ALT2 (2) - Select instance: spdif signal: SPDIF_OUT
+    //     ALT3 (3) - Select instance: ccm signal: CCM_CLKO1
+    //     ALT4 (4) - Select instance: ecspi1 signal: ECSPI1_RDY
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO05
+    //     ALT6 (6) - Select instance: enet signal: ENET_TX_ER
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO19_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO19_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO19(0x020E05F0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO19_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO19_SRE_V(SLOW));
+
+    // Config gpio4.GPIO4_IO09 to pad KEY_ROW1(U6)
+    // MLB_INT_B
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1(0x020E025C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS0
+    //     ALT1 (1) - Select instance: enet signal: ENET_COL
+    //     ALT2 (2) - Select instance: audmux signal: AUD5_RXD
+    //     ALT3 (3) - Select instance: kpp signal: KEY_ROW1
+    //     ALT4 (4) - Select instance: uart5 signal: UART5_RX_DATA
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO09
+    //     ALT6 (6) - Select instance: usdhc2 signal: SD2_VSELECT
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1(0x020E0644)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/gpio5_iomux_config.c

@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: gpio5_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for gpio5 module.
+void gpio5_iomux_config(void)
+{
+    // Config gpio5.GPIO5_IO04 to pad EIM_ADDR24(F25)
+    // EIMD18_I2C3_STEER
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24(0x020E0130)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_ADDR24
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA19
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA19
+    //     ALT4 (4) - Select instance: ipu1 signal: IPU1_SISG2
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO04
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG24
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_GDRL
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24(0x020E0500)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24_SRE_V(FAST));
+
+    // Config gpio5.GPIO5_IO14 to pad DISP0_DATA20(U22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20(0x020E00E4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA20
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA20
+    //     ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_SCLK
+    //     ALT3 (3) - Select instance: audmux signal: AUD4_TXC
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO14
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20(0x020E03F8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE_V(SLOW));
+
+    // Config gpio5.GPIO5_IO15 to pad DISP0_DATA21(T20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21(0x020E00E8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA21
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA21
+    //     ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_MOSI
+    //     ALT3 (3) - Select instance: audmux signal: AUD4_TXD
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO15
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21(0x020E03FC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21_SRE_V(SLOW));
+
+    // Config gpio5.GPIO5_IO16 to pad DISP0_DATA22(V24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22(0x020E00EC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA22
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA22
+    //     ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_MISO
+    //     ALT3 (3) - Select instance: audmux signal: AUD4_TXFS
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO16
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22(0x020E0400)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22_SRE_V(SLOW));
+
+    // Config gpio5.GPIO5_IO17 to pad DISP0_DATA23(W24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23(0x020E00F0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA23
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA23
+    //     ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_SS0
+    //     ALT3 (3) - Select instance: audmux signal: AUD4_RXD
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO17
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23(0x020E0404)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23_SRE_V(SLOW));
+
+    // Config gpio5.GPIO5_IO20 to pad CSI0_DATA_EN(P3)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN(0x020E008C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA_EN
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA00
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO20
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE_CLK
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN(0x020E03A0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/gpio6_iomux_config.c

@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: gpio6_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for gpio6 module.
+void gpio6_iomux_config(void)
+{
+    // Config gpio6.GPIO6_IO15 to pad NAND_CS2_B(A17)
+    // SDa_CD_B
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B(0x020E027C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_CE2_B
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG0
+    //     ALT2 (2) - Select instance: esai signal: ESAI_TX0
+    //     ALT3 (3) - Select instance: eim signal: EIM_CRE
+    //     ALT4 (4) - Select instance: ccm signal: CCM_CLKO2
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO15
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B(0x020E0664)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B_SRE_V(SLOW));
+
+    // Config gpio6.GPIO6_IO31 to pad EIM_BCLK(N22)
+    // ACCEL_INT1_B (or ACCEL_INT2_B pop option)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_WR(0x00000005);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR(0x0000B0B1);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK(0x020E0138)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_BCLK
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN16
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO31
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE9
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK_MUX_MODE_V(ALT5));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK(0x020E0508)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK_SRE_V(FAST));
+}

bsp/imx6sx/cortex-a9/board/gpio_iomux_config.c

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: gpio_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsgpio.h"
+#include "io.h"
+#include <assert.h>
+
+void gpio_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_GPIO1:
+            return gpio1_iomux_config();
+
+        case HW_GPIO2:
+            return gpio2_iomux_config();
+
+        case HW_GPIO3:
+            return gpio3_iomux_config();
+
+        case HW_GPIO4:
+            return gpio4_iomux_config();
+
+        case HW_GPIO5:
+            return gpio5_iomux_config();
+
+        case HW_GPIO6:
+            return gpio6_iomux_config();
+
+        case HW_GPIO7:
+            return gpio7_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/gpmi_iomux_config.c

@@ -0,0 +1,1140 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: gpmi_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for gpmi module.
+void gpmi_iomux_config(void)
+{
+    // Config gpmi.NAND_ALE to pad NAND_ALE(A16)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_ALE(0x020E026C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_ALE
+    //     ALT1 (1) - Select instance: usdhc4 signal: SD4_RESET
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO08
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_ALE(0x020E0654)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE_V(SLOW));
+
+    // Config gpmi.NAND_CE0_B to pad NAND_CS0_B(F15)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B(0x020E0274)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_CE0_B
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO11
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B(0x020E065C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE_V(SLOW));
+
+    // Config gpmi.NAND_CE1_B to pad NAND_CS1_B(C16)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B(0x020E0278)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_CE1_B
+    //     ALT1 (1) - Select instance: usdhc4 signal: SD4_VSELECT
+    //     ALT2 (2) - Select instance: usdhc3 signal: SD3_VSELECT
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO14
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B(0x020E0660)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B_SRE_V(SLOW));
+
+    // Config gpmi.NAND_CLE to pad NAND_CLE(C15)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_CLE(0x020E0270)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_CLE
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO07
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_CLE(0x020E0658)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE_V(SLOW));
+
+    // Config gpmi.NAND_DATA00 to pad NAND_DATA00(A18)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00(0x020E0284)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_DATA00
+    //     ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA4
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO00
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00(0x020E066C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE_V(SLOW));
+
+    // Config gpmi.NAND_DATA01 to pad NAND_DATA01(C17)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01(0x020E0288)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_DATA01
+    //     ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA5
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO01
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01(0x020E0670)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE_V(SLOW));
+
+    // Config gpmi.NAND_DATA02 to pad NAND_DATA02(F16)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02(0x020E028C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_DATA02
+    //     ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA6
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO02
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02(0x020E0674)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE_V(SLOW));
+
+    // Config gpmi.NAND_DATA03 to pad NAND_DATA03(D17)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03(0x020E0290)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_DATA03
+    //     ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA7
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO03
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03(0x020E0678)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE_V(SLOW));
+
+    // Config gpmi.NAND_DATA04 to pad NAND_DATA04(A19)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04(0x020E0294)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_DATA04
+    //     ALT1 (1) - Select instance: usdhc2 signal: SD2_DATA4
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO04
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04(0x020E067C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE_V(SLOW));
+
+    // Config gpmi.NAND_DATA05 to pad NAND_DATA05(B18)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05(0x020E0298)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_DATA05
+    //     ALT1 (1) - Select instance: usdhc2 signal: SD2_DATA5
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO05
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05(0x020E0680)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE_V(SLOW));
+
+    // Config gpmi.NAND_DATA06 to pad NAND_DATA06(E17)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06(0x020E029C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_DATA06
+    //     ALT1 (1) - Select instance: usdhc2 signal: SD2_DATA6
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO06
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06(0x020E0684)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE_V(SLOW));
+
+    // Config gpmi.NAND_DATA07 to pad NAND_DATA07(C18)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07(0x020E02A0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_DATA07
+    //     ALT1 (1) - Select instance: usdhc2 signal: SD2_DATA7
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO07
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07(0x020E0688)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE_V(SLOW));
+
+    // Config gpmi.NAND_DQS to pad SD4_DATA0(D18)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0(0x020E0340)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA0
+    //     ALT2 (2) - Select instance: gpmi signal: NAND_DQS
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO08
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0(0x020E0728)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE_V(SLOW));
+
+    // Config gpmi.NAND_READY to pad NAND_READY(B16)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_READY(0x020E02A4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_READY
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO10
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_READY(0x020E068C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE_V(SLOW));
+
+    // Config gpmi.NAND_RE_B to pad SD4_CMD(B17)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD4_CMD(0x020E033C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc4 signal: SD4_CMD
+    //     ALT1 (1) - Select instance: gpmi signal: NAND_RE_B
+    //     ALT2 (2) - Select instance: uart3 signal: UART3_TX_DATA
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO09
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD4_CMD(0x020E0724)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE_V(SLOW));
+
+    // Config gpmi.NAND_WE_B to pad SD4_CLK(E16)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD4_CLK(0x020E0338)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc4 signal: SD4_CLK
+    //     ALT1 (1) - Select instance: gpmi signal: NAND_WE_B
+    //     ALT2 (2) - Select instance: uart3 signal: UART3_RX_DATA
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO10
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD4_CLK(0x020E0720)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE_V(SLOW));
+
+    // Config gpmi.NAND_WP_B to pad NAND_WP_B(E15)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B(0x020E02A8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_WP_B
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO09
+    //     ALT9 (9) - Select instance: i2c4 signal: I2C4_SCL
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B(0x020E0690)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/i2c2_iomux_config.c

@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: i2c2_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for i2c2 module.
+void i2c2_iomux_config(void)
+{
+    // Config i2c2.I2C2_SCL to pad EIM_EB2(E22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_WR(0x00000016);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR(0x0001B860);
+    // HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_EB2(0x020E01CC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_EB2
+    //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_SS0
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA19
+    //     ALT4 (4) - Select instance: hdmi signal: HDMI_TX_DDC_SCL
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO30
+    //     ALT6 (6) - Select instance: i2c2 signal: I2C2_SCL
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG30
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA05
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_SION_V(ENABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_MUX_MODE_V(ALT6));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_EB2(0x020E059C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_ODE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SPEED_V(50MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_DSE_V(60_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_SRE_V(SLOW));
+    // Pad EIM_EB2 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_I2C2_SCL_IN_SELECT_INPUT(0x020E0870)
+    //   DAISY [0] - MUX Mode Select Field Reset: EIM_EB2_ALT6
+    //               Selecting Pads Involved in Daisy Chain.
+    //     EIM_EB2_ALT6 (0) - Select signal i2c2 I2C2_SCL as input from pad EIM_EB2(ALT6).
+    //     KEY_COL3_ALT4 (1) - Select signal i2c2 I2C2_SCL as input from pad KEY_COL3(ALT4).
+    HW_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_WR(
+            BF_IOMUXC_I2C2_SCL_IN_SELECT_INPUT_DAISY_V(EIM_EB2_ALT6));
+
+    // Config i2c2.I2C2_SDA to pad KEY_ROW3(T7)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_WR(0x00000014);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR(0x0001B860);
+    // HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3(0x020E0264)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: asrc signal: ASRC_EXT_CLK
+    //     ALT2 (2) - Select instance: hdmi signal: HDMI_TX_DDC_SDA
+    //     ALT3 (3) - Select instance: kpp signal: KEY_ROW3
+    //     ALT4 (4) - Select instance: i2c2 signal: I2C2_SDA
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO13
+    //     ALT6 (6) - Select instance: usdhc1 signal: SD1_VSELECT
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION_V(ENABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_V(ALT4));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3(0x020E064C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_V(50MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_V(60_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE_V(SLOW));
+    // Pad KEY_ROW3 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_I2C2_SDA_IN_SELECT_INPUT(0x020E0874)
+    //   DAISY [0] - MUX Mode Select Field Reset: EIM_DATA16_ALT6
+    //               Selecting Pads Involved in Daisy Chain.
+    //     EIM_DATA16_ALT6 (0) - Select signal i2c2 I2C2_SDA as input from pad EIM_DATA16(ALT6).
+    //     KEY_ROW3_ALT4 (1) - Select signal i2c2 I2C2_SDA as input from pad KEY_ROW3(ALT4).
+    HW_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_WR(
+            BF_IOMUXC_I2C2_SDA_IN_SELECT_INPUT_DAISY_V(KEY_ROW3_ALT4));
+}

bsp/imx6sx/cortex-a9/board/i2c3_iomux_config.c

@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: i2c3_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for i2c3 module.
+void i2c3_iomux_config(void)
+{
+    // Config i2c3.I2C3_SCL to pad GPIO03(R7)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_WR(0x00000012);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR(0x0001B860);
+    // HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO03(0x020E0228)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: esai signal: ESAI_RX_HF_CLK
+    //     ALT2 (2) - Select instance: i2c3 signal: I2C3_SCL
+    //     ALT3 (3) - Select instance: xtalosc signal: XTALOSC_REF_CLK_24M
+    //     ALT4 (4) - Select instance: ccm signal: CCM_CLKO2
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO03
+    //     ALT6 (6) - Select instance: usb signal: USB_H1_OC
+    //     ALT7 (7) - Select instance: mlb signal: MLB_CLK
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO03_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO03_SION_V(ENABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO03_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO03(0x020E05F8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO03_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_ODE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SPEED_V(50MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_DSE_V(60_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO03_SRE_V(SLOW));
+    // Pad GPIO03 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_I2C3_SCL_IN_SELECT_INPUT(0x020E0878)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA17_ALT6
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     EIM_DATA17_ALT6 (0) - Select signal i2c3 I2C3_SCL as input from pad EIM_DATA17(ALT6).
+    //     GPIO03_ALT2 (1) - Select signal i2c3 I2C3_SCL as input from pad GPIO03(ALT2).
+    //     GPIO05_ALT6 (2) - Select signal i2c3 I2C3_SCL as input from pad GPIO05(ALT6).
+    HW_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_WR(
+            BF_IOMUXC_I2C3_SCL_IN_SELECT_INPUT_DAISY_V(GPIO03_ALT2));
+
+    // Config i2c3.I2C3_SDA to pad EIM_DATA18(D24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(0x00000016);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(0x0001B860);
+    // HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18(0x020E014C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA18
+    //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_MOSI
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN07
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA17
+    //     ALT4 (4) - Select instance: ipu1 signal: IPU1_DI1_D0_CS
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO18
+    //     ALT6 (6) - Select instance: i2c3 signal: I2C3_SDA
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_VCOM1
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION_V(ENABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE_V(ALT6));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18(0x020E051C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED_V(50MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE_V(60_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE_V(SLOW));
+    // Pad EIM_DATA18 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_I2C3_SDA_IN_SELECT_INPUT(0x020E087C)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA18_ALT6
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     EIM_DATA18_ALT6 (0) - Select signal i2c3 I2C3_SDA as input from pad EIM_DATA18(ALT6).
+    //     GPIO16_ALT6 (1) - Select signal i2c3 I2C3_SDA as input from pad GPIO16(ALT6).
+    //     GPIO06_ALT2 (2) - Select signal i2c3 I2C3_SDA as input from pad GPIO06(ALT2).
+    HW_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_WR(
+            BF_IOMUXC_I2C3_SDA_IN_SELECT_INPUT_DAISY_V(EIM_DATA18_ALT6));
+}

bsp/imx6sx/cortex-a9/board/i2c_iomux_config.c

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: i2c_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsi2c.h"
+#include "io.h"
+#include <assert.h>
+
+void i2c_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_I2C1:
+            return i2c1_iomux_config();
+
+        case HW_I2C2:
+            return i2c2_iomux_config();
+
+        case HW_I2C3:
+            return i2c3_iomux_config();
+
+        case HW_I2C4:
+            return i2c4_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/iomux_config.c

@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include <iomux_config.h>
+
+// Function to configure iomux for i.MX6SDL board SABRE AI rev. B.
+void iomux_config(void)
+{
+    audmux_iomux_config();
+    ccm_iomux_config();
+    ecspi1_iomux_config();
+    eim_iomux_config();
+    enet_iomux_config();
+    esai_iomux_config();
+    flexcan1_iomux_config();
+    flexcan2_iomux_config();
+    gpio1_iomux_config();
+    gpio2_iomux_config();
+    gpio4_iomux_config();
+    gpio5_iomux_config();
+    gpio6_iomux_config();
+    gpmi_iomux_config();
+    i2c2_iomux_config();
+    i2c3_iomux_config();
+    ipu1_iomux_config();
+    mlb_iomux_config();
+    mmdc_iomux_config();
+    pwm3_iomux_config();
+    pwm4_iomux_config();
+    sjc_iomux_config();
+    spdif_iomux_config();
+    uart2_iomux_config();
+    uart3_iomux_config();
+    uart4_iomux_config();
+    usdhc1_iomux_config();
+    usdhc3_iomux_config();
+    wdog1_iomux_config();
+}
+
+// Definitions for unused modules.
+void arm_iomux_config()
+{
+};
+
+void asrc_iomux_config()
+{
+};
+
+void dcic1_iomux_config()
+{
+};
+
+void dcic2_iomux_config()
+{
+};
+
+void ecspi2_iomux_config()
+{
+};
+
+void ecspi3_iomux_config()
+{
+};
+
+void ecspi4_iomux_config()
+{
+};
+
+void epdc_iomux_config()
+{
+};
+
+void epit1_iomux_config()
+{
+};
+
+void epit2_iomux_config()
+{
+};
+
+void gpio3_iomux_config()
+{
+};
+
+void gpio7_iomux_config()
+{
+};
+
+void gpt_iomux_config()
+{
+};
+
+void hdmi_iomux_config()
+{
+};
+
+void i2c1_iomux_config()
+{
+};
+
+void i2c4_iomux_config()
+{
+};
+
+void kpp_iomux_config()
+{
+};
+
+void lcd_iomux_config()
+{
+};
+
+void ldb_iomux_config()
+{
+};
+
+void mipi_csi_iomux_config()
+{
+};
+
+void mipi_dsi_iomux_config()
+{
+};
+
+void mipi_hsi_iomux_config()
+{
+};
+
+void pcie_iomux_config()
+{
+};
+
+void pmu_iomux_config()
+{
+};
+
+void pwm1_iomux_config()
+{
+};
+
+void pwm2_iomux_config()
+{
+};
+
+void sdma_iomux_config()
+{
+};
+
+void snvs_iomux_config()
+{
+};
+
+void src_iomux_config()
+{
+};
+
+void uart1_iomux_config()
+{
+};
+
+void uart5_iomux_config()
+{
+};
+
+void usb_iomux_config()
+{
+};
+
+void usdhc2_iomux_config()
+{
+};
+
+void usdhc4_iomux_config()
+{
+};
+
+void wdog2_iomux_config()
+{
+};
+
+void xtalosc_iomux_config()
+{
+};

bsp/imx6sx/cortex-a9/board/ipu1_iomux_config.c

@@ -0,0 +1,2846 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: ipu1_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for ipu1 module.
+void ipu1_iomux_config(void)
+{
+    // Config ipu1.IPU1_CSI0_DATA04 to pad CSI0_DATA04(N1)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04(0x020E0074)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA04
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA02
+    //     ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_SCLK
+    //     ALT3 (3) - Select instance: kpp signal: KEY_COL5
+    //     ALT4 (4) - Select instance: audmux signal: AUD3_TXC
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO22
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE01
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04(0x020E0388)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA05 to pad CSI0_DATA05(P2)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05(0x020E0078)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA05
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA03
+    //     ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_MOSI
+    //     ALT3 (3) - Select instance: kpp signal: KEY_ROW5
+    //     ALT4 (4) - Select instance: audmux signal: AUD3_TXD
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO23
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE02
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05(0x020E038C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA06 to pad CSI0_DATA06(N4)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06(0x020E007C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA06
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA04
+    //     ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_MISO
+    //     ALT3 (3) - Select instance: kpp signal: KEY_COL6
+    //     ALT4 (4) - Select instance: audmux signal: AUD3_TXFS
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO24
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE03
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06(0x020E0390)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA07 to pad CSI0_DATA07(N3)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07(0x020E0080)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA07
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA05
+    //     ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_SS0
+    //     ALT3 (3) - Select instance: kpp signal: KEY_ROW6
+    //     ALT4 (4) - Select instance: audmux signal: AUD3_RXD
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO25
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE04
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07(0x020E0394)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA08 to pad CSI0_DATA08(N6)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08(0x020E0084)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA08
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA06
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_SCLK
+    //     ALT3 (3) - Select instance: kpp signal: KEY_COL7
+    //     ALT4 (4) - Select instance: i2c1 signal: I2C1_SDA
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO26
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE05
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08(0x020E0398)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA09 to pad CSI0_DATA09(N5)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09(0x020E0088)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA09
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA07
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_MOSI
+    //     ALT3 (3) - Select instance: kpp signal: KEY_ROW7
+    //     ALT4 (4) - Select instance: i2c1 signal: I2C1_SCL
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO27
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE06
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09(0x020E039C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA10 to pad CSI0_DATA10(M1)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10(0x020E004C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA10
+    //     ALT1 (1) - Select instance: audmux signal: AUD3_RXC
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_MISO
+    //     ALT3 (3) - Select instance: uart1 signal: UART1_TX_DATA
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO28
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE07
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10(0x020E0360)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA11 to pad CSI0_DATA11(M3)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11(0x020E0050)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA11
+    //     ALT1 (1) - Select instance: audmux signal: AUD3_RXFS
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_SS0
+    //     ALT3 (3) - Select instance: uart1 signal: UART1_RX_DATA
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO29
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE08
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11(0x020E0364)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA12 to pad CSI0_DATA12(M2)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12(0x020E0054)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA12
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA08
+    //     ALT3 (3) - Select instance: uart4 signal: UART4_TX_DATA
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO30
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE09
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12(0x020E0368)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA13 to pad CSI0_DATA13(L1)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13(0x020E0058)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA13
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA09
+    //     ALT3 (3) - Select instance: uart4 signal: UART4_RX_DATA
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO31
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE10
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13(0x020E036C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA14 to pad CSI0_DATA14(M4)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14(0x020E005C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA14
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA10
+    //     ALT3 (3) - Select instance: uart5 signal: UART5_TX_DATA
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO00
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE11
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14(0x020E0370)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA15 to pad CSI0_DATA15(M5)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15(0x020E0060)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA15
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA11
+    //     ALT3 (3) - Select instance: uart5 signal: UART5_RX_DATA
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO01
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE12
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15(0x020E0374)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA16 to pad CSI0_DATA16(L4)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16(0x020E0064)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA16
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA12
+    //     ALT3 (3) - Select instance: uart4 signal: UART4_RTS_B
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO02
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE13
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16(0x020E0378)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA17 to pad CSI0_DATA17(L3)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17(0x020E0068)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA17
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA13
+    //     ALT3 (3) - Select instance: uart4 signal: UART4_CTS_B
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO03
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE14
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17(0x020E037C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA18 to pad CSI0_DATA18(M6)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18(0x020E006C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA18
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA14
+    //     ALT3 (3) - Select instance: uart5 signal: UART5_RTS_B
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO04
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE15
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18(0x020E0380)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA19 to pad CSI0_DATA19(L6)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19(0x020E0070)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA19
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA15
+    //     ALT3 (3) - Select instance: uart5 signal: UART5_CTS_B
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO05
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19(0x020E0384)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_HSYNC to pad CSI0_HSYNC(P4)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC(0x020E0090)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_HSYNC
+    //     ALT3 (3) - Select instance: ccm signal: CCM_CLKO1
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO19
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE_CTL
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC(0x020E03A4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_PIXCLK to pad CSI0_PIXCLK(P1)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK(0x020E0094)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_PIXCLK
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO18
+    //     ALT7 (7) - Select instance: arm signal: ARM_EVENTO
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK(0x020E03A8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_VSYNC to pad CSI0_VSYNC(N2)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC(0x020E0098)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_VSYNC
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA01
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO21
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE00
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC(0x020E03AC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DI0_DISP_CLK to pad DI0_DISP_CLK(N19)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR(0x0001B060);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK(0x020E009C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_DISP_CLK
+    //     ALT1 (1) - Select instance: lcd signal: LCD_CLK
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO16
+    //     ALT8 (8) - Select instance: lcd signal: LCD_WR_RWN
+    HW_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK(0x020E03B0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SPEED_V(50MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_DSE_V(60_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DI0_PIN02 to pad DI0_PIN02(N25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02(0x020E00A4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_PIN02
+    //     ALT1 (1) - Select instance: lcd signal: LCD_HSYNC
+    //     ALT2 (2) - Select instance: audmux signal: AUD6_TXD
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO18
+    //     ALT8 (8) - Select instance: lcd signal: LCD_RS
+    HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02(0x020E03B8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DI0_PIN03 to pad DI0_PIN03(N20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03(0x020E00A8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_PIN03
+    //     ALT1 (1) - Select instance: lcd signal: LCD_VSYNC
+    //     ALT2 (2) - Select instance: audmux signal: AUD6_TXFS
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO19
+    //     ALT8 (8) - Select instance: lcd signal: LCD_CS
+    HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03(0x020E03BC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DI0_PIN04 to pad DI0_PIN04(P25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04(0x020E00AC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_PIN04
+    //     ALT1 (1) - Select instance: lcd signal: LCD_BUSY
+    //     ALT2 (2) - Select instance: audmux signal: AUD6_RXD
+    //     ALT3 (3) - Select instance: usdhc1 signal: SD1_WP
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO20
+    //     ALT8 (8) - Select instance: lcd signal: LCD_RESET
+    HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04(0x020E03C0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DI0_PIN15 to pad DI0_PIN15(N21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15(0x020E00A0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DI0_PIN15
+    //     ALT1 (1) - Select instance: lcd signal: LCD_ENABLE
+    //     ALT2 (2) - Select instance: audmux signal: AUD6_TXC
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO17
+    //     ALT8 (8) - Select instance: lcd signal: LCD_RD_E
+    HW_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15(0x020E03B4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA00 to pad DISP0_DATA00(P24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00(0x020E00B0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA00
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA00
+    //     ALT2 (2) - Select instance: ecspi3 signal: ECSPI3_SCLK
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO21
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00(0x020E03C4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA01 to pad DISP0_DATA01(P22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01(0x020E00B4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA01
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA01
+    //     ALT2 (2) - Select instance: ecspi3 signal: ECSPI3_MOSI
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO22
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01(0x020E03C8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA02 to pad DISP0_DATA02(P23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02(0x020E00E0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA02
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA02
+    //     ALT2 (2) - Select instance: ecspi3 signal: ECSPI3_MISO
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO23
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02(0x020E03F4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA03 to pad DISP0_DATA03(P21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03(0x020E00F4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA03
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA03
+    //     ALT2 (2) - Select instance: ecspi3 signal: ECSPI3_SS0
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO24
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03(0x020E0408)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA04 to pad DISP0_DATA04(P20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04(0x020E00F8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA04
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA04
+    //     ALT2 (2) - Select instance: ecspi3 signal: ECSPI3_SS1
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO25
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04(0x020E040C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA05 to pad DISP0_DATA05(R25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05(0x020E00FC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA05
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA05
+    //     ALT2 (2) - Select instance: ecspi3 signal: ECSPI3_SS2
+    //     ALT3 (3) - Select instance: audmux signal: AUD6_RXFS
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO26
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05(0x020E0410)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA06 to pad DISP0_DATA06(R23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06(0x020E0100)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA06
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA06
+    //     ALT2 (2) - Select instance: ecspi3 signal: ECSPI3_SS3
+    //     ALT3 (3) - Select instance: audmux signal: AUD6_RXC
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO27
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06(0x020E0414)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA07 to pad DISP0_DATA07(R24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07(0x020E0104)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA07
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA07
+    //     ALT2 (2) - Select instance: ecspi3 signal: ECSPI3_RDY
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO28
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07(0x020E0418)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA08 to pad DISP0_DATA08(R22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08(0x020E0108)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA08
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA08
+    //     ALT2 (2) - Select instance: pwm1 signal: PWM1_OUT
+    //     ALT3 (3) - Select instance: wdog1 signal: WDOG1_B
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO29
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08(0x020E041C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA09 to pad DISP0_DATA09(T25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09(0x020E010C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA09
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA09
+    //     ALT2 (2) - Select instance: pwm2 signal: PWM2_OUT
+    //     ALT3 (3) - Select instance: wdog2 signal: WDOG2_B
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO30
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09(0x020E0420)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA10 to pad DISP0_DATA10(R21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10(0x020E00B8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA10
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA10
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO31
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10(0x020E03CC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA11 to pad DISP0_DATA11(T23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11(0x020E00BC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA11
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA11
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO05
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11(0x020E03D0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA12 to pad DISP0_DATA12(T24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12(0x020E00C0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA12
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA12
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO06
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12(0x020E03D4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA13 to pad DISP0_DATA13(R20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13(0x020E00C4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA13
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA13
+    //     ALT3 (3) - Select instance: audmux signal: AUD5_RXFS
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO07
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13(0x020E03D8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA14 to pad DISP0_DATA14(U25)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14(0x020E00C8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA14
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA14
+    //     ALT3 (3) - Select instance: audmux signal: AUD5_RXC
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO08
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14(0x020E03DC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA15 to pad DISP0_DATA15(T22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15(0x020E00CC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA15
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA15
+    //     ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_SS1
+    //     ALT3 (3) - Select instance: ecspi2 signal: ECSPI2_SS1
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO09
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15(0x020E03E0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA16 to pad DISP0_DATA16(T21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16(0x020E00D0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA16
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA16
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_MOSI
+    //     ALT3 (3) - Select instance: audmux signal: AUD5_TXC
+    //     ALT4 (4) - Select instance: sdma signal: SDMA_EXT_EVENT0
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO10
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16(0x020E03E4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_DISP0_DATA17 to pad DISP0_DATA17(U24)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17(0x020E00D4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA17
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA17
+    //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_MISO
+    //     ALT3 (3) - Select instance: audmux signal: AUD5_TXD
+    //     ALT4 (4) - Select instance: sdma signal: SDMA_EXT_EVENT1
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO11
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17(0x020E03E8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/ipu_iomux_config.c

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: ipu_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsipu.h"
+#include "io.h"
+#include <assert.h>
+
+void ipu_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_IPU1:
+            return ipu1_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/mlb_iomux_config.c

@@ -0,0 +1,267 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: mlb_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for mlb module.
+void mlb_iomux_config(void)
+{
+    // Config mlb.MLB_CLK to pad ENET_TX_DATA1(W20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR(0x0001B0B0);
+    // HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1(0x020E0208)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: mlb signal: MLB_CLK
+    //     ALT1 (1) - Select instance: enet signal: ENET_TX_DATA1
+    //     ALT2 (2) - Select instance: esai signal: ESAI_TX2_RX3
+    //     ALT4 (4) - Select instance: enet signal: ENET_1588_EVENT0_IN
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO29
+    //     ALT9 (9) - Select instance: i2c4 signal: I2C4_SDA
+    HW_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1(0x020E05D8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1_SRE_V(SLOW));
+    // Pad ENET_TX_DATA1 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT(0x020E08DC)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_TX_DATA1_ALT0
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_TX_DATA1_ALT0 (0) - Select signal mlb MLB_CLK as input from pad ENET_TX_DATA1(ALT0).
+    //     GPIO03_ALT7 (1) - Select signal mlb MLB_CLK as input from pad GPIO03(ALT7).
+    HW_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_WR(
+            BF_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY_V(ENET_TX_DATA1_ALT0));
+
+    // Config mlb.MLB_DATA to pad GPIO02(T1)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_WR(0x00000007);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR(0x0001B0B0);
+    // HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO02(0x020E0224)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: esai signal: ESAI_TX_FS
+    //     ALT2 (2) - Select instance: kpp signal: KEY_ROW6
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO02
+    //     ALT6 (6) - Select instance: usdhc2 signal: SD2_WP
+    //     ALT7 (7) - Select instance: mlb signal: MLB_DATA
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO02_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO02_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO02_MUX_MODE_V(ALT7));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO02(0x020E05F4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO02_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO02_SRE_V(SLOW));
+    // Pad GPIO02 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT(0x020E08E0)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_MDC_ALT0
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_MDC_ALT0 (0) - Select signal mlb MLB_DATA as input from pad ENET_MDC(ALT0).
+    //     GPIO02_ALT7 (1) - Select signal mlb MLB_DATA as input from pad GPIO02(ALT7).
+    HW_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_WR(
+            BF_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY_V(ENET_MDC_ALT0));
+
+    // Config mlb.MLB_SIG to pad GPIO06(T3)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_WR(0x00000007);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR(0x0001B0B0);
+    // HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO06(0x020E0234)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: esai signal: ESAI_TX_CLK
+    //     ALT2 (2) - Select instance: i2c3 signal: I2C3_SDA
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO06
+    //     ALT6 (6) - Select instance: usdhc2 signal: SD2_LCTL
+    //     ALT7 (7) - Select instance: mlb signal: MLB_SIG
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO06_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO06_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO06_MUX_MODE_V(ALT7));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO06(0x020E0604)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO06_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO06_SRE_V(SLOW));
+    // Pad GPIO06 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT(0x020E08E4)
+    //   DAISY [0] - MUX Mode Select Field Reset: ENET_RX_DATA1_ALT0
+    //               Selecting Pads Involved in Daisy Chain.
+    //     ENET_RX_DATA1_ALT0 (0) - Select signal mlb MLB_SIG as input from pad ENET_RX_DATA1(ALT0).
+    //     GPIO06_ALT7 (1) - Select signal mlb MLB_SIG as input from pad GPIO06(ALT7).
+    HW_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_WR(
+            BF_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY_V(ENET_RX_DATA1_ALT0));
+}

bsp/imx6sx/cortex-a9/board/mmdc_iomux_config.c

@@ -0,0 +1,8080 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: mmdc_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for mmdc module.
+void mmdc_iomux_config(void)
+{
+    // Config mmdc.DRAM_ADDR00 to pad DRAM_ADDR00(AC14)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00(0x020E0424)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR01 to pad DRAM_ADDR01(AB14)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01(0x020E0428)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR02 to pad DRAM_ADDR02(AA14)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02(0x020E0444)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR03 to pad DRAM_ADDR03(Y14)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03(0x020E0448)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR04 to pad DRAM_ADDR04(W14)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04(0x020E044C)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR05 to pad DRAM_ADDR05(AE13)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05(0x020E0450)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR06 to pad DRAM_ADDR06(AC13)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06(0x020E0454)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR07 to pad DRAM_ADDR07(Y13)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07(0x020E0458)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR08 to pad DRAM_ADDR08(AB13)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08(0x020E045C)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR09 to pad DRAM_ADDR09(AE12)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09(0x020E0460)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE_V(KEEP) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR10 to pad DRAM_ADDR10(AA15)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10(0x020E042C)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR11 to pad DRAM_ADDR11(AC12)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11(0x020E0430)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR12 to pad DRAM_ADDR12(AD12)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12(0x020E0434)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR13 to pad DRAM_ADDR13(AC17)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13(0x020E0438)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR14 to pad DRAM_ADDR14(AA12)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14(0x020E043C)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ADDR15 to pad DRAM_ADDR15(Y12)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15(0x020E0440)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_CAS to pad DRAM_CAS(AE16)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_WR(0x00008030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS(0x020E0464)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_CS0 to pad DRAM_CS0(Y16)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0(0x020E0468)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_CTLDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_CTLDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_CTLDS(0x020E076C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_CS1 to pad DRAM_CS1(AD17)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1(0x020E046C)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_CTLDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_CTLDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_CTLDS(0x020E076C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA00 to pad DRAM_DATA00(AD2)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B0DS(0x020E0764)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA01 to pad DRAM_DATA01(AE2)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B0DS(0x020E0764)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA02 to pad DRAM_DATA02(AC4)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B0DS(0x020E0764)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA03 to pad DRAM_DATA03(AA5)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B0DS(0x020E0764)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA04 to pad DRAM_DATA04(AC1)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B0DS(0x020E0764)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA05 to pad DRAM_DATA05(AD1)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B0DS(0x020E0764)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA06 to pad DRAM_DATA06(AB4)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B0DS(0x020E0764)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA07 to pad DRAM_DATA07(AE4)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B0DS(0x020E0764)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B0DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA08 to pad DRAM_DATA08(AD5)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B1DS(0x020E0770)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA09 to pad DRAM_DATA09(AE5)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B1DS(0x020E0770)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA10 to pad DRAM_DATA10(AA6)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B1DS(0x020E0770)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA11 to pad DRAM_DATA11(AE7)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B1DS(0x020E0770)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA12 to pad DRAM_DATA12(AB5)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B1DS(0x020E0770)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA13 to pad DRAM_DATA13(AC5)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B1DS(0x020E0770)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA14 to pad DRAM_DATA14(AB6)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B1DS(0x020E0770)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA15 to pad DRAM_DATA15(AC7)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B1DS(0x020E0770)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B1DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA16 to pad DRAM_DATA16(AB7)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B2DS(0x020E0778)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA17 to pad DRAM_DATA17(AA8)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B2DS(0x020E0778)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA18 to pad DRAM_DATA18(AB9)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B2DS(0x020E0778)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA19 to pad DRAM_DATA19(Y9)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B2DS(0x020E0778)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA20 to pad DRAM_DATA20(Y7)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B2DS(0x020E0778)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA21 to pad DRAM_DATA21(Y8)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B2DS(0x020E0778)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA22 to pad DRAM_DATA22(AC8)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B2DS(0x020E0778)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA23 to pad DRAM_DATA23(AA9)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B2DS(0x020E0778)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B2DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA24 to pad DRAM_DATA24(AE9)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B3DS(0x020E077C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA25 to pad DRAM_DATA25(Y10)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B3DS(0x020E077C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA26 to pad DRAM_DATA26(AE11)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B3DS(0x020E077C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA27 to pad DRAM_DATA27(AB11)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B3DS(0x020E077C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA28 to pad DRAM_DATA28(AC9)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B3DS(0x020E077C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA29 to pad DRAM_DATA29(AD9)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B3DS(0x020E077C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA30 to pad DRAM_DATA30(AD11)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B3DS(0x020E077C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA31 to pad DRAM_DATA31(AC11)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B3DS(0x020E077C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B3DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA32 to pad DRAM_DATA32(AA17)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B4DS(0x020E0780)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA33 to pad DRAM_DATA33(AA18)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B4DS(0x020E0780)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA34 to pad DRAM_DATA34(AC18)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B4DS(0x020E0780)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA35 to pad DRAM_DATA35(AE19)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B4DS(0x020E0780)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA36 to pad DRAM_DATA36(Y17)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B4DS(0x020E0780)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA37 to pad DRAM_DATA37(Y18)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B4DS(0x020E0780)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA38 to pad DRAM_DATA38(AB19)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B4DS(0x020E0780)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA39 to pad DRAM_DATA39(AC19)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B4DS(0x020E0780)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B4DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B4DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA40 to pad DRAM_DATA40(Y19)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B5DS(0x020E0784)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA41 to pad DRAM_DATA41(AB20)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B5DS(0x020E0784)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA42 to pad DRAM_DATA42(AB21)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B5DS(0x020E0784)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA43 to pad DRAM_DATA43(AD21)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B5DS(0x020E0784)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA44 to pad DRAM_DATA44(Y20)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B5DS(0x020E0784)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA45 to pad DRAM_DATA45(AA20)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B5DS(0x020E0784)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA46 to pad DRAM_DATA46(AE21)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B5DS(0x020E0784)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA47 to pad DRAM_DATA47(AC21)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B5DS(0x020E0784)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B5DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B5DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA48 to pad DRAM_DATA48(AC22)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B6DS(0x020E078C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA49 to pad DRAM_DATA49(AE22)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B6DS(0x020E078C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA50 to pad DRAM_DATA50(AE24)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B6DS(0x020E078C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA51 to pad DRAM_DATA51(AC24)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B6DS(0x020E078C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA52 to pad DRAM_DATA52(AB22)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B6DS(0x020E078C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA53 to pad DRAM_DATA53(AC23)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B6DS(0x020E078C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA54 to pad DRAM_DATA54(AD25)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B6DS(0x020E078C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA55 to pad DRAM_DATA55(AC25)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(0x00000030);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B6DS(0x020E078C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B6DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B6DS_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_DATA56 to pad DRAM_DATA56(AB25)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B7DS(0x020E0748)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA57 to pad DRAM_DATA57(AA21)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B7DS(0x020E0748)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA58 to pad DRAM_DATA58(Y25)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B7DS(0x020E0748)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA59 to pad DRAM_DATA59(Y22)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B7DS(0x020E0748)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA60 to pad DRAM_DATA60(AB23)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B7DS(0x020E0748)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA61 to pad DRAM_DATA61(AA23)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B7DS(0x020E0748)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA62 to pad DRAM_DATA62(Y23)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B7DS(0x020E0748)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DATA63 to pad DRAM_DATA63(W25)
+    // HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_B7DS(0x020E0748)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_B7DS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_B7DS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE(0x020E0760)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DQM0 to pad DRAM_DQM0(AC3)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_WR(0x00008030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0(0x020E0470)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DQM1 to pad DRAM_DQM1(AC6)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_WR(0x00008030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1(0x020E0474)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DQM2 to pad DRAM_DQM2(AB8)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_WR(0x00008030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2(0x020E0478)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DQM3 to pad DRAM_DQM3(AE10)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_WR(0x00008030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3(0x020E047C)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DQM4 to pad DRAM_DQM4(AB18)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_WR(0x00008030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4(0x020E0480)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DQM5 to pad DRAM_DQM5(AC20)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_WR(0x00008030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5(0x020E0484)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DQM6 to pad DRAM_DQM6(AD24)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_WR(0x00008030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6(0x020E0488)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_DQM7 to pad DRAM_DQM7(Y21)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_WR(0x00008030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7(0x020E048C)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ODT0 to pad DRAM_ODT0(AC16)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR(0x00003030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0(0x020E04B4)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_ODT1 to pad DRAM_ODT1(AB17)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR(0x00003030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1(0x020E04B8)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_RAS to pad DRAM_RAS(AB15)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_WR(0x00008030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS(0x020E0490)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_RESET to pad DRAM_RESET(Y6)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR(0x00083030);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET(0x020E0494)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL_V(LPDDR2) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE_V(40_OHM));
+
+    // Config mmdc.DRAM_SDBA0 to pad DRAM_SDBA0(AC15)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0(0x020E0498)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDBA1 to pad DRAM_SDBA1(Y15)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1(0x020E049C)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_ADDDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_ADDDS(0x020E074C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_ADDDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDBA2 to pad DRAM_SDBA2(AB12)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_WR(0x0000B000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2(0x020E04A0)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_CTLDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_CTLDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_CTLDS(0x020E076C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDCKE0 to pad DRAM_SDCKE0(Y11)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_WR(0x00003000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0(0x020E04A4)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_CTLDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_CTLDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_CTLDS(0x020E076C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDCKE1 to pad DRAM_SDCKE1(AA11)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_WR(0x00003000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1(0x020E04A8)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_CTLDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_CTLDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_CTLDS(0x020E076C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDCLK0_P to pad DRAM_SDCLK0_P(AD15)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_WR(0x00008030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P(0x020E04AC)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDCLK1_P to pad DRAM_SDCLK1_P(AD14)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_WR(0x00008030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P(0x020E04B0)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_ODT_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDQS0_P to pad DRAM_SDQS0_P(AE3)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_WR(0x00002030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P(0x020E04BC)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //                    NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL register.
+    //                    Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+    //                    register.
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS
+    //              register.
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL(0x020E0750)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDQS1_P to pad DRAM_SDQS1_P(AD6)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_WR(0x00002030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P(0x020E04C0)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //                    NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL register.
+    //                    Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+    //                    register.
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS
+    //              register.
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL(0x020E0750)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDQS2_P to pad DRAM_SDQS2_P(AD8)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_WR(0x00002030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P(0x020E04C4)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //                    NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL register.
+    //                    Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+    //                    register.
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS
+    //              register.
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL(0x020E0750)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDQS3_P to pad DRAM_SDQS3_P(AC10)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_WR(0x00002030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P(0x020E04C8)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //                    NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL register.
+    //                    Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+    //                    register.
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS
+    //              register.
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL(0x020E0750)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDQS4_P to pad DRAM_SDQS4_P(AD18)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_WR(0x00002030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P(0x020E04CC)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //                    NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL register.
+    //                    Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+    //                    register.
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS
+    //              register.
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_PKE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL(0x020E0750)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDQS5_P to pad DRAM_SDQS5_P(AD20)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_WR(0x00002030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P(0x020E04D0)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //                    NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL register.
+    //                    Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+    //                    register.
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS
+    //              register.
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_PKE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL(0x020E0750)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDQS6_P to pad DRAM_SDQS6_P(AD23)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_WR(0x00002030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P(0x020E04D4)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //                    NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL register.
+    //                    Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+    //                    register.
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS
+    //              register.
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_PKE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL(0x020E0750)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDQS7_P to pad DRAM_SDQS7_P(AA25)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_WR(0x00002030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P(0x020E04D8)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //                    NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL register.
+    //                    Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+    //                    register.
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRHYS
+    //              register.
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //                NOTE: Read Only Field
+    //                The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_PKE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL(0x020E0750)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_V(CMOS));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRHYS(0x020E075C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+
+    // Config mmdc.DRAM_SDWE to pad DRAM_SDWE(AB16)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_WR(0x00008000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(0x00001000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(0x00002000);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(0x00000030);
+    // HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(0x00080000);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE(0x020E04DC)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: RESERVED0
+    //                     NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE register.
+    //                     Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+    //                     register.
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    //   DDR_INPUT [17] - DDR / CMOS Input Mode Field Reset: CMOS
+    //     CMOS (0) - CMOS input mode.
+    //     DIFFERENTIAL (1) - Differential input mode.
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPK
+    //              register.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: DISABLED
+    //              NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE register.
+    //              Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+    //              register.
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODT [10:8] - On Die Termination Field Reset: DISABLED
+    //     DISABLED (0) - Disabled
+    //     120_OHM (1) - 120 Ohm ODT
+    //     60_OHM (2) - 60 Ohm ODT
+    //     40_OHM (3) - 40 Ohm ODT
+    //     30_OHM (4) - 30 Ohm ODT
+    //     RESERVED0 (5) - Reserved
+    //     20_OHM (6) - 20 Ohm ODT
+    //     RESERVED1 (7) - Reserved
+    //   DSE [5:3] - Drive Strength Field Reset: HIZ
+    //               NOTE: This field can be configured using the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_CTLDS register.
+    //               Note: The value of this field does not reflect the vaule of the IOMUXC_SW_PAD_CTL_GRP_IOMUXC_SW_PAD_CTL_GRP_CTLDS
+    //               register.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_DDR_INPUT_V(CMOS) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_ODT_V(DISABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPKE(0x020E0754)
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_V(ENABLED));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDRPK(0x020E0758)
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDRPK_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_V(PULL));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_CTLDS(0x020E076C)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    HW_IOMUXC_SW_PAD_CTL_GRP_CTLDS_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_V(40_OHM));
+    // Pad Group Control Register:
+    // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE(0x020E0774)
+    //   DDR_SEL [19:18] - DDR Select Field Reset: LPDDR2
+    //     RESERVED0 (0) - Reserved
+    //     RESERVED1 (1) - Reserved
+    //     LPDDR2 (2) - LPDDR2 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.2V)
+    //     DDR3 (3) - DDR3 mode (240 Ohm driver unit calibration, 240, 120, 80, 60, 48, 40, 32 Ohm drive strengths at 1.5V)
+    HW_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_WR(
+            BF_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_V(LPDDR2));
+}

bsp/imx6sx/cortex-a9/board/pwm3_iomux_config.c

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: pwm3_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for pwm3 module.
+void pwm3_iomux_config(void)
+{
+    // Config pwm3.PWM3_OUT to pad SD4_DATA1(B19)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1(0x020E0344)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA1
+    //     ALT2 (2) - Select instance: pwm3 signal: PWM3_OUT
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO09
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1(0x020E072C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/pwm4_iomux_config.c

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: pwm4_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for pwm4 module.
+void pwm4_iomux_config(void)
+{
+    // Config pwm4.PWM4_OUT to pad SD4_DATA2(F17)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2(0x020E0348)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA2
+    //     ALT2 (2) - Select instance: pwm4 signal: PWM4_OUT
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO10
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2(0x020E0730)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/pwm_iomux_config.c

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: pwm_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regspwm.h"
+#include "io.h"
+#include <assert.h>
+
+void pwm_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_PWM1:
+            return pwm1_iomux_config();
+
+        case HW_PWM2:
+            return pwm2_iomux_config();
+
+        case HW_PWM3:
+            return pwm3_iomux_config();
+
+        case HW_PWM4:
+            return pwm4_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/sjc_iomux_config.c

@@ -0,0 +1,367 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: sjc_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for sjc module.
+void sjc_iomux_config(void)
+{
+    // Config sjc.JTAG_MOD to pad JTAG_MOD(H6)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_WR(0x0000B060);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD(0x020E0614)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 50MHZ
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 60_OHM
+    //               NOTE: Read Only Field
+    //               The value of this field is fixed and cannot be changed.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //             NOTE: Read Only Field
+    //             The value of this field is fixed and cannot be changed.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE_V(ENABLED));
+
+    // Config sjc.JTAG_TCK to pad JTAG_TCK(H5)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_WR(0x00007060);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK(0x020E0618)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 47K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 50MHZ
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 60_OHM
+    //               NOTE: Read Only Field
+    //               The value of this field is fixed and cannot be changed.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //             NOTE: Read Only Field
+    //             The value of this field is fixed and cannot be changed.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS_V(47K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE_V(ENABLED));
+
+    // Config sjc.JTAG_TDI to pad JTAG_TDI(G5)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_WR(0x00007060);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI(0x020E061C)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 47K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 50MHZ
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 60_OHM
+    //               NOTE: Read Only Field
+    //               The value of this field is fixed and cannot be changed.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //             NOTE: Read Only Field
+    //             The value of this field is fixed and cannot be changed.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS_V(47K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE_V(ENABLED));
+
+    // Config sjc.JTAG_TDO to pad JTAG_TDO(G6)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_WR(0x000090B1);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO(0x020E0620)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: KEEP
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //               NOTE: Read Only Field
+    //               The value of this field is fixed and cannot be changed.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: FAST
+    //             Slew rate control.
+    //             NOTE: Read Only Field
+    //             The value of this field is fixed and cannot be changed.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE_V(ENABLED));
+
+    // Config sjc.JTAG_TMS to pad JTAG_TMS(C3)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_WR(0x00007060);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS(0x020E0624)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 47K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 50MHZ
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 60_OHM
+    //               NOTE: Read Only Field
+    //               The value of this field is fixed and cannot be changed.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //             NOTE: Read Only Field
+    //             The value of this field is fixed and cannot be changed.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS_V(47K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE_V(ENABLED));
+
+    // Config sjc.JTAG_TRSTB to pad JTAG_TRSTB(C2)
+    // HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_WR(0x00007060);
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB(0x020E0628)
+    //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 47K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //              NOTE: Read Only Field
+    //              The value of this field is fixed and cannot be changed.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 50MHZ
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 60_OHM
+    //               NOTE: Read Only Field
+    //               The value of this field is fixed and cannot be changed.
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //             NOTE: Read Only Field
+    //             The value of this field is fixed and cannot be changed.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PUS_V(47K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB_PKE_V(ENABLED));
+}

bsp/imx6sx/cortex-a9/board/spdif_iomux_config.c

@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: spdif_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for spdif module.
+void spdif_iomux_config(void)
+{
+    // Config spdif.SPDIF_IN to pad KEY_COL3(U5)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR(0x00000006);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR(0x00003000);
+    // HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_WR(0x00000002);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_COL3(0x020E0250)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS3
+    //     ALT1 (1) - Select instance: enet signal: ENET_CRS
+    //     ALT2 (2) - Select instance: hdmi signal: HDMI_TX_DDC_SCL
+    //     ALT3 (3) - Select instance: kpp signal: KEY_COL3
+    //     ALT4 (4) - Select instance: i2c2 signal: I2C2_SCL
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO12
+    //     ALT6 (6) - Select instance: spdif signal: SPDIF_IN
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_V(ALT6));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_COL3(0x020E0638)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_V(100K_OHM_PD) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_V(RESERVED0) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_V(HIZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE_V(SLOW));
+    // Pad KEY_COL3 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT(0x020E08F0)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA21_ALT7
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     EIM_DATA21_ALT7 (0) - Select signal spdif SPDIF_IN as input from pad EIM_DATA21(ALT7).
+    //     ENET_RX_ER_ALT3 (1) - Select signal spdif SPDIF_IN as input from pad ENET_RX_ER(ALT3).
+    //     GPIO16_ALT4 (2) - Select signal spdif SPDIF_IN as input from pad GPIO16(ALT4).
+    //     KEY_COL3_ALT6 (3) - Select signal spdif SPDIF_IN as input from pad KEY_COL3(ALT6).
+    HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_WR(
+            BF_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY_V(GPIO16_ALT4));
+}

bsp/imx6sx/cortex-a9/board/uart2_iomux_config.c

@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: uart2_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for uart2 module.
+void uart2_iomux_config(void)
+{
+    // Config uart2.UART2_CTS_B to pad SD4_DATA6(B20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR(0x0001B0B0);
+    // HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_WR(0x00000004);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6(0x020E0358)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA6
+    //     ALT2 (2) - Select instance: uart2 signal: UART2_CTS_B
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO14
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6(0x020E0740)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE_V(SLOW));
+    // Pad SD4_DATA6 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_UART2_UART_RTS_B_SELECT_INPUT(0x020E0900)
+    //   DAISY [2:0] - MUX Mode Select Field Reset: EIM_DATA28_ALT4
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     EIM_DATA28_ALT4 (0) - Select signal uart2 UART2_CTS_B as input from pad EIM_DATA28(ALT4).
+    //     EIM_DATA29_ALT4 (1) - Select signal uart2 UART2_RTS_B as input from pad EIM_DATA29(ALT4).
+    //     SD3_CLK_ALT1 (2) - Select signal uart2 UART2_RTS_B as input from pad SD3_CLK(ALT1).
+    //     SD3_CMD_ALT1 (3) - Select signal uart2 UART2_CTS_B as input from pad SD3_CMD(ALT1).
+    //     SD4_DATA5_ALT2 (4) - Select signal uart2 UART2_RTS_B as input from pad SD4_DATA5(ALT2).
+    //     SD4_DATA6_ALT2 (5) - Select signal uart2 UART2_CTS_B as input from pad SD4_DATA6(ALT2).
+    HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_WR(
+            BF_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY_V(SD4_DATA5_ALT2));
+
+    // Config uart2.UART2_RTS_B to pad SD4_DATA5(C19)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR(0x0001B0B0);
+    // HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_WR(0x00000004);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5(0x020E0354)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA5
+    //     ALT2 (2) - Select instance: uart2 signal: UART2_RTS_B
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO13
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5(0x020E073C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE_V(SLOW));
+    // Pad SD4_DATA5 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_UART2_UART_RTS_B_SELECT_INPUT(0x020E0900)
+    //   DAISY [2:0] - MUX Mode Select Field Reset: EIM_DATA28_ALT4
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     EIM_DATA28_ALT4 (0) - Select signal uart2 UART2_CTS_B as input from pad EIM_DATA28(ALT4).
+    //     EIM_DATA29_ALT4 (1) - Select signal uart2 UART2_RTS_B as input from pad EIM_DATA29(ALT4).
+    //     SD3_CLK_ALT1 (2) - Select signal uart2 UART2_RTS_B as input from pad SD3_CLK(ALT1).
+    //     SD3_CMD_ALT1 (3) - Select signal uart2 UART2_CTS_B as input from pad SD3_CMD(ALT1).
+    //     SD4_DATA5_ALT2 (4) - Select signal uart2 UART2_RTS_B as input from pad SD4_DATA5(ALT2).
+    //     SD4_DATA6_ALT2 (5) - Select signal uart2 UART2_CTS_B as input from pad SD4_DATA6(ALT2).
+    HW_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_WR(
+            BF_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT_DAISY_V(SD4_DATA5_ALT2));
+
+    // Config uart2.UART2_RX_DATA to pad GPIO08(R5)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_WR(0x00000004);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR(0x0001B0B0);
+    // HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_WR(0x00000003);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO08(0x020E023C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: esai signal: ESAI_TX5_RX0
+    //     ALT1 (1) - Select instance: xtalosc signal: XTALOSC_REF_CLK_32K
+    //     ALT2 (2) - Select instance: epit2 signal: EPIT2_OUT
+    //     ALT3 (3) - Select instance: flexcan1 signal: FLEXCAN1_RX
+    //     ALT4 (4) - Select instance: uart2 signal: UART2_RX_DATA
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO08
+    //     ALT6 (6) - Select instance: spdif signal: SPDIF_SR_CLK
+    //     ALT7 (7) - Select instance: usb signal: USB_OTG_PWR_CTL_WAKE
+    //     ALT8 (8) - Select instance: i2c4 signal: I2C4_SDA
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO08_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO08_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO08_MUX_MODE_V(ALT4));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO08(0x020E060C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO08_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO08_SRE_V(SLOW));
+    // Pad GPIO08 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT(0x020E0904)
+    //   DAISY [2:0] - MUX Mode Select Field Reset: EIM_DATA26_ALT4
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     EIM_DATA26_ALT4 (0) - Select signal uart2 UART2_TX_DATA as input from pad EIM_DATA26(ALT4).
+    //     EIM_DATA27_ALT4 (1) - Select signal uart2 UART2_RX_DATA as input from pad EIM_DATA27(ALT4).
+    //     GPIO07_ALT4 (2) - Select signal uart2 UART2_TX_DATA as input from pad GPIO07(ALT4).
+    //     GPIO08_ALT4 (3) - Select signal uart2 UART2_RX_DATA as input from pad GPIO08(ALT4).
+    //     SD3_DATA4_ALT1 (4) - Select signal uart2 UART2_RX_DATA as input from pad SD3_DATA4(ALT1).
+    //     SD3_DATA5_ALT1 (5) - Select signal uart2 UART2_TX_DATA as input from pad SD3_DATA5(ALT1).
+    //     SD4_DATA4_ALT2 (6) - Select signal uart2 UART2_RX_DATA as input from pad SD4_DATA4(ALT2).
+    //     SD4_DATA7_ALT2 (7) - Select signal uart2 UART2_TX_DATA as input from pad SD4_DATA7(ALT2).
+    HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_WR(
+            BF_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY_V(GPIO08_ALT4));
+
+    // Config uart2.UART2_TX_DATA to pad GPIO07(R3)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_WR(0x00000004);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR(0x0001B0B0);
+    // HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_WR(0x00000003);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO07(0x020E0238)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: esai signal: ESAI_TX4_RX1
+    //     ALT2 (2) - Select instance: epit1 signal: EPIT1_OUT
+    //     ALT3 (3) - Select instance: flexcan1 signal: FLEXCAN1_TX
+    //     ALT4 (4) - Select instance: uart2 signal: UART2_TX_DATA
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO07
+    //     ALT6 (6) - Select instance: spdif signal: SPDIF_LOCK
+    //     ALT7 (7) - Select instance: usb signal: USB_OTG_HOST_MODE
+    //     ALT8 (8) - Select instance: i2c4 signal: I2C4_SCL
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO07_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO07_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO07_MUX_MODE_V(ALT4));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO07(0x020E0608)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO07_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO07_SRE_V(SLOW));
+    // Pad GPIO07 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT(0x020E0904)
+    //   DAISY [2:0] - MUX Mode Select Field Reset: EIM_DATA26_ALT4
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     EIM_DATA26_ALT4 (0) - Select signal uart2 UART2_TX_DATA as input from pad EIM_DATA26(ALT4).
+    //     EIM_DATA27_ALT4 (1) - Select signal uart2 UART2_RX_DATA as input from pad EIM_DATA27(ALT4).
+    //     GPIO07_ALT4 (2) - Select signal uart2 UART2_TX_DATA as input from pad GPIO07(ALT4).
+    //     GPIO08_ALT4 (3) - Select signal uart2 UART2_RX_DATA as input from pad GPIO08(ALT4).
+    //     SD3_DATA4_ALT1 (4) - Select signal uart2 UART2_RX_DATA as input from pad SD3_DATA4(ALT1).
+    //     SD3_DATA5_ALT1 (5) - Select signal uart2 UART2_TX_DATA as input from pad SD3_DATA5(ALT1).
+    //     SD4_DATA4_ALT2 (6) - Select signal uart2 UART2_RX_DATA as input from pad SD4_DATA4(ALT2).
+    //     SD4_DATA7_ALT2 (7) - Select signal uart2 UART2_TX_DATA as input from pad SD4_DATA7(ALT2).
+    HW_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_WR(
+            BF_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT_DAISY_V(GPIO08_ALT4));
+}

bsp/imx6sx/cortex-a9/board/uart3_iomux_config.c

@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: uart3_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for uart3 module.
+void uart3_iomux_config(void)
+{
+    // Config uart3.UART3_CTS_B to pad EIM_DATA30(J20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_WR(0x00000004);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR(0x0001B0B0);
+    // HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_WR(0x00000003);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30(0x020E017C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_DATA30
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA21
+    //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN11
+    //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI0_DATA03
+    //     ALT4 (4) - Select instance: uart3 signal: UART3_CTS_B
+    //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO30
+    //     ALT6 (6) - Select instance: usb signal: USB_H1_OC
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDOEZ
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE_V(ALT4));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30(0x020E054C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE_V(SLOW));
+    // Pad EIM_DATA30 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_UART3_UART_RTS_B_SELECT_INPUT(0x020E0908)
+    //   DAISY [2:0] - MUX Mode Select Field Reset: EIM_DATA23_ALT2
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     EIM_DATA23_ALT2 (0) - Select signal uart3 UART3_CTS_B as input from pad EIM_DATA23(ALT2).
+    //     EIM_DATA30_ALT4 (1) - Select signal uart3 UART3_CTS_B as input from pad EIM_DATA30(ALT4).
+    //     EIM_DATA31_ALT4 (2) - Select signal uart3 UART3_RTS_B as input from pad EIM_DATA31(ALT4).
+    //     EIM_EB3_ALT2 (3) - Select signal uart3 UART3_RTS_B as input from pad EIM_EB3(ALT2).
+    //     SD3_DATA3_ALT1 (4) - Select signal uart3 UART3_CTS_B as input from pad SD3_DATA3(ALT1).
+    //     SD3_RESET_ALT1 (5) - Select signal uart3 UART3_RTS_B as input from pad SD3_RESET(ALT1).
+    HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_WR(
+            BF_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY_V(EIM_EB3_ALT2));
+
+    // Config uart3.UART3_RTS_B to pad EIM_EB3(F23)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR(0x0001B0B0);
+    // HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_WR(0x00000003);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_EIM_EB3(0x020E01D0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: eim signal: EIM_EB3
+    //     ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_RDY
+    //     ALT2 (2) - Select instance: uart3 signal: UART3_RTS_B
+    //     ALT3 (3) - Select instance: uart1 signal: UART1_RI_B
+    //     ALT4 (4) - Select instance: ipu1 signal: IPU1_CSI1_HSYNC
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO31
+    //     ALT6 (6) - Select instance: ipu1 signal: IPU1_DI1_PIN03
+    //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG31
+    //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE0
+    //     ALT9 (9) - Select instance: eim signal: EIM_ACLK_FREERUN
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_EIM_EB3(0x020E05A0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE_V(SLOW));
+    // Pad EIM_EB3 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_UART3_UART_RTS_B_SELECT_INPUT(0x020E0908)
+    //   DAISY [2:0] - MUX Mode Select Field Reset: EIM_DATA23_ALT2
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     EIM_DATA23_ALT2 (0) - Select signal uart3 UART3_CTS_B as input from pad EIM_DATA23(ALT2).
+    //     EIM_DATA30_ALT4 (1) - Select signal uart3 UART3_CTS_B as input from pad EIM_DATA30(ALT4).
+    //     EIM_DATA31_ALT4 (2) - Select signal uart3 UART3_RTS_B as input from pad EIM_DATA31(ALT4).
+    //     EIM_EB3_ALT2 (3) - Select signal uart3 UART3_RTS_B as input from pad EIM_EB3(ALT2).
+    //     SD3_DATA3_ALT1 (4) - Select signal uart3 UART3_CTS_B as input from pad SD3_DATA3(ALT1).
+    //     SD3_RESET_ALT1 (5) - Select signal uart3 UART3_RTS_B as input from pad SD3_RESET(ALT1).
+    HW_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_WR(
+            BF_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT_DAISY_V(EIM_EB3_ALT2));
+
+    // Config uart3.UART3_RX_DATA to pad SD4_CLK(E16)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR(0x0001B0B0);
+    // HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_WR(0x00000002);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD4_CLK(0x020E0338)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc4 signal: SD4_CLK
+    //     ALT1 (1) - Select instance: gpmi signal: NAND_WE_B
+    //     ALT2 (2) - Select instance: uart3 signal: UART3_RX_DATA
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO10
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD4_CLK(0x020E0720)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE_V(SLOW));
+    // Pad SD4_CLK is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT(0x020E090C)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA24_ALT2
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     EIM_DATA24_ALT2 (0) - Select signal uart3 UART3_TX_DATA as input from pad EIM_DATA24(ALT2).
+    //     EIM_DATA25_ALT2 (1) - Select signal uart3 UART3_RX_DATA as input from pad EIM_DATA25(ALT2).
+    //     SD4_CLK_ALT2 (2) - Select signal uart3 UART3_RX_DATA as input from pad SD4_CLK(ALT2).
+    //     SD4_CMD_ALT2 (3) - Select signal uart3 UART3_TX_DATA as input from pad SD4_CMD(ALT2).
+    HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_WR(
+            BF_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY_V(SD4_CLK_ALT2));
+
+    // Config uart3.UART3_TX_DATA to pad SD4_CMD(B17)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR(0x0001B0B0);
+    // HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_WR(0x00000002);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD4_CMD(0x020E033C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc4 signal: SD4_CMD
+    //     ALT1 (1) - Select instance: gpmi signal: NAND_RE_B
+    //     ALT2 (2) - Select instance: uart3 signal: UART3_TX_DATA
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO09
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD4_CMD(0x020E0724)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE_V(SLOW));
+    // Pad SD4_CMD is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT(0x020E090C)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA24_ALT2
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     EIM_DATA24_ALT2 (0) - Select signal uart3 UART3_TX_DATA as input from pad EIM_DATA24(ALT2).
+    //     EIM_DATA25_ALT2 (1) - Select signal uart3 UART3_RX_DATA as input from pad EIM_DATA25(ALT2).
+    //     SD4_CLK_ALT2 (2) - Select signal uart3 UART3_RX_DATA as input from pad SD4_CLK(ALT2).
+    //     SD4_CMD_ALT2 (3) - Select signal uart3 UART3_TX_DATA as input from pad SD4_CMD(ALT2).
+    HW_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_WR(
+            BF_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT_DAISY_V(SD4_CLK_ALT2));
+}

bsp/imx6sx/cortex-a9/board/uart4_iomux_config.c

@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: uart4_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for uart4 module.
+void uart4_iomux_config(void)
+{
+    // Config uart4.UART4_RX_DATA to pad KEY_ROW0(V6)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_WR(0x00000004);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR(0x0001B0B0);
+    // HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(0x00000003);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0(0x020E0258)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_MOSI
+    //     ALT1 (1) - Select instance: enet signal: ENET_TX_DATA3
+    //     ALT2 (2) - Select instance: audmux signal: AUD5_TXD
+    //     ALT3 (3) - Select instance: kpp signal: KEY_ROW0
+    //     ALT4 (4) - Select instance: uart4 signal: UART4_RX_DATA
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO07
+    //     ALT6 (6) - Select instance: dcic2 signal: DCIC2_OUT
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE_V(ALT4));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0(0x020E0640)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE_V(SLOW));
+    // Pad KEY_ROW0 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT(0x020E0914)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: CSI0_DATA12_ALT3
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     CSI0_DATA12_ALT3 (0) - Select signal uart4 UART4_TX_DATA as input from pad CSI0_DATA12(ALT3).
+    //     CSI0_DATA13_ALT3 (1) - Select signal uart4 UART4_RX_DATA as input from pad CSI0_DATA13(ALT3).
+    //     KEY_COL0_ALT4 (2) - Select signal uart4 UART4_TX_DATA as input from pad KEY_COL0(ALT4).
+    //     KEY_ROW0_ALT4 (3) - Select signal uart4 UART4_RX_DATA as input from pad KEY_ROW0(ALT4).
+    HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(
+            BF_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY_V(KEY_ROW0_ALT4));
+
+    // Config uart4.UART4_TX_DATA to pad KEY_COL0(W5)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_WR(0x00000004);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR(0x0001B0B0);
+    // HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(0x00000003);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_COL0(0x020E0244)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SCLK
+    //     ALT1 (1) - Select instance: enet signal: ENET_RX_DATA3
+    //     ALT2 (2) - Select instance: audmux signal: AUD5_TXC
+    //     ALT3 (3) - Select instance: kpp signal: KEY_COL0
+    //     ALT4 (4) - Select instance: uart4 signal: UART4_TX_DATA
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO06
+    //     ALT6 (6) - Select instance: dcic1 signal: DCIC1_OUT
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_V(ALT4));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_COL0(0x020E062C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE_V(SLOW));
+    // Pad KEY_COL0 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT(0x020E0914)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: CSI0_DATA12_ALT3
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     CSI0_DATA12_ALT3 (0) - Select signal uart4 UART4_TX_DATA as input from pad CSI0_DATA12(ALT3).
+    //     CSI0_DATA13_ALT3 (1) - Select signal uart4 UART4_RX_DATA as input from pad CSI0_DATA13(ALT3).
+    //     KEY_COL0_ALT4 (2) - Select signal uart4 UART4_TX_DATA as input from pad KEY_COL0(ALT4).
+    //     KEY_ROW0_ALT4 (3) - Select signal uart4 UART4_RX_DATA as input from pad KEY_ROW0(ALT4).
+    HW_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_WR(
+            BF_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT_DAISY_V(KEY_ROW0_ALT4));
+}

bsp/imx6sx/cortex-a9/board/uart_iomux_config.c

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: uart_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsuart.h"
+#include "io.h"
+#include <assert.h>
+
+void uart_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_UART1:
+            return uart1_iomux_config();
+
+        case HW_UART2:
+            return uart2_iomux_config();
+
+        case HW_UART3:
+            return uart3_iomux_config();
+
+        case HW_UART4:
+            return uart4_iomux_config();
+
+        case HW_UART5:
+            return uart5_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/usdhc1_iomux_config.c

@@ -0,0 +1,772 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: usdhc1_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for usdhc1 module.
+void usdhc1_iomux_config(void)
+{
+    // Config usdhc1.SD1_CD_B to pad GPIO01(T4)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_WR(0x00000006);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO01(0x020E0210)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: esai signal: ESAI_RX_CLK
+    //     ALT1 (1) - Select instance: wdog2 signal: WDOG2_B
+    //     ALT2 (2) - Select instance: kpp signal: KEY_ROW5
+    //     ALT3 (3) - Select instance: usb signal: USB_OTG_ID
+    //     ALT4 (4) - Select instance: pwm2 signal: PWM2_OUT
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO01
+    //     ALT6 (6) - Select instance: usdhc1 signal: SD1_CD_B
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO01_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO01_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO01_MUX_MODE_V(ALT6));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO01(0x020E05E0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO01_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO01_SRE_V(SLOW));
+
+    // Config usdhc1.SD1_CLK to pad SD1_CLK(D20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR(0x0001B0B0);
+    // HW_IOMUXC_USDHC1_CARD_CLK_IN_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD1_CLK(0x020E02DC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc1 signal: SD1_CLK
+    //     ALT3 (3) - Select instance: gpt signal: GPT_CLKIN
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO20
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD1_CLK(0x020E06C4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE_V(SLOW));
+    // Pad SD1_CLK is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_USDHC1_CARD_CLK_IN_SELECT_INPUT(0x020E0928)
+    //   DAISY [0] - MUX Mode Select Field Reset: RESERVED0
+    //               Selecting Pads Involved in Daisy Chain.
+    //     RESERVED0 (0) - This field value is reserved.
+    //     SD1_CLK_ALT0 (1) - Select signal usdhc1 SD1_CLK as input from pad SD1_CLK(ALT0).
+    HW_IOMUXC_USDHC1_CARD_CLK_IN_SELECT_INPUT_WR(
+            BF_IOMUXC_USDHC1_CARD_CLK_IN_SELECT_INPUT_DAISY_V(SD1_CLK_ALT0));
+
+    // Config usdhc1.SD1_CMD to pad SD1_CMD(B21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD1_CMD(0x020E02E0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc1 signal: SD1_CMD
+    //     ALT2 (2) - Select instance: pwm4 signal: PWM4_OUT
+    //     ALT3 (3) - Select instance: gpt signal: GPT_COMPARE1
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO18
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD1_CMD(0x020E06C8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE_V(SLOW));
+
+    // Config usdhc1.SD1_DATA0 to pad SD1_DATA0(A21)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0(0x020E02E4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc1 signal: SD1_DATA0
+    //     ALT3 (3) - Select instance: gpt signal: GPT_CAPTURE1
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO16
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0(0x020E06CC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_V(SLOW));
+
+    // Config usdhc1.SD1_DATA1 to pad SD1_DATA1(C20)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1(0x020E02E8)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc1 signal: SD1_DATA1
+    //     ALT2 (2) - Select instance: pwm3 signal: PWM3_OUT
+    //     ALT3 (3) - Select instance: gpt signal: GPT_CAPTURE2
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO17
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1(0x020E06D0)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_V(SLOW));
+
+    // Config usdhc1.SD1_DATA2 to pad SD1_DATA2(E19)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2(0x020E02EC)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc1 signal: SD1_DATA2
+    //     ALT2 (2) - Select instance: gpt signal: GPT_COMPARE2
+    //     ALT3 (3) - Select instance: pwm2 signal: PWM2_OUT
+    //     ALT4 (4) - Select instance: wdog1 signal: WDOG1_B
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO19
+    //     ALT6 (6) - Select instance: wdog1 signal: WDOG1_RESET_B_DEB
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2(0x020E06D4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE_V(SLOW));
+
+    // Config usdhc1.SD1_DATA3 to pad SD1_DATA3(F18)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3(0x020E02F0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc1 signal: SD1_DATA3
+    //     ALT2 (2) - Select instance: gpt signal: GPT_COMPARE3
+    //     ALT3 (3) - Select instance: pwm1 signal: PWM1_OUT
+    //     ALT4 (4) - Select instance: wdog2 signal: WDOG2_B
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO21
+    //     ALT6 (6) - Select instance: wdog2 signal: WDOG2_RESET_B_DEB
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3(0x020E06D8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE_V(SLOW));
+
+    // Config usdhc1.SD1_DATA4 to pad NAND_DATA00(A18)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00(0x020E0284)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_DATA00
+    //     ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA4
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO00
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00(0x020E066C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE_V(SLOW));
+
+    // Config usdhc1.SD1_DATA5 to pad NAND_DATA01(C17)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01(0x020E0288)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_DATA01
+    //     ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA5
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO01
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01(0x020E0670)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE_V(SLOW));
+
+    // Config usdhc1.SD1_DATA6 to pad NAND_DATA02(F16)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02(0x020E028C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_DATA02
+    //     ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA6
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO02
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02(0x020E0674)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE_V(SLOW));
+
+    // Config usdhc1.SD1_DATA7 to pad NAND_DATA03(D17)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR(0x00000001);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03(0x020E0290)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: gpmi signal: NAND_DATA03
+    //     ALT1 (1) - Select instance: usdhc1 signal: SD1_DATA7
+    //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO03
+    HW_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_V(ALT1));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03(0x020E0678)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/usdhc3_iomux_config.c

@@ -0,0 +1,832 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: usdhc3_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for usdhc3 module.
+void usdhc3_iomux_config(void)
+{
+    // Config usdhc3.SD3_CLK to pad SD3_CLK(D14)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR(0x0001B0B0);
+    // HW_IOMUXC_USDHC3_CARD_CLK_IN_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD3_CLK(0x020E030C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc3 signal: SD3_CLK
+    //     ALT1 (1) - Select instance: uart2 signal: UART2_RTS_B
+    //     ALT2 (2) - Select instance: flexcan1 signal: FLEXCAN1_RX
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO03
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD3_CLK(0x020E06F4)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE_V(SLOW));
+    // Pad SD3_CLK is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_USDHC3_CARD_CLK_IN_SELECT_INPUT(0x020E0934)
+    //   DAISY [0] - MUX Mode Select Field Reset: RESERVED0
+    //               Selecting Pads Involved in Daisy Chain.
+    //     RESERVED0 (0) - This field value is reserved.
+    //     SD3_CLK_ALT0 (1) - Select signal usdhc3 SD3_CLK as input from pad SD3_CLK(ALT0).
+    HW_IOMUXC_USDHC3_CARD_CLK_IN_SELECT_INPUT_WR(
+            BF_IOMUXC_USDHC3_CARD_CLK_IN_SELECT_INPUT_DAISY_V(SD3_CLK_ALT0));
+
+    // Config usdhc3.SD3_CMD to pad SD3_CMD(B13)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD3_CMD(0x020E0310)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc3 signal: SD3_CMD
+    //     ALT1 (1) - Select instance: uart2 signal: UART2_CTS_B
+    //     ALT2 (2) - Select instance: flexcan1 signal: FLEXCAN1_TX
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO02
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD3_CMD(0x020E06F8)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE_V(SLOW));
+
+    // Config usdhc3.SD3_DATA0 to pad SD3_DATA0(E14)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0(0x020E0314)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc3 signal: SD3_DATA0
+    //     ALT1 (1) - Select instance: uart1 signal: UART1_CTS_B
+    //     ALT2 (2) - Select instance: flexcan2 signal: FLEXCAN2_TX
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO04
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0(0x020E06FC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE_V(SLOW));
+
+    // Config usdhc3.SD3_DATA1 to pad SD3_DATA1(F14)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1(0x020E0318)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc3 signal: SD3_DATA1
+    //     ALT1 (1) - Select instance: uart1 signal: UART1_RTS_B
+    //     ALT2 (2) - Select instance: flexcan2 signal: FLEXCAN2_RX
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO05
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1(0x020E0700)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE_V(SLOW));
+
+    // Config usdhc3.SD3_DATA2 to pad SD3_DATA2(A15)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2(0x020E031C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc3 signal: SD3_DATA2
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO06
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2(0x020E0704)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE_V(SLOW));
+
+    // Config usdhc3.SD3_DATA3 to pad SD3_DATA3(B15)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3(0x020E0320)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc3 signal: SD3_DATA3
+    //     ALT1 (1) - Select instance: uart3 signal: UART3_CTS_B
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO07
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3(0x020E0708)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE_V(SLOW));
+
+    // Config usdhc3.SD3_DATA4 to pad SD3_DATA4(D13)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4(0x020E0324)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc3 signal: SD3_DATA4
+    //     ALT1 (1) - Select instance: uart2 signal: UART2_RX_DATA
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO01
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4(0x020E070C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE_V(SLOW));
+
+    // Config usdhc3.SD3_DATA5 to pad SD3_DATA5(C13)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5(0x020E0328)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc3 signal: SD3_DATA5
+    //     ALT1 (1) - Select instance: uart2 signal: UART2_TX_DATA
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO00
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5(0x020E0710)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE_V(SLOW));
+
+    // Config usdhc3.SD3_DATA6 to pad SD3_DATA6(E13)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6(0x020E032C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc3 signal: SD3_DATA6
+    //     ALT1 (1) - Select instance: uart1 signal: UART1_RX_DATA
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO18
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6(0x020E0714)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE_V(SLOW));
+
+    // Config usdhc3.SD3_DATA7 to pad SD3_DATA7(F13)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7(0x020E0330)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc3 signal: SD3_DATA7
+    //     ALT1 (1) - Select instance: uart1 signal: UART1_TX_DATA
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO17
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7(0x020E0718)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE_V(SLOW));
+
+    // Config usdhc3.SD3_RESET to pad SD3_RESET(D15)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_SD3_RESET(0x020E0334)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: usdhc3 signal: SD3_RESET
+    //     ALT1 (1) - Select instance: uart3 signal: UART3_RTS_B
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO08
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_SD3_RESET(0x020E071C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_SRE_V(SLOW));
+
+    // Config usdhc3.SD3_VSELECT to pad GPIO18(P6)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO18(0x020E021C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: esai signal: ESAI_TX1
+    //     ALT1 (1) - Select instance: enet signal: ENET_RX_CLK
+    //     ALT2 (2) - Select instance: usdhc3 signal: SD3_VSELECT
+    //     ALT3 (3) - Select instance: sdma signal: SDMA_EXT_EVENT1
+    //     ALT4 (4) - Select instance: asrc signal: ASRC_EXT_CLK
+    //     ALT5 (5) - Select instance: gpio7 signal: GPIO7_IO13
+    //     ALT6 (6) - Select instance: snvs signal: SNVS_VIO_5_CTL
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO18_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO18_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO18_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO18(0x020E05EC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO18_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO18_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/usdhc_iomux_config.c

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: usdhc_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsusdhc.h"
+#include "io.h"
+#include <assert.h>
+
+void usdhc_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_USDHC1:
+            return usdhc1_iomux_config();
+
+        case HW_USDHC2:
+            return usdhc2_iomux_config();
+
+        case HW_USDHC3:
+            return usdhc3_iomux_config();
+
+        case HW_USDHC4:
+            return usdhc4_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/wdog1_iomux_config.c

@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: wdog1_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for wdog1 module.
+void wdog1_iomux_config(void)
+{
+    // Config wdog1.WDOG1_B to pad DISP0_DATA08(R22)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_WR(0x00000003);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08(0x020E0108)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_DISP0_DATA08
+    //     ALT1 (1) - Select instance: lcd signal: LCD_DATA08
+    //     ALT2 (2) - Select instance: pwm1 signal: PWM1_OUT
+    //     ALT3 (3) - Select instance: wdog1 signal: WDOG1_B
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO29
+    HW_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08_MUX_MODE_V(ALT3));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08(0x020E041C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/wdog_iomux_config.c

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: wdog_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regswdog.h"
+#include "io.h"
+#include <assert.h>
+
+void wdog_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_WDOG1:
+            return wdog1_iomux_config();
+
+        case HW_WDOG2:
+            return wdog2_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/cpu/SConscript

@@ -0,0 +1,17 @@
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'iar':
+        src += Glob('*_iar.S')
+elif rtconfig.PLATFORM == 'gcc':
+        src += Glob('*_gcc.S')
+elif rtconfig.PLATFORM == 'armcc':
+        src += Glob('*_rvds.S')
+
+group = DefineGroup('AM335x', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/imx6sx/cortex-a9/cpu/armv7.h

@@ -0,0 +1,64 @@
+#ifndef __ARMV7_H__
+#define __ARMV7_H__
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long r10;
+	unsigned long fp;
+	unsigned long ip;
+	unsigned long sp;
+	unsigned long lr;
+	unsigned long pc;
+	unsigned long cpsr;
+};
+
+struct rt_hw_stack
+{
+	unsigned long cpsr;
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long r10;
+	unsigned long fp;
+	unsigned long ip;
+	unsigned long lr;
+	unsigned long pc;
+};
+
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define MONITORMODE 0x16
+#define ABORTMODE   0x17
+#define HYPMODE     0x1b
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
+
+#define T_Bit       (1<<5)
+#define F_Bit       (1<<6)
+#define I_Bit       (1<<7)
+#define A_Bit       (1<<8)
+#define E_Bit       (1<<9)
+#define J_Bit       (1<<24)
+
+#endif

bsp/imx6sx/cortex-a9/cpu/context_gcc.S

@@ -0,0 +1,105 @@
+/*
+ * File      : context.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .text, "ax"
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    mrs r0, cpsr
+    cpsid i
+    bx  lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    msr cpsr, r0
+    bx  lr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    ldr sp, [r0]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task spsr
+    msr spsr_cxsf, r4
+
+    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
+
+.section .bss.share.isr
+_guest_switch_lvl:
+    .word 0
+
+.globl vmm_virq_update
+
+.section .text.isr, "ax"
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
+
+    mrs r4, cpsr
+    tst lr, #0x01
+    orrne r4, r4, #0x20     @ it's thumb code
+
+    stmfd sp!, {r4}         @ push cpsr
+
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    ldr sp, [r1]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
+    msr spsr_cxsf, r4
+    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    ldr r2, =rt_thread_switch_interrupt_flag
+    ldr r3, [r2]
+    cmp r3, #1
+    beq _reswitch
+    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
+    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
+    str r0, [ip]
+    str r3, [r2]
+_reswitch:
+    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
+    str r1, [r2]
+    bx  lr

bsp/imx6sx/cortex-a9/cpu/cortexA9_gcc.S

@@ -0,0 +1,327 @@
+/*
+ * Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file cortexA9.s
+ * @brief This file contains cortexA9 functions
+ *
+ */
+ 
+    .code 32
+    .section ".text","ax"
+
+/*
+ * bool arm_set_interrupt_state(bool enable)
+ */
+    .global arm_set_interrupt_state
+    .func arm_set_interrupt_state
+arm_set_interrupt_state:
+    mrs             r2,CPSR            @ read CPSR (Current Program Status Register)
+    teq     r0,#0
+    bicne   r1,r2,#0xc0        @ disable IRQ and FIQ
+    orreq   r1,r2,#0xc0        @ enable IRQ and FIQ
+    msr     CPSR_c,r1
+    tst     r2,#0x80
+    movne   r0,#0
+    moveq   r0,#1
+    bx      lr
+    .endfunc
+
+  .global cpu_get_current
+  @ int cpu_get_current(void)@
+  @ get current CPU ID
+  .func cpu_get_current
+cpu_get_current: 
+    mrc   p15, 0, r0, c0, c0, 5
+    and   r0, r0, #3
+	BX	  lr
+  .endfunc    @cpu_get_current()@
+
+  .global enable_neon_fpu
+  .func enable_neon_fpu
+enable_neon_fpu:
+	/* set NSACR, both Secure and Non-secure access are allowed to NEON */
+	MRC p15, 0, r0, c1, c1, 2
+	ORR r0, r0, #(0x3<<10) @ enable fpu/neon
+	MCR p15, 0, r0, c1, c1, 2
+	/* Set the CPACR for access to CP10 and CP11*/
+	LDR r0, =0xF00000
+	MCR p15, 0, r0, c1, c0, 2
+	/* Set the FPEXC EN bit to enable the FPU */
+	MOV r3, #0x40000000 
+	@VMSR FPEXC, r3
+	MCR p10, 7, r3, c8, c0, 0
+  .endfunc
+
+  .global disable_strict_align_check
+  .func disable_strict_align_check
+disable_strict_align_check:
+  	/*Ray's note: disable strict alignment fault checking.
+ 	without disabling this, data abort will happen when accessing
+	the BPB structure of file system since it is packed.*/
+    
+  	push	{r0, lr}
+	
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, r0, #(0x1<<1) @clear A bit of SCTLR 
+	mcr p15, 0, r0, c1, c0, 0
+
+    pop {r0, pc}
+  .endfunc
+
+  .global disable_L1_cache
+  .func disable_L1_cache
+disable_L1_cache:
+    push	{r0-r6, lr}
+
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, r0, #(0x1<<12) 
+	bic r0, r0, #(0x1<<11) 
+	bic r0, r0, #(0x1<<2) 
+	bic r0, r0, #(0x1<<0) 
+	mcr p15, 0, r0, c1, c0, 0
+
+    pop {r0-r6, pc}
+
+  .endfunc
+
+  .global get_arm_private_peripheral_base
+  @ uint32_t get_arm_private_peripheral_base(void)@
+  .func get_arm_private_peripheral_base
+get_arm_private_peripheral_base: 
+
+  @ Get base address of private perpherial space
+  mrc     p15, 4, r0, c15, c0, 0  @ Read periph base address
+  bx      lr
+  
+  .endfunc    @get_arm_private_peripheral_base()@
+
+@ ------------------------------------------------------------
+@ TLB
+@ ------------------------------------------------------------
+
+  .global arm_unified_tlb_invalidate
+  @ void arm_unified_tlb_invalidate(void)@
+  .func arm_unified_tlb_invalidate
+arm_unified_tlb_invalidate:
+  mov     r0, #1
+  mcr     p15, 0, r0, c8, c7, 0                 @ TLBIALL - Invalidate entire unified TLB
+  dsb
+  bx      lr
+  .endfunc
+
+  .global arm_unified_tlb_invalidate_is
+  @ void arm_unified_tlb_invalidate_is(void)@
+  .func arm_unified_tlb_invalidate_is
+arm_unified_tlb_invalidate_is:
+  mov     r0, #1
+  mcr     p15, 0, r0, c8, c3, 0                 @ TLBIALLIS - Invalidate entire unified TLB Inner Shareable
+  dsb
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+@ Branch Prediction
+@ ------------------------------------------------------------
+
+  .global arm_branch_prediction_enable
+  @ void arm_branch_prediction_enable(void)
+  .func arm_branch_prediction_enable
+arm_branch_prediction_enable:
+  mrc     p15, 0, r0, c1, c0, 0                 @ Read SCTLR
+  orr     r0, r0, #(1 << 11)                    @ Set the Z bit (bit 11)
+  mcr     p15, 0,r0, c1, c0, 0                  @ Write SCTLR
+  bx      lr
+  .endfunc
+
+  .global arm_branch_prediction_disable
+  @ void arm_branch_prediction_disable(void)
+  .func arm_branch_prediction_disable
+arm_branch_prediction_disable:
+  mrc     p15, 0, r0, c1, c0, 0                 @ Read SCTLR
+  bic     r0, r0, #(1 << 11)                    @ Clear the Z bit (bit 11)
+  mcr     p15, 0,r0, c1, c0, 0                  @ Write SCTLR
+  bx      lr
+  .endfunc
+  
+  .global arm_branch_target_cache_invalidate
+  @ void arm_branch_target_cache_invalidate(void)
+  .func arm_branch_target_cache_invalidate
+arm_branch_target_cache_invalidate:
+  mov     r0, #0
+  mcr     p15, 0, r0, c7, c5, 6                 @ BPIALL - Invalidate entire branch predictor array
+  bx      lr
+  .endfunc
+
+  .global arm_branch_target_cache_invalidate_is
+  @ void arm_branch_target_cache_invalidate_is(void)
+  .func arm_branch_target_cache_invalidate_is
+arm_branch_target_cache_invalidate_is:
+  mov     r0, #0
+  mcr     p15, 0, r0, c7, c1, 6                 @ BPIALLIS - Invalidate entire branch predictor array Inner Shareable
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+@ SCU
+@ ------------------------------------------------------------
+
+  @ SCU offset from base of private peripheral space --> 0x000
+
+  .global scu_enable
+  @ void scu_enable(void)
+  @ Enables the SCU
+  .func scu_enable
+scu_enable:
+
+  mrc     p15, 4, r0, c15, c0, 0  @ Read periph base address
+
+  ldr     r1, [r0, #0x0]          @ Read the SCU Control Register
+  orr     r1, r1, #0x1            @ Set bit 0 (The Enable bit)
+  str     r1, [r0, #0x0]          @ Write back modifed value
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global  scu_join_smp
+  @ void scu_join_smp(void)
+  @ Set this CPU as participating in SMP
+  .func scu_join_smp
+scu_join_smp:
+
+  @ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg
+
+  mrc     p15, 0, r0, c1, c0, 1   @ Read ACTLR
+  orr     r0, r0, #0x040          @ Set bit 6
+  mcr     p15, 0, r0, c1, c0, 1   @ Write ACTLR
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_leave_smp
+  @ void scu_leave_smp(void)
+  @ Set this CPU as NOT participating in SMP
+  .func scu_leave_smp
+scu_leave_smp:
+
+  @ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg
+
+  mrc     p15, 0, r0, c1, c0, 1   @ Read ACTLR
+  bic     r0, r0, #0x040          @ Clear bit 6
+  mcr     p15, 0, r0, c1, c0, 1   @ Write ACTLR
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_get_cpus_in_smp
+  @ unsigned int scu_get_cpus_in_smp(void)
+  @ The return value is 1 bit per core:
+  @ bit 0 - CPU 0
+  @ bit 1 - CPU 1
+  @ etc...
+  .func scu_get_cpus_in_smp
+scu_get_cpus_in_smp:
+
+  mrc     p15, 4, r0, c15, c0, 0  @ Read periph base address
+
+  ldr     r0, [r0, #0x004]        @ Read SCU Configuration register
+  mov     r0, r0, lsr #4          @ Bits 7:4 gives the cores in SMP mode, shift then mask
+  and     r0, r0, #0x0F
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_enable_maintenance_broadcast
+  @ void scu_enable_maintenance_broadcast(void)
+  @ Enable the broadcasting of cache & TLB maintenance operations
+  @ When enabled AND in SMP, broadcast all "inner sharable"
+  @ cache and TLM maintenance operations to other SMP cores
+  .func scu_enable_maintenance_broadcast
+scu_enable_maintenance_broadcast:
+  mrc     p15, 0, r0, c1, c0, 1   @ Read Aux Ctrl register
+  orr     r0, r0, #0x01           @ Set the FW bit (bit 0)
+  mcr     p15, 0, r0, c1, c0, 1   @ Write Aux Ctrl register
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_disable_maintenance_broadcast
+  @ void scu_disable_maintenance_broadcast(void)
+  @ Disable the broadcasting of cache & TLB maintenance operations
+  .func scu_disable_maintenance_broadcast
+scu_disable_maintenance_broadcast:
+  mrc     p15, 0, r0, c1, c0, 1   @ Read Aux Ctrl register
+  bic     r0, r0, #0x01           @ Clear the FW bit (bit 0)
+  mcr     p15, 0, r0, c1, c0, 1   @ Write Aux Ctrl register
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_secure_invalidate
+  @ void scu_secure_invalidate(unsigned int cpu, unsigned int ways)
+  @ cpu: 0x0=CPU 0 0x1=CPU 1 etc...
+  @ This function invalidates the SCU copy of the tag rams
+  @ for the specified core.  typically only done at start-up.
+  @ Possible flow:
+  @ - Invalidate L1 caches
+  @ - Invalidate SCU copy of TAG RAMs
+  @ - Join SMP
+  .func scu_secure_invalidate
+scu_secure_invalidate:
+  and     r0, r0, #0x03           @ Mask off unused bits of CPU ID
+  mov     r0, r0, lsl #2          @ Convert into bit offset (four bits per core)
+  
+  and     r1, r1, #0x0F           @ Mask off unused bits of ways
+  mov     r1, r1, lsl r0          @ Shift ways into the correct CPU field
+
+  mrc     p15, 4, r2, c15, c0, 0  @ Read periph base address
+
+  str     r1, [r2, #0x0C]         @ Write to SCU Invalidate All in Secure State
+  
+  bx      lr
+
+  .endfunc
+
+@ ------------------------------------------------------------
+@ End of cortexA9.s
+@ ------------------------------------------------------------
+    .end

bsp/imx6sx/cortex-a9/cpu/cp15.h

@@ -0,0 +1,12 @@
+#ifndef __CP15_H__
+#define __CP15_H__
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_vector_set_base(unsigned int addr);
+
+#endif

bsp/imx6sx/cortex-a9/cpu/cp15_gcc.S

@@ -0,0 +1,140 @@
+/*
+ * File      : cp15_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * http://www.rt-thread.org
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.globl rt_cpu_get_smp_id
+rt_cpu_get_smp_id:
+    mrc     p15, #0, r0, c0, c0, #5
+    bx      lr
+
+.globl rt_cpu_vector_set_base
+rt_cpu_vector_set_base:
+    mcr     p15, #0, r0, c12, c0, #0
+    dsb
+    bx      lr
+
+.globl rt_hw_cpu_dcache_enable
+rt_hw_cpu_dcache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_hw_cpu_icache_enable
+rt_hw_cpu_icache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+_FLD_MAX_WAY:
+   .word  0x3ff
+_FLD_MAX_IDX:
+   .word  0x7ff
+
+.globl rt_cpu_dcache_clean_flush
+rt_cpu_dcache_clean_flush:
+    push    {r4-r11}
+    dmb
+    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
+    ands    r3, r0, #0x7000000       @ get level of coherency
+    mov     r3, r3, lsr #23
+    beq     finished
+    mov     r10, #0
+loop1:
+    add     r2, r10, r10, lsr #1
+    mov     r1, r0, lsr r2
+    and     r1, r1, #7
+    cmp     r1, #2
+    blt     skip
+    mcr     p15, #2, r10, c0, c0, #0
+    isb
+    mrc     p15, #1, r1, c0, c0, #0
+    and     r2, r1, #7
+    add     r2, r2, #4
+    ldr     r4, _FLD_MAX_WAY
+    ands    r4, r4, r1, lsr #3
+    clz     r5, r4
+    ldr     r7, _FLD_MAX_IDX
+    ands    r7, r7, r1, lsr #13
+loop2:
+    mov     r9, r4
+loop3:
+    orr     r11, r10, r9, lsl r5
+    orr     r11, r11, r7, lsl r2
+    mcr     p15, #0, r11, c7, c14, #2
+    subs    r9, r9, #1
+    bge     loop3
+    subs    r7, r7, #1
+    bge     loop2
+skip:
+    add     r10, r10, #2
+    cmp     r3, r10
+    bgt     loop1
+
+finished:
+    dsb
+    isb
+    pop     {r4-r11}
+    bx      lr
+
+.globl rt_hw_cpu_dcache_disable
+rt_hw_cpu_dcache_disable:
+    push    {r4-r11, lr}
+    bl      rt_cpu_dcache_clean_flush
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    pop     {r4-r11, lr}
+    bx      lr
+
+.globl rt_hw_cpu_icache_disable
+rt_hw_cpu_icache_disable:
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_cpu_mmu_disable
+rt_cpu_mmu_disable:
+    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0, r0, #1
+    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_mmu_enable
+rt_cpu_mmu_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0, r0, #0x001
+    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_tlb_set
+rt_cpu_tlb_set:
+    mcr     p15, #0, r0, c2, c0, #0
+    dmb
+    bx      lr

bsp/imx6sx/cortex-a9/cpu/cpu.c

@@ -0,0 +1,37 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <board.h>
+
+/**
+ * @addtogroup AM33xx
+ */
+/*@{*/
+
+/** shutdown CPU */
+void rt_hw_cpu_shutdown()
+{
+	rt_uint32_t level;
+	rt_kprintf("shutdown...\n");
+
+	level = rt_hw_interrupt_disable();
+	while (level)
+	{
+		RT_ASSERT(0);
+	}
+}
+
+/*@}*/

bsp/imx6sx/cortex-a9/cpu/gic.c_old

@@ -0,0 +1,316 @@
+/*
+ * File      : gic.c, ARM Generic Interrupt Controller
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013-2014, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ * 2014-04-03     Grissiom     many enhancements
+ */
+
+#include <rtthread.h>
+#include <board.h>
+
+#include "gic.h"
+#include "cp15.h"
+
+struct arm_gic
+{
+    rt_uint32_t offset;
+
+    rt_uint32_t dist_hw_base;
+    rt_uint32_t cpu_hw_base;
+};
+static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
+
+#define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00)
+#define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04)
+#define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08)
+#define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0c)
+#define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10)
+#define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14)
+#define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18)
+
+#define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000)
+#define GIC_DIST_TYPE(hw_base)              __REG32((hw_base) + 0x004)
+#define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380 + ((n)/32) * 4)
+#define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  ((n)/4) * 4)
+#define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  ((n)/4) * 4)
+#define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
+#define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00)
+#define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
+#define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8)
+
+static unsigned int _gic_max_irq;
+
+int arm_gic_get_active_irq(rt_uint32_t index)
+{
+    int irq;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
+    irq += _gic_table[index].offset;
+    return irq;
+}
+
+void arm_gic_ack(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_mask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_clear_pending(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_clear_active(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
+{
+    rt_uint32_t old_tgt;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
+
+    old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
+    old_tgt |=   cpumask << ((irq % 4)*8);
+
+    GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
+}
+
+void arm_gic_umask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_dump_type(rt_uint32_t index)
+{
+    unsigned int gic_type;
+
+    gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
+    rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
+               (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
+               _gic_table[index].dist_hw_base,
+               _gic_max_irq,
+               gic_type & (1 << 10) ? "has" : "no",
+               gic_type);
+}
+
+void arm_gic_dump(rt_uint32_t index)
+{
+    unsigned int i, k;
+
+    k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
+    rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
+    rt_kprintf("--- hw mask ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
+    }
+    rt_kprintf("\n--- hw pending ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
+                                        i * 32));
+    }
+    rt_kprintf("\n--- hw active ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
+    }
+    rt_kprintf("\n");
+}
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
+#endif
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
+{
+    unsigned int gic_type, i;
+    rt_uint32_t cpumask = 1 << 0;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].dist_hw_base = dist_base;
+    _gic_table[index].offset = irq_start;
+
+    /* Find out how many interrupts are supported. */
+    gic_type = GIC_DIST_TYPE(dist_base);
+    _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
+
+    /*
+     * The GIC only supports up to 1020 interrupt sources.
+     * Limit this to either the architected maximum, or the
+     * platform maximum.
+     */
+    if (_gic_max_irq > 1020)
+        _gic_max_irq = 1020;
+    if (_gic_max_irq > ARM_GIC_NR_IRQS)
+        _gic_max_irq = ARM_GIC_NR_IRQS;
+
+#ifndef RT_PRETENT_AS_CPU0
+    /* If we are run on the second core, the GIC should have already been setup
+     * by BootStrapProcessor. */
+    if ((rt_cpu_get_smp_id() & 0xF) != 0)
+        return 0;
+#endif
+#ifdef RT_USING_VMM
+    return 0;
+#endif
+
+    cpumask |= cpumask << 8;
+    cpumask |= cpumask << 16;
+
+    GIC_DIST_CTRL(dist_base) = 0x0;
+
+    /* Set all global interrupts to be level triggered, active low. */
+    for (i = 32; i < _gic_max_irq; i += 16)
+        GIC_DIST_CONFIG(dist_base, i) = 0x0;
+
+    /* Set all global interrupts to this CPU only. */
+    for (i = 32; i < _gic_max_irq; i += 4)
+        GIC_DIST_TARGET(dist_base, i) = cpumask;
+
+    /* Set priority on all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 4)
+        GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
+
+    /* Disable all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
+    /* All interrupts defaults to IGROUP1(IRQ). */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
+
+    /* Enable group0 and group1 interrupt forwarding. */
+    GIC_DIST_CTRL(dist_base) = 0x03;
+
+    return 0;
+}
+
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].cpu_hw_base = cpu_base;
+
+#ifndef RT_PRETENT_AS_CPU0
+    /* If we are run on the second core, the GIC should have already been setup
+     * by BootStrapProcessor. */
+    if ((rt_cpu_get_smp_id() & 0xF) != 0)
+        return 0;
+#endif
+#ifdef RT_USING_VMM
+    return 0;
+#endif
+
+    GIC_CPU_PRIMASK(cpu_base) = 0xf0;
+    /* Enable CPU interrupt */
+    GIC_CPU_CTRL(cpu_base) = 0x01;
+
+    return 0;
+}
+
+void arm_gic_set_group(rt_uint32_t index, int vector, int group)
+{
+    /* As for GICv2, there are only group0 and group1. */
+    RT_ASSERT(group <= 1);
+    RT_ASSERT(vector < _gic_max_irq);
+
+    if (group == 0)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) &= ~(1 << (vector % 32));
+    }
+    else if (group == 1)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) |=  (1 << (vector % 32));
+    }
+}
+
+void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq)
+{
+    unsigned int reg;
+
+    RT_ASSERT(irq <= 15);
+    RT_ASSERT(target_cpu <= 255);
+
+    reg = (target_cpu << 16) | irq;
+    GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg;
+}
+
+void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq)
+{
+    RT_ASSERT(irq <= 15);
+    RT_ASSERT(target_cpu <= 255);
+
+    GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = target_cpu << (irq % 4);
+}

bsp/imx6sx/cortex-a9/cpu/gic.h_old

@@ -0,0 +1,35 @@
+/*
+ * File      : gic.h, ARM Generic Interrupt Controller
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#ifndef __GIC_H__
+#define __GIC_H__
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
+
+void arm_gic_mask(rt_uint32_t index, int irq);
+void arm_gic_umask(rt_uint32_t index, int irq);
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
+void arm_gic_set_group(rt_uint32_t index, int vector, int group);
+
+int arm_gic_get_active_irq(rt_uint32_t index);
+void arm_gic_ack(rt_uint32_t index, int irq);
+
+void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq);
+void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq);
+
+void arm_gic_dump_type(rt_uint32_t index);
+
+#endif
+

bsp/imx6sx/cortex-a9/cpu/interrupt.c

@@ -0,0 +1,152 @@
+/*
+ * File      : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-06     Bernard      first version
+ * 2014-04-03     Grissiom     port to VMM
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <irq_numbers.h>
+#include <interrupt.h>
+
+#include <gic.h>
+#include "cp15.h"
+
+#define MAX_HANDLERS                IMX_INTERRUPT_COUNT
+
+extern volatile rt_uint8_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+extern void rt_cpu_vector_set_base(unsigned int addr);
+extern int system_vectors;
+
+/* keep compatible with platform SDK */
+void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr)
+{
+    rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown");
+}
+
+void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
+{
+    gic_set_irq_priority(irq_id, priority);
+    gic_set_irq_security(irq_id, false);    // set IRQ as non-secure
+    gic_set_cpu_target(irq_id, cpu_id, true);
+    gic_enable_irq(irq_id, true);
+}
+
+void disable_interrupt(uint32_t irq_id, uint32_t cpu_id)
+{
+    gic_enable_irq(irq_id, false);
+    gic_set_cpu_target(irq_id, cpu_id, false);
+}
+
+static void rt_hw_vector_init(void)
+{
+    int sctrl;
+    unsigned int *src = (unsigned int *)&system_vectors;
+
+    /* C12-C0 is only active when SCTLR.V = 0 */
+    asm volatile ("mrc p15, #0, %0, c1, c0, #0"
+                  :"=r" (sctrl));
+    sctrl &= ~(1 << 13);
+    asm volatile ("mcr p15, #0, %0, c1, c0, #0"
+                  :
+                  :"r" (sctrl));
+
+    asm volatile ("mcr p15, #0, %0, c12, c0, #0"
+                  :
+                  :"r" (src));
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    rt_hw_vector_init();
+    gic_init();
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    disable_interrupt(vector, 0);
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    enable_interrupt(vector, 0, 0);
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+        // arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id());
+    }
+
+    return old_handler;
+}
+
+/**
+ * Trigger a software IRQ
+ *
+ * Since we are running in single core, the target CPU are always CPU0.
+ */
+void rt_hw_interrupt_trigger(int vector)
+{
+    // arm_gic_trigger(0, 1, vector);
+}
+
+void rt_hw_interrupt_clear(int vector)
+{
+    gic_write_end_of_irq(vector);
+}

bsp/imx6sx/cortex-a9/cpu/interrupt.h_old

@@ -0,0 +1,24 @@
+/*
+ * File      : interrupt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-06     Bernard      first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+void rt_hw_interrupt_control(int vector, int priority, int route);
+int rt_hw_interrupt_get_active(int fiq_irq);
+void rt_hw_interrupt_ack(int fiq_irq);
+void rt_hw_interrupt_trigger(int vector);
+void rt_hw_interrupt_clear(int vector);
+
+#endif

bsp/imx6sx/cortex-a9/cpu/mmu.c

@@ -0,0 +1,207 @@
+/*
+ * File      : mmu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-01-10     bernard      porting to AM1808
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include "cp15.h"
+
+#define DESC_SEC       (0x2)
+#define CB             (3<<2)  //cache_on, write_back
+#define CNB            (2<<2)  //cache_on, write_through
+#define NCB            (1<<2)  //cache_off,WR_BUF on
+#define NCNB           (0<<2)  //cache_off,WR_BUF off
+#define AP_RW          (3<<10) //supervisor=RW, user=RW
+#define AP_RO          (2<<10) //supervisor=RW, user=RO
+#define XN             (1<<4)  // eXecute Never
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0<<5)
+#define DOMAIN1        (0x1<<5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
+
+/* Read/Write, cache, write back */
+#define RW_CB          (AP_RW|DOMAIN0|CB|DESC_SEC)
+/* Read/Write, cache, write through */
+#define RW_CNB         (AP_RW|DOMAIN0|CNB|DESC_SEC)
+/* Read/Write without cache and write buffer */
+#define RW_NCNB        (AP_RW|DOMAIN0|NCNB|DESC_SEC)
+/* Read/Write without cache and write buffer, no execute */
+#define RW_NCNBXN      (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
+/* Read/Write without cache and write buffer */
+#define RW_FAULT       (AP_RW|DOMAIN1|NCNB|DESC_SEC)
+
+/* dump 2nd level page table */
+void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    for (i = 0; i < 256; i++)
+    {
+        rt_uint32_t pte2 = ptb[i];
+        if ((pte2 & 0x3) == 0)
+        {
+            if (fcnt == 0)
+                rt_kprintf("    ");
+            rt_kprintf("%04x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("    %04x: %x: ", i, pte2);
+        if ((pte2 & 0x3) == 0x1)
+        {
+            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
+                       (pte2 >> 15) & 0x1,
+                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
+                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
+        }
+    }
+}
+
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    rt_kprintf("page table@%p\n", ptb);
+    for (i = 0; i < 1024*4; i++)
+    {
+        rt_uint32_t pte1 = ptb[i];
+        if ((pte1 & 0x3) == 0)
+        {
+            rt_kprintf("%03x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("%03x: %08x: ", i, pte1);
+        if ((pte1 & 0x3) == 0x3)
+        {
+            rt_kprintf("LPAE\n");
+        }
+        else if ((pte1 & 0x3) == 0x1)
+        {
+            rt_kprintf("pte,ns:%d,domain:%d\n",
+                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
+            /*
+             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
+             *                               - 0x80000000 + 0xC0000000));
+             */
+        }
+        else if (pte1 & (1 << 18))
+        {
+            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("section,ns:%d,ap:%x,"
+                       "xn:%d,texcb:%02x,domain:%d\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       (((pte1 & (0x7 << 12)) >> 10) |
+                        ((pte1 &        0x0c) >>  2)) & 0x1f,
+                       (pte1 >> 5) & 0xf);
+        }
+    }
+}
+
+/* level1 page table, each entry for 1MB memory. */
+volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
+void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
+                      rt_uint32_t vaddrEnd,
+                      rt_uint32_t paddrStart,
+                      rt_uint32_t attr)
+{
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for(i = 0; i <= nSec; i++)
+    {
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
+        pTT++;
+    }
+}
+
+unsigned long rt_hw_set_domain_register(unsigned long domain_val)
+{
+    unsigned long old_domain;
+
+    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
+    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
+
+    return old_domain;
+}
+
+void rt_hw_mmu_init(void)
+{
+    rt_hw_cpu_dcache_disable();
+    rt_hw_cpu_icache_disable();
+    rt_cpu_mmu_disable();
+
+    /* set page table */
+    /* 4G 1:1 memory */
+    rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB);
+    /* IO memory region */
+    rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN);
+
+    /*rt_hw_cpu_dump_page_table(MMUTable);*/
+    rt_hw_set_domain_register(0x55555555);
+
+    rt_cpu_tlb_set(MMUTable);
+
+    rt_cpu_mmu_enable();
+
+    rt_hw_cpu_icache_enable();
+    rt_hw_cpu_dcache_enable();
+}
+

bsp/imx6sx/cortex-a9/cpu/pmu.c

@@ -0,0 +1,12 @@
+#include <rtthread.h>
+#include "pmu.h"
+
+void rt_hw_pmu_dump_feature(void)
+{
+    unsigned long reg;
+
+    reg = rt_hw_pmu_get_control();
+    rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n",
+               reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f);
+    RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f));
+}

bsp/imx6sx/cortex-a9/cpu/pmu.h

@@ -0,0 +1,151 @@
+#ifndef __PMU_H__
+#define __PMU_H__
+
+#include "board.h"
+
+/* Number of counters */
+#define ARM_PMU_CNTER_NR 4
+
+enum rt_hw_pmu_event_type {
+    ARM_PMU_EVENT_PMNC_SW_INCR      = 0x00,
+    ARM_PMU_EVENT_L1_ICACHE_REFILL  = 0x01,
+    ARM_PMU_EVENT_ITLB_REFILL       = 0x02,
+    ARM_PMU_EVENT_L1_DCACHE_REFILL  = 0x03,
+    ARM_PMU_EVENT_L1_DCACHE_ACCESS  = 0x04,
+    ARM_PMU_EVENT_DTLB_REFILL       = 0x05,
+    ARM_PMU_EVENT_MEM_READ          = 0x06,
+    ARM_PMU_EVENT_MEM_WRITE         = 0x07,
+    ARM_PMU_EVENT_INSTR_EXECUTED    = 0x08,
+    ARM_PMU_EVENT_EXC_TAKEN         = 0x09,
+    ARM_PMU_EVENT_EXC_EXECUTED      = 0x0A,
+    ARM_PMU_EVENT_CID_WRITE         = 0x0B,
+};
+
+/* Enable bit */
+#define ARM_PMU_PMCR_E   (0x01 << 0)
+/* Event counter reset */
+#define ARM_PMU_PMCR_P   (0x01 << 1)
+/* Cycle counter reset */
+#define ARM_PMU_PMCR_C   (0x01 << 2)
+/* Cycle counter divider */
+#define ARM_PMU_PMCR_D   (0x01 << 3)
+
+#ifdef __GNUC__
+rt_inline void rt_hw_pmu_enable_cnt(int divide64)
+{
+    unsigned long pmcr;
+    unsigned long pmcntenset;
+
+    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
+    pmcr |= ARM_PMU_PMCR_E | ARM_PMU_PMCR_P | ARM_PMU_PMCR_C;
+    if (divide64)
+        pmcr |= ARM_PMU_PMCR_D;
+    else
+        pmcr &= ~ARM_PMU_PMCR_D;
+    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
+
+    /* enable all the counters */
+    pmcntenset = ~0;
+    asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset));
+    /* clear overflows(just in case) */
+    asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset));
+}
+
+rt_inline unsigned long rt_hw_pmu_get_control(void)
+{
+    unsigned long pmcr;
+    asm ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
+    return pmcr;
+}
+
+rt_inline unsigned long rt_hw_pmu_get_ceid(void)
+{
+    unsigned long reg;
+    /* only PMCEID0 is supported, PMCEID1 is RAZ. */
+    asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg));
+    return reg;
+}
+
+rt_inline unsigned long rt_hw_pmu_get_cnten(void)
+{
+    unsigned long pmcnt;
+    asm ("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt));
+    return pmcnt;
+}
+
+rt_inline void rt_hw_pmu_reset_cycle(void)
+{
+    unsigned long pmcr;
+
+    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
+    pmcr |= ARM_PMU_PMCR_C;
+    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
+    asm volatile ("isb");
+}
+
+rt_inline void rt_hw_pmu_reset_event(void)
+{
+    unsigned long pmcr;
+
+    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
+    pmcr |= ARM_PMU_PMCR_P;
+    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
+    asm volatile ("isb");
+}
+
+rt_inline unsigned long rt_hw_pmu_get_cycle(void)
+{
+    unsigned long cyc;
+    asm volatile ("isb");
+    asm volatile ("mrc  p15, 0, %0, c9, c13, 0" : "=r"(cyc));
+    return cyc;
+}
+
+rt_inline void rt_hw_pmu_select_counter(int idx)
+{
+    RT_ASSERT(idx < ARM_PMU_CNTER_NR);
+
+    asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx));
+    /* Linux add an isb here, don't know why here. */
+    asm volatile ("isb");
+}
+
+rt_inline void rt_hw_pmu_select_event(int idx,
+                                      enum rt_hw_pmu_event_type eve)
+{
+    RT_ASSERT(idx < ARM_PMU_CNTER_NR);
+
+    rt_hw_pmu_select_counter(idx);
+    asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve));
+}
+
+rt_inline unsigned long rt_hw_pmu_read_counter(int idx)
+{
+    unsigned long reg;
+
+    rt_hw_pmu_select_counter(idx);
+    asm volatile ("isb");
+    asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg));
+    return reg;
+}
+
+rt_inline unsigned long rt_hw_pmu_get_ovsr(void)
+{
+    unsigned long reg;
+    asm volatile ("isb");
+    asm ("mrc  p15, 0, %0, c9, c12, 3" : "=r"(reg));
+    return reg;
+}
+
+rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg)
+{
+    asm ("mcr  p15, 0, %0, c9, c12, 3" : : "r"(reg));
+    asm volatile ("isb");
+}
+
+#endif
+
+void rt_hw_pmu_dump_feature(void);
+
+#endif /* end of include guard: __PMU_H__ */
+

bsp/imx6sx/cortex-a9/cpu/stack.c

@@ -0,0 +1,66 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+#include <armv7.h>
+
+/**
+ * @addtogroup AM33xx
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	rt_uint32_t *stk;
+
+	stk 	 = (rt_uint32_t*)stack_addr;
+	*(stk) 	 = (rt_uint32_t)tentry;			/* entry point */
+	*(--stk) = (rt_uint32_t)texit;			/* lr */
+	*(--stk) = 0;							/* r12 */
+	*(--stk) = 0;							/* r11 */
+	*(--stk) = 0;							/* r10 */
+	*(--stk) = 0;							/* r9 */
+	*(--stk) = 0;							/* r8 */
+	*(--stk) = 0;							/* r7 */
+	*(--stk) = 0;							/* r6 */
+	*(--stk) = 0;							/* r5 */
+	*(--stk) = 0;							/* r4 */
+	*(--stk) = 0;							/* r3 */
+	*(--stk) = 0;							/* r2 */
+	*(--stk) = 0;							/* r1 */
+	*(--stk) = (rt_uint32_t)parameter;		/* r0 : argument */
+
+	/* cpsr */
+	if ((rt_uint32_t)tentry & 0x01)
+		*(--stk) = SVCMODE | 0x20;			/* thumb mode */
+	else
+		*(--stk) = SVCMODE;					/* arm mode   */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
+
+/*@}*/

bsp/imx6sx/cortex-a9/cpu/start_gcc.S

@@ -0,0 +1,249 @@
+/*
+ * File      : start_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+.equ UND_Stack_Size,     0x00000000
+.equ SVC_Stack_Size,     0x00000100
+.equ ABT_Stack_Size,     0x00000000
+.equ RT_FIQ_STACK_PGSZ,  0x00000000
+.equ RT_IRQ_STACK_PGSZ,  0x00000100
+.equ USR_Stack_Size,     0x00000100
+
+#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+                 RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
+
+.section .data.share.isr
+/* stack */
+.globl stack_start
+.globl stack_top
+
+stack_start:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top:
+
+.text
+/* reset entry */
+.globl _reset
+_reset:
+    bl      rt_cpu_mmu_disable
+    /* set the cpu to SVC32 mode and disable interrupt */
+    mrs     r0, cpsr
+    bic     r0, r0, #0x1f
+    orr     r0, r0, #0x13
+    msr     cpsr_c, r0
+
+    /* setup stack */
+    bl      stack_setup
+
+    /* clear .bss */
+    mov     r0,#0                   /* get a zero                       */
+    ldr     r1,=__bss_start         /* bss start                        */
+    ldr     r2,=__bss_end           /* bss end                          */
+
+bss_loop:
+    cmp     r1,r2                   /* check if data to clear           */
+    strlo   r0,[r1],#4              /* clear 4 bytes                    */
+    blo     bss_loop                /* loop until done                  */
+
+    /* call C++ constructors of global objects                          */
+    ldr     r0, =__ctors_start__
+    ldr     r1, =__ctors_end__
+
+ctor_loop:
+    cmp     r0, r1
+    beq     ctor_end
+    ldr     r2, [r0], #4
+    stmfd   sp!, {r0-r1}
+    mov     lr, pc
+    bx      r2
+    ldmfd   sp!, {r0-r1}
+    b       ctor_loop
+ctor_end:
+
+    /* start RT-Thread Kernel */
+    ldr     pc, _rtthread_startup
+_rtthread_startup:
+    .word rtthread_startup
+
+stack_setup:
+    ldr     r0, =stack_top
+
+    @  Set the startup stack for svc
+    mov     sp, r0
+
+    @  Enter Undefined Instruction Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #UND_Stack_Size
+
+    @  Enter Abort Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #ABT_Stack_Size
+
+    @  Enter FIQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_FIQ_STACK_PGSZ
+
+    @  Enter IRQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_IRQ_STACK_PGSZ
+
+    /* come back to SVC mode */
+    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
+    bx      lr
+
+/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
+.section .text.isr, "ax"
+    .align  5
+.globl vector_fiq
+vector_fiq:
+    stmfd   sp!,{r0-r7,lr}
+    bl      rt_hw_trap_fiq
+    ldmfd   sp!,{r0-r7,lr}
+    subs    pc, lr, #4
+
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+
+.globl      rt_current_thread
+.globl      vmm_thread
+.globl      vmm_virq_check
+
+    .align  5
+.globl vector_irq
+vector_irq:
+    stmfd   sp!, {r0-r12,lr}
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+
+    @ if rt_thread_switch_interrupt_flag set, jump to
+    @ rt_hw_context_switch_interrupt_do and don't return
+    ldr     r0, =rt_thread_switch_interrupt_flag
+    ldr     r1, [r0]
+    cmp     r1, #1
+    beq     rt_hw_context_switch_interrupt_do
+
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc,  lr, #4
+
+rt_hw_context_switch_interrupt_do:
+    mov     r1,  #0         @ clear flag
+    str     r1,  [r0]
+
+    mov     r1, sp          @ r1 point to {r0-r3} in stack
+    add     sp, sp, #4*4
+    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
+    mrs     r0,  spsr       @ get cpsr of interrupt thread
+    sub     r2,  lr, #4     @ save old task's pc to r2
+
+    @ Switch to SVC mode with no interrupt. If the usr mode guest is
+    @ interrupted, this will just switch to the stack of kernel space.
+    @ save the registers in kernel space won't trigger data abort.
+    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
+
+    stmfd   sp!, {r2}       @ push old task's pc
+    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
+    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
+    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
+    stmfd   sp!, {r0}       @ push old task's cpsr
+
+    ldr     r4,  =rt_interrupt_from_thread
+    ldr     r5,  [r4]
+    str     sp,  [r5]       @ store sp in preempted tasks's TCB
+
+    ldr     r6,  =rt_interrupt_to_thread
+    ldr     r6,  [r6]
+    ldr     sp,  [r6]       @ get new task's stack pointer
+
+    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
+    msr     spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
+
+.macro push_svc_reg
+    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
+    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
+    mov     r0, sp
+    mrs     r6, spsr                @/* Save CPSR                       */
+    str     lr, [r0, #15*4]         @/* Push PC                         */
+    str     r6, [r0, #16*4]         @/* Push CPSR                       */
+    cps     #Mode_SVC
+    str     sp, [r0, #13*4]         @/* Save calling SP                 */
+    str     lr, [r0, #14*4]         @/* Save calling PC                 */
+.endm
+
+    .align  5
+    .globl	vector_swi
+vector_swi:
+    push_svc_reg
+    bl      rt_hw_trap_swi
+    b       .
+
+    .align  5
+    .globl	vector_undef
+vector_undef:
+    push_svc_reg
+    bl      rt_hw_trap_undef
+    b       .
+
+    .align  5
+    .globl	vector_pabt
+vector_pabt:
+    push_svc_reg
+    bl      rt_hw_trap_pabt
+    b       .
+
+    .align  5
+    .globl	vector_dabt
+vector_dabt:
+    push_svc_reg
+    bl      rt_hw_trap_dabt
+    b       .
+
+    .align  5
+    .globl	vector_resv
+vector_resv:
+    push_svc_reg
+    bl      rt_hw_trap_resv
+    b       .

bsp/imx6sx/cortex-a9/cpu/trap.c

@@ -0,0 +1,181 @@
+/*
+ * File      : trap.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include "armv7.h"
+
+#include "gic.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("undefined instruction:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("software interrupt:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("prefetch abort:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("data abort:");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("reserved trap:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    // vectNum = RESERVED[31:13] | CPUID[12:10] | INTERRUPT_ID[9:0]
+    // send ack and get ID source
+    uint32_t vectNum = gic_read_irq_ack();
+
+    // Check that INT_ID isn't 1023 or 1022 (spurious interrupt)
+    if (vectNum & 0x0200)
+    {
+        gic_write_end_of_irq(vectNum);  // send end of irq
+    }
+    else
+    {
+        // copy the local value to the global image of CPUID
+        unsigned cpu = (vectNum >> 10) & 0x7;
+        unsigned irq = vectNum & 0x1FF;
+
+        /* skip warning */
+        cpu = cpu;
+
+        // Call the service routine stored in the handlers array. If there isn't
+        // one for this IRQ, then call the default handler.
+        /* get interrupt service routine */
+        isr_func = isr_table[irq].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+        isr_table[irq].counter++;
+#endif
+        if (isr_func)
+        {
+            /* Interrupt for myself. */
+            param = isr_table[irq].param;
+            /* turn to interrupt service routine */
+            isr_func(irq, param);
+        }
+
+        // Signal the end of the irq.
+        gic_write_end_of_irq(vectNum);
+    }
+}
+
+void rt_hw_trap_fiq(void)
+{
+    /* TODO */
+}

bsp/imx6sx/cortex-a9/cpu/vector_gcc.S

@@ -0,0 +1,65 @@
+/*
+ * File      : vector_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .vectors, "ax"
+.code 32
+
+.globl system_vectors
+system_vectors:
+    ldr pc, _vector_reset
+    ldr pc, _vector_undef
+    ldr pc, _vector_swi
+    ldr pc, _vector_pabt
+    ldr pc, _vector_dabt
+    ldr pc, _vector_resv
+    ldr pc, _vector_irq
+    ldr pc, _vector_fiq
+
+.globl _reset
+.globl vector_undef
+.globl vector_swi
+.globl vector_pabt
+.globl vector_dabt
+.globl vector_resv
+.globl vector_irq
+.globl vector_fiq
+
+_vector_reset:
+    .word _reset
+_vector_undef:
+    .word vector_undef
+_vector_swi:
+    .word vector_swi
+_vector_pabt:
+    .word vector_pabt
+_vector_dabt:
+    .word vector_dabt
+_vector_resv:
+    .word vector_resv
+_vector_irq:
+    .word vector_irq
+_vector_fiq:
+    .word vector_fiq
+
+.balignl 	16,0xdeadbeef

bsp/imx6sx/cortex-a9/drivers/SConscript

@@ -0,0 +1,13 @@
+import copy
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/imx6sx/cortex-a9/drivers/board.c

@@ -0,0 +1,86 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-11-20     Bernard    the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <components.h>
+
+#include "board.h"
+
+#include <registers/regsarmglobaltimer.h>
+#include <registers/regsepit.h>
+
+#include <uart/imx_uart.h>
+#include <timer/epit.h>
+#include <core/cortex_a9.h>
+
+static void rt_hw_timer_isr(int vector, void *param)
+{
+    rt_tick_increase();
+    epit_get_compare_event(HW_EPIT1);
+}
+
+int rt_hw_timer_init(void)
+{
+    uint32_t freq;
+    // The ARM private peripheral clock is half the CPU clock.
+    uint32_t periphClock = get_main_clock(CPU_CLK) / 2;
+    uint32_t prescaler = (periphClock / 1000000) - 1;
+
+    // Divide down the prescaler until it fits into 8 bits. We add up the number of ticks
+    // it takes to equal a microsecond interval.
+    while (prescaler > 0xff)
+    {
+        prescaler /= 2;
+    }
+
+    // Make sure the timer is off.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0;
+
+    // Clear counter.
+    HW_ARMGLOBALTIMER_COUNTERn_WR(0, 0);
+    HW_ARMGLOBALTIMER_COUNTERn_WR(1, 0);
+
+    // Set prescaler and clear other flags.
+    HW_ARMGLOBALTIMER_CONTROL_WR(BF_ARMGLOBALTIMER_CONTROL_PRESCALER(prescaler));
+
+    // Now turn on the timer.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1;
+
+    freq = get_main_clock(IPG_CLK);
+    epit_init(HW_EPIT1, CLKSRC_IPG_CLK, freq / 1000000,
+              SET_AND_FORGET, 10000, WAIT_MODE_EN | STOP_MODE_EN);
+
+    epit_counter_enable(HW_EPIT1, 10000, IRQ_MODE);
+
+    rt_hw_interrupt_install(IMX_INT_EPIT1, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(IMX_INT_EPIT1);
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_timer_init);
+
+/**
+ * This function will initialize beaglebone board
+ */
+void rt_hw_board_init(void)
+{
+    enable_neon_fpu();
+    disable_strict_align_check();
+
+    rt_components_board_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
+/*@}*/

bsp/imx6sx/cortex-a9/drivers/board.h

@@ -0,0 +1,33 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-06     Bernard    the first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <registers.h>
+#include <irq_numbers.h>
+
+#if defined(__CC_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void*)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif defined(__GNUC__)
+extern int __bss_end;
+#define HEAP_BEGIN      ((void*)&__bss_end)
+#endif
+
+#define HEAP_END        (void*)(0x80000000 + 32 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif

bsp/imx6sx/cortex-a9/drivers/emac_drv.c

@@ -0,0 +1,221 @@
+/*
+ * File      : emac_drv.c
+ *             i.MX6 EMAC Ethernet driver
+ * COPYRIGHT (C) 2015, Shanghai Real-Thread Electronic Technology Co.,Ltd
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-07-15     Bernard      The first version
+ */
+
+#include <rtthread.h>
+#include <netif/ethernetif.h>
+
+#include <soc_memory_map.h>
+#include <stdint.h>
+#include <enet/enet.h>
+#include <lwipopts.h>
+#include "emac_drv.h"
+
+#define MAX_ADDR_LEN 			6
+#define IMX_EMAC_DEVICE(eth)	(struct emac_device*)(eth)
+
+struct emac_device
+{
+	/* inherit from Ethernet device */
+	struct eth_device parent;
+
+	imx_enet_priv_t enet_priv;
+	/* interface address info. */
+	rt_uint8_t  dev_addr[MAX_ADDR_LEN];			/* MAC address	*/
+};
+static struct emac_device _emac;
+
+#define ENET_PHY_ADDR 1
+extern int imx_enet_mii_type(imx_enet_priv_t * dev, enum imx_mii_type mii_type);
+extern void imx_enet_iomux(void);
+extern void imx_enet_phy_reset(void);
+
+static unsigned char s_pkt_send[2048];
+static unsigned char s_pkt_recv[2048];
+
+void init_enet(struct emac_device* emac)
+{
+    // setup iomux for ENET
+    imx_enet_iomux();
+    imx_enet_phy_reset();
+
+    // init enet0
+    imx_enet_init(&emac->enet_priv, ENET_BASE_ADDR, ENET_PHY_ADDR);
+    imx_enet_mii_type(&emac->enet_priv, RGMII);
+
+    // init phy0.
+    imx_enet_phy_init(&emac->enet_priv);
+
+    // Check PHY link status.
+    if (!(emac->enet_priv.status & ENET_STATUS_LINK_ON))
+    {
+		rt_kprintf("ENET link status check fail\n");
+    }
+
+    imx_enet_start(&emac->enet_priv, emac->dev_addr);
+}
+
+void imx_enet_isr(int vector, void *param)
+{
+	unsigned int value = 0;
+	imx_enet_priv_t * dev = &(_emac.enet_priv);
+	volatile hw_enet_t *enet_reg = dev->enet_reg;
+
+    value = enet_reg->EIR.U;
+    enet_reg->EIR.U = value & (~ENET_EVENT_MII);
+
+    if (value & ENET_EVENT_TX_ERR)
+	{
+        dev->tx_busy = 0;
+    }
+	else if (value & ENET_EVENT_TX)
+	{
+        dev->tx_busy = 0;
+    }
+
+    if (value & ENET_EVENT_RX)
+	{
+		eth_device_ready(&(_emac.parent));
+    }
+
+    if (value & ENET_EVENT_HBERR)
+	{
+        // printf("WARNGING[POLL]: Hearbeat error!\n");
+    }
+
+    if (value & ENET_EVENT_EBERR)
+	{
+        // printf("WARNING[POLL]: Ethernet Bus Error!\n");
+    }
+}
+
+static rt_err_t imx_emac_init(rt_device_t dev)
+{
+	struct emac_device *emac;
+
+	emac = IMX_EMAC_DEVICE(dev);
+
+	/* initialize enet */
+	init_enet(emac);
+	return RT_EOK;
+}
+
+static rt_err_t imx_emac_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	return RT_EOK;
+}
+
+static rt_err_t imx_emac_close(rt_device_t dev)
+{
+	return RT_EOK;
+}
+
+static rt_size_t imx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_set_errno(-RT_ENOSYS);
+	return 0;
+}
+
+static rt_size_t imx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	rt_set_errno(-RT_ENOSYS);
+	return 0;
+}
+
+static rt_err_t imx_emac_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    struct emac_device *emac;
+
+    emac = IMX_EMAC_DEVICE(dev);
+    RT_ASSERT(emac != RT_NULL);
+
+	switch(cmd)
+	{
+	case NIOCTL_GADDR:
+		/* get MAC address */
+		if(args) rt_memcpy(args, emac->dev_addr, 6);
+		else return -RT_ERROR;
+		break;
+
+	default :
+		break;
+	}
+
+	return RT_EOK;
+}
+
+/* Ethernet device interface */
+/* transmit packet. */
+rt_err_t imx_emac_tx(rt_device_t dev, struct pbuf* p)
+{
+    rt_err_t result = RT_EOK;
+    struct emac_device *emac;
+
+    emac = IMX_EMAC_DEVICE(dev);
+    RT_ASSERT(emac != RT_NULL);
+
+    /* copy pbuf to a whole ETH frame */
+    pbuf_copy_partial(p, s_pkt_send, p->tot_len, 0);
+	/* send to the enet */
+	imx_enet_send(&emac->enet_priv, s_pkt_send, p->tot_len, 1);
+
+    return result;
+}
+
+/* reception packet. */
+struct pbuf *imx_emac_rx(rt_device_t dev)
+{
+	int len;
+    struct pbuf* p = RT_NULL;
+    struct emac_device *emac;
+
+    emac = IMX_EMAC_DEVICE(dev);
+    RT_ASSERT(emac != RT_NULL);
+
+	imx_enet_recv(&emac->enet_priv, s_pkt_recv, &len);
+	if (len > 0)
+	{
+		/* We allocate a pbuf chain of pbufs from the pool. */
+		p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+		if (p != RT_NULL)
+		{
+			pbuf_take(p, s_pkt_recv, len);
+		}
+	}
+
+    return p;
+}
+
+int imx_emac_hw_init(void)
+{
+    /* test MAC address */
+	_emac.dev_addr[0] = 0x00;
+	_emac.dev_addr[1] = 0x11;
+	_emac.dev_addr[2] = 0x22;
+	_emac.dev_addr[3] = 0x33;
+	_emac.dev_addr[4] = 0x44;
+	_emac.dev_addr[5] = 0x55;
+
+	_emac.parent.parent.init       = imx_emac_init;
+	_emac.parent.parent.open       = imx_emac_open;
+	_emac.parent.parent.close      = imx_emac_close;
+	_emac.parent.parent.read       = imx_emac_read;
+	_emac.parent.parent.write      = imx_emac_write;
+	_emac.parent.parent.control    = imx_emac_control;
+	_emac.parent.parent.user_data  = RT_NULL;
+
+	_emac.parent.eth_rx     = imx_emac_rx;
+	_emac.parent.eth_tx     = imx_emac_tx;
+
+    /* register ETH device */
+    eth_device_init(&(_emac.parent), "e0");
+
+	return 0;
+}
+INIT_DEVICE_EXPORT(imx_emac_hw_init);

bsp/imx6sx/cortex-a9/drivers/emac_drv.h

@@ -0,0 +1,16 @@
+/*
+ * File      : drv_emac.h
+ *             i.MX6 EMAC Ethernet driver
+ * COPYRIGHT (C) 2015, Shanghai Real-Thread Electronic Technology Co.,Ltd
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-07-15     Bernard      The first version
+ */
+
+#ifndef EMAC_DRV_H__
+#define EMAC_DRV_H__
+
+int emac_hw_init(void);
+
+#endif

bsp/imx6sx/cortex-a9/drivers/serial.c

@@ -0,0 +1,202 @@
+/*
+ *  serial.c UART driver
+ *
+ * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  This file is part of RT-Thread (http://www.rt-thread.org)
+ *  Maintainer: bernard.xiong <bernard.xiong at gmail.com>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-03-30     Bernard      the first verion
+ */
+
+#include <rthw.h>
+#include <registers/regsuart.h>
+#include <uart/imx_uart.h>
+
+#include <rtdevice.h>
+
+#include "serial.h"
+
+struct hw_uart_device
+{
+    uint32_t instance;
+    int irqno;
+};
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)param;
+
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+}
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct hw_uart_device *uart;
+    uint32_t baudrate;
+    uint8_t parity, stopbits, datasize, flowcontrol;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    baudrate = cfg->baud_rate;
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        datasize = EIGHTBITS;
+        break;
+    case DATA_BITS_7:
+        datasize = SEVENBITS;
+        break;
+    }
+    if (cfg->stop_bits == STOP_BITS_1) stopbits = STOPBITS_ONE;
+    else if (cfg->stop_bits == STOP_BITS_2) stopbits = STOPBITS_TWO;
+
+    parity = PARITY_NONE;
+    flowcontrol = FLOWCTRL_OFF;
+
+    /* initailize UART */
+    // uart_init(uart->instance, baudrate, parity, stopbits, datasize, flowcontrol);
+
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, serial, "uart");
+    rt_hw_interrupt_mask(uart->irqno);
+
+    /* Set the IRQ mode for the Rx FIFO */
+    uart_set_FIFO_mode(uart->instance, RX_FIFO, 1, IRQ_MODE);
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        rt_hw_interrupt_mask(uart->irqno);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    uart_putchar(uart->instance, (uint8_t*)&c);
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    ch = uart_getchar(uart->instance);
+    if (ch == NONE_CHAR) ch = -1;
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+#ifdef RT_USING_UART0
+/* UART device driver structure */
+static struct hw_uart_device _uart0_device =
+{
+    HW_UART0,
+    IMX_INT_UART0
+};
+static struct rt_serial_device _serial0;
+#endif
+
+#ifdef RT_USING_UART1
+/* UART1 device driver structure */
+static struct hw_uart_device _uart1_device =
+{
+    HW_UART1,
+    IMX_INT_UART1
+};
+static struct rt_serial_device _serial1;
+#endif
+
+int rt_hw_uart_init(void)
+{
+    struct hw_uart_device *uart;
+    struct serial_configure config;
+
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
+
+#ifdef RT_USING_UART0
+    uart = &_uart0_device;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif
+
+#ifdef RT_USING_UART1
+    uart = &_uart1_device;
+    _serial1.ops = &_uart_ops;
+    _serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
+#endif
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);

bsp/imx6sx/cortex-a9/drivers/serial.h

@@ -0,0 +1,39 @@
+/*
+ *  UART driver
+ *
+ * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  This file is part of RT-Thread (http://www.rt-thread.org)
+ *  Maintainer: bernard.xiong <bernard.xiong at gmail.com>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-03-30     Bernard      the first verion
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+#include <board.h>
+
+int rt_hw_uart_init(void);
+
+#endif
+
+

bsp/imx6sx/cortex-a9/imx6.lds

@@ -0,0 +1,99 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+
+SECTIONS
+{
+    . = 0x80100000;
+
+    __text_start = .;
+    .text :
+    {
+        *(.vectors)
+        *(.text)
+        *(.text.*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+    } =0
+    __text_end = .;
+
+    __rodata_start = .;
+    .rodata   : { *(.rodata) *(.rodata.*) }
+    __rodata_end = .;
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16 * 1024);
+    .l1_page_table :
+    {
+        __l1_page_table_start = .;
+        . += 16K;
+    }
+
+    __data_start = .;
+    . = ALIGN(4);
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+    }
+    __data_end = .;
+
+    . = ALIGN(4);
+    __bss_start = __data_end;
+    .bss       :
+    {
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    }
+    . = ALIGN(4);
+    __bss_end = .;
+
+    /* Stabs debugging sections.  */
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+
+    _end = .;
+}

bsp/imx6sx/cortex-a9/rtconfig.h

@@ -0,0 +1,194 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
+
+// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
+#define RT_NAME_MAX	6
+// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
+#define RT_ALIGN_SIZE	4
+// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
+// <item description="8">8</item>
+// <item description="32">32</item>
+// <item description="256">256</item>
+// </integer>
+#define RT_THREAD_PRIORITY_MAX	32
+// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="1000" />
+#define RT_TICK_PER_SECOND	1000
+// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
+#define IDLE_THREAD_STACK_SIZE	512
+// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
+#define RT_DEBUG
+// <integer name="RT_DEBUG_SCHEDULER" description="scheduler debug enable" default="0" />
+// #define RT_DEBUG_SCHEDULER  1
+// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
+#define RT_USING_OVERFLOW_CHECK
+// </section>
+
+// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
+#define RT_USING_HOOK
+// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
+// #define RT_USING_TIMER_SOFT
+// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
+#define RT_TIMER_THREAD_PRIO	4
+// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
+#define RT_TIMER_THREAD_STACK_SIZE	512
+// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
+#define RT_TIMER_TICK_PER_SECOND	10
+// </section>
+
+// <section name="IPC" description="Inter-Thread communication" default="always" >
+// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
+#define RT_USING_SEMAPHORE
+// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
+#define RT_USING_MUTEX
+// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
+#define RT_USING_EVENT
+// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
+#define RT_USING_MAILBOX
+// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
+#define RT_USING_MESSAGEQUEUE
+// </section>
+
+// <section name="MM" description="Memory Management" default="always" >
+// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
+#define RT_USING_MEMPOOL
+// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
+// #define RT_USING_MEMHEAP
+// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
+#define RT_USING_HEAP
+// <bool name="RT_USING_MEMHEAP_AS_HEAP" description="Using Memory Heap Object as system heap" default="true" />
+// #define RT_USING_MEMHEAP_AS_HEAP
+// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
+#define RT_USING_SMALL_MEM
+// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
+// #define RT_USING_SLAB
+// </section>
+
+// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
+#define RT_USING_DEVICE
+// <bool name="RT_USING_DEVICE_IPC" description="Using IPC in Device Driver Framework" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
+#define RT_USING_SERIAL
+// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
+#define RT_UART_RX_BUFFER_SIZE    64
+// <bool name="RT_USING_INTERRUPT_INFO" description="Using interrupt information description" default="true" />
+#define RT_USING_INTERRUPT_INFO
+// <bool name="RT_USING_UART0" description="Enable UART0" default="false" />
+// #define RT_USING_UART0
+// <bool name="RT_USING_UART1" description="Enable UART1" default="true" />
+#define RT_USING_UART1
+// </section>
+
+// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
+#define RT_USING_CONSOLE
+// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
+#define RT_CONSOLE_DEVICE_NAME	"uart1"
+// </section>
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
+#define RT_USING_FINSH
+// <bool name="FINSH_USING_MSH" description="Using module shell" default="true" />
+#define FINSH_USING_MSH
+// <bool name="FINSH_USING_MSH_DEFAULT" description="The default shell is msh" default="true" />
+#define FINSH_USING_MSH_DEFAULT
+// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
+#define FINSH_USING_SYMTAB
+// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
+#define FINSH_USING_DESCRIPTION
+// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
+#define FINSH_THREAD_STACK_SIZE	4096
+// </section>
+
+// <section name="LIBC" description="C Runtime library setting" default="always" >
+// <bool name="RT_USING_LIBC" description="Using libc library" default="true" />
+#define RT_USING_LIBC
+// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
+#define RT_USING_PTHREADS
+// </section>
+
+// <section name="RT_USING_DFS" description="Device file system" default="true" >
+// #define RT_USING_DFS
+// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
+#define DFS_USING_WORKDIR
+// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
+#define DFS_FILESYSTEMS_MAX	2
+// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
+#define DFS_FD_MAX	4
+// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
+// #define RT_USING_DFS_ELMFAT
+// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
+// <item description="LFN1">1</item>
+// <item description="LFN1">2</item>
+// </integer>
+#define RT_DFS_ELM_USE_LFN	1
+// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="256" />
+#define RT_DFS_ELM_MAX_LFN	64
+// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
+// #define RT_USING_DFS_YAFFS2
+// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
+// #define RT_USING_DFS_UFFS
+// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
+#define RT_USING_DFS_DEVFS
+// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
+// #define RT_USING_DFS_NFS
+// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
+#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
+// </section>
+
+// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
+#define RT_USING_LWIP
+// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
+#define RT_LWIP_ICMP
+// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
+// #define RT_LWIP_IGMP
+// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
+#define RT_LWIP_UDP
+// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
+#define RT_LWIP_TCP
+// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
+#define RT_LWIP_DNS
+// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
+// #define RT_LWIP_SNMP
+// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
+#define RT_LWIP_DHCP
+// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
+#define RT_LWIP_TCPTHREAD_PRIORITY	12
+// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE	8
+// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
+#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
+// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
+#define RT_LWIP_ETHTHREAD_PRIORITY	14
+// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE	8
+// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
+#define RT_LWIP_ETHTHREAD_STACKSIZE	512
+// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
+// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
+// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+// </section>
+
+#define RT_USING_LOGTRACE
+
+// </RDTConfigurator>
+
+#endif

bsp/imx6sx/cortex-a9/rtconfig.py

@@ -0,0 +1,102 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='i.mx6'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM 	= 'gcc'
+    # EXEC_PATH 	= r'/opt/arm-2012.09/bin'
+    EXEC_PATH   = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
+elif CROSS_TOOL == 'keil':
+    PLATFORM 	= 'armcc'
+    EXEC_PATH 	= 'C:/Keil'
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp'
+    CFLAGS = DEVICE + ' -Wall'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LINK_SCRIPT = 'imx6.lds'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-imx6.map,-cref,-u,system_vectors'+\
+                      ' -T %s' % LINK_SCRIPT
+
+    CPATH = ''
+    LPATH = ''
+
+    # generate debug info in all cases
+    AFLAGS += ' -gdwarf-2'
+    CFLAGS += ' -g -gdwarf-2'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
+                  SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMP'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imx6.map --scatter imx6.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = ' --cpu DARMP'
+
+    CFLAGS = ''
+    AFLAGS = ''
+    LFLAGS = ' --config imx6.icf'
+
+    EXEC_PATH += '/arm/bin/'
+    RT_USING_MINILIBC = False
+    POST_ACTION = ''

bsp/imx6sx/iMX6_Platform_SDK/Doxyfile

@@ -0,0 +1,1924 @@
+# Doxyfile 1.8.3.1
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project
+#
+# All text after a hash (#) is considered a comment and will be ignored
+# The format is:
+#       TAG = value [value, ...]
+# For lists items can also be appended using:
+#       TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (" ")
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file 
+# that follow. The default is UTF-8 which is also the encoding used for all 
+# text before the first occurrence of this tag. Doxygen uses libiconv (or the 
+# iconv built into libc) for the transcoding. See 
+# http://www.gnu.org/software/libiconv for the list of possible encodings.
+
+DOXYFILE_ENCODING      = UTF-8
+
+# The PROJECT_NAME tag is a single word (or sequence of words) that should 
+# identify the project. Note that if you do not use Doxywizard you need 
+# to put quotes around the project name if it contains spaces.
+
+PROJECT_NAME           = "Platform SDK"
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number. 
+# This could be handy for archiving the generated documentation or 
+# if some version control system is used.
+
+PROJECT_NUMBER         = 1.0
+
+# Using the PROJECT_BRIEF tag one can provide an optional one line description 
+# for a project that appears at the top of each page and should give viewer 
+# a quick idea about the purpose of the project. Keep the description short.
+
+PROJECT_BRIEF          = "Freescale SoC SDK"
+
+# With the PROJECT_LOGO tag one can specify an logo or icon that is 
+# included in the documentation. The maximum height of the logo should not 
+# exceed 55 pixels and the maximum width should not exceed 200 pixels. 
+# Doxygen will copy the logo to the output directory.
+
+PROJECT_LOGO           = tools/doxygen_config/Freescale25.png
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) 
+# base path where the generated documentation will be put. 
+# If a relative path is entered, it will be relative to the location 
+# where doxygen was started. If left blank the current directory will be used.
+
+OUTPUT_DIRECTORY       = doc
+
+# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 
+# 4096 sub-directories (in 2 levels) under the output directory of each output 
+# format and will distribute the generated files over these directories. 
+# Enabling this option can be useful when feeding doxygen a huge amount of 
+# source files, where putting all generated files in the same directory would 
+# otherwise cause performance problems for the file system.
+
+CREATE_SUBDIRS         = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all 
+# documentation generated by doxygen is written. Doxygen will use this 
+# information to generate all constant output in the proper language. 
+# The default language is English, other supported languages are: 
+# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, 
+# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, 
+# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English 
+# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, 
+# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak, 
+# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
+
+OUTPUT_LANGUAGE        = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will 
+# include brief member descriptions after the members that are listed in 
+# the file and class documentation (similar to JavaDoc). 
+# Set to NO to disable this.
+
+BRIEF_MEMBER_DESC      = YES
+
+# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend 
+# the brief description of a member or function before the detailed description. 
+# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the 
+# brief descriptions will be completely suppressed.
+
+REPEAT_BRIEF           = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator 
+# that is used to form the text in various listings. Each string 
+# in this list, if found as the leading text of the brief description, will be 
+# stripped from the text and the result after processing the whole list, is 
+# used as the annotated text. Otherwise, the brief description is used as-is. 
+# If left blank, the following values are used ("$name" is automatically 
+# replaced with the name of the entity): "The $name class" "The $name widget" 
+# "The $name file" "is" "provides" "specifies" "contains" 
+# "represents" "a" "an" "the"
+
+ABBREVIATE_BRIEF       = "The $name class" \
+                         "The $name widget" \
+                         "The $name file" \
+                         is \
+                         provides \
+                         specifies \
+                         contains \
+                         represents \
+                         a \
+                         an \
+                         the
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then 
+# Doxygen will generate a detailed section even if there is only a brief 
+# description.
+
+ALWAYS_DETAILED_SEC    = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all 
+# inherited members of a class in the documentation of that class as if those 
+# members were ordinary class members. Constructors, destructors and assignment 
+# operators of the base classes will not be shown.
+
+INLINE_INHERITED_MEMB  = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full 
+# path before files name in the file list and in the header files. If set 
+# to NO the shortest path that makes the file name unique will be used.
+
+FULL_PATH_NAMES        = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag 
+# can be used to strip a user-defined part of the path. Stripping is 
+# only done if one of the specified strings matches the left-hand part of 
+# the path. The tag can be used to show relative paths in the file list. 
+# If left blank the directory from which doxygen is run is used as the 
+# path to strip. Note that you specify absolute paths here, but also 
+# relative paths, which will be relative from the directory where doxygen is 
+# started.
+
+STRIP_FROM_PATH        = 
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of 
+# the path mentioned in the documentation of a class, which tells 
+# the reader which header file to include in order to use a class. 
+# If left blank only the name of the header file containing the class 
+# definition is used. Otherwise one should specify the include paths that 
+# are normally passed to the compiler using the -I flag.
+
+STRIP_FROM_INC_PATH    = 
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter 
+# (but less readable) file names. This can be useful if your file system 
+# doesn't support long names like on DOS, Mac, or CD-ROM.
+
+SHORT_NAMES            = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen 
+# will interpret the first line (until the first dot) of a JavaDoc-style 
+# comment as the brief description. If set to NO, the JavaDoc 
+# comments will behave just like regular Qt-style comments 
+# (thus requiring an explicit @brief command for a brief description.)
+
+JAVADOC_AUTOBRIEF      = NO
+
+# If the QT_AUTOBRIEF tag is set to YES then Doxygen will 
+# interpret the first line (until the first dot) of a Qt-style 
+# comment as the brief description. If set to NO, the comments 
+# will behave just like regular Qt-style comments (thus requiring 
+# an explicit \brief command for a brief description.)
+
+QT_AUTOBRIEF           = NO
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen 
+# treat a multi-line C++ special comment block (i.e. a block of //! or /// 
+# comments) as a brief description. This used to be the default behaviour. 
+# The new default is to treat a multi-line C++ comment block as a detailed 
+# description. Set this tag to YES if you prefer the old behaviour instead.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented 
+# member inherits the documentation from any documented member that it 
+# re-implements.
+
+INHERIT_DOCS           = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce 
+# a new page for each member. If set to NO, the documentation of a member will 
+# be part of the file/class/namespace that contains it.
+
+SEPARATE_MEMBER_PAGES  = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab. 
+# Doxygen uses this value to replace tabs by spaces in code fragments.
+
+TAB_SIZE               = 4
+
+# This tag can be used to specify a number of aliases that acts 
+# as commands in the documentation. An alias has the form "name=value". 
+# For example adding "sideeffect=\par Side Effects:\n" will allow you to 
+# put the command \sideeffect (or @sideeffect) in the documentation, which 
+# will result in a user-defined paragraph with heading "Side Effects:". 
+# You can put \n's in the value part of an alias to insert newlines.
+
+ALIASES                = 
+
+# This tag can be used to specify a number of word-keyword mappings (TCL only). 
+# A mapping has the form "name=value". For example adding 
+# "class=itcl::class" will allow you to use the command class in the 
+# itcl::class meaning.
+
+TCL_SUBST              = 
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C 
+# sources only. Doxygen will then generate output that is more tailored for C. 
+# For instance, some of the names that are used will be different. The list 
+# of all members will be omitted, etc.
+
+OPTIMIZE_OUTPUT_FOR_C  = YES
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java 
+# sources only. Doxygen will then generate output that is more tailored for 
+# Java. For instance, namespaces will be presented as packages, qualified 
+# scopes will look different, etc.
+
+OPTIMIZE_OUTPUT_JAVA   = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran 
+# sources only. Doxygen will then generate output that is more tailored for 
+# Fortran.
+
+OPTIMIZE_FOR_FORTRAN   = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL 
+# sources. Doxygen will then generate output that is tailored for 
+# VHDL.
+
+OPTIMIZE_OUTPUT_VHDL   = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it 
+# parses. With this tag you can assign which parser to use for a given 
+# extension. Doxygen has a built-in mapping, but you can override or extend it 
+# using this tag. The format is ext=language, where ext is a file extension, 
+# and language is one of the parsers supported by doxygen: IDL, Java, 
+# Javascript, CSharp, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, 
+# C++. For instance to make doxygen treat .inc files as Fortran files (default 
+# is PHP), and .f files as C (default is Fortran), use: inc=Fortran f=C. Note 
+# that for custom extensions you also need to set FILE_PATTERNS otherwise the 
+# files are not read by doxygen.
+
+EXTENSION_MAPPING      = 
+
+# If MARKDOWN_SUPPORT is enabled (the default) then doxygen pre-processes all 
+# comments according to the Markdown format, which allows for more readable 
+# documentation. See http://daringfireball.net/projects/markdown/ for details. 
+# The output of markdown processing is further processed by doxygen, so you 
+# can mix doxygen, HTML, and XML commands with Markdown formatting. 
+# Disable only in case of backward compatibilities issues.
+
+MARKDOWN_SUPPORT       = YES
+
+# When enabled doxygen tries to link words that correspond to documented classes, 
+# or namespaces to their corresponding documentation. Such a link can be 
+# prevented in individual cases by by putting a % sign in front of the word or 
+# globally by setting AUTOLINK_SUPPORT to NO.
+
+AUTOLINK_SUPPORT       = YES
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want 
+# to include (a tag file for) the STL sources as input, then you should 
+# set this tag to YES in order to let doxygen match functions declarations and 
+# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. 
+# func(std::string) {}). This also makes the inheritance and collaboration 
+# diagrams that involve STL classes more complete and accurate.
+
+BUILTIN_STL_SUPPORT    = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to 
+# enable parsing support.
+
+CPP_CLI_SUPPORT        = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. 
+# Doxygen will parse them like normal C++ but will assume all classes use public 
+# instead of private inheritance when no explicit protection keyword is present.
+
+SIP_SUPPORT            = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate 
+# getter and setter methods for a property. Setting this option to YES (the 
+# default) will make doxygen replace the get and set methods by a property in 
+# the documentation. This will only work if the methods are indeed getting or 
+# setting a simple type. If this is not the case, or you want to show the 
+# methods anyway, you should set this option to NO.
+
+IDL_PROPERTY_SUPPORT   = NO
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC 
+# tag is set to YES, then doxygen will reuse the documentation of the first 
+# member in the group (if any) for the other members of the group. By default 
+# all members of a group must be documented explicitly.
+
+DISTRIBUTE_GROUP_DOC   = NO
+
+# Set the SUBGROUPING tag to YES (the default) to allow class member groups of 
+# the same type (for instance a group of public functions) to be put as a 
+# subgroup of that type (e.g. under the Public Functions section). Set it to 
+# NO to prevent subgrouping. Alternatively, this can be done per class using 
+# the \nosubgrouping command.
+
+SUBGROUPING            = YES
+
+# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and 
+# unions are shown inside the group in which they are included (e.g. using 
+# @ingroup) instead of on a separate page (for HTML and Man pages) or 
+# section (for LaTeX and RTF).
+
+INLINE_GROUPED_CLASSES = NO
+
+# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and 
+# unions with only public data fields will be shown inline in the documentation 
+# of the scope in which they are defined (i.e. file, namespace, or group 
+# documentation), provided this scope is documented. If set to NO (the default), 
+# structs, classes, and unions are shown on a separate page (for HTML and Man 
+# pages) or section (for LaTeX and RTF).
+
+INLINE_SIMPLE_STRUCTS  = YES
+
+# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum 
+# is documented as struct, union, or enum with the name of the typedef. So 
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct 
+# with name TypeT. When disabled the typedef will appear as a member of a file, 
+# namespace, or class. And the struct will be named TypeS. This can typically 
+# be useful for C code in case the coding convention dictates that all compound 
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+
+TYPEDEF_HIDES_STRUCT   = YES
+
+# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to 
+# determine which symbols to keep in memory and which to flush to disk. 
+# When the cache is full, less often used symbols will be written to disk. 
+# For small to medium size projects (<1000 input files) the default value is 
+# probably good enough. For larger projects a too small cache size can cause 
+# doxygen to be busy swapping symbols to and from disk most of the time 
+# causing a significant performance penalty. 
+# If the system has enough physical memory increasing the cache will improve the 
+# performance by keeping more symbols in memory. Note that the value works on 
+# a logarithmic scale so increasing the size by one will roughly double the 
+# memory usage. The cache size is given by this formula: 
+# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, 
+# corresponding to a cache size of 2^16 = 65536 symbols.
+
+SYMBOL_CACHE_SIZE      = 0
+
+# Similar to the SYMBOL_CACHE_SIZE the size of the symbol lookup cache can be 
+# set using LOOKUP_CACHE_SIZE. This cache is used to resolve symbols given 
+# their name and scope. Since this can be an expensive process and often the 
+# same symbol appear multiple times in the code, doxygen keeps a cache of 
+# pre-resolved symbols. If the cache is too small doxygen will become slower. 
+# If the cache is too large, memory is wasted. The cache size is given by this 
+# formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range is 0..9, the default is 0, 
+# corresponding to a cache size of 2^16 = 65536 symbols.
+
+LOOKUP_CACHE_SIZE      = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in 
+# documentation are documented, even if no documentation was available. 
+# Private class members and static file members will be hidden unless 
+# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
+
+EXTRACT_ALL            = YES
+
+# If the EXTRACT_PRIVATE tag is set to YES all private members of a class 
+# will be included in the documentation.
+
+EXTRACT_PRIVATE        = YES
+
+# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal 
+# scope will be included in the documentation.
+
+EXTRACT_PACKAGE        = NO
+
+# If the EXTRACT_STATIC tag is set to YES all static members of a file 
+# will be included in the documentation.
+
+EXTRACT_STATIC         = YES
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) 
+# defined locally in source files will be included in the documentation. 
+# If set to NO only classes defined in header files are included.
+
+EXTRACT_LOCAL_CLASSES  = YES
+
+# This flag is only useful for Objective-C code. When set to YES local 
+# methods, which are defined in the implementation section but not in 
+# the interface are included in the documentation. 
+# If set to NO (the default) only methods in the interface are included.
+
+EXTRACT_LOCAL_METHODS  = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be 
+# extracted and appear in the documentation as a namespace called 
+# 'anonymous_namespace{file}', where file will be replaced with the base 
+# name of the file that contains the anonymous namespace. By default 
+# anonymous namespaces are hidden.
+
+EXTRACT_ANON_NSPACES   = NO
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all 
+# undocumented members of documented classes, files or namespaces. 
+# If set to NO (the default) these members will be included in the 
+# various overviews, but no documentation section is generated. 
+# This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_MEMBERS     = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all 
+# undocumented classes that are normally visible in the class hierarchy. 
+# If set to NO (the default) these classes will be included in the various 
+# overviews. This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_CLASSES     = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all 
+# friend (class|struct|union) declarations. 
+# If set to NO (the default) these declarations will be included in the 
+# documentation.
+
+HIDE_FRIEND_COMPOUNDS  = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any 
+# documentation blocks found inside the body of a function. 
+# If set to NO (the default) these blocks will be appended to the 
+# function's detailed documentation block.
+
+HIDE_IN_BODY_DOCS      = NO
+
+# The INTERNAL_DOCS tag determines if documentation 
+# that is typed after a \internal command is included. If the tag is set 
+# to NO (the default) then the documentation will be excluded. 
+# Set it to YES to include the internal documentation.
+
+INTERNAL_DOCS          = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate 
+# file names in lower-case letters. If set to YES upper-case letters are also 
+# allowed. This is useful if you have classes or files whose names only differ 
+# in case and if your file system supports case sensitive file names. Windows 
+# and Mac users are advised to set this option to NO.
+
+CASE_SENSE_NAMES       = NO
+
+# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen 
+# will show members with their full class and namespace scopes in the 
+# documentation. If set to YES the scope will be hidden.
+
+HIDE_SCOPE_NAMES       = NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen 
+# will put a list of the files that are included by a file in the documentation 
+# of that file.
+
+SHOW_INCLUDE_FILES     = YES
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen 
+# will list include files with double quotes in the documentation 
+# rather than with sharp brackets.
+
+FORCE_LOCAL_INCLUDES   = NO
+
+# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] 
+# is inserted in the documentation for inline members.
+
+INLINE_INFO            = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen 
+# will sort the (detailed) documentation of file and class members 
+# alphabetically by member name. If set to NO the members will appear in 
+# declaration order.
+
+SORT_MEMBER_DOCS       = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the 
+# brief documentation of file, namespace and class members alphabetically 
+# by member name. If set to NO (the default) the members will appear in 
+# declaration order.
+
+SORT_BRIEF_DOCS        = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen 
+# will sort the (brief and detailed) documentation of class members so that 
+# constructors and destructors are listed first. If set to NO (the default) 
+# the constructors will appear in the respective orders defined by 
+# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. 
+# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO 
+# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.
+
+SORT_MEMBERS_CTORS_1ST = YES
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the 
+# hierarchy of group names into alphabetical order. If set to NO (the default) 
+# the group names will appear in their defined order.
+
+SORT_GROUP_NAMES       = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be 
+# sorted by fully-qualified names, including namespaces. If set to 
+# NO (the default), the class list will be sorted only by class name, 
+# not including the namespace part. 
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. 
+# Note: This option applies only to the class list, not to the 
+# alphabetical list.
+
+SORT_BY_SCOPE_NAME     = NO
+
+# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to 
+# do proper type resolution of all parameters of a function it will reject a 
+# match between the prototype and the implementation of a member function even 
+# if there is only one candidate or it is obvious which candidate to choose 
+# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen 
+# will still accept a match between prototype and implementation in such cases.
+
+STRICT_PROTO_MATCHING  = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or 
+# disable (NO) the todo list. This list is created by putting \todo 
+# commands in the documentation.
+
+GENERATE_TODOLIST      = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or 
+# disable (NO) the test list. This list is created by putting \test 
+# commands in the documentation.
+
+GENERATE_TESTLIST      = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or 
+# disable (NO) the bug list. This list is created by putting \bug 
+# commands in the documentation.
+
+GENERATE_BUGLIST       = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or 
+# disable (NO) the deprecated list. This list is created by putting 
+# \deprecated commands in the documentation.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional 
+# documentation sections, marked by \if section-label ... \endif 
+# and \cond section-label ... \endcond blocks.
+
+ENABLED_SECTIONS       = 
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines 
+# the initial value of a variable or macro consists of for it to appear in 
+# the documentation. If the initializer consists of more lines than specified 
+# here it will be hidden. Use a value of 0 to hide initializers completely. 
+# The appearance of the initializer of individual variables and macros in the 
+# documentation can be controlled using \showinitializer or \hideinitializer 
+# command in the documentation regardless of this setting.
+
+MAX_INITIALIZER_LINES  = 1
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated 
+# at the bottom of the documentation of classes and structs. If set to YES the 
+# list will mention the files that were used to generate the documentation.
+
+SHOW_USED_FILES        = NO
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page. 
+# This will remove the Files entry from the Quick Index and from the 
+# Folder Tree View (if specified). The default is YES.
+
+SHOW_FILES             = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the 
+# Namespaces page.  This will remove the Namespaces entry from the Quick Index 
+# and from the Folder Tree View (if specified). The default is YES.
+
+SHOW_NAMESPACES        = NO
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that 
+# doxygen should invoke to get the current version for each file (typically from 
+# the version control system). Doxygen will invoke the program by executing (via 
+# popen()) the command <command> <input-file>, where <command> is the value of 
+# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file 
+# provided by doxygen. Whatever the program writes to standard output 
+# is used as the file version. See the manual for examples.
+
+FILE_VERSION_FILTER    = 
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed 
+# by doxygen. The layout file controls the global structure of the generated 
+# output files in an output format independent way. To create the layout file 
+# that represents doxygen's defaults, run doxygen with the -l option. 
+# You can optionally specify a file name after the option, if omitted 
+# DoxygenLayout.xml will be used as the name of the layout file.
+
+LAYOUT_FILE            = tools/doxygen_config/DoxygenLayout.xml
+
+# The CITE_BIB_FILES tag can be used to specify one or more bib files 
+# containing the references data. This must be a list of .bib files. The 
+# .bib extension is automatically appended if omitted. Using this command 
+# requires the bibtex tool to be installed. See also 
+# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style 
+# of the bibliography can be controlled using LATEX_BIB_STYLE. To use this 
+# feature you need bibtex and perl available in the search path. Do not use 
+# file names with spaces, bibtex cannot handle them.
+
+CITE_BIB_FILES         = 
+
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated 
+# by doxygen. Possible values are YES and NO. If left blank NO is used.
+
+QUIET                  = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are 
+# generated by doxygen. Possible values are YES and NO. If left blank 
+# NO is used.
+
+WARNINGS               = YES
+
+# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings 
+# for undocumented members. If EXTRACT_ALL is set to YES then this flag will 
+# automatically be disabled.
+
+WARN_IF_UNDOCUMENTED   = NO
+
+# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for 
+# potential errors in the documentation, such as not documenting some 
+# parameters in a documented function, or documenting parameters that 
+# don't exist or using markup commands wrongly.
+
+WARN_IF_DOC_ERROR      = YES
+
+# The WARN_NO_PARAMDOC option can be enabled to get warnings for 
+# functions that are documented, but have no documentation for their parameters 
+# or return value. If set to NO (the default) doxygen will only warn about 
+# wrong or incomplete parameter documentation, but not about the absence of 
+# documentation.
+
+WARN_NO_PARAMDOC       = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that 
+# doxygen can produce. The string should contain the $file, $line, and $text 
+# tags, which will be replaced by the file and line number from which the 
+# warning originated and the warning text. Optionally the format may contain 
+# $version, which will be replaced by the version of the file (if it could 
+# be obtained via FILE_VERSION_FILTER)
+
+WARN_FORMAT            = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning 
+# and error messages should be written. If left blank the output is written 
+# to stderr.
+
+WARN_LOGFILE           = 
+
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag can be used to specify the files and/or directories that contain 
+# documented source files. You may enter file names like "myfile.cpp" or 
+# directories like "/usr/src/myproject". Separate the files or directories 
+# with spaces.
+
+INPUT                  = sdk \
+                         sdk/common/filesystem/fat/cache_wrappers.c
+
+# This tag can be used to specify the character encoding of the source files 
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is 
+# also the default input encoding. Doxygen uses libiconv (or the iconv built 
+# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for 
+# the list of possible encodings.
+
+INPUT_ENCODING         = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the 
+# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp 
+# and *.h) to filter out the source-files in the directories. If left 
+# blank the following patterns are tested: 
+# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh 
+# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py 
+# *.f90 *.f *.for *.vhd *.vhdl
+
+FILE_PATTERNS          = *.c \
+                         *.cc \
+                         *.cxx \
+                         *.c++ \
+                         *.d \
+                         *.java \
+                         *.ii \
+                         *.ixx \
+                         *.ipp \
+                         *.i++ \
+                         *.inl \
+                         *.h \
+                         *.hh \
+                         *.hxx \
+                         *.hpp \
+                         *.h++ \
+                         *.idl \
+                         *.odl \
+                         *.cs \
+                         *.php \
+                         *.php3 \
+                         *.inc \
+                         *.m \
+                         *.mm \
+                         *.dox \
+                         *.py \
+                         *.f90 \
+                         *.f \
+                         *.for \
+                         *.vhd \
+                         *.vhdl
+
+# The RECURSIVE tag can be used to turn specify whether or not subdirectories 
+# should be searched for input files as well. Possible values are YES and NO. 
+# If left blank NO is used.
+
+RECURSIVE              = YES
+
+# The EXCLUDE tag can be used to specify files and/or directories that should be 
+# excluded from the INPUT source files. This way you can easily exclude a 
+# subdirectory from a directory tree whose root is specified with the INPUT tag. 
+# Note that relative paths are relative to the directory from which doxygen is 
+# run.
+
+EXCLUDE                = 
+
+# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or 
+# directories that are symbolic links (a Unix file system feature) are excluded 
+# from the input.
+
+EXCLUDE_SYMLINKS       = NO
+
+# If the value of the INPUT tag contains directories, you can use the 
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude 
+# certain files from those directories. Note that the wildcards are matched 
+# against the file with absolute path, so to exclude all test directories 
+# for example use the pattern */test/*
+
+EXCLUDE_PATTERNS       = */sdk/include/*/registers \
+                         */sdk/*/iomux/* \
+                         */test/* \
+                         texture*.* \
+                         ._* \
+                         */sdk/common/hdmi_transmitter \
+                         */sdk/common/profile \
+                         *perfmon* \
+                         rotate_texture.c \
+                         waveform_data.h \
+                         auo_lut.c \
+                         */src/* \
+                         hab*.h \
+                         io.h \
+                         sdma_script_code_mx53.h \
+                         */sdk/include/mx6dq \
+                         */sdk/include/mx6sdl \
+                         */sdk/include/mx6sl \
+                         */sdk/common/filesystem/fat \
+                         */sdk/common/filesystem/include \
+                         epdc_regs.h \
+                         lcdc_regs.h \
+                         pxp_regs.h \
+                         spdc_regs.h \
+                         */sdk/common/usb_stack
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names 
+# (namespaces, classes, functions, etc.) that should be excluded from the 
+# output. The symbol name can be a fully qualified name, a word, or if the 
+# wildcard * is used, a substring. Examples: ANamespace, AClass, 
+# AClass::ANamespace, ANamespace::*Test
+
+EXCLUDE_SYMBOLS        = 
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or 
+# directories that contain example code fragments that are included (see 
+# the \include command).
+
+EXAMPLE_PATH           = 
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the 
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp 
+# and *.h) to filter out the source-files in the directories. If left 
+# blank all files are included.
+
+EXAMPLE_PATTERNS       = *
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be 
+# searched for input files to be used with the \include or \dontinclude 
+# commands irrespective of the value of the RECURSIVE tag. 
+# Possible values are YES and NO. If left blank NO is used.
+
+EXAMPLE_RECURSIVE      = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or 
+# directories that contain image that are included in the documentation (see 
+# the \image command).
+
+IMAGE_PATH             = 
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should 
+# invoke to filter for each input file. Doxygen will invoke the filter program 
+# by executing (via popen()) the command <filter> <input-file>, where <filter> 
+# is the value of the INPUT_FILTER tag, and <input-file> is the name of an 
+# input file. Doxygen will then use the output that the filter program writes 
+# to standard output.  If FILTER_PATTERNS is specified, this tag will be 
+# ignored.
+
+INPUT_FILTER           = 
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern 
+# basis.  Doxygen will compare the file name with each pattern and apply the 
+# filter if there is a match.  The filters are a list of the form: 
+# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further 
+# info on how filters are used. If FILTER_PATTERNS is empty or if 
+# non of the patterns match the file name, INPUT_FILTER is applied.
+
+FILTER_PATTERNS        = 
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using 
+# INPUT_FILTER) will be used to filter the input files when producing source 
+# files to browse (i.e. when SOURCE_BROWSER is set to YES).
+
+FILTER_SOURCE_FILES    = NO
+
+# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file 
+# pattern. A pattern will override the setting for FILTER_PATTERN (if any) 
+# and it is also possible to disable source filtering for a specific pattern 
+# using *.ext= (so without naming a filter). This option only has effect when 
+# FILTER_SOURCE_FILES is enabled.
+
+FILTER_SOURCE_PATTERNS = 
+
+# If the USE_MD_FILE_AS_MAINPAGE tag refers to the name of a markdown file that 
+# is part of the input, its contents will be placed on the main page (index.html). 
+# This can be useful if you have a project on for instance GitHub and want reuse 
+# the introduction page also for the doxygen output.
+
+USE_MDFILE_AS_MAINPAGE = 
+
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will 
+# be generated. Documented entities will be cross-referenced with these sources. 
+# Note: To get rid of all source code in the generated output, make sure also 
+# VERBATIM_HEADERS is set to NO.
+
+SOURCE_BROWSER         = NO
+
+# Setting the INLINE_SOURCES tag to YES will include the body 
+# of functions and classes directly in the documentation.
+
+INLINE_SOURCES         = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct 
+# doxygen to hide any special comment blocks from generated source code 
+# fragments. Normal C, C++ and Fortran comments will always remain visible.
+
+STRIP_CODE_COMMENTS    = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES 
+# then for each documented function all documented 
+# functions referencing it will be listed.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES 
+# then for each documented function all documented entities 
+# called/used by that function will be listed.
+
+REFERENCES_RELATION    = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) 
+# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from 
+# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will 
+# link to the source code.  Otherwise they will link to the documentation.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code 
+# will point to the HTML generated by the htags(1) tool instead of doxygen 
+# built-in source browser. The htags tool is part of GNU's global source 
+# tagging system (see http://www.gnu.org/software/global/global.html). You 
+# will need version 4.8.6 or higher.
+
+USE_HTAGS              = NO
+
+# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen 
+# will generate a verbatim copy of the header file for each class for 
+# which an include is specified. Set to NO to disable this.
+
+VERBATIM_HEADERS       = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index 
+# of all compounds will be generated. Enable this if the project 
+# contains a lot of classes, structs, unions or interfaces.
+
+ALPHABETICAL_INDEX     = YES
+
+# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then 
+# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns 
+# in which this list will be split (can be a number in the range [1..20])
+
+COLS_IN_ALPHA_INDEX    = 5
+
+# In case all classes in a project start with a common prefix, all 
+# classes will be put under the same header in the alphabetical index. 
+# The IGNORE_PREFIX tag can be used to specify one or more prefixes that 
+# should be ignored while generating the index headers.
+
+IGNORE_PREFIX          = 
+
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES (the default) Doxygen will 
+# generate HTML output.
+
+GENERATE_HTML          = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. 
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be 
+# put in front of it. If left blank `html' will be used as the default path.
+
+HTML_OUTPUT            = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for 
+# each generated HTML page (for example: .htm,.php,.asp). If it is left blank 
+# doxygen will generate files with .html extension.
+
+HTML_FILE_EXTENSION    = .html
+
+# The HTML_HEADER tag can be used to specify a personal HTML header for 
+# each generated HTML page. If it is left blank doxygen will generate a 
+# standard header. Note that when using a custom header you are responsible  
+# for the proper inclusion of any scripts and style sheets that doxygen 
+# needs, which is dependent on the configuration options used. 
+# It is advised to generate a default header using "doxygen -w html 
+# header.html footer.html stylesheet.css YourConfigFile" and then modify 
+# that header. Note that the header is subject to change so you typically 
+# have to redo this when upgrading to a newer version of doxygen or when 
+# changing the value of configuration settings such as GENERATE_TREEVIEW!
+
+HTML_HEADER            = 
+
+# The HTML_FOOTER tag can be used to specify a personal HTML footer for 
+# each generated HTML page. If it is left blank doxygen will generate a 
+# standard footer.
+
+HTML_FOOTER            = 
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading 
+# style sheet that is used by each HTML page. It can be used to 
+# fine-tune the look of the HTML output. If left blank doxygen will 
+# generate a default style sheet. Note that it is recommended to use 
+# HTML_EXTRA_STYLESHEET instead of this one, as it is more robust and this 
+# tag will in the future become obsolete.
+
+HTML_STYLESHEET        = 
+
+# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional 
+# user-defined cascading style sheet that is included after the standard 
+# style sheets created by doxygen. Using this option one can overrule 
+# certain style aspects. This is preferred over using HTML_STYLESHEET 
+# since it does not replace the standard style sheet and is therefor more 
+# robust against future updates. Doxygen will copy the style sheet file to 
+# the output directory.
+
+HTML_EXTRA_STYLESHEET  = 
+
+# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or 
+# other source files which should be copied to the HTML output directory. Note 
+# that these files will be copied to the base HTML output directory. Use the 
+# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these 
+# files. In the HTML_STYLESHEET file, use the file name only. Also note that 
+# the files will be copied as-is; there are no commands or markers available.
+
+HTML_EXTRA_FILES       = 
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. 
+# Doxygen will adjust the colors in the style sheet and background images 
+# according to this color. Hue is specified as an angle on a colorwheel, 
+# see http://en.wikipedia.org/wiki/Hue for more information. 
+# For instance the value 0 represents red, 60 is yellow, 120 is green, 
+# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. 
+# The allowed range is 0 to 359.
+
+HTML_COLORSTYLE_HUE    = 220
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of 
+# the colors in the HTML output. For a value of 0 the output will use 
+# grayscales only. A value of 255 will produce the most vivid colors.
+
+HTML_COLORSTYLE_SAT    = 100
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to 
+# the luminance component of the colors in the HTML output. Values below 
+# 100 gradually make the output lighter, whereas values above 100 make 
+# the output darker. The value divided by 100 is the actual gamma applied, 
+# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, 
+# and 100 does not change the gamma.
+
+HTML_COLORSTYLE_GAMMA  = 80
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML 
+# page will contain the date and time when the page was generated. Setting 
+# this to NO can help when comparing the output of multiple runs.
+
+HTML_TIMESTAMP         = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML 
+# documentation will contain sections that can be hidden and shown after the 
+# page has loaded.
+
+HTML_DYNAMIC_SECTIONS  = NO
+
+# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of 
+# entries shown in the various tree structured indices initially; the user 
+# can expand and collapse entries dynamically later on. Doxygen will expand 
+# the tree to such a level that at most the specified number of entries are 
+# visible (unless a fully collapsed tree already exceeds this amount). 
+# So setting the number of entries 1 will produce a full collapsed tree by 
+# default. 0 is a special value representing an infinite number of entries 
+# and will result in a full expanded tree by default.
+
+HTML_INDEX_NUM_ENTRIES = 100
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files 
+# will be generated that can be used as input for Apple's Xcode 3 
+# integrated development environment, introduced with OSX 10.5 (Leopard). 
+# To create a documentation set, doxygen will generate a Makefile in the 
+# HTML output directory. Running make will produce the docset in that 
+# directory and running "make install" will install the docset in 
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find 
+# it at startup. 
+# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html 
+# for more information.
+
+GENERATE_DOCSET        = NO
+
+# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the 
+# feed. A documentation feed provides an umbrella under which multiple 
+# documentation sets from a single provider (such as a company or product suite) 
+# can be grouped.
+
+DOCSET_FEEDNAME        = "Doxygen generated docs"
+
+# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that 
+# should uniquely identify the documentation set bundle. This should be a 
+# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen 
+# will append .docset to the name.
+
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+
+# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely 
+# identify the documentation publisher. This should be a reverse domain-name 
+# style string, e.g. com.mycompany.MyDocSet.documentation.
+
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+
+# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.
+
+DOCSET_PUBLISHER_NAME  = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES, additional index files 
+# will be generated that can be used as input for tools like the 
+# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) 
+# of the generated HTML documentation.
+
+GENERATE_HTMLHELP      = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can 
+# be used to specify the file name of the resulting .chm file. You 
+# can add a path in front of the file if the result should not be 
+# written to the html output directory.
+
+CHM_FILE               = 
+
+# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can 
+# be used to specify the location (absolute path including file name) of 
+# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run 
+# the HTML help compiler on the generated index.hhp.
+
+HHC_LOCATION           = 
+
+# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag 
+# controls if a separate .chi index file is generated (YES) or that 
+# it should be included in the master .chm file (NO).
+
+GENERATE_CHI           = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING 
+# is used to encode HtmlHelp index (hhk), content (hhc) and project file 
+# content.
+
+CHM_INDEX_ENCODING     = 
+
+# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag 
+# controls whether a binary table of contents is generated (YES) or a 
+# normal table of contents (NO) in the .chm file.
+
+BINARY_TOC             = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members 
+# to the contents of the HTML help documentation and to the tree view.
+
+TOC_EXPAND             = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and 
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated 
+# that can be used as input for Qt's qhelpgenerator to generate a 
+# Qt Compressed Help (.qch) of the generated HTML documentation.
+
+GENERATE_QHP           = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can 
+# be used to specify the file name of the resulting .qch file. 
+# The path specified is relative to the HTML output folder.
+
+QCH_FILE               = 
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating 
+# Qt Help Project output. For more information please see 
+# http://doc.trolltech.com/qthelpproject.html#namespace
+
+QHP_NAMESPACE          = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating 
+# Qt Help Project output. For more information please see 
+# http://doc.trolltech.com/qthelpproject.html#virtual-folders
+
+QHP_VIRTUAL_FOLDER     = doc
+
+# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to 
+# add. For more information please see 
+# http://doc.trolltech.com/qthelpproject.html#custom-filters
+
+QHP_CUST_FILTER_NAME   = 
+
+# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the 
+# custom filter to add. For more information please see 
+# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters"> 
+# Qt Help Project / Custom Filters</a>.
+
+QHP_CUST_FILTER_ATTRS  = 
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this 
+# project's 
+# filter section matches. 
+# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes"> 
+# Qt Help Project / Filter Attributes</a>.
+
+QHP_SECT_FILTER_ATTRS  = 
+
+# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can 
+# be used to specify the location of Qt's qhelpgenerator. 
+# If non-empty doxygen will try to run qhelpgenerator on the generated 
+# .qhp file.
+
+QHG_LOCATION           = 
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files  
+# will be generated, which together with the HTML files, form an Eclipse help 
+# plugin. To install this plugin and make it available under the help contents 
+# menu in Eclipse, the contents of the directory containing the HTML and XML 
+# files needs to be copied into the plugins directory of eclipse. The name of 
+# the directory within the plugins directory should be the same as 
+# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before 
+# the help appears.
+
+GENERATE_ECLIPSEHELP   = NO
+
+# A unique identifier for the eclipse help plugin. When installing the plugin 
+# the directory name containing the HTML and XML files should also have 
+# this name.
+
+ECLIPSE_DOC_ID         = org.doxygen.Project
+
+# The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) 
+# at top of each HTML page. The value NO (the default) enables the index and 
+# the value YES disables it. Since the tabs have the same information as the 
+# navigation tree you can set this option to NO if you already set 
+# GENERATE_TREEVIEW to YES.
+
+DISABLE_INDEX          = NO
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index 
+# structure should be generated to display hierarchical information. 
+# If the tag value is set to YES, a side panel will be generated 
+# containing a tree-like index structure (just like the one that 
+# is generated for HTML Help). For this to work a browser that supports 
+# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). 
+# Windows users are probably better off using the HTML help feature. 
+# Since the tree basically has the same information as the tab index you 
+# could consider to set DISABLE_INDEX to NO when enabling this option.
+
+GENERATE_TREEVIEW      = YES
+
+# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values 
+# (range [0,1..20]) that doxygen will group on one line in the generated HTML 
+# documentation. Note that a value of 0 will completely suppress the enum 
+# values from appearing in the overview section.
+
+ENUM_VALUES_PER_LINE   = 1
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be 
+# used to set the initial width (in pixels) of the frame in which the tree 
+# is shown.
+
+TREEVIEW_WIDTH         = 250
+
+# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open 
+# links to external symbols imported via tag files in a separate window.
+
+EXT_LINKS_IN_WINDOW    = NO
+
+# Use this tag to change the font size of Latex formulas included 
+# as images in the HTML documentation. The default is 10. Note that 
+# when you change the font size after a successful doxygen run you need 
+# to manually remove any form_*.png images from the HTML output directory 
+# to force them to be regenerated.
+
+FORMULA_FONTSIZE       = 10
+
+# Use the FORMULA_TRANPARENT tag to determine whether or not the images 
+# generated for formulas are transparent PNGs. Transparent PNGs are 
+# not supported properly for IE 6.0, but are supported on all modern browsers. 
+# Note that when changing this option you need to delete any form_*.png files 
+# in the HTML output before the changes have effect.
+
+FORMULA_TRANSPARENT    = YES
+
+# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax 
+# (see http://www.mathjax.org) which uses client side Javascript for the 
+# rendering instead of using prerendered bitmaps. Use this if you do not 
+# have LaTeX installed or if you want to formulas look prettier in the HTML 
+# output. When enabled you may also need to install MathJax separately and 
+# configure the path to it using the MATHJAX_RELPATH option.
+
+USE_MATHJAX            = NO
+
+# When MathJax is enabled you can set the default output format to be used for 
+# thA MathJax output. Supported types are HTML-CSS, NativeMML (i.e. MathML) and 
+# SVG. The default value is HTML-CSS, which is slower, but has the best 
+# compatibility.
+
+MATHJAX_FORMAT         = HTML-CSS
+
+# When MathJax is enabled you need to specify the location relative to the 
+# HTML output directory using the MATHJAX_RELPATH option. The destination 
+# directory should contain the MathJax.js script. For instance, if the mathjax 
+# directory is located at the same level as the HTML output directory, then 
+# MATHJAX_RELPATH should be ../mathjax. The default value points to 
+# the MathJax Content Delivery Network so you can quickly see the result without 
+# installing MathJax.  However, it is strongly recommended to install a local 
+# copy of MathJax from http://www.mathjax.org before deployment.
+
+MATHJAX_RELPATH        = http://www.mathjax.org/mathjax
+
+# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension 
+# names that should be enabled during MathJax rendering.
+
+MATHJAX_EXTENSIONS     = 
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box 
+# for the HTML output. The underlying search engine uses javascript 
+# and DHTML and should work on any modern browser. Note that when using 
+# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets 
+# (GENERATE_DOCSET) there is already a search function so this one should 
+# typically be disabled. For large projects the javascript based search engine 
+# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
+
+SEARCHENGINE           = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be 
+# implemented using a web server instead of a web client using Javascript. 
+# There are two flavours of web server based search depending on the 
+# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for 
+# searching and an index file used by the script. When EXTERNAL_SEARCH is 
+# enabled the indexing and searching needs to be provided by external tools. 
+# See the manual for details.
+
+SERVER_BASED_SEARCH    = NO
+
+# When EXTERNAL_SEARCH is enabled doxygen will no longer generate the PHP 
+# script for searching. Instead the search results are written to an XML file 
+# which needs to be processed by an external indexer. Doxygen will invoke an 
+# external search engine pointed to by the SEARCHENGINE_URL option to obtain 
+# the search results. Doxygen ships with an example indexer (doxyindexer) and 
+# search engine (doxysearch.cgi) which are based on the open source search engine 
+# library Xapian. See the manual for configuration details.
+
+EXTERNAL_SEARCH        = NO
+
+# The SEARCHENGINE_URL should point to a search engine hosted by a web server 
+# which will returned the search results when EXTERNAL_SEARCH is enabled. 
+# Doxygen ships with an example search engine (doxysearch) which is based on 
+# the open source search engine library Xapian. See the manual for configuration 
+# details.
+
+SEARCHENGINE_URL       = 
+
+# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed 
+# search data is written to a file for indexing by an external tool. With the 
+# SEARCHDATA_FILE tag the name of this file can be specified.
+
+SEARCHDATA_FILE        = searchdata.xml
+
+# When SERVER_BASED_SEARCH AND EXTERNAL_SEARCH are both enabled the 
+# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is 
+# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple 
+# projects and redirect the results back to the right project.
+
+EXTERNAL_SEARCH_ID     = 
+
+# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen 
+# projects other than the one defined by this configuration file, but that are 
+# all added to the same external search index. Each project needs to have a 
+# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id 
+# of to a relative location where the documentation can be found. 
+# The format is: EXTRA_SEARCH_MAPPINGS = id1=loc1 id2=loc2 ...
+
+EXTRA_SEARCH_MAPPINGS  = 
+
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will 
+# generate Latex output.
+
+GENERATE_LATEX         = NO
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. 
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be 
+# put in front of it. If left blank `latex' will be used as the default path.
+
+LATEX_OUTPUT           = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be 
+# invoked. If left blank `latex' will be used as the default command name. 
+# Note that when enabling USE_PDFLATEX this option is only used for 
+# generating bitmaps for formulas in the HTML output, but not in the 
+# Makefile that is written to the output directory.
+
+LATEX_CMD_NAME         = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to 
+# generate index for LaTeX. If left blank `makeindex' will be used as the 
+# default command name.
+
+MAKEINDEX_CMD_NAME     = makeindex
+
+# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact 
+# LaTeX documents. This may be useful for small projects and may help to 
+# save some trees in general.
+
+COMPACT_LATEX          = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used 
+# by the printer. Possible values are: a4, letter, legal and 
+# executive. If left blank a4wide will be used.
+
+PAPER_TYPE             = a4
+
+# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX 
+# packages that should be included in the LaTeX output.
+
+EXTRA_PACKAGES         = 
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for 
+# the generated latex document. The header should contain everything until 
+# the first chapter. If it is left blank doxygen will generate a 
+# standard header. Notice: only use this tag if you know what you are doing!
+
+LATEX_HEADER           = 
+
+# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for 
+# the generated latex document. The footer should contain everything after 
+# the last chapter. If it is left blank doxygen will generate a 
+# standard footer. Notice: only use this tag if you know what you are doing!
+
+LATEX_FOOTER           = 
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated 
+# is prepared for conversion to pdf (using ps2pdf). The pdf file will 
+# contain links (just like the HTML output) instead of page references 
+# This makes the output suitable for online browsing using a pdf viewer.
+
+PDF_HYPERLINKS         = YES
+
+# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of 
+# plain latex in the generated Makefile. Set this option to YES to get a 
+# higher quality PDF documentation.
+
+USE_PDFLATEX           = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. 
+# command to the generated LaTeX files. This will instruct LaTeX to keep 
+# running if errors occur, instead of asking the user for help. 
+# This option is also used when generating formulas in HTML.
+
+LATEX_BATCHMODE        = NO
+
+# If LATEX_HIDE_INDICES is set to YES then doxygen will not 
+# include the index chapters (such as File Index, Compound Index, etc.) 
+# in the output.
+
+LATEX_HIDE_INDICES     = NO
+
+# If LATEX_SOURCE_CODE is set to YES then doxygen will include 
+# source code with syntax highlighting in the LaTeX output. 
+# Note that which sources are shown also depends on other settings 
+# such as SOURCE_BROWSER.
+
+LATEX_SOURCE_CODE      = NO
+
+# The LATEX_BIB_STYLE tag can be used to specify the style to use for the 
+# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See 
+# http://en.wikipedia.org/wiki/BibTeX for more info.
+
+LATEX_BIB_STYLE        = plain
+
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output 
+# The RTF output is optimized for Word 97 and may not look very pretty with 
+# other RTF readers or editors.
+
+GENERATE_RTF           = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. 
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be 
+# put in front of it. If left blank `rtf' will be used as the default path.
+
+RTF_OUTPUT             = rtf
+
+# If the COMPACT_RTF tag is set to YES Doxygen generates more compact 
+# RTF documents. This may be useful for small projects and may help to 
+# save some trees in general.
+
+COMPACT_RTF            = YES
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated 
+# will contain hyperlink fields. The RTF file will 
+# contain links (just like the HTML output) instead of page references. 
+# This makes the output suitable for online browsing using WORD or other 
+# programs which support those fields. 
+# Note: wordpad (write) and others do not support links.
+
+RTF_HYPERLINKS         = NO
+
+# Load style sheet definitions from file. Syntax is similar to doxygen's 
+# config file, i.e. a series of assignments. You only have to provide 
+# replacements, missing definitions are set to their default value.
+
+RTF_STYLESHEET_FILE    = 
+
+# Set optional variables used in the generation of an rtf document. 
+# Syntax is similar to doxygen's config file.
+
+RTF_EXTENSIONS_FILE    = 
+
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES (the default) Doxygen will 
+# generate man pages
+
+GENERATE_MAN           = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put. 
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be 
+# put in front of it. If left blank `man' will be used as the default path.
+
+MAN_OUTPUT             = man
+
+# The MAN_EXTENSION tag determines the extension that is added to 
+# the generated man pages (default is the subroutine's section .3)
+
+MAN_EXTENSION          = .3
+
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output, 
+# then it will generate one additional man file for each entity 
+# documented in the real man page(s). These additional files 
+# only source the real man page, but without them the man command 
+# would be unable to find the correct page. The default is NO.
+
+MAN_LINKS              = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES Doxygen will 
+# generate an XML file that captures the structure of 
+# the code including all documentation.
+
+GENERATE_XML           = NO
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put. 
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be 
+# put in front of it. If left blank `xml' will be used as the default path.
+
+XML_OUTPUT             = xml
+
+# The XML_SCHEMA tag can be used to specify an XML schema, 
+# which can be used by a validating XML parser to check the 
+# syntax of the XML files.
+
+XML_SCHEMA             = 
+
+# The XML_DTD tag can be used to specify an XML DTD, 
+# which can be used by a validating XML parser to check the 
+# syntax of the XML files.
+
+XML_DTD                = 
+
+# If the XML_PROGRAMLISTING tag is set to YES Doxygen will 
+# dump the program listings (including syntax highlighting 
+# and cross-referencing information) to the XML output. Note that 
+# enabling this will significantly increase the size of the XML output.
+
+XML_PROGRAMLISTING     = YES
+
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will 
+# generate an AutoGen Definitions (see autogen.sf.net) file 
+# that captures the structure of the code including all 
+# documentation. Note that this feature is still experimental 
+# and incomplete at the moment.
+
+GENERATE_AUTOGEN_DEF   = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES Doxygen will 
+# generate a Perl module file that captures the structure of 
+# the code including all documentation. Note that this 
+# feature is still experimental and incomplete at the 
+# moment.
+
+GENERATE_PERLMOD       = NO
+
+# If the PERLMOD_LATEX tag is set to YES Doxygen will generate 
+# the necessary Makefile rules, Perl scripts and LaTeX code to be able 
+# to generate PDF and DVI output from the Perl module output.
+
+PERLMOD_LATEX          = NO
+
+# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be 
+# nicely formatted so it can be parsed by a human reader.  This is useful 
+# if you want to understand what is going on.  On the other hand, if this 
+# tag is set to NO the size of the Perl module output will be much smaller 
+# and Perl will parse it just the same.
+
+PERLMOD_PRETTY         = YES
+
+# The names of the make variables in the generated doxyrules.make file 
+# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. 
+# This is useful so different doxyrules.make files included by the same 
+# Makefile don't overwrite each other's variables.
+
+PERLMOD_MAKEVAR_PREFIX = 
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+
+# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will 
+# evaluate all C-preprocessor directives found in the sources and include 
+# files.
+
+ENABLE_PREPROCESSING   = YES
+
+# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro 
+# names in the source code. If set to NO (the default) only conditional 
+# compilation will be performed. Macro expansion can be done in a controlled 
+# way by setting EXPAND_ONLY_PREDEF to YES.
+
+MACRO_EXPANSION        = NO
+
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES 
+# then the macro expansion is limited to the macros specified with the 
+# PREDEFINED and EXPAND_AS_DEFINED tags.
+
+EXPAND_ONLY_PREDEF     = NO
+
+# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files 
+# pointed to by INCLUDE_PATH will be searched when a #include is found.
+
+SEARCH_INCLUDES        = YES
+
+# The INCLUDE_PATH tag can be used to specify one or more directories that 
+# contain include files that are not input files but should be processed by 
+# the preprocessor.
+
+INCLUDE_PATH           = 
+
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard 
+# patterns (like *.h and *.hpp) to filter out the header-files in the 
+# directories. If left blank, the patterns specified with FILE_PATTERNS will 
+# be used.
+
+INCLUDE_FILE_PATTERNS  = 
+
+# The PREDEFINED tag can be used to specify one or more macro names that 
+# are defined before the preprocessor is started (similar to the -D option of 
+# gcc). The argument of the tag is a list of macros of the form: name 
+# or name=definition (no spaces). If the definition and the = are 
+# omitted =1 is assumed. To prevent a macro definition from being 
+# undefined via #undef or recursively expanded use the := operator 
+# instead of the = operator.
+
+PREDEFINED             = 
+
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then 
+# this tag can be used to specify a list of macro names that should be expanded. 
+# The macro definition that is found in the sources will be used. 
+# Use the PREDEFINED tag if you want to use a different macro definition that 
+# overrules the definition found in the source code.
+
+EXPAND_AS_DEFINED      = 
+
+# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then 
+# doxygen's preprocessor will remove all references to function-like macros 
+# that are alone on a line, have an all uppercase name, and do not end with a 
+# semicolon, because these will confuse the parser if not removed.
+
+SKIP_FUNCTION_MACROS   = YES
+
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+
+# The TAGFILES option can be used to specify one or more tagfiles. For each 
+# tag file the location of the external documentation should be added. The 
+# format of a tag file without this location is as follows: 
+#   TAGFILES = file1 file2 ... 
+# Adding location for the tag files is done as follows: 
+#   TAGFILES = file1=loc1 "file2 = loc2" ... 
+# where "loc1" and "loc2" can be relative or absolute paths 
+# or URLs. Note that each tag file must have a unique name (where the name does 
+# NOT include the path). If a tag file is not located in the directory in which 
+# doxygen is run, you must also specify the path to the tagfile here.
+
+TAGFILES               = 
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create 
+# a tag file that is based on the input files it reads.
+
+GENERATE_TAGFILE       = 
+
+# If the ALLEXTERNALS tag is set to YES all external classes will be listed 
+# in the class index. If set to NO only the inherited external classes 
+# will be listed.
+
+ALLEXTERNALS           = NO
+
+# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed 
+# in the modules index. If set to NO, only the current project's groups will 
+# be listed.
+
+EXTERNAL_GROUPS        = YES
+
+# The PERL_PATH should be the absolute path and name of the perl script 
+# interpreter (i.e. the result of `which perl').
+
+PERL_PATH              = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+
+# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will 
+# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base 
+# or super classes. Setting the tag to NO turns the diagrams off. Note that 
+# this option also works with HAVE_DOT disabled, but it is recommended to 
+# install and use dot, since it yields more powerful graphs.
+
+CLASS_DIAGRAMS         = YES
+
+# You can define message sequence charts within doxygen comments using the \msc 
+# command. Doxygen will then run the mscgen tool (see 
+# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the 
+# documentation. The MSCGEN_PATH tag allows you to specify the directory where 
+# the mscgen tool resides. If left empty the tool is assumed to be found in the 
+# default search path.
+
+MSCGEN_PATH            = 
+
+# If set to YES, the inheritance and collaboration graphs will hide 
+# inheritance and usage relations if the target is undocumented 
+# or is not a class.
+
+HIDE_UNDOC_RELATIONS   = YES
+
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is 
+# available from the path. This tool is part of Graphviz, a graph visualization 
+# toolkit from AT&T and Lucent Bell Labs. The other options in this section 
+# have no effect if this option is set to NO (the default)
+
+HAVE_DOT               = NO
+
+# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is 
+# allowed to run in parallel. When set to 0 (the default) doxygen will 
+# base this on the number of processors available in the system. You can set it 
+# explicitly to a value larger than 0 to get control over the balance 
+# between CPU load and processing speed.
+
+DOT_NUM_THREADS        = 0
+
+# By default doxygen will use the Helvetica font for all dot files that 
+# doxygen generates. When you want a differently looking font you can specify 
+# the font name using DOT_FONTNAME. You need to make sure dot is able to find 
+# the font, which can be done by putting it in a standard location or by setting 
+# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the 
+# directory containing the font.
+
+DOT_FONTNAME           = Helvetica
+
+# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. 
+# The default size is 10pt.
+
+DOT_FONTSIZE           = 10
+
+# By default doxygen will tell dot to use the Helvetica font. 
+# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to 
+# set the path where dot can find it.
+
+DOT_FONTPATH           = 
+
+# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen 
+# will generate a graph for each documented class showing the direct and 
+# indirect inheritance relations. Setting this tag to YES will force the 
+# CLASS_DIAGRAMS tag to NO.
+
+CLASS_GRAPH            = YES
+
+# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen 
+# will generate a graph for each documented class showing the direct and 
+# indirect implementation dependencies (inheritance, containment, and 
+# class references variables) of the class with other documented classes.
+
+COLLABORATION_GRAPH    = YES
+
+# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen 
+# will generate a graph for groups, showing the direct groups dependencies
+
+GROUP_GRAPHS           = YES
+
+# If the UML_LOOK tag is set to YES doxygen will generate inheritance and 
+# collaboration diagrams in a style similar to the OMG's Unified Modeling 
+# Language.
+
+UML_LOOK               = NO
+
+# If the UML_LOOK tag is enabled, the fields and methods are shown inside 
+# the class node. If there are many fields or methods and many nodes the 
+# graph may become too big to be useful. The UML_LIMIT_NUM_FIELDS 
+# threshold limits the number of items for each type to make the size more 
+# managable. Set this to 0 for no limit. Note that the threshold may be 
+# exceeded by 50% before the limit is enforced.
+
+UML_LIMIT_NUM_FIELDS   = 10
+
+# If set to YES, the inheritance and collaboration graphs will show the 
+# relations between templates and their instances.
+
+TEMPLATE_RELATIONS     = NO
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT 
+# tags are set to YES then doxygen will generate a graph for each documented 
+# file showing the direct and indirect include dependencies of the file with 
+# other documented files.
+
+INCLUDE_GRAPH          = YES
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and 
+# HAVE_DOT tags are set to YES then doxygen will generate a graph for each 
+# documented header file showing the documented files that directly or 
+# indirectly include this file.
+
+INCLUDED_BY_GRAPH      = YES
+
+# If the CALL_GRAPH and HAVE_DOT options are set to YES then 
+# doxygen will generate a call dependency graph for every global function 
+# or class method. Note that enabling this option will significantly increase 
+# the time of a run. So in most cases it will be better to enable call graphs 
+# for selected functions only using the \callgraph command.
+
+CALL_GRAPH             = NO
+
+# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then 
+# doxygen will generate a caller dependency graph for every global function 
+# or class method. Note that enabling this option will significantly increase 
+# the time of a run. So in most cases it will be better to enable caller 
+# graphs for selected functions only using the \callergraph command.
+
+CALLER_GRAPH           = NO
+
+# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen 
+# will generate a graphical hierarchy of all classes instead of a textual one.
+
+GRAPHICAL_HIERARCHY    = YES
+
+# If the DIRECTORY_GRAPH and HAVE_DOT tags are set to YES 
+# then doxygen will show the dependencies a directory has on other directories 
+# in a graphical way. The dependency relations are determined by the #include 
+# relations between the files in the directories.
+
+DIRECTORY_GRAPH        = NO
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images 
+# generated by dot. Possible values are svg, png, jpg, or gif. 
+# If left blank png will be used. If you choose svg you need to set 
+# HTML_FILE_EXTENSION to xhtml in order to make the SVG files 
+# visible in IE 9+ (other browsers do not have this requirement).
+
+DOT_IMAGE_FORMAT       = png
+
+# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to 
+# enable generation of interactive SVG images that allow zooming and panning. 
+# Note that this requires a modern browser other than Internet Explorer. 
+# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you 
+# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files 
+# visible. Older versions of IE do not have SVG support.
+
+INTERACTIVE_SVG        = NO
+
+# The tag DOT_PATH can be used to specify the path where the dot tool can be 
+# found. If left blank, it is assumed the dot tool can be found in the path.
+
+DOT_PATH               = /usr/local/bin/dot
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that 
+# contain dot files that are included in the documentation (see the 
+# \dotfile command).
+
+DOTFILE_DIRS           = 
+
+# The MSCFILE_DIRS tag can be used to specify one or more directories that 
+# contain msc files that are included in the documentation (see the 
+# \mscfile command).
+
+MSCFILE_DIRS           = 
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of 
+# nodes that will be shown in the graph. If the number of nodes in a graph 
+# becomes larger than this value, doxygen will truncate the graph, which is 
+# visualized by representing a node as a red box. Note that doxygen if the 
+# number of direct children of the root node in a graph is already larger than 
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note 
+# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+
+DOT_GRAPH_MAX_NODES    = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the 
+# graphs generated by dot. A depth value of 3 means that only nodes reachable 
+# from the root by following a path via at most 3 edges will be shown. Nodes 
+# that lay further from the root node will be omitted. Note that setting this 
+# option to 1 or 2 may greatly reduce the computation time needed for large 
+# code bases. Also note that the size of a graph can be further restricted by 
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+
+MAX_DOT_GRAPH_DEPTH    = 0
+
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent 
+# background. This is disabled by default, because dot on Windows does not 
+# seem to support this out of the box. Warning: Depending on the platform used, 
+# enabling this option may lead to badly anti-aliased labels on the edges of 
+# a graph (i.e. they become hard to read).
+
+DOT_TRANSPARENT        = NO
+
+# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output 
+# files in one run (i.e. multiple -o and -T options on the command line). This 
+# makes dot run faster, but since only newer versions of dot (>1.8.10) 
+# support this, this feature is disabled by default.
+
+DOT_MULTI_TARGETS      = YES
+
+# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will 
+# generate a legend page explaining the meaning of the various boxes and 
+# arrows in the dot generated graphs.
+
+GENERATE_LEGEND        = YES
+
+# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will 
+# remove the intermediate dot files that are used to generate 
+# the various graphs.
+
+DOT_CLEANUP            = YES

bsp/imx6sx/iMX6_Platform_SDK/LICENSE.txt

@@ -0,0 +1,24 @@
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+o Redistributions of source code must retain the above copyright notice, this list
+  of conditions and the following disclaimer.
+
+o Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+
+o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+  contributors may be used to endorse or promote products derived from this
+  software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

bsp/imx6sx/iMX6_Platform_SDK/Makefile

@@ -0,0 +1,167 @@
+#-------------------------------------------------------------------------------
+# Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+#
+# THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+# SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+# OF SUCH DAMAGE.
+#-------------------------------------------------------------------------------
+
+#
+# Top-level Makefile.
+#
+# This file is responsible for building all libraries and applications.
+#
+# Targets:
+#  - all
+#  - sdk
+#  - board
+#  - sdk_unit_test
+#  - power_modes_test
+#  - obds
+#  - gpu_demo
+#  - smp_primes
+#  - stream
+#  - usb_hid_mouse
+#  - httpd
+#  - ping
+#  - clean
+#  - clean_sdk
+#  - clean_board
+#  - clean_sdk_unit_test
+#  - clean_power_modes_test
+#  - clean_obds
+#  - clean_gpu_demo
+#  - clean_smp_primes
+#  - clean_stream
+#  - clean_usb_hid_mouse
+#  - clean_httpd
+#  - clean_ping
+#
+# The clean targets work with any combination of configuration variables. For
+# example, clean_sdk with TARGET set will clean libsdk for only that TARGET, while
+# clean_sdk without TARGET set will clean libsdk in all targets.
+#
+
+include mk/common.mk
+
+# Turn off parallel jobs for this makefile only. Child makefiles will still use the
+# specified number of jobs. This isn't strictly necessary, and actually slows the build
+# a little bit, but greatly improves the readability of the log output.
+.NOTPARALLEL:
+
+# Determine if the target is either the MX6DQ or MX6SDL.
+ifeq "$(TARGET)" "mx6dq"
+is_dq_or_sdl = 1
+else ifeq "$(TARGET)" "mx6sdl"
+is_dq_or_sdl = 1
+endif
+
+# Library subdirectories that the apps depend upon. Handled automatically by targets.mk.
+SUBDIRS = \
+    sdk \
+    lwip \
+    $(BOARD_ROOT)
+
+# List of all applications to build. Applications must reside in the apps directory.
+ALL_APPS = \
+    filesystem \
+    httpd \
+    obds \
+    ping \
+    power_modes_test \
+    sdk_unit_test \
+    stream \
+    usb_hid_mouse
+
+# Apps that are only built for MX6DQ and MX6SDL.
+ifdef is_dq_or_sdl
+ALL_APPS += \
+    caam_blob_gen \
+    gpu_demo \
+    smp_primes
+endif
+
+# Default target.
+.PHONY: all
+all: $(sort $(ALL_APPS)) ;
+
+# App targets. All apps depend on the listed subdirectories.
+.PHONY: ALL_APPS
+$(ALL_APPS): $(SUBDIRS)
+	@$(call printmessage,build,Building, $@ ,gray,[$(TARGET) $(BOARD) $(BOARD_REVISION)],,\n)
+	@$(MAKE) $(silent_make) -r -C apps/$@
+
+# Print message before recursive into subdirs.
+$(SUBDIRS)::
+	@$(call printmessage,build,Building, $(@F) ,gray,[$(TARGET) $(BOARD) $(BOARD_REVISION)],,\n)
+
+# Target with a simple name for building the board package.
+.PHONY: board
+board: $(BOARD_ROOT)
+
+# Target to clean everything.
+.PHONY: clean
+clean:
+	@echo "Deleting output directory..."
+	@rm -rf output
+	@echo "done."
+
+# Target to clean just the sdk library and objects.
+.PHONY: clean_sdk
+clean_sdk:
+ifdef TARGET
+	rm -rf $(LIBSDK) $(OUTPUT_ROOT)/lib/obj/sdk
+else
+	rm -rf $(SDK_ROOT)/output/*/lib/libsdk.a $(SDK_ROOT)/output/*/lib/obj/sdk
+endif
+
+# Target to clean the board library and objects.
+.PHONY: clean_board
+clean_board:
+ifdef TARGET
+ ifdef BOARD
+	rm -rf $(LIBBOARD) $(OUTPUT_ROOT)/lib/obj/board_$(BOARD_WITH_REV)
+ else
+	rm -rf $(OUTPUT_ROOT)/lib/libboard* $(OUTPUT_ROOT)/lib/obj/board_*
+ endif
+else
+	rm -rf $(SDK_ROOT)/output/*/lib/libboard* $(SDK_ROOT)/output/*/lib/obj/board_*
+endif
+
+# Set up targets to clean each of the applications. For an app "foo", the target to clean
+# just that app is "clean_foo". If no TARGET is passed to make, the app is cleaned
+# for all targets.
+ALL_APP_CLEAN_TARGETS := $(addprefix clean_,$(ALL_APPS))
+.PHONY: $(ALL_APP_CLEAN_TARGETS)
+$(ALL_APP_CLEAN_TARGETS):
+ifdef TARGET
+ ifdef BOARD
+  ifdef BOARD_REVISION
+   ifdef BOARD_REVISION_IS_DEFAULT
+# Clean all revs of the board.
+	rm -rf $(OUTPUT_ROOT)/$(patsubst clean_%,%,$@)/$(BOARD)_rev_*
+   else
+# Specific rev specified so clean just that one rev.
+	rm -rf $(OUTPUT_ROOT)/$(patsubst clean_%,%,$@)/$(BOARD_WITH_REV)
+   endif
+  else
+# Clean all revs of the board.
+	rm -rf $(OUTPUT_ROOT)/$(patsubst clean_%,%,$@)/$(BOARD)_rev_*
+  endif
+ else
+# Clean all boards of the app.
+	rm -rf $(OUTPUT_ROOT)/$(patsubst clean_%,%,$@)
+ endif
+else
+# Clean all boards and targets of the app.
+	rm -rf $(SDK_ROOT)/output/*/$(patsubst clean_%,%,$@)
+endif
+
+include mk/targets.mk

bsp/imx6sx/iMX6_Platform_SDK/SConscript

@@ -0,0 +1,123 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+# sdk/utility/src/runtime_support.c
+# sdk/drivers/keypad/src/keypad_port.c
+# sdk/drivers/snvs/src/snvs.c
+# sdk/core/src/interrupt.c
+
+src = Split('''
+board/common/board_network.c
+board/common/board_io_expanders.c
+board/common/hardware_modules.c
+apps/common/platform_init.c
+apps/common/print_version.c
+sdk/utility/src/sdk_version.c
+sdk/utility/src/text_color.c
+sdk/utility/src/menu.c
+sdk/utility/src/spinlock.c
+sdk/utility/src/system_util.c
+sdk/core/src/ccm_pll.c
+sdk/core/src/abort_handler.c
+sdk/core/src/mmu.c
+sdk/core/src/armv7_cache.c
+sdk/core/src/gic.c
+sdk/common/ioexpander/src/max7310.c
+sdk/common/pmic/pfuse/pf0100.c
+sdk/common/profile/profile.c
+sdk/drivers/hdmi/src/hdmi_tx.c
+sdk/drivers/hdmi/src/hdmi_tx_audio.c
+sdk/drivers/hdmi/src/hdmi_common.c
+sdk/drivers/hdmi/src/hdmi_tx_phy.c
+sdk/drivers/vdoa/src/vdoa.c
+sdk/drivers/i2c/src/software_i2c_port.cpp
+sdk/drivers/i2c/src/imx_i2c_slave.c
+sdk/drivers/i2c/src/i2c_device.cpp
+sdk/drivers/i2c/src/imx_i2c.c
+sdk/drivers/pmu/src/pmu_driver.cpp
+sdk/drivers/sdma/src/sdma.c
+sdk/drivers/sdma/src/sdma_script_info.c
+sdk/drivers/eim/src/eim.c
+sdk/drivers/timer/src/epit.c
+sdk/drivers/timer/src/gpt.c
+sdk/drivers/timer/src/timer.c
+sdk/drivers/ipu/src/ipu_ic.c
+sdk/drivers/ipu/src/ips_disp_panel.c
+sdk/drivers/ipu/src/ipu_csi.c
+sdk/drivers/ipu/src/ipu_dmfc.c
+sdk/drivers/ipu/src/ipu_di.c
+sdk/drivers/ipu/src/ipu_vdi.c
+sdk/drivers/ipu/src/ipu_dc.c
+sdk/drivers/ipu/src/ipu_idmac.c
+sdk/drivers/ipu/src/ipu_dp.c
+sdk/drivers/ipu/src/ipu_common.c
+sdk/drivers/pcie/src/pcie_phy.c
+sdk/drivers/pcie/src/pcie.c
+sdk/drivers/pcie/src/pcie_prot.c
+sdk/drivers/gpio/src/gpio.c
+sdk/drivers/gpio/src/gpio_pin.cpp
+sdk/drivers/gpio/src/imx6sdl_gpio_map.c
+sdk/drivers/ocotp/src/ocotp.c
+sdk/drivers/usb/src/mx6x_usb.c
+sdk/drivers/usb/src/usb_common.c
+sdk/drivers/usb/src/usbd_drv.c
+sdk/drivers/usb/src/usbh_drv.c
+sdk/drivers/caam/src/caam.c
+sdk/drivers/uart/src/imx_uart.c
+sdk/drivers/enet/src/enet_drv.c
+sdk/drivers/tempmon/src/tempmon.c
+sdk/drivers/epdc/src/mxc_epdc.c
+sdk/drivers/cpu_utility/src/cpu_workpoint.c
+sdk/drivers/cpu_utility/src/cpu_multicore.c
+sdk/drivers/cpu_utility/src/cpu_get_cores.c
+sdk/drivers/gpmi/src/gpmi_dma_components.cpp
+sdk/drivers/gpmi/src/gpmi_dma_sequences.cpp
+sdk/drivers/gpmi/src/bch_ecc.c
+sdk/drivers/gpmi/src/gpmi_dma_isr.cpp
+sdk/drivers/gpmi/src/gpmi_nand_operations.cpp
+sdk/drivers/gpmi/src/gpmi.cpp
+sdk/drivers/board_id/src/board_id.c
+sdk/drivers/audio/src/imx_esai.c
+sdk/drivers/audio/src/snd_card.c
+sdk/drivers/audio/src/wm8958_dac.c
+sdk/drivers/audio/src/imx-ssi.c
+sdk/drivers/audio/src/imx_audmux.c
+sdk/drivers/audio/src/sgtl5000.c
+sdk/drivers/audio/src/imx_spdif.c
+sdk/drivers/audio/src/cs42888.c
+sdk/drivers/audio/src/wm8962.c
+sdk/drivers/ldb/src/ldb.c
+sdk/drivers/spi/src/ecspi.c
+sdk/drivers/spi/src/spi_device.cpp
+sdk/drivers/accelerometer/src/mma8451.c
+sdk/drivers/usdhc/src/usdhc_sd.c
+sdk/drivers/usdhc/src/usdhc_host.c
+sdk/drivers/usdhc/src/usdhc_mmc.c
+sdk/drivers/usdhc/src/usdhc.c
+sdk/drivers/pwm/src/pwm.c
+sdk/drivers/video/src/adv7180.c
+sdk/drivers/rtc/src/rtc.c
+sdk/drivers/rtc/src/srtc.c
+sdk/drivers/flexcan/src/can.c
+''')
+
+CPPPATH = [
+cwd + '/board/common',
+cwd + '/board/mx6sdl/sabre_ai',
+cwd + '/board/mx6sdl/sabre_ai/rev_b_iomux',
+cwd + '/sdk',
+cwd + '/sdk/common',
+cwd + '/sdk/core',
+cwd + '/sdk/drivers',
+cwd + '/sdk/utility',
+cwd + '/sdk/include',
+cwd + '/sdk/include/mx6sdl',
+cwd + '/sdk/include/mx6sdl/registers'
+]
+
+CPPDEFINES = ['CHIP_MX6SDL', 'BOARD_SABRE_AI', 'BOARD_REV_B']
+
+group = DefineGroup('PlatformSDK', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/imx6sx/iMX6_Platform_SDK/apps/common/basic_sdk_app.ld.S

@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+OUTPUT_FORMAT("elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+
+/*
+ * OCRAM
+ */
+#if defined(CHIP_MX6SDL) || defined(CHIP_MX6SL)
+    // mx6sl and mx6sdl both have 128kB of OCRAM.
+    #define OCRAM_LEN 128K
+#elif defined(CHIP_MX6DQ)
+    // mx6dq has 256kB of OCRAM
+    #define OCRAM_LEN 256K
+#else
+    #error Unknown chip!
+#endif
+
+/*
+ * External DDR
+ */
+#if defined(CHIP_MX6SL)
+    // mx6sl has only one DDR chip select that starts at a different address
+    #define DDR_ORG 0x80000000
+#elif defined(CHIP_MX6SDL) || defined(CHIP_MX6DQ)
+    // mx6dq and mx6sdl DDR memory starts at this address
+    #define DDR_ORG 0x10000000
+#else
+    #error Unknown chip!
+#endif
+
+#if defined(BOARD_SABRE_AI)
+    // mx6dq and mx6sdl sabre-ai board has 2GB of DDR3
+    #define DDR_LEN 2048M
+#else
+    // all other boards have 1GB of DDR3
+    #define DDR_LEN 1024M
+#endif
+
+// Maximum size of the signed image
+#if !defined(MAX_IMAGE_SIZE)
+#define MAX_IMAGE_SIZE 4M
+#endif
+
+// Maximum size of HAB CSF data
+#if !defined(MAX_HAB_CSF_DATA_SIZE)
+#define MAX_HAB_CSF_DATA_SIZE 8K
+#endif
+
+// Size of stacks section
+#if !defined(STACK_SIZE)
+#define STACK_SIZE 48K
+#endif
+
+// Size of the malloc heap, defaults to 128MB
+#if !defined(HEAP_SIZE)
+#define HEAP_SIZE 128M
+#endif
+
+// Size of the L1 page table.
+#define L1_PAGE_TABLE_SIZE 16K
+
+// Size of the RAM vectors table at the top of OCRAM.
+//
+// The vectors in ROM at address 0 point to these RAM vectors.
+#define RAM_VECTORS_SIZE 72
+
+INPUT (crtbegin.o crti.o crtend.o crtn.o)
+
+MEMORY
+{
+    OCRAM (rwx) : ORIGIN = 0x00900000, LENGTH = OCRAM_LEN
+    DDR (rwx)   : ORIGIN = DDR_ORG, LENGTH = DDR_LEN
+}
+
+SECTIONS
+{
+/*
+ * -- OCRAM --
+ *
+ * Nothing in OCRAM can be loaded at boot, because the boot image must be a contiguous
+ * region of memory.
+ */
+
+    /* MMU L1 page table */
+    .l1_page_table (NOLOAD) :
+    {
+        __l1_page_table_start = .;
+        . += L1_PAGE_TABLE_SIZE;
+    } > OCRAM
+
+    /* allocate a heap in ocram */
+    .heap.ocram (NOLOAD) : ALIGN(4)
+    {
+        __heap_ocram_start = .;
+        . += LENGTH(OCRAM) - L1_PAGE_TABLE_SIZE - RAM_VECTORS_SIZE ;
+        __heap_ocram_end = .;
+    } > OCRAM
+    
+    /* RAM vector table comes at the end of OCRAM */
+    .ram_vectors (ORIGIN(OCRAM) + LENGTH(OCRAM) - RAM_VECTORS_SIZE) (NOLOAD) :
+    {
+        __ram_vectors_start = .;
+        . += RAM_VECTORS_SIZE;
+        __ram_vectors_end = .;
+    } > OCRAM
+
+
+/*
+ * -- DDR --
+ */
+
+    /* -- read-only sections -- */
+    
+    _start_image_add = ORIGIN(DDR);
+    
+    .ivt (ORIGIN(DDR)) :
+    {
+        . = . + 0x400;
+        *(.ivt)
+    } > DDR
+    
+    .boot_data :
+    {
+        __start_boot_data = .;
+        *(.boot_data)
+    } > DDR
+    
+    /* aligned to ease the hexdump read of generated binary */ 
+    .dcd_hdr : ALIGN(16)
+    {
+        __start_dcd = .;
+        *(.dcd_hdr)
+    } > DDR
+    .dcd_wrt_cmd :
+    {
+        *(.dcd_wrt_cmd)
+    } > DDR
+    .dcd_data :
+    {
+        *(.dcd_data)
+    } > DDR
+    
+    .text : ALIGN(8)
+    {
+        CREATE_OBJECT_SYMBOLS
+        *(.startup)
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+        
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.gcc_except_table)
+    } > DDR
+
+    .ctors :
+    {
+        /* gcc uses crtbegin.o to find the start of
+           the constructors, so we make sure it is
+           first.  Because this is a wildcard, it
+           doesn't matter if the user does not
+           actually link against crtbegin.o; the
+           linker won't look for a file to match a
+           wildcard.  The wildcard also means that it
+           doesn't matter which directory crtbegin.o
+           is in.  */
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*crtbegin?.o(.ctors))
+        /* We don't want to include the .ctor section from
+           the crtend.o file until after the sorted ctors.
+           The .ctor section from the crtend file contains the
+           end of ctors marker and it must be last */
+        KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*(.ctors))
+    } > DDR
+    .dtors :
+    {
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*crtbegin?.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+    } > DDR
+
+    .rodata :
+    {
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+        . = ALIGN(4);
+        KEEP(*(.init))
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+        
+        . = ALIGN(4);
+        KEEP(*(.fini))
+        
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+    } > DDR
+
+    /* Unwind index. This section is related to C++ exceptions, and is required even
+       though exceptions are disabled with -fno-exceptions. */
+    PROVIDE_HIDDEN(__exidx_start = .);
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > DDR
+    PROVIDE_HIDDEN(__exidx_end = .);
+
+    /* -- read-write sections -- */
+    
+    .data : ALIGN(8)
+    {
+        *(.data .data.* .gnu.linkonce.d.*)
+        SORT(CONSTRUCTORS)
+    } > DDR
+
+    /* Reserve some space for HAB CSF data */
+    .hab.data (_start_image_add + MAX_IMAGE_SIZE) : ALIGN(4)
+    {
+        __hab_data = .;
+        . += MAX_HAB_CSF_DATA_SIZE;
+        . = ALIGN (32);
+        __hab_data_end = .;
+    } > DDR
+    /* End of HAB reserved space (must place it before BSS section) */
+
+    _image_size = . - _start_image_add;
+
+    /* The .bss section comes after the hab data because it is not signed */
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.shbss)
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+        *(.bss)
+        __bss_end__ = .;
+    } > DDR
+
+    /* Region to contain exception handler stacks */
+    .stacks (NOLOAD) :
+    {
+        __stacks_start = .;
+        . += STACK_SIZE;
+        __stacks_end = .;
+        top_of_stacks = .;
+    } > DDR
+    
+    /* define range of the malloc heap */
+    free_memory_start = ALIGN(32); /* malloc starts allocating from here */
+    . += HEAP_SIZE;
+    free_memory_end = .;
+
+    _end = .;
+}

bsp/imx6sx/iMX6_Platform_SDK/apps/common/ivt.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "hab_defines.h"
+
+extern unsigned * _start_image_add;
+extern unsigned * __start_boot_data;
+extern unsigned * _image_size;
+
+extern unsigned * __hab_data;
+
+extern uint8_t input_dcd_hdr[];
+
+extern void _start(void);
+
+struct hab_ivt input_ivt __attribute__ ((section (".ivt"))) ={
+    /** @ref hdr word with tag #HAB_TAG_IVT, length and HAB version fields
+     *  (see @ref data)
+     */
+    IVT_HDR(sizeof(struct hab_ivt), HAB_VER(4, 0)),
+    /** Absolute address of the first instruction to execute from the
+     *  image
+     */
+    (hab_image_entry_f)_start,
+
+    /** Reserved in this version of HAB: should be NULL. */
+    NULL,
+    /** Absolute address of the image DCD: may be NULL. */
+    &input_dcd_hdr,
+    /** Absolute address of the Boot Data: may be NULL, but not interpreted
+     *  any further by HAB
+     */
+    &__start_boot_data,
+    /** Absolute address of the IVT.*/
+    (const void*) (&input_ivt),
+    
+    /** Absolute address of the image CSF.*/
+    (const void*) &__hab_data,
+
+    /** Reserved in this version of HAB: should be zero. */
+    0
+};
+
+typedef struct {
+    uint32_t start;            /**< Start address of the image */
+    uint32_t size;             /**< Size of the image */
+    uint32_t plugin;           /**< Plugin flag */
+} boot_data_t;
+
+boot_data_t bd __attribute__ ((section (".boot_data"))) ={
+    (uint32_t) &_start_image_add,
+    (uint32_t) &_image_size,
+    0,
+};
+

bsp/imx6sx/iMX6_Platform_SDK/apps/common/platform_init.c

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sdk.h"
+#include "board_io_expanders.h"
+#include "platform_init.h"
+#include "core/cortex_a9.h"
+#include "core/mmu.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+void platform_init(void)
+{
+    enable_neon_fpu();
+    disable_strict_align_check();
+    mmu_init();
+
+    // Map some SDRAM for DMA
+#if defined(BOARD_EVB)
+    mmu_map_l1_range(0x30000000, 0x30000000, 0x70000000, kNoncacheable, kShareable, kRWAccess);
+#elif defined(BOARD_SMART_DEVICE)
+    mmu_map_l1_range(0x20000000, 0x20000000, 0x30000000, kNoncacheable, kShareable, kRWAccess);
+#endif
+
+    // Enable interrupts. Until this point, the startup code has left interrupts disabled.
+    gic_init();
+    arm_set_interrupt_state(true);
+    
+    // Initialize clock sources, dividers, ... 
+    ccm_init();
+    
+    // Configure the EPIT timer used for system delay function. 
+    system_time_init();
+    
+    // Initialize the debug/console UART 
+    uart_init(g_debug_uart_port, 115200, PARITY_NONE, STOPBITS_ONE, EIGHTBITS, FLOWCTRL_OFF);
+
+    // flush UART RX FIFO 
+    uint8_t c;
+    do {
+        c = uart_getchar(g_debug_uart_port);
+    } while (c != NONE_CHAR);
+
+    // Some init for the board 
+    board_ioexpander_init();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/apps/common/platform_init.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__PLATFORM_INIT_H__)
+#define __PLATFORM_INIT_H__
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//! @brief Do basic hardware initialization to make the system usable.
+//!
+//! Performs minimal initialization to enable most drivers to work. The GIC,
+//! CCM, and UART drivers are inited. The systme timer is inited. And
+//! board_ioexpander_init() is called.
+void platform_init(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // __PLATFORM_INIT_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/apps/common/print_clock_info.c

@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "print_clock_info.h"
+#include "core/ccm_pll.h"
+#include "registers/regsuart.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+void show_freq(void)
+{
+    printf("========== Clock frequencies ===========\n");
+
+    printf("CPU: %d kHz\n", get_main_clock(CPU_CLK)/1000);
+    printf("DDR: %d kHz\n", get_main_clock(MMDC_CH0_AXI_CLK)/1000);
+    printf("IPG: %d kHz\n", get_main_clock(IPG_CLK)/1000);
+    
+    peri_clocks_t clk = UART1_MODULE_CLK + (g_debug_uart_port - HW_UART1);
+    printf("Debug UART: %d Hz\n", get_peri_clock(clk));
+
+    printf("========================================\n\n");
+}
+
+//! @todo Rewrite for MMDC controller. This code is currently for MX53.
+void show_ddr_config(void)
+{
+#if 0
+    uint32_t temp1, dsiz, row, col, cs_info;
+    uint32_t temp2, num_banks, ddr_type;
+    uint32_t density, megabyte;
+    uint32_t num_rows = 1, num_cols = 1, num_dsiz = 1, i = 1;
+
+    printf("========== DDR configuration ===========\n");
+
+    megabyte = 1024 * 1024;
+    /* read ESDCTL and gather information */
+    temp1 = readl(ESDCTL_REGISTERS_BASE_ADDR + 0x00);
+    dsiz = ((temp1 & (0x00030000)) >> 16);
+    /*Calculate dsize */
+    while (i <= dsiz) {
+        num_dsiz *= 2;
+        i++;
+    }
+    dsiz = 16 * num_dsiz;
+
+    row = ((temp1 & (0x07000000)) >> 24) + 11;
+    col = ((temp1 & (0x00700000)) >> 20) + 9;
+    cs_info = (temp1 & (0xC0000000)) >> 30;
+    /* read ESDMISC to get # of BANK info */
+    temp2 = readl(ESDCTL_REGISTERS_BASE_ADDR + 0x18);
+    num_banks = (!((temp2 & (0x00000020)) >> 5)) * 4 + 4;
+    ddr_type = (temp2 & (0x00000018)) >> 3;
+    printf("data bits: %d, num_banks: %d \n", dsiz, num_banks);
+    printf("row: %d, col: %d \n", row, col);
+
+    if (ddr_type == 1)
+        printf("DDR type is DDR2 \n");
+    else if (ddr_type == 2)
+        printf("DDR type is LPDDR2\n");
+    else
+        printf("DDR type is DDR3 \n");
+
+    if (cs_info == 0)
+        printf("No chip select is enabled \n");
+    else if (cs_info == 2)
+        printf("Chip select CSD0 is used \n");
+    else if (cs_info == 1)
+        printf("Chip select CSD1 is used  \n");
+    else
+        printf("Both chip select CSD0 and CSD1 are used  \n");
+
+    /* Now calculate the DDR density per chip select */
+
+    i = 1;
+    /* First need to calculate the number of rows and cols 2^row and 2^col */
+    while (i <= row) {
+        num_rows *= 2;
+        i++;
+    }
+
+    debug_printf("num_rows= %d\n", num_rows);
+    i = 1;
+
+    while (i <= col) {
+        num_cols *= 2;
+        i++;
+    }
+
+    debug_printf("num_cols= %d\n", num_cols);
+    density = num_rows * num_cols / megabyte;
+    density = density * dsiz * num_banks / 8;
+    printf("Density per chip select: %dMB \n", density);
+    printf("========================================\n\n");
+#endif // 0
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/apps/common/print_clock_info.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !defined(__PRINT_CLOCK_INFO_H__)
+#define __PRINT_CLOCK_INFO_H__
+
+#include "sdk.h"
+
+//! @addtogroup app_common
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Display module frequency
+ */
+void show_freq(void);
+
+/*!
+ * @brief Display the board's DDR configuration
+ */
+void show_ddr_config(void);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif // __PRINT_CLOCK_INFO_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/apps/common/print_version.c

@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file  print_version.c
+ * @brief Contains function to print out the app release version.
+ */
+
+#include "sdk.h"
+#include "sdk_version.h"
+#include "board_id/board_id.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+/*!
+ * print out the diag release version info
+ *
+ */
+void print_version(void)
+{
+    char chip_str[64] = { 0 };
+    char chip_rev_str[64] = { 0 };
+    char board_str[64] = { 0 };
+    char board_rev_str[64] = { 0 };
+
+    fsl_board_id_t fsl_board_id = get_board_id();
+
+    chip_name(chip_str, fsl_board_id.B.CHIP_TYPE_ID, false);
+    chip_revision(chip_rev_str, fsl_board_id.B.CHIP_REV_MAJOR, fsl_board_id.B.CHIP_REV_MINOR);
+    board_name(board_str, BOARD_TYPE);
+    board_revision(board_rev_str, BOARD_REVISION);
+
+    printf("\n\n\n\n");
+    printf("**************************************************************************\n");
+    printf("    Platform SDK (%s) for %s %s %s %s\n", k_sdk_version, chip_str, chip_rev_str,
+           board_str, board_rev_str);
+    printf("    Build: %s, %s\n", __DATE__, __TIME__);
+    printf("    %s\n", k_sdk_copyright);
+    printf("**************************************************************************\n\n");
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/apps/common/print_version.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file print_version.h
+ * @brief release version define - should be changed for each release
+ */
+
+#if !defined(__PRINT_VERSION_H__)
+#define __PRINT_VERSION_H__
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Prints the version header to the console.
+ */
+void print_version(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // __PRINT_VERSION_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/board/common/board_audio.c

@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sdk.h"
+#include "registers/regsccm.h"
+#include "registers/regsesai.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+void SGTL5000PowerUp_and_clockinit(void)
+{
+}
+
+/*!
+ *
+ * Additional code related to clock configuration
+ *
+ */
+unsigned int spdif_get_tx_clk_freq(void)
+{
+    return 30000000;
+}
+
+/*! From obds
+ * Audio Codec Power on
+ */
+void audio_codec_power_on (void)
+{
+#ifdef BOARD_SMART_DEVICE
+    //CODEC PWR_EN, key_col12
+    gpio_set_gpio(GPIO_PORT4, 10);
+    gpio_set_direction(GPIO_PORT4, 10, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT4, 10, GPIO_HIGH_LEVEL);
+#endif
+}
+
+/*! From obds
+ * Audio Clock Config
+ */
+void audio_clock_config(void)
+{
+#if defined(BOARD_SMART_DEVICE) 
+    ccm_iomux_config();
+
+    HW_CCM_CCOSR_WR(BF_CCM_CCOSR_CLKO2_EN(1)
+                    | BF_CCM_CCOSR_CLKO2_DIV(6)
+                    | BF_CCM_CCOSR_CLKO2_SEL(0x13)
+                    | BF_CCM_CCOSR_CLKO_SEL(1));
+#endif
+}
+
+/*!
+ * @brief SPDIF clock configuration
+ *
+ * Use the default setting as follow:
+ * CDCDR[spdif0_clk_sel](PLL3)->CDCDR[spdif0_clk_pred](div2)->CDCDR[spdif0_clk_podf](div8)-> spdif0_clk_root, so
+ * the freqency of spdif0_clk should be 480/2/8 = 30MHz.
+ */
+void spdif_clk_cfg(void)
+{
+    HW_CCM_CDCDR.B.SPDIF0_CLK_SEL = 3;  // PLL3
+    HW_CCM_CDCDR.B.SPDIF0_CLK_PODF = 7; // div 8
+    HW_CCM_CDCDR.B.SPDIF0_CLK_PRED = 1; // div 2
+
+    clock_gating_config(SPDIF_BASE_ADDR, CLOCK_ON);
+
+    return;
+}
+
+/*!
+ * Power no esai codec.
+ */
+int esai_codec_power_on(void)
+{
+    // No need to do anything for BOARD_SABRE_AI
+    return 0;
+}
+
+void esai_clk_sel_gate_on()
+{
+    // source from PLL3_508
+    HW_CCM_CSCMR2.B.ESAI_CLK_SEL = 1;
+
+    clock_gating_config(REGS_ESAI_BASE, CLOCK_ON);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/board/common/board_buttons.c

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sdk.h"
+#include "registers/regsiomuxc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief IOMUX configuration for the Android_Buttons
+//! @todo Confirm this functionality. Values written to the PAD registers do not make sense with comments.
+void android_buttons_iomux_config()
+{
+    //HOME_(SD2_CMD_GPI1_11)
+    gpio_set_gpio(GPIO_PORT1, 11);
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_WR(                            // pull-up enabled at pad
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE_V(KEEP) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED_V(200MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_V(60_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE_V(SLOW));
+
+    //BACK_(SD2_DATA3_GPI1_12)
+    gpio_set_gpio(GPIO_PORT1, 12);
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_WR(                          // pull-up enabled at pad
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE_V(KEEP) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED_V(200MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_V(60_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE_V(SLOW));
+
+    //PROG_(SD4_DATA4_GPI2_12)
+    gpio_set_gpio(GPIO_PORT2, 12);
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_WR(                          // pull-up enabled at pad
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE_V(KEEP) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_V(200MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_V(60_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE_V(SLOW));
+
+    //VOL+_(SD4_DATA7_GPI2_15)
+    gpio_set_gpio(GPIO_PORT2, 15);
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_WR(                          // pull-up enabled at pad
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE_V(KEEP) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_V(200MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_V(60_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE_V(SLOW));
+
+    //VOL-_(DISP0_DATA20_GPI5_14)
+    gpio_set_gpio(GPIO_PORT5, 14);
+    HW_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_WR(                       // pull-up enabled at pad
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_HYS_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PUE_V(KEEP) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_PKE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SPEED_V(200MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_DSE_V(60_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20_SRE_V(SLOW));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/board/common/board_camera.c

@@ -0,0 +1,884 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sdk.h"
+#include "camera/camera_def.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsccm.h"
+
+#define CAMERA_I2C_PORT (1)
+
+void camera_ipu1_iomux_config(void);
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+
+uint8_t g_camera_i2c_port = CAMERA_I2C_PORT;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+/* dummy empty function for camera_test
+ * camera power is always on for MX6DQ SMD board*/
+void camera_power_on(void)
+{
+}
+
+/*IOMUX configuration for CSI port0*/
+void csi_port0_iomux_config(void)
+{
+    camera_ipu1_iomux_config();
+
+    /* set GPR1 to enable parallel interface
+     * bit 19: 0 - Enable mipi to IPU1 CSI0, virtual channel is fixed to 0
+     *         1 - Enable parallel interface to IPU CSI0
+     * bit 20: 0 - Enable mipi to IPU2 CSI1, virtual channel is fixed to 3
+     *         1 - Enable parallel interface to IPU2 CSI1
+     * IPU1 CSI1 directly connect to mipi CSI2, virtual channel is fixed to 1
+     * IPU2 CSI0 directly connect to mipi CSI2, virtual channel is fixed to 2
+     */
+
+#if defined(CHIP_MX6DQ)
+    BW_IOMUXC_GPR1_MIPI_IPU1_MUX(1/*PARALLEL_INTERFACE*/);
+#endif
+#if defined(CHIP_MX6SDL)
+    BW_IOMUXC_GPR13_IPU_CSI0_MUX(4/*IPU_CSI0*/);
+#endif
+
+}
+
+
+//! @brief Function to configure IOMUXC for ipu1 module.
+//! @todo Move this function to [chip]/[board]/iomuxc folders?
+void camera_ipu1_iomux_config(void)
+{
+    // Config ipu1.IPU1_CSI0_DATA12 to pad CSI0_DATA12(M2)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR(0x000130B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12(0x020E0288)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA12
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA08
+    //     ALT3 (3) - Select instance: uart4 signal: UART4_TX_DATA
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO30
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE09
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12(0x020E0658)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     TBD (0) - TBD
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA13 to pad CSI0_DATA13(L1)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR(0x000130B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13(0x020E028C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA13
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA09
+    //     ALT3 (3) - Select instance: uart4 signal: UART4_RX_DATA
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO31
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE10
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13(0x020E065C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     TBD (0) - TBD
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA14 to pad CSI0_DATA14(M4)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR(0x000130B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14(0x020E0290)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA14
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA10
+    //     ALT3 (3) - Select instance: uart5 signal: UART5_TX_DATA
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO00
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE11
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14(0x020E0660)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     TBD (0) - TBD
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA15 to pad CSI0_DATA15(M5)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR(0x000130B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15(0x020E0294)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA15
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA11
+    //     ALT3 (3) - Select instance: uart5 signal: UART5_RX_DATA
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO01
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE12
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15(0x020E0664)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     TBD (0) - TBD
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA16 to pad CSI0_DATA16(L4)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR(0x000130B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16(0x020E0298)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA16
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA12
+    //     ALT3 (3) - Select instance: uart4 signal: UART4_RTS_B
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO02
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE13
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16(0x020E0668)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     TBD (0) - TBD
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA17 to pad CSI0_DATA17(L3)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR(0x000130B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17(0x020E029C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA17
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA13
+    //     ALT3 (3) - Select instance: uart4 signal: UART4_CTS_B
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO03
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE14
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17(0x020E066C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     TBD (0) - TBD
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA18 to pad CSI0_DATA18(M6)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR(0x000130B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18(0x020E02A0)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA18
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA14
+    //     ALT3 (3) - Select instance: uart5 signal: UART5_RTS_B
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO04
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE15
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18(0x020E0670)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     TBD (0) - TBD
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_DATA19 to pad CSI0_DATA19(L6)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR(0x000130B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19(0x020E02A4)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA19
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA15
+    //     ALT3 (3) - Select instance: uart5 signal: UART5_CTS_B
+    //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO05
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19(0x020E0674)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     TBD (0) - TBD
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_HSYNC to pad CSI0_HSYNC(P4)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR(0x000130B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC(0x020E025C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_HSYNC
+    //     ALT3 (3) - Select instance: ccm signal: CCM_CLKO1
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO19
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE_CTL
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC(0x020E062C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     TBD (0) - TBD
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_PIXCLK to pad CSI0_PIXCLK(P1)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR(0x000130B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK(0x020E0258)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_PIXCLK
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO18
+    //     ALT7 (7) - Select instance: arm signal: ARM_EVENTO
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK(0x020E0628)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     TBD (0) - TBD
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_SRE_V(SLOW));
+
+    // Config ipu1.IPU1_CSI0_VSYNC to pad CSI0_VSYNC(N2)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR(0x000130B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC(0x020E0264)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_VSYNC
+    //     ALT1 (1) - Select instance: eim signal: EIM_DATA01
+    //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO21
+    //     ALT7 (7) - Select instance: arm signal: ARM_TRACE00
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC(0x020E0634)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     TBD (0) - TBD
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_SRE_V(SLOW));
+}
+
+/*!
+ * reset camera sensor through GPIO on SMD board 
+ *
+ */
+void sensor_reset(void)
+{
+    int32_t reset_occupy = 1000, reset_delay = 1000;
+
+    sensor_standby(0);
+
+    /* MX6DQ/SDL_SMART_DEVICE: camera reset through GPIO1_17 */
+	BW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE__ALT5);
+	gpio_set_direction(GPIO_PORT1, 17, GPIO_GDIR_OUTPUT);
+
+	gpio_set_level(GPIO_PORT1, 17, GPIO_LOW_LEVEL);
+    hal_delay_us(reset_occupy);
+
+	gpio_set_level(GPIO_PORT1, 17, GPIO_HIGH_LEVEL);
+    hal_delay_us(reset_delay);
+}
+
+/*!
+ * set camera sensor to standby mode.
+ *
+ * @param	enable: specify whether set camera sensor to standby mode
+ * 
+ */
+void sensor_standby(int32_t enable)
+{
+    /* MX6DQ/SDL_SMART_DEVICE: setting to gpio1_16, power down high active */
+	BW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE__ALT5);
+	gpio_set_direction(GPIO_PORT1, 16, GPIO_GDIR_OUTPUT);
+    if (enable)
+		gpio_set_level(GPIO_PORT1, 16, GPIO_HIGH_LEVEL);
+    else
+		gpio_set_level(GPIO_PORT1, 16, GPIO_LOW_LEVEL);
+}
+
+/*!
+ * set camera sensor clock to 24MHz. 
+ *
+ */
+void sensor_clock_setting(void)
+{
+    int32_t clock_delay = 1000;
+
+    /*MX6DQ/SDL_SMART_DEVICE: config clko */
+    /*config gpio_0 to be clko */
+	BW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE__ALT0);
+
+	BW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE__FAST);
+	BW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE(BV_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE__80_OHM);
+
+    /*select osc_clk 24MHz, CKO1 output drives cko2 clock */
+	HW_CCM_CCOSR_WR(
+			BF_CCM_CCOSR_CLKO2_EN(1) |
+			BF_CCM_CCOSR_CLKO2_DIV(0) | /*div 1*/
+			BF_CCM_CCOSR_CLKO2_SEL(0xe) | /*osc_clk*/
+			BF_CCM_CCOSR_CLKO_SEL(1) |
+			BF_CCM_CCOSR_CLKO1_EN(1) |
+			BF_CCM_CCOSR_CLKO1_DIV(0)); /*div 1*/
+
+    hal_delay_us(clock_delay);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/board/common/board_can.c

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "iomux_config.h"
+#include "ioexpander/max7310.h"
+#include "gpio/gpio.h"
+#include "registers/regsflexcan.h"
+#include "flexcan/flexcan.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+/*!
+ * board dependent IOMUX configuration functions
+ */
+void hw_can_iomux_config(uint32_t module_instance)
+{
+
+#ifdef BOARD_SABRE_AI
+    board_ioexpander_iomux_config();
+    /* CAN_EN active high output */
+    max7310_set_gpio_output(1, 6, GPIO_HIGH_LEVEL); //expander b, io6
+
+    /* CAN_STBY active high output */
+    max7310_set_gpio_output(1, 5, GPIO_HIGH_LEVEL); //expander b, io5 
+#endif
+
+    flexcan_iomux_config(module_instance);
+
+#ifdef BOARD_SABRE_AI
+    switch (module_instance)
+    {
+    case HW_FLEXCAN1:
+        board_ioexpander_iomux_config();
+        /* Select CAN, ENET_CAN1_STEER(PORT_EXP_B3) */
+        max7310_set_gpio_output(1, 3, GPIO_HIGH_LEVEL); //expander b, io3
+        /* Select ALT5 mode of GPIO_4 for GPIO1_4 - CAN1_NERR_B */
+        /* active low input */
+        gpio_set_gpio(GPIO_PORT1, 4);
+        gpio_set_direction(GPIO_PORT1, 4, GPIO_GDIR_INPUT);
+        break;
+
+    case HW_FLEXCAN2:
+        /* Select ALT5 mode of SD4_DAT3 for GPIO2_11 - CAN2_NERR_B */
+        /* active low input */
+        gpio_set_gpio(GPIO_PORT2, 11);
+        gpio_set_direction(GPIO_PORT2, 11, GPIO_GDIR_INPUT);
+        break;
+
+    default:
+        printf("ERR: invalid FLEXCAN instance for iomux config\n");
+        break;
+    }
+#endif
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/board/common/board_display.c

@@ -0,0 +1,322 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sdk.h"
+#include "registers/regsccmanalog.h"
+#include "registers/regsccm.h"
+#include "registers/regsiomuxc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+/*!
+ * Provide the LVDS power through GPIO pins
+ */
+void lvds_power_on(void)
+{
+#if defined(BOARD_EVB)
+    board_ioexpander_iomux_config();
+    /*3.3V power supply through the load switch FDC6331L */
+    max7310_set_gpio_output(0, 0, GPIO_HIGH_LEVEL);
+    max7310_set_gpio_output(1, 1, GPIO_HIGH_LEVEL);
+
+    /*lvds backlight enable, GPIO_9 */
+    gpio_set_gpio(GPIO_PORT1, 9);
+    gpio_set_direction(GPIO_PORT1, 9, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT1, 9, GPIO_HIGH_LEVEL);
+#endif
+
+#ifdef BOARD_SMART_DEVICE
+    // 3v3 on by default
+    // AUX_5V_EN LVDS0 power
+    gpio_set_gpio(GPIO_PORT6, 10);
+    gpio_set_direction(GPIO_PORT6, 10, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT6, 10, GPIO_HIGH_LEVEL);
+    // PMIC_5V LVDS1 power on by default
+    // backlight both lvds1/0, disp0_contrast/disp0_pwm, gpio1[21]
+    gpio_set_gpio(GPIO_PORT1, 21);
+    gpio_set_direction(GPIO_PORT1, 21, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT1, 21, GPIO_HIGH_LEVEL);
+#endif
+
+#ifdef BOARD_SABRE_AI
+    board_ioexpander_iomux_config();
+    /*3.3V power supply through IOexpander */
+    max7310_set_gpio_output(0, 0, GPIO_HIGH_LEVEL);
+
+    /*lvds backlight enable, GPIO_9 */
+    gpio_set_gpio(GPIO_PORT2, 9);
+    gpio_set_direction(GPIO_PORT2, 9, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT2, 9, GPIO_HIGH_LEVEL);
+
+#endif
+}
+
+/*! From obds
+ * Disable the display panel
+ */
+void disable_para_panel(void)
+{
+    gpio_set_gpio(GPIO_PORT2, 31);
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS_V(100K_OHM_PU) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE_V(SLOW));
+    gpio_set_direction(GPIO_PORT2, 31, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT2, 31, GPIO_LOW_LEVEL);
+}
+
+/*! Copy from OBDS
+ * Provide the power for TFT LCD backlight
+ */
+void tftlcd_backlight_en(char *panel_name)
+{
+    if (!strcmp(panel_name, "CLAA01 WVGA")) {
+        /*GPIO to provide backlight */
+        gpio_set_gpio(GPIO_PORT4, 20);
+        gpio_set_direction(GPIO_PORT4, 20, GPIO_GDIR_OUTPUT);
+        gpio_set_level(GPIO_PORT4, 20, GPIO_HIGH_LEVEL);
+    } else if (!strcmp(panel_name, "BoundaryDev WVGA")) {
+#if defined (BOARD_REV_A)
+        /*lvds/parallel display backlight enable, GPIO2_0 */
+        gpio_set_gpio(GPIO_PORT2, 9);
+        gpio_set_direction(GPIO_PORT2, 9, GPIO_GDIR_OUTPUT);
+        gpio_set_level(GPIO_PORT2, 9, GPIO_HIGH_LEVEL);
+
+        // lcd_contrast conflict with actual BoundaryDev display so seeting to input
+        // since TSC not used on SABRE AI
+        gpio_set_gpio(GPIO_PORT4, 20);
+        gpio_set_direction(GPIO_PORT4, 20, GPIO_GDIR_INPUT);
+#elif defined (BOARD_REV_B) || defined(BOARD_REV_C)
+        gpio_set_gpio(GPIO_PORT4, 20);
+        gpio_set_direction(GPIO_PORT4, 20, GPIO_GDIR_OUTPUT);
+        gpio_set_level(GPIO_PORT4, 20, GPIO_HIGH_LEVEL);
+#endif
+    } else {
+        printf("Unsupported panel!\n");
+    }
+#if 0
+#ifdef BOARD_SABRE_AI
+    /*lvds/parallel display backlight enable, GPIO2_0 */
+    gpio_set_gpio(GPIO_PORT2, 9);
+    gpio_set_direction(GPIO_PORT2, 9, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT2, 9, GPIO_LOW_LEVEL);
+
+    // lcd_contrast conflict with actual BoundaryDev display so seeting to input
+    // since TSC not used on SABRE AI
+    gpio_set_gpio(GPIO_PORT4, 20);
+    gpio_set_direction(GPIO_PORT4, 20, GPIO_GDIR_INPUT);
+#endif
+#ifdef BOARD_SMART_DEVICE
+    /* AUX_3V15 */
+    gpio_set_gpio(GPIO_PORT6, 9);
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_V(100K_OHM_PU) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE_V(SLOW));
+    gpio_set_direction(GPIO_PORT6, 9, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT6, 9, GPIO_HIGH_LEVEL);
+    // backlight both lvds1/0, disp0_contrast/disp0_pwm, gpio1[21]
+    gpio_set_gpio(GPIO_PORT1, 21);
+    gpio_set_direction(GPIO_PORT1, 21, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT1, 21, GPIO_HIGH_LEVEL);
+    // AUX_5V_EN LVDS0 power
+    gpio_set_gpio(GPIO_PORT6, 10);
+    gpio_set_direction(GPIO_PORT6, 10, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT6, 10, GPIO_HIGH_LEVEL);
+#endif
+#endif
+
+}
+
+/*! Copy from OBDS
+ * Reset the TFT LCD
+ */
+void tftlcd_reset(char *panel_name)
+{
+    if (!strcmp(panel_name, "CLAA01 WVGA")) {
+#ifdef BOARD_EVB
+        gpio_set_gpio(GPIO_PORT2, 31);
+        HW_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_WR(
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_HYS_V(ENABLED) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUS_V(100K_OHM_PU) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PUE_V(PULL) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_PKE_V(ENABLED) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_ODE_V(DISABLED) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SPEED_V(100MHZ) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_DSE_V(40_OHM) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_SRE_V(SLOW));
+        gpio_set_direction(GPIO_PORT2, 31, GPIO_GDIR_OUTPUT);
+        gpio_set_level(GPIO_PORT2, 31, GPIO_LOW_LEVEL);
+        hal_delay_us(1000);
+        gpio_set_level(GPIO_PORT2, 31, GPIO_HIGH_LEVEL);
+        hal_delay_us(1000);
+#endif
+#ifdef BOARD_SMART_DEVICE
+        gpio_set_gpio(GPIO_PORT3, 8);
+        HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR(
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS_V(ENABLED) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS_V(100K_OHM_PU) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE_V(PULL) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE_V(ENABLED) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE_V(DISABLED) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED_V(100MHZ) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE_V(40_OHM) |
+                BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE_V(SLOW));
+        gpio_set_direction(GPIO_PORT3, 8, GPIO_GDIR_OUTPUT);
+        gpio_set_level(GPIO_PORT3, 8, GPIO_LOW_LEVEL);
+        hal_delay_us(1000);
+        gpio_set_level(GPIO_PORT3, 8, GPIO_HIGH_LEVEL);
+        hal_delay_us(1000);
+#endif
+    }
+}
+
+/*!
+ * @brief Configure ldb clock as per the display resolution.
+ *
+ * ldb clock is derived from PLL5, ldb on ipu1
+ */
+void ldb_clock_config(int freq, int ipu_index)
+{
+    if (freq == 65000000)       //for XGA resolution
+    {
+        //config pll3 PFD1 to 455M. pll3 is 480M 
+        BW_CCM_ANALOG_PFD_480_PFD1_FRAC(19);
+
+        // set ldb_di0_clk_sel to PLL3 PFD1
+        HW_CCM_CS2CDR.B.LDB_DI0_CLK_SEL = 3;
+        HW_CCM_CS2CDR.B.LDB_DI1_CLK_SEL = 3;
+
+        // set clk_div to 7
+        HW_CCM_CSCMR2.B.LDB_DI0_IPU_DIV = 1;
+        HW_CCM_CSCMR2.B.LDB_DI1_IPU_DIV = 1;
+
+        if (ipu_index == 1) {
+            //set ipu1_di0_clk_sel from ldb_di0_clk 
+            HW_CCM_CHSCCDR.B.IPU1_DI0_CLK_SEL = 3;  // ldb_di0_clk
+            HW_CCM_CHSCCDR.B.IPU1_DI1_CLK_SEL = 3;  // ldb_di0_clk
+        }
+#if CHIP_MX6DQ
+        else {
+            //set ipu2_di0_clk_sel from ldb_di0_clk 
+            HW_CCM_CSCDR2.B.IPU2_DI0_CLK_SEL = 3;
+            HW_CCM_CSCDR2.B.IPU2_DI1_CLK_SEL = 3;
+        }
+#endif // CHIP_MX6DQ
+    } else {
+        printf("The frequency %d for LDB is not supported yet.", freq);
+    }
+}
+
+void epdc_clock_setting(int freq)
+{
+#if defined(CHIP_MX6SDL)
+    HW_CCM_CSCDR2.B.EPDC_PIX_PRE_CLK_SEL = 0x3; // 307M PFD
+
+    HW_CCM_CSCDR2.B.EPDC_PIX_CLK_SEL = 0x0;
+
+    /*set the output as 271M */
+    BW_CCM_ANALOG_PFD_528_PFD0_FRAC(0x23);
+
+    HW_CCM_CSCDR2.B.EPDC_PIX_PODF = 0x7;    // post divider
+
+//  HW_IOMUXC_SW_MUX_CTL_PAD_GPIO_3.B.MUX_MODE = ALT4; //set as clko
+#endif
+
+#if defined(CHIP_MX6SL)
+    HW_CCM_CSCDR2.B.EPDC_PIX_CLK_SEL = 0x5; //Use 540MPFD
+
+    HW_CCM_CSCDR2.B.EPDC_PIX_PRED = 0x5;    //pred for EPDC
+
+    HW_CCM_CBCMR.B.EPDC_PIX_PODF = 0x4;
+
+    /*set the AXI clock, divided from MMDC clock */
+    HW_CCM_CHSCCDR.B.EPDC_AXI_CLK_SEL = 0x0;
+    HW_CCM_CHSCCDR.B.EPDC_AXI_PODF = 0x1;
+#endif
+}
+
+void epdc_power_supply(void)
+{
+    int i = 0;
+#if defined(CHIP_MX6SDL)
+#if defined(BOARD_EVB)
+    /*PMIC wakeup */
+    gpio_set_gpio(GPIO_PORT2, 31);
+    gpio_set_direction(GPIO_PORT2, 31, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT2, 31, GPIO_HIGH_LEVEL);
+
+    /*PMIC vcom */
+    gpio_set_gpio(GPIO_PORT3, 17);
+    gpio_set_direction(GPIO_PORT3, 17, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT3, 17, GPIO_HIGH_LEVEL);
+#elif defined(BOARD_SMART_DEVICE)
+    /*PMIC wakeup */
+    gpio_set_gpio(GPIO_PORT3, 20);
+    gpio_set_direction(GPIO_PORT3, 20, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT3, 20, GPIO_HIGH_LEVEL);
+
+    /*PMIC vcom */
+    gpio_set_gpio(GPIO_PORT3, 17);
+    gpio_set_direction(GPIO_PORT3, 17, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT3, 17, GPIO_HIGH_LEVEL);
+#endif
+#endif
+
+#if defined(CHIP_MX6SL)
+    //EN : pmic_wakeup gpio2.14
+    gpio_set_gpio(GPIO_PORT2, 14);
+    gpio_set_direction(GPIO_PORT2, 14, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT2, 14, GPIO_HIGH_LEVEL);
+
+    //CEN : pmic_vcom gpio2.3
+    gpio_set_gpio(GPIO_PORT2, 3);
+    gpio_set_direction(GPIO_PORT2, 3, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT2, 3, GPIO_HIGH_LEVEL);
+#endif
+    for (i = 0; i < 1000000; i++)
+        __asm("nop");
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/board/common/board_hdmi.c

@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sdk.h"
+#include "registers/regsccm.h"
+#include "registers/regsccmanalog.h"
+#include "registers/regsiomuxc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+/*!
+ * config instance hdmi_tx of Module HDMI_TX to Protocol CEC
+ * port including CEC_LINE
+ */
+void hdmi_tx_cec_pgm_iomux(void)
+{
+    // config EIM_A25 pad for hdmi_tx instance CEC_LINE port
+    HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25_MUX_MODE_V(ALT6));
+    // Pad EIM_A25 is involved in Daisy Chain.
+    HW_IOMUXC_HDMI_ICECIN_SELECT_INPUT_WR(
+            BF_IOMUXC_HDMI_ICECIN_SELECT_INPUT_DAISY_V(EIM_ADDR25_ALT6));
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUS_V(22K_OHM_PU) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_ODE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25_SRE_V(SLOW));
+}
+
+/*!
+ * config instance hdmi_tx of Module HDMI_TX to Protocol DDC
+ * ports including DDC_SCL, DDC_SDA.
+ */
+void hdmi_tx_ddc_pgm_iomux(void)
+{
+    // config KEY_COL3 pad for hdmi_tx instance DDC_SCL port
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_V(ALT2));
+    // Pad KEY_COL3 is involved in Daisy Chain.
+    HW_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_WR(
+            BF_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT_DAISY_V(KEY_COL3_ALT2));
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_V(22K_OHM_PU) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE_V(SLOW));
+
+    // config KEY_ROW3 pad for hdmi_tx instance DDC_SDA port
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_V(ALT2));
+    // Pad KEY_ROW3 is involved in Daisy Chain.
+    HW_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_WR(
+            BF_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT_DAISY_V(KEY_ROW3_ALT2));
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_V(22K_OHM_PU) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE_V(SLOW));
+}
+
+/*!
+ * config instance hdmi_tx of Module HDMI_TX to Protocol PHYDTB
+ * ports including {OPHYDTB[1]}, {OPHYDTB[0]}
+ */
+void hdmi_tx_phydtb_pgm_iomux(void)
+{
+    // config SD1_DAT1 pad for hdmi_tx instance OPHYDTB[0] port
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(6/*ALT6*/));
+
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE_V(KEEP) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_V(FAST));
+
+    // config SD1_DAT0 pad for hdmi_tx instance OPHYDTB[1] port
+    HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE(6/*ALT6*/));
+
+    HW_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_V(100K_OHM_PD) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE_V(KEEP) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_V(FAST));
+}
+
+/*!
+ * HDMI pin mux and internal connection mux
+ * be noted that the HDMI is drivern by the IPU1 di0 here
+ */
+void hdmi_pgm_iomux(void)
+{
+    ipu1_iomux_config();
+    hdmi_tx_cec_pgm_iomux();
+    hdmi_tx_ddc_pgm_iomux();
+    hdmi_tx_phydtb_pgm_iomux();
+}
+
+/*!
+ * HDMI power up
+ */
+void ext_hdmi_transmitter_power_on(void)
+{
+    /*3.3V for core, default is on */
+    /*5V for IO, default is on */
+}
+
+void hdmi_clock_set(int ipu_index, uint32_t pclk)
+{
+    switch (pclk) {
+    case 74250000:
+    case 148500000:
+        if (ipu_index == 1) {
+            //clk output from 540M PFD1 of PLL3 
+            HW_CCM_CHSCCDR.B.IPU1_DI0_CLK_SEL = 0;  // derive clock from divided pre-muxed ipu1 di0 clock
+            HW_CCM_CHSCCDR.B.IPU1_DI0_PODF = 5; // div by 6
+            HW_CCM_CHSCCDR.B.IPU1_DI0_PRE_CLK_SEL = 5;  // derive clock from 540M PFD
+        }
+#if CHIP_MX6DQ
+        else {
+            //clk output from 540M PFD1 of PLL3 
+            HW_CCM_CSCDR2.B.IPU2_DI0_CLK_SEL = 0;   // derive clock from divided pre-muxed ipu1 di0 clock
+            HW_CCM_CSCDR2.B.IPU2_DI0_PODF = 5;  // div by 6
+            HW_CCM_CSCDR2.B.IPU2_DI0_PRE_CLK_SEL = 5;   // derive clock from 540M PFD
+        }
+#endif // CHIP_MX6DQ
+        //config PFD1 of PLL3 to be 445MHz 
+        BW_CCM_ANALOG_PFD_480_PFD1_FRAC(0x13);
+        break;
+
+    default:
+        printf("the hdmi pixel clock is not supported!\n");
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/board/common/board_i2c.c

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sdk.h"
+#include "board_i2c.h"
+#include "registers/regsi2c.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Globals
+////////////////////////////////////////////////////////////////////////////////
+
+const i2c_device_info_t g_wm8958_i2c_device = { HW_I2C2, (0x34 >> 1), 100000 };
+
+const i2c_device_info_t g_wm8962_i2c_device = { HW_I2C1, (0x34 >> 1), 48000 };
+
+const i2c_device_info_t g_sgtl5000_i2c_device = { HW_I2C2, 0x0a, 100000 };
+
+#if defined (BOARD_EVB)
+const i2c_device_info_t g_cs42888_i2c_device = { HW_I2C1, (0x90 >> 1), 100000 };
+#else
+const i2c_device_info_t g_cs42888_i2c_device = { HW_I2C2, (0x90 >> 1), 100000 };
+#endif
+
+const i2c_device_info_t g_pmic_ltc3589_i2c_device = { HW_I2C2, (0x68 >> 1), 170000 };
+
+const i2c_device_info_t g_pmic_da9053_i2c_device = { HW_I2C1, (0x90 >> 1), 170000 };
+
+const i2c_device_info_t g_pmic_max17135_i2c_device = { HW_I2C1, (0x90 >> 1), 170000 };
+
+const i2c_device_info_t g_pmic_pf0100_i2c_device = { HW_I2C2, (0x10 >> 1), 170000 };
+
+
+#if defined(BOARD_EVB)
+const i2c_device_info_t g_adv7180_i2c_device = { HW_I2C1, (0x42 >> 1), 50000 };
+#else
+const i2c_device_info_t g_adv7180_i2c_device = { HW_I2C3, (0x42 >> 1), 50000 };
+#endif
+
+
+const i2c_device_info_t g_os81050_i2c_device = { HW_I2C3, (0x40 >> 1), 50000 };
+
+#if defined(BOARD_SMART_DEVICE)
+const i2c_device_info_t g_p1003_tsc_i2c_device = { HW_I2C3, (0x8 >> 1), 50000 };
+#else
+const i2c_device_info_t g_p1003_tsc_i2c_device = { HW_I2C2, (0x8 >> 1), 50000 };
+#endif
+
+const i2c_device_info_t g_at24cx_i2c_device = { HW_I2C3, (0xa0 >> 1), 170000 };
+
+const i2c_device_info_t g_si476x_i2c_device = { HW_I2C2, (0xC6 >> 1), 50000 };
+
+#if defined(BOARD_SMART_DEVICE)
+const i2c_device_info_t g_mma8451_i2c_device = { HW_I2C1, 0x1C, 170000 };
+#elif defined(BOARD_SABRE_AI)
+const i2c_device_info_t g_mma8451_i2c_device = { HW_I2C3, 0x1C, 170000 };
+#endif
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/board/common/board_i2c.h

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__BOARD_I2C_H__)
+#define __BOARD_I2C_H__
+
+#include "sdk_types.h"
+#include "i2c/imx_i2c.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Externs
+////////////////////////////////////////////////////////////////////////////////
+
+//! @name Audio codecs
+//@{
+extern const i2c_device_info_t g_wm8958_i2c_device;
+extern const i2c_device_info_t g_wm8962_i2c_device;
+extern const i2c_device_info_t g_sgtl5000_i2c_device;
+extern const i2c_device_info_t g_cs42888_i2c_device;
+//@}
+
+//! @name PMICs
+//@{
+extern const i2c_device_info_t g_pmic_ltc3589_i2c_device;
+extern const i2c_device_info_t g_pmic_da9053_i2c_device;
+extern const i2c_device_info_t g_pmic_pf0100_i2c_device;
+extern const i2c_device_info_t g_pmic_max17135_i2c_device;
+//@}
+
+//! @brief ADV7180 video decoder
+extern const i2c_device_info_t g_adv7180_i2c_device;
+
+//! @brief OS81050 MLB MOST controller
+extern const i2c_device_info_t g_os81050_i2c_device;
+
+//! @brief P1003 touch screen controller
+extern const i2c_device_info_t g_p1003_tsc_i2c_device;
+
+//! @brief AT24Cxx EEPROM
+extern const i2c_device_info_t g_at24cx_i2c_device;
+
+//! @brief Si476x FM tuner
+extern const i2c_device_info_t g_si476x_i2c_device;
+
+//! @brief MMA8451 accelerometer.
+extern const i2c_device_info_t g_mma8451_i2c_device;
+
+#endif // __BOARD_I2C_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/board/common/board_io_expanders.c

@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sdk.h"
+#include "board_io_expanders.h"
+#include "registers/regsi2c.h"
+#include "registers/regsiomuxc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Globals
+////////////////////////////////////////////////////////////////////////////////
+
+imx_i2c_request_t max7310_i2c_req_array[MAX7310_NBR];
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+void board_ioexpander_init(void)
+{
+#if defined(BOARD_SABRE_AI)
+    // Bring max7310 out of reset
+    // (this iomux setting should be done in gpio_iomux_config())
+    gpio_set_gpio(GPIO_PORT1, 15);
+    gpio_set_direction(GPIO_PORT1, 15, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT1, 15, GPIO_HIGH_LEVEL);
+ 
+    // for I2C3 steering
+    // Select ALT5 mode of EIM_A24 for GPIO5_4 - EIMD18_I2C3_STEER(EIM_A24)
+    // high output to select I2C3 option
+    // (this iomux setting should be done in gpio_iomux_config())
+    gpio_set_gpio(GPIO_PORT5, 4);
+    gpio_set_direction(GPIO_PORT5, 4, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT5, 4, GPIO_HIGH_LEVEL);
+#endif
+
+    // Build array of I2C request structures.
+#if defined(BOARD_EVB) || defined(BOARD_SABRE_AI)
+    // Configure some board signals through I/O expanders
+    max7310_i2c_req_array[0].ctl_addr = HW_I2C3; // the I2C controller base address
+    max7310_i2c_req_array[0].dev_addr = MAX7310_I2C_ID0;    // the I2C DEVICE address
+    max7310_init(0, MAX7310_ID0_DEF_DIR, MAX7310_ID0_DEF_VAL);
+    
+    max7310_i2c_req_array[1].ctl_addr = HW_I2C3; // the I2C controller base address
+    max7310_i2c_req_array[1].dev_addr = MAX7310_I2C_ID1;    // the I2C DEVICE address
+    max7310_init(1, MAX7310_ID1_DEF_DIR, MAX7310_ID1_DEF_VAL);
+#endif
+#if defined(BOARD_SABRE_AI)
+    max7310_i2c_req_array[2].ctl_addr = HW_I2C3; // the I2C controller base address
+    max7310_i2c_req_array[2].dev_addr = MAX7310_I2C_ID2;    // the I2C DEVICE address
+    max7310_init(2, MAX7310_ID2_DEF_DIR, MAX7310_ID2_DEF_VAL);
+#endif
+}
+
+void board_ioexpander_iomux_config(void)
+{
+#if defined(BOARD_SABRE_AI)
+
+    i2c3_iomux_config();
+
+#if !defined(BOARD_REV_A)
+    /*
+     * for I2C3 steering:
+     *
+     * i2c3_iomux_config() selected ALT5 mode of EIM_A24
+     * for GPIO5_4 - EIMD18_I2C3_STEER(EIM_A24)
+     *
+     * high output to select I2C3 option
+     */
+    gpio_set_direction(GPIO_PORT5, 4, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT5, 4, GPIO_HIGH_LEVEL);
+
+#endif // !defined(BOARD_REV_A)
+
+#endif // defined(BOARD_SABRE_AI)
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/board/common/board_io_expanders.h

@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__BOARD_IO_EXPANDERS_H__)
+#define __BOARD_IO_EXPANDERS_H__
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+/* 
+ * BOARD_SMART_DEVICE for compile error
+ */
+#if defined(BOARD_SMART_DEVICE)
+#define MAX7310_NBR 0
+#endif
+
+/* For the ARD board which has 3 MAX7310 */
+#ifdef BOARD_SABRE_AI
+#define MAX7310_NBR 3
+
+/* I/O expander A */
+#define MAX7310_I2C_BASE_ID0     3
+#define MAX7310_I2C_ID0          0x30
+#define MAX7310_ID0_DEF_DIR      0x00   // init direction for the I/O
+#define MAX7310_ID0_DEF_VAL      0xFF   // init value for the output
+
+/* I/O expander B */
+#define MAX7310_I2C_BASE_ID1     3
+#define MAX7310_I2C_ID1          0x32
+#define MAX7310_ID1_DEF_DIR      0x00   // init direction for the I/O
+#define MAX7310_ID1_DEF_VAL      0xE7   // init value for the output
+
+/* I/O expander C */
+#define MAX7310_I2C_BASE_ID2     3
+#define MAX7310_I2C_ID2          0x34
+#define MAX7310_ID2_DEF_DIR      0x00   // init direction for the I/O
+#define MAX7310_ID2_DEF_VAL      0x57   // init value for the output
+#endif
+
+#ifdef BOARD_EVB
+/* For the EVB board which has 2 MAX7310 */
+#define MAX7310_NBR 2
+
+/* Number 1 controls: BACKLIGHT_ON, PORT3_P114, CPU_PER_RST_B, PORT3_P110,
+   PORT3_P105, PORT3_P112, PORT3_P107, PORT3_P109.
+*/
+#define MAX7310_I2C_BASE_ID0     3
+#define MAX7310_I2C_ID0          (0x36 >> 1)
+#define MAX7310_ID0_DEF_DIR      0x00   // init direction for the I/O
+#define MAX7310_ID0_DEF_VAL      0xFF   // init value for the output
+
+/* Number 2 controls: CTRL_0, CTRL_1, CTRL_2, CTRL_3, CTRL_4, PORT3_P116,
+   PORT2_P81, PORT3_P101
+*/
+#define MAX7310_I2C_BASE_ID1     3
+#define MAX7310_I2C_ID1          (0x3E >> 1)
+#define MAX7310_ID1_DEF_DIR      0x00   // init direction for the I/O
+#define MAX7310_ID1_DEF_VAL      0x09   // init value for the output
+#endif
+
+////////////////////////////////////////////////////////////////////////////////
+// Globals
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Array of I2C requests for all used expanders on the board.
+//!
+//! This array is primarily used to pass details about I2C addresses and ports
+//! to the max7310 driver.
+extern imx_i2c_request_t max7310_i2c_req_array[];
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Init the array of I/O expanders.
+ */
+void board_ioexpander_init(void);
+
+/*!
+ * @brief Configure the IOMUX so we can access the I/O expander.
+ */
+void board_ioexpander_iomux_config(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif // __BOARD_IO_EXPANDERS_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6sx/iMX6_Platform_SDK/board/common/board_mipi.c

@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sdk.h"
+#include "registers/regsccm.h"
+#include "registers/regsccmanalog.h"
+#include "registers/regsiomuxc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+/*!
+ * Provide the mipi camera power and reset
+ */
+void mipi_cam_power_on(void)
+{
+#if defined(BOARD_EVB)
+    board_ioexpander_iomux_config();
+    /*reset of camera sensor, pin 27 */
+    max7310_set_gpio_output(0, 2, GPIO_LOW_LEVEL);
+    hal_delay_us(1000);
+    max7310_set_gpio_output(0, 2, GPIO_HIGH_LEVEL);
+
+    /*power supply through pin25 of connector, for cam_pdown, power down and then up */
+    max7310_set_gpio_output(0, 0, GPIO_LOW_LEVEL);
+    hal_delay_us(1000);
+    max7310_set_gpio_output(0, 0, GPIO_HIGH_LEVEL);
+//    max7310_set_gpio_output(1, 1, GPIO_HIGH_LEVEL);
+#endif
+
+#if defined(BOARD_SABRE_AI)
+    board_ioexpander_iomux_config();
+    /*power supply through pin25 of connector, direct connected to P3V3_DELAY,
+       controlled by CPU_PER_RST_B */
+    /*reset of camera sensor, together with the reset button */
+    max7310_set_gpio_output(0, 2, GPIO_LOW_LEVEL);
+    hal_delay_us(1000);
+    max7310_set_gpio_output(0, 2, GPIO_HIGH_LEVEL);
+    max7310_set_gpio_output(0, 0, GPIO_HIGH_LEVEL);
+
+#endif
+
+#if defined(BOARD_SMART_DEVICE)
+    /*power supply through pin25 of connector, for cam_pdown */
+    gpio_set_gpio(GPIO_PORT6, 9);
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_V(100K_OHM_PU) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE_V(SLOW));
+    gpio_set_direction(GPIO_PORT6, 9, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT6, 9, GPIO_HIGH_LEVEL);
+
+    /*reset of camera sensor, pin 27 */
+    gpio_set_gpio(GPIO_PORT6, 10);
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUS_V(100K_OHM_PU) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_SRE_V(SLOW));
+    gpio_set_direction(GPIO_PORT6, 10, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT6, 10, GPIO_LOW_LEVEL);
+    hal_delay_us(1000);
+    gpio_set_level(GPIO_PORT6, 10, GPIO_HIGH_LEVEL);
+#endif
+}
+
+/*!
+ * enable mipi backlight
+ */
+void mipi_backlight_en(void)
+{
+    //configure pin19 of the mipi dsi/csi connector
+#ifdef BOARD_EVB
+    //set GPIO1_9 to 0 so clear vbus on board
+    gpio_set_direction(GPIO_PORT1, 9, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT1, 9, GPIO_HIGH_LEVEL);
+#endif
+
+#ifdef BOARD_SABRE_AI
+    //default be populated by P3V3_DELAYED
+#endif
+
+#ifdef BOARD_SMART_DEVICE
+    gpio_set_gpio(GPIO_PORT2, 0);
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_V(100K_OHM_PU) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE_V(SLOW));
+    gpio_set_direction(GPIO_PORT2, 0, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT2, 0, GPIO_HIGH_LEVEL);
+#endif
+}
+
+/*!
+ * reset MIPI display
+ */
+void mipi_display_reset(void)
+{
+#ifdef BOARD_EVB
+/*pin29 of mipi connector for the LCD reset*/
+    gpio_set_gpio(GPIO_PORT5, 0);
+    HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS_V(100K_OHM_PU) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE_V(SLOW));
+    gpio_set_direction(GPIO_PORT5, 0, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT5, 0, GPIO_LOW_LEVEL);
+    hal_delay_us(1000);
+    gpio_set_level(GPIO_PORT5, 0, GPIO_HIGH_LEVEL);
+    hal_delay_us(1000);
+#endif
+
+#ifdef BOARD_SABRE_AI
+/*binded with the board reset button*/
+#endif
+
+#ifdef BOARD_SMART_DEVICE
+/*pin29 of mipi connector for the LCD reset*/
+    gpio_set_gpio(GPIO_PORT6, 11);
+    HW_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUS_V(100K_OHM_PU) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B_SRE_V(SLOW));
+    gpio_set_direction(GPIO_PORT6, 11, GPIO_GDIR_OUTPUT);
+    gpio_set_level(GPIO_PORT6, 11, GPIO_LOW_LEVEL);
+    hal_delay_us(1000);
+    gpio_set_level(GPIO_PORT6, 11, GPIO_HIGH_LEVEL);
+    hal_delay_us(1000);
+#endif
+}
+
+void mipi_clock_set(void)
+{
+    BW_CCM_ANALOG_PFD_480_PFD1_FRAC(0x10);
+}
+
+void mipi_csi2_clock_set(void)
+{
+    //set VIDPLL(PLL5) to 596MHz 
+    HW_CCM_ANALOG_PLL_VIDEO_WR(BF_CCM_ANALOG_PLL_VIDEO_DIV_SELECT(0) |
+                               BF_CCM_ANALOG_PLL_VIDEO_ENABLE(1));
+    HW_CCM_ANALOG_PLL_VIDEO_NUM_WR(0x00000000);
+    HW_CCM_ANALOG_PLL_VIDEO_DENOM_WR(0x00000001);
+    while (!HW_CCM_ANALOG_PLL_VIDEO.B.LOCK) ;   //waiting for PLL lock
+    BF_CLR(CCM_ANALOG_PLL_VIDEO, BYPASS);
+
+    //select CSI0_HSYNC osc_clk 24MHz, CKO1 output drives cko2 clock
+    HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_SION_V(DISABLED) |
+            BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_MUX_MODE_V(ALT3));
+
+    HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_HYS_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUS_V(100K_OHM_PU) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PUE_V(PULL) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_PKE_V(ENABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_ODE_V(DISABLED) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SPEED_V(100MHZ) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_DSE_V(40_OHM) |
+            BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_SRE_V(SLOW));
+
+    HW_CCM_CCOSR_WR(
+                    BF_CCM_CCOSR_CLKO1_SEL(0) |
+                    BF_CCM_CCOSR_CLKO1_DIV(0) |
+                    BF_CCM_CCOSR_CLKO1_EN(1) |
+                    BF_CCM_CCOSR_CLKO_SEL(1) |       // select cko2 for cko1 output
+                    BF_CCM_CCOSR_CLKO2_SEL(0xe) |    // osc_clk
+                    BF_CCM_CCOSR_CLKO2_DIV(0) |      // div 1
+                    BF_CCM_CCOSR_CLKO2_EN(1));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////