[bsp/nxp] add new imxrt series

.travis.yml

@@ -34,7 +34,10 @@ env:
   - RTT_BSP='gd32303e-eval' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='gd32450z-eval' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='gkipc' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imxrt/imxrt1050-evk' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='imx6sx/cortex-a9' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='imxrt/imxrt1052-atk-commander' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='imxrt/imxrt1052-fire-pro' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='imxrt/imxrt1052-nxp-evk' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm'
@@ -52,7 +55,6 @@ env:
 #  - RTT_BSP='lpc54608-LPCXpresso' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='ls1bdev' RTT_TOOL_CHAIN='sourcery-mips'
   - RTT_BSP='ls1cdev' RTT_TOOL_CHAIN='sourcery-mips'
-  - RTT_BSP='imx6sx/cortex-a9' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='m16c62p' # m32c
   - RTT_BSP='mb9bf500r' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='mb9bf506r' RTT_TOOL_CHAIN='sourcery-arm'
@@ -70,6 +72,7 @@ env:
   - RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='sam7x' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='simulator' # x86
+  - RTT_BSP='stm32/stm32f072-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f091-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f103-atk-nano' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f103-atk-warshipv3' RTT_TOOL_CHAIN='sourcery-arm'
@@ -78,6 +81,7 @@ env:
   - RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f103-hw100k-ibox' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f103-mini-system' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-yf-ufun' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f107-uc-eval' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f401-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f405-smdz-breadfruit' RTT_TOOL_CHAIN='sourcery-arm'

bsp/imxrt/Libraries/Kconfig

@@ -0,0 +1,24 @@
+config SOC_IMXRT1015_SERIES
+    bool
+    select ARCH_ARM_CORTEX_M7
+    select ARCH_ARM_CORTEX_FPU
+
+config SOC_IMXRT1020_SERIES
+    bool
+    select ARCH_ARM_CORTEX_M7
+    select ARCH_ARM_CORTEX_FPU
+
+config SOC_IMXRT1050_SERIES
+    bool
+    select ARCH_ARM_CORTEX_M7
+    select ARCH_ARM_CORTEX_FPU
+
+config SOC_IMXRT1060_SERIES
+    bool
+    select ARCH_ARM_CORTEX_M7
+    select ARCH_ARM_CORTEX_FPU
+
+config SOC_IMXRT1064_SERIES
+    bool
+    select ARCH_ARM_CORTEX_M7
+    select ARCH_ARM_CORTEX_FPU

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/DriverTemplates/Driver_CAN.c

@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2015-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_CAN.h"
+
+#define ARM_CAN_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) // CAN driver version
+
+// Driver Version
+static const ARM_DRIVER_VERSION can_driver_version = { ARM_CAN_API_VERSION, ARM_CAN_DRV_VERSION };
+
+// Driver Capabilities
+static const ARM_CAN_CAPABILITIES can_driver_capabilities = {
+  32U,  // Number of CAN Objects available
+  1U,   // Supports reentrant calls to ARM_CAN_MessageSend, ARM_CAN_MessageRead, ARM_CAN_ObjectConfigure and abort message sending used by ARM_CAN_Control.
+  0U,   // Does not support CAN with Flexible Data-rate mode (CAN_FD)
+  0U,   // Does not support restricted operation mode
+  1U,   // Supports bus monitoring mode
+  1U,   // Supports internal loopback mode
+  1U,   // Supports external loopback mode
+};
+
+// Object Capabilities
+static const ARM_CAN_OBJ_CAPABILITIES can_object_capabilities = {
+  1U,   // Object supports transmission
+  1U,   // Object supports reception
+  0U,   // Object does not support RTR reception and automatic Data transmission
+  0U,   // Object does not support RTR transmission and automatic Data reception
+  1U,   // Object allows assignment of multiple filters to it
+  1U,   // Object supports exact identifier filtering
+  0U,   // Object does not support range identifier filtering
+  1U,   // Object supports mask identifier filtering
+  3U    // Object can buffer 3 messages
+};
+
+static uint8_t                     can_driver_powered     = 0U;
+static uint8_t                     can_driver_initialized = 0U;
+static ARM_CAN_SignalUnitEvent_t   CAN_SignalUnitEvent    = NULL;
+static ARM_CAN_SignalObjectEvent_t CAN_SignalObjectEvent  = NULL;
+
+//
+//   Functions
+//
+
+static ARM_DRIVER_VERSION CAN_GetVersion (void) {
+  // Return driver version
+  return can_driver_version;
+}
+
+static ARM_CAN_CAPABILITIES CAN_GetCapabilities (void) {
+  // Return driver capabilities
+  return can_driver_capabilities;
+}
+
+static int32_t CAN_Initialize (ARM_CAN_SignalUnitEvent_t   cb_unit_event,
+                               ARM_CAN_SignalObjectEvent_t cb_object_event) {
+
+  if (can_driver_initialized != 0U) { return ARM_DRIVER_OK; }
+
+  CAN_SignalUnitEvent   = cb_unit_event;
+  CAN_SignalObjectEvent = cb_object_event;
+
+  // Add code for pin, memory, RTX objects initialization
+  // ..
+
+  can_driver_initialized = 1U;
+
+  return ARM_DRIVER_OK;
+}
+
+static int32_t CAN_Uninitialize (void) {
+
+  // Add code for pin, memory, RTX objects de-initialization
+  // ..
+
+  can_driver_initialized = 0U;
+
+  return ARM_DRIVER_OK;
+}
+
+static int32_t CAN_PowerControl (ARM_POWER_STATE state) {
+  switch (state) {
+    case ARM_POWER_OFF:
+      can_driver_powered = 0U;
+      // Add code to disable interrupts and put peripheral into reset mode,
+      // and if possible disable clock
+      // ..
+
+    case ARM_POWER_FULL:
+      if (can_driver_initialized == 0U) { return ARM_DRIVER_ERROR; }
+      if (can_driver_powered     != 0U) { return ARM_DRIVER_OK;    }
+
+      // Add code to enable clocks, reset variables enable interrupts
+      // and put peripheral into operational
+      // ..
+
+      can_driver_powered = 1U;
+      break;
+
+    default:
+      // Other states are not supported
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+uint32_t CAN_GetClock (void) {
+
+  // Add code to return peripheral clock frequency
+  // ..
+}
+
+static int32_t CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
+
+  // Add code to setup peripheral parameters to generate specified bitrate
+  // with specified bit segments
+  // ..
+
+  return ARM_DRIVER_OK;
+}
+
+static int32_t CAN_SetMode (ARM_CAN_MODE mode) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
+
+  switch (mode) {
+    case ARM_CAN_MODE_INITIALIZATION:
+      // Add code to put peripheral into initialization mode
+      // ..
+      break;
+    case ARM_CAN_MODE_NORMAL:
+      // Add code to put peripheral into normal operation mode
+      // ..
+      break;
+    case ARM_CAN_MODE_RESTRICTED:
+      // Add code to put peripheral into restricted operation mode
+      // ..
+      break;
+    case ARM_CAN_MODE_MONITOR:
+      // Add code to put peripheral into bus monitoring mode
+      // ..
+      break;
+    case ARM_CAN_MODE_LOOPBACK_INTERNAL:
+      // Add code to put peripheral into internal loopback mode
+      // ..
+      break;
+    case ARM_CAN_MODE_LOOPBACK_EXTERNAL:
+      // Add code to put peripheral into external loopback mode
+      // ..
+      break;
+    default:
+      // Handle unknown mode code
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+ARM_CAN_OBJ_CAPABILITIES CAN_ObjectGetCapabilities (uint32_t obj_idx) {
+  // Return object capabilities
+  return can_object_capabilities;
+}
+
+static int32_t CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
+
+  switch (operation) {
+    case ARM_CAN_FILTER_ID_EXACT_ADD:
+      // Add code to setup peripheral to receive messages with specified exact ID
+      break;
+    case ARM_CAN_FILTER_ID_MASKABLE_ADD:
+      // Add code to setup peripheral to receive messages with specified maskable ID
+      break;
+    case ARM_CAN_FILTER_ID_RANGE_ADD:
+      // Add code to setup peripheral to receive messages within specified range of IDs
+      break;
+    case ARM_CAN_FILTER_ID_EXACT_REMOVE:
+      // Add code to remove specified exact ID from being received by peripheral
+      break;
+    case ARM_CAN_FILTER_ID_MASKABLE_REMOVE:
+      // Add code to remove specified maskable ID from being received by peripheral
+      break;
+    case ARM_CAN_FILTER_ID_RANGE_REMOVE:
+      // Add code to remove specified range of IDs from being received by peripheral
+      break;
+    default:
+      // Handle unknown operation code
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+static int32_t CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
+
+  switch (obj_cfg) {
+    case ARM_CAN_OBJ_INACTIVE:
+      // Deactivate object
+      // ..
+      break;
+    case ARM_CAN_OBJ_RX_RTR_TX_DATA:
+      // Setup object to automatically return data when RTR with it's ID is received
+      // ..
+      break;
+    case ARM_CAN_OBJ_TX_RTR_RX_DATA:
+      // Setup object to send RTR and receive data response
+      // ..
+      break;
+    case ARM_CAN_OBJ_TX:
+      // Setup object to be used for sending messages
+      // ..
+      break;
+    case ARM_CAN_OBJ_RX:
+      // Setup object to be used for receiving messages
+      // ..
+      break;
+    default:
+      // Handle unknown object configuration code
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+static int32_t CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
+
+  // Add code to send requested message
+  // ..
+
+  return ((int32_t)size);
+}
+
+static int32_t CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR;  }
+
+  // Add code to read previously received message
+  // (reception was started when object was configured for reception)
+  // ..
+
+  return ((int32_t)size);
+}
+
+static int32_t CAN_Control (uint32_t control, uint32_t arg) {
+
+  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
+
+  switch (control & ARM_CAN_CONTROL_Msk) {
+    case ARM_CAN_ABORT_MESSAGE_SEND:
+      // Add code to abort message pending to be sent
+      // ..
+      break;
+    case ARM_CAN_SET_FD_MODE:
+      // Add code to enable Flexible Data-rate mode
+      // ..
+      break;
+    case ARM_CAN_SET_TRANSCEIVER_DELAY:
+      // Add code to set transceiver delay
+      // ..
+      break;
+    default:
+      // Handle unknown control code
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+static ARM_CAN_STATUS CAN_GetStatus (void) {
+
+  // Add code to return device bus and error status
+  // ..
+}
+
+
+// IRQ handlers
+// Add interrupt routines to handle transmission, reception, error and status interrupts
+// ..
+
+// CAN driver functions structure
+
+ARM_DRIVER_CAN Driver_CAN = {
+  CAN_GetVersion,
+  CAN_GetCapabilities,
+  CAN_Initialize,
+  CAN_Uninitialize,
+  CAN_PowerControl,
+  CAN_GetClock,
+  CAN_SetBitrate,
+  CAN_SetMode,
+  CAN_ObjectGetCapabilities,
+  CAN_ObjectSetFilter,
+  CAN_ObjectConfigure,
+  CAN_MessageSend,
+  CAN_MessageRead,
+  CAN_Control,
+  CAN_GetStatus
+};
+

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c

@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_ETH_MAC.h"
+
+#define ARM_ETH_MAC_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_ETH_MAC_API_VERSION,
+    ARM_ETH_MAC_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_ETH_MAC_CAPABILITIES DriverCapabilities = {
+    0, /* 1 = IPv4 header checksum verified on receive */
+    0, /* 1 = IPv6 checksum verification supported on receive */
+    0, /* 1 = UDP payload checksum verified on receive */
+    0, /* 1 = TCP payload checksum verified on receive */
+    0, /* 1 = ICMP payload checksum verified on receive */
+    0, /* 1 = IPv4 header checksum generated on transmit */
+    0, /* 1 = IPv6 checksum generation supported on transmit */
+    0, /* 1 = UDP payload checksum generated on transmit */
+    0, /* 1 = TCP payload checksum generated on transmit */
+    0, /* 1 = ICMP payload checksum generated on transmit */
+    0, /* Ethernet Media Interface type */
+    0, /* 1 = driver provides initial valid MAC address */
+    0, /* 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated */
+    0, /* 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated */
+    0, /* 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated */
+    0  /* 1 = Precision Timer supported */
+};
+
+//
+//  Functions
+//
+
+ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion(void)
+{
+}
+
+ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities(void)
+{
+}
+
+int32_t ARM_ETH_MAC_Initialize(ARM_ETH_MAC_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_ETH_MAC_Uninitialize(void)
+{
+}
+
+int32_t ARM_ETH_MAC_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_ETH_MAC_GetMacAddress(ARM_ETH_MAC_ADDR *ptr_addr)
+{
+}
+
+int32_t ARM_ETH_MAC_SetMacAddress(const ARM_ETH_MAC_ADDR *ptr_addr)
+{
+}
+
+int32_t ARM_ETH_MAC_SetAddressFilter(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr)
+{
+}
+
+int32_t ARM_ETH_MAC_SendFrame(const uint8_t *frame, uint32_t len, uint32_t flags)
+{
+}
+
+int32_t ARM_ETH_MAC_ReadFrame(uint8_t *frame, uint32_t len)
+{
+}
+
+uint32_t ARM_ETH_MAC_GetRxFrameSize(void)
+{
+}
+
+int32_t ARM_ETH_MAC_GetRxFrameTime(ARM_ETH_MAC_TIME *time)
+{
+}
+
+int32_t ARM_ETH_MAC_GetTxFrameTime(ARM_ETH_MAC_TIME *time)
+{
+}
+
+int32_t ARM_ETH_MAC_Control(uint32_t control, uint32_t arg)
+{
+    switch (control)
+    {
+    case ARM_ETH_MAC_CONFIGURE:
+
+        switch (arg & ARM_ETH_MAC_SPEED_Msk)
+        {
+        case ARM_ETH_MAC_SPEED_10M:
+            break;
+        case ARM_ETH_SPEED_100M:
+            break;
+        default:
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+
+        switch (arg & ARM_ETH_MAC_DUPLEX_Msk)
+        {
+        case ARM_ETH_MAC_DUPLEX_FULL:
+            break;
+        }
+
+        if (arg & ARM_ETH_MAC_LOOPBACK)
+        {
+        }
+
+        if ((arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX) ||
+            (arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX))
+        {
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+
+        if (!(arg & ARM_ETH_MAC_ADDRESS_BROADCAST))
+        {
+        }
+
+        if (arg & ARM_ETH_MAC_ADDRESS_MULTICAST)
+        {
+        }
+
+        if (arg & ARM_ETH_MAC_ADDRESS_ALL)
+        {
+        }
+
+        break;
+
+    case ARM_ETH_MAC_CONTROL_TX:
+        break;
+
+    case ARM_ETH_MAC_CONTROL_RX:
+        break;
+
+    case ARM_ETH_MAC_FLUSH:
+        if (arg & ARM_ETH_MAC_FLUSH_RX)
+        {
+        }
+        if (arg & ARM_ETH_MAC_FLUSH_TX)
+        {
+        }
+        break;
+
+    case ARM_ETH_MAC_SLEEP:
+        break;
+
+    case ARM_ETH_MAC_VLAN_FILTER:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_ETH_MAC_ControlTimer(uint32_t control, ARM_ETH_MAC_TIME *time)
+{
+}
+
+int32_t ARM_ETH_MAC_PHY_Read(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
+{
+}
+
+int32_t ARM_ETH_MAC_PHY_Write(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
+{
+}
+
+void ARM_ETH_MAC_SignalEvent(uint32_t event)
+{
+}
+
+// End ETH MAC Interface
+
+ARM_DRIVER_ETH_MAC Driver_ETH_MAC =
+{
+    ARM_ETH_MAC_GetVersion,
+    ARM_ETH_MAC_GetCapabilities,
+    ARM_ETH_MAC_Initialize,
+    ARM_ETH_MAC_Uninitialize,
+    ARM_ETH_MAC_PowerControl,
+    ARM_ETH_MAC_GetMacAddress,
+    ARM_ETH_MAC_SetMacAddress,
+    ARM_ETH_MAC_SetAddressFilter,
+    ARM_ETH_MAC_SendFrame,
+    ARM_ETH_MAC_ReadFrame,
+    ARM_ETH_MAC_GetRxFrameSize,
+    ARM_ETH_MAC_GetRxFrameTime,
+    ARM_ETH_MAC_GetTxFrameTime,
+    ARM_ETH_MAC_ControlTimer,
+    ARM_ETH_MAC_Control,
+    ARM_ETH_MAC_PHY_Read,
+    ARM_ETH_MAC_PHY_Write
+};

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c

@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_ETH_PHY.h"
+
+#define ARM_ETH_PHY_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_ETH_PHY_API_VERSION,
+    ARM_ETH_PHY_DRV_VERSION
+};
+
+//
+// Functions
+//
+
+ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion(void)
+{
+}
+
+int32_t ARM_ETH_PHY_Initialize(ARM_ETH_PHY_Read_t fn_read, ARM_ETH_PHY_Write_t fn_write)
+{
+}
+
+int32_t ARM_ETH_PHY_Uninitialize(void)
+{
+}
+
+int32_t ARM_ETH_PHY_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_ETH_PHY_SetInterface(uint32_t interface)
+{
+    switch (interface)
+    {
+    case ARM_ETH_INTERFACE_MII:
+        break;
+    case ARM_ETH_INTERFACE_RMII:
+        break;
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_ETH_PHY_SetMode(uint32_t mode)
+{
+    switch (mode & ARM_ETH_PHY_SPEED_Msk)
+    {
+    case ARM_ETH_PHY_SPEED_10M:
+        break;
+    case ARM_ETH_PHY_SPEED_100M:
+        break;
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+
+    switch (mode & ARM_ETH_PHY_DUPLEX_Msk)
+    {
+    case ARM_ETH_PHY_DUPLEX_HALF:
+        break;
+    case ARM_ETH_PHY_DUPLEX_FULL:
+        break;
+    }
+
+    if (mode & ARM_ETH_PHY_AUTO_NEGOTIATE)
+    {
+    }
+
+    if (mode & ARM_ETH_PHY_LOOPBACK)
+    {
+    }
+
+    if (mode & ARM_ETH_PHY_ISOLATE)
+    {
+    }
+}
+
+ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState(void)
+{
+}
+
+ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo(void)
+{
+}
+
+ARM_DRIVER_ETH_PHY ARM_Driver_ETH_PHY_(ETH_PHY_NUM) =
+{
+    ARM_ETH_PHY_GetVersion,
+    ARM_ETH_PHY_Initialize,
+    ARM_ETH_PHY_Uninitialize,
+    ARM_ETH_PHY_PowerControl,
+    ARM_ETH_PHY_SetInterface,
+    ARM_ETH_PHY_SetMode,
+    ARM_ETH_PHY_GetLinkState,
+    ARM_ETH_PHY_GetLinkInfo,
+};

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/DriverTemplates/Driver_Flash.c

@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_Flash.h"
+
+#define ARM_FLASH_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Sector Information */
+#ifdef FLASH_SECTORS
+static ARM_FLASH_SECTOR FLASH_SECTOR_INFO[FLASH_SECTOR_COUNT] = {
+    FLASH_SECTORS
+};
+#else
+#define FLASH_SECTOR_INFO    NULL
+#endif
+
+/* Flash Information */
+static ARM_FLASH_INFO FlashInfo = {
+    0, /* FLASH_SECTOR_INFO  */
+    0, /* FLASH_SECTOR_COUNT */
+    0, /* FLASH_SECTOR_SIZE  */
+    0, /* FLASH_PAGE_SIZE    */
+    0, /* FLASH_PROGRAM_UNIT */
+    0  /* FLASH_ERASED_VALUE */
+};
+
+/* Flash Status */
+static ARM_FLASH_STATUS FlashStatus;
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_FLASH_API_VERSION,
+    ARM_FLASH_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_FLASH_CAPABILITIES DriverCapabilities = {
+    0, /* event_ready */
+    0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */
+    0  /* erase_chip */
+};
+
+//
+// Functions
+//
+
+ARM_DRIVER_VERSION ARM_Flash_GetVersion(void)
+{
+}
+
+ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void)
+{
+}
+
+int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_Flash_Uninitialize(void)
+{
+}
+
+int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt)
+{
+}
+
+int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, uint32_t cnt)
+{
+}
+
+int32_t ARM_Flash_EraseSector(uint32_t addr)
+{
+}
+
+int32_t ARM_Flash_EraseChip(void)
+{
+}
+
+ARM_FLASH_STATUS ARM_Flash_GetStatus(void)
+{
+}
+
+ARM_FLASH_INFO * ARM_Flash_GetInfo(void)
+{
+}
+
+void ARM_Flash_SignalEvent(uint32_t event)
+{
+}
+// End Flash Interface
+
+ARM_DRIVER_FLASH Driver_FLASH = {
+    ARM_Flash_GetVersion,
+    ARM_Flash_GetCapabilities,
+    ARM_Flash_Initialize,
+    ARM_Flash_Uninitialize,
+    ARM_Flash_PowerControl,
+    ARM_Flash_ReadData,
+    ARM_Flash_ProgramData,
+    ARM_Flash_EraseSector,
+    ARM_Flash_EraseChip,
+    ARM_Flash_GetStatus,
+    ARM_Flash_GetInfo
+};

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/DriverTemplates/Driver_I2C.c

@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_I2C.h"
+
+#define ARM_I2C_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_I2C_API_VERSION,
+    ARM_I2C_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_I2C_CAPABILITIES DriverCapabilities = {
+    0  /* supports 10-bit addressing */
+};
+
+//
+//  Functions
+//
+
+ARM_DRIVER_VERSION ARM_I2C_GetVersion(void)
+{
+}
+
+ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities(void)
+{
+}
+
+int32_t ARM_I2C_Initialize(ARM_I2C_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_I2C_Uninitialize(void)
+{
+}
+
+int32_t ARM_I2C_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_I2C_MasterTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+{
+}
+
+int32_t ARM_I2C_MasterReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+{
+}
+
+int32_t ARM_I2C_SlaveTransmit(const uint8_t *data, uint32_t num)
+{
+}
+
+int32_t ARM_I2C_SlaveReceive(uint8_t *data, uint32_t num)
+{
+}
+
+int32_t ARM_I2C_GetDataCount(void)
+{
+}
+
+int32_t ARM_I2C_Control(uint32_t control, uint32_t arg)
+{
+    switch (control)
+    {
+    case ARM_I2C_OWN_ADDRESS:
+        break;
+
+    case ARM_I2C_BUS_SPEED:
+        switch (arg)
+        {
+        case ARM_I2C_BUS_SPEED_STANDARD:
+            break;
+        case ARM_I2C_BUS_SPEED_FAST:
+            break;
+        case ARM_I2C_BUS_SPEED_FAST_PLUS:
+            break;
+        default:
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+        break;
+
+    case ARM_I2C_BUS_CLEAR:
+        break;
+
+    case ARM_I2C_ABORT_TRANSFER:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+ARM_I2C_STATUS ARM_I2C_GetStatus(void)
+{
+}
+
+void ARM_I2C_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End I2C Interface
+
+ARM_DRIVER_I2C Driver_I2C = {
+    ARM_I2C_GetVersion,
+    ARM_I2C_GetCapabilities,
+    ARM_I2C_Initialize,
+    ARM_I2C_Uninitialize,
+    ARM_I2C_PowerControl,
+    ARM_I2C_MasterTransmit,
+    ARM_I2C_MasterReceive,
+    ARM_I2C_SlaveTransmit,
+    ARM_I2C_SlaveReceive,
+    ARM_I2C_GetDataCount,
+    ARM_I2C_Control,
+    ARM_I2C_GetStatus
+};

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/DriverTemplates/Driver_MCI.c

@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_MCI.h"
+
+#define ARM_MCI_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_MCI_API_VERSION,
+    ARM_MCI_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_MCI_CAPABILITIES DriverCapabilities = {
+    0, /* cd_state          */
+    0, /* cd_event          */
+    0, /* vdd               */
+    0, /* vdd_1v8           */
+    0, /* vccq              */
+    0, /* vccq_1v8          */
+    0, /* vccq_1v2          */
+    1, /* data_width_4      */
+    1, /* data_width_8      */
+    0, /* data_width_4_ddr  */
+    0, /* data_width_8_ddr  */
+    0, /* high_speed        */
+    0, /* uhs_signaling     */
+    0, /* uhs_tuning        */
+    0, /* uhs_sdr50         */
+    0, /* uhs_sdr104        */
+    0, /* uhs_ddr50         */
+    0, /* uhs_driver_type_a */
+    0, /* uhs_driver_type_c */
+    0, /* uhs_driver_type_d */
+    1, /* sdio_interrupt    */
+    1, /* read_wait         */
+    0, /* suspend_resume    */
+    0, /* mmc_interrupt     */
+    0, /* mmc_boot          */
+    0, /* ccs               */
+    0  /* ccs_timeout       */
+};
+
+//
+//   Functions
+//
+
+ARM_DRIVER_VERSION ARM_MCI_GetVersion(void)
+{
+}
+
+ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities(void)
+{
+}
+
+int32_t ARM_MCI_Initialize(ARM_MCI_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_MCI_Uninitialize(void)
+{
+}
+
+int32_t ARM_MCI_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_MCI_CardPower(uint32_t voltage)
+{
+    switch (voltage & ARM_MCI_POWER_VDD_Msk)
+    {
+    case ARM_MCI_POWER_VDD_OFF:
+        return ARM_DRIVER_OK;
+
+    case ARM_MCI_POWER_VDD_3V3:
+        return ARM_DRIVER_OK;
+
+    default:
+        break;
+    }
+}
+
+int32_t ARM_MCI_ReadCD(void)
+{
+}
+
+int32_t ARM_MCI_ReadWP(void)
+{
+}
+
+int32_t ARM_MCI_SendCommand(uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response)
+{
+}
+
+int32_t ARM_MCI_SetupTransfer(uint8_t  *data, uint32_t block_count, uint32_t block_size, uint32_t mode)
+{
+}
+
+int32_t ARM_MCI_AbortTransfer(void)
+{
+}
+
+int32_t ARM_MCI_Control(uint32_t control, uint32_t arg)
+{
+    switch (control)
+    {
+    case ARM_MCI_BUS_SPEED:
+        break;
+
+    case ARM_MCI_BUS_SPEED_MODE:
+        break;
+
+    case ARM_MCI_BUS_CMD_MODE:
+        /* Implement external pull-up control to support MMC cards in open-drain mode */
+        /* Default mode is push-pull and is configured in Driver_MCI0.Initialize()    */
+        if (arg == ARM_MCI_BUS_CMD_PUSH_PULL)
+        {
+            /* Configure external circuit to work in push-pull mode */
+        }
+        else if (arg == ARM_MCI_BUS_CMD_OPEN_DRAIN)
+        {
+            /* Configure external circuit to work in open-drain mode */
+        }
+        else
+        {
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+        break;
+
+    case ARM_MCI_BUS_DATA_WIDTH:
+        switch (arg)
+        {
+        case ARM_MCI_BUS_DATA_WIDTH_1:
+            break;
+        case ARM_MCI_BUS_DATA_WIDTH_4:
+            break;
+        case ARM_MCI_BUS_DATA_WIDTH_8:
+            break;
+        default:
+            return ARM_DRIVER_ERROR_UNSUPPORTED;
+        }
+        break;
+
+    case ARM_MCI_CONTROL_RESET:
+        break;
+
+    case ARM_MCI_CONTROL_CLOCK_IDLE:
+        break;
+
+    case ARM_MCI_DATA_TIMEOUT:
+        break;
+
+    case ARM_MCI_MONITOR_SDIO_INTERRUPT:
+        break;
+
+    case ARM_MCI_CONTROL_READ_WAIT:
+        break;
+
+    case ARM_MCI_DRIVER_STRENGTH:
+    default: return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+ARM_MCI_STATUS ARM_MCI_GetStatus(void)
+{
+}
+
+void ARM_MCI_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End MCI Interface
+
+ARM_DRIVER_MCI Driver_MCI = {
+    ARM_MCI_GetVersion,
+    ARM_MCI_GetCapabilities,
+    ARM_MCI_Initialize,
+    ARM_MCI_Uninitialize,
+    ARM_MCI_PowerControl,
+    ARM_MCI_CardPower,
+    ARM_MCI_ReadCD,
+    ARM_MCI_ReadWP,
+    ARM_MCI_SendCommand,
+    ARM_MCI_SetupTransfer,
+    ARM_MCI_AbortTransfer,
+    ARM_MCI_Control,
+    ARM_MCI_GetStatus
+};

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/DriverTemplates/Driver_SAI.c

@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_SAI.h"
+
+#define ARM_SAI_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_SAI_API_VERSION,
+    ARM_SAI_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_SAI_CAPABILITIES DriverCapabilities = {
+    1, /* supports asynchronous Transmit/Receive */
+    0, /* supports synchronous Transmit/Receive */
+    0, /* supports user defined Protocol */
+    1, /* supports I2S Protocol */
+    0, /* supports MSB/LSB justified Protocol */
+    0, /* supports PCM short/long frame Protocol */
+    0, /* supports AC'97 Protocol */
+    0, /* supports Mono mode */
+    0, /* supports Companding */
+    0, /* supports MCLK (Master Clock) pin */
+    0  /* supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR */
+};
+
+//
+//  Functions
+//
+
+ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)
+{
+}
+
+ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)
+{
+}
+
+int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_SAI_Uninitialize (void)
+{
+}
+
+int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_SAI_Send (const void *data, uint32_t num)
+{
+}
+
+int32_t ARM_SAI_Receive (void *data, uint32_t num)
+{
+}
+
+uint32_t ARM_SAI_GetTxCount (void)
+{
+}
+
+uint32_t ARM_SAI_GetRxCount (void)
+{
+}
+
+int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)
+{
+}
+
+ARM_SAI_STATUS ARM_SAI_GetStatus (void)
+{
+}
+
+void ARM_SAI_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End SAI Interface
+
+ARM_DRIVER_SAI Driver_SAI = {
+    ARM_SAI_GetVersion,
+    ARM_SAI_GetCapabilities,
+    ARM_SAI_Initialize,
+    ARM_SAI_Uninitialize,
+    ARM_SAI_PowerControl,
+    ARM_SAI_Send,
+    ARM_SAI_Receive,
+    ARM_SAI_GetTxCount,
+    ARM_SAI_GetRxCount,
+    ARM_SAI_Control,
+    ARM_SAI_GetStatus
+};

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/DriverTemplates/Driver_SPI.c

@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_SPI.h"
+
+#define ARM_SPI_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_SPI_API_VERSION,
+    ARM_SPI_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_SPI_CAPABILITIES DriverCapabilities = {
+    1, /* Simplex Mode (Master and Slave) */
+    1, /* TI Synchronous Serial Interface */
+    1, /* Microwire Interface */
+    0  /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */
+};
+
+//
+//  Functions
+//
+
+ARM_DRIVER_VERSION ARM_SPI_GetVersion(void)
+{
+}
+
+ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities(void)
+{
+}
+
+int32_t ARM_SPI_Initialize(ARM_SPI_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_SPI_Uninitialize(void)
+{
+}
+
+int32_t ARM_SPI_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_SPI_Send(const void *data, uint32_t num)
+{
+}
+
+int32_t ARM_SPI_Receive(void *data, uint32_t num)
+{
+}
+
+int32_t ARM_SPI_Transfer(const void *data_out, void *data_in, uint32_t num)
+{
+}
+
+uint32_t ARM_SPI_GetDataCount(void)
+{
+}
+
+int32_t ARM_SPI_Control(uint32_t control, uint32_t arg)
+{
+    switch (control & ARM_SPI_CONTROL_Msk)
+    {
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    case ARM_SPI_MODE_INACTIVE:             // SPI Inactive
+        return ARM_DRIVER_OK;
+
+    case ARM_SPI_MODE_MASTER:               // SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
+        break;
+
+    case ARM_SPI_MODE_SLAVE:                // SPI Slave  (Output on MISO, Input on MOSI)
+        break;
+
+    case ARM_SPI_MODE_MASTER_SIMPLEX:       // SPI Master (Output/Input on MOSI); arg = Bus Speed in bps
+    case ARM_SPI_MODE_SLAVE_SIMPLEX:        // SPI Slave  (Output/Input on MISO)
+        return ARM_SPI_ERROR_MODE;
+
+    case ARM_SPI_SET_BUS_SPEED:             // Set Bus Speed in bps; arg = value
+        break;
+
+    case ARM_SPI_GET_BUS_SPEED:             // Get Bus Speed in bps
+        break;
+
+    case ARM_SPI_SET_DEFAULT_TX_VALUE:      // Set default Transmit value; arg = value
+        break;
+
+    case ARM_SPI_CONTROL_SS:                // Control Slave Select; arg = 0:inactive, 1:active
+        break;
+
+    case ARM_SPI_ABORT_TRANSFER:            // Abort current data transfer
+        break;
+    }
+}
+
+ARM_SPI_STATUS ARM_SPI_GetStatus(void)
+{
+}
+
+void ARM_SPI_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End SPI Interface
+
+ARM_DRIVER_SPI Driver_SPI = {
+    ARM_SPI_GetVersion,
+    ARM_SPI_GetCapabilities,
+    ARM_SPI_Initialize,
+    ARM_SPI_Uninitialize,
+    ARM_SPI_PowerControl,
+    ARM_SPI_Send,
+    ARM_SPI_Receive,
+    ARM_SPI_Transfer,
+    ARM_SPI_GetDataCount,
+    ARM_SPI_Control,
+    ARM_SPI_GetStatus
+};

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/DriverTemplates/Driver_Storage.c

@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "Driver_Storage.h"
+
+#define ARM_STORAGE_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+    ARM_STORAGE_API_VERSION,
+    ARM_STORAGE_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_STORAGE_CAPABILITIES DriverCapabilities = {
+    1,  /* Asynchronous Mode */
+    1,  /* Supports EraseAll operation */
+    0   /* Reserved */
+};
+
+
+//
+// Functions
+//
+
+ARM_DRIVER_VERSION ARM_Storage_GetVersion (void)  {
+}
+
+ARM_STORAGE_CAPABILITIES ARM_Storage_GetCapabilities (void)  {
+}
+
+int32_t ARM_Storage_Initialize (ARM_Storage_Callback_t callback)  {
+}
+
+int32_t ARM_Storage_Uninitialize (void)  {
+}
+
+int32_t ARM_Storage_PowerControl (ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_Storage_ReadData (uint64_t addr, void *data, uint32_t size)  {
+}
+
+int32_t ARM_Storage_ProgramData (uint64_t addr, const void *data, uint32_t size)  {
+}
+
+int32_t ARM_Storage_Erase (uint64_t addr, uint32_t size)  {
+}
+
+int32_t ARM_Storage_EraseAll (void)  {
+}
+
+ARM_STORAGE_STATUS ARM_Storage_GetStatus (void)  {
+}
+
+int32_t ARM_Storage_GetInfo (ARM_STORAGE_INFO *info)  {
+}
+
+uint32_t ARM_Storage_ResolveAddress(uint64_t addr) {
+}
+
+int32_t ARM_Storage_GetNextBlock(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block) {
+}
+
+int32_t ARM_Storage_GetBlock(uint64_t addr, ARM_STORAGE_BLOCK *block) {
+}
+// End Storage Interface
+
+ARM_DRIVER_STORAGE Driver_STORAGE = {
+    ARM_Storage_GetVersion,
+    ARM_Storage_GetCapabilities,
+    ARM_Storage_Initialize,
+    ARM_Storage_Uninitialize,
+    ARM_Storage_PowerControl,
+    ARM_Storage_ReadData,
+    ARM_Storage_ProgramData,
+    ARM_Storage_Erase,
+    ARM_Storage_EraseAll,
+    ARM_Storage_GetStatus,
+    ARM_Storage_GetInfo,
+    ARM_Storage_ResolveAddress,
+    ARM_Storage_GetNextBlock,
+    ARM_Storage_GetBlock
+};

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/DriverTemplates/Driver_USART.c

@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_USART.h"
+
+#define ARM_USART_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0)  /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = { 
+    ARM_USART_API_VERSION,
+    ARM_USART_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USART_CAPABILITIES DriverCapabilities = {
+    1, /* supports UART (Asynchronous) mode */
+    0, /* supports Synchronous Master mode */
+    0, /* supports Synchronous Slave mode */
+    0, /* supports UART Single-wire mode */
+    0, /* supports UART IrDA mode */
+    0, /* supports UART Smart Card mode */
+    0, /* Smart Card Clock generator available */
+    0, /* RTS Flow Control available */
+    0, /* CTS Flow Control available */
+    0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */
+    0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */
+    0, /* RTS Line: 0=not available, 1=available */
+    0, /* CTS Line: 0=not available, 1=available */
+    0, /* DTR Line: 0=not available, 1=available */
+    0, /* DSR Line: 0=not available, 1=available */
+    0, /* DCD Line: 0=not available, 1=available */
+    0, /* RI Line: 0=not available, 1=available */
+    0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */
+    0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */
+    0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */
+    0  /* Signal RI change event: \ref ARM_USART_EVENT_RI */
+};
+
+//
+//   Functions
+//
+
+ARM_DRIVER_VERSION ARM_USART_GetVersion(void)
+{
+}
+
+ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void)
+{
+}
+
+int32_t ARM_USART_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+}
+
+int32_t ARM_USART_Uninitialize(void)
+{
+}
+
+int32_t ARM_USART_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_USART_Send(const void *data, uint32_t num)
+{
+}
+
+int32_t ARM_USART_Receive(void *data, uint32_t num)
+{
+}
+
+int32_t ARM_USART_Transfer(const void *data_out, void *data_in, uint32_t num)
+{
+}
+
+uint32_t ARM_USART_GetTxCount(void)
+{
+}
+
+uint32_t ARM_USART_GetRxCount(void)
+{
+}
+
+int32_t ARM_USART_Control(uint32_t control, uint32_t arg)
+{
+}
+
+ARM_USART_STATUS ARM_USART_GetStatus(void)
+{
+}
+
+int32_t ARM_USART_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+}
+
+ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus(void)
+{
+}
+
+void ARM_USART_SignalEvent(uint32_t event)
+{
+    // function body
+}
+
+// End USART Interface
+
+ARM_DRIVER_USART Driver_USART = {
+    ARM_USART_GetVersion,
+    ARM_USART_GetCapabilities,
+    ARM_USART_Initialize,
+    ARM_USART_Uninitialize,
+    ARM_USART_PowerControl,
+    ARM_USART_Send,
+    ARM_USART_Receive,
+    ARM_USART_Transfer,
+    ARM_USART_GetTxCount,
+    ARM_USART_GetRxCount,
+    ARM_USART_Control,
+    ARM_USART_GetStatus,
+    ARM_USART_SetModemControl,
+    ARM_USART_GetModemStatus
+};

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/DriverTemplates/Driver_USBD.c

@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_USBD.h"
+
+#define ARM_USBD_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION usbd_driver_version = { 
+    ARM_USBD_API_VERSION,
+    ARM_USBD_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = {
+    0, /* vbus_detection */
+    0, /* event_vbus_on */
+    0  /* event_vbus_off */
+};
+
+//
+// Functions
+//
+
+ARM_DRIVER_VERSION ARM_USBD_GetVersion(void)
+{
+}
+
+ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities(void)
+{
+}
+
+int32_t ARM_USBD_Initialize(ARM_USBD_SignalDeviceEvent_t cb_device_event,
+                            ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
+{
+}
+
+int32_t ARM_USBD_Uninitialize(void)
+{
+}
+
+int32_t ARM_USBD_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_USBD_DeviceConnect(void)
+{
+}
+
+int32_t ARM_USBD_DeviceDisconnect(void)
+{
+}
+
+ARM_USBD_STATE ARM_USBD_DeviceGetState(void)
+{
+}
+
+int32_t ARM_USBD_DeviceRemoteWakeup(void)
+{
+}
+
+int32_t ARM_USBD_DeviceSetAddress(uint8_t dev_addr)
+{
+}
+
+int32_t ARM_USBD_ReadSetupPacket(uint8_t *setup)
+{
+}
+
+int32_t ARM_USBD_EndpointConfigure(uint8_t ep_addr,
+                                   uint8_t ep_type,
+                                   uint16_t ep_max_packet_size)
+{
+}
+
+int32_t ARM_USBD_EndpointUnconfigure(uint8_t ep_addr)
+{
+}
+
+int32_t ARM_USBD_EndpointStall(uint8_t ep_addr, bool stall)
+{
+}
+
+int32_t ARM_USBD_EndpointTransfer(uint8_t ep_addr, uint8_t *data, uint32_t num)
+{
+}
+
+uint32_t ARM_USBD_EndpointTransferGetResult(uint8_t ep_addr)
+{
+}
+
+int32_t ARM_USBD_EndpointTransferAbort(uint8_t ep_addr)
+{
+}
+
+uint16_t ARM_USBD_GetFrameNumber(void)
+{
+}
+
+void ARM_USBD_SignalDeviceEvent(uint32_t event)
+{
+    // function body
+}
+
+void ARM_USBD_SignalEndpointEvent(uint8_t ep_addr, uint32_t ep_event)
+{
+    // function body
+}
+
+// End USBD Interface
+
+ARM_DRIVER_USBD Driver_USBD =
+{
+    ARM_USBD_GetVersion,
+    ARM_USBD_GetCapabilities,
+    ARM_USBD_Initialize,
+    ARM_USBD_Uninitialize,
+    ARM_USBD_PowerControl,
+    ARM_USBD_DeviceConnect,
+    ARM_USBD_DeviceDisconnect,
+    ARM_USBD_DeviceGetState,
+    ARM_USBD_DeviceRemoteWakeup,
+    ARM_USBD_DeviceSetAddress,
+    ARM_USBD_ReadSetupPacket,
+    ARM_USBD_EndpointConfigure,
+    ARM_USBD_EndpointUnconfigure,
+    ARM_USBD_EndpointStall,
+    ARM_USBD_EndpointTransfer,
+    ARM_USBD_EndpointTransferGetResult,
+    ARM_USBD_EndpointTransferAbort,
+    ARM_USBD_GetFrameNumber
+};

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/DriverTemplates/Driver_USBH.c

@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "Driver_USBH.h"
+
+/* USB Host Driver */
+
+#define ARM_USBH_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION usbh_driver_version = { 
+    ARM_USBH_API_VERSION,
+    ARM_USBH_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USBH_CAPABILITIES usbd_driver_capabilities = {
+    0x0001, /* Root HUB available Ports Mask   */
+    0,      /* Automatic SPLIT packet handling */
+    0,      /* Signal Connect event */
+    0,      /* Signal Disconnect event */
+    0       /* Signal Overcurrent event */
+};
+
+//
+// Functions
+//
+
+ARM_DRIVER_VERSION ARM_USBH_GetVersion(void)
+{
+}
+
+ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities(void)
+{
+}
+
+int32_t ARM_USBH_Initialize(ARM_USBH_SignalPortEvent_t cb_port_event,
+                            ARM_USBH_SignalEndpointEvent_t cb_endpoint_event)
+{
+}
+
+int32_t ARM_USBH_Uninitialize(void)
+{
+}
+
+int32_t ARM_USBH_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_USBH_PortVbusOnOff(uint8_t port, bool vbus)
+{
+}
+
+int32_t ARM_USBH_PortReset(uint8_t port)
+{
+}
+
+int32_t ARM_USBH_PortSuspend(uint8_t port)
+{
+}
+
+int32_t ARM_USBH_PortResume(uint8_t port)
+{
+}
+
+ARM_USBH_PORT_STATE ARM_USBH_PortGetState(uint8_t port)
+{
+}
+
+ARM_USBH_EP_HANDLE ARM_USBH_EndpointCreate(uint8_t dev_addr,
+                                           uint8_t dev_speed,
+                                           uint8_t hub_addr,
+                                           uint8_t hub_port,
+                                           uint8_t ep_addr,
+                                           uint8_t ep_type,
+                                           uint16_t ep_max_packet_size,
+                                           uint8_t ep_interval)
+{
+}
+
+int32_t ARM_USBH_EndpointModify(ARM_USBH_EP_HANDLE ep_hndl,
+                                uint8_t dev_addr,
+                                uint8_t dev_speed,
+                                uint8_t hub_addr,
+                                uint8_t hub_port,
+                                uint16_t ep_max_packet_size)
+{
+}
+
+int32_t ARM_USBH_EndpointDelete(ARM_USBH_EP_HANDLE ep_hndl)
+{
+}
+
+int32_t ARM_USBH_EndpointReset(ARM_USBH_EP_HANDLE ep_hndl)
+{
+}
+
+int32_t ARM_USBH_EndpointTransfer(ARM_USBH_EP_HANDLE ep_hndl,
+                                  uint32_t packet,
+                                  uint8_t *data,
+                                  uint32_t num)
+{
+}
+
+uint32_t ARM_USBH_EndpointTransferGetResult(ARM_USBH_EP_HANDLE ep_hndl)
+{
+}
+
+int32_t ARM_USBH_EndpointTransferAbort(ARM_USBH_EP_HANDLE ep_hndl)
+{
+}
+
+uint16_t ARM_USBH_GetFrameNumber(void)
+{
+}
+
+void ARM_USBH_SignalPortEvent(uint8_t port, uint32_t event)
+{
+    // function body
+}
+
+void ARM_USBH_SignalEndpointEvent(ARM_USBH_EP_HANDLE ep_hndl, uint32_t event)
+{
+    // function body
+}
+
+/* USB Host HCI (OHCI/EHCI) Driver */
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION usbh_hci_driver_version = { 
+    ARM_USBH_API_VERSION,
+    ARM_USBH_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USBH_HCI_CAPABILITIES usbh_hci_driver_capabilities = {
+    0x0001  /* Root HUB available Ports Mask   */
+};
+
+//
+// Functions
+//
+
+ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion(void)
+{
+}
+
+ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities(void)
+{
+}
+
+int32_t ARM_USBH_HCI_Initialize(ARM_USBH_HCI_Interrupt_t cb_interrupt)
+{
+}
+
+int32_t ARM_USBH_HCI_Uninitialize(void)
+{
+}
+
+int32_t ARM_USBH_HCI_PowerControl(ARM_POWER_STATE state)
+{
+    switch (state)
+    {
+    case ARM_POWER_OFF:
+        break;
+
+    case ARM_POWER_LOW:
+        break;
+
+    case ARM_POWER_FULL:
+        break;
+
+    default:
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+    }
+}
+
+int32_t ARM_USBH_HCI_PortVbusOnOff(uint8_t port, bool vbus)
+{
+}
+
+void ARM_USBH_HCI_Interrupt(void)
+{
+    // function body
+}
+
+// End USBH Interface
+
+ARM_DRIVER_USBH_HCI Driver_USBH_HCI = {
+    ARM_USBH_HCI_GetVersion,
+    ARM_USBH_HCI_GetCapabilities,
+    ARM_USBH_HCI_Initialize,
+    ARM_USBH_HCI_Uninitialize,
+    ARM_USBH_HCI_PowerControl,
+    ARM_USBH_HCI_PortVbusOnOff
+};

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_CAN.h

@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2015-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        13. Sept 2017
+ * $Revision:    V1.2
+ *
+ * Project:      CAN (Controller Area Network) Driver definitions
+ */
+
+/* History:
+ *  Version 1.2
+ *    Added ARM_CAN_UNIT_STATE_BUS_OFF unit state and
+ *    ARM_CAN_EVENT_UNIT_INACTIVE unit event
+ *  Version 1.1
+ *    ARM_CAN_STATUS made volatile
+ *  Version 1.0
+ *    Initial release
+ */
+
+#ifndef DRIVER_CAN_H_
+#define DRIVER_CAN_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_CAN_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2)  /* API version */
+
+
+/****** CAN Bitrate selection codes *****/
+typedef enum _ARM_CAN_BITRATE_SELECT {
+  ARM_CAN_BITRATE_NOMINAL,              ///< Select nominal (flexible data-rate arbitration) bitrate
+  ARM_CAN_BITRATE_FD_DATA               ///< Select flexible data-rate data bitrate
+} ARM_CAN_BITRATE_SELECT;
+
+/****** CAN Bit Propagation Segment codes (PROP_SEG) *****/
+#define ARM_CAN_BIT_PROP_SEG_Pos        0UL       ///< bits 7..0
+#define ARM_CAN_BIT_PROP_SEG_Msk       (0xFFUL << ARM_CAN_BIT_PROP_SEG_Pos)
+#define ARM_CAN_BIT_PROP_SEG(x)      (((x)     << ARM_CAN_BIT_PROP_SEG_Pos) & ARM_CAN_BIT_PROP_SEG_Msk)
+
+/****** CAN Bit Phase Buffer Segment 1 (PHASE_SEG1) codes *****/
+#define ARM_CAN_BIT_PHASE_SEG1_Pos      8UL       ///< bits 15..8
+#define ARM_CAN_BIT_PHASE_SEG1_Msk     (0xFFUL << ARM_CAN_BIT_PHASE_SEG1_Pos)
+#define ARM_CAN_BIT_PHASE_SEG1(x)    (((x)     << ARM_CAN_BIT_PHASE_SEG1_Pos) & ARM_CAN_BIT_PHASE_SEG1_Msk)
+
+/****** CAN Bit Phase Buffer Segment 2 (PHASE_SEG2) codes *****/
+#define ARM_CAN_BIT_PHASE_SEG2_Pos      16UL      ///< bits 23..16
+#define ARM_CAN_BIT_PHASE_SEG2_Msk     (0xFFUL << ARM_CAN_BIT_PHASE_SEG2_Pos)
+#define ARM_CAN_BIT_PHASE_SEG2(x)    (((x)     << ARM_CAN_BIT_PHASE_SEG2_Pos) & ARM_CAN_BIT_PHASE_SEG2_Msk)
+
+/****** CAN Bit (Re)Synchronization Jump Width Segment (SJW) *****/
+#define ARM_CAN_BIT_SJW_Pos             24UL      ///< bits 28..24
+#define ARM_CAN_BIT_SJW_Msk            (0x1FUL << ARM_CAN_BIT_SJW_Pos)
+#define ARM_CAN_BIT_SJW(x)           (((x)     << ARM_CAN_BIT_SJW_Pos) & ARM_CAN_BIT_SJW_Msk)
+
+/****** CAN Mode codes *****/
+typedef enum _ARM_CAN_MODE {
+  ARM_CAN_MODE_INITIALIZATION,          ///< Initialization mode
+  ARM_CAN_MODE_NORMAL,                  ///< Normal operation mode
+  ARM_CAN_MODE_RESTRICTED,              ///< Restricted operation mode
+  ARM_CAN_MODE_MONITOR,                 ///< Bus monitoring mode
+  ARM_CAN_MODE_LOOPBACK_INTERNAL,       ///< Loopback internal mode
+  ARM_CAN_MODE_LOOPBACK_EXTERNAL        ///< Loopback external mode
+} ARM_CAN_MODE;
+
+/****** CAN Filter Operation codes *****/
+typedef enum _ARM_CAN_FILTER_OPERATION {
+  ARM_CAN_FILTER_ID_EXACT_ADD,          ///< Add    exact id filter
+  ARM_CAN_FILTER_ID_EXACT_REMOVE,       ///< Remove exact id filter
+  ARM_CAN_FILTER_ID_RANGE_ADD,          ///< Add    range id filter
+  ARM_CAN_FILTER_ID_RANGE_REMOVE,       ///< Remove range id filter
+  ARM_CAN_FILTER_ID_MASKABLE_ADD,       ///< Add    maskable id filter
+  ARM_CAN_FILTER_ID_MASKABLE_REMOVE     ///< Remove maskable id filter
+} ARM_CAN_FILTER_OPERATION;
+
+/****** CAN Object Configuration codes *****/
+typedef enum _ARM_CAN_OBJ_CONFIG {
+  ARM_CAN_OBJ_INACTIVE,                 ///< CAN object inactive
+  ARM_CAN_OBJ_TX,                       ///< CAN transmit object
+  ARM_CAN_OBJ_RX,                       ///< CAN receive object
+  ARM_CAN_OBJ_RX_RTR_TX_DATA,           ///< CAN object that on RTR reception automatically transmits Data Frame
+  ARM_CAN_OBJ_TX_RTR_RX_DATA            ///< CAN object that transmits RTR and automatically receives Data Frame
+} ARM_CAN_OBJ_CONFIG;
+
+/**
+\brief CAN Object Capabilities
+*/
+typedef struct _ARM_CAN_OBJ_CAPABILITIES {
+  uint32_t tx               : 1;        ///< Object supports transmission
+  uint32_t rx               : 1;        ///< Object supports reception
+  uint32_t rx_rtr_tx_data   : 1;        ///< Object supports RTR reception and automatic Data Frame transmission
+  uint32_t tx_rtr_rx_data   : 1;        ///< Object supports RTR transmission and automatic Data Frame reception
+  uint32_t multiple_filters : 1;        ///< Object allows assignment of multiple filters to it
+  uint32_t exact_filtering  : 1;        ///< Object supports exact identifier filtering
+  uint32_t range_filtering  : 1;        ///< Object supports range identifier filtering
+  uint32_t mask_filtering   : 1;        ///< Object supports mask identifier filtering
+  uint32_t message_depth    : 8;        ///< Number of messages buffers (FIFO) for that object
+  uint32_t reserved         : 16;       ///< Reserved (must be zero)
+} ARM_CAN_OBJ_CAPABILITIES;
+
+/****** CAN Control Function Operation codes *****/
+#define ARM_CAN_CONTROL_Pos             0UL
+#define ARM_CAN_CONTROL_Msk            (0xFFUL << ARM_CAN_CONTROL_Pos)
+#define ARM_CAN_SET_FD_MODE            (1UL    << ARM_CAN_CONTROL_Pos)          ///< Set FD operation mode;                   arg: 0 = disable, 1 = enable
+#define ARM_CAN_ABORT_MESSAGE_SEND     (2UL    << ARM_CAN_CONTROL_Pos)          ///< Abort sending of CAN message;            arg = object
+#define ARM_CAN_CONTROL_RETRANSMISSION (3UL    << ARM_CAN_CONTROL_Pos)          ///< Enable/disable automatic retransmission; arg: 0 = disable, 1 = enable (default state)
+#define ARM_CAN_SET_TRANSCEIVER_DELAY  (4UL    << ARM_CAN_CONTROL_Pos)          ///< Set transceiver delay;                   arg = delay in time quanta
+
+/****** CAN ID Frame Format codes *****/
+#define ARM_CAN_ID_IDE_Pos              31UL
+#define ARM_CAN_ID_IDE_Msk             (1UL    << ARM_CAN_ID_IDE_Pos)
+
+/****** CAN Identifier encoding *****/
+#define ARM_CAN_STANDARD_ID(id)        (id & 0x000007FFUL)                      ///< CAN identifier in standard format (11-bits)
+#define ARM_CAN_EXTENDED_ID(id)       ((id & 0x1FFFFFFFUL) | ARM_CAN_ID_IDE_Msk)///< CAN identifier in extended format (29-bits)
+
+/**
+\brief CAN Message Information
+*/
+typedef struct _ARM_CAN_MSG_INFO {
+  uint32_t id;                          ///< CAN identifier with frame format specifier (bit 31)
+  uint32_t rtr              : 1;        ///< Remote transmission request frame
+  uint32_t edl              : 1;        ///< Flexible data-rate format extended data length
+  uint32_t brs              : 1;        ///< Flexible data-rate format with bitrate switch 
+  uint32_t esi              : 1;        ///< Flexible data-rate format error state indicator
+  uint32_t dlc              : 4;        ///< Data length code
+  uint32_t reserved         : 24;
+} ARM_CAN_MSG_INFO;
+
+/****** CAN specific error code *****/
+#define ARM_CAN_INVALID_BITRATE_SELECT (ARM_DRIVER_ERROR_SPECIFIC - 1)          ///< Bitrate selection not supported
+#define ARM_CAN_INVALID_BITRATE        (ARM_DRIVER_ERROR_SPECIFIC - 2)          ///< Requested bitrate not supported
+#define ARM_CAN_INVALID_BIT_PROP_SEG   (ARM_DRIVER_ERROR_SPECIFIC - 3)          ///< Propagation segment value not supported
+#define ARM_CAN_INVALID_BIT_PHASE_SEG1 (ARM_DRIVER_ERROR_SPECIFIC - 4)          ///< Phase segment 1 value not supported
+#define ARM_CAN_INVALID_BIT_PHASE_SEG2 (ARM_DRIVER_ERROR_SPECIFIC - 5)          ///< Phase segment 2 value not supported
+#define ARM_CAN_INVALID_BIT_SJW        (ARM_DRIVER_ERROR_SPECIFIC - 6)          ///< SJW value not supported
+#define ARM_CAN_NO_MESSAGE_AVAILABLE   (ARM_DRIVER_ERROR_SPECIFIC - 7)          ///< Message is not available
+
+/****** CAN Status codes *****/
+#define ARM_CAN_UNIT_STATE_INACTIVE    (0U)             ///< Unit state: Not active on bus (initialization)
+#define ARM_CAN_UNIT_STATE_ACTIVE      (1U)             ///< Unit state: Active on bus (can generate active error frame)
+#define ARM_CAN_UNIT_STATE_PASSIVE     (2U)             ///< Unit state: Error passive (can not generate active error frame)
+#define ARM_CAN_UNIT_STATE_BUS_OFF     (3U)             ///< Unit state: Bus-off (can recover to active state)
+#define ARM_CAN_LEC_NO_ERROR           (0U)             ///< Last error code: No error
+#define ARM_CAN_LEC_BIT_ERROR          (1U)             ///< Last error code: Bit error
+#define ARM_CAN_LEC_STUFF_ERROR        (2U)             ///< Last error code: Bit stuffing error
+#define ARM_CAN_LEC_CRC_ERROR          (3U)             ///< Last error code: CRC error
+#define ARM_CAN_LEC_FORM_ERROR         (4U)             ///< Last error code: Illegal fixed-form bit
+#define ARM_CAN_LEC_ACK_ERROR          (5U)             ///< Last error code: Acknowledgment error
+
+/**
+\brief CAN Status
+*/
+typedef volatile struct _ARM_CAN_STATUS {
+  uint32_t unit_state       : 4;        ///< Unit bus state
+  uint32_t last_error_code  : 4;        ///< Last error code
+  uint32_t tx_error_count   : 8;        ///< Transmitter error count
+  uint32_t rx_error_count   : 8;        ///< Receiver error count
+  uint32_t reserved         : 8;
+} ARM_CAN_STATUS;
+
+
+/****** CAN Unit Event *****/
+#define ARM_CAN_EVENT_UNIT_INACTIVE    (0U)             ///< Unit entered Inactive state
+#define ARM_CAN_EVENT_UNIT_ACTIVE      (1U)             ///< Unit entered Error Active state
+#define ARM_CAN_EVENT_UNIT_WARNING     (2U)             ///< Unit entered Error Warning state (one or both error counters >= 96)
+#define ARM_CAN_EVENT_UNIT_PASSIVE     (3U)             ///< Unit entered Error Passive state
+#define ARM_CAN_EVENT_UNIT_BUS_OFF     (4U)             ///< Unit entered Bus-off state
+
+/****** CAN Send/Receive Event *****/
+#define ARM_CAN_EVENT_SEND_COMPLETE    (1UL << 0)       ///< Send complete
+#define ARM_CAN_EVENT_RECEIVE          (1UL << 1)       ///< Message received
+#define ARM_CAN_EVENT_RECEIVE_OVERRUN  (1UL << 2)       ///< Received message overrun
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_CAN_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_CAN_CAPABILITIES
+
+  \fn          int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t   cb_unit_event,
+                                           ARM_CAN_SignalObjectEvent_t cb_object_event)
+  \brief       Initialize CAN interface and register signal (callback) functions.
+  \param[in]   cb_unit_event   Pointer to \ref ARM_CAN_SignalUnitEvent callback function
+  \param[in]   cb_object_event Pointer to \ref ARM_CAN_SignalObjectEvent callback function
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_Uninitialize (void)
+  \brief       De-initialize CAN interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state)
+  \brief       Control CAN interface power.
+  \param[in]   state  Power state
+                 - \ref ARM_POWER_OFF :  power off: no operation possible
+                 - \ref ARM_POWER_LOW :  low power mode: retain state, detect and signal wake-up events
+                 - \ref ARM_POWER_FULL : power on: full operation at maximum performance
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_CAN_GetClock (void)
+  \brief       Retrieve CAN base clock frequency.
+  \return      base clock frequency
+
+  \fn          int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments)
+  \brief       Set bitrate for CAN interface.
+  \param[in]   select       Bitrate selection
+                 - \ref ARM_CAN_BITRATE_NOMINAL : nominal (flexible data-rate arbitration) bitrate
+                 - \ref ARM_CAN_BITRATE_FD_DATA : flexible data-rate data bitrate
+  \param[in]   bitrate      Bitrate
+  \param[in]   bit_segments Bit segments settings
+                 - \ref ARM_CAN_BIT_PROP_SEG(x) :   number of time quanta for propagation time segment
+                 - \ref ARM_CAN_BIT_PHASE_SEG1(x) : number of time quanta for phase buffer segment 1
+                 - \ref ARM_CAN_BIT_PHASE_SEG2(x) : number of time quanta for phase buffer Segment 2
+                 - \ref ARM_CAN_BIT_SJW(x) :        number of time quanta for (re-)synchronization jump width
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode)
+  \brief       Set operating mode for CAN interface.
+  \param[in]   mode   Operating mode
+                 - \ref ARM_CAN_MODE_INITIALIZATION :    initialization mode
+                 - \ref ARM_CAN_MODE_NORMAL :            normal operation mode
+                 - \ref ARM_CAN_MODE_RESTRICTED :        restricted operation mode
+                 - \ref ARM_CAN_MODE_MONITOR :           bus monitoring mode
+                 - \ref ARM_CAN_MODE_LOOPBACK_INTERNAL : loopback internal mode
+                 - \ref ARM_CAN_MODE_LOOPBACK_EXTERNAL : loopback external mode
+  \return      \ref execution_status
+
+  \fn          ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx)
+  \brief       Retrieve capabilities of an object.
+  \param[in]   obj_idx  Object index
+  \return      \ref ARM_CAN_OBJ_CAPABILITIES
+
+  \fn          int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg)
+  \brief       Add or remove filter for message reception.
+  \param[in]   obj_idx      Object index of object that filter should be or is assigned to
+  \param[in]   operation    Operation on filter
+                 - \ref ARM_CAN_FILTER_ID_EXACT_ADD :       add    exact id filter
+                 - \ref ARM_CAN_FILTER_ID_EXACT_REMOVE :    remove exact id filter
+                 - \ref ARM_CAN_FILTER_ID_RANGE_ADD :       add    range id filter
+                 - \ref ARM_CAN_FILTER_ID_RANGE_REMOVE :    remove range id filter
+                 - \ref ARM_CAN_FILTER_ID_MASKABLE_ADD :    add    maskable id filter
+                 - \ref ARM_CAN_FILTER_ID_MASKABLE_REMOVE : remove maskable id filter
+  \param[in]   id           ID or start of ID range (depending on filter type)
+  \param[in]   arg          Mask or end of ID range (depending on filter type)
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg)
+  \brief       Configure object.
+  \param[in]   obj_idx  Object index
+  \param[in]   obj_cfg  Object configuration state
+                 - \ref ARM_CAN_OBJ_INACTIVE :       deactivate object
+                 - \ref ARM_CAN_OBJ_RX :             configure object for reception
+                 - \ref ARM_CAN_OBJ_TX :             configure object for transmission
+                 - \ref ARM_CAN_OBJ_RX_RTR_TX_DATA : configure object that on RTR reception automatically transmits Data Frame
+                 - \ref ARM_CAN_OBJ_TX_RTR_RX_DATA : configure object that transmits RTR and automatically receives Data Frame
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size)
+  \brief       Send message on CAN bus.
+  \param[in]   obj_idx  Object index
+  \param[in]   msg_info Pointer to CAN message information
+  \param[in]   data     Pointer to data buffer
+  \param[in]   size     Number of data bytes to send
+  \return      value >= 0  number of data bytes accepted to send
+  \return      value < 0   \ref execution_status
+
+  \fn          int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size)
+  \brief       Read message received on CAN bus.
+  \param[in]   obj_idx  Object index
+  \param[out]  msg_info Pointer to read CAN message information
+  \param[out]  data     Pointer to data buffer for read data
+  \param[in]   size     Maximum number of data bytes to read
+  \return      value >= 0  number of data bytes read
+  \return      value < 0   \ref execution_status
+
+  \fn          int32_t ARM_CAN_Control (uint32_t control, uint32_t arg)
+  \brief       Control CAN interface.
+  \param[in]   control  Operation
+                 - \ref ARM_CAN_SET_FD_MODE :            set FD operation mode
+                 - \ref ARM_CAN_ABORT_MESSAGE_SEND :     abort sending of CAN message
+                 - \ref ARM_CAN_CONTROL_RETRANSMISSION : enable/disable automatic retransmission
+                 - \ref ARM_CAN_SET_TRANSCEIVER_DELAY :  set transceiver delay
+  \param[in]   arg      Argument of operation
+  \return      \ref execution_status
+
+  \fn          ARM_CAN_STATUS ARM_CAN_GetStatus (void)
+  \brief       Get CAN status.
+  \return      CAN status \ref ARM_CAN_STATUS
+
+  \fn          void ARM_CAN_SignalUnitEvent (uint32_t event)
+  \brief       Signal CAN unit event.
+  \param[in]   event \ref CAN_unit_events
+  \return      none
+
+  \fn          void ARM_CAN_SignalObjectEvent (uint32_t obj_idx, uint32_t event)
+  \brief       Signal CAN object event.
+  \param[in]   obj_idx  Object index
+  \param[in]   event \ref CAN_events
+  \return      none
+*/
+
+typedef void (*ARM_CAN_SignalUnitEvent_t)   (uint32_t event);                   ///< Pointer to \ref ARM_CAN_SignalUnitEvent   : Signal CAN Unit Event.
+typedef void (*ARM_CAN_SignalObjectEvent_t) (uint32_t obj_idx, uint32_t event); ///< Pointer to \ref ARM_CAN_SignalObjectEvent : Signal CAN Object Event.
+
+
+/**
+\brief CAN Device Driver Capabilities.
+*/
+typedef struct _ARM_CAN_CAPABILITIES {
+  uint32_t num_objects            : 8;  ///< Number of \ref can_objects available
+  uint32_t reentrant_operation    : 1;  ///< Support for reentrant calls to \ref ARM_CAN_MessageSend, \ref ARM_CAN_MessageRead, \ref ARM_CAN_ObjectConfigure and abort message sending used by \ref ARM_CAN_Control
+  uint32_t fd_mode                : 1;  ///< Support for CAN with flexible data-rate mode (CAN_FD) (set by \ref ARM_CAN_Control)
+  uint32_t restricted_mode        : 1;  ///< Support for restricted operation mode (set by \ref ARM_CAN_SetMode)
+  uint32_t monitor_mode           : 1;  ///< Support for bus monitoring mode (set by \ref ARM_CAN_SetMode)
+  uint32_t internal_loopback      : 1;  ///< Support for internal loopback mode (set by \ref ARM_CAN_SetMode)
+  uint32_t external_loopback      : 1;  ///< Support for external loopback mode (set by \ref ARM_CAN_SetMode)
+  uint32_t reserved               : 18; ///< Reserved (must be zero)
+} ARM_CAN_CAPABILITIES;
+
+
+/**
+\brief Access structure of the CAN Driver.
+*/
+typedef struct _ARM_DRIVER_CAN {
+  ARM_DRIVER_VERSION       (*GetVersion)            (void);                             ///< Pointer to \ref ARM_CAN_GetVersion            : Get driver version.
+  ARM_CAN_CAPABILITIES     (*GetCapabilities)       (void);                             ///< Pointer to \ref ARM_CAN_GetCapabilities       : Get driver capabilities.
+  int32_t                  (*Initialize)            (ARM_CAN_SignalUnitEvent_t   cb_unit_event,                     
+                                                     ARM_CAN_SignalObjectEvent_t cb_object_event); ///< Pointer to \ref ARM_CAN_Initialize : Initialize CAN interface.
+  int32_t                  (*Uninitialize)          (void);                             ///< Pointer to \ref ARM_CAN_Uninitialize          : De-initialize CAN interface.
+  int32_t                  (*PowerControl)          (ARM_POWER_STATE          state);   ///< Pointer to \ref ARM_CAN_PowerControl          : Control CAN interface power.
+  uint32_t                 (*GetClock)              (void);                             ///< Pointer to \ref ARM_CAN_GetClock              : Retrieve CAN base clock frequency.
+  int32_t                  (*SetBitrate)            (ARM_CAN_BITRATE_SELECT   select,
+                                                     uint32_t                 bitrate,
+                                                     uint32_t                 bit_segments);       ///< Pointer to \ref ARM_CAN_SetBitrate : Set bitrate for CAN interface.
+  int32_t                  (*SetMode)               (ARM_CAN_MODE             mode);    ///< Pointer to \ref ARM_CAN_SetMode               : Set operating mode for CAN interface.
+  ARM_CAN_OBJ_CAPABILITIES (*ObjectGetCapabilities) (uint32_t                 obj_idx); ///< Pointer to \ref ARM_CAN_ObjectGetCapabilities : Retrieve capabilities of an object.
+  int32_t                  (*ObjectSetFilter)       (uint32_t                 obj_idx,
+                                                     ARM_CAN_FILTER_OPERATION operation,
+                                                     uint32_t                 id,
+                                                     uint32_t                 arg);     ///< Pointer to \ref ARM_CAN_ObjectSetFilter       : Add or remove filter for message reception.
+  int32_t                  (*ObjectConfigure)       (uint32_t                 obj_idx,
+                                                     ARM_CAN_OBJ_CONFIG       obj_cfg); ///< Pointer to \ref ARM_CAN_ObjectConfigure       : Configure object.
+  int32_t                  (*MessageSend)           (uint32_t                 obj_idx,
+                                                     ARM_CAN_MSG_INFO        *msg_info,
+                                                     const uint8_t           *data,
+                                                     uint8_t                  size);    ///< Pointer to \ref ARM_CAN_MessageSend           : Send message on CAN bus.
+  int32_t                  (*MessageRead)           (uint32_t                 obj_idx,
+                                                     ARM_CAN_MSG_INFO        *msg_info,
+                                                     uint8_t                 *data,
+                                                     uint8_t                  size);    ///< Pointer to \ref ARM_CAN_MessageRead           : Read message received on CAN bus.
+  int32_t                  (*Control)               (uint32_t                 control,
+                                                     uint32_t                 arg);     ///< Pointer to \ref ARM_CAN_Control               : Control CAN interface.
+  ARM_CAN_STATUS           (*GetStatus)             (void);                             ///< Pointer to \ref ARM_CAN_GetStatus             : Get CAN status.
+} const ARM_DRIVER_CAN;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_CAN_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_Common.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.0
+ *
+ * Project:      Common Driver definitions
+ */
+
+/* History:
+ *  Version 2.0
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Added General return codes definitions
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_COMMON_H_
+#define DRIVER_COMMON_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct _ARM_DRIVER_VERSION {
+  uint16_t api;                         ///< API version
+  uint16_t drv;                         ///< Driver version
+} ARM_DRIVER_VERSION;
+
+/* General return codes */
+#define ARM_DRIVER_OK                 0 ///< Operation succeeded 
+#define ARM_DRIVER_ERROR             -1 ///< Unspecified error
+#define ARM_DRIVER_ERROR_BUSY        -2 ///< Driver is busy
+#define ARM_DRIVER_ERROR_TIMEOUT     -3 ///< Timeout occurred
+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
+#define ARM_DRIVER_ERROR_PARAMETER   -5 ///< Parameter error
+#define ARM_DRIVER_ERROR_SPECIFIC    -6 ///< Start of driver specific errors 
+
+/**
+\brief General power states
+*/ 
+typedef enum _ARM_POWER_STATE {
+  ARM_POWER_OFF,                        ///< Power off: no operation possible
+  ARM_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
+  ARM_POWER_FULL                        ///< Power on: full operation at maximum performance
+} ARM_POWER_STATE;
+
+#endif /* DRIVER_COMMON_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_ETH.h

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.1
+ *
+ * Project:      Ethernet PHY and MAC Driver common definitions
+ */
+
+/* History:
+ *  Version 2.1
+ *    ARM_ETH_LINK_INFO made volatile
+ *  Version 2.0
+ *    Removed ARM_ETH_STATUS enumerator
+ *    Removed ARM_ETH_MODE enumerator
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_ETH_H_
+#define DRIVER_ETH_H_
+
+#include "Driver_Common.h"
+
+/**
+\brief Ethernet Media Interface type
+*/
+#define ARM_ETH_INTERFACE_MII           (0)     ///< Media Independent Interface (MII)
+#define ARM_ETH_INTERFACE_RMII          (1)     ///< Reduced Media Independent Interface (RMII)
+#define ARM_ETH_INTERFACE_SMII          (2)     ///< Serial Media Independent Interface (SMII)
+
+/**
+\brief Ethernet link speed
+*/
+#define ARM_ETH_SPEED_10M               (0)     ///< 10 Mbps link speed
+#define ARM_ETH_SPEED_100M              (1)     ///< 100 Mbps link speed
+#define ARM_ETH_SPEED_1G                (2)     ///< 1 Gpbs link speed
+
+/**
+\brief Ethernet duplex mode
+*/
+#define ARM_ETH_DUPLEX_HALF             (0)     ///< Half duplex link
+#define ARM_ETH_DUPLEX_FULL             (1)     ///< Full duplex link
+
+/**
+\brief Ethernet link state
+*/
+typedef enum _ARM_ETH_LINK_STATE {
+  ARM_ETH_LINK_DOWN,                    ///< Link is down
+  ARM_ETH_LINK_UP                       ///< Link is up
+} ARM_ETH_LINK_STATE;
+
+/**
+\brief Ethernet link information
+*/
+typedef volatile struct _ARM_ETH_LINK_INFO {
+  uint32_t speed    : 2;                ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit
+  uint32_t duplex   : 1;                ///< Duplex mode: 0= Half, 1= Full
+  uint32_t reserved : 29;
+} ARM_ETH_LINK_INFO;
+
+/**
+\brief Ethernet MAC Address
+*/
+typedef struct _ARM_ETH_MAC_ADDR {
+  uint8_t b[6];                         ///< MAC Address (6 bytes), MSB first
+} ARM_ETH_MAC_ADDR;
+
+#endif /* DRIVER_ETH_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_ETH_MAC.h

@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.1
+ *
+ * Project:      Ethernet MAC (Media Access Control) Driver definitions
+ */
+
+/* History:
+ *  Version 2.1
+ *    Added ARM_ETH_MAC_SLEEP Control
+ *  Version 2.0
+ *    Changed MAC Address handling:
+ *      moved from ARM_ETH_MAC_Initialize
+ *      to new functions ARM_ETH_MAC_GetMacAddress and ARM_ETH_MAC_SetMacAddress
+ *    Replaced ARM_ETH_MAC_SetMulticastAddr function with ARM_ETH_MAC_SetAddressFilter
+ *    Extended ARM_ETH_MAC_SendFrame function with flags
+ *    Added ARM_ETH_MAC_Control function:
+ *      more control options (Broadcast, Multicast, Checksum offload, VLAN, ...)
+ *      replaces ARM_ETH_MAC_SetMode
+ *      replaces ARM_ETH_MAC_EnableTx, ARM_ETH_MAC_EnableRx
+ *    Added optional event on transmitted frame
+ *    Added support for PTP (Precision Time Protocol) through new functions:
+ *       ARM_ETH_MAC_ControlTimer
+ *       ARM_ETH_MAC_GetRxFrameTime
+ *       ARM_ETH_MAC_GetTxFrameTime
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Name space prefix ARM_ added
+ *  Version 1.01
+ *    Renamed capabilities items for checksum offload
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_ETH_MAC_H_
+#define DRIVER_ETH_MAC_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_ETH.h"
+
+#define ARM_ETH_MAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,1)  /* API version */
+
+
+#define _ARM_Driver_ETH_MAC_(n)      Driver_ETH_MAC##n
+#define  ARM_Driver_ETH_MAC_(n) _ARM_Driver_ETH_MAC_(n)
+
+
+/****** Ethernet MAC Control Codes *****/
+
+#define ARM_ETH_MAC_CONFIGURE           (0x01)      ///< Configure MAC; arg = configuration
+#define ARM_ETH_MAC_CONTROL_TX          (0x02)      ///< Transmitter; arg: 0=disabled (default), 1=enabled
+#define ARM_ETH_MAC_CONTROL_RX          (0x03)      ///< Receiver; arg: 0=disabled (default), 1=enabled
+#define ARM_ETH_MAC_FLUSH               (0x04)      ///< Flush buffer; arg = ARM_ETH_MAC_FLUSH_...
+#define ARM_ETH_MAC_SLEEP               (0x05)      ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit
+#define ARM_ETH_MAC_VLAN_FILTER         (0x06)      ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default)
+
+/*----- Ethernet MAC Configuration -----*/
+#define ARM_ETH_MAC_SPEED_Pos            0
+#define ARM_ETH_MAC_SPEED_Msk           (3UL                 << ARM_ETH_MAC_SPEED_Pos)
+#define ARM_ETH_MAC_SPEED_10M           (ARM_ETH_SPEED_10M   << ARM_ETH_MAC_SPEED_Pos)  ///< 10 Mbps link speed
+#define ARM_ETH_MAC_SPEED_100M          (ARM_ETH_SPEED_100M  << ARM_ETH_MAC_SPEED_Pos)  ///< 100 Mbps link speed
+#define ARM_ETH_MAC_SPEED_1G            (ARM_ETH_SPEED_1G    << ARM_ETH_MAC_SPEED_Pos)  ///< 1 Gpbs link speed
+#define ARM_ETH_MAC_DUPLEX_Pos           2
+#define ARM_ETH_MAC_DUPLEX_Msk          (1UL                 << ARM_ETH_MAC_DUPLEX_Pos)
+#define ARM_ETH_MAC_DUPLEX_HALF         (ARM_ETH_DUPLEX_HALF << ARM_ETH_MAC_DUPLEX_Pos) ///< Half duplex link
+#define ARM_ETH_MAC_DUPLEX_FULL         (ARM_ETH_DUPLEX_FULL << ARM_ETH_MAC_DUPLEX_Pos) ///< Full duplex link
+#define ARM_ETH_MAC_LOOPBACK            (1UL << 4)  ///< Loop-back test mode
+#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5)  ///< Receiver Checksum offload
+#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6)  ///< Transmitter Checksum offload
+#define ARM_ETH_MAC_ADDRESS_BROADCAST   (1UL << 7)  ///< Accept frames with Broadcast address
+#define ARM_ETH_MAC_ADDRESS_MULTICAST   (1UL << 8)  ///< Accept frames with any Multicast address
+#define ARM_ETH_MAC_ADDRESS_ALL         (1UL << 9)  ///< Accept frames with any address (Promiscuous Mode)
+
+/*----- Ethernet MAC Flush Flags -----*/
+#define ARM_ETH_MAC_FLUSH_RX            (1UL << 0)  ///< Flush Receive buffer
+#define ARM_ETH_MAC_FLUSH_TX            (1UL << 1)  ///< Flush Transmit buffer
+
+/*----- Ethernet MAC VLAN Filter Flag -----*/
+#define ARM_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit)
+
+
+/****** Ethernet MAC Frame Transmit Flags *****/
+#define ARM_ETH_MAC_TX_FRAME_FRAGMENT   (1UL << 0)  ///< Indicate frame fragment
+#define ARM_ETH_MAC_TX_FRAME_EVENT      (1UL << 1)  ///< Generate event when frame is transmitted
+#define ARM_ETH_MAC_TX_FRAME_TIMESTAMP  (1UL << 2)  ///< Capture frame time stamp
+
+
+/****** Ethernet MAC Timer Control Codes *****/
+#define ARM_ETH_MAC_TIMER_GET_TIME      (0x01)      ///< Get current time
+#define ARM_ETH_MAC_TIMER_SET_TIME      (0x02)      ///< Set new time
+#define ARM_ETH_MAC_TIMER_INC_TIME      (0x03)      ///< Increment current time
+#define ARM_ETH_MAC_TIMER_DEC_TIME      (0x04)      ///< Decrement current time
+#define ARM_ETH_MAC_TIMER_SET_ALARM     (0x05)      ///< Set alarm time
+#define ARM_ETH_MAC_TIMER_ADJUST_CLOCK  (0x06)      ///< Adjust clock frequency; time->ns: correction factor * 2^31
+
+
+/**
+\brief Ethernet MAC Time
+*/
+typedef struct _ARM_ETH_MAC_TIME {
+  uint32_t ns;                          ///< Nano seconds
+  uint32_t sec;                         ///< Seconds
+} ARM_ETH_MAC_TIME;
+
+
+/****** Ethernet MAC Event *****/
+#define ARM_ETH_MAC_EVENT_RX_FRAME      (1UL << 0)  ///< Frame Received
+#define ARM_ETH_MAC_EVENT_TX_FRAME      (1UL << 1)  ///< Frame Transmitted
+#define ARM_ETH_MAC_EVENT_WAKEUP        (1UL << 2)  ///< Wake-up (on Magic Packet)
+#define ARM_ETH_MAC_EVENT_TIMER_ALARM   (1UL << 3)  ///< Timer Alarm
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_ETH_MAC_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event)
+  \brief       Initialize Ethernet MAC Device.
+  \param[in]   cb_event  Pointer to \ref ARM_ETH_MAC_SignalEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Uninitialize (void)
+  \brief       De-initialize Ethernet MAC Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state)
+  \brief       Control Ethernet MAC Device Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr)
+  \brief       Get Ethernet MAC Address.
+  \param[in]   ptr_addr  Pointer to address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr)
+  \brief       Set Ethernet MAC Address.
+  \param[in]   ptr_addr  Pointer to address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr,
+                                                           uint32_t          num_addr)
+  \brief       Configure Address Filter.
+  \param[in]   ptr_addr  Pointer to addresses
+  \param[in]   num_addr  Number of addresses to configure
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags)
+  \brief       Send Ethernet frame.
+  \param[in]   frame  Pointer to frame buffer with data to send
+  \param[in]   len    Frame buffer length in bytes
+  \param[in]   flags  Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...)
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len)
+  \brief       Read data of received Ethernet frame.
+  \param[in]   frame  Pointer to frame buffer for data to read into
+  \param[in]   len    Frame buffer length in bytes
+  \return      number of data bytes read or execution status
+                 - value >= 0: number of data bytes read
+                 - value < 0: error occurred, value is execution status as defined with \ref execution_status 
+*/
+/**
+  \fn          uint32_t ARM_ETH_MAC_GetRxFrameSize (void)
+  \brief       Get size of received Ethernet frame.
+  \return      number of bytes in received frame
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time)
+  \brief       Get time of received Ethernet frame.
+  \param[in]   time  Pointer to time structure for data to read into
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time)
+  \brief       Get time of transmitted Ethernet frame.
+  \param[in]   time  Pointer to time structure for data to read into
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg)
+  \brief       Control Ethernet Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time)
+  \brief       Control Precision Timer.
+  \param[in]   control  Operation
+  \param[in]   time     Pointer to time structure
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
+  \brief       Read Ethernet PHY Register through Management Interface.
+  \param[in]   phy_addr  5-bit device address
+  \param[in]   reg_addr  5-bit register address
+  \param[out]  data      Pointer where the result is written to
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
+  \brief       Write Ethernet PHY Register through Management Interface.
+  \param[in]   phy_addr  5-bit device address
+  \param[in]   reg_addr  5-bit register address
+  \param[in]   data      16-bit data to write
+  \return      \ref execution_status
+*/
+
+/**
+  \fn          void ARM_ETH_MAC_SignalEvent (uint32_t event)
+  \brief       Callback function that signals a Ethernet Event.
+  \param[in]   event  event notification mask
+  \return      none
+*/
+
+typedef void (*ARM_ETH_MAC_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_ETH_MAC_SignalEvent : Signal Ethernet Event.
+
+
+/**
+\brief Ethernet MAC Capabilities
+*/
+typedef struct _ARM_ETH_MAC_CAPABILITIES {
+  uint32_t checksum_offload_rx_ip4  : 1;        ///< 1 = IPv4 header checksum verified on receive
+  uint32_t checksum_offload_rx_ip6  : 1;        ///< 1 = IPv6 checksum verification supported on receive
+  uint32_t checksum_offload_rx_udp  : 1;        ///< 1 = UDP payload checksum verified on receive
+  uint32_t checksum_offload_rx_tcp  : 1;        ///< 1 = TCP payload checksum verified on receive
+  uint32_t checksum_offload_rx_icmp : 1;        ///< 1 = ICMP payload checksum verified on receive
+  uint32_t checksum_offload_tx_ip4  : 1;        ///< 1 = IPv4 header checksum generated on transmit
+  uint32_t checksum_offload_tx_ip6  : 1;        ///< 1 = IPv6 checksum generation supported on transmit
+  uint32_t checksum_offload_tx_udp  : 1;        ///< 1 = UDP payload checksum generated on transmit
+  uint32_t checksum_offload_tx_tcp  : 1;        ///< 1 = TCP payload checksum generated on transmit
+  uint32_t checksum_offload_tx_icmp : 1;        ///< 1 = ICMP payload checksum generated on transmit
+  uint32_t media_interface          : 2;        ///< Ethernet Media Interface type
+  uint32_t mac_address              : 1;        ///< 1 = driver provides initial valid MAC address
+  uint32_t event_rx_frame           : 1;        ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated
+  uint32_t event_tx_frame           : 1;        ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated
+  uint32_t event_wakeup             : 1;        ///< 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated
+  uint32_t precision_timer          : 1;        ///< 1 = Precision Timer supported
+  uint32_t reserved                 : 15;       ///< Reserved (must be zero)
+} ARM_ETH_MAC_CAPABILITIES;
+
+
+/**
+\brief Access structure of the Ethernet MAC Driver
+*/
+typedef struct _ARM_DRIVER_ETH_MAC {
+  ARM_DRIVER_VERSION       (*GetVersion)      (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetVersion : Get driver version.
+  ARM_ETH_MAC_CAPABILITIES (*GetCapabilities) (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetCapabilities : Get driver capabilities.
+  int32_t                  (*Initialize)      (ARM_ETH_MAC_SignalEvent_t cb_event);                  ///< Pointer to \ref ARM_ETH_MAC_Initialize : Initialize Ethernet MAC Device.
+  int32_t                  (*Uninitialize)    (void);                                                ///< Pointer to \ref ARM_ETH_MAC_Uninitialize : De-initialize Ethernet MAC Device.
+  int32_t                  (*PowerControl)    (ARM_POWER_STATE state);                               ///< Pointer to \ref ARM_ETH_MAC_PowerControl : Control Ethernet MAC Device Power.
+  int32_t                  (*GetMacAddress)   (      ARM_ETH_MAC_ADDR *ptr_addr);                    ///< Pointer to \ref ARM_ETH_MAC_GetMacAddress : Get Ethernet MAC Address.
+  int32_t                  (*SetMacAddress)   (const ARM_ETH_MAC_ADDR *ptr_addr);                    ///< Pointer to \ref ARM_ETH_MAC_SetMacAddress : Set Ethernet MAC Address.
+  int32_t                  (*SetAddressFilter)(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr); ///< Pointer to \ref ARM_ETH_MAC_SetAddressFilter : Configure Address Filter.
+  int32_t                  (*SendFrame)       (const uint8_t *frame, uint32_t len, uint32_t flags);  ///< Pointer to \ref ARM_ETH_MAC_SendFrame : Send Ethernet frame.
+  int32_t                  (*ReadFrame)       (      uint8_t *frame, uint32_t len);                  ///< Pointer to \ref ARM_ETH_MAC_ReadFrame : Read data of received Ethernet frame.
+  uint32_t                 (*GetRxFrameSize)  (void);                                                ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameSize : Get size of received Ethernet frame.
+  int32_t                  (*GetRxFrameTime)  (ARM_ETH_MAC_TIME *time);                              ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameTime : Get time of received Ethernet frame.
+  int32_t                  (*GetTxFrameTime)  (ARM_ETH_MAC_TIME *time);                              ///< Pointer to \ref ARM_ETH_MAC_GetTxFrameTime : Get time of transmitted Ethernet frame.
+  int32_t                  (*ControlTimer)    (uint32_t control, ARM_ETH_MAC_TIME *time);            ///< Pointer to \ref ARM_ETH_MAC_ControlTimer : Control Precision Timer.
+  int32_t                  (*Control)         (uint32_t control, uint32_t arg);                      ///< Pointer to \ref ARM_ETH_MAC_Control : Control Ethernet Interface.
+  int32_t                  (*PHY_Read)        (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);  ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register through Management Interface.
+  int32_t                  (*PHY_Write)       (uint8_t phy_addr, uint8_t reg_addr, uint16_t  data);  ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register through Management Interface.
+} const ARM_DRIVER_ETH_MAC;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_ETH_MAC_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_ETH_PHY.h

@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.1
+ *
+ * Project:      Ethernet PHY (Physical Transceiver) Driver definitions
+ */
+
+/* History:
+ *  Version 2.1
+ *    ARM_ETH_LINK_INFO made volatile
+ *  Version 2.0
+ *    changed parameter "mode" in function ARM_ETH_PHY_SetMode
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_ETH_PHY_H_
+#define DRIVER_ETH_PHY_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_ETH.h"
+
+#define ARM_ETH_PHY_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,1)  /* API version */
+
+
+#define _ARM_Driver_ETH_PHY_(n)      Driver_ETH_PHY##n
+#define  ARM_Driver_ETH_PHY_(n) _ARM_Driver_ETH_PHY_(n)
+
+
+/****** Ethernet PHY Mode *****/
+#define ARM_ETH_PHY_SPEED_Pos            0
+#define ARM_ETH_PHY_SPEED_Msk           (3UL                 << ARM_ETH_PHY_SPEED_Pos)
+#define ARM_ETH_PHY_SPEED_10M           (ARM_ETH_SPEED_10M   << ARM_ETH_PHY_SPEED_Pos)  ///< 10 Mbps link speed
+#define ARM_ETH_PHY_SPEED_100M          (ARM_ETH_SPEED_100M  << ARM_ETH_PHY_SPEED_Pos)  ///< 100 Mbps link speed
+#define ARM_ETH_PHY_SPEED_1G            (ARM_ETH_SPEED_1G    << ARM_ETH_PHY_SPEED_Pos)  ///< 1 Gpbs link speed
+#define ARM_ETH_PHY_DUPLEX_Pos           2
+#define ARM_ETH_PHY_DUPLEX_Msk          (1UL                 << ARM_ETH_PHY_DUPLEX_Pos)
+#define ARM_ETH_PHY_DUPLEX_HALF         (ARM_ETH_DUPLEX_HALF << ARM_ETH_PHY_DUPLEX_Pos) ///< Half duplex link
+#define ARM_ETH_PHY_DUPLEX_FULL         (ARM_ETH_DUPLEX_FULL << ARM_ETH_PHY_DUPLEX_Pos) ///< Full duplex link
+#define ARM_ETH_PHY_AUTO_NEGOTIATE      (1UL << 3)                                      ///< Auto Negotiation mode
+#define ARM_ETH_PHY_LOOPBACK            (1UL << 4)                                      ///< Loop-back test mode
+#define ARM_ETH_PHY_ISOLATE             (1UL << 5)                                      ///< Isolate PHY from MII/RMII interface
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t  fn_read,
+                                               ARM_ETH_PHY_Write_t fn_write)
+  \brief       Initialize Ethernet PHY Device.
+  \param[in]   fn_read   Pointer to \ref ARM_ETH_MAC_PHY_Read
+  \param[in]   fn_write  Pointer to \ref ARM_ETH_MAC_PHY_Write
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_Uninitialize (void)
+  \brief       De-initialize Ethernet PHY Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state)
+  \brief       Control Ethernet PHY Device Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_SetInterface (uint32_t interface)
+  \brief       Set Ethernet Media Interface.
+  \param[in]   interface  Media Interface type
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_ETH_PHY_SetMode (uint32_t mode)
+  \brief       Set Ethernet PHY Device Operation mode.
+  \param[in]   mode  Operation Mode
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void)
+  \brief       Get Ethernet PHY Device Link state.
+  \return      current link status \ref ARM_ETH_LINK_STATE
+*/
+/**
+  \fn          ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void)
+  \brief       Get Ethernet PHY Device Link information.
+  \return      current link parameters \ref ARM_ETH_LINK_INFO
+*/
+
+
+typedef int32_t (*ARM_ETH_PHY_Read_t)  (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register.
+typedef int32_t (*ARM_ETH_PHY_Write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t  data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register.
+
+
+/**
+\brief Access structure of the Ethernet PHY Driver
+*/
+typedef struct _ARM_DRIVER_ETH_PHY {
+  ARM_DRIVER_VERSION (*GetVersion)   (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetVersion : Get driver version.
+  int32_t            (*Initialize)   (ARM_ETH_PHY_Read_t  fn_read,
+                                      ARM_ETH_PHY_Write_t fn_write);  ///< Pointer to \ref ARM_ETH_PHY_Initialize : Initialize PHY Device.
+  int32_t            (*Uninitialize) (void);                          ///< Pointer to \ref ARM_ETH_PHY_Uninitialize : De-initialize PHY Device.
+  int32_t            (*PowerControl) (ARM_POWER_STATE state);         ///< Pointer to \ref ARM_ETH_PHY_PowerControl : Control PHY Device Power.
+  int32_t            (*SetInterface) (uint32_t interface);            ///< Pointer to \ref ARM_ETH_PHY_SetInterface : Set Ethernet Media Interface.
+  int32_t            (*SetMode)      (uint32_t mode);                 ///< Pointer to \ref ARM_ETH_PHY_SetMode : Set Ethernet PHY Device Operation mode.
+  ARM_ETH_LINK_STATE (*GetLinkState) (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetLinkState : Get Ethernet PHY Device Link state.
+  ARM_ETH_LINK_INFO  (*GetLinkInfo)  (void);                          ///< Pointer to \ref ARM_ETH_PHY_GetLinkInfo : Get Ethernet PHY Device Link information.
+} const ARM_DRIVER_ETH_PHY;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_ETH_PHY_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_Flash.h

@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.1
+ *
+ * Project:      Flash Driver definitions
+ */
+
+/* History:
+ *  Version 2.1
+ *    ARM_FLASH_STATUS made volatile
+ *  Version 2.0
+ *    Renamed driver NOR -> Flash (more generic)
+ *    Non-blocking operation
+ *    Added Events, Status and Capabilities
+ *    Linked Flash information (GetInfo)
+ *  Version 1.11
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_FLASH_H_
+#define DRIVER_FLASH_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_FLASH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,1)  /* API version */
+
+
+#define _ARM_Driver_Flash_(n)      Driver_Flash##n
+#define  ARM_Driver_Flash_(n) _ARM_Driver_Flash_(n)
+
+
+#define ARM_FLASH_SECTOR_INFO(addr,size) { (addr), (addr)+(size)-1 }
+
+/**
+\brief Flash Sector information
+*/
+typedef struct _ARM_FLASH_SECTOR {
+  uint32_t start;                       ///< Sector Start address
+  uint32_t end;                         ///< Sector End address (start+size-1)
+} const ARM_FLASH_SECTOR;
+
+/**
+\brief Flash information
+*/
+typedef struct _ARM_FLASH_INFO {
+  ARM_FLASH_SECTOR *sector_info;        ///< Sector layout information (NULL=Uniform sectors)
+  uint32_t          sector_count;       ///< Number of sectors
+  uint32_t          sector_size;        ///< Uniform sector size in bytes (0=sector_info used) 
+  uint32_t          page_size;          ///< Optimal programming page size in bytes
+  uint32_t          program_unit;       ///< Smallest programmable unit in bytes
+  uint8_t           erased_value;       ///< Contents of erased memory (usually 0xFF)
+} const ARM_FLASH_INFO;
+
+
+/**
+\brief Flash Status
+*/
+typedef volatile struct _ARM_FLASH_STATUS {
+  uint32_t busy     : 1;                ///< Flash busy flag
+  uint32_t error    : 1;                ///< Read/Program/Erase error flag (cleared on start of next operation)
+  uint32_t reserved : 30;
+} ARM_FLASH_STATUS;
+
+
+/****** Flash Event *****/
+#define ARM_FLASH_EVENT_READY           (1UL << 0)  ///< Flash Ready
+#define ARM_FLASH_EVENT_ERROR           (1UL << 1)  ///< Read/Program/Erase Error
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_Flash_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_FLASH_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event)
+  \brief       Initialize the Flash Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_Flash_SignalEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_Uninitialize (void)
+  \brief       De-initialize the Flash Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state)
+  \brief       Control the Flash interface power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt)
+  \brief       Read data from Flash.
+  \param[in]   addr  Data address.
+  \param[out]  data  Pointer to a buffer storing the data read from Flash.
+  \param[in]   cnt   Number of data items to read.
+  \return      number of data items read or \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt)
+  \brief       Program data to Flash.
+  \param[in]   addr  Data address.
+  \param[in]   data  Pointer to a buffer containing the data to be programmed to Flash.
+  \param[in]   cnt   Number of data items to program.
+  \return      number of data items programmed or \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_EraseSector (uint32_t addr)
+  \brief       Erase Flash Sector.
+  \param[in]   addr  Sector address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_Flash_EraseChip (void)
+  \brief       Erase complete Flash.
+               Optional function for faster full chip erase.
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_FLASH_STATUS ARM_Flash_GetStatus (void)
+  \brief       Get Flash status.
+  \return      Flash status \ref ARM_FLASH_STATUS
+*/
+/**
+  \fn          ARM_FLASH_INFO * ARM_Flash_GetInfo (void)
+  \brief       Get Flash information.
+  \return      Pointer to Flash information \ref ARM_FLASH_INFO
+*/
+
+/**
+  \fn          void ARM_Flash_SignalEvent (uint32_t event)
+  \brief       Signal Flash event.
+  \param[in]   event  Event notification mask
+  \return      none
+*/
+
+typedef void (*ARM_Flash_SignalEvent_t) (uint32_t event);    ///< Pointer to \ref ARM_Flash_SignalEvent : Signal Flash Event.
+
+
+/**
+\brief Flash Driver Capabilities.
+*/
+typedef struct _ARM_FLASH_CAPABILITIES {
+  uint32_t event_ready  : 1;            ///< Signal Flash Ready event
+  uint32_t data_width   : 2;            ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit
+  uint32_t erase_chip   : 1;            ///< Supports EraseChip operation
+  uint32_t reserved     : 28;           ///< Reserved (must be zero)
+} ARM_FLASH_CAPABILITIES;
+
+
+/**
+\brief Access structure of the Flash Driver
+*/
+typedef struct _ARM_DRIVER_FLASH {
+  ARM_DRIVER_VERSION     (*GetVersion)     (void);                                          ///< Pointer to \ref ARM_Flash_GetVersion : Get driver version.
+  ARM_FLASH_CAPABILITIES (*GetCapabilities)(void);                                          ///< Pointer to \ref ARM_Flash_GetCapabilities : Get driver capabilities.
+  int32_t                (*Initialize)     (ARM_Flash_SignalEvent_t cb_event);              ///< Pointer to \ref ARM_Flash_Initialize : Initialize Flash Interface.
+  int32_t                (*Uninitialize)   (void);                                          ///< Pointer to \ref ARM_Flash_Uninitialize : De-initialize Flash Interface.
+  int32_t                (*PowerControl)   (ARM_POWER_STATE state);                         ///< Pointer to \ref ARM_Flash_PowerControl : Control Flash Interface Power.
+  int32_t                (*ReadData)       (uint32_t addr,       void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ReadData : Read data from Flash.
+  int32_t                (*ProgramData)    (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ProgramData : Program data to Flash.
+  int32_t                (*EraseSector)    (uint32_t addr);                                 ///< Pointer to \ref ARM_Flash_EraseSector : Erase Flash Sector.
+  int32_t                (*EraseChip)      (void);                                          ///< Pointer to \ref ARM_Flash_EraseChip : Erase complete Flash.
+  ARM_FLASH_STATUS       (*GetStatus)      (void);                                          ///< Pointer to \ref ARM_Flash_GetStatus : Get Flash status.
+  ARM_FLASH_INFO *       (*GetInfo)        (void);                                          ///< Pointer to \ref ARM_Flash_GetInfo : Get Flash information.
+} const ARM_DRIVER_FLASH;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_FLASH_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_I2C.h

@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.3
+ *
+ * Project:      I2C (Inter-Integrated Circuit) Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    ARM_I2C_STATUS made volatile
+ *  Version 2.2
+ *    Removed function ARM_I2C_MasterTransfer in order to simplify drivers
+ *      and added back parameter "xfer_pending" to functions
+ *      ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
+ *  Version 2.1
+ *    Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending"
+ *      from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
+ *    Added function ARM_I2C_GetDataCount
+ *    Removed flag "address_nack" from ARM_I2C_STATUS
+ *    Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE
+ *      with event ARM_I2C_EVENT_TRANSFER_DONE
+ *    Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE
+ *    Removed parameter "arg" from function ARM_I2C_SignalEvent
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *    Added:
+ *      Slave Mode
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_I2C_H_
+#define DRIVER_I2C_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+/****** I2C Control Codes *****/
+
+#define ARM_I2C_OWN_ADDRESS             (0x01)      ///< Set Own Slave Address; arg = address 
+#define ARM_I2C_BUS_SPEED               (0x02)      ///< Set Bus Speed; arg = speed
+#define ARM_I2C_BUS_CLEAR               (0x03)      ///< Execute Bus clear: send nine clock pulses
+#define ARM_I2C_ABORT_TRANSFER          (0x04)      ///< Abort Master/Slave Transmit/Receive
+
+/*----- I2C Bus Speed -----*/
+#define ARM_I2C_BUS_SPEED_STANDARD      (0x01)      ///< Standard Speed (100kHz)
+#define ARM_I2C_BUS_SPEED_FAST          (0x02)      ///< Fast Speed     (400kHz)
+#define ARM_I2C_BUS_SPEED_FAST_PLUS     (0x03)      ///< Fast+ Speed    (  1MHz)
+#define ARM_I2C_BUS_SPEED_HIGH          (0x04)      ///< High Speed     (3.4MHz)
+
+
+/****** I2C Address Flags *****/
+
+#define ARM_I2C_ADDRESS_10BIT           (0x0400)    ///< 10-bit address flag
+#define ARM_I2C_ADDRESS_GC              (0x8000)    ///< General Call flag
+
+
+/**
+\brief I2C Status
+*/
+typedef volatile struct _ARM_I2C_STATUS {
+  uint32_t busy             : 1;        ///< Busy flag
+  uint32_t mode             : 1;        ///< Mode: 0=Slave, 1=Master
+  uint32_t direction        : 1;        ///< Direction: 0=Transmitter, 1=Receiver
+  uint32_t general_call     : 1;        ///< General Call indication (cleared on start of next Slave operation)
+  uint32_t arbitration_lost : 1;        ///< Master lost arbitration (cleared on start of next Master operation)
+  uint32_t bus_error        : 1;        ///< Bus error detected (cleared on start of next Master/Slave operation)
+  uint32_t reserved         : 26;
+} ARM_I2C_STATUS;
+
+
+/****** I2C Event *****/
+#define ARM_I2C_EVENT_TRANSFER_DONE       (1UL << 0)  ///< Master/Slave Transmit/Receive finished
+#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1)  ///< Master/Slave Transmit/Receive incomplete transfer
+#define ARM_I2C_EVENT_SLAVE_TRANSMIT      (1UL << 2)  ///< Slave Transmit operation requested
+#define ARM_I2C_EVENT_SLAVE_RECEIVE       (1UL << 3)  ///< Slave Receive operation requested
+#define ARM_I2C_EVENT_ADDRESS_NACK        (1UL << 4)  ///< Address not acknowledged from Slave
+#define ARM_I2C_EVENT_GENERAL_CALL        (1UL << 5)  ///< General Call indication
+#define ARM_I2C_EVENT_ARBITRATION_LOST    (1UL << 6)  ///< Master lost arbitration
+#define ARM_I2C_EVENT_BUS_ERROR           (1UL << 7)  ///< Bus error detected (START/STOP at illegal position)
+#define ARM_I2C_EVENT_BUS_CLEAR           (1UL << 8)  ///< Bus clear finished
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_I2C_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_I2C_CAPABILITIES
+
+  \fn          int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event)
+  \brief       Initialize I2C Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_I2C_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_Uninitialize (void)
+  \brief       De-initialize I2C Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state)
+  \brief       Control I2C Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
+  \brief       Start transmitting data as I2C Master.
+  \param[in]   addr          Slave address (7-bit or 10-bit)
+  \param[in]   data          Pointer to buffer with data to transmit to I2C Slave
+  \param[in]   num           Number of data bytes to transmit
+  \param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
+  \brief       Start receiving data as I2C Master.
+  \param[in]   addr          Slave address (7-bit or 10-bit)
+  \param[out]  data          Pointer to buffer for data to receive from I2C Slave
+  \param[in]   num           Number of data bytes to receive
+  \param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num)
+  \brief       Start transmitting data as I2C Slave.
+  \param[in]   data  Pointer to buffer with data to transmit to I2C Master
+  \param[in]   num   Number of data bytes to transmit
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num)
+  \brief       Start receiving data as I2C Slave.
+  \param[out]  data  Pointer to buffer for data to receive from I2C Master
+  \param[in]   num   Number of data bytes to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_I2C_GetDataCount (void)
+  \brief       Get transferred data count.
+  \return      number of data bytes transferred; -1 when Slave is not addressed by Master
+
+  \fn          int32_t ARM_I2C_Control (uint32_t control, uint32_t arg)
+  \brief       Control I2C Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      \ref execution_status
+
+  \fn          ARM_I2C_STATUS ARM_I2C_GetStatus (void)
+  \brief       Get I2C status.
+  \return      I2C status \ref ARM_I2C_STATUS
+
+  \fn          void ARM_I2C_SignalEvent (uint32_t event)
+  \brief       Signal I2C Events.
+  \param[in]   event  \ref I2C_events notification mask
+*/
+
+typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event.
+
+
+/**
+\brief I2C Driver Capabilities.
+*/
+typedef struct _ARM_I2C_CAPABILITIES {
+  uint32_t address_10_bit : 1;          ///< supports 10-bit addressing
+  uint32_t reserved       : 31;         ///< Reserved (must be zero)
+} ARM_I2C_CAPABILITIES;
+
+
+/**
+\brief Access structure of the I2C Driver.
+*/
+typedef struct _ARM_DRIVER_I2C {
+  ARM_DRIVER_VERSION   (*GetVersion)     (void);                                                                ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version.
+  ARM_I2C_CAPABILITIES (*GetCapabilities)(void);                                                                ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)     (ARM_I2C_SignalEvent_t cb_event);                                      ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface.
+  int32_t              (*Uninitialize)   (void);                                                                ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface.
+  int32_t              (*PowerControl)   (ARM_POWER_STATE state);                                               ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power.
+  int32_t              (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master.
+  int32_t              (*MasterReceive)  (uint32_t addr,       uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master.
+  int32_t              (*SlaveTransmit)  (               const uint8_t *data, uint32_t num);                    ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave.
+  int32_t              (*SlaveReceive)   (                     uint8_t *data, uint32_t num);                    ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave.
+  int32_t              (*GetDataCount)   (void);                                                                ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count.
+  int32_t              (*Control)        (uint32_t control, uint32_t arg);                                      ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface.
+  ARM_I2C_STATUS       (*GetStatus)      (void);                                                                ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status.
+} const ARM_DRIVER_I2C;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_I2C_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_MCI.h

@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.3
+ *
+ * Project:      MCI (Memory Card Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    ARM_MCI_STATUS made volatile
+ *  Version 2.2
+ *    Added timeout and error flags to ARM_MCI_STATUS
+ *    Added support for controlling optional RST_n pin (eMMC)
+ *    Removed explicit Clock Control (ARM_MCI_CONTROL_CLOCK)
+ *    Removed event ARM_MCI_EVENT_BOOT_ACK_TIMEOUT
+ *  Version 2.1
+ *    Decoupled SPI mode from MCI driver
+ *    Replaced function ARM_MCI_CardSwitchRead with ARM_MCI_ReadCD and ARM_MCI_ReadWP
+ *  Version 2.0
+ *    Added support for:
+ *      SD UHS-I (Ultra High Speed)
+ *      SD I/O Interrupt
+ *      Read Wait (SD I/O)
+ *      Suspend/Resume (SD I/O)
+ *      MMC Interrupt
+ *      MMC Boot
+ *      Stream Data transfer (MMC)
+ *      VCCQ Power Supply Control (eMMC)
+ *      Command Completion Signal (CCS) for CE-ATA
+ *    Added ARM_MCI_Control function
+ *    Added ARM_MCI_GetStatus function
+ *    Removed ARM_MCI_BusMode, ARM_MCI_BusDataWidth, ARM_MCI_BusSingaling functions
+ *      (replaced by ARM_MCI_Control)
+ *    Changed ARM_MCI_CardPower function (voltage parameter)
+ *    Changed ARM_MCI_SendCommnad function (flags parameter)
+ *    Changed ARM_MCI_SetupTransfer function (mode parameter)
+ *    Removed ARM_MCI_ReadTransfer and ARM_MCI_WriteTransfer functions
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_MCI_H_
+#define DRIVER_MCI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+/****** MCI Send Command Flags *****/
+#define ARM_MCI_RESPONSE_Pos             0
+#define ARM_MCI_RESPONSE_Msk            (3UL << ARM_MCI_RESPONSE_Pos)
+#define ARM_MCI_RESPONSE_NONE           (0UL << ARM_MCI_RESPONSE_Pos)   ///< No response expected (default)
+#define ARM_MCI_RESPONSE_SHORT          (1UL << ARM_MCI_RESPONSE_Pos)   ///< Short response (48-bit)
+#define ARM_MCI_RESPONSE_SHORT_BUSY     (2UL << ARM_MCI_RESPONSE_Pos)   ///< Short response with busy signal (48-bit)
+#define ARM_MCI_RESPONSE_LONG           (3UL << ARM_MCI_RESPONSE_Pos)   ///< Long response (136-bit)
+
+#define ARM_MCI_RESPONSE_INDEX          (1UL << 2)  ///< Check command index in response
+#define ARM_MCI_RESPONSE_CRC            (1UL << 3)  ///< Check CRC in response
+
+#define ARM_MCI_WAIT_BUSY               (1UL << 4)  ///< Wait until busy before sending the command
+
+#define ARM_MCI_TRANSFER_DATA           (1UL << 5)  ///< Activate Data transfer
+
+#define ARM_MCI_CARD_INITIALIZE         (1UL << 6)  ///< Execute Memory Card initialization sequence
+
+#define ARM_MCI_INTERRUPT_COMMAND       (1UL << 7)  ///< Send Interrupt command (CMD40 - MMC only)
+#define ARM_MCI_INTERRUPT_RESPONSE      (1UL << 8)  ///< Send Interrupt response (CMD40 - MMC only)
+
+#define ARM_MCI_BOOT_OPERATION          (1UL << 9)  ///< Execute Boot operation (MMC only)
+#define ARM_MCI_BOOT_ALTERNATIVE        (1UL << 10) ///< Execute Alternative Boot operation (MMC only)
+#define ARM_MCI_BOOT_ACK                (1UL << 11) ///< Expect Boot Acknowledge (MMC only)
+
+#define ARM_MCI_CCSD                    (1UL << 12) ///< Send Command Completion Signal Disable (CCSD) for CE-ATA device
+#define ARM_MCI_CCS                     (1UL << 13) ///< Expect Command Completion Signal (CCS) for CE-ATA device
+
+
+/****** MCI Setup Transfer Mode *****/
+#define ARM_MCI_TRANSFER_READ           (0UL << 0)  ///< Data Read Transfer (from MCI)
+#define ARM_MCI_TRANSFER_WRITE          (1UL << 0)  ///< Data Write Transfer (to MCI)
+#define ARM_MCI_TRANSFER_BLOCK          (0UL << 1)  ///< Block Data transfer (default)
+#define ARM_MCI_TRANSFER_STREAM         (1UL << 1)  ///< Stream Data transfer (MMC only)
+
+
+/****** MCI Control Codes *****/
+#define ARM_MCI_BUS_SPEED               (0x01)      ///< Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s
+#define ARM_MCI_BUS_SPEED_MODE          (0x02)      ///< Set Bus Speed Mode as specified with arg
+#define ARM_MCI_BUS_CMD_MODE            (0x03)      ///< Set CMD Line Mode as specified with arg
+#define ARM_MCI_BUS_DATA_WIDTH          (0x04)      ///< Set Bus Data Width as specified with arg
+#define ARM_MCI_DRIVER_STRENGTH         (0x05)      ///< Set SD UHS-I Driver Strength as specified with arg 
+#define ARM_MCI_CONTROL_RESET           (0x06)      ///< Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active 
+#define ARM_MCI_CONTROL_CLOCK_IDLE      (0x07)      ///< Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled
+#define ARM_MCI_UHS_TUNING_OPERATION    (0x08)      ///< Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute
+#define ARM_MCI_UHS_TUNING_RESULT       (0x09)      ///< Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error
+#define ARM_MCI_DATA_TIMEOUT            (0x0A)      ///< Set Data timeout; arg = timeout in bus cycles
+#define ARM_MCI_CSS_TIMEOUT             (0x0B)      ///< Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles
+#define ARM_MCI_MONITOR_SDIO_INTERRUPT  (0x0C)      ///< Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled
+#define ARM_MCI_CONTROL_READ_WAIT       (0x0D)      ///< Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled
+#define ARM_MCI_SUSPEND_TRANSFER        (0x0E)      ///< Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer
+#define ARM_MCI_RESUME_TRANSFER         (0x0F)      ///< Resume Data transfer (SD I/O)
+
+/*----- MCI Bus Speed Mode -----*/
+#define ARM_MCI_BUS_DEFAULT_SPEED       (0x00)      ///< SD/MMC: Default Speed mode up to 25/26MHz
+#define ARM_MCI_BUS_HIGH_SPEED          (0x01)      ///< SD/MMC: High    Speed mode up to 50/52MHz
+#define ARM_MCI_BUS_UHS_SDR12           (0x02)      ///< SD: SDR12  (Single Data Rate) up to  25MHz,  12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR25           (0x03)      ///< SD: SDR25  (Single Data Rate) up to  50MHz,  25  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR50           (0x04)      ///< SD: SDR50  (Single Data Rate) up to 100MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_SDR104          (0x05)      ///< SD: SDR104 (Single Data Rate) up to 208MHz, 104  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+#define ARM_MCI_BUS_UHS_DDR50           (0x06)      ///< SD: DDR50  (Dual Data Rate)   up to  50MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signaling
+
+/*----- MCI CMD Line Mode -----*/
+#define ARM_MCI_BUS_CMD_PUSH_PULL       (0x00)      ///< Push-Pull CMD line (default)
+#define ARM_MCI_BUS_CMD_OPEN_DRAIN      (0x01)      ///< Open Drain CMD line (MMC only)
+
+/*----- MCI Bus Data Width -----*/
+#define ARM_MCI_BUS_DATA_WIDTH_1        (0x00)      ///< Bus data width: 1 bit (default)
+#define ARM_MCI_BUS_DATA_WIDTH_4        (0x01)      ///< Bus data width: 4 bits
+#define ARM_MCI_BUS_DATA_WIDTH_8        (0x02)      ///< Bus data width: 8 bits
+#define ARM_MCI_BUS_DATA_WIDTH_4_DDR    (0x03)      ///< Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only
+#define ARM_MCI_BUS_DATA_WIDTH_8_DDR    (0x04)      ///< Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only
+
+/*----- MCI Driver Strength -----*/
+#define ARM_MCI_DRIVER_TYPE_A           (0x01)      ///< SD UHS-I Driver Type A
+#define ARM_MCI_DRIVER_TYPE_B           (0x00)      ///< SD UHS-I Driver Type B (default)
+#define ARM_MCI_DRIVER_TYPE_C           (0x02)      ///< SD UHS-I Driver Type C
+#define ARM_MCI_DRIVER_TYPE_D           (0x03)      ///< SD UHS-I Driver Type D
+
+
+/****** MCI Card Power *****/
+#define ARM_MCI_POWER_VDD_Pos            0
+#define ARM_MCI_POWER_VDD_Msk           (0x0FUL << ARM_MCI_POWER_VDD_Pos)
+#define ARM_MCI_POWER_VDD_OFF           (0x01UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) turned off
+#define ARM_MCI_POWER_VDD_3V3           (0x02UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) = 3.3V
+#define ARM_MCI_POWER_VDD_1V8           (0x03UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) = 1.8V
+#define ARM_MCI_POWER_VCCQ_Pos           4
+#define ARM_MCI_POWER_VCCQ_Msk          (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)
+#define ARM_MCI_POWER_VCCQ_OFF          (0x01UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ turned off
+#define ARM_MCI_POWER_VCCQ_3V3          (0x02UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 3.3V
+#define ARM_MCI_POWER_VCCQ_1V8          (0x03UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 1.8V
+#define ARM_MCI_POWER_VCCQ_1V2          (0x04UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 1.2V
+
+
+/**
+\brief MCI Status
+*/
+typedef volatile struct _ARM_MCI_STATUS {
+  uint32_t command_active   : 1;        ///< Command active flag
+  uint32_t command_timeout  : 1;        ///< Command timeout flag (cleared on start of next command)
+  uint32_t command_error    : 1;        ///< Command error flag (cleared on start of next command)
+  uint32_t transfer_active  : 1;        ///< Transfer active flag
+  uint32_t transfer_timeout : 1;        ///< Transfer timeout flag (cleared on start of next command)
+  uint32_t transfer_error   : 1;        ///< Transfer error flag (cleared on start of next command)
+  uint32_t sdio_interrupt   : 1;        ///< SD I/O Interrupt flag (cleared on start of monitoring)
+  uint32_t ccs              : 1;        ///< CCS flag (cleared on start of next command)
+  uint32_t reserved         : 24;
+} ARM_MCI_STATUS;
+
+
+/****** MCI Card Event *****/
+#define ARM_MCI_EVENT_CARD_INSERTED     (1UL << 0)  ///< Memory Card inserted
+#define ARM_MCI_EVENT_CARD_REMOVED      (1UL << 1)  ///< Memory Card removed
+#define ARM_MCI_EVENT_COMMAND_COMPLETE  (1UL << 2)  ///< Command completed
+#define ARM_MCI_EVENT_COMMAND_TIMEOUT   (1UL << 3)  ///< Command timeout
+#define ARM_MCI_EVENT_COMMAND_ERROR     (1UL << 4)  ///< Command response error (CRC error or invalid response)
+#define ARM_MCI_EVENT_TRANSFER_COMPLETE (1UL << 5)  ///< Data transfer completed
+#define ARM_MCI_EVENT_TRANSFER_TIMEOUT  (1UL << 6)  ///< Data transfer timeout
+#define ARM_MCI_EVENT_TRANSFER_ERROR    (1UL << 7)  ///< Data transfer CRC failed
+#define ARM_MCI_EVENT_SDIO_INTERRUPT    (1UL << 8)  ///< SD I/O Interrupt
+#define ARM_MCI_EVENT_CCS               (1UL << 9)  ///< Command Completion Signal (CCS)
+#define ARM_MCI_EVENT_CCS_TIMEOUT       (1UL << 10) ///< Command Completion Signal (CCS) Timeout
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_MCI_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_MCI_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event)
+  \brief         Initialize the Memory Card Interface
+  \param[in]     cb_event  Pointer to \ref ARM_MCI_SignalEvent
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_Uninitialize (void)
+  \brief         De-initialize Memory Card Interface.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_PowerControl (ARM_POWER_STATE state)
+  \brief         Control Memory Card Interface Power.
+  \param[in]     state   Power state \ref ARM_POWER_STATE
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_CardPower (uint32_t voltage)
+  \brief         Set Memory Card Power supply voltage.
+  \param[in]     voltage  Memory Card Power supply voltage
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_ReadCD (void)
+  \brief         Read Card Detect (CD) state.
+  \return        1:card detected, 0:card not detected, or error
+*/
+/**
+  \fn            int32_t ARM_MCI_ReadWP (void)
+  \brief         Read Write Protect (WP) state.
+  \return        1:write protected, 0:not write protected, or error
+*/
+/**
+  \fn            int32_t ARM_MCI_SendCommand (uint32_t  cmd,
+                                              uint32_t  arg,
+                                              uint32_t  flags,
+                                              uint32_t *response)
+  \brief         Send Command to card and get the response.
+  \param[in]     cmd       Memory Card command
+  \param[in]     arg       Command argument
+  \param[in]     flags     Command flags
+  \param[out]    response  Pointer to buffer for response
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_SetupTransfer (uint8_t *data,
+                                                uint32_t block_count,
+                                                uint32_t block_size,
+                                                uint32_t mode)
+  \brief         Setup read or write transfer operation.
+  \param[in,out] data         Pointer to data block(s) to be written or read
+  \param[in]     block_count  Number of blocks
+  \param[in]     block_size   Size of a block in bytes
+  \param[in]     mode         Transfer mode
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_AbortTransfer (void)
+  \brief         Abort current read/write data transfer.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_MCI_Control (uint32_t control, uint32_t arg)
+  \brief         Control MCI Interface.
+  \param[in]     control  Operation
+  \param[in]     arg      Argument of operation (optional)
+  \return        \ref execution_status
+*/
+/**
+  \fn            ARM_MCI_STATUS ARM_MCI_GetStatus (void)
+  \brief         Get MCI status.
+  \return        MCI status \ref ARM_MCI_STATUS
+*/
+
+/**
+  \fn            void ARM_MCI_SignalEvent (uint32_t event)
+  \brief         Callback function that signals a MCI Card Event.
+  \param[in]     event \ref mci_event_gr
+  \return        none
+*/
+
+typedef void (*ARM_MCI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_MCI_SignalEvent : Signal MCI Card Event.
+
+
+/**
+\brief  MCI Driver Capabilities.
+*/
+typedef struct _ARM_MCI_CAPABILITIES {
+  uint32_t cd_state          : 1;       ///< Card Detect State available
+  uint32_t cd_event          : 1;       ///< Signal Card Detect change event
+  uint32_t wp_state          : 1;       ///< Write Protect State available
+  uint32_t vdd               : 1;       ///< Supports VDD Card Power Supply Control
+  uint32_t vdd_1v8           : 1;       ///< Supports 1.8 VDD Card Power Supply
+  uint32_t vccq              : 1;       ///< Supports VCCQ Card Power Supply Control (eMMC)
+  uint32_t vccq_1v8          : 1;       ///< Supports 1.8 VCCQ Card Power Supply (eMMC)
+  uint32_t vccq_1v2          : 1;       ///< Supports 1.2 VCCQ Card Power Supply (eMMC)
+  uint32_t data_width_4      : 1;       ///< Supports 4-bit data
+  uint32_t data_width_8      : 1;       ///< Supports 8-bit data
+  uint32_t data_width_4_ddr  : 1;       ///< Supports 4-bit data, DDR (Dual Data Rate) - MMC only
+  uint32_t data_width_8_ddr  : 1;       ///< Supports 8-bit data, DDR (Dual Data Rate) - MMC only
+  uint32_t high_speed        : 1;       ///< Supports SD/MMC High Speed Mode
+  uint32_t uhs_signaling     : 1;       ///< Supports SD UHS-I (Ultra High Speed) 1.8V signaling 
+  uint32_t uhs_tuning        : 1;       ///< Supports SD UHS-I tuning 
+  uint32_t uhs_sdr50         : 1;       ///< Supports SD UHS-I SDR50  (Single Data Rate) up to  50MB/s
+  uint32_t uhs_sdr104        : 1;       ///< Supports SD UHS-I SDR104 (Single Data Rate) up to 104MB/s
+  uint32_t uhs_ddr50         : 1;       ///< Supports SD UHS-I DDR50  (Dual   Data Rate) up to  50MB/s
+  uint32_t uhs_driver_type_a : 1;       ///< Supports SD UHS-I Driver Type A
+  uint32_t uhs_driver_type_c : 1;       ///< Supports SD UHS-I Driver Type C
+  uint32_t uhs_driver_type_d : 1;       ///< Supports SD UHS-I Driver Type D 
+  uint32_t sdio_interrupt    : 1;       ///< Supports SD I/O Interrupt 
+  uint32_t read_wait         : 1;       ///< Supports Read Wait (SD I/O)
+  uint32_t suspend_resume    : 1;       ///< Supports Suspend/Resume (SD I/O)
+  uint32_t mmc_interrupt     : 1;       ///< Supports MMC Interrupt 
+  uint32_t mmc_boot          : 1;       ///< Supports MMC Boot 
+  uint32_t rst_n             : 1;       ///< Supports RST_n Pin Control (eMMC)
+  uint32_t ccs               : 1;       ///< Supports Command Completion Signal (CCS) for CE-ATA
+  uint32_t ccs_timeout       : 1;       ///< Supports Command Completion Signal (CCS) timeout for CE-ATA
+  uint32_t reserved          : 3;       ///< Reserved (must be zero)
+} ARM_MCI_CAPABILITIES;
+
+
+/**
+\brief  Access structure of the MCI Driver.
+*/
+typedef struct _ARM_DRIVER_MCI {
+  ARM_DRIVER_VERSION   (*GetVersion)     (void);                           ///< Pointer to \ref ARM_MCI_GetVersion : Get driver version.
+  ARM_MCI_CAPABILITIES (*GetCapabilities)(void);                           ///< Pointer to \ref ARM_MCI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)     (ARM_MCI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_MCI_Initialize : Initialize MCI Interface.
+  int32_t              (*Uninitialize)   (void);                           ///< Pointer to \ref ARM_MCI_Uninitialize : De-initialize MCI Interface.
+  int32_t              (*PowerControl)   (ARM_POWER_STATE state);          ///< Pointer to \ref ARM_MCI_PowerControl : Control MCI Interface Power.
+  int32_t              (*CardPower)      (uint32_t voltage);               ///< Pointer to \ref ARM_MCI_CardPower : Set card power supply voltage.
+  int32_t              (*ReadCD)         (void);                           ///< Pointer to \ref ARM_MCI_ReadCD : Read Card Detect (CD) state.
+  int32_t              (*ReadWP)         (void);                           ///< Pointer to \ref ARM_MCI_ReadWP : Read Write Protect (WP) state.
+  int32_t              (*SendCommand)    (uint32_t cmd, 
+                                          uint32_t arg, 
+                                          uint32_t flags,
+                                          uint32_t *response);             ///< Pointer to \ref ARM_MCI_SendCommand : Send Command to card and get the response.
+  int32_t              (*SetupTransfer)  (uint8_t *data,
+                                          uint32_t block_count,
+                                          uint32_t block_size,
+                                          uint32_t mode);                  ///< Pointer to \ref ARM_MCI_SetupTransfer : Setup data transfer operation.
+  int32_t              (*AbortTransfer)  (void);                           ///< Pointer to \ref ARM_MCI_AbortTransfer : Abort current data transfer.
+  int32_t              (*Control)        (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_MCI_Control : Control MCI Interface.
+  ARM_MCI_STATUS       (*GetStatus)      (void);                           ///< Pointer to \ref ARM_MCI_GetStatus : Get MCI status.
+} const ARM_DRIVER_MCI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_MCI_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_NAND.h

@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        14. Nov 2017
+ * $Revision:    V2.3
+ *
+ * Project:      NAND Flash Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    Extended ARM_NAND_ECC_INFO structure
+ *  Version 2.2
+ *    ARM_NAND_STATUS made volatile
+ *  Version 2.1
+ *    Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (command agnostic)
+ *    Added support for:
+ *      NV-DDR & NV-DDR2 Interface (ONFI specification)
+ *      VCC, VCCQ and VPP Power Supply Control
+ *      WP (Write Protect) Control
+ *  Version 1.11
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_NAND_H_
+#define DRIVER_NAND_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+/****** NAND Device Power *****/
+#define ARM_NAND_POWER_VCC_Pos           0
+#define ARM_NAND_POWER_VCC_Msk          (0x07UL << ARM_NAND_POWER_VCC_Pos)
+#define ARM_NAND_POWER_VCC_OFF          (0x01UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC Power off
+#define ARM_NAND_POWER_VCC_3V3          (0x02UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC = 3.3V
+#define ARM_NAND_POWER_VCC_1V8          (0x03UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC = 1.8V
+#define ARM_NAND_POWER_VCCQ_Pos          3
+#define ARM_NAND_POWER_VCCQ_Msk         (0x07UL << ARM_NAND_POWER_VCCQ_Pos)
+#define ARM_NAND_POWER_VCCQ_OFF         (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off
+#define ARM_NAND_POWER_VCCQ_3V3         (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V
+#define ARM_NAND_POWER_VCCQ_1V8         (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V
+#define ARM_NAND_POWER_VPP_OFF          (1UL << 6)                          ///< VPP off
+#define ARM_NAND_POWER_VPP_ON           (1Ul << 7)                          ///< VPP on
+
+
+/****** NAND Control Codes *****/
+#define ARM_NAND_BUS_MODE               (0x01)      ///< Set Bus Mode as specified with arg
+#define ARM_NAND_BUS_DATA_WIDTH         (0x02)      ///< Set Bus Data Width as specified with arg
+#define ARM_NAND_DRIVER_STRENGTH        (0x03)      ///< Set Driver Strength as specified with arg
+#define ARM_NAND_DEVICE_READY_EVENT     (0x04)      ///< Generate \ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled 
+#define ARM_NAND_DRIVER_READY_EVENT     (0x05)      ///< Generate \ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled 
+
+/*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/
+#define ARM_NAND_BUS_INTERFACE_Pos       4
+#define ARM_NAND_BUS_INTERFACE_Msk      (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)
+#define ARM_NAND_BUS_SDR                (0x00UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface:    SDR  (Single Data Rate) - Traditional interface (default)
+#define ARM_NAND_BUS_DDR                (0x01UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface: NV-DDR  (Double Data Rate)
+#define ARM_NAND_BUS_DDR2               (0x02UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface: NV-DDR2 (Double Data Rate)
+#define ARM_NAND_BUS_TIMING_MODE_Pos     0
+#define ARM_NAND_BUS_TIMING_MODE_Msk    (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)
+#define ARM_NAND_BUS_TIMING_MODE_0      (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 0 (default)
+#define ARM_NAND_BUS_TIMING_MODE_1      (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 1
+#define ARM_NAND_BUS_TIMING_MODE_2      (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 2
+#define ARM_NAND_BUS_TIMING_MODE_3      (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 3
+#define ARM_NAND_BUS_TIMING_MODE_4      (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 4 (SDR EDO capable)
+#define ARM_NAND_BUS_TIMING_MODE_5      (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 5 (SDR EDO capable)
+#define ARM_NAND_BUS_TIMING_MODE_6      (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 6 (NV-DDR2 only)
+#define ARM_NAND_BUS_TIMING_MODE_7      (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 7 (NV-DDR2 only)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos    8
+#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_0     (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 0 (default)
+#define ARM_NAND_BUS_DDR2_DO_WCYC_1     (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 1
+#define ARM_NAND_BUS_DDR2_DO_WCYC_2     (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 2
+#define ARM_NAND_BUS_DDR2_DO_WCYC_4     (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 4
+#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos    12
+#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
+#define ARM_NAND_BUS_DDR2_DI_WCYC_0     (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 0 (default)
+#define ARM_NAND_BUS_DDR2_DI_WCYC_1     (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 1
+#define ARM_NAND_BUS_DDR2_DI_WCYC_2     (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 2
+#define ARM_NAND_BUS_DDR2_DI_WCYC_4     (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 4
+#define ARM_NAND_BUS_DDR2_VEN           (1UL << 16)                               ///< DDR2 Enable external VREFQ as reference
+#define ARM_NAND_BUS_DDR2_CMPD          (1UL << 17)                               ///< DDR2 Enable complementary DQS (DQS_c) signal
+#define ARM_NAND_BUS_DDR2_CMPR          (1UL << 18)                               ///< DDR2 Enable complementary RE_n (RE_c) signal
+
+/*----- NAND Data Bus Width -----*/
+#define ARM_NAND_BUS_DATA_WIDTH_8       (0x00)      ///< Bus Data Width:  8 bit (default)
+#define ARM_NAND_BUS_DATA_WIDTH_16      (0x01)      ///< Bus Data Width: 16 bit
+
+/*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/
+#define ARM_NAND_DRIVER_STRENGTH_18     (0x00)      ///< Driver Strength 2.0x = 18 Ohms
+#define ARM_NAND_DRIVER_STRENGTH_25     (0x01)      ///< Driver Strength 1.4x = 25 Ohms
+#define ARM_NAND_DRIVER_STRENGTH_35     (0x02)      ///< Driver Strength 1.0x = 35 Ohms (default)
+#define ARM_NAND_DRIVER_STRENGTH_50     (0x03)      ///< Driver Strength 0.7x = 50 Ohms
+
+
+/****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/
+#define ARM_NAND_ECC_INDEX_Pos           0
+#define ARM_NAND_ECC_INDEX_Msk          (0xFFUL << ARM_NAND_ECC_INDEX_Pos)
+#define ARM_NAND_ECC(n)                 ((n) & ARM_NAND_ECC_INDEX_Msk)     ///< Select ECC
+#define ARM_NAND_ECC0                   (1UL << 8)                         ///< Use ECC0 of selected ECC
+#define ARM_NAND_ECC1                   (1UL << 9)                         ///< Use ECC1 of selected ECC
+
+/****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/
+#define ARM_NAND_DRIVER_DONE_EVENT      (1UL << 16) ///< Generate \ref ARM_NAND_EVENT_DRIVER_DONE
+
+/****** NAND Sequence Execution Code *****/
+#define ARM_NAND_CODE_SEND_CMD1         (1UL << 17) ///< Send Command 1
+#define ARM_NAND_CODE_SEND_ADDR_COL1    (1UL << 18) ///< Send Column Address 1
+#define ARM_NAND_CODE_SEND_ADDR_COL2    (1UL << 19) ///< Send Column Address 2
+#define ARM_NAND_CODE_SEND_ADDR_ROW1    (1UL << 20) ///< Send Row Address 1
+#define ARM_NAND_CODE_SEND_ADDR_ROW2    (1UL << 21) ///< Send Row Address 2
+#define ARM_NAND_CODE_SEND_ADDR_ROW3    (1UL << 22) ///< Send Row Address 3
+#define ARM_NAND_CODE_INC_ADDR_ROW      (1UL << 23) ///< Auto-increment Row Address
+#define ARM_NAND_CODE_WRITE_DATA        (1UL << 24) ///< Write Data
+#define ARM_NAND_CODE_SEND_CMD2         (1UL << 25) ///< Send Command 2
+#define ARM_NAND_CODE_WAIT_BUSY         (1UL << 26) ///< Wait while R/Bn busy
+#define ARM_NAND_CODE_READ_DATA         (1UL << 27) ///< Read Data
+#define ARM_NAND_CODE_SEND_CMD3         (1UL << 28) ///< Send Command 3
+#define ARM_NAND_CODE_READ_STATUS       (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0)
+
+/*----- NAND Sequence Execution Code: Command -----*/
+#define ARM_NAND_CODE_CMD1_Pos           0
+#define ARM_NAND_CODE_CMD1_Msk          (0xFFUL << ARM_NAND_CODE_CMD1_Pos)
+#define ARM_NAND_CODE_CMD2_Pos           8
+#define ARM_NAND_CODE_CMD2_Msk          (0xFFUL << ARM_NAND_CODE_CMD2_Pos)
+#define ARM_NAND_CODE_CMD3_Pos           16
+#define ARM_NAND_CODE_CMD3_Msk          (0xFFUL << ARM_NAND_CODE_CMD3_Pos)
+
+/*----- NAND Sequence Execution Code: Column Address -----*/
+#define ARM_NAND_CODE_ADDR_COL1_Pos      0
+#define ARM_NAND_CODE_ADDR_COL1_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)
+#define ARM_NAND_CODE_ADDR_COL2_Pos      8
+#define ARM_NAND_CODE_ADDR_COL2_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)
+
+/*----- NAND Sequence Execution Code: Row Address -----*/
+#define ARM_NAND_CODE_ADDR_ROW1_Pos      0
+#define ARM_NAND_CODE_ADDR_ROW1_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)
+#define ARM_NAND_CODE_ADDR_ROW2_Pos      8
+#define ARM_NAND_CODE_ADDR_ROW2_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)
+#define ARM_NAND_CODE_ADDR_ROW3_Pos      16
+#define ARM_NAND_CODE_ADDR_ROW3_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)
+
+
+/****** NAND specific error codes *****/
+#define ARM_NAND_ERROR_ECC              (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< ECC generation/correction failed
+
+
+/**
+\brief NAND ECC (Error Correction Code) Information
+*/
+typedef struct _ARM_NAND_ECC_INFO {
+  uint32_t type             :  2;       ///< Type: 1=ECC0 over Main, 2=ECC0 over Main+Spare, 3=ECC0 over Main and ECC1 over Spare
+  uint32_t page_layout      :  1;       ///< Page layout: 0=|Main0|Spare0|...|MainN-1|SpareN-1|, 1=|Main0|...|MainN-1|Spare0|...|SpareN-1|
+  uint32_t page_count       :  3;       ///< Number of virtual pages: N = 2 ^ page_count
+  uint32_t page_size        :  4;       ///< Virtual Page size (Main+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448, 15=Not used (extended description)
+  uint32_t reserved         : 14;       ///< Reserved (must be zero)
+  uint32_t correctable_bits :  8;       ///< Number of correctable bits (based on 512 byte codeword size)
+  uint16_t codeword_size     [2];       ///< Number of bytes over which ECC is calculated
+  uint16_t ecc_size          [2];       ///< ECC size in bytes (rounded up)
+  uint16_t ecc_offset        [2];       ///< ECC offset in bytes (where ECC starts in Spare)
+  /* Extended description */
+  uint16_t virtual_page_size [2];       ///< Virtual Page size in bytes (Main/Spare)
+  uint16_t codeword_offset   [2];       ///< Codeword offset in bytes (where ECC protected data starts in Main/Spare)
+  uint16_t codeword_gap      [2];       ///< Codeword gap in bytes till next protected data
+  uint16_t ecc_gap           [2];       ///< ECC gap in bytes till next generated ECC
+} ARM_NAND_ECC_INFO;
+
+
+/**
+\brief NAND Status
+*/
+typedef volatile struct _ARM_NAND_STATUS {
+  uint32_t busy      : 1;               ///< Driver busy flag
+  uint32_t ecc_error : 1;               ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence)
+  uint32_t reserved  : 30;
+} ARM_NAND_STATUS;
+
+
+/****** NAND Event *****/
+#define ARM_NAND_EVENT_DEVICE_READY     (1UL << 0)  ///< Device Ready: R/Bn rising edge
+#define ARM_NAND_EVENT_DRIVER_READY     (1UL << 1)  ///< Driver Ready
+#define ARM_NAND_EVENT_DRIVER_DONE      (1UL << 2)  ///< Driver operation done
+#define ARM_NAND_EVENT_ECC_ERROR        (1UL << 3)  ///< ECC could not correct data
+
+
+// Function documentation
+/**
+  \fn            ARM_DRIVER_VERSION ARM_NAND_GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn            ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_NAND_CAPABILITIES
+*/
+/**
+  \fn            int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event)
+  \brief         Initialize the NAND Interface.
+  \param[in]     cb_event  Pointer to \ref ARM_NAND_SignalEvent
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_Uninitialize (void)
+  \brief         De-initialize the NAND Interface.
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state)
+  \brief         Control the NAND interface power.
+  \param[in]     state  Power state
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_DevicePower (uint32_t voltage)
+  \brief         Set device power supply voltage.
+  \param[in]     voltage  NAND Device supply voltage
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable)
+  \brief         Control WPn (Write Protect).
+  \param[in]     dev_num  Device number
+  \param[in]     enable
+                - \b false Write Protect off
+                - \b true  Write Protect on
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable)
+  \brief         Control CEn (Chip Enable).
+  \param[in]     dev_num  Device number
+  \param[in]     enable
+                - \b false Chip Enable off
+                - \b true  Chip Enable on
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num)
+  \brief         Get Device Busy pin state.
+  \param[in]     dev_num  Device number
+  \return        1=busy, 0=not busy, or error
+*/
+/**
+  \fn            int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd)
+  \brief         Send command to NAND device.
+  \param[in]     dev_num  Device number
+  \param[in]     cmd      Command
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr)
+  \brief         Send address to NAND device.
+  \param[in]     dev_num  Device number
+  \param[in]     addr     Address
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)
+  \brief         Read data from NAND device.
+  \param[in]     dev_num  Device number
+  \param[out]    data     Pointer to buffer for data to read from NAND device
+  \param[in]     cnt      Number of data items to read
+  \param[in]     mode     Operation mode
+  \return        number of data items read or \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)
+  \brief         Write data to NAND device.
+  \param[in]     dev_num  Device number
+  \param[out]    data     Pointer to buffer with data to write to NAND device
+  \param[in]     cnt      Number of data items to write
+  \param[in]     mode     Operation mode
+  \return        number of data items written or \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,
+                                                   uint32_t addr_col, uint32_t addr_row,
+                                                   void *data, uint32_t data_cnt,
+                                                   uint8_t *status, uint32_t *count)
+  \brief         Execute sequence of operations.
+  \param[in]     dev_num  Device number
+  \param[in]     code     Sequence code
+  \param[in]     cmd      Command(s)
+  \param[in]     addr_col Column address
+  \param[in]     addr_row Row address
+  \param[in,out] data     Pointer to data to be written or read 
+  \param[in]     data_cnt Number of data items in one iteration
+  \param[out]    status   Pointer to status read
+  \param[in,out] count    Number of iterations
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_AbortSequence (uint32_t dev_num)
+  \brief         Abort sequence execution.
+  \param[in]     dev_num  Device number
+  \return        \ref execution_status
+*/
+/**
+  \fn            int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg)
+  \brief         Control NAND Interface.
+  \param[in]     dev_num  Device number
+  \param[in]     control  Operation
+  \param[in]     arg      Argument of operation
+  \return        \ref execution_status
+*/
+/**
+  \fn            ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num)
+  \brief         Get NAND status.
+  \param[in]     dev_num  Device number
+  \return        NAND status \ref ARM_NAND_STATUS
+*/
+/**
+  \fn            int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info)
+  \brief         Inquire about available ECC.
+  \param[in]     index   Inquire ECC index
+  \param[out]    info    Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved
+  \return        \ref execution_status
+*/
+
+/**
+  \fn            void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event)
+  \brief         Signal NAND event.
+  \param[in]     dev_num  Device number
+  \param[in]     event    Event notification mask
+  \return        none
+*/
+
+typedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event);    ///< Pointer to \ref ARM_NAND_SignalEvent : Signal NAND Event.
+
+
+/**
+\brief NAND Driver Capabilities.
+*/
+typedef struct _ARM_NAND_CAPABILITIES {
+  uint32_t event_device_ready  : 1;     ///< Signal Device Ready event (R/Bn rising edge)
+  uint32_t reentrant_operation : 1;     ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData)
+  uint32_t sequence_operation  : 1;     ///< Supports Sequence operation (ExecuteSequence, AbortSequence)
+  uint32_t vcc                 : 1;     ///< Supports VCC Power Supply Control
+  uint32_t vcc_1v8             : 1;     ///< Supports 1.8 VCC Power Supply
+  uint32_t vccq                : 1;     ///< Supports VCCQ I/O Power Supply Control
+  uint32_t vccq_1v8            : 1;     ///< Supports 1.8 VCCQ I/O Power Supply
+  uint32_t vpp                 : 1;     ///< Supports VPP High Voltage Power Supply Control
+  uint32_t wp                  : 1;     ///< Supports WPn (Write Protect) Control
+  uint32_t ce_lines            : 4;     ///< Number of CEn (Chip Enable) lines: ce_lines + 1
+  uint32_t ce_manual           : 1;     ///< Supports manual CEn (Chip Enable) Control
+  uint32_t rb_monitor          : 1;     ///< Supports R/Bn (Ready/Busy) Monitoring
+  uint32_t data_width_16       : 1;     ///< Supports 16-bit data
+  uint32_t ddr                 : 1;     ///< Supports NV-DDR  Data Interface (ONFI)
+  uint32_t ddr2                : 1;     ///< Supports NV-DDR2 Data Interface (ONFI)
+  uint32_t sdr_timing_mode     : 3;     ///< Fastest (highest) SDR     Timing Mode supported (ONFI)
+  uint32_t ddr_timing_mode     : 3;     ///< Fastest (highest) NV_DDR  Timing Mode supported (ONFI)
+  uint32_t ddr2_timing_mode    : 3;     ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI)
+  uint32_t driver_strength_18  : 1;     ///< Supports Driver Strength 2.0x = 18 Ohms
+  uint32_t driver_strength_25  : 1;     ///< Supports Driver Strength 1.4x = 25 Ohms
+  uint32_t driver_strength_50  : 1;     ///< Supports Driver Strength 0.7x = 50 Ohms
+  uint32_t reserved            : 2;     ///< Reserved (must be zero)
+} ARM_NAND_CAPABILITIES;
+
+
+/**
+\brief Access structure of the NAND Driver.
+*/
+typedef struct _ARM_DRIVER_NAND {
+  ARM_DRIVER_VERSION    (*GetVersion)     (void);                                                             ///< Pointer to \ref ARM_NAND_GetVersion : Get driver version.
+  ARM_NAND_CAPABILITIES (*GetCapabilities)(void);                                                             ///< Pointer to \ref ARM_NAND_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)     (ARM_NAND_SignalEvent_t cb_event);                                  ///< Pointer to \ref ARM_NAND_Initialize : Initialize NAND Interface.
+  int32_t               (*Uninitialize)   (void);                                                             ///< Pointer to \ref ARM_NAND_Uninitialize : De-initialize NAND Interface.
+  int32_t               (*PowerControl)   (ARM_POWER_STATE state);                                            ///< Pointer to \ref ARM_NAND_PowerControl : Control NAND Interface Power.
+  int32_t               (*DevicePower)    (uint32_t voltage);                                                 ///< Pointer to \ref ARM_NAND_DevicePower : Set device power supply voltage.
+  int32_t               (*WriteProtect)   (uint32_t dev_num, bool enable);                                    ///< Pointer to \ref ARM_NAND_WriteProtect : Control WPn (Write Protect).
+  int32_t               (*ChipEnable)     (uint32_t dev_num, bool enable);                                    ///< Pointer to \ref ARM_NAND_ChipEnable : Control CEn (Chip Enable).
+  int32_t               (*GetDeviceBusy)  (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state.
+  int32_t               (*SendCommand)    (uint32_t dev_num, uint8_t cmd);                                    ///< Pointer to \ref ARM_NAND_SendCommand : Send command to NAND device.
+  int32_t               (*SendAddress)    (uint32_t dev_num, uint8_t addr);                                   ///< Pointer to \ref ARM_NAND_SendAddress : Send address to NAND device.
+  int32_t               (*ReadData)       (uint32_t dev_num,       void *data, uint32_t cnt, uint32_t mode);  ///< Pointer to \ref ARM_NAND_ReadData : Read data from NAND device.
+  int32_t               (*WriteData)      (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode);  ///< Pointer to \ref ARM_NAND_WriteData : Write data to NAND device.
+  int32_t               (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd,
+                                           uint32_t addr_col, uint32_t addr_row,
+                                           void *data, uint32_t data_cnt,
+                                           uint8_t *status, uint32_t *count);                                 ///< Pointer to \ref ARM_NAND_ExecuteSequence : Execute sequence of operations.
+  int32_t               (*AbortSequence)  (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_AbortSequence : Abort sequence execution. 
+  int32_t               (*Control)        (uint32_t dev_num, uint32_t control, uint32_t arg);                 ///< Pointer to \ref ARM_NAND_Control : Control NAND Interface.
+  ARM_NAND_STATUS       (*GetStatus)      (uint32_t dev_num);                                                 ///< Pointer to \ref ARM_NAND_GetStatus : Get NAND status.
+  int32_t               (*InquireECC)     ( int32_t index, ARM_NAND_ECC_INFO *info);                          ///< Pointer to \ref ARM_NAND_InquireECC : Inquire about available ECC. 
+} const ARM_DRIVER_NAND;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_NAND_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_SAI.h

@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V1.1
+ *
+ * Project:      SAI (Serial Audio Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 1.1
+ *    ARM_SAI_STATUS made volatile
+ *  Version 1.0
+ *    Initial release
+ */
+
+#ifndef DRIVER_SAI_H_
+#define DRIVER_SAI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_SAI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,1)  /* API version */
+
+
+/****** SAI Control Codes *****/
+
+#define ARM_SAI_CONTROL_Msk             (0xFFU)
+#define ARM_SAI_CONFIGURE_TX            (0x01U)     ///< Configure Transmitter;  arg1 and arg2 provide additional configuration
+#define ARM_SAI_CONFIGURE_RX            (0x02U)     ///< Configure Receiver;     arg1 and arg2 provide additional configuration
+#define ARM_SAI_CONTROL_TX              (0x03U)     ///< Control Transmitter;    arg1.0: 0=disable (default), 1=enable; arg1.1: mute
+#define ARM_SAI_CONTROL_RX              (0x04U)     ///< Control Receiver;       arg1.0: 0=disable (default), 1=enable
+#define ARM_SAI_MASK_SLOTS_TX           (0x05U)     ///< Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default
+#define ARM_SAI_MASK_SLOTS_RX           (0x06U)     ///< Mask Receiver    slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default
+#define ARM_SAI_ABORT_SEND              (0x07U)     ///< Abort \ref ARM_SAI_Send
+#define ARM_SAI_ABORT_RECEIVE           (0x08U)     ///< Abort \ref ARM_SAI_Receive
+
+/*----- SAI Control Codes: Configuration Parameters: Mode -----*/
+#define ARM_SAI_MODE_Pos                 8
+#define ARM_SAI_MODE_Msk                (1U << ARM_SAI_MODE_Pos)
+#define ARM_SAI_MODE_MASTER             (1U << ARM_SAI_MODE_Pos)                ///< Master Mode
+#define ARM_SAI_MODE_SLAVE              (0U << ARM_SAI_MODE_Pos)                ///< Slave Mode (default)
+
+/*----- SAI Control Codes: Configuration Parameters: Synchronization -----*/
+#define ARM_SAI_SYNCHRONIZATION_Pos      9
+#define ARM_SAI_SYNCHRONIZATION_Msk     (1U << ARM_SAI_SYNCHRONIZATION_Pos)
+#define ARM_SAI_ASYNCHRONOUS            (0U << ARM_SAI_SYNCHRONIZATION_Pos)     ///< Asynchronous (default)
+#define ARM_SAI_SYNCHRONOUS             (1U << ARM_SAI_SYNCHRONIZATION_Pos)     ///< Synchronous
+
+/*----- SAI Control Codes: Configuration Parameters: Protocol -----*/
+#define ARM_SAI_PROTOCOL_Pos             10
+#define ARM_SAI_PROTOCOL_Msk            (7U << ARM_SAI_PROTOCOL_Pos)
+#define ARM_SAI_PROTOCOL_USER           (0U << ARM_SAI_PROTOCOL_Pos)            ///< User defined (default) 
+#define ARM_SAI_PROTOCOL_I2S            (1U << ARM_SAI_PROTOCOL_Pos)            ///< I2S
+#define ARM_SAI_PROTOCOL_MSB_JUSTIFIED  (2U << ARM_SAI_PROTOCOL_Pos)            ///< MSB (left) justified 
+#define ARM_SAI_PROTOCOL_LSB_JUSTIFIED  (3U << ARM_SAI_PROTOCOL_Pos)            ///< LSB (right) justified
+#define ARM_SAI_PROTOCOL_PCM_SHORT      (4U << ARM_SAI_PROTOCOL_Pos)            ///< PCM with short frame
+#define ARM_SAI_PROTOCOL_PCM_LONG       (5U << ARM_SAI_PROTOCOL_Pos)            ///< PCM with long frame
+#define ARM_SAI_PROTOCOL_AC97           (6U << ARM_SAI_PROTOCOL_Pos)            ///< AC'97
+
+/*----- SAI Control Codes: Configuration Parameters: Data Size -----*/
+#define ARM_SAI_DATA_SIZE_Pos            13
+#define ARM_SAI_DATA_SIZE_Msk                    (0x1FU  << ARM_SAI_DATA_SIZE_Pos)
+#define ARM_SAI_DATA_SIZE(n)            ((((n)-1)&0x1FU) << ARM_SAI_DATA_SIZE_Pos)  ///< Data size in bits (8..32)
+
+/*----- SAI Control Codes: Configuration Parameters: Bit Order -----*/
+#define ARM_SAI_BIT_ORDER_Pos            18
+#define ARM_SAI_BIT_ORDER_Msk           (1U << ARM_SAI_BIT_ORDER_Pos)
+#define ARM_SAI_MSB_FIRST               (0U << ARM_SAI_BIT_ORDER_Pos)           ///< Data is transferred with MSB first (default)
+#define ARM_SAI_LSB_FIRST               (1U << ARM_SAI_BIT_ORDER_Pos)           ///< Data is transferred with LSB first; User Protocol only (ignored otherwise)
+
+/*----- SAI Control Codes: Configuration Parameters: Mono Mode -----*/
+#define ARM_SAI_MONO_MODE               (1U << 19)                              ///< Mono Mode (only for I2S, MSB/LSB justified)
+
+/*----- SAI Control Codes:Configuration Parameters: Companding -----*/
+#define ARM_SAI_COMPANDING_Pos           20
+#define ARM_SAI_COMPANDING_Msk          (3U << ARM_SAI_COMPANDING_Pos)
+#define ARM_SAI_COMPANDING_NONE         (0U << ARM_SAI_COMPANDING_Pos)          ///< No compading (default)
+#define ARM_SAI_COMPANDING_A_LAW        (2U << ARM_SAI_COMPANDING_Pos)          ///< A-Law companding
+#define ARM_SAI_COMPANDING_U_LAW        (3U << ARM_SAI_COMPANDING_Pos)          ///< u-Law companding
+
+/*----- SAI Control Codes: Configuration Parameters: Clock Polarity -----*/
+#define ARM_SAI_CLOCK_POLARITY_Pos       23
+#define ARM_SAI_CLOCK_POLARITY_Msk      (1U << ARM_SAI_CLOCK_POLARITY_Pos)
+#define ARM_SAI_CLOCK_POLARITY_0        (0U << ARM_SAI_CLOCK_POLARITY_Pos)      ///< Drive on falling edge, Capture on rising  edge (default)
+#define ARM_SAI_CLOCK_POLARITY_1        (1U << ARM_SAI_CLOCK_POLARITY_Pos)      ///< Drive on rising  edge, Capture on falling edge
+
+/*----- SAI Control Codes: Configuration Parameters: Master Clock Pin -----*/
+#define ARM_SAI_MCLK_PIN_Pos             24
+#define ARM_SAI_MCLK_PIN_Msk            (3U << ARM_SAI_MCLK_PIN_Pos)
+#define ARM_SAI_MCLK_PIN_INACTIVE       (0U << ARM_SAI_MCLK_PIN_Pos)            ///< MCLK not used (default)
+#define ARM_SAI_MCLK_PIN_OUTPUT         (1U << ARM_SAI_MCLK_PIN_Pos)            ///< MCLK is output (Master only)
+#define ARM_SAI_MCLK_PIN_INPUT          (2U << ARM_SAI_MCLK_PIN_Pos)            ///< MCLK is input  (Master only)
+
+
+/****** SAI Configuration (arg1) *****/
+
+/*----- SAI Configuration (arg1): Frame Length -----*/
+#define ARM_SAI_FRAME_LENGTH_Pos          0
+#define ARM_SAI_FRAME_LENGTH_Msk                  (0x3FFU  << ARM_SAI_FRAME_LENGTH_Pos)
+#define ARM_SAI_FRAME_LENGTH(n)          ((((n)-1)&0x3FFU) << ARM_SAI_FRAME_LENGTH_Pos)     ///< Frame length in bits (8..1024); default depends on protocol and data
+
+/*----- SAI Configuration (arg1): Frame Sync Width -----*/
+#define ARM_SAI_FRAME_SYNC_WIDTH_Pos      10
+#define ARM_SAI_FRAME_SYNC_WIDTH_Msk              (0xFFU  << ARM_SAI_FRAME_SYNC_WIDTH_Pos)
+#define ARM_SAI_FRAME_SYNC_WIDTH(n)      ((((n)-1)&0xFFU) << ARM_SAI_FRAME_SYNC_WIDTH_Pos)  ///< Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Frame Sync Polarity -----*/
+#define ARM_SAI_FRAME_SYNC_POLARITY_Pos   18
+#define ARM_SAI_FRAME_SYNC_POLARITY_Msk  (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos)
+#define ARM_SAI_FRAME_SYNC_POLARITY_HIGH (0U << ARM_SAI_FRAME_SYNC_POLARITY_Pos)            ///< Frame Sync is active high (default); User Protocol only (ignored otherwise)
+#define ARM_SAI_FRAME_SYNC_POLARITY_LOW  (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos)            ///< Frame Sync is active low; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Frame Sync Early -----*/
+#define ARM_SAI_FRAME_SYNC_EARLY         (1U << 19)                                         ///< Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Slot Count -----*/
+#define ARM_SAI_SLOT_COUNT_Pos            20
+#define ARM_SAI_SLOT_COUNT_Msk                    (0x1FU  << ARM_SAI_SLOT_COUNT_Pos)
+#define ARM_SAI_SLOT_COUNT(n)            ((((n)-1)&0x1FU) << ARM_SAI_SLOT_COUNT_Pos)        ///< Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Slot Size -----*/
+#define ARM_SAI_SLOT_SIZE_Pos             25
+#define ARM_SAI_SLOT_SIZE_Msk            (3U << ARM_SAI_SLOT_SIZE_Pos)
+#define ARM_SAI_SLOT_SIZE_DEFAULT        (0U << ARM_SAI_SLOT_SIZE_Pos)                      ///< Slot size is equal to data size (default)
+#define ARM_SAI_SLOT_SIZE_16             (1U << ARM_SAI_SLOT_SIZE_Pos)                      ///< Slot size = 16 bits; User Protocol only (ignored otherwise)
+#define ARM_SAI_SLOT_SIZE_32             (3U << ARM_SAI_SLOT_SIZE_Pos)                      ///< Slot size = 32 bits; User Protocol only (ignored otherwise)
+
+/*----- SAI Configuration (arg1): Slot Offset -----*/
+#define ARM_SAI_SLOT_OFFSET_Pos           27
+#define ARM_SAI_SLOT_OFFSET_Msk               (0x1FU  << ARM_SAI_SLOT_OFFSET_Pos)
+#define ARM_SAI_SLOT_OFFSET(n)           (((n)&0x1FU) << ARM_SAI_SLOT_OFFSET_Pos)           ///< Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise)
+
+/****** SAI Configuration (arg2) *****/
+
+/*----- SAI Control Codes: Configuration Parameters: Audio Frequency (Master only) -----*/
+#define ARM_SAI_AUDIO_FREQ_Msk          (0x0FFFFFU)                                         ///< Audio frequency mask
+
+/*----- SAI Control Codes: Configuration Parameters: Master Clock Prescaler (Master only and MCLK Pin) -----*/
+#define ARM_SAI_MCLK_PRESCALER_Pos       20
+#define ARM_SAI_MCLK_PRESCALER_Msk      (0xFFFU << ARM_SAI_MCLK_PRESCALER_Pos)
+#define ARM_SAI_MCLK_PRESCALER(n)       ((((n)-1)&0xFFFU) << ARM_SAI_MCLK_PRESCALER_Pos)    ///< MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1)
+
+
+/****** SAI specific error codes *****/
+#define ARM_SAI_ERROR_SYNCHRONIZATION       (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Synchronization not supported
+#define ARM_SAI_ERROR_PROTOCOL              (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified Protocol not supported
+#define ARM_SAI_ERROR_DATA_SIZE             (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified Data size not supported
+#define ARM_SAI_ERROR_BIT_ORDER             (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Bit order not supported
+#define ARM_SAI_ERROR_MONO_MODE             (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified Mono mode not supported
+#define ARM_SAI_ERROR_COMPANDING            (ARM_DRIVER_ERROR_SPECIFIC - 6)     ///< Specified Companding not supported
+#define ARM_SAI_ERROR_CLOCK_POLARITY        (ARM_DRIVER_ERROR_SPECIFIC - 7)     ///< Specified Clock polarity not supported
+#define ARM_SAI_ERROR_AUDIO_FREQ            (ARM_DRIVER_ERROR_SPECIFIC - 8)     ///< Specified Audio frequency not supported
+#define ARM_SAI_ERROR_MCLK_PIN              (ARM_DRIVER_ERROR_SPECIFIC - 9)     ///< Specified MCLK Pin setting not supported
+#define ARM_SAI_ERROR_MCLK_PRESCALER        (ARM_DRIVER_ERROR_SPECIFIC - 10)    ///< Specified MCLK Prescaler not supported
+#define ARM_SAI_ERROR_FRAME_LENGHT          (ARM_DRIVER_ERROR_SPECIFIC - 11)    ///< Specified Frame length not supported
+#define ARM_SAI_ERROR_FRAME_SYNC_WIDTH      (ARM_DRIVER_ERROR_SPECIFIC - 12)    ///< Specified Frame Sync width not supported
+#define ARM_SAI_ERROR_FRAME_SYNC_POLARITY   (ARM_DRIVER_ERROR_SPECIFIC - 13)    ///< Specified Frame Sync polarity not supported
+#define ARM_SAI_ERROR_FRAME_SYNC_EARLY      (ARM_DRIVER_ERROR_SPECIFIC - 14)    ///< Specified Frame Sync early not supported
+#define ARM_SAI_ERROR_SLOT_COUNT            (ARM_DRIVER_ERROR_SPECIFIC - 15)    ///< Specified Slot count not supported
+#define ARM_SAI_ERROR_SLOT_SIZE             (ARM_DRIVER_ERROR_SPECIFIC - 16)    ///< Specified Slot size not supported
+#define ARM_SAI_ERROR_SLOT_OFFESET          (ARM_DRIVER_ERROR_SPECIFIC - 17)    ///< Specified Slot offset not supported
+
+
+/**
+\brief SAI Status
+*/
+typedef volatile struct _ARM_SAI_STATUS {
+  uint32_t tx_busy          : 1;        ///< Transmitter busy flag
+  uint32_t rx_busy          : 1;        ///< Receiver busy flag
+  uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)
+  uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)
+  uint32_t frame_error      : 1;        ///< Sync Frame error detected (cleared on start of next send/receive operation)
+  uint32_t reserved         : 27;
+} ARM_SAI_STATUS;
+
+
+/****** SAI Event *****/
+#define ARM_SAI_EVENT_SEND_COMPLETE     (1U << 0)   ///< Send completed
+#define ARM_SAI_EVENT_RECEIVE_COMPLETE  (1U << 1)   ///< Receive completed
+#define ARM_SAI_EVENT_TX_UNDERFLOW      (1U << 2)   ///< Transmit data not available
+#define ARM_SAI_EVENT_RX_OVERFLOW       (1U << 3)   ///< Receive data overflow
+#define ARM_SAI_EVENT_FRAME_ERROR       (1U << 4)   ///< Sync Frame error in Slave mode (optional)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_SAI_CAPABILITIES
+
+  \fn          int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)
+  \brief       Initialize SAI Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_SAI_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_Uninitialize (void)
+  \brief       De-initialize SAI Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control SAI Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_Send (const void *data, uint32_t num)
+  \brief       Start sending data to SAI transmitter.
+  \param[in]   data  Pointer to buffer with data to send to SAI transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SAI_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from SAI receiver.
+  \param[out]  data  Pointer to buffer for data to receive from SAI receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_SAI_GetTxCount (void)
+  \brief       Get transmitted data count.
+  \return      number of data items transmitted
+
+  \fn          uint32_t ARM_SAI_GetRxCount (void)
+  \brief       Get received data count.
+  \return      number of data items received
+
+  \fn          int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)
+  \brief       Control SAI Interface.
+  \param[in]   control  Operation
+  \param[in]   arg1     Argument 1 of operation (optional)
+  \param[in]   arg2     Argument 2 of operation (optional)
+  \return      common \ref execution_status and driver specific \ref sai_execution_status
+
+  \fn          ARM_SAI_STATUS ARM_SAI_GetStatus (void)
+  \brief       Get SAI status.
+  \return      SAI status \ref ARM_SAI_STATUS
+
+  \fn          void ARM_SAI_SignalEvent (uint32_t event)
+  \brief       Signal SAI Events.
+  \param[in]   event \ref SAI_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_SAI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_SAI_SignalEvent : Signal SAI Event.
+
+
+/**
+\brief SAI Driver Capabilities.
+*/
+typedef struct _ARM_SAI_CAPABILITIES {
+  uint32_t asynchronous          : 1;   ///< supports asynchronous Transmit/Receive
+  uint32_t synchronous           : 1;   ///< supports synchronous Transmit/Receive
+  uint32_t protocol_user         : 1;   ///< supports user defined Protocol
+  uint32_t protocol_i2s          : 1;   ///< supports I2S Protocol
+  uint32_t protocol_justified    : 1;   ///< supports MSB/LSB justified Protocol
+  uint32_t protocol_pcm          : 1;   ///< supports PCM short/long frame Protocol
+  uint32_t protocol_ac97         : 1;   ///< supports AC'97 Protocol
+  uint32_t mono_mode             : 1;   ///< supports Mono mode
+  uint32_t companding            : 1;   ///< supports Companding
+  uint32_t mclk_pin              : 1;   ///< supports MCLK (Master Clock) pin
+  uint32_t event_frame_error     : 1;   ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR
+  uint32_t reserved              : 21;  ///< Reserved (must be zero)
+} ARM_SAI_CAPABILITIES;
+
+
+/**
+\brief Access structure of the SAI Driver.
+*/
+typedef struct _ARM_DRIVER_SAI {
+  ARM_DRIVER_VERSION   (*GetVersion)      (void);                                            ///< Pointer to \ref ARM_SAI_GetVersion : Get driver version.
+  ARM_SAI_CAPABILITIES (*GetCapabilities) (void);                                            ///< Pointer to \ref ARM_SAI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)      (ARM_SAI_SignalEvent_t cb_event);                  ///< Pointer to \ref ARM_SAI_Initialize : Initialize SAI Interface.
+  int32_t              (*Uninitialize)    (void);                                            ///< Pointer to \ref ARM_SAI_Uninitialize : De-initialize SAI Interface.
+  int32_t              (*PowerControl)    (ARM_POWER_STATE state);                           ///< Pointer to \ref ARM_SAI_PowerControl : Control SAI Interface Power.
+  int32_t              (*Send)            (const void *data, uint32_t num);                  ///< Pointer to \ref ARM_SAI_Send : Start sending data to SAI Interface.
+  int32_t              (*Receive)         (      void *data, uint32_t num);                  ///< Pointer to \ref ARM_SAI_Receive : Start receiving data from SAI Interface.
+  uint32_t             (*GetTxCount)      (void);                                            ///< Pointer to \ref ARM_SAI_GetTxCount : Get transmitted data count.
+  uint32_t             (*GetRxCount)      (void);                                            ///< Pointer to \ref ARM_SAI_GetRxCount : Get received data count.
+  int32_t              (*Control)         (uint32_t control, uint32_t arg1, uint32_t arg2);  ///< Pointer to \ref ARM_SAI_Control : Control SAI Interface.
+  ARM_SAI_STATUS       (*GetStatus)       (void);                                            ///< Pointer to \ref ARM_SAI_GetStatus : Get SAI status.
+} const ARM_DRIVER_SAI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_SAI_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_SPI.h

@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.2
+ *
+ * Project:      SPI (Serial Peripheral Interface) Driver definitions
+ */
+
+/* History:
+ *  Version 2.2
+ *    ARM_SPI_STATUS made volatile
+ *  Version 2.1
+ *    Renamed status flag "tx_rx_busy" to "busy"
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *    Added:
+ *      Slave Mode
+ *      Half-duplex Modes
+ *      Configurable number of data bits
+ *      Support for TI Mode and Microwire
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added "send_done_event" to Capabilities
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_SPI_H_
+#define DRIVER_SPI_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */
+
+
+/****** SPI Control Codes *****/
+
+#define ARM_SPI_CONTROL_Pos              0
+#define ARM_SPI_CONTROL_Msk             (0xFFUL << ARM_SPI_CONTROL_Pos)
+
+/*----- SPI Control Codes: Mode -----*/
+#define ARM_SPI_MODE_INACTIVE           (0x00UL << ARM_SPI_CONTROL_Pos)     ///< SPI Inactive
+#define ARM_SPI_MODE_MASTER             (0x01UL << ARM_SPI_CONTROL_Pos)     ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
+#define ARM_SPI_MODE_SLAVE              (0x02UL << ARM_SPI_CONTROL_Pos)     ///< SPI Slave  (Output on MISO, Input on MOSI)
+#define ARM_SPI_MODE_MASTER_SIMPLEX     (0x03UL << ARM_SPI_CONTROL_Pos)     ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps
+#define ARM_SPI_MODE_SLAVE_SIMPLEX      (0x04UL << ARM_SPI_CONTROL_Pos)     ///< SPI Slave  (Output/Input on MISO)
+
+/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/
+#define ARM_SPI_FRAME_FORMAT_Pos         8
+#define ARM_SPI_FRAME_FORMAT_Msk        (7UL << ARM_SPI_FRAME_FORMAT_Pos)
+#define ARM_SPI_CPOL0_CPHA0             (0UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 0, Clock Phase 0 (default)
+#define ARM_SPI_CPOL0_CPHA1             (1UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 0, Clock Phase 1
+#define ARM_SPI_CPOL1_CPHA0             (2UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 1, Clock Phase 0
+#define ARM_SPI_CPOL1_CPHA1             (3UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 1, Clock Phase 1
+#define ARM_SPI_TI_SSI                  (4UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Texas Instruments Frame Format
+#define ARM_SPI_MICROWIRE               (5UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< National Microwire Frame Format
+
+/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_SPI_DATA_BITS_Pos            12
+#define ARM_SPI_DATA_BITS_Msk           (0x3FUL << ARM_SPI_DATA_BITS_Pos)
+#define ARM_SPI_DATA_BITS(n)            (((n) & 0x3F) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits
+
+/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/
+#define ARM_SPI_BIT_ORDER_Pos            18
+#define ARM_SPI_BIT_ORDER_Msk           (1UL << ARM_SPI_BIT_ORDER_Pos)
+#define ARM_SPI_MSB_LSB                 (0UL << ARM_SPI_BIT_ORDER_Pos)      ///< SPI Bit order from MSB to LSB (default)
+#define ARM_SPI_LSB_MSB                 (1UL << ARM_SPI_BIT_ORDER_Pos)      ///< SPI Bit order from LSB to MSB
+
+/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/
+#define ARM_SPI_SS_MASTER_MODE_Pos       19
+#define ARM_SPI_SS_MASTER_MODE_Msk      (3UL << ARM_SPI_SS_MASTER_MODE_Pos)
+#define ARM_SPI_SS_MASTER_UNUSED        (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default)
+#define ARM_SPI_SS_MASTER_SW            (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled
+#define ARM_SPI_SS_MASTER_HW_OUTPUT     (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output
+#define ARM_SPI_SS_MASTER_HW_INPUT      (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input
+#define ARM_SPI_SS_SLAVE_MODE_Pos        21
+#define ARM_SPI_SS_SLAVE_MODE_Msk       (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)
+#define ARM_SPI_SS_SLAVE_HW             (0UL << ARM_SPI_SS_SLAVE_MODE_Pos)  ///< SPI Slave Select when Slave: Hardware monitored (default)
+#define ARM_SPI_SS_SLAVE_SW             (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)  ///< SPI Slave Select when Slave: Software controlled
+
+
+/*----- SPI Control Codes: Miscellaneous Controls  -----*/
+#define ARM_SPI_SET_BUS_SPEED           (0x10UL << ARM_SPI_CONTROL_Pos)     ///< Set Bus Speed in bps; arg = value
+#define ARM_SPI_GET_BUS_SPEED           (0x11UL << ARM_SPI_CONTROL_Pos)     ///< Get Bus Speed in bps
+#define ARM_SPI_SET_DEFAULT_TX_VALUE    (0x12UL << ARM_SPI_CONTROL_Pos)     ///< Set default Transmit value; arg = value
+#define ARM_SPI_CONTROL_SS              (0x13UL << ARM_SPI_CONTROL_Pos)     ///< Control Slave Select; arg: 0=inactive, 1=active 
+#define ARM_SPI_ABORT_TRANSFER          (0x14UL << ARM_SPI_CONTROL_Pos)     ///< Abort current data transfer
+
+
+/****** SPI Slave Select Signal definitions *****/
+#define ARM_SPI_SS_INACTIVE              0                                  ///< SPI Slave Select Signal Inactive
+#define ARM_SPI_SS_ACTIVE                1                                  ///< SPI Slave Select Signal Active
+
+
+/****** SPI specific error codes *****/
+#define ARM_SPI_ERROR_MODE              (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported
+#define ARM_SPI_ERROR_FRAME_FORMAT      (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified Frame Format not supported
+#define ARM_SPI_ERROR_DATA_BITS         (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported
+#define ARM_SPI_ERROR_BIT_ORDER         (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Bit order not supported
+#define ARM_SPI_ERROR_SS_MODE           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified Slave Select Mode not supported
+
+
+/**
+\brief SPI Status
+*/
+typedef volatile struct _ARM_SPI_STATUS {
+  uint32_t busy       : 1;              ///< Transmitter/Receiver busy flag
+  uint32_t data_lost  : 1;              ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
+  uint32_t mode_fault : 1;              ///< Mode fault detected; optional (cleared on start of transfer operation)
+  uint32_t reserved   : 29;
+} ARM_SPI_STATUS;
+
+
+/****** SPI Event *****/
+#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0)  ///< Data Transfer completed
+#define ARM_SPI_EVENT_DATA_LOST         (1UL << 1)  ///< Data lost: Receive overflow / Transmit underflow
+#define ARM_SPI_EVENT_MODE_FAULT        (1UL << 2)  ///< Master Mode Fault (SS deactivated when Master)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_SPI_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_SPI_CAPABILITIES
+
+  \fn          int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event)
+  \brief       Initialize SPI Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_SPI_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Uninitialize (void)
+  \brief       De-initialize SPI Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control SPI Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Send (const void *data, uint32_t num)
+  \brief       Start sending data to SPI transmitter.
+  \param[in]   data  Pointer to buffer with data to send to SPI transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from SPI receiver.
+  \param[out]  data  Pointer to buffer for data to receive from SPI receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_SPI_Transfer (const void *data_out,
+                                               void *data_in,
+                                         uint32_t    num)
+  \brief       Start sending/receiving data to/from SPI transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to SPI transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from SPI receiver
+  \param[in]   num       Number of data items to transfer
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_SPI_GetDataCount (void)
+  \brief       Get transferred data count.
+  \return      number of data items transferred
+
+  \fn          int32_t ARM_SPI_Control (uint32_t control, uint32_t arg)
+  \brief       Control SPI Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      common \ref execution_status and driver specific \ref spi_execution_status
+
+  \fn          ARM_SPI_STATUS ARM_SPI_GetStatus (void)
+  \brief       Get SPI status.
+  \return      SPI status \ref ARM_SPI_STATUS
+
+  \fn          void ARM_SPI_SignalEvent (uint32_t event)
+  \brief       Signal SPI Events.
+  \param[in]   event \ref SPI_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_SPI_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_SPI_SignalEvent : Signal SPI Event.
+
+
+/**
+\brief SPI Driver Capabilities.
+*/
+typedef struct _ARM_SPI_CAPABILITIES {
+  uint32_t simplex          : 1;        ///< supports Simplex Mode (Master and Slave)
+  uint32_t ti_ssi           : 1;        ///< supports TI Synchronous Serial Interface
+  uint32_t microwire        : 1;        ///< supports Microwire Interface
+  uint32_t event_mode_fault : 1;        ///< Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT
+  uint32_t reserved         : 28;       ///< Reserved (must be zero)
+} ARM_SPI_CAPABILITIES;
+
+
+/**
+\brief Access structure of the SPI Driver.
+*/
+typedef struct _ARM_DRIVER_SPI {
+  ARM_DRIVER_VERSION   (*GetVersion)      (void);                             ///< Pointer to \ref ARM_SPI_GetVersion : Get driver version.
+  ARM_SPI_CAPABILITIES (*GetCapabilities) (void);                             ///< Pointer to \ref ARM_SPI_GetCapabilities : Get driver capabilities.
+  int32_t              (*Initialize)      (ARM_SPI_SignalEvent_t cb_event);   ///< Pointer to \ref ARM_SPI_Initialize : Initialize SPI Interface.
+  int32_t              (*Uninitialize)    (void);                             ///< Pointer to \ref ARM_SPI_Uninitialize : De-initialize SPI Interface.
+  int32_t              (*PowerControl)    (ARM_POWER_STATE state);            ///< Pointer to \ref ARM_SPI_PowerControl : Control SPI Interface Power.
+  int32_t              (*Send)            (const void *data, uint32_t num);   ///< Pointer to \ref ARM_SPI_Send : Start sending data to SPI Interface.
+  int32_t              (*Receive)         (      void *data, uint32_t num);   ///< Pointer to \ref ARM_SPI_Receive : Start receiving data from SPI Interface.
+  int32_t              (*Transfer)        (const void *data_out,
+                                                 void *data_in,
+                                           uint32_t    num);                  ///< Pointer to \ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI.
+  uint32_t             (*GetDataCount)    (void);                             ///< Pointer to \ref ARM_SPI_GetDataCount : Get transferred data count.
+  int32_t              (*Control)         (uint32_t control, uint32_t arg);   ///< Pointer to \ref ARM_SPI_Control : Control SPI Interface.
+  ARM_SPI_STATUS       (*GetStatus)       (void);                             ///< Pointer to \ref ARM_SPI_GetStatus : Get SPI status.
+} const ARM_DRIVER_SPI;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_SPI_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_USART.h

@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.3
+ *
+ * Project:      USART (Universal Synchronous Asynchronous Receiver Transmitter)
+ *               Driver definitions
+ */
+
+/* History:
+ *  Version 2.3
+ *    ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile
+ *  Version 2.2
+ *    Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions 
+ *  Version 2.1
+ *    Removed optional argument parameter from Signal Event
+ *  Version 2.0
+ *    New simplified driver:
+ *      complexity moved to upper layer (especially data handling)
+ *      more unified API for different communication interfaces
+ *      renamed driver UART -> USART (Asynchronous & Synchronous)
+ *    Added modes:
+ *      Synchronous
+ *      Single-wire
+ *      IrDA
+ *      Smart Card  
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added events:
+ *      ARM_UART_EVENT_TX_EMPTY,     ARM_UART_EVENT_RX_TIMEOUT
+ *      ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD
+ *    Added functions: SetTxThreshold, SetRxThreshold
+ *    Added "rx_timeout_event" to capabilities
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USART_H_
+#define DRIVER_USART_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_Common.h"
+
+#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */
+
+
+/****** USART Control Codes *****/
+
+#define ARM_USART_CONTROL_Pos                0
+#define ARM_USART_CONTROL_Msk               (0xFFUL << ARM_USART_CONTROL_Pos)
+
+/*----- USART Control Codes: Mode -----*/
+#define ARM_USART_MODE_ASYNCHRONOUS         (0x01UL << ARM_USART_CONTROL_Pos)   ///< UART (Asynchronous); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_MASTER   (0x02UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Master (generates clock signal); arg = Baudrate
+#define ARM_USART_MODE_SYNCHRONOUS_SLAVE    (0x03UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Slave (external clock signal)
+#define ARM_USART_MODE_SINGLE_WIRE          (0x04UL << ARM_USART_CONTROL_Pos)   ///< UART Single-wire (half-duplex); arg = Baudrate
+#define ARM_USART_MODE_IRDA                 (0x05UL << ARM_USART_CONTROL_Pos)   ///< UART IrDA; arg = Baudrate
+#define ARM_USART_MODE_SMART_CARD           (0x06UL << ARM_USART_CONTROL_Pos)   ///< UART Smart Card; arg = Baudrate
+
+/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
+#define ARM_USART_DATA_BITS_Pos              8
+#define ARM_USART_DATA_BITS_Msk             (7UL << ARM_USART_DATA_BITS_Pos)
+#define ARM_USART_DATA_BITS_5               (5UL << ARM_USART_DATA_BITS_Pos)    ///< 5 Data bits
+#define ARM_USART_DATA_BITS_6               (6UL << ARM_USART_DATA_BITS_Pos)    ///< 6 Data bit
+#define ARM_USART_DATA_BITS_7               (7UL << ARM_USART_DATA_BITS_Pos)    ///< 7 Data bits
+#define ARM_USART_DATA_BITS_8               (0UL << ARM_USART_DATA_BITS_Pos)    ///< 8 Data bits (default)
+#define ARM_USART_DATA_BITS_9               (1UL << ARM_USART_DATA_BITS_Pos)    ///< 9 Data bits
+
+/*----- USART Control Codes: Mode Parameters: Parity -----*/
+#define ARM_USART_PARITY_Pos                 12
+#define ARM_USART_PARITY_Msk                (3UL << ARM_USART_PARITY_Pos)
+#define ARM_USART_PARITY_NONE               (0UL << ARM_USART_PARITY_Pos)       ///< No Parity (default)
+#define ARM_USART_PARITY_EVEN               (1UL << ARM_USART_PARITY_Pos)       ///< Even Parity
+#define ARM_USART_PARITY_ODD                (2UL << ARM_USART_PARITY_Pos)       ///< Odd Parity
+
+/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
+#define ARM_USART_STOP_BITS_Pos              14
+#define ARM_USART_STOP_BITS_Msk             (3UL << ARM_USART_STOP_BITS_Pos)
+#define ARM_USART_STOP_BITS_1               (0UL << ARM_USART_STOP_BITS_Pos)    ///< 1 Stop bit (default)
+#define ARM_USART_STOP_BITS_2               (1UL << ARM_USART_STOP_BITS_Pos)    ///< 2 Stop bits
+#define ARM_USART_STOP_BITS_1_5             (2UL << ARM_USART_STOP_BITS_Pos)    ///< 1.5 Stop bits
+#define ARM_USART_STOP_BITS_0_5             (3UL << ARM_USART_STOP_BITS_Pos)    ///< 0.5 Stop bits
+
+/*----- USART Control Codes: Mode Parameters: Flow Control -----*/
+#define ARM_USART_FLOW_CONTROL_Pos           16
+#define ARM_USART_FLOW_CONTROL_Msk          (3UL << ARM_USART_FLOW_CONTROL_Pos)
+#define ARM_USART_FLOW_CONTROL_NONE         (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)
+#define ARM_USART_FLOW_CONTROL_RTS          (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control
+#define ARM_USART_FLOW_CONTROL_CTS          (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control
+#define ARM_USART_FLOW_CONTROL_RTS_CTS      (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control
+
+/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
+#define ARM_USART_CPOL_Pos                   18
+#define ARM_USART_CPOL_Msk                  (1UL << ARM_USART_CPOL_Pos)
+#define ARM_USART_CPOL0                     (0UL << ARM_USART_CPOL_Pos)         ///< CPOL = 0 (default)
+#define ARM_USART_CPOL1                     (1UL << ARM_USART_CPOL_Pos)         ///< CPOL = 1
+
+/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
+#define ARM_USART_CPHA_Pos                   19
+#define ARM_USART_CPHA_Msk                  (1UL << ARM_USART_CPHA_Pos)
+#define ARM_USART_CPHA0                     (0UL << ARM_USART_CPHA_Pos)         ///< CPHA = 0 (default)
+#define ARM_USART_CPHA1                     (1UL << ARM_USART_CPHA_Pos)         ///< CPHA = 1
+
+
+/*----- USART Control Codes: Miscellaneous Controls  -----*/
+#define ARM_USART_SET_DEFAULT_TX_VALUE      (0x10UL << ARM_USART_CONTROL_Pos)   ///< Set default Transmit value (Synchronous Receive only); arg = value
+#define ARM_USART_SET_IRDA_PULSE            (0x11UL << ARM_USART_CONTROL_Pos)   ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period  
+#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Guard Time; arg = number of bit periods
+#define ARM_USART_SET_SMART_CARD_CLOCK      (0x13UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated
+#define ARM_USART_CONTROL_SMART_CARD_NACK   (0x14UL << ARM_USART_CONTROL_Pos)   ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_TX                (0x15UL << ARM_USART_CONTROL_Pos)   ///< Transmitter; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_RX                (0x16UL << ARM_USART_CONTROL_Pos)   ///< Receiver; arg: 0=disabled, 1=enabled
+#define ARM_USART_CONTROL_BREAK             (0x17UL << ARM_USART_CONTROL_Pos)   ///< Continuous Break transmission; arg: 0=disabled, 1=enabled
+#define ARM_USART_ABORT_SEND                (0x18UL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Send
+#define ARM_USART_ABORT_RECEIVE             (0x19UL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Receive
+#define ARM_USART_ABORT_TRANSFER            (0x1AUL << ARM_USART_CONTROL_Pos)   ///< Abort \ref ARM_USART_Transfer
+
+
+
+/****** USART specific error codes *****/
+#define ARM_USART_ERROR_MODE                (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported
+#define ARM_USART_ERROR_BAUDRATE            (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified baudrate not supported
+#define ARM_USART_ERROR_DATA_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported
+#define ARM_USART_ERROR_PARITY              (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Parity not supported
+#define ARM_USART_ERROR_STOP_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified number of Stop bits not supported
+#define ARM_USART_ERROR_FLOW_CONTROL        (ARM_DRIVER_ERROR_SPECIFIC - 6)     ///< Specified Flow Control not supported
+#define ARM_USART_ERROR_CPOL                (ARM_DRIVER_ERROR_SPECIFIC - 7)     ///< Specified Clock Polarity not supported
+#define ARM_USART_ERROR_CPHA                (ARM_DRIVER_ERROR_SPECIFIC - 8)     ///< Specified Clock Phase not supported
+
+
+/**
+\brief USART Status
+*/
+typedef volatile struct _ARM_USART_STATUS {
+  uint32_t tx_busy          : 1;        ///< Transmitter busy flag
+  uint32_t rx_busy          : 1;        ///< Receiver busy flag
+  uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)
+  uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)
+  uint32_t rx_break         : 1;        ///< Break detected on receive (cleared on start of next receive operation)
+  uint32_t rx_framing_error : 1;        ///< Framing error detected on receive (cleared on start of next receive operation)
+  uint32_t rx_parity_error  : 1;        ///< Parity error detected on receive (cleared on start of next receive operation)
+  uint32_t reserved         : 25;
+} ARM_USART_STATUS;
+
+/**
+\brief USART Modem Control
+*/
+typedef enum _ARM_USART_MODEM_CONTROL {
+  ARM_USART_RTS_CLEAR,                  ///< Deactivate RTS
+  ARM_USART_RTS_SET,                    ///< Activate RTS
+  ARM_USART_DTR_CLEAR,                  ///< Deactivate DTR
+  ARM_USART_DTR_SET                     ///< Activate DTR
+} ARM_USART_MODEM_CONTROL;
+
+/**
+\brief USART Modem Status
+*/
+typedef volatile struct _ARM_USART_MODEM_STATUS {
+  uint32_t cts      : 1;                ///< CTS state: 1=Active, 0=Inactive
+  uint32_t dsr      : 1;                ///< DSR state: 1=Active, 0=Inactive
+  uint32_t dcd      : 1;                ///< DCD state: 1=Active, 0=Inactive
+  uint32_t ri       : 1;                ///< RI  state: 1=Active, 0=Inactive
+  uint32_t reserved : 28;
+} ARM_USART_MODEM_STATUS;
+
+
+/****** USART Event *****/
+#define ARM_USART_EVENT_SEND_COMPLETE       (1UL << 0)  ///< Send completed; however USART may still transmit data
+#define ARM_USART_EVENT_RECEIVE_COMPLETE    (1UL << 1)  ///< Receive completed
+#define ARM_USART_EVENT_TRANSFER_COMPLETE   (1UL << 2)  ///< Transfer completed
+#define ARM_USART_EVENT_TX_COMPLETE         (1UL << 3)  ///< Transmit completed (optional)
+#define ARM_USART_EVENT_TX_UNDERFLOW        (1UL << 4)  ///< Transmit data not available (Synchronous Slave)
+#define ARM_USART_EVENT_RX_OVERFLOW         (1UL << 5)  ///< Receive data overflow
+#define ARM_USART_EVENT_RX_TIMEOUT          (1UL << 6)  ///< Receive character timeout (optional)
+#define ARM_USART_EVENT_RX_BREAK            (1UL << 7)  ///< Break detected on receive
+#define ARM_USART_EVENT_RX_FRAMING_ERROR    (1UL << 8)  ///< Framing error detected on receive
+#define ARM_USART_EVENT_RX_PARITY_ERROR     (1UL << 9)  ///< Parity error detected on receive
+#define ARM_USART_EVENT_CTS                 (1UL << 10) ///< CTS state changed (optional)
+#define ARM_USART_EVENT_DSR                 (1UL << 11) ///< DSR state changed (optional)
+#define ARM_USART_EVENT_DCD                 (1UL << 12) ///< DCD state changed (optional)
+#define ARM_USART_EVENT_RI                  (1UL << 13) ///< RI  state changed (optional)
+
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USART_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+
+  \fn          ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)
+  \brief       Get driver capabilities
+  \return      \ref ARM_USART_CAPABILITIES
+
+  \fn          int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)
+  \brief       Initialize USART Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_USART_SignalEvent
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Uninitialize (void)
+  \brief       De-initialize USART Interface.
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USART Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Send (const void *data, uint32_t num)
+  \brief       Start sending data to USART transmitter.
+  \param[in]   data  Pointer to buffer with data to send to USART transmitter
+  \param[in]   num   Number of data items to send
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Receive (void *data, uint32_t num)
+  \brief       Start receiving data from USART receiver.
+  \param[out]  data  Pointer to buffer for data to receive from USART receiver
+  \param[in]   num   Number of data items to receive
+  \return      \ref execution_status
+
+  \fn          int32_t ARM_USART_Transfer (const void *data_out,
+                                                 void *data_in,
+                                           uint32_t    num)
+  \brief       Start sending/receiving data to/from USART transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to USART transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from USART receiver
+  \param[in]   num       Number of data items to transfer
+  \return      \ref execution_status
+
+  \fn          uint32_t ARM_USART_GetTxCount (void)
+  \brief       Get transmitted data count.
+  \return      number of data items transmitted
+
+  \fn          uint32_t ARM_USART_GetRxCount (void)
+  \brief       Get received data count.
+  \return      number of data items received
+
+  \fn          int32_t ARM_USART_Control (uint32_t control, uint32_t arg)
+  \brief       Control USART Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      common \ref execution_status and driver specific \ref usart_execution_status
+
+  \fn          ARM_USART_STATUS ARM_USART_GetStatus (void)
+  \brief       Get USART status.
+  \return      USART status \ref ARM_USART_STATUS
+
+  \fn          int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)
+  \brief       Set USART Modem Control line state.
+  \param[in]   control  \ref ARM_USART_MODEM_CONTROL
+  \return      \ref execution_status 
+
+  \fn          ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)
+  \brief       Get USART Modem Status lines state.
+  \return      modem status \ref ARM_USART_MODEM_STATUS
+
+  \fn          void ARM_USART_SignalEvent (uint32_t event)
+  \brief       Signal USART Events.
+  \param[in]   event  \ref USART_events notification mask
+  \return      none
+*/
+
+typedef void (*ARM_USART_SignalEvent_t) (uint32_t event);  ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event.
+
+
+/**
+\brief USART Device Driver Capabilities.
+*/
+typedef struct _ARM_USART_CAPABILITIES {
+  uint32_t asynchronous       : 1;      ///< supports UART (Asynchronous) mode 
+  uint32_t synchronous_master : 1;      ///< supports Synchronous Master mode
+  uint32_t synchronous_slave  : 1;      ///< supports Synchronous Slave mode
+  uint32_t single_wire        : 1;      ///< supports UART Single-wire mode
+  uint32_t irda               : 1;      ///< supports UART IrDA mode
+  uint32_t smart_card         : 1;      ///< supports UART Smart Card mode
+  uint32_t smart_card_clock   : 1;      ///< Smart Card Clock generator available
+  uint32_t flow_control_rts   : 1;      ///< RTS Flow Control available
+  uint32_t flow_control_cts   : 1;      ///< CTS Flow Control available
+  uint32_t event_tx_complete  : 1;      ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
+  uint32_t event_rx_timeout   : 1;      ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+  uint32_t rts                : 1;      ///< RTS Line: 0=not available, 1=available
+  uint32_t cts                : 1;      ///< CTS Line: 0=not available, 1=available
+  uint32_t dtr                : 1;      ///< DTR Line: 0=not available, 1=available
+  uint32_t dsr                : 1;      ///< DSR Line: 0=not available, 1=available
+  uint32_t dcd                : 1;      ///< DCD Line: 0=not available, 1=available
+  uint32_t ri                 : 1;      ///< RI Line: 0=not available, 1=available
+  uint32_t event_cts          : 1;      ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS
+  uint32_t event_dsr          : 1;      ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR
+  uint32_t event_dcd          : 1;      ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD
+  uint32_t event_ri           : 1;      ///< Signal RI change event: \ref ARM_USART_EVENT_RI
+  uint32_t reserved           : 11;     ///< Reserved (must be zero)
+} ARM_USART_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USART Driver.
+*/
+typedef struct _ARM_DRIVER_USART {
+  ARM_DRIVER_VERSION     (*GetVersion)      (void);                              ///< Pointer to \ref ARM_USART_GetVersion : Get driver version.
+  ARM_USART_CAPABILITIES (*GetCapabilities) (void);                              ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities.
+  int32_t                (*Initialize)      (ARM_USART_SignalEvent_t cb_event);  ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface.
+  int32_t                (*Uninitialize)    (void);                              ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface.
+  int32_t                (*PowerControl)    (ARM_POWER_STATE state);             ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power.
+  int32_t                (*Send)            (const void *data, uint32_t num);    ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter.
+  int32_t                (*Receive)         (      void *data, uint32_t num);    ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver.
+  int32_t                (*Transfer)        (const void *data_out,
+                                                   void *data_in,
+                                             uint32_t    num);                   ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART.
+  uint32_t               (*GetTxCount)      (void);                              ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count.
+  uint32_t               (*GetRxCount)      (void);                              ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count.
+  int32_t                (*Control)         (uint32_t control, uint32_t arg);    ///< Pointer to \ref ARM_USART_Control : Control USART Interface.
+  ARM_USART_STATUS       (*GetStatus)       (void);                              ///< Pointer to \ref ARM_USART_GetStatus : Get USART status.
+  int32_t                (*SetModemControl) (ARM_USART_MODEM_CONTROL control);   ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state.
+  ARM_USART_MODEM_STATUS (*GetModemStatus)  (void);                              ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.
+} const ARM_DRIVER_USART;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USART_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_USB.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.0
+ *
+ * Project:      USB Driver common definitions
+ */
+
+/* History:
+ *  Version 2.0
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.01
+ *    Added PID Types
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USB_H_
+#define DRIVER_USB_H_
+
+#include "Driver_Common.h"
+
+/* USB Role */
+#define ARM_USB_ROLE_NONE               (0)
+#define ARM_USB_ROLE_HOST               (1)
+#define ARM_USB_ROLE_DEVICE             (2)
+
+/* USB Pins */
+#define ARM_USB_PIN_DP                  (1 << 0) ///< USB D+ pin
+#define ARM_USB_PIN_DM                  (1 << 1) ///< USB D- pin
+#define ARM_USB_PIN_VBUS                (1 << 2) ///< USB VBUS pin
+#define ARM_USB_PIN_OC                  (1 << 3) ///< USB OverCurrent pin
+#define ARM_USB_PIN_ID                  (1 << 4) ///< USB ID pin
+
+/* USB Speed */
+#define ARM_USB_SPEED_LOW               (0)      ///< Low-speed USB
+#define ARM_USB_SPEED_FULL              (1)      ///< Full-speed USB
+#define ARM_USB_SPEED_HIGH              (2)      ///< High-speed USB
+
+/* USB PID Types */
+#define ARM_USB_PID_OUT                 (1)
+#define ARM_USB_PID_IN                  (9)
+#define ARM_USB_PID_SOF                 (5)
+#define ARM_USB_PID_SETUP               (13)
+#define ARM_USB_PID_DATA0               (3)
+#define ARM_USB_PID_DATA1               (11)
+#define ARM_USB_PID_DATA2               (7)
+#define ARM_USB_PID_MDATA               (15)
+#define ARM_USB_PID_ACK                 (2)
+#define ARM_USB_PID_NAK                 (10)
+#define ARM_USB_PID_STALL               (14)
+#define ARM_USB_PID_NYET                (6)
+#define ARM_USB_PID_PRE                 (12)
+#define ARM_USB_PID_ERR                 (12)
+#define ARM_USB_PID_SPLIT               (8)
+#define ARM_USB_PID_PING                (4)
+#define ARM_USB_PID_RESERVED            (0)
+
+/* USB Endpoint Address (bEndpointAddress) */
+#define ARM_USB_ENDPOINT_NUMBER_MASK    (0x0F)
+#define ARM_USB_ENDPOINT_DIRECTION_MASK (0x80)
+
+/* USB Endpoint Type */
+#define ARM_USB_ENDPOINT_CONTROL        (0)      ///< Control Endpoint
+#define ARM_USB_ENDPOINT_ISOCHRONOUS    (1)      ///< Isochronous Endpoint
+#define ARM_USB_ENDPOINT_BULK           (2)      ///< Bulk Endpoint
+#define ARM_USB_ENDPOINT_INTERRUPT      (3)      ///< Interrupt Endpoint
+
+/* USB Endpoint Maximum Packet Size (wMaxPacketSize) */
+#define ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK           (0x07FF)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK   (0x1800)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_1      (0x0000)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_2      (0x0800)
+#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_3      (0x1000)
+
+#endif /* DRIVER_USB_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_USBD.h

@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.2
+ *
+ * Project:      USB Device Driver definitions
+ */
+
+/* History:
+ *  Version 2.2
+ *    ARM_USBD_STATE made volatile
+ *  Version 2.1
+ *    Added ARM_USBD_ReadSetupPacket function
+ *  Version 2.0
+ *    Removed ARM_USBD_DeviceConfigure function
+ *    Removed ARM_USBD_SET_ADDRESS_STAGE parameter from ARM_USBD_DeviceSetAddress function
+ *    Removed ARM_USBD_EndpointReadStart function
+ *    Replaced ARM_USBD_EndpointRead and ARM_USBD_EndpointWrite functions with ARM_USBD_EndpointTransfer
+ *    Added ARM_USBD_EndpointTransferGetResult function
+ *    Renamed ARM_USBD_EndpointAbort function to ARM_USBD_EndpointTransferAbort
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *    Changed return values of some functions to int32_t
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USBD_H_
+#define DRIVER_USBD_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_USB.h"
+
+#define ARM_USBD_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */
+
+
+/**
+\brief USB Device State
+*/
+typedef volatile struct _ARM_USBD_STATE {
+  uint32_t vbus     : 1;                ///< USB Device VBUS flag
+  uint32_t speed    : 2;                ///< USB Device speed setting (ARM_USB_SPEED_xxx)
+  uint32_t active   : 1;                ///< USB Device active flag
+  uint32_t reserved : 28;
+} ARM_USBD_STATE;
+
+
+/****** USB Device Event *****/
+#define ARM_USBD_EVENT_VBUS_ON          (1UL << 0)      ///< USB Device VBUS On
+#define ARM_USBD_EVENT_VBUS_OFF         (1UL << 1)      ///< USB Device VBUS Off
+#define ARM_USBD_EVENT_RESET            (1UL << 2)      ///< USB Reset occurred
+#define ARM_USBD_EVENT_HIGH_SPEED       (1UL << 3)      ///< USB switch to High Speed occurred
+#define ARM_USBD_EVENT_SUSPEND          (1UL << 4)      ///< USB Suspend occurred
+#define ARM_USBD_EVENT_RESUME           (1UL << 5)      ///< USB Resume occurred
+
+/****** USB Endpoint Event *****/
+#define ARM_USBD_EVENT_SETUP            (1UL << 0)      ///< SETUP Packet
+#define ARM_USBD_EVENT_OUT              (1UL << 1)      ///< OUT Packet(s)
+#define ARM_USBD_EVENT_IN               (1UL << 2)      ///< IN Packet(s)
+
+
+#ifndef __DOXYGEN_MW__                  // exclude from middleware documentation
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBD_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBD_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,
+                                            ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
+  \brief       Initialize USB Device Interface.
+  \param[in]   cb_device_event    Pointer to \ref ARM_USBD_SignalDeviceEvent
+  \param[in]   cb_endpoint_event  Pointer to \ref ARM_USBD_SignalEndpointEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_Uninitialize (void)
+  \brief       De-initialize USB Device Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Device Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceConnect (void)
+  \brief       Connect USB Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceDisconnect (void)
+  \brief       Disconnect USB Device.
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_USBD_STATE ARM_USBD_DeviceGetState (void)
+  \brief       Get current USB Device State.
+  \return      Device State \ref ARM_USBD_STATE
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceRemoteWakeup (void)
+  \brief       Trigger USB Remote Wakeup.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_DeviceSetAddress (uint8_t dev_addr)
+  \brief       Set USB Device Address.
+  \param[in]   dev_addr  Device Address
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_ReadSetupPacket (uint8_t *setup)
+  \brief       Read setup packet received over Control Endpoint.
+  \param[out]  setup  Pointer to buffer for setup packet
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointConfigure (uint8_t  ep_addr,
+                                                   uint8_t  ep_type,
+                                                   uint16_t ep_max_packet_size)
+  \brief       Configure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type  Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointUnconfigure (uint8_t ep_addr)
+  \brief       Unconfigure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointStall (uint8_t ep_addr, bool stall)
+  \brief       Set/Clear Stall for USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   stall  Operation
+                - \b false Clear
+                - \b true Set
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)
+  \brief       Read data from or Write data to USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[out]  data Pointer to buffer for data to read or with data to write
+  \param[in]   num  Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint32_t ARM_USBD_EndpointTransferGetResult (uint8_t ep_addr)
+  \brief       Get result of USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      number of successfully transferred data bytes
+*/
+/**
+  \fn          int32_t ARM_USBD_EndpointTransferAbort (uint8_t ep_addr)
+  \brief       Abort current USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint16_t ARM_USBD_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+
+/**
+  \fn          void ARM_USBD_SignalDeviceEvent (uint32_t event)
+  \brief       Signal USB Device Event.
+  \param[in]   event \ref USBD_dev_events
+  \return      none
+*/
+/**
+  \fn          void ARM_USBD_SignalEndpointEvent (uint8_t ep_addr, uint32_t event)
+  \brief       Signal USB Endpoint Event.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   event \ref USBD_ep_events
+  \return      none
+*/
+
+typedef void (*ARM_USBD_SignalDeviceEvent_t)   (uint32_t event);                    ///< Pointer to \ref ARM_USBD_SignalDeviceEvent : Signal USB Device Event.
+typedef void (*ARM_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, uint32_t event);   ///< Pointer to \ref ARM_USBD_SignalEndpointEvent : Signal USB Endpoint Event.
+
+
+/**
+\brief USB Device Driver Capabilities.
+*/
+typedef struct _ARM_USBD_CAPABILITIES {
+  uint32_t vbus_detection  : 1;         ///< VBUS detection
+  uint32_t event_vbus_on   : 1;         ///< Signal VBUS On event
+  uint32_t event_vbus_off  : 1;         ///< Signal VBUS Off event
+  uint32_t reserved        : 29;        ///< Reserved (must be zero)
+} ARM_USBD_CAPABILITIES;
+
+
+/**
+\brief Access structure of the USB Device Driver.
+*/
+typedef struct _ARM_DRIVER_USBD {
+  ARM_DRIVER_VERSION    (*GetVersion)                (void);                                              ///< Pointer to \ref ARM_USBD_GetVersion : Get driver version.
+  ARM_USBD_CAPABILITIES (*GetCapabilities)           (void);                                              ///< Pointer to \ref ARM_USBD_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)                (ARM_USBD_SignalDeviceEvent_t   cb_device_event,                     
+                                                      ARM_USBD_SignalEndpointEvent_t cb_endpoint_event);  ///< Pointer to \ref ARM_USBD_Initialize : Initialize USB Device Interface. 
+  int32_t               (*Uninitialize)              (void);                                              ///< Pointer to \ref ARM_USBD_Uninitialize : De-initialize USB Device Interface.
+  int32_t               (*PowerControl)              (ARM_POWER_STATE state);                             ///< Pointer to \ref ARM_USBD_PowerControl : Control USB Device Interface Power.
+  int32_t               (*DeviceConnect)             (void);                                              ///< Pointer to \ref ARM_USBD_DeviceConnect : Connect USB Device.
+  int32_t               (*DeviceDisconnect)          (void);                                              ///< Pointer to \ref ARM_USBD_DeviceDisconnect : Disconnect USB Device.
+  ARM_USBD_STATE        (*DeviceGetState)            (void);                                              ///< Pointer to \ref ARM_USBD_DeviceGetState : Get current USB Device State.
+  int32_t               (*DeviceRemoteWakeup)        (void);                                              ///< Pointer to \ref ARM_USBD_DeviceRemoteWakeup : Trigger USB Remote Wakeup.
+  int32_t               (*DeviceSetAddress)          (uint8_t dev_addr);                                  ///< Pointer to \ref ARM_USBD_DeviceSetAddress : Set USB Device Address.
+  int32_t               (*ReadSetupPacket)           (uint8_t *setup);                                    ///< Pointer to \ref ARM_USBD_ReadSetupPacket : Read setup packet received over Control Endpoint.
+  int32_t               (*EndpointConfigure)         (uint8_t ep_addr,
+                                                      uint8_t ep_type,
+                                                      uint16_t ep_max_packet_size);                       ///< Pointer to \ref ARM_USBD_EndpointConfigure : Configure USB Endpoint.
+  int32_t               (*EndpointUnconfigure)       (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointUnconfigure : Unconfigure USB Endpoint.
+  int32_t               (*EndpointStall)             (uint8_t ep_addr, bool stall);                       ///< Pointer to \ref ARM_USBD_EndpointStall : Set/Clear Stall for USB Endpoint.
+  int32_t               (*EndpointTransfer)          (uint8_t ep_addr, uint8_t *data, uint32_t num);      ///< Pointer to \ref ARM_USBD_EndpointTransfer : Read data from or Write data to USB Endpoint.
+  uint32_t              (*EndpointTransferGetResult) (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointTransferGetResult : Get result of USB Endpoint transfer.
+  int32_t               (*EndpointTransferAbort)     (uint8_t ep_addr);                                   ///< Pointer to \ref ARM_USBD_EndpointTransferAbort : Abort current USB Endpoint transfer.
+  uint16_t              (*GetFrameNumber)            (void);                                              ///< Pointer to \ref ARM_USBD_GetFrameNumber : Get current USB Frame Number.
+} const ARM_DRIVER_USBD;
+
+#endif /* __DOXYGEN_MW__ */
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USBD_H_ */

bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Driver/Include/Driver_USBH.h

@@ -0,0 +1,417 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+  *
+ * $Date:        2. Feb 2017
+ * $Revision:    V2.2
+ *
+ * Project:      USB Host Driver definitions
+*/
+
+/* History:
+ *  Version 2.2
+ *    ARM_USBH_PORT_STATE made volatile
+ *  Version 2.1
+ *    Renamed structure ARM_USBH_EP_HANDLE to ARM_USBH_PIPE_HANDLE
+ *    Renamed functions ARM_USBH_Endpoint... to ARM_USBH_Pipe...
+ *    Renamed function ARM_USBH_SignalEndpointEvent to ARM_USBH_SignalPipeEvent
+ *  Version 2.0
+ *    Replaced function ARM_USBH_PortPowerOnOff with ARM_USBH_PortVbusOnOff
+ *    Changed function ARM_USBH_EndpointCreate parameters
+ *    Replaced function ARM_USBH_EndpointConfigure with ARM_USBH_EndpointModify
+ *    Replaced function ARM_USBH_EndpointClearHalt with ARM_USBH_EndpointReset
+ *    Replaced function ARM_USBH_URB_Submit with ARM_USBH_EndpointTransfer
+ *    Replaced function ARM_USBH_URB_Abort with ARM_USBH_EndpointTransferAbort
+ *    Added function ARM_USBH_EndpointTransferGetResult
+ *    Added function ARM_USBH_GetFrameNumber
+ *    Changed prefix ARM_DRV -> ARM_DRIVER
+ *  Version 1.20
+ *    Added API for OHCI/EHCI Host Controller Interface (HCI)
+ *  Version 1.10
+ *    Namespace prefix ARM_ added
+ *  Version 1.00
+ *    Initial release
+ */
+
+#ifndef DRIVER_USBH_H_
+#define DRIVER_USBH_H_
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+#include "Driver_USB.h"
+
+#define ARM_USBH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */
+
+
+/**
+\brief USB Host Port State
+*/
+typedef volatile struct _ARM_USBH_PORT_STATE {
+  uint32_t connected   : 1;             ///< USB Host Port connected flag
+  uint32_t overcurrent : 1;             ///< USB Host Port overcurrent flag
+  uint32_t speed       : 2;             ///< USB Host Port speed setting (ARM_USB_SPEED_xxx)
+  uint32_t reserved    : 28;
+} ARM_USBH_PORT_STATE;
+
+/**
+\brief USB Host Pipe Handle
+*/
+typedef uint32_t ARM_USBH_PIPE_HANDLE;
+#define ARM_USBH_EP_HANDLE ARM_USBH_PIPE_HANDLE  /* Legacy name */
+
+
+/****** USB Host Packet Information *****/
+#define ARM_USBH_PACKET_TOKEN_Pos         0
+#define ARM_USBH_PACKET_TOKEN_Msk        (0x0FUL << ARM_USBH_PACKET_TOKEN_Pos)
+#define ARM_USBH_PACKET_SETUP            (0x01UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< SETUP Packet
+#define ARM_USBH_PACKET_OUT              (0x02UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< OUT Packet
+#define ARM_USBH_PACKET_IN               (0x03UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< IN Packet
+#define ARM_USBH_PACKET_PING             (0x04UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< PING Packet
+
+#define ARM_USBH_PACKET_DATA_Pos          4
+#define ARM_USBH_PACKET_DATA_Msk         (0x0FUL << ARM_USBH_PACKET_DATA_Pos)
+#define ARM_USBH_PACKET_DATA0            (0x01UL << ARM_USBH_PACKET_DATA_Pos)   ///< DATA0 PID
+#define ARM_USBH_PACKET_DATA1            (0x02UL << ARM_USBH_PACKET_DATA_Pos)   ///< DATA1 PID
+
+#define ARM_USBH_PACKET_SPLIT_Pos         8
+#define ARM_USBH_PACKET_SPLIT_Msk        (0x0FUL << ARM_USBH_PACKET_SPLIT_Pos)
+#define ARM_USBH_PACKET_SSPLIT           (0x08UL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet
+#define ARM_USBH_PACKET_SSPLIT_S         (0x09UL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data Start
+#define ARM_USBH_PACKET_SSPLIT_E         (0x0AUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data End
+#define ARM_USBH_PACKET_SSPLIT_S_E       (0x0BUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data All
+#define ARM_USBH_PACKET_CSPLIT           (0x0CUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< CSPLIT Packet
+
+#define ARM_USBH_PACKET_PRE              (1UL << 12)                            ///< PRE Token
+
+
+/****** USB Host Port Event *****/
+#define ARM_USBH_EVENT_CONNECT           (1UL << 0)     ///< USB Device Connected to Port
+#define ARM_USBH_EVENT_DISCONNECT        (1UL << 1)     ///< USB Device Disconnected from Port
+#define ARM_USBH_EVENT_OVERCURRENT       (1UL << 2)     ///< USB Device caused Overcurrent
+#define ARM_USBH_EVENT_RESET             (1UL << 3)     ///< USB Reset completed
+#define ARM_USBH_EVENT_SUSPEND           (1UL << 4)     ///< USB Suspend occurred
+#define ARM_USBH_EVENT_RESUME            (1UL << 5)     ///< USB Resume occurred
+#define ARM_USBH_EVENT_REMOTE_WAKEUP     (1UL << 6)     ///< USB Device activated Remote Wakeup
+
+/****** USB Host Pipe Event *****/
+#define ARM_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0)     ///< Transfer completed
+#define ARM_USBH_EVENT_HANDSHAKE_NAK     (1UL << 1)     ///< NAK Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_NYET    (1UL << 2)     ///< NYET Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_MDATA   (1UL << 3)     ///< MDATA Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_STALL   (1UL << 4)     ///< STALL Handshake received
+#define ARM_USBH_EVENT_HANDSHAKE_ERR     (1UL << 5)     ///< ERR Handshake received
+#define ARM_USBH_EVENT_BUS_ERROR         (1UL << 6)     ///< Bus Error detected
+
+
+#ifndef __DOXYGEN_MW__                  // exclude from middleware documentation
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBH_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBH_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBH_Initialize (ARM_USBH_SignalPortEvent_t cb_port_event,
+                                            ARM_USBH_SignalPipeEvent_t cb_pipe_event)
+  \brief       Initialize USB Host Interface.
+  \param[in]   cb_port_event  Pointer to \ref ARM_USBH_SignalPortEvent
+  \param[in]   cb_pipe_event  Pointer to \ref ARM_USBH_SignalPipeEvent
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_Uninitialize (void)
+  \brief       De-initialize USB Host Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Host Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortVbusOnOff (uint8_t port, bool vbus)
+  \brief       Root HUB Port VBUS on/off.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   vbus
+                - \b false VBUS off
+                - \b true  VBUS on
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortReset (uint8_t port)
+  \brief       Do Root HUB Port Reset.
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortSuspend (uint8_t port)
+  \brief       Suspend Root HUB Port (stop generating SOFs).
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PortResume (uint8_t port)
+  \brief       Resume Root HUB Port (start generating SOFs).
+  \param[in]   port  Root HUB Port Number
+  \return      \ref execution_status
+*/
+/**
+  \fn          ARM_USBH_PORT_STATE ARM_USBH_PortGetState (uint8_t port)
+  \brief       Get current Root HUB Port State.
+  \param[in]   port  Root HUB Port Number
+  \return      Port State \ref ARM_USBH_PORT_STATE
+*/
+/**
+  \fn          ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate (uint8_t  dev_addr,
+                                                         uint8_t  dev_speed,
+                                                         uint8_t  hub_addr,
+                                                         uint8_t  hub_port,
+                                                         uint8_t  ep_addr,
+                                                         uint8_t  ep_type,
+                                                         uint16_t ep_max_packet_size,
+                                                         uint8_t  ep_interval)
+  \brief       Create Pipe in System.
+  \param[in]   dev_addr   Device Address
+  \param[in]   dev_speed  Device Speed
+  \param[in]   hub_addr   Hub Address
+  \param[in]   hub_port   Hub Port
+  \param[in]   ep_addr    Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type    Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \param[in]   ep_interval        Endpoint Polling Interval
+  \return      Pipe Handle \ref ARM_USBH_PIPE_HANDLE
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeModify (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                            uint8_t              dev_addr,
+                                            uint8_t              dev_speed,
+                                            uint8_t              hub_addr,
+                                            uint8_t              hub_port,
+                                            uint16_t             ep_max_packet_size)
+  \brief       Modify Pipe in System.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   dev_addr   Device Address
+  \param[in]   dev_speed  Device Speed
+  \param[in]   hub_addr   Hub Address
+  \param[in]   hub_port   Hub Port
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeDelete (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Delete Pipe from System.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeReset (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Reset Pipe.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeTransfer (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                              uint32_t             packet,
+                                              uint8_t             *data,
+                                              uint32_t             num)
+  \brief       Transfer packets through USB Pipe.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   packet     Packet information
+  \param[in]   data       Pointer to buffer with data to send or for data to receive
+  \param[in]   num        Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint32_t ARM_USBH_PipeTransferGetResult (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Get result of USB Pipe transfer.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      number of successfully transferred data bytes
+*/
+/**
+  \fn          int32_t ARM_USBH_PipeTransferAbort (ARM_USBH_PIPE_HANDLE pipe_hndl)
+  \brief       Abort current USB Pipe transfer.
+  \param[in]   pipe_hndl  Pipe Handle
+  \return      \ref execution_status
+*/
+/**
+  \fn          uint16_t ARM_USBH_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+
+/**
+  \fn          void ARM_USBH_SignalPortEvent (uint8_t port, uint32_t event)
+  \brief       Signal Root HUB Port Event.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   event \ref USBH_port_events
+  \return      none
+*/
+/**
+  \fn          void ARM_USBH_SignalPipeEvent (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event)
+  \brief       Signal Pipe Event.
+  \param[in]   pipe_hndl  Pipe Handle
+  \param[in]   event  \ref USBH_pipe_events
+  \return      none
+*/
+
+typedef void (*ARM_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event);                    ///< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event.
+typedef void (*ARM_USBH_SignalPipeEvent_t) (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event);  ///< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event.
+#define ARM_USBH_SignalEndpointEvent_t ARM_USBH_SignalPipeEvent_t  /* Legacy name */
+
+
+/**
+\brief USB Host Driver Capabilities.
+*/
+typedef struct _ARM_USBH_CAPABILITIES {
+  uint32_t port_mask          : 15;     ///< Root HUB available Ports Mask
+  uint32_t auto_split         :  1;     ///< Automatic SPLIT packet handling
+  uint32_t event_connect      :  1;     ///< Signal Connect event
+  uint32_t event_disconnect   :  1;     ///< Signal Disconnect event
+  uint32_t event_overcurrent  :  1;     ///< Signal Overcurrent event
+  uint32_t reserved           : 13;     ///< Reserved (must be zero)
+} ARM_USBH_CAPABILITIES;
+
+
+/**
+\brief Access structure of USB Host Driver.
+*/
+typedef struct _ARM_DRIVER_USBH {
+  ARM_DRIVER_VERSION    (*GetVersion)            (void);                                     ///< Pointer to \ref ARM_USBH_GetVersion : Get driver version.
+  ARM_USBH_CAPABILITIES (*GetCapabilities)       (void);                                     ///< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities.
+  int32_t               (*Initialize)            (ARM_USBH_SignalPortEvent_t cb_port_event,            
+                                                  ARM_USBH_SignalPipeEvent_t cb_pipe_event); ///< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface.
+  int32_t               (*Uninitialize)          (void);                                     ///< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface.
+  int32_t               (*PowerControl)          (ARM_POWER_STATE state);                    ///< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power.
+  int32_t               (*PortVbusOnOff)         (uint8_t port, bool vbus);                  ///< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off.
+  int32_t               (*PortReset)             (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset.
+  int32_t               (*PortSuspend)           (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs).
+  int32_t               (*PortResume)            (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs).
+  ARM_USBH_PORT_STATE   (*PortGetState)          (uint8_t port);                             ///< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State.
+  ARM_USBH_PIPE_HANDLE  (*PipeCreate)            (uint8_t dev_addr,
+                                                  uint8_t dev_speed,
+                                                  uint8_t hub_addr,
+                                                  uint8_t hub_port,
+                                                  uint8_t ep_addr,
+                                                  uint8_t ep_type,
+                                                  uint16_t ep_max_packet_size,
+                                                  uint8_t ep_interval);                      ///< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System.
+  int32_t               (*PipeModify)            (ARM_USBH_PIPE_HANDLE pipe_hndl,
+                                                  uint8_t dev_addr,
+                                                  uint8_t dev_speed,
+                                                  uint8_t hub_addr,
+                                                  uint8_t hub_port,
+                                                  uint16_t ep_max_packet_size);              ///< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System.
+  int32_t               (*PipeDelete)            (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System.
+  int32_t               (*PipeReset)             (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe.
+  int32_t               (*PipeTransfer)          (ARM_USBH_PIPE_HANDLE pipe_hndl, 
+                                                  uint32_t packet,
+                                                  uint8_t *data,
+                                                  uint32_t num);                             ///< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe.
+  uint32_t              (*PipeTransferGetResult) (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer.
+  int32_t               (*PipeTransferAbort)     (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer.
+  uint16_t              (*GetFrameNumber)        (void);                                     ///< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number.                    
+} const ARM_DRIVER_USBH;
+
+
+// HCI (OHCI/EHCI)
+
+// Function documentation
+/**
+  \fn          ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion (void)
+  \brief       Get USB Host HCI (OHCI/EHCI) driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+/**
+  \fn          ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBH_HCI_CAPABILITIES
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt)
+  \brief       Initialize USB Host HCI (OHCI/EHCI) Interface.
+  \param[in]   cb_interrupt Pointer to Interrupt Handler Routine
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_Uninitialize (void)
+  \brief       De-initialize USB Host HCI (OHCI/EHCI) Interface.
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Host HCI (OHCI/EHCI) Interface Power.
+  \param[in]   state Power state
+  \return      \ref execution_status
+*/
+/**
+  \fn          int32_t ARM_USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus)
+  \brief       USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   vbus
+                - \b false VBUS off
+                - \b true  VBUS on
+  \return      \ref execution_status
+*/
+
+/**
+  \fn          void ARM_USBH_HCI_Interrupt (void)
+  \brief       USB Host HCI Interrupt Handler.
+  \return      none
+*/
+
+typedef void (*ARM_USBH_HCI_Interrupt_t) (void);  ///< Pointer to Interrupt Handler Routine.
+
+
+/**
+\brief USB Host HCI (OHCI/EHCI) Driver Capabilities.
+*/
+typedef struct _ARM_USBH_HCI_CAPABILITIES {
+  uint32_t port_mask : 15;              ///< Root HUB available Ports Mask
+  uint32_t reserved  : 17;              ///< Reserved (must be zero)
+} ARM_USBH_HCI_CAPABILITIES;
+
+
+/**
+  \brief Access structure of USB Host HCI (OHCI/EHCI) Driver.
+*/
+typedef struct _ARM_DRIVER_USBH_HCI {
+  ARM_DRIVER_VERSION        (*GetVersion)      (void);                                  ///< Pointer to \ref ARM_USBH_HCI_GetVersion : Get USB Host HCI (OHCI/EHCI) driver version.
+  ARM_USBH_HCI_CAPABILITIES (*GetCapabilities) (void);                                  ///< Pointer to \ref ARM_USBH_HCI_GetCapabilities : Get driver capabilities.
+  int32_t                   (*Initialize)      (ARM_USBH_HCI_Interrupt_t cb_interrupt); ///< Pointer to \ref ARM_USBH_HCI_Initialize : Initialize USB Host HCI (OHCI/EHCI) Interface.
+  int32_t                   (*Uninitialize)    (void);                                  ///< Pointer to \ref ARM_USBH_HCI_Uninitialize : De-initialize USB Host HCI (OHCI/EHCI) Interface.
+  int32_t                   (*PowerControl)    (ARM_POWER_STATE state);                 ///< Pointer to \ref ARM_USBH_HCI_PowerControl : Control USB Host HCI (OHCI/EHCI) Interface Power.
+  int32_t                   (*PortVbusOnOff)   (uint8_t port, bool vbus);               ///< Pointer to \ref ARM_USBH_HCI_PortVbusOnOff : USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
+} const ARM_DRIVER_USBH_HCI;
+
+#endif /* __DOXYGEN_MW__ */
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* DRIVER_USBH_H_ */

bsp/imxrt/Libraries/imxrt1021/CMSIS/Include/arm_math.h → bsp/imxrt/Libraries/MIMXRT1050/CMSIS/Include/arm_math.h

@@ -321,6 +321,9 @@
 #elif defined (ARM_MATH_CM4)
   #include "core_cm4.h"
   #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM33)
+  #include "core_cm33.h"
+  #define ARM_MATH_DSP
 #elif defined (ARM_MATH_CM3)
   #include "core_cm3.h"
 #elif defined (ARM_MATH_CM0)

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/MIMXRT1052.xml → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/MIMXRT1052.xml

@@ -5,38 +5,10 @@
   <version>1.0</version>
   <description>MIMXRT1052DVL6B</description>
   <licenseText>
-The Clear BSD License
 Copyright 2016-2018 NXP
 All rights reserved.
 
-Redistribution and use in source and binary forms, with or without
-modification, are permitted (subject to the limitations in the
-disclaimer below) provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright
-  notice, this list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright
-  notice, this list of conditions and the following disclaimer in the
-  documentation and/or other materials provided with the distribution.
-
-* Neither the name of the copyright holder nor the names of its
-  contributors may be used to endorse or promote products derived from
-  this software without specific prior written permission.
-
-NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-HOLDERS AND CONTRIBUTORS &quot;AS IS&quot; AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+SPDX-License-Identifier: BSD-3-Clause
   </licenseText>
   <cpu>
     <name>CM7</name>
@@ -3596,17 +3568,17 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
                 </enumeratedValue>
                 <enumeratedValue>
                   <name>SAI1_MCLK1_SEL_3</name>
-                  <description>iomux.sai1_ipg_clk_sai_mclk[2]</description>
+                  <description>iomux.sai1_ipg_clk_sai_mclk</description>
                   <value>0x3</value>
                 </enumeratedValue>
                 <enumeratedValue>
                   <name>SAI1_MCLK1_SEL_4</name>
-                  <description>iomux.sai2_ipg_clk_sai_mclk[2]</description>
+                  <description>iomux.sai2_ipg_clk_sai_mclk</description>
                   <value>0x4</value>
                 </enumeratedValue>
                 <enumeratedValue>
                   <name>SAI1_MCLK1_SEL_5</name>
-                  <description>iomux.sai3_ipg_clk_sai_mclk[2]</description>
+                  <description>iomux.sai3_ipg_clk_sai_mclk</description>
                   <value>0x5</value>
                 </enumeratedValue>
               </enumeratedValues>
@@ -3635,17 +3607,17 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
                 </enumeratedValue>
                 <enumeratedValue>
                   <name>SAI1_MCLK2_SEL_3</name>
-                  <description>iomux.sai1_ipg_clk_sai_mclk[2]</description>
+                  <description>iomux.sai1_ipg_clk_sai_mclk</description>
                   <value>0x3</value>
                 </enumeratedValue>
                 <enumeratedValue>
                   <name>SAI1_MCLK2_SEL_4</name>
-                  <description>iomux.sai2_ipg_clk_sai_mclk[2]</description>
+                  <description>iomux.sai2_ipg_clk_sai_mclk</description>
                   <value>0x4</value>
                 </enumeratedValue>
                 <enumeratedValue>
                   <name>SAI1_MCLK2_SEL_5</name>
-                  <description>iomux.sai3_ipg_clk_sai_mclk[2]</description>
+                  <description>iomux.sai3_ipg_clk_sai_mclk</description>
                   <value>0x5</value>
                 </enumeratedValue>
               </enumeratedValues>
@@ -7287,7 +7259,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
           <addressOffset>0x38</addressOffset>
           <size>32</size>
           <access>read-write</access>
-          <resetValue>0</resetValue>
+          <resetValue>0xAA0000</resetValue>
           <resetMask>0xFFFFFFFF</resetMask>
           <fields>
             <field>
@@ -7703,13 +7675,6 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
                 </enumeratedValue>
               </enumeratedValues>
             </field>
-            <field>
-              <name>CM7_INIT_VTOR</name>
-              <description>Vector table offset register out of reset</description>
-              <bitOffset>7</bitOffset>
-              <bitWidth>25</bitWidth>
-              <access>read-write</access>
-            </field>
           </fields>
         </register>
         <register>
@@ -7925,19 +7890,19 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
           <resetMask>0xFFFFFFFF</resetMask>
           <fields>
             <field>
-              <name>LOCK_M7_APC_AC_R1_TOP</name>
+              <name>LOCK_M7_APC_AC_R2_TOP</name>
               <description>lock M7_APC_AC_R2_TOP field for changes</description>
               <bitOffset>0</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
               <enumeratedValues>
                 <enumeratedValue>
-                  <name>LOCK_M7_APC_AC_R1_TOP_0</name>
+                  <name>LOCK_M7_APC_AC_R2_TOP_0</name>
                   <description>Register field [31:1] is not locked</description>
                   <value>0</value>
                 </enumeratedValue>
                 <enumeratedValue>
-                  <name>LOCK_M7_APC_AC_R1_TOP_1</name>
+                  <name>LOCK_M7_APC_AC_R2_TOP_1</name>
                   <description>Register field [31:1] is locked (read access only)</description>
                   <value>0x1</value>
                 </enumeratedValue>
@@ -7981,7 +7946,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               </enumeratedValues>
             </field>
             <field>
-              <name>M7_APC_AC_R2_BOT</name>
+              <name>M7_APC_AC_R3_BOT</name>
               <description>APC end address of memory region-3</description>
               <bitOffset>3</bitOffset>
               <bitWidth>29</bitWidth>
@@ -8097,145 +8062,6 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitWidth>1</bitWidth>
               <access>read-write</access>
             </field>
-            <field>
-              <name>Reserved</name>
-              <description>Reserved</description>
-              <bitOffset>3</bitOffset>
-              <bitWidth>29</bitWidth>
-              <access>read-only</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>OCRAM_MAGIC_ADDR</name>
-          <description>OCRAM Magic Address Register</description>
-          <addressOffset>0x4</addressOffset>
-          <size>32</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0xFFFFFFFF</resetMask>
-          <fields>
-            <field>
-              <name>OCRAM_WR_RD_SEL</name>
-              <description>OCRAM Write Read Select</description>
-              <bitOffset>0</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>OCRAM_WR_RD_SEL_0</name>
-                  <description>When OCRAM read access hits magic address, it will generate interrupt.</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>OCRAM_WR_RD_SEL_1</name>
-                  <description>When OCRAM write access hits magic address, it will generate interrupt.</description>
-                  <value>0x1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>OCRAM_MAGIC_ADDR</name>
-              <description>OCRAM Magic Address</description>
-              <bitOffset>1</bitOffset>
-              <bitWidth>16</bitWidth>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>Reserved</name>
-              <description>Reserved</description>
-              <bitOffset>17</bitOffset>
-              <bitWidth>15</bitWidth>
-              <access>read-only</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>DTCM_MAGIC_ADDR</name>
-          <description>DTCM Magic Address Register</description>
-          <addressOffset>0x8</addressOffset>
-          <size>32</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0xFFFFFFFF</resetMask>
-          <fields>
-            <field>
-              <name>DTCM_WR_RD_SEL</name>
-              <description>DTCM Write Read Select</description>
-              <bitOffset>0</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>DTCM_WR_RD_SEL_0</name>
-                  <description>When DTCM read access hits magic address, it will generate interrupt.</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>DTCM_WR_RD_SEL_1</name>
-                  <description>When DTCM write access hits magic address, it will generate interrupt.</description>
-                  <value>0x1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>DTCM_MAGIC_ADDR</name>
-              <description>DTCM Magic Address</description>
-              <bitOffset>1</bitOffset>
-              <bitWidth>16</bitWidth>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>Reserved</name>
-              <description>Reserved</description>
-              <bitOffset>17</bitOffset>
-              <bitWidth>15</bitWidth>
-              <access>read-only</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>ITCM_MAGIC_ADDR</name>
-          <description>ITCM Magic Address Register</description>
-          <addressOffset>0xC</addressOffset>
-          <size>32</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0xFFFFFFFF</resetMask>
-          <fields>
-            <field>
-              <name>ITCM_WR_RD_SEL</name>
-              <description>ITCM Write Read Select</description>
-              <bitOffset>0</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>ITCM_WR_RD_SEL_0</name>
-                  <description>When ITCM read access hits magic address, it will generate interrupt.</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>ITCM_WR_RD_SEL_1</name>
-                  <description>When ITCM write access hits magic address, it will generate interrupt.</description>
-                  <value>0x1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>ITCM_MAGIC_ADDR</name>
-              <description>ITCM Magic Address</description>
-              <bitOffset>1</bitOffset>
-              <bitWidth>16</bitWidth>
-              <access>read-write</access>
-            </field>
-            <field>
-              <name>Reserved</name>
-              <description>Reserved</description>
-              <bitOffset>17</bitOffset>
-              <bitWidth>15</bitWidth>
-              <access>read-only</access>
-            </field>
           </fields>
         </register>
         <register>
@@ -8247,66 +8073,6 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
           <resetValue>0</resetValue>
           <resetMask>0xFFFFFFFF</resetMask>
           <fields>
-            <field>
-              <name>ITCM_MAM_STATUS</name>
-              <description>ITCM Magic Address Match Status</description>
-              <bitOffset>0</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-write</access>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>ITCM_MAM_STATUS_0</name>
-                  <description>ITCM did not access magic address.</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>ITCM_MAM_STATUS_1</name>
-                  <description>ITCM accessed magic address.</description>
-                  <value>0x1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>DTCM_MAM_STATUS</name>
-              <description>DTCM Magic Address Match Status</description>
-              <bitOffset>1</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-write</access>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>DTCM_MAM_STATUS_0</name>
-                  <description>DTCM did not access magic address.</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>DTCM_MAM_STATUS_1</name>
-                  <description>DTCM accessed magic address.</description>
-                  <value>0x1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>OCRAM_MAM_STATUS</name>
-              <description>OCRAM Magic Address Match Status</description>
-              <bitOffset>2</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-write</access>
-              <modifiedWriteValues>oneToClear</modifiedWriteValues>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>OCRAM_MAM_STATUS_0</name>
-                  <description>OCRAM did not access magic address.</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>OCRAM_MAM_STATUS_1</name>
-                  <description>OCRAM accessed magic address.</description>
-                  <value>0x1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
             <field>
               <name>ITCM_ERR_STATUS</name>
               <description>ITCM Access Error Status</description>
@@ -8367,13 +8133,6 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
                 </enumeratedValue>
               </enumeratedValues>
             </field>
-            <field>
-              <name>Reserved</name>
-              <description>Reserved</description>
-              <bitOffset>6</bitOffset>
-              <bitWidth>26</bitWidth>
-              <access>read-only</access>
-            </field>
           </fields>
         </register>
         <register>
@@ -8385,63 +8144,6 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
           <resetValue>0</resetValue>
           <resetMask>0xFFFFFFFF</resetMask>
           <fields>
-            <field>
-              <name>ITCM_MAM_STAT_EN</name>
-              <description>ITCM Magic Address Match Status Enable</description>
-              <bitOffset>0</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>ITCM_MAM_STAT_EN_0</name>
-                  <description>Masked</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>ITCM_MAM_STAT_EN_1</name>
-                  <description>Enabled</description>
-                  <value>0x1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>DTCM_MAM_STAT_EN</name>
-              <description>DTCM Magic Address Match Status Enable</description>
-              <bitOffset>1</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>DTCM_MAM_STAT_EN_0</name>
-                  <description>Masked</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>DTCM_MAM_STAT_EN_1</name>
-                  <description>Enabled</description>
-                  <value>0x1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>OCRAM_MAM_STAT_EN</name>
-              <description>OCRAM Magic Address Match Status Enable</description>
-              <bitOffset>2</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>OCRAM_MAM_STAT_EN_0</name>
-                  <description>Masked</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>OCRAM_MAM_STAT_EN_1</name>
-                  <description>Enabled</description>
-                  <value>0x1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
             <field>
               <name>ITCM_ERR_STAT_EN</name>
               <description>ITCM Access Error Status Enable</description>
@@ -8499,13 +8201,6 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
                 </enumeratedValue>
               </enumeratedValues>
             </field>
-            <field>
-              <name>Reserved</name>
-              <description>Reserved</description>
-              <bitOffset>6</bitOffset>
-              <bitWidth>26</bitWidth>
-              <access>read-only</access>
-            </field>
           </fields>
         </register>
         <register>
@@ -8517,63 +8212,6 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
           <resetValue>0</resetValue>
           <resetMask>0xFFFFFFFF</resetMask>
           <fields>
-            <field>
-              <name>ITCM_MAM_SIG_EN</name>
-              <description>ITCM Magic Address Match Interrupt Enable</description>
-              <bitOffset>0</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>ITCM_MAM_SIG_EN_0</name>
-                  <description>Masked</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>ITCM_MAM_SIG_EN_1</name>
-                  <description>Enabled</description>
-                  <value>0x1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>DTCM_MAM_SIG_EN</name>
-              <description>DTCM Magic Address Match Interrupt Enable</description>
-              <bitOffset>1</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>DTCM_MAM_SIG_EN_0</name>
-                  <description>Masked</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>DTCM_MAM_SIG_EN_1</name>
-                  <description>Enabled</description>
-                  <value>0x1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
-            <field>
-              <name>OCRAM_MAM_SIG_EN</name>
-              <description>OCRAM Magic Address Match Interrupt Enable</description>
-              <bitOffset>2</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-write</access>
-              <enumeratedValues>
-                <enumeratedValue>
-                  <name>OCRAM_MAM_SIG_EN_0</name>
-                  <description>Masked</description>
-                  <value>0</value>
-                </enumeratedValue>
-                <enumeratedValue>
-                  <name>OCRAM_MAM_SIG_EN_1</name>
-                  <description>Enabled</description>
-                  <value>0x1</value>
-                </enumeratedValue>
-              </enumeratedValues>
-            </field>
             <field>
               <name>ITCM_ERR_SIG_EN</name>
               <description>ITCM Access Error Interrupt Enable</description>
@@ -8631,13 +8269,6 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
                 </enumeratedValue>
               </enumeratedValues>
             </field>
-            <field>
-              <name>Reserved</name>
-              <description>Reserved</description>
-              <bitOffset>6</bitOffset>
-              <bitWidth>26</bitWidth>
-              <access>read-only</access>
-            </field>
           </fields>
         </register>
       </registers>
@@ -20932,6 +20563,10 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
         <size>0x180</size>
         <usage>registers</usage>
       </addressBlock>
+      <interrupt>
+        <name>PMU_EVENT</name>
+        <value>61</value>
+      </interrupt>
       <registers>
         <register>
           <name>REG_1P1</name>
@@ -27439,6 +27074,14 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
         <size>0x2A0</size>
         <usage>registers</usage>
       </addressBlock>
+      <interrupt>
+        <name>TEMP_LOW_HIGH</name>
+        <value>63</value>
+      </interrupt>
+      <interrupt>
+        <name>TEMP_PANIC</name>
+        <value>64</value>
+      </interrupt>
       <registers>
         <register>
           <name>TEMPSENSE0</name>
@@ -78032,6 +77675,94 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
             </field>
           </fields>
         </register>
+        <register>
+          <name>DBG1</name>
+          <description>Debug 1 register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x10000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>CFSM</name>
+              <description>CAN Finite State Machine</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CBN</name>
+              <description>CAN Bit Number</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBG2</name>
+          <description>Debug 2 register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>RMP</name>
+              <description>Rx Matching Pointer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MPP</name>
+              <description>Matching Process in Progress</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>MPP_0</name>
+                  <description>No matching process ongoing.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>MPP_1</name>
+                  <description>Matching process is in progress.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TAP</name>
+              <description>Tx Arbitration Pointer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP</name>
+              <description>Arbitration Process in Progress</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>APP_0</name>
+                  <description>No matching process ongoing.</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APP_1</name>
+                  <description>Matching process is in progress.</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
         <register>
           <name>CS0</name>
           <description>Message Buffer 0 CS Register</description>
@@ -90342,6 +90073,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>0</bitOffset>
               <bitWidth>6</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToSet</modifiedWriteValues>
             </field>
             <field>
               <name>BUSY</name>
@@ -90349,6 +90081,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>8</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-only</access>
+              <modifiedWriteValues>oneToSet</modifiedWriteValues>
             </field>
             <field>
               <name>ERROR</name>
@@ -90356,6 +90089,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>9</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToSet</modifiedWriteValues>
             </field>
             <field>
               <name>RELOAD_SHADOWS</name>
@@ -90363,6 +90097,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>10</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToSet</modifiedWriteValues>
             </field>
             <field>
               <name>WR_UNLOCK</name>
@@ -90370,6 +90105,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>16</bitOffset>
               <bitWidth>16</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToSet</modifiedWriteValues>
             </field>
           </fields>
         </register>
@@ -90388,6 +90124,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>0</bitOffset>
               <bitWidth>6</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
             </field>
             <field>
               <name>BUSY</name>
@@ -90395,6 +90132,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>8</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-only</access>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
             </field>
             <field>
               <name>ERROR</name>
@@ -90402,6 +90140,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>9</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
             </field>
             <field>
               <name>RELOAD_SHADOWS</name>
@@ -90409,6 +90148,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>10</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
             </field>
             <field>
               <name>WR_UNLOCK</name>
@@ -90416,6 +90156,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>16</bitOffset>
               <bitWidth>16</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
             </field>
           </fields>
         </register>
@@ -90434,6 +90175,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>0</bitOffset>
               <bitWidth>6</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToToggle</modifiedWriteValues>
             </field>
             <field>
               <name>BUSY</name>
@@ -90441,6 +90183,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>8</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-only</access>
+              <modifiedWriteValues>oneToToggle</modifiedWriteValues>
             </field>
             <field>
               <name>ERROR</name>
@@ -90448,6 +90191,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>9</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToToggle</modifiedWriteValues>
             </field>
             <field>
               <name>RELOAD_SHADOWS</name>
@@ -90455,6 +90199,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>10</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToToggle</modifiedWriteValues>
             </field>
             <field>
               <name>WR_UNLOCK</name>
@@ -90462,6 +90207,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>16</bitOffset>
               <bitWidth>16</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToToggle</modifiedWriteValues>
             </field>
           </fields>
         </register>
@@ -90651,6 +90397,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>0</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToSet</modifiedWriteValues>
             </field>
             <field>
               <name>SPARE</name>
@@ -90658,6 +90405,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>1</bitOffset>
               <bitWidth>30</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToSet</modifiedWriteValues>
             </field>
             <field>
               <name>LOCK</name>
@@ -90665,6 +90413,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>31</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToSet</modifiedWriteValues>
             </field>
           </fields>
         </register>
@@ -90683,6 +90432,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>0</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
             </field>
             <field>
               <name>SPARE</name>
@@ -90690,6 +90440,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>1</bitOffset>
               <bitWidth>30</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
             </field>
             <field>
               <name>LOCK</name>
@@ -90697,6 +90448,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>31</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
             </field>
           </fields>
         </register>
@@ -90715,6 +90467,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>0</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToToggle</modifiedWriteValues>
             </field>
             <field>
               <name>SPARE</name>
@@ -90722,6 +90475,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>1</bitOffset>
               <bitWidth>30</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToToggle</modifiedWriteValues>
             </field>
             <field>
               <name>LOCK</name>
@@ -90729,6 +90483,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitOffset>31</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
+              <modifiedWriteValues>oneToToggle</modifiedWriteValues>
             </field>
           </fields>
         </register>
@@ -90854,13 +90609,6 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
               <bitWidth>2</bitWidth>
               <access>read-only</access>
             </field>
-            <field>
-              <name>SRK</name>
-              <description>Status of shadow register and OTP write lock for srk region</description>
-              <bitOffset>14</bitOffset>
-              <bitWidth>1</bitWidth>
-              <access>read-only</access>
-            </field>
             <field>
               <name>OTPMK_MSB</name>
               <description>Status of shadow register read and write, OTP read and write lock for otpmk region (MSB)</description>
@@ -185395,7 +185143,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
             </field>
             <field>
               <name>AC_PROT_EN</name>
-              <description>Enable access permission control</description>
+              <description>Enable access permission control When AC_PROT_EN is asserted, all encrypted regions are limited to be ARM core access only</description>
               <bitOffset>6</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-write</access>
@@ -185582,7 +185330,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
           <fields>
             <field>
               <name>ADDR_OFFSET0</name>
-              <description>Address offset used to remap received address to output address of memory region0</description>
+              <description>Signed offset for BEE region 0</description>
               <bitOffset>0</bitOffset>
               <bitWidth>16</bitWidth>
               <access>read-write</access>
@@ -185606,14 +185354,14 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
           <resetMask>0xFFFFFFFF</resetMask>
           <fields>
             <field>
-              <name>ADDR_OFFSET0</name>
-              <description>Address offset used to remap received address to output address of memory region1</description>
+              <name>ADDR_OFFSET1</name>
+              <description>Signed offset for BEE region 1</description>
               <bitOffset>0</bitOffset>
               <bitWidth>16</bitWidth>
               <access>read-write</access>
             </field>
             <field>
-              <name>ADDR_OFFSET0_LOCK</name>
+              <name>ADDR_OFFSET1_LOCK</name>
               <description>Lock bits for addr_offset1</description>
               <bitOffset>16</bitOffset>
               <bitWidth>16</bitWidth>
@@ -185704,7 +185452,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
           <fields>
             <field>
               <name>IRQ_VEC</name>
-              <description>bit 7: Protected region-3 access violation bit 6: Protected region-2 access violation bit 5: Protected region-1 access violation bit 4: Protected region-0 access violation bit 3: Region-1 read channel security violation bit 2: Read channel illegal access detected bit 1: Region-0 Read channel security violation bit 0: Disable abort</description>
+              <description>bit 7: Protected region-3 access violation bit 6: Protected region-2 access violation bit 5: Protected region-1 access violation bit 4: Protected region-0 access violation bit 3: Region-1 read channel security violation bit 2: Read channel illegal access detected bit 1: Region-0 read channel security violation bit 0: Disable abort</description>
               <bitOffset>0</bitOffset>
               <bitWidth>8</bitWidth>
               <access>read-write</access>
@@ -185712,7 +185460,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
             </field>
             <field>
               <name>BEE_IDLE</name>
-              <description>Lock bits for addr_offset1</description>
+              <description>1'b1: BEE is idle; 1'b0: BEE is active</description>
               <bitOffset>8</bitOffset>
               <bitWidth>1</bitWidth>
               <access>read-only</access>
@@ -193179,19 +192927,19 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
         <value>60</value>
       </interrupt>
       <interrupt>
-        <name>ANATOP_EVENT0</name>
+        <name>PMU_EVENT</name>
         <value>61</value>
       </interrupt>
       <interrupt>
-        <name>ANATOP_EVENT1</name>
+        <name>Reserved78</name>
         <value>62</value>
       </interrupt>
       <interrupt>
-        <name>ANATOP_TAMP_LOW_HIGH</name>
+        <name>TEMP_LOW_HIGH</name>
         <value>63</value>
       </interrupt>
       <interrupt>
-        <name>ANATOP_TEMP_PANIC</name>
+        <name>TEMP_PANIC</name>
         <value>64</value>
       </interrupt>
       <interrupt>
@@ -193538,38 +193286,6 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
         <name>PWM4_FAULT</name>
         <value>151</value>
       </interrupt>
-      <interrupt>
-        <name>Reserved168</name>
-        <value>152</value>
-      </interrupt>
-      <interrupt>
-        <name>Reserved169</name>
-        <value>153</value>
-      </interrupt>
-      <interrupt>
-        <name>Reserved170</name>
-        <value>154</value>
-      </interrupt>
-      <interrupt>
-        <name>Reserved171</name>
-        <value>155</value>
-      </interrupt>
-      <interrupt>
-        <name>Reserved172</name>
-        <value>156</value>
-      </interrupt>
-      <interrupt>
-        <name>Reserved173</name>
-        <value>157</value>
-      </interrupt>
-      <interrupt>
-        <name>SJC_ARM_DEBUG</name>
-        <value>158</value>
-      </interrupt>
-      <interrupt>
-        <name>NMI_WAKEUP</name>
-        <value>159</value>
-      </interrupt>
       <registers>
         <register>
           <name>NVICISER0</name>
@@ -195150,7 +194866,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
           <fields>
             <field>
               <name>PRI61</name>
-              <description>Priority of the INT_ANATOP_EVENT0 interrupt 61</description>
+              <description>Priority of the INT_PMU_EVENT interrupt 61</description>
               <bitOffset>4</bitOffset>
               <bitWidth>4</bitWidth>
               <access>read-write</access>
@@ -195168,7 +194884,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
           <fields>
             <field>
               <name>PRI62</name>
-              <description>Priority of the INT_ANATOP_EVENT1 interrupt 62</description>
+              <description>Priority of the INT_Reserved78 interrupt 62</description>
               <bitOffset>4</bitOffset>
               <bitWidth>4</bitWidth>
               <access>read-write</access>
@@ -195186,7 +194902,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
           <fields>
             <field>
               <name>PRI63</name>
-              <description>Priority of the INT_ANATOP_TAMP_LOW_HIGH interrupt 63</description>
+              <description>Priority of the INT_TEMP_LOW_HIGH interrupt 63</description>
               <bitOffset>4</bitOffset>
               <bitWidth>4</bitWidth>
               <access>read-write</access>
@@ -195204,7 +194920,7 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
           <fields>
             <field>
               <name>PRI64</name>
-              <description>Priority of the INT_ANATOP_TEMP_PANIC interrupt 64</description>
+              <description>Priority of the INT_TEMP_PANIC interrupt 64</description>
               <bitOffset>4</bitOffset>
               <bitWidth>4</bitWidth>
               <access>read-write</access>
@@ -196777,150 +196493,6 @@ IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
             </field>
           </fields>
         </register>
-        <register>
-          <name>NVICIP152</name>
-          <description>Interrupt Priority Register 152</description>
-          <addressOffset>0x398</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0xFF</resetMask>
-          <fields>
-            <field>
-              <name>PRI152</name>
-              <description>Priority of the INT_Reserved168 interrupt 152</description>
-              <bitOffset>4</bitOffset>
-              <bitWidth>4</bitWidth>
-              <access>read-write</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>NVICIP153</name>
-          <description>Interrupt Priority Register 153</description>
-          <addressOffset>0x399</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0xFF</resetMask>
-          <fields>
-            <field>
-              <name>PRI153</name>
-              <description>Priority of the INT_Reserved169 interrupt 153</description>
-              <bitOffset>4</bitOffset>
-              <bitWidth>4</bitWidth>
-              <access>read-write</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>NVICIP154</name>
-          <description>Interrupt Priority Register 154</description>
-          <addressOffset>0x39A</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0xFF</resetMask>
-          <fields>
-            <field>
-              <name>PRI154</name>
-              <description>Priority of the INT_Reserved170 interrupt 154</description>
-              <bitOffset>4</bitOffset>
-              <bitWidth>4</bitWidth>
-              <access>read-write</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>NVICIP155</name>
-          <description>Interrupt Priority Register 155</description>
-          <addressOffset>0x39B</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0xFF</resetMask>
-          <fields>
-            <field>
-              <name>PRI155</name>
-              <description>Priority of the INT_Reserved171 interrupt 155</description>
-              <bitOffset>4</bitOffset>
-              <bitWidth>4</bitWidth>
-              <access>read-write</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>NVICIP156</name>
-          <description>Interrupt Priority Register 156</description>
-          <addressOffset>0x39C</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0xFF</resetMask>
-          <fields>
-            <field>
-              <name>PRI156</name>
-              <description>Priority of the INT_Reserved172 interrupt 156</description>
-              <bitOffset>4</bitOffset>
-              <bitWidth>4</bitWidth>
-              <access>read-write</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>NVICIP157</name>
-          <description>Interrupt Priority Register 157</description>
-          <addressOffset>0x39D</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0xFF</resetMask>
-          <fields>
-            <field>
-              <name>PRI157</name>
-              <description>Priority of the INT_Reserved173 interrupt 157</description>
-              <bitOffset>4</bitOffset>
-              <bitWidth>4</bitWidth>
-              <access>read-write</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>NVICIP158</name>
-          <description>Interrupt Priority Register 158</description>
-          <addressOffset>0x39E</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0xFF</resetMask>
-          <fields>
-            <field>
-              <name>PRI158</name>
-              <description>Priority of the INT_SJC_ARM_DEBUG interrupt 158</description>
-              <bitOffset>4</bitOffset>
-              <bitWidth>4</bitWidth>
-              <access>read-write</access>
-            </field>
-          </fields>
-        </register>
-        <register>
-          <name>NVICIP159</name>
-          <description>Interrupt Priority Register 159</description>
-          <addressOffset>0x39F</addressOffset>
-          <size>8</size>
-          <access>read-write</access>
-          <resetValue>0</resetValue>
-          <resetMask>0xFF</resetMask>
-          <fields>
-            <field>
-              <name>PRI159</name>
-              <description>Priority of the INT_NMI_WAKEUP interrupt 159</description>
-              <bitOffset>4</bitOffset>
-              <bitWidth>4</bitWidth>
-              <access>read-write</access>
-            </field>
-          </fields>
-        </register>
         <register>
           <name>NVICSTIR</name>
           <description>Software Trigger Interrupt Register</description>

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/MIMXRT1052_features.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/MIMXRT1052_features.h

@@ -1,44 +1,16 @@
 /*
 ** ###################################################################
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b180509
+**     Version:             rev. 1.1, 2018-11-16
+**     Build:               b181120
 **
 **     Abstract:
 **         Chip specific module features.
 **
-**     The Clear BSD License
 **     Copyright 2016 Freescale Semiconductor, Inc.
 **     Copyright 2016-2018 NXP
 **     All rights reserved.
 **
-**     Redistribution and use in source and binary forms, with or without
-**     modification, are permitted (subject to the limitations in the
-**     disclaimer below) provided that the following conditions are met:
-**
-**     * Redistributions of source code must retain the above copyright
-**       notice, this list of conditions and the following disclaimer.
-**
-**     * Redistributions in binary form must reproduce the above copyright
-**       notice, this list of conditions and the following disclaimer in the
-**       documentation and/or other materials provided with the distribution.
-**
-**     * Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from
-**       this software without specific prior written permission.
-**
-**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
@@ -46,6 +18,12 @@
 **     Revisions:
 **     - rev. 0.1 (2017-01-10)
 **         Initial version.
+**     - rev. 1.0 (2018-09-21)
+**         Update interrupt vector table and dma request source.
+**         Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
+**         Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
+**     - rev. 1.1 (2018-11-16)
+**         Update feature files to align with IMXRT1050RM Rev.1.
 **
 ** ###################################################################
 */
@@ -185,20 +163,34 @@
 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
 /* @brief Has doze mode support (register bit field MCR[DOZE]). */
 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
+/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0)
 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
-/* @brief Has extended bit timing register (register CBT). */
-#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
+/* @brief Instance has extended bit timing register (register CBT). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0)
 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
+/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0)
 /* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
 #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
+/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1)
 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
+/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1)
+/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1)
+/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1)
 /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
 #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0)
+/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
+#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (0)
 /* @brief Has extra MB interrupt or common one. */
 #define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
 
@@ -256,6 +248,13 @@
 /* @brief Has Additional 1588 Timer Channel Interrupt. */
 #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
 
+/* EWM module features */
+
+/* @brief Has clock select (register CLKCTRL). */
+#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT  (1)
+/* @brief Has clock prescaler (register CLKPRESCALER). */
+#define FSL_FEATURE_EWM_HAS_PRESCALER  (1)
+
 /* FLEXIO module features */
 
 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
@@ -282,7 +281,7 @@
 /* FLEXRAM module features */
 
 /* @brief Bank size */
-#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024)
+#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
 /* @brief Total Bank numbers */
 #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
 
@@ -418,7 +417,7 @@
 /* @brief Lowest interrupt request number. */
 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
 /* @brief Highest interrupt request number. */
-#define FSL_FEATURE_INTERRUPT_IRQ_MAX (159)
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (151)
 
 /* OCOTP module features */
 
@@ -507,8 +506,19 @@
 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
 /* @brief Has register of MCR. */
 #define FSL_FEATURE_SAI_HAS_MCR (0)
+/* @brief Has bit field MICS of the MCR register. */
+#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
 /* @brief Has register of MDR */
 #define FSL_FEATURE_SAI_HAS_MDR (0)
+/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
+#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
+
+/* SEMC module features */
+
+/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */
+#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (1)
+/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]).) */
+#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (1)
 
 /* SNVS module features */
 

bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/arm/MIMXRT1052xxxxx_flexspi_nor.scf

@@ -0,0 +1,90 @@
+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVJ5B
+**                          MIMXRT1052CVL5B
+**                          MIMXRT1052DVJ6B
+**                          MIMXRT1052DVL6B
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
+**     Version:             rev. 1.0, 2018-09-21
+**     Build:               b180921
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+#define m_flash_config_start           0x60000000
+#define m_flash_config_size            0x00001000
+
+#define m_ivt_start                    0x60001000
+#define m_ivt_size                     0x00001000
+
+#define m_interrupts_start             0x60002000
+#define m_interrupts_size              0x00000400
+
+#define m_text_start                   0x60002400
+#define m_text_size                    0x03FFDC00
+
+#define m_data_start                   0x20000000
+#define m_data_size                    0x00020000
+
+#define m_data2_start                  0x20200000
+#define m_data2_size                   0x00040000
+
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start {   ; load region size_region
+  RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
+    * (.boot_hdr.conf, +FIRST)
+  }
+
+  RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
+    * (.boot_hdr.ivt, +FIRST)
+    * (.boot_hdr.boot_data)
+    * (.boot_hdr.dcd_data)
+  }
+#else
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start {   ; load region size_region
+#endif
+  VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
+    * (RESET,+FIRST)
+  }
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+    * (NonCacheable.init)
+    * (NonCacheable)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+}

bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/arm/MIMXRT1052xxxxx_flexspi_nor_sdram.scf

@@ -0,0 +1,100 @@
+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVJ5B
+**                          MIMXRT1052CVL5B
+**                          MIMXRT1052DVJ6B
+**                          MIMXRT1052DVL6B
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
+**     Version:             rev. 1.0, 2018-09-21
+**     Build:               b180921
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+#define m_flash_config_start           0x60000000
+#define m_flash_config_size            0x00001000
+
+#define m_ivt_start                    0x60001000
+#define m_ivt_size                     0x00001000
+
+#define m_interrupts_start             0x60002000
+#define m_interrupts_size              0x00000400
+
+#define m_text_start                   0x60002400
+#define m_text_size                    0x03FFDC00
+
+#define m_data_start                   0x80000000
+#define m_data_size                    0x01E00000
+
+#define m_ncache_start                 0x81E00000
+#define m_ncache_size                  0x00200000
+
+#define m_data2_start                  0x20000000
+#define m_data2_size                   0x00020000
+
+#define m_data3_start                  0x20200000
+#define m_data3_size                   0x00040000
+
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start {   ; load region size_region
+  RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
+    * (.boot_hdr.conf, +FIRST)
+  }
+
+  RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
+    * (.boot_hdr.ivt, +FIRST)
+    * (.boot_hdr.boot_data)
+    * (.boot_hdr.dcd_data)
+  }
+#else
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start {   ; load region size_region
+#endif
+  VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
+    * (RESET,+FIRST)
+  }
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+    *(m_usb_dma_init_data)
+    *(m_usb_dma_noninit_data)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+  RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
+    * (NonCacheable.init)
+    * (NonCacheable)
+  }
+}

bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/arm/MIMXRT1052xxxxx_ram.scf

@@ -0,0 +1,71 @@
+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVJ5B
+**                          MIMXRT1052CVL5B
+**                          MIMXRT1052DVJ6B
+**                          MIMXRT1052DVL6B
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
+**     Version:             rev. 1.0, 2018-09-21
+**     Build:               b180921
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+#define m_interrupts_start             0x00000000
+#define m_interrupts_size              0x00000400
+
+#define m_text_start                   0x00000400
+#define m_text_size                    0x0001FC00
+
+#define m_data_start                   0x20000000
+#define m_data_size                    0x00020000
+
+#define m_data2_start                  0x20200000
+#define m_data2_size                   0x00040000
+
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start {   ; load region size_region
+  VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
+    * (RESET,+FIRST)
+  }
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+    * (NonCacheable.init)
+    * (NonCacheable)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+}

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_sdram.scf → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/arm/MIMXRT1052xxxxx_sdram.scf

@@ -8,45 +8,17 @@
 **
 **     Compiler:            Keil ARM C/C++ Compiler
 **     Reference manual:    IMXRT1050RM Rev.1, 03/2018
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b180509
+**     Version:             rev. 1.0, 2018-09-21
+**     Build:               b180921
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
-**     The Clear BSD License
 **     Copyright 2016 Freescale Semiconductor, Inc.
 **     Copyright 2016-2018 NXP
 **     All rights reserved.
 **
-**     Redistribution and use in source and binary forms, with or without
-**     modification, are permitted (subject to the limitations in the
-**     disclaimer below) provided that the following conditions are met:
-**
-**     * Redistributions of source code must retain the above copyright
-**       notice, this list of conditions and the following disclaimer.
-**
-**     * Redistributions in binary form must reproduce the above copyright
-**       notice, this list of conditions and the following disclaimer in the
-**       documentation and/or other materials provided with the distribution.
-**
-**     * Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from
-**       this software without specific prior written permission.
-**
-**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
@@ -85,11 +57,11 @@
   #define Heap_Size                    0x0400
 #endif
 
-LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size {   ; load region size_region
-  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start {   ; load region size_region
+  VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
     * (RESET,+FIRST)
   }
-  ER_m_text m_text_start m_text_size { ; load address = execution address
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
     * (InRoot$$Sections)
     .ANY (+RO)
   }

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/MIMXRT1052xxxxx_sdram_txt.scf → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/arm/MIMXRT1052xxxxx_sdram_txt.scf

@@ -8,45 +8,17 @@
 **
 **     Compiler:            Keil ARM C/C++ Compiler
 **     Reference manual:    IMXRT1050RM Rev.1, 03/2018
-**     Version:             rev. 0.1, 2017-01-10
-**     Build:               b180509
+**     Version:             rev. 1.0, 2018-09-21
+**     Build:               b180921
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
-**     The Clear BSD License
 **     Copyright 2016 Freescale Semiconductor, Inc.
 **     Copyright 2016-2018 NXP
 **     All rights reserved.
 **
-**     Redistribution and use in source and binary forms, with or without
-**     modification, are permitted (subject to the limitations in the
-**     disclaimer below) provided that the following conditions are met:
-**
-**     * Redistributions of source code must retain the above copyright
-**       notice, this list of conditions and the following disclaimer.
-**
-**     * Redistributions in binary form must reproduce the above copyright
-**       notice, this list of conditions and the following disclaimer in the
-**       documentation and/or other materials provided with the distribution.
-**
-**     * Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from
-**       this software without specific prior written permission.
-**
-**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
@@ -85,11 +57,11 @@
   #define Heap_Size                    0x0400
 #endif
 
-LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size {   ; load region size_region
-  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start {   ; load region size_region
+  VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
     * (RESET,+FIRST)
   }
-  ER_m_text m_text_start m_text_size { ; load address = execution address
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
     * (InRoot$$Sections)
     .ANY (+RO)
   }

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/arm/startup_MIMXRT1052.s → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/arm/startup_MIMXRT1052.s

@@ -2,44 +2,16 @@
 ; *  @file:    startup_MIMXRT1052.s
 ; *  @purpose: CMSIS Cortex-M7 Core Device Startup File
 ; *            MIMXRT1052
-; *  @version: 0.1
-; *  @date:    2017-1-10
-; *  @build:   b180509
+; *  @version: 1.0
+; *  @date:    2018-9-21
+; *  @build:   b180921
 ; * -------------------------------------------------------------------------
 ; *
-; * The Clear BSD License
 ; * Copyright 1997-2016 Freescale Semiconductor, Inc.
 ; * Copyright 2016-2018 NXP
 ; * All rights reserved.
 ; *
-; * Redistribution and use in source and binary forms, with or without
-; * modification, are permitted (subject to the limitations in the
-; * disclaimer below) provided that the following conditions are met:
-; *
-; * * Redistributions of source code must retain the above copyright
-; *   notice, this list of conditions and the following disclaimer.
-; *
-; * * Redistributions in binary form must reproduce the above copyright
-; *   notice, this list of conditions and the following disclaimer in the
-; *   documentation and/or other materials provided with the distribution.
-; *
-; * * Neither the name of the copyright holder nor the names of its
-; *   contributors may be used to endorse or promote products derived from
-; *   this software without specific prior written permission.
-; *
-; * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-; * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-; * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-; * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-; * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-; * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-; * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-; * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; * SPDX-License-Identifier: BSD-3-Clause
 ; *
 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
 ; *
@@ -137,10 +109,10 @@ __Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
                 DCD     SAI3_RX_IRQHandler                  ;SAI3 interrupt
                 DCD     SAI3_TX_IRQHandler                  ;SAI3 interrupt
                 DCD     SPDIF_IRQHandler                    ;SPDIF interrupt
-                DCD     ANATOP_EVENT0_IRQHandler            ;ANATOP interrupt
-                DCD     ANATOP_EVENT1_IRQHandler            ;ANATOP interrupt
-                DCD     ANATOP_TAMP_LOW_HIGH_IRQHandler     ;ANATOP interrupt
-                DCD     ANATOP_TEMP_PANIC_IRQHandler        ;ANATOP interrupt
+                DCD     PMU_EVENT_IRQHandler                ;Brown-out event interrupt
+                DCD     Reserved78_IRQHandler               ;Reserved interrupt
+                DCD     TEMP_LOW_HIGH_IRQHandler            ;TempSensor low/high interrupt
+                DCD     TEMP_PANIC_IRQHandler               ;TempSensor panic interrupt
                 DCD     USB_PHY1_IRQHandler                 ;USBPHY (UTMI0), Interrupt
                 DCD     USB_PHY2_IRQHandler                 ;USBPHY (UTMI0), Interrupt
                 DCD     ADC1_IRQHandler                     ;ADC1 interrupt
@@ -228,14 +200,14 @@ __Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
                 DCD     PWM4_2_IRQHandler                   ;PWM4 capture 2, compare 2, or reload 0 interrupt
                 DCD     PWM4_3_IRQHandler                   ;PWM4 capture 3, compare 3, or reload 0 interrupt
                 DCD     PWM4_FAULT_IRQHandler               ;PWM4 fault or reload error interrupt
-                DCD     Reserved168_IRQHandler              ;Reserved interrupt
-                DCD     Reserved169_IRQHandler              ;Reserved interrupt
-                DCD     Reserved170_IRQHandler              ;Reserved interrupt
-                DCD     Reserved171_IRQHandler              ;Reserved interrupt
-                DCD     Reserved172_IRQHandler              ;Reserved interrupt
-                DCD     Reserved173_IRQHandler              ;Reserved interrupt
-                DCD     SJC_ARM_DEBUG_IRQHandler            ;SJC ARM debug interrupt
-                DCD     NMI_WAKEUP_IRQHandler               ;NMI wake up
+                DCD     DefaultISR                          ;168
+                DCD     DefaultISR                          ;169
+                DCD     DefaultISR                          ;170
+                DCD     DefaultISR                          ;171
+                DCD     DefaultISR                          ;172
+                DCD     DefaultISR                          ;173
+                DCD     DefaultISR                          ;174
+                DCD     DefaultISR                          ;175
                 DCD     DefaultISR                          ;176
                 DCD     DefaultISR                          ;177
                 DCD     DefaultISR                          ;178
@@ -781,10 +753,10 @@ Default_Handler\
                 EXPORT  SAI3_RX_DriverIRQHandler         [WEAK]
                 EXPORT  SAI3_TX_DriverIRQHandler         [WEAK]
                 EXPORT  SPDIF_DriverIRQHandler         [WEAK]
-                EXPORT  ANATOP_EVENT0_IRQHandler         [WEAK]
-                EXPORT  ANATOP_EVENT1_IRQHandler         [WEAK]
-                EXPORT  ANATOP_TAMP_LOW_HIGH_IRQHandler         [WEAK]
-                EXPORT  ANATOP_TEMP_PANIC_IRQHandler         [WEAK]
+                EXPORT  PMU_EVENT_IRQHandler         [WEAK]
+                EXPORT  Reserved78_IRQHandler         [WEAK]
+                EXPORT  TEMP_LOW_HIGH_IRQHandler         [WEAK]
+                EXPORT  TEMP_PANIC_IRQHandler         [WEAK]
                 EXPORT  USB_PHY1_IRQHandler         [WEAK]
                 EXPORT  USB_PHY2_IRQHandler         [WEAK]
                 EXPORT  ADC1_IRQHandler         [WEAK]
@@ -872,14 +844,6 @@ Default_Handler\
                 EXPORT  PWM4_2_IRQHandler         [WEAK]
                 EXPORT  PWM4_3_IRQHandler         [WEAK]
                 EXPORT  PWM4_FAULT_IRQHandler         [WEAK]
-                EXPORT  Reserved168_IRQHandler         [WEAK]
-                EXPORT  Reserved169_IRQHandler         [WEAK]
-                EXPORT  Reserved170_IRQHandler         [WEAK]
-                EXPORT  Reserved171_IRQHandler         [WEAK]
-                EXPORT  Reserved172_IRQHandler         [WEAK]
-                EXPORT  Reserved173_IRQHandler         [WEAK]
-                EXPORT  SJC_ARM_DEBUG_IRQHandler         [WEAK]
-                EXPORT  NMI_WAKEUP_IRQHandler         [WEAK]
                 EXPORT  DefaultISR         [WEAK]
 DMA0_DMA16_DriverIRQHandler
 DMA1_DMA17_DriverIRQHandler
@@ -942,10 +906,10 @@ SAI2_DriverIRQHandler
 SAI3_RX_DriverIRQHandler
 SAI3_TX_DriverIRQHandler
 SPDIF_DriverIRQHandler
-ANATOP_EVENT0_IRQHandler
-ANATOP_EVENT1_IRQHandler
-ANATOP_TAMP_LOW_HIGH_IRQHandler
-ANATOP_TEMP_PANIC_IRQHandler
+PMU_EVENT_IRQHandler
+Reserved78_IRQHandler
+TEMP_LOW_HIGH_IRQHandler
+TEMP_PANIC_IRQHandler
 USB_PHY1_IRQHandler
 USB_PHY2_IRQHandler
 ADC1_IRQHandler
@@ -1033,14 +997,6 @@ PWM4_1_IRQHandler
 PWM4_2_IRQHandler
 PWM4_3_IRQHandler
 PWM4_FAULT_IRQHandler
-Reserved168_IRQHandler
-Reserved169_IRQHandler
-Reserved170_IRQHandler
-Reserved171_IRQHandler
-Reserved172_IRQHandler
-Reserved173_IRQHandler
-SJC_ARM_DEBUG_IRQHandler
-NMI_WAKEUP_IRQHandler
 DefaultISR
                 LDR    R0, =DefaultISR
                 BX     R0

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/cmsis_drivers/fsl_lpi2c_cmsis.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/cmsis_drivers/fsl_lpi2c_cmsis.c

@@ -30,7 +30,7 @@
  * ARMCC does not support split the data section automatically, so the driver
  * needs to split the data to separate sections explicitly, to reduce codesize.
  */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 #define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
 #endif
 
@@ -915,7 +915,7 @@ AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C0_EdmaHandle);
 edma_handle_t LPI2C0_EdmaTxHandle;
 edma_handle_t LPI2C0_EdmaRxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c0_edma_driver_state")
 cmsis_lpi2c_edma_driver_state_t LPI2C0_EdmaDriverState = {
 #else
@@ -972,7 +972,7 @@ ARM_I2C_STATUS LPI2C0_Master_EdmaGetStatus(void)
 
 cmsis_i2c_handle_t LPI2C0_Handle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c0_interrupt_driver_state")
 cmsis_lpi2c_interrupt_driver_state_t LPI2C0_InterruptDriverState = {
 #else
@@ -1083,7 +1083,7 @@ AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C1_EdmaHandle);
 edma_handle_t LPI2C1_EdmaTxHandle;
 edma_handle_t LPI2C1_EdmaRxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c1_edma_driver_state")
 cmsis_lpi2c_edma_driver_state_t LPI2C1_EdmaDriverState = {
 #else
@@ -1140,7 +1140,7 @@ ARM_I2C_STATUS LPI2C1_Master_EdmaGetStatus(void)
 
 cmsis_i2c_handle_t LPI2C1_Handle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c1_interrupt_driver_state")
 cmsis_lpi2c_interrupt_driver_state_t LPI2C1_InterruptDriverState = {
 #else
@@ -1250,7 +1250,7 @@ AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C2_EdmaHandle);
 edma_handle_t LPI2C2_EdmaTxHandle;
 edma_handle_t LPI2C2_EdmaRxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c2_edma_driver_state")
 cmsis_lpi2c_edma_driver_state_t LPI2C2_EdmaDriverState = {
 #else
@@ -1307,7 +1307,7 @@ ARM_I2C_STATUS LPI2C2_Master_EdmaGetStatus(void)
 
 cmsis_i2c_handle_t LPI2C2_Handle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c2_interrupt_driver_state")
 cmsis_lpi2c_interrupt_driver_state_t LPI2C2_InterruptDriverState = {
 #else
@@ -1418,7 +1418,7 @@ AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C3_EdmaHandle);
 edma_handle_t LPI2C3_EdmaTxHandle;
 edma_handle_t LPI2C3_EdmaRxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c3_edma_driver_state")
 cmsis_lpi2c_edma_driver_state_t LPI2C3_EdmaDriverState = {
 #else
@@ -1474,7 +1474,7 @@ ARM_I2C_STATUS LPI2C3_Master_EdmaGetStatus(void)
 #else
 
 cmsis_i2c_handle_t LPI2C3_Handle;
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c3_interrupt_driver_state")
 cmsis_lpi2c_interrupt_driver_state_t LPI2C3_InterruptDriverState = {
 #else
@@ -1584,7 +1584,7 @@ AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C4_EdmaHandle);
 edma_handle_t LPI2C4_EdmaTxHandle;
 edma_handle_t LPI2C4_EdmaRxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c4_edma_driver_state")
 cmsis_lpi2c_edma_driver_state_t LPI2C4_EdmaDriverState = {
 #else
@@ -1640,7 +1640,7 @@ ARM_I2C_STATUS LPI2C4_Master_EdmaGetStatus(void)
 #else
 
 cmsis_i2c_handle_t LPI2C4_Handle;
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c4_interrupt_driver_state")
 cmsis_lpi2c_interrupt_driver_state_t LPI2C4_InterruptDriverState = {
 #else
@@ -1750,7 +1750,7 @@ AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C5_EdmaHandle);
 edma_handle_t LPI2C5_EdmaTxHandle;
 edma_handle_t LPI2C5_EdmaRxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c5_edma_driver_state")
 cmsis_lpi2c_edma_driver_state_t LPI2C5_EdmaDriverState = {
 #else
@@ -1806,7 +1806,7 @@ ARM_I2C_STATUS LPI2C5_Master_EdmaGetStatus(void)
 #else
 
 cmsis_i2c_handle_t LPI2C5_Handle;
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c5_interrupt_driver_state")
 cmsis_lpi2c_interrupt_driver_state_t LPI2C5_InterruptDriverState = {
 #else
@@ -1916,7 +1916,7 @@ AT_NONCACHEABLE_SECTION(lpi2c_master_edma_handle_t LPI2C6_EdmaHandle);
 edma_handle_t LPI2C6_EdmaTxHandle;
 edma_handle_t LPI2C6_EdmaRxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c6_edma_driver_state")
 cmsis_lpi2c_edma_driver_state_t LPI2C6_EdmaDriverState = {
 #else
@@ -1972,7 +1972,7 @@ ARM_I2C_STATUS LPI2C6_Master_EdmaGetStatus(void)
 #else
 
 cmsis_i2c_handle_t LPI2C6_Handle;
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpi2c6_interrupt_driver_state")
 cmsis_lpi2c_interrupt_driver_state_t LPI2C6_InterruptDriverState = {
 #else

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/cmsis_drivers/fsl_lpspi_cmsis.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/cmsis_drivers/fsl_lpspi_cmsis.c

@@ -18,7 +18,6 @@
  * limitations under the License.
  */
 
-
 #include "fsl_lpspi_cmsis.h"
 
 /* Component ID definition, used by tools. */
@@ -26,7 +25,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.lpspi_cmsis"
 #endif
 
-
 #if ((RTE_SPI0 && defined(LPSPI0)) || (RTE_SPI1 && defined(LPSPI1)) || (RTE_SPI2 && defined(LPSPI2)) || \
      (RTE_SPI3 && defined(LPSPI3)) || (RTE_SPI4 && defined(LPSPI4)) || (RTE_SPI5 && defined(LPSPI5)))
 
@@ -36,7 +34,7 @@
  * ARMCC does not support split the data section automatically, so the driver
  * needs to split the data to separate sections explicitly, to reduce codesize.
  */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 #define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
 #endif
 
@@ -1229,7 +1227,7 @@ AT_NONCACHEABLE_SECTION(cmsis_lpspi_edma_handle_t LPSPI0_EdmaHandle);
 edma_handle_t LPSPI0_EdmaTxDataToTxRegHandle;
 edma_handle_t LPSPI0_EdmaRxRegToRxDataHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpspi0_edma_driver_state")
 cmsis_lpspi_edma_driver_state_t LPSPI0_EdmaDriverState = {
 #else
@@ -1295,7 +1293,7 @@ static ARM_SPI_STATUS LPSPI0_EdmaGetStatus(void)
 
 cmsis_lpspi_handle_t LPSPI0_Handle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpspi0_interrupt_driver_state")
 cmsis_lpspi_interrupt_driver_state_t LPSPI0_InterruptDriverState = {
 #else
@@ -1392,7 +1390,7 @@ AT_NONCACHEABLE_SECTION(cmsis_lpspi_edma_handle_t LPSPI1_EdmaHandle);
 edma_handle_t LPSPI1_EdmaTxDataToTxRegHandle;
 edma_handle_t LPSPI1_EdmaRxRegToRxDataHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpspi1_edma_driver_state")
 cmsis_lpspi_edma_driver_state_t LPSPI1_EdmaDriverState = {
 #else
@@ -1458,7 +1456,7 @@ static ARM_SPI_STATUS LPSPI1_EdmaGetStatus(void)
 
 cmsis_lpspi_handle_t LPSPI1_Handle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpspi1_interrupt_driver_state")
 cmsis_lpspi_interrupt_driver_state_t LPSPI1_InterruptDriverState = {
 #else
@@ -1555,7 +1553,7 @@ AT_NONCACHEABLE_SECTION(cmsis_lpspi_edma_handle_t LPSPI2_EdmaHandle);
 edma_handle_t LPSPI2_EdmaTxDataToTxRegHandle;
 edma_handle_t LPSPI2_EdmaRxRegToRxDataHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpspi2_edma_driver_state")
 cmsis_lpspi_edma_driver_state_t LPSPI2_EdmaDriverState = {
 #else
@@ -1621,7 +1619,7 @@ static ARM_SPI_STATUS LPSPI2_EdmaGetStatus(void)
 
 cmsis_lpspi_handle_t LPSPI2_Handle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpspi2_interrupt_driver_state")
 cmsis_lpspi_interrupt_driver_state_t LPSPI2_InterruptDriverState = {
 #else
@@ -1718,7 +1716,7 @@ AT_NONCACHEABLE_SECTION(cmsis_lpspi_edma_handle_t LPSPI3_EdmaHandle);
 edma_handle_t LPSPI3_EdmaTxDataToTxRegHandle;
 edma_handle_t LPSPI3_EdmaRxRegToRxDataHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpspi3_edma_driver_state")
 cmsis_lpspi_edma_driver_state_t LPSPI3_EdmaDriverState = {
 #else
@@ -1784,7 +1782,7 @@ static ARM_SPI_STATUS LPSPI3_EdmaGetStatus(void)
 
 cmsis_lpspi_handle_t LPSPI3_Handle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpspi3_interrupt_driver_state")
 cmsis_lpspi_interrupt_driver_state_t LPSPI3_InterruptDriverState = {
 #else
@@ -1881,7 +1879,7 @@ AT_NONCACHEABLE_SECTION(cmsis_lpspi_edma_handle_t LPSPI4_EdmaHandle);
 edma_handle_t LPSPI4_EdmaTxDataToTxRegHandle;
 edma_handle_t LPSPI4_EdmaRxRegToRxDataHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpspi4_edma_driver_state")
 cmsis_lpspi_edma_driver_state_t LPSPI4_EdmaDriverState = {
 #else
@@ -1947,7 +1945,7 @@ static ARM_SPI_STATUS LPSPI4_EdmaGetStatus(void)
 
 cmsis_lpspi_handle_t LPSPI4_Handle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpspi4_interrupt_driver_state")
 cmsis_lpspi_interrupt_driver_state_t LPSPI4_InterruptDriverState = {
 #else
@@ -2044,7 +2042,7 @@ AT_NONCACHEABLE_SECTION(cmsis_lpspi_edma_handle_t LPSPI5_EdmaHandle);
 edma_handle_t LPSPI5_EdmaTxDataToTxRegHandle;
 edma_handle_t LPSPI5_EdmaRxRegToRxDataHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpspi5_edma_driver_state")
 cmsis_lpspi_edma_driver_state_t LPSPI5_EdmaDriverState = {
 #else
@@ -2110,7 +2108,7 @@ static ARM_SPI_STATUS LPSPI5_EdmaGetStatus(void)
 
 cmsis_lpspi_handle_t LPSPI5_Handle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpspi5_interrupt_driver_state")
 cmsis_lpspi_interrupt_driver_state_t LPSPI5_InterruptDriverState = {
 #else

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/cmsis_drivers/fsl_lpspi_cmsis.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/cmsis_drivers/fsl_lpspi_cmsis.h

@@ -18,13 +18,13 @@
  * limitations under the License.
  */
 
-
 #ifndef _FSL_LPSPI_CMSISI_H_
 #define _FSL_LPSPI_CMSISI_H_
 
 #include "fsl_common.h"
 #include "RTE_Device.h"
 #include "Driver_SPI.h"
+#include "fsl_lpspi.h"
 #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
 #include "fsl_lpspi_edma.h"
 #endif

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/cmsis_drivers/fsl_lpuart_cmsis.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/cmsis_drivers/fsl_lpuart_cmsis.c

@@ -18,7 +18,6 @@
  * limitations under the License.
  */
 
-
 #include "fsl_lpuart_cmsis.h"
 
 /* Component ID definition, used by tools. */
@@ -26,7 +25,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.lpuart_cmsis"
 #endif
 
-
 /* Re-mapping for LPUART & UART indexing. */
 #if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && FSL_FEATURE_SOC_UART_COUNT
 
@@ -190,7 +188,7 @@
  * ARMCC does not support split the data section automatically, so the driver
  * needs to split the data to separate sections explicitly, to reduce codesize.
  */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 #define ARMCC_SECTION(section_name) __attribute__((section(section_name)))
 #endif
 
@@ -687,7 +685,7 @@ static ARM_USART_STATUS LPUART_DmaGetStatus(cmsis_lpuart_dma_driver_state_t *lpu
     stat.tx_underflow = 0U;
     stat.rx_overflow = (!(!(ksdk_lpuart_status & kLPUART_RxOverrunFlag)));
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    stat.rx_break = (!(!(ksdk_lpuart_status & kLPUART_LinBreakFlag)));
+    stat.rx_break = (!(!(ksdk_lpuart_status & (uint32_t)kLPUART_LinBreakFlag)));
 #else
     stat.rx_break = 0U;
 #endif
@@ -940,7 +938,7 @@ static ARM_USART_STATUS LPUART_EdmaGetStatus(cmsis_lpuart_edma_driver_state_t *l
     stat.tx_underflow = 0U;
     stat.rx_overflow = (!(!(ksdk_lpuart_status & kLPUART_RxOverrunFlag)));
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    stat.rx_break = (!(!(ksdk_lpuart_status & kLPUART_LinBreakFlag)));
+    stat.rx_break = (!(!(ksdk_lpuart_status & (uint32_t)kLPUART_LinBreakFlag)));
 #else
     stat.rx_break = 0U;
 #endif
@@ -1189,7 +1187,7 @@ static ARM_USART_STATUS LPUART_NonBlockingGetStatus(cmsis_lpuart_non_blocking_dr
     stat.tx_underflow = 0U;
     stat.rx_overflow = (!(!(ksdk_lpuart_status & kLPUART_RxOverrunFlag)));
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    stat.rx_break = (!(!(ksdk_lpuart_status & kLPUART_LinBreakFlag)));
+    stat.rx_break = (!(!(ksdk_lpuart_status & (uint32_t)kLPUART_LinBreakFlag)));
 #else
     stat.rx_break = 0U;
 #endif
@@ -1229,7 +1227,7 @@ lpuart_dma_handle_t LPUART0_DmaHandle;
 dma_handle_t LPUART0_DmaRxHandle;
 dma_handle_t LPUART0_DmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart0_dma_driver_state")
 cmsis_lpuart_dma_driver_state_t LPUART0_DmaDriverState = {
 #else
@@ -1308,7 +1306,7 @@ lpuart_edma_handle_t LPUART0_EdmaHandle;
 edma_handle_t LPUART0_EdmaRxHandle;
 edma_handle_t LPUART0_EdmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart0_edma_driver_state")
 cmsis_lpuart_edma_driver_state_t LPUART0_EdmaDriverState = {
 #else
@@ -1383,7 +1381,7 @@ static uint8_t lpuart0_rxRingBuffer[USART_RX_BUFFER_LEN];
 static uint8_t lpuart1_rxRingBuffer[USART_RX_BUFFER_LEN];
 #endif
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart0_non_blocking_driver_state")
 cmsis_lpuart_non_blocking_driver_state_t LPUART0_NonBlockingDriverState = {
 #else
@@ -1541,7 +1539,7 @@ lpuart_dma_handle_t LPUART1_DmaHandle;
 dma_handle_t LPUART1_DmaRxHandle;
 dma_handle_t LPUART1_DmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart1_dma_driver_state")
 cmsis_lpuart_dma_driver_state_t LPUART1_DmaDriverState = {
 #else
@@ -1619,7 +1617,7 @@ lpuart_edma_handle_t LPUART1_EdmaHandle;
 edma_handle_t LPUART1_EdmaRxHandle;
 edma_handle_t LPUART1_EdmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart1_edma_driver_state")
 cmsis_lpuart_edma_driver_state_t LPUART1_EdmaDriverState = {
 #else
@@ -1694,7 +1692,7 @@ static uint8_t lpuart1_rxRingBuffer[USART_RX_BUFFER_LEN];
 static uint8_t lpuart2_rxRingBuffer[USART_RX_BUFFER_LEN];
 #endif
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart1_non_blocking_driver_state")
 cmsis_lpuart_non_blocking_driver_state_t LPUART1_NonBlockingDriverState = {
 #else
@@ -1841,7 +1839,7 @@ lpuart_dma_handle_t LPUART2_DmaHandle;
 dma_handle_t LPUART2_DmaRxHandle;
 dma_handle_t LPUART2_DmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart2_dma_driver_state")
 cmsis_lpuart_dma_driver_state_t LPUART2_DmaDriverState = {
 #else
@@ -1919,7 +1917,7 @@ lpuart_edma_handle_t LPUART2_EdmaHandle;
 edma_handle_t LPUART2_EdmaRxHandle;
 edma_handle_t LPUART2_EdmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart2_edma_driver_state")
 cmsis_lpuart_edma_driver_state_t LPUART2_EdmaDriverState = {
 #else
@@ -1994,7 +1992,7 @@ static uint8_t lpuart2_rxRingBuffer[USART_RX_BUFFER_LEN];
 static uint8_t lpuart3_rxRingBuffer[USART_RX_BUFFER_LEN];
 #endif
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart2_non_blocking_driver_state")
 cmsis_lpuart_non_blocking_driver_state_t LPUART2_NonBlockingDriverState = {
 #else
@@ -2141,7 +2139,7 @@ lpuart_dma_handle_t LPUART3_DmaHandle;
 dma_handle_t LPUART3_DmaRxHandle;
 dma_handle_t LPUART3_DmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart3_dma_driver_state")
 cmsis_lpuart_dma_driver_state_t LPUART3_DmaDriverState = {
 #else
@@ -2219,7 +2217,7 @@ lpuart_edma_handle_t LPUART3_EdmaHandle;
 edma_handle_t LPUART3_EdmaRxHandle;
 edma_handle_t LPUART3_EdmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart3_edma_driver_state")
 cmsis_lpuart_edma_driver_state_t LPUART3_EdmaDriverState = {
 #else
@@ -2294,7 +2292,7 @@ static uint8_t lpuart3_rxRingBuffer[USART_RX_BUFFER_LEN];
 static uint8_t lpuart4_rxRingBuffer[USART_RX_BUFFER_LEN];
 #endif
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart3_non_blocking_driver_state")
 cmsis_lpuart_non_blocking_driver_state_t LPUART3_NonBlockingDriverState = {
 #else
@@ -2441,7 +2439,7 @@ lpuart_dma_handle_t LPUART4_DmaHandle;
 dma_handle_t LPUART4_DmaRxHandle;
 dma_handle_t LPUART4_DmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart4_dma_driver_state")
 cmsis_lpuart_dma_driver_state_t LPUART4_DmaDriverState = {
 #else
@@ -2518,7 +2516,7 @@ lpuart_edma_handle_t LPUART4_EdmaHandle;
 edma_handle_t LPUART4_EdmaRxHandle;
 edma_handle_t LPUART4_EdmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart4_edma_driver_state")
 cmsis_lpuart_edma_driver_state_t LPUART4_EdmaDriverState = {
 #else
@@ -2592,7 +2590,7 @@ static uint8_t lpuart4_rxRingBuffer[USART_RX_BUFFER_LEN];
 static uint8_t lpuart5_rxRingBuffer[USART_RX_BUFFER_LEN];
 #endif
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart4_non_blocking_driver_state")
 cmsis_lpuart_non_blocking_driver_state_t LPUART4_NonBlockingDriverState = {
 #else
@@ -2739,7 +2737,7 @@ lpuart_dma_handle_t LPUART5_DmaHandle;
 dma_handle_t LPUART5_DmaRxHandle;
 dma_handle_t LPUART5_DmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart5_dma_driver_state")
 cmsis_lpuart_dma_driver_state_t LPUART5_DmaDriverState = {
 #else
@@ -2819,7 +2817,7 @@ lpuart_edma_handle_t LPUART5_EdmaHandle;
 edma_handle_t LPUART5_EdmaRxHandle;
 edma_handle_t LPUART5_EdmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart5_edma_driver_state")
 cmsis_lpuart_edma_driver_state_t LPUART5_EdmaDriverState = {
 #else
@@ -2890,7 +2888,7 @@ lpuart_handle_t LPUART5_Handle;
 static uint8_t lpuart5_rxRingBuffer[USART_RX_BUFFER_LEN];
 #endif
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart5_non_blocking_driver_state")
 cmsis_lpuart_non_blocking_driver_state_t LPUART5_NonBlockingDriverState = {
 #else
@@ -3037,7 +3035,7 @@ lpuart_dma_handle_t LPUART6_DmaHandle;
 dma_handle_t LPUART6_DmaRxHandle;
 dma_handle_t LPUART6_DmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart5_dma_driver_state")
 cmsis_lpuart_dma_driver_state_t LPUART6_DmaDriverState = {
 #else
@@ -3117,7 +3115,7 @@ lpuart_edma_handle_t LPUART6_EdmaHandle;
 edma_handle_t LPUART6_EdmaRxHandle;
 edma_handle_t LPUART6_EdmaTxHandle;
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart6_edma_driver_state")
 cmsis_lpuart_edma_driver_state_t LPUART6_EdmaDriverState = {
 #else
@@ -3188,7 +3186,7 @@ lpuart_handle_t LPUART6_Handle;
 static uint8_t lpuart6_rxRingBuffer[USART_RX_BUFFER_LEN];
 #endif
 
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
 ARMCC_SECTION("lpuart6_non_blocking_driver_state")
 cmsis_lpuart_non_blocking_driver_state_t LPUART6_NonBlockingDriverState = {
 #else

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_adc.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_adc.c

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_adc.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -56,8 +29,10 @@ static uint32_t ADC_GetInstance(ADC_Type *base);
 /*! @brief Pointers to ADC bases for each instance. */
 static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to ADC clocks for each instance. */
 static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -80,14 +55,22 @@ static uint32_t ADC_GetInstance(ADC_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initialize the ADC module.
+ *
+ * param base ADC peripheral base address.
+ * param config Pointer to "adc_config_t" structure.
+ */
 void ADC_Init(ADC_Type *base, const adc_config_t *config)
 {
     assert(NULL != config);
 
     uint32_t tmp32;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock. */
     CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     /* ADCx_CFG */
     tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */
     tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) |
@@ -123,16 +106,46 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config)
     base->GC = tmp32;
 }
 
+/*!
+ * brief De-initializes the ADC module.
+ *
+ * param base ADC peripheral base address.
+ */
 void ADC_Deinit(ADC_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock. */
     CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Gets an available pre-defined settings for the converter's configuration.
+ *
+ * This function initializes the converter configuration structure with available settings. The default values are:
+ * code
+ *  config->enableAsynchronousClockOutput = true;
+ *  config->enableOverWrite =               false;
+ *  config->enableContinuousConversion =    false;
+ *  config->enableHighSpeed =               false;
+ *  config->enableLowPower =                false;
+ *  config->enableLongSample =              false;
+ *  config->referenceVoltageSource =        kADC_ReferenceVoltageSourceAlt0;
+ *  config->samplePeriodMode =              kADC_SamplePeriod2or12Clocks;
+ *  config->clockSource =                   kADC_ClockSourceAD;
+ *  config->clockDriver =                   kADC_ClockDriver1;
+ *  config->resolution =                    kADC_Resolution12Bit;
+ * endcode
+ * param base   ADC peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
 void ADC_GetDefaultConfig(adc_config_t *config)
 {
     assert(NULL != config);
 
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     config->enableAsynchronousClockOutput = true;
     config->enableOverWrite = false;
     config->enableContinuousConversion = false;
@@ -146,6 +159,33 @@ void ADC_GetDefaultConfig(adc_config_t *config)
     config->resolution = kADC_Resolution12Bit;
 }
 
+/*!
+ * brief Configures the conversion channel.
+ *
+ * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
+ * configures the channel while the external trigger source helps to trigger the conversion.
+ *
+ * Note that the "Channel Group" has a detailed description.
+ * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
+ * group of status and control registers, one for each conversion. The channel group parameter indicates which group of
+ * registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B
+ * registers. The
+ * channel groups are used in a "ping-pong" approach to control the ADC operation.  At any point, only one of
+ * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and
+ * hardware
+ * trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for
+ * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual
+ * about the
+ * number of SC1n registers (channel groups) specific to this device.  None of the channel groups 1 or greater are used
+ * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
+ * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
+ * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
+ * conversion aborts the current conversion.
+ *
+ * param base          ADC peripheral base address.
+ * param channelGroup  Channel group index.
+ * param config        Pointer to the "adc_channel_config_t" structure for the conversion channel.
+ */
 void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config)
 {
     assert(NULL != config);
@@ -168,6 +208,19 @@ void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_chann
  *  3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC.
  *  4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status.
  */
+/*!
+ * brief  Automates the hardware calibration.
+ *
+ * This auto calibration helps to adjust the plus/minus side gain automatically.
+ * Execute the calibration before using the converter. Note that the software trigger should be used
+ * during calibration.
+ *
+ * param  base ADC peripheral base address.
+ *
+ * return                 Execution status.
+ * retval kStatus_Success Calibration is done successfully.
+ * retval kStatus_Fail    Calibration has failed.
+ */
 status_t ADC_DoAutoCalibration(ADC_Type *base)
 {
     status_t status = kStatus_Success;
@@ -222,6 +275,12 @@ status_t ADC_DoAutoCalibration(ADC_Type *base)
     return status;
 }
 
+/*!
+ * brief Set user defined offset.
+ *
+ * param base   ADC peripheral base address.
+ * param config Pointer to "adc_offest_config_t" structure.
+ */
 void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
 {
     assert(NULL != config);
@@ -236,6 +295,19 @@ void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
     base->OFS = tmp32;
 }
 
+/*!
+ * brief Configures the hardware compare mode.
+ *
+ * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the
+ * result
+ * in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate
+ * reference
+ * manual for more information.
+ *
+ * param base ADC peripheral base address.
+ * param Pointer to "adc_hardware_compare_config_t" structure.
+ *
+ */
 void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config)
 {
     uint32_t tmp32;
@@ -273,6 +345,16 @@ void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_con
     base->CV = tmp32;
 }
 
+/*!
+ * brief Configures the hardware average mode.
+ *
+ * The hardware average mode provides a way to process the conversion result automatically by using hardware. The
+ * multiple
+ * conversion results are accumulated and averaged internally making them easier to read.
+ *
+ * param base ADC peripheral base address.
+ * param mode Setting the hardware average mode. See "adc_hardware_average_mode_t".
+ */
 void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode)
 {
     uint32_t tmp32;
@@ -290,6 +372,12 @@ void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mo
     }
 }
 
+/*!
+ * brief Clears the converter's status falgs.
+ *
+ * param base ADC peripheral base address.
+ * param mask Mask value for the cleared flags. See "adc_status_flags_t".
+ */
 void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
 {
     uint32_t tmp32 = 0;

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_adc.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_ADC_H_
@@ -46,7 +20,7 @@
 * Definitions
 ******************************************************************************/
 /*! @brief ADC driver version */
-#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
 
 /*!
  * @brief Converter's status flags.

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc_etc.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_adc_etc.c

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_adc_etc.h"
@@ -55,9 +29,10 @@ static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base);
  ******************************************************************************/
 /*! @brief Pointers to ADC_ETC bases for each instance. */
 static ADC_ETC_Type *const s_adcetcBases[] = ADC_ETC_BASE_PTRS;
-
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to ADC_ETC clocks for each instance. */
 static const clock_ip_name_t s_adcetcClocks[] = ADC_ETC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -80,6 +55,12 @@ static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base)
 }
 #endif /* ADC_ETC_CLOCKS */
 
+/*!
+* brief Initialize the ADC_ETC module.
+*
+* param base ADC_ETC peripheral base address.
+* param config Pointer to "adc_etc_config_t" structure.
+*/
 void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
 {
     assert(NULL != config);
@@ -119,6 +100,11 @@ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
     base->CTRL = tmp32;
 }
 
+/*!
+* brief De-Initialize the ADC_ETC module.
+*
+* param base ADC_ETC peripheral base address.
+*/
 void ADC_ETC_Deinit(ADC_ETC_Type *base)
 {
     /* Do software reset to clear all logical. */
@@ -132,8 +118,26 @@ void ADC_ETC_Deinit(ADC_ETC_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+* brief Gets an available pre-defined settings for the ADC_ETC's configuration.
+* This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
+* code
+*   config->enableTSCBypass = true;
+*   config->enableTSC0Trigger = false;
+*   config->enableTSC1Trigger = false;
+*   config->TSC0triggerPriority = 0U;
+*   config->TSC1triggerPriority = 0U;
+*   config->clockPreDivider = 0U;
+*   config->XBARtriggerMask = 0U;
+* endCode
+*
+* param config Pointer to "adc_etc_config_t" structure.
+*/
 void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
 {
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     config->enableTSCBypass = true;
     config->enableTSC0Trigger = false;
     config->enableTSC1Trigger = false;
@@ -146,6 +150,13 @@ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
     config->XBARtriggerMask = 0U;
 }
 
+/*!
+* brief Set the external XBAR trigger configuration.
+*
+* param base ADC_ETC peripheral base address.
+* param triggerGroup Trigger group index.
+* param config Pointer to "adc_etc_trigger_config_t" structure.
+*/
 void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config)
 {
     assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
@@ -172,6 +183,16 @@ void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const a
     base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32;
 }
 
+/*!
+* brief Set the external XBAR trigger chain configuration.
+* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
+* configurated.
+*
+* param base ADC_ETC peripheral base address.
+* param triggerGroup Trigger group index. Available number is 0~7.
+* param chainGroup Trigger chain group index. Available number is 0~7.
+* param config Pointer to "adc_etc_trigger_chain_config_t" structure.
+*/
 void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
                                    uint32_t triggerGroup,
                                    uint32_t chainGroup,
@@ -262,6 +283,14 @@ void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
     }
 }
 
+/*!
+* brief Gets the interrupt status flags of external XBAR and TSC triggers.
+*
+* param base ADC_ETC peripheral base address.
+* param sourceIndex trigger source index.
+*
+* return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
+*/
 uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex)
 {
     uint32_t tmp32 = 0U;
@@ -289,6 +318,13 @@ uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_tr
     return tmp32;
 }
 
+/*!
+* brief Clears the ADC_ETC's interrupt status falgs.
+*
+* param base ADC_ETC peripheral base address.
+* param sourceIndex trigger source index.
+* param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
+*/
 void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask)
 {
     if (0U != (mask & kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */
@@ -309,6 +345,16 @@ void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trig
     }
 }
 
+/*!
+* brief Get ADC conversion result from external XBAR sources.
+* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
+* return Trigger0 source's chain1 conversion result.
+*
+* param base ADC_ETC peripheral base address.
+* param triggerGroup Trigger group index. Available number is 0~7.
+* param chainGroup Trigger chain group index. Available number is 0~7.
+* return ADC conversion result value.
+*/
 uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup)
 {
     assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT);

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_adc_etc.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_adc_etc.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_ADC_ETC_H_
@@ -46,7 +20,7 @@
 * Definitions
 ******************************************************************************/
 /*! @brief ADC_ETC driver version */
-#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
 /*! @brief The mask of status flags cleared by writing 1. */
 #define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U
 
@@ -97,8 +71,9 @@ typedef enum _adc_etc_interrupt_enable
 */
 typedef enum _adc_etc_dma_mode_selection
 {
-    kADC_ETC_TrigDMAWithLatchedSignal = 0U,  /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
-    kADC_ETC_TrigDMAWithPulsedSignal = 1U,   /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
+    kADC_ETC_TrigDMAWithLatchedSignal =
+        0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
+    kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
 } adc_etc_dma_mode_selection_t;
 #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
 
@@ -107,21 +82,21 @@ typedef enum _adc_etc_dma_mode_selection
  */
 typedef struct _adc_etc_config
 {
-    bool enableTSCBypass;         /* If bypass TSC, TSC would trigger ADC directly.
-                                     Otherwise TSC would trigger ADC through ADC_ETC. */
-    bool enableTSC0Trigger;       /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
-    bool enableTSC1Trigger;       /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
+    bool enableTSCBypass;   /* If bypass TSC, TSC would trigger ADC directly.
+                               Otherwise TSC would trigger ADC through ADC_ETC. */
+    bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
+    bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
 #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
-    adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */ 
-#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
-    uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
-    uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
-    uint32_t clockPreDivider;     /* Pre-divider for trig delay and interval. Available range is 0-255.
-                                    Clock would be divided by (clockPreDivider+1). */
-    uint32_t XBARtriggerMask;     /* Enable the corresponding trigger source. Available range is trigger0:0x01 to
-                                     trigger7:0x80
-                                     For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is
-                                     enabled. */
+    adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */
+#endif                                    /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
+    uint32_t TSC0triggerPriority;         /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
+    uint32_t TSC1triggerPriority;         /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
+    uint32_t clockPreDivider;             /* Pre-divider for trig delay and interval. Available range is 0-255.
+                                            Clock would be divided by (clockPreDivider+1). */
+    uint32_t XBARtriggerMask; /* Enable the corresponding trigger source. Available range is trigger0:0x01 to
+                                 trigger7:0x80
+                                 For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is
+                                 enabled. */
 } adc_etc_config_t;
 
 /*!

bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_aipstz.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_aipstz.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.aipstz"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * brief Configure the privilege level for master.
+ *
+ * param base    AIPSTZ peripheral base pointer
+ * param master  Masters for AIPSTZ.
+ * param privilegeConfig Configuration is ORed from aipstz_master_privilege_level_t.
+ */
+void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig)
+{
+    uint32_t mask = ((uint32_t)master >> 8) - 1;
+    uint32_t shift = (uint32_t)master & 0xFF;
+    base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift);
+}
+
+/*!
+ * brief Configure the access for peripheral.
+ *
+ * param base    AIPSTZ peripheral base pointer
+ * param master  Peripheral for AIPSTZ.
+ * param accessControl Configuration is ORed from aipstz_peripheral_access_control_t.
+ */
+void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl)
+{
+    volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16));
+    uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1;
+    uint32_t shift = (uint32_t)peripheral & 0xFF;
+
+    *reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift);
+}

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_aipstz.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_aipstz.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_AIPSTZ_H_
 #define _FSL_AIPSTZ_H_

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_aoi.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_aoi.c

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #include "fsl_aoi.h"
 
@@ -38,7 +12,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.aoi"
 #endif
 
-
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -49,9 +22,9 @@ static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS;
 /*! @brief Pointers to aoi clocks for each instance. */
 static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
+       /*******************************************************************************
+        * Prototypes
+        ******************************************************************************/
 /*!
  * @brief Get instance number for AOI module.
  *
@@ -82,6 +55,13 @@ static uint32_t AOI_GetInstance(AOI_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes an AOI instance for operation.
+ *
+ * This function un-gates the AOI clock.
+ *
+ * param base AOI peripheral address.
+ */
 void AOI_Init(AOI_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -90,6 +70,13 @@ void AOI_Init(AOI_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Deinitializes an AOI instance for operation.
+ *
+ * This function shutdowns AOI module.
+ *
+ * param  base AOI peripheral address.
+ */
 void AOI_Deinit(AOI_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -98,6 +85,22 @@ void AOI_Deinit(AOI_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Gets the Boolean evaluation associated.
+ *
+ * This function returns the Boolean evaluation associated.
+ *
+ * Example:
+  code
+    aoi_event_config_t demoEventLogicStruct;
+
+    AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);
+  endcode
+ *
+ * param  base AOI peripheral address.
+ * param  event Index of the event which will be set of type aoi_event_t.
+ * param  config Selected input configuration .
+ */
 void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)
 {
     assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
@@ -132,6 +135,45 @@ void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config
     config->PT3DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT);
 }
 
+/*!
+ * brief Configures an AOI event.
+ *
+ * This function configures an AOI event according
+ * to the aoiEventConfig structure. This function configures all  inputs (A, B, C, and D)
+ * of all  product terms (0, 1, 2, and 3) of a desired event.
+ *
+ * Example:
+  code
+    aoi_event_config_t demoEventLogicStruct;
+
+    demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
+    demoEventLogicStruct.PT0BC = kAOI_InputSignal;
+    demoEventLogicStruct.PT0CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT0DC = kAOI_LogicOne;
+
+    demoEventLogicStruct.PT1AC = kAOI_LogicZero;
+    demoEventLogicStruct.PT1BC = kAOI_LogicOne;
+    demoEventLogicStruct.PT1CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT1DC = kAOI_LogicOne;
+
+    demoEventLogicStruct.PT2AC = kAOI_LogicZero;
+    demoEventLogicStruct.PT2BC = kAOI_LogicOne;
+    demoEventLogicStruct.PT2CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT2DC = kAOI_LogicOne;
+
+    demoEventLogicStruct.PT3AC = kAOI_LogicZero;
+    demoEventLogicStruct.PT3BC = kAOI_LogicOne;
+    demoEventLogicStruct.PT3CC = kAOI_LogicOne;
+    demoEventLogicStruct.PT3DC = kAOI_LogicOne;
+
+    AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);
+  endcode
+ *
+ * param  base AOI peripheral address.
+ * param  event Event which will be configured of type aoi_event_t.
+ * param  eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for
+ * filling out the members of this structure and passing the pointer to this function.
+ */
 void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)
 {
     assert(eventConfig != NULL);

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_aoi.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_aoi.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_AOI_H_
 #define _FSL_AOI_H_

bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_bee.c

@@ -0,0 +1,303 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_bee.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.bee"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void aligned_memcpy(void *dst, const void *src, size_t size)
+{
+    register uint32_t *to32 = (uint32_t *)(uintptr_t)dst;
+    register const uint32_t *from32 = (const uint32_t *)(uintptr_t)src;
+
+    while (size >= sizeof(uint32_t))
+    {
+        *to32 = *from32;
+        size -= sizeof(uint32_t);
+        to32++;
+        from32++;
+    }
+}
+
+/*!
+ * brief Resets BEE module to factory default values.
+ *
+ * This function performs hardware reset of BEE module. Attributes and keys from software for both regions are cleared.
+ *
+ * param base BEE peripheral address.
+ */
+void BEE_Init(BEE_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(kCLOCK_Bee);
+#endif
+
+    base->CTRL = BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK;
+}
+
+/*!
+ * brief Resets BEE module, clears keys for both regions and disables clock to the BEE.
+ *
+ * This function performs hardware reset of BEE module and disables clocks. Attributes and keys from software for both
+ * regions are cleared.
+ *
+ * param base BEE peripheral address.
+ */
+void BEE_Deinit(BEE_Type *base)
+{
+    base->CTRL &=
+        ~(BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK | BEE_CTRL_KEY_VALID_MASK);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_DisableClock(kCLOCK_Bee);
+#endif
+}
+
+/*!
+ * brief Loads default values to the BEE region configuration structure.
+ *
+ * Loads default values to the BEE region configuration structure. The default values are as follows:
+ * code
+ *   config->region0Mode = kBEE_AesCtrMode;
+ *   config->region1Mode = kBEE_AesCtrMode;
+ *   config->region0AddrOffset = 0U;
+ *   config->region1AddrOffset = 0U;
+ *   config->region0SecLevel = kBEE_SecurityLevel3;
+ *   config->region1SecLevel = kBEE_SecurityLevel3;
+ *   config->region1Bot = 0U;
+ *   config->region1Top = 0U;
+ *   config->accessPermission = kBEE_AccessProtDisabled;
+ *   config->endianSwapEn = kBEE_EndianSwapEnabled;
+ * endcode
+ *
+ * param config Configuration structure for BEE peripheral.
+ */
+void BEE_GetDefaultConfig(bee_region_config_t *config)
+{
+    assert(config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->region0Mode = kBEE_AesCtrMode;
+    config->region1Mode = kBEE_AesCtrMode;
+    config->region0AddrOffset = 0U;
+    config->region1AddrOffset = 0U;
+    config->region0SecLevel = kBEE_SecurityLevel3;
+    config->region1SecLevel = kBEE_SecurityLevel3;
+    config->region1Bot = 0U;
+    config->region1Top = 0U;
+    config->accessPermission = kBEE_AccessProtDisabled;
+    config->endianSwapEn = kBEE_EndianSwapEnabled;
+}
+
+/*!
+ * brief Sets BEE configuration.
+ *
+ * This function sets BEE peripheral and BEE region settings accorging to given configuration structure.
+ *
+ * param base BEE peripheral address.
+ * param config Configuration structure for BEE.
+ */
+void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config)
+{
+    uint32_t beeCtrlVal;
+    bool reenable = false;
+
+    /* Wait until BEE is in idle state */
+    while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag))
+    {
+    }
+
+    /* Disable BEE before region configuration in case it is enabled. */
+    if (base->CTRL & BEE_CTRL_BEE_ENABLE_MASK)
+    {
+        BEE_Disable(base);
+        reenable = true;
+    }
+
+    /* Preserve CTRL bit values that are not set by this function */
+    beeCtrlVal = base->CTRL & 0xFFFF0037;
+
+    /* Set variable according to configuration */
+    beeCtrlVal |= BEE_CTRL_AC_PROT_EN(config->accessPermission) | BEE_CTRL_LITTLE_ENDIAN(config->endianSwapEn) |
+                  BEE_CTRL_SECURITY_LEVEL_R0(config->region0SecLevel) | BEE_CTRL_CTRL_AES_MODE_R0(config->region0Mode) |
+                  BEE_CTRL_SECURITY_LEVEL_R1(config->region1SecLevel) | BEE_CTRL_CTRL_AES_MODE_R1(config->region1Mode);
+
+    /* Load values to registers */
+    base->CTRL = beeCtrlVal;
+    base->ADDR_OFFSET0 = config->region0AddrOffset;
+    base->ADDR_OFFSET1 = config->region1AddrOffset;
+    base->REGION1_BOT = config->region1Bot;
+    base->REGION1_TOP = config->region1Top;
+
+    /* Reenable BEE if it was enabled before. */
+    if (reenable)
+    {
+        BEE_Enable(base);
+    }
+}
+
+/*!
+ * brief Loads the AES key for selected region into BEE key registers.
+ *
+ * This function loads given AES key to BEE register for the given region.
+ * The key must be 32-bit aligned and stored in little-endian format.
+ *
+ * Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers.
+ * Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2.
+ *
+ * param base BEE peripheral address.
+ * param region Selection of the BEE region to be configured.
+ * param key AES key (in little-endian format).
+ * param keySize Size of AES key.
+ */
+status_t BEE_SetRegionKey(BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize)
+{
+    bool redisable = false;
+
+    /* Key must be 32-bit aligned */
+    if (((uintptr_t)key & 0x3u) || (keySize != 16))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Wait until BEE is in idle state */
+    while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag))
+    {
+    }
+
+    /* Clear KEY_VALID bit before new key is loaded */
+    base->CTRL &= ~BEE_CTRL_KEY_VALID_MASK;
+
+    /* Write key registers, key is stored in little-endian format in memory */
+    aligned_memcpy((uint32_t *)&base->AES_KEY0_W0, key, keySize);
+
+    /* Enable BEE before key configuration. */
+    if (!(base->CTRL & BEE_CTRL_BEE_ENABLE_MASK))
+    {
+        BEE_Enable(base);
+        redisable = true;
+    }
+
+    if (region == kBEE_Region0)
+    {
+        base->CTRL &= ~BEE_CTRL_KEY_REGION_SEL_MASK;
+    }
+
+    else if (region == kBEE_Region1)
+    {
+        base->CTRL |= BEE_CTRL_KEY_REGION_SEL_MASK;
+    }
+
+    else
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Set KEY_VALID bit to trigger key loading */
+    base->CTRL |= BEE_CTRL_KEY_VALID_MASK;
+    /* Wait until key is ready */
+    while (!(base->CTRL & BEE_CTRL_KEY_VALID_MASK))
+    {
+    }
+
+    /* Redisable BEE if it was disabled before this function call. */
+    if (redisable)
+    {
+        BEE_Disable(base);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Loads the nonce for selected region into BEE nonce registers.
+ *
+ * This function loads given nonce(only AES CTR mode) to BEE register for the given region.
+ * The nonce must be 32-bit aligned and stored in little-endian format.
+ *
+ * param base BEE peripheral address.
+ * param region Selection of the BEE region to be configured.
+ * param nonce AES nonce (in little-endian format).
+ * param nonceSize Size of AES nonce.
+ */
+status_t BEE_SetRegionNonce(BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize)
+{
+    /* Nonce must be 32-bit aligned */
+    if (((uintptr_t)nonce & 0x3u) || (nonceSize != 16))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Wait until BEE is in idle state */
+    while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag))
+    {
+    }
+
+    /* Write nonce registers, nonce is stored in little-endian format in memory */
+    if (region == kBEE_Region0)
+    {
+        aligned_memcpy((uint32_t *)&base->CTR_NONCE0_W0, nonce, nonceSize);
+    }
+
+    else if (region == kBEE_Region1)
+    {
+        aligned_memcpy((uint32_t *)&base->CTR_NONCE1_W0, nonce, nonceSize);
+    }
+
+    else
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Gets the BEE status flags.
+ *
+ * This function returns status of BEE peripheral.
+ *
+ * param base BEE peripheral address.
+ *
+ * return The status flags. This is the logical OR of members of the
+ *         enumeration ::bee_status_flags_t
+ */
+uint32_t BEE_GetStatusFlags(BEE_Type *base)
+{
+    return base->STATUS;
+}
+
+/*!
+ * brief Clears the BEE status flags.
+ *
+ * param base BEE peripheral base address.
+ * param mask The status flags to clear. This is a logical OR of members of the
+ *             enumeration ::bee_status_flags_t
+ */
+void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask)
+{
+    /* w1c */
+    base->STATUS |= mask;
+}

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_bee.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_bee.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
  * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_BEE_H_
@@ -48,15 +22,15 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief BEE driver version. Version 2.0.0.
+/*! @brief BEE driver version. Version 2.0.1.
  *
- * Current version: 2.0.0
+ * Current version: 2.0.1
  *
  * Change log:
- * - Version 2.0.0
+ * - Version 2.0.1
  *   - Initial version
  */
-#define FSL_BEE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+#define FSL_BEE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
 typedef enum _bee_aes_mode
@@ -71,11 +45,25 @@ typedef enum _bee_region
     kBEE_Region1 = 1U  /*!< BEE region 1 */
 } bee_region_t;
 
-typedef enum _bee_region_enable
+typedef enum _bee_ac_prot_enable
 {
-    kBEE_RegionDisabled = 0U, /*!< BEE region disabled */
-    kBEE_RegionEnabled = 1U   /*!< BEE region enabled */
-} bee_region_enable_t;
+    kBEE_AccessProtDisabled = 0U, /*!< BEE access permission control disabled */
+    kBEE_AccessProtEnabled = 1U   /*!< BEE access permission control enabled */
+} bee_ac_prot_enable;
+
+typedef enum _bee_endian_swap_enable
+{
+    kBEE_EndianSwapDisabled = 1U, /*!< BEE endian swap disabled */
+    kBEE_EndianSwapEnabled = 0U   /*!< BEE endian swap enabled */
+} bee_endian_swap_enable;
+
+typedef enum _bee_security_level
+{
+    kBEE_SecurityLevel0 = 0U, /*!< BEE security level 0 */
+    kBEE_SecurityLevel1 = 1U, /*!< BEE security level 1 */
+    kBEE_SecurityLevel2 = 2U, /*!< BEE security level 2 */
+    kBEE_SecurityLevel3 = 3U  /*!< BEE security level 3 */
+} bee_security_level;
 
 typedef enum _bee_status_flags
 {
@@ -91,11 +79,16 @@ typedef enum _bee_status_flags
 /*! @brief BEE region configuration structure. */
 typedef struct _bee_region_config
 {
-    bee_aes_mode_t mode;          /*!< AES mode used for encryption/decryption */
-    uint32_t regionBot;           /*!< Region bottom address */
-    uint32_t regionTop;           /*!< Region top address */
-    uint32_t addrOffset;          /*!< Region address offset */
-    bee_region_enable_t regionEn; /*!< Region enable/disable */
+    bee_aes_mode_t region0Mode;          /*!< AES mode used for encryption/decryption for region 0 */
+    bee_aes_mode_t region1Mode;          /*!< AES mode used for encryption/decryption for region 1 */
+    uint32_t region0AddrOffset;          /*!< Region 0 address offset */
+    uint32_t region1AddrOffset;          /*!< Region 1 address offset */
+    bee_security_level region0SecLevel;  /*!< Region 0 security level */
+    bee_security_level region1SecLevel;  /*!< Region 1 security level */
+    uint32_t region1Bot;                 /*!< Region 1 bottom address */
+    uint32_t region1Top;                 /*!< Region 1 top address */
+    bee_ac_prot_enable accessPermission; /*!< Access permission control enable/disable */
+    bee_endian_swap_enable endianSwapEn; /*!< Endian swap enable/disable */
 } bee_region_config_t;
 
 /*******************************************************************************
@@ -133,7 +126,7 @@ void BEE_Deinit(BEE_Type *base);
  */
 static inline void BEE_Enable(BEE_Type *base)
 {
-    base->CTRL |= BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_KEY_VALID_MASK;
+    base->CTRL |= BEE_CTRL_BEE_ENABLE_MASK;
 }
 
 /*!
@@ -145,7 +138,7 @@ static inline void BEE_Enable(BEE_Type *base)
  */
 static inline void BEE_Disable(BEE_Type *base)
 {
-    base->CTRL &= ~BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_KEY_VALID_MASK;
+    base->CTRL &= ~BEE_CTRL_BEE_ENABLE_MASK;
 }
 
 /*!
@@ -153,45 +146,62 @@ static inline void BEE_Disable(BEE_Type *base)
  *
  * Loads default values to the BEE region configuration structure. The default values are as follows:
  * @code
- *   config->mode = kBEE_AesCbcMode;
- *   config->regionBot = 0U;
- *   config->regionTop = 0U;
- *   config->addrOffset = 0xF0000000U;
- *   config->regionEn = kBEE_RegionDisabled;
+ *   config->region0Mode = kBEE_AesCtrMode;
+ *   config->region1Mode = kBEE_AesCtrMode;
+ *   config->region0AddrOffset = 0U;
+ *   config->region1AddrOffset = 0U;
+ *   config->region0SecLevel = kBEE_SecurityLevel3;
+ *   config->region1SecLevel = kBEE_SecurityLevel3;
+ *   config->region1Bot = 0U;
+ *   config->region1Top = 0U;
+ *   config->accessPermission = kBEE_AccessProtDisabled;
+ *   config->endianSwapEn = kBEE_EndianSwapEnabled;
  * @endcode
  *
- * @param config Configuration structure for BEE region.
+ * @param config Configuration structure for BEE peripheral.
  */
 void BEE_GetDefaultConfig(bee_region_config_t *config);
 
 /*!
- * @brief Sets BEE region configuration.
+ * @brief Sets BEE configuration.
  *
- * This function sets BEE region settings accorging to given configuration structure.
+ * This function sets BEE peripheral and BEE region settings accorging to given configuration structure.
  *
  * @param base BEE peripheral address.
- * @param region Selection of the BEE region to be configured.
- * @param config Configuration structure for BEE region.
+ * @param config Configuration structure for BEE.
  */
-status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_region_config_t *config);
+void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config);
 
 /*!
- * @brief Loads the AES key and nonce for selected region into BEE key registers.
+ * @brief Loads the AES key for selected region into BEE key registers.
  *
- * This function loads given AES key and nonce(only AES CTR mode) to BEE register for the given region.
+ * This function loads given AES key to BEE register for the given region.
+ * The key must be 32-bit aligned and stored in little-endian format.
  *
  * Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers.
  * Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2.
  *
  * @param base BEE peripheral address.
  * @param region Selection of the BEE region to be configured.
- * @param key AES key.
+ * @param key AES key (in little-endian format).
  * @param keySize Size of AES key.
- * @param nonce AES nonce.
- * @param nonceSize Size of AES nonce.
  */
 status_t BEE_SetRegionKey(
-    BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize, const uint8_t *nonce, size_t nonceSize);
+    BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize);
+
+/*!
+ * @brief Loads the nonce for selected region into BEE nonce registers.
+ *
+ * This function loads given nonce(only AES CTR mode) to BEE register for the given region.
+ * The nonce must be 32-bit aligned and stored in little-endian format.
+ *
+ * @param base BEE peripheral address.
+ * @param region Selection of the BEE region to be configured.
+ * @param nonce AES nonce (in little-endian format).
+ * @param nonceSize Size of AES nonce.
+ */
+status_t BEE_SetRegionNonce(
+    BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize);
 
 /*!
  * @brief Gets the BEE status flags.
@@ -214,18 +224,6 @@ uint32_t BEE_GetStatusFlags(BEE_Type *base);
  */
 void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask);
 
-/*!
- * @brief Computes offset to be set for specifed memory location.
- *
- * This function calculates offset that must be set for BEE region to access physical memory location.
- *
- * @param addressMemory Address of physical memory location.
- */
-static inline uint32_t BEE_GetOffset(uint32_t addressMemory)
-{
-    return (addressMemory >> 16);
-}
-
 #if defined(__cplusplus)
 }
 #endif

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_cache.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cache.c

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_cache.h"
@@ -50,10 +24,10 @@
 #define L2CACHE_SMALLWAYS_NUM 8U
 #define L2CACHE_1KBCOVERTOB 1024U
 #define L2CACHE_SAMLLWAYS_SIZE 16U
-#define L2CACHE_LOCKDOWN_REGNUM 8  /*!< Lock down register numbers.*/
-/*******************************************************************************
-* Prototypes
-******************************************************************************/
+#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/
+                                  /*******************************************************************************
+                                  * Prototypes
+                                  ******************************************************************************/
 /*!
  * @brief Set for all ways and waiting for the operation finished.
  *  This is provided for all the background operations.
@@ -192,10 +166,15 @@ static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way)
     *size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB;
 }
 
+/*!
+ * brief Initializes the level 2 cache controller module.
+ *
+ * param config Pointer to configuration structure. See "l2cache_config_t".
+ */
 void L2CACHE_Init(l2cache_config_t *config)
 {
-    assert (config);
-    
+    assert(config);
+
     uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */
     uint8_t count;
     uint32_t auxReg = 0;
@@ -206,7 +185,7 @@ void L2CACHE_Init(l2cache_config_t *config)
     if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK)
     {
         L2CACHE_Disable();
-    }    
+    }
 
     /* Unlock all entries. */
     if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
@@ -214,20 +193,18 @@ void L2CACHE_Init(l2cache_config_t *config)
         waysNum = 0xFFFFU;
     }
 
-    for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count ++)
+    for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++)
     {
-        L2CACHE_LockdownByWayEnable(count, waysNum, false);    
+        L2CACHE_LockdownByWayEnable(count, waysNum, false);
     }
-    
+
     /* Set the ways and way-size etc. */
     auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) |
-            L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | 
-            L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
-            L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
-            L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
-            L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
-            L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) |
-            L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
+             L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
+             L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
+             L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
+             L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
+             L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
     L2CACHEC->REG1_AUX_CONTROL = auxReg;
 
     /* Set the tag/data ram latency. */
@@ -235,23 +212,44 @@ void L2CACHE_Init(l2cache_config_t *config)
     {
         uint32_t data = 0;
         /* Tag latency. */
-        data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)|
-            L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)|
-            L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate)|
-            L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
+        data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
+               L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
+               L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) |
+               L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
         L2CACHEC->REG1_TAG_RAM_CONTROL = data;
         /* Data latency. */
-        data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)|
-            L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)|
-            L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate)|
-            L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
+        data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
+               L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
+               L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) |
+               L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
         L2CACHEC->REG1_DATA_RAM_CONTROL = data;
     }
 }
 
+/*!
+ * brief Gets an available default settings for the cache controller.
+ *
+ * This function initializes the cache controller configuration structure with default settings.
+ * The default values are:
+ * code
+ *   config->waysNum = kL2CACHE_8ways;
+ *   config->waySize = kL2CACHE_32KbSize;
+ *   config->repacePolicy = kL2CACHE_Roundrobin;
+ *   config->lateConfig = NULL;
+ *   config->istrPrefetchEnable = false;
+ *   config->dataPrefetchEnable = false;
+ *   config->nsLockdownEnable = false;
+ *   config->writeAlloc = kL2CACHE_UseAwcache;
+ * endcode
+ * param config Pointer to the configuration structure.
+ */
 void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
 {
     assert(config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
                       L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
     uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
@@ -265,9 +263,15 @@ void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
     config->istrPrefetchEnable = false;
     config->dataPrefetchEnable = false;
     config->nsLockdownEnable = false;
-    config->writeAlloc = kL2CACHE_UseAwcache; 
+    config->writeAlloc = kL2CACHE_UseAwcache;
 }
 
+/*!
+ * brief Enables the level 2 cache controller.
+ * This function enables the cache controller. Must be written using a secure access.
+ * If write with a Non-secure access will cause a DECERR response.
+ *
+ */
 void L2CACHE_Enable(void)
 {
     /* Invalidate first. */
@@ -276,6 +280,12 @@ void L2CACHE_Enable(void)
     L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK;
 }
 
+/*!
+ * brief Disables the level 2 cache controller.
+ * This function disables the cache controller. Must be written using a secure access.
+ * If write with a Non-secure access will cause a DECERR response.
+ *
+ */
 void L2CACHE_Disable(void)
 {
     /* First CleanInvalidate all enties in the cache. */
@@ -286,6 +296,11 @@ void L2CACHE_Disable(void)
     __DSB();
 }
 
+/*!
+ * brief Invalidates the Level 2 cache.
+ * This function invalidates all entries in cache.
+ *
+ */
 void L2CACHE_Invalidate(void)
 {
     /* Invalidate all entries in cache. */
@@ -294,6 +309,11 @@ void L2CACHE_Invalidate(void)
     L2CACHEC->REG7_CACHE_SYNC = 0;
 }
 
+/*!
+ * brief Cleans the level 2 cache controller.
+ * This function cleans all entries in the level 2 cache controller.
+ *
+ */
 void L2CACHE_Clean(void)
 {
     /* Clean all entries of the cache. */
@@ -302,6 +322,11 @@ void L2CACHE_Clean(void)
     L2CACHEC->REG7_CACHE_SYNC = 0;
 }
 
+/*!
+ * brief Cleans and invalidates the level 2 cache controller.
+ * This function cleans and invalidates all entries in the level 2 cache controller.
+ *
+ */
 void L2CACHE_CleanInvalidate(void)
 {
     /* Clean all entries of the cache. */
@@ -310,6 +335,17 @@ void L2CACHE_CleanInvalidate(void)
     L2CACHEC->REG7_CACHE_SYNC = 0;
 }
 
+/*!
+ * brief Invalidates the Level 2 cache lines in the range of two physical addresses.
+ * This function invalidates all cache lines between two physical addresses.
+ *
+ * param address  The start address of the memory to be invalidated.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
 {
     uint32_t endAddr = address + size_byte;
@@ -326,6 +362,17 @@ void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
     L2CACHEC->REG7_CACHE_SYNC = 0;
 }
 
+/*!
+ * brief Cleans the Level 2 cache lines in the range of two physical addresses.
+ * This function cleans all cache lines between two physical addresses.
+ *
+ * param address  The start address of the memory to be cleaned.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
 {
     uint32_t num_ways = 0;
@@ -353,6 +400,17 @@ void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
     L2CACHEC->REG7_CACHE_SYNC = 0;
 }
 
+/*!
+ * brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
+ * This function cleans and invalidates all cache lines between two physical addresses.
+ *
+ * param address  The start address of the memory to be cleaned and invalidated.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
 {
     uint32_t num_ways = 0;
@@ -380,6 +438,23 @@ void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
     L2CACHEC->REG7_CACHE_SYNC = 0;
 }
 
+/*!
+ * brief Enables or disables to lock down the data and instruction by way.
+ * This function locks down the cached instruction/data by way and prevent the adresses from
+ * being allocated and prevent dara from being evicted out of the level 2 cache.
+ * But the normal cache maintenance operations that invalidate, clean or clean
+ * and validate cache contents affect the locked-down cache lines as normal.
+ *
+ * param masterId  The master id, range from 0 ~ 7.
+ * param mask  The ways to be enabled or disabled to lockdown.
+ *               each bit in value is related to each way of the cache. for example:
+ *               value: bit 0  ------ way 0.
+ *               value: bit 1  ------ way 1.
+ *               --------------------------
+ *               value: bit 15 ------ way 15.
+ * Note: please make sure the value setting is align with your supported ways.
+ * param enable  True enable the lockdown, false to disable the lockdown.
+ */
 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
 {
     uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
@@ -407,12 +482,22 @@ void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
         L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
     }
 }
-#endif  /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 
+/*!
+ * brief Invalidate cortex-m7 L1 instruction cache by range.
+ *
+ * param address  The start address of the memory to be invalidated.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L1 I-cache line size if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
 {
 #if (__DCACHE_PRESENT == 1U)
-    uint32_t addr = address & (uint32_t)~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1);
+    uint32_t addr = address & (uint32_t) ~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1);
     int32_t size = size_byte + address - addr;
     uint32_t linesize = 32U;
 
@@ -425,9 +510,21 @@ void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
     }
     __DSB();
     __ISB();
-#endif    
+#endif
 }
 
+/*!
+ * brief Invalidates all instruction caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be invalidated.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
 {
 #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
@@ -436,9 +533,21 @@ void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
 #endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
 #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 
-   L1CACHE_InvalidateICacheByRange(address, size_byte);
+    L1CACHE_InvalidateICacheByRange(address, size_byte);
 }
 
+/*!
+ * brief Invalidates all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be invalidated.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
 {
 #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
@@ -449,6 +558,18 @@ void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
     L1CACHE_InvalidateDCacheByRange(address, size_byte);
 }
 
+/*!
+ * brief Cleans all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be cleaned.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
 {
     L1CACHE_CleanDCacheByRange(address, size_byte);
@@ -459,6 +580,18 @@ void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
 #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 }
 
+/*!
+ * brief Cleans and Invalidates all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be cleaned and invalidated.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
 void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
 {
     L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cache.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cache.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef _FSL_CACHE_H_
 #define _FSL_CACHE_H_

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_clock.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_clock.c

@@ -1,34 +1,8 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_clock.h"
@@ -36,15 +10,47 @@
 #ifndef FSL_COMPONENT_ID
 #define FSL_COMPONENT_ID "platform.drivers.clock"
 #endif
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to
+achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected
+in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */
+#if __FPU_USED
+
+#if ((defined(__ICCARM__)) || (defined(__GNUC__)))
+
+#if (__ARMVFP__ >= __ARMFPV5__) && \
+    (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/
+typedef double clock_64b_t;
+#else
+typedef uint64_t clock_64b_t;
+#endif
+
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+
+#if defined __TARGET_FPU_FPV5_D16
+typedef double clock_64b_t;
+#else
+typedef uint64_t clock_64b_t;
+#endif
+
+#else
+typedef uint64_t clock_64b_t;
+#endif
+
+#else
+typedef uint64_t clock_64b_t;
+#endif
 
 /*******************************************************************************
  * Variables
  ******************************************************************************/
 
 /* External XTAL (OSC) clock frequency. */
-uint32_t g_xtalFreq;
+volatile uint32_t g_xtalFreq;
 /* External RTC XTAL clock frequency. */
-uint32_t g_rtcXtalFreq;
+volatile uint32_t g_rtcXtalFreq;
 
 /*******************************************************************************
  * Prototypes
@@ -127,6 +133,20 @@ static uint32_t CLOCK_GetPeriphClkFreq(void)
     return freq;
 }
 
+/*!
+ * brief Initialize the external 24MHz clock.
+ *
+ * This function supports two modes:
+ * 1. Use external crystal oscillator.
+ * 2. Bypass the external crystal oscillator, using input source clock directly.
+ *
+ * After this function, please call ref CLOCK_SetXtal0Freq to inform clock driver
+ * the external clock frequency.
+ *
+ * param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
+ * note This device does not support bypass external crystal oscillator, so
+ * the input parameter should always be false.
+ */
 void CLOCK_InitExternalClk(bool bypassXtalOsc)
 {
     /* This device does not support bypass XTAL OSC. */
@@ -143,11 +163,26 @@ void CLOCK_InitExternalClk(bool bypassXtalOsc)
     CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK;
 }
 
+/*!
+ * brief Deinitialize the external 24MHz clock.
+ *
+ * This function disables the external 24MHz clock.
+ *
+ * After this function, please call ref CLOCK_SetXtal0Freq to set external clock
+ * frequency to 0.
+ */
 void CLOCK_DeinitExternalClk(void)
 {
     CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */
 }
 
+/*!
+ * brief Switch the OSC.
+ *
+ * This function switches the OSC source for SoC.
+ *
+ * param osc   OSC source to switch to.
+ */
 void CLOCK_SwitchOsc(clock_osc_t osc)
 {
     if (osc == kCLOCK_RcOsc)
@@ -156,16 +191,110 @@ void CLOCK_SwitchOsc(clock_osc_t osc)
         XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK;
 }
 
+/*!
+ * brief Initialize the RC oscillator 24MHz clock.
+ */
 void CLOCK_InitRcOsc24M(void)
 {
     XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK;
 }
 
+/*!
+ * brief Power down the RCOSC 24M clock.
+ */
 void CLOCK_DeinitRcOsc24M(void)
 {
     XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK;
 }
 
+/*!
+ * brief Gets the AHB clock frequency.
+ *
+ * return  The AHB clock frequency value in hertz.
+ */
+uint32_t CLOCK_GetAhbFreq(void)
+{
+    return CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
+}
+
+/*!
+ * brief Gets the SEMC clock frequency.
+ *
+ * return  The SEMC clock frequency value in hertz.
+ */
+uint32_t CLOCK_GetSemcFreq(void)
+{
+    uint32_t freq;
+
+    /* SEMC alternative clock ---> SEMC Clock */
+    if (CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK)
+    {
+        /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */
+        if (CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
+        {
+            freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1);
+        }
+        /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */
+        else
+        {
+            freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2);
+        }
+    }
+    /* Periph_clk ---> SEMC Clock */
+    else
+    {
+        freq = CLOCK_GetPeriphClkFreq();
+    }
+
+    freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U);
+
+    return freq;
+}
+
+/*!
+ * brief Gets the IPG clock frequency.
+ *
+ * return  The IPG clock frequency value in hertz.
+ */
+uint32_t CLOCK_GetIpgFreq(void)
+{
+    return CLOCK_GetAhbFreq() / (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U);
+}
+
+/*!
+ * brief Gets the PER clock frequency.
+ *
+ * return  The PER clock frequency value in hertz.
+ */
+uint32_t CLOCK_GetPerClkFreq(void)
+{
+    uint32_t freq;
+
+    /* Osc_clk ---> PER Clock*/
+    if (CCM->CSCMR1 & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
+    {
+        freq = CLOCK_GetOscFreq();
+    }
+    /* Periph_clk ---> AHB Clock ---> IPG Clock ---> PER Clock */
+    else
+    {
+        freq = CLOCK_GetFreq(kCLOCK_IpgClk);
+    }
+
+    freq /= (((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_PODF_MASK) >> CCM_CSCMR1_PERCLK_PODF_SHIFT) + 1U);
+
+    return freq;
+}
+
+/*!
+ * brief Gets the clock frequency for a specific clock name.
+ *
+ * This function checks the current clock configurations and then calculates
+ * the clock frequency for a specific clock name defined in clock_name_t.
+ *
+ * param clockName Clock names defined in clock_name_t
+ * return Clock frequency value in hertz
+ */
 uint32_t CLOCK_GetFreq(clock_name_t name)
 {
     uint32_t freq;
@@ -173,42 +302,20 @@ uint32_t CLOCK_GetFreq(clock_name_t name)
     switch (name)
     {
         case kCLOCK_CpuClk:
-        /* Periph_clk ---> AHB Clock */
         case kCLOCK_AhbClk:
-            /* Periph_clk ---> AHB Clock */
-            freq =
-                CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
+            freq = CLOCK_GetAhbFreq();
             break;
 
         case kCLOCK_SemcClk:
-            /* SEMC alternative clock ---> SEMC Clock */
-            if (CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK)
-            {
-                /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */
-                if (CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
-                {
-                    freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1);
-                }
-                /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */
-                else
-                {
-                    freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2);
-                }
-            }
-            /* Periph_clk ---> SEMC Clock */
-            else
-            {
-                freq = CLOCK_GetPeriphClkFreq();
-            }
-
-            freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U);
+            freq = CLOCK_GetSemcFreq();
             break;
 
         case kCLOCK_IpgClk:
-            /* Periph_clk ---> AHB Clock ---> IPG Clock */
-            freq =
-                CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
-            freq /= (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U);
+            freq = CLOCK_GetIpgFreq();
+            break;
+
+        case kCLOCK_PerClk:
+            freq = CLOCK_GetPerClkFreq();
             break;
 
         case kCLOCK_OscClk:
@@ -273,6 +380,17 @@ uint32_t CLOCK_GetFreq(clock_name_t name)
     return freq;
 }
 
+/*! brief Enable USB HS clock.
+ *
+ * This function only enables the access to USB HS prepheral, upper layer
+ * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
+ * clock to use USB HS.
+ *
+ * param src  USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused.
+ * param freq USB HS does not care about the clock source, so this parameter is ignored.
+ * retval true The clock is set successfully.
+ * retval false The clock source is invalid to get proper USB HS clock.
+ */
 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
 {
     CCM->CCGR6 |= CCM_CCGR6_CG0_MASK;
@@ -287,6 +405,17 @@ bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
     return true;
 }
 
+/*! brief Enable USB HS clock.
+ *
+ * This function only enables the access to USB HS prepheral, upper layer
+ * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
+ * clock to use USB HS.
+ *
+ * param src  USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused.
+ * param freq USB HS does not care about the clock source, so this parameter is ignored.
+ * retval true The clock is set successfully.
+ * retval false The clock source is invalid to get proper USB HS clock.
+ */
 bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
 {
     CCM->CCGR6 |= CCM_CCGR6_CG0_MASK;
@@ -301,12 +430,21 @@ bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
     return true;
 }
 
+/*! brief Enable USB HS PHY PLL clock.
+ *
+ * This function enables the internal 480MHz USB PHY PLL clock.
+ *
+ * param src  USB HS PHY PLL clock source.
+ * param freq The frequency specified by src.
+ * retval true The clock is set successfully.
+ * retval false The clock source is invalid to get proper USB HS clock.
+ */
 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
 {
     const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
     if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
     {
-        CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; 
+        CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
     }
     else
     {
@@ -321,12 +459,23 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
     return true;
 }
 
+/*! brief Disable USB HS PHY PLL clock.
+ *
+ * This function disables USB HS PHY PLL clock.
+ */
 void CLOCK_DisableUsbhs0PhyPllClock(void)
 {
-    CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; 
+    CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
     USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
 }
 
+/*!
+ * brief Initialize the ARM PLL.
+ *
+ * This function initialize the ARM PLL with specific settings
+ *
+ * param config   configuration to set to PLL.
+ */
 void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)
 {
     /* Bypass PLL first */
@@ -345,11 +494,21 @@ void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)
     CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK;
 }
 
+/*!
+ * brief De-initialize the ARM PLL.
+ */
 void CLOCK_DeinitArmPll(void)
 {
     CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK;
 }
 
+/*!
+ * brief Initialize the System PLL.
+ *
+ * This function initializes the System PLL with specific settings
+ *
+ * param config Configuration to set to PLL.
+ */
 void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
 {
     /* Bypass PLL first */
@@ -360,6 +519,15 @@ void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
         (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) |
         CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider);
 
+    /* Initialize the fractional mode */
+    CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator);
+    CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator);
+
+    /* Initialize the spread spectrum mode */
+    CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) |
+                             CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) |
+                             CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop);
+
     while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0)
     {
     }
@@ -368,11 +536,21 @@ void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
     CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK;
 }
 
+/*!
+ * brief De-initialize the System PLL.
+ */
 void CLOCK_DeinitSysPll(void)
 {
     CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK;
 }
 
+/*!
+ * brief Initialize the USB1 PLL.
+ *
+ * This function initializes the USB1 PLL with specific settings
+ *
+ * param config Configuration to set to PLL.
+ */
 void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config)
 {
     /* Bypass PLL first */
@@ -391,11 +569,21 @@ void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config)
     CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK;
 }
 
+/*!
+ * brief Deinitialize the USB1 PLL.
+ */
 void CLOCK_DeinitUsb1Pll(void)
 {
     CCM_ANALOG->PLL_USB1 = 0U;
 }
 
+/*!
+ * brief Initialize the USB2 PLL.
+ *
+ * This function initializes the USB2 PLL with specific settings
+ *
+ * param config Configuration to set to PLL.
+ */
 void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config)
 {
     /* Bypass PLL first */
@@ -414,11 +602,21 @@ void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config)
     CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_BYPASS_MASK;
 }
 
+/*!
+ * brief Deinitialize the USB2 PLL.
+ */
 void CLOCK_DeinitUsb2Pll(void)
 {
     CCM_ANALOG->PLL_USB2 = 0U;
 }
 
+/*!
+ * brief Initializes the Audio PLL.
+ *
+ * This function initializes the Audio PLL with specific settings
+ *
+ * param config Configuration to set to PLL.
+ */
 void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
 {
     uint32_t pllAudio;
@@ -491,11 +689,21 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
     CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
 }
 
+/*!
+ * brief De-initialize the Audio PLL.
+ */
 void CLOCK_DeinitAudioPll(void)
 {
     CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK;
 }
 
+/*!
+ * brief Initialize the video PLL.
+ *
+ * This function configures the Video PLL with specific settings
+ *
+ * param config   configuration to set to PLL.
+ */
 void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)
 {
     uint32_t pllVideo;
@@ -567,11 +775,21 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)
     CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
 }
 
+/*!
+ * brief De-initialize the Video PLL.
+ */
 void CLOCK_DeinitVideoPll(void)
 {
     CCM_ANALOG->PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK;
 }
 
+/*!
+ * brief Initialize the ENET PLL.
+ *
+ * This function initializes the ENET PLL with specific settings.
+ *
+ * param config Configuration to set to PLL.
+ */
 void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
 {
     uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider);
@@ -602,16 +820,29 @@ void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
     CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK;
 }
 
+/*!
+ * brief Deinitialize the ENET PLL.
+ *
+ * This function disables the ENET PLL.
+ */
 void CLOCK_DeinitEnetPll(void)
 {
     CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK;
 }
 
+/*!
+ * brief Get current PLL output frequency.
+ *
+ * This function get current output frequency of specific PLL
+ *
+ * param pll   pll name to get frequency.
+ * return The PLL output frequency in hertz.
+ */
 uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
 {
     uint32_t freq;
     uint32_t divSelect;
-    uint64_t freqTmp;
+    clock_64b_t freqTmp;
 
     const uint32_t enetRefClkFreq[] = {
         25000000U,  /* 25M */
@@ -644,8 +875,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
             break;
         case kCLOCK_PllSys:
             /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
-            freqTmp =
-                ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
+            freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) /
+                      ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM));
 
             if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
             {
@@ -668,8 +899,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
             divSelect =
                 (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT;
 
-            freqTmp =
-                ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
+            freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) /
+                      ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
 
             freq = freq * divSelect + (uint32_t)freqTmp;
 
@@ -723,8 +954,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
             divSelect =
                 (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT;
 
-            freqTmp =
-                ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_VIDEO_DENOM));
+            freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) /
+                      ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM));
 
             freq = freq * divSelect + (uint32_t)freqTmp;
 
@@ -794,6 +1025,16 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
     return freq;
 }
 
+/*!
+ * brief Initialize the System PLL PFD.
+ *
+ * This function initializes the System PLL PFD. During new value setting,
+ * the clock output is disabled to prevent glitch.
+ *
+ * param pfd Which PFD clock to enable.
+ * param pfdFrac The PFD FRAC value.
+ * note It is recommended that PFD settings are kept between 12-35.
+ */
 void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac)
 {
     uint32_t pfdIndex = (uint32_t)pfd;
@@ -809,11 +1050,28 @@ void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac)
     CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8 * pfdIndex));
 }
 
+/*!
+ * brief De-initialize the System PLL PFD.
+ *
+ * This function disables the System PLL PFD.
+ *
+ * param pfd Which PFD clock to disable.
+ */
 void CLOCK_DeinitSysPfd(clock_pfd_t pfd)
 {
     CCM_ANALOG->PFD_528 |= CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfd);
 }
 
+/*!
+ * brief Initialize the USB1 PLL PFD.
+ *
+ * This function initializes the USB1 PLL PFD. During new value setting,
+ * the clock output is disabled to prevent glitch.
+ *
+ * param pfd Which PFD clock to enable.
+ * param pfdFrac The PFD FRAC value.
+ * note It is recommended that PFD settings are kept between 12-35.
+ */
 void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac)
 {
     uint32_t pfdIndex = (uint32_t)pfd;
@@ -829,11 +1087,26 @@ void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac)
     CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8 * pfdIndex));
 }
 
+/*!
+ * brief De-initialize the USB1 PLL PFD.
+ *
+ * This function disables the USB1 PLL PFD.
+ *
+ * param pfd Which PFD clock to disable.
+ */
 void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd)
 {
     CCM_ANALOG->PFD_480 |= CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfd);
 }
 
+/*!
+ * brief Get current System PLL PFD output frequency.
+ *
+ * This function get current output frequency of specific System PLL PFD
+ *
+ * param pfd   pfd name to get frequency.
+ * return The PFD output frequency in hertz.
+ */
 uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd)
 {
     uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
@@ -865,6 +1138,14 @@ uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd)
     return freq;
 }
 
+/*!
+ * brief Get current USB1 PLL PFD output frequency.
+ *
+ * This function get current output frequency of specific USB1 PLL PFD
+ *
+ * param pfd   pfd name to get frequency.
+ * return The PFD output frequency in hertz.
+ */
 uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd)
 {
     uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
@@ -896,6 +1177,15 @@ uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd)
     return freq;
 }
 
+/*! brief Enable USB HS PHY PLL clock.
+ *
+ * This function enables the internal 480MHz USB PHY PLL clock.
+ *
+ * param src  USB HS PHY PLL clock source.
+ * param freq The frequency specified by src.
+ * retval true The clock is set successfully.
+ * retval false The clock source is invalid to get proper USB HS clock.
+ */
 bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
 {
     const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
@@ -910,8 +1200,12 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
     return true;
 }
 
+/*! brief Disable USB HS PHY PLL clock.
+ *
+ * This function disables USB HS PHY PLL clock.
+ */
 void CLOCK_DisableUsbhs1PhyPllClock(void)
 {
-    CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; 
+    CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK;
     USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
 }

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_clock.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_clock.h

@@ -1,34 +1,8 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- * that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_CLOCK_H_
@@ -49,7 +23,7 @@
  *
  * When set to 0, peripheral drivers will enable clock in initialize function
  * and disable clock in de-initialize function. When set to 1, peripheral
- * driver will not control the clock, application could contol the clock out of
+ * driver will not control the clock, application could control the clock out of
  * the driver.
  *
  * @note All drivers share this feature switcher. If it is set to 1, application
@@ -65,8 +39,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief CLOCK driver version 2.1.2. */
-#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*! @brief CLOCK driver version 2.1.5. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
 
 /* analog pll definition */
 #define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
@@ -74,9 +48,9 @@
 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
 
 /*@}*/
-#define CCM_TUPLE(reg, shift, mask, busyShift)                                                                     \
-    ((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | \
-     ((busyShift) << 26U))
+#define CCM_TUPLE(reg, shift, mask, busyShift)                               \
+    (int)((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | \
+          ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
 #define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))
 #define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)
 #define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))
@@ -108,14 +82,14 @@
  * CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver.
  * @endcode
  */
-extern uint32_t g_xtalFreq;
+extern volatile uint32_t g_xtalFreq;
 
 /*! @brief External RTC XTAL (32K OSC) clock frequency.
  *
  * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
  * function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
  */
-extern uint32_t g_rtcXtalFreq;
+extern volatile uint32_t g_rtcXtalFreq;
 
 /* For compatible with other platforms */
 #define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
@@ -394,31 +368,32 @@ typedef enum _clock_name
     kCLOCK_AhbClk = 0x1U,  /*!< AHB clock */
     kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */
     kCLOCK_IpgClk = 0x3U,  /*!< IPG clock */
+    kCLOCK_PerClk = 0x4U,  /*!< PER clock */
 
-    kCLOCK_OscClk = 0x4U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
-    kCLOCK_RtcClk = 0x5U, /*!< RTC clock. (RTCCLK) */
+    kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
+    kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */
 
-    kCLOCK_ArmPllClk = 0x6U, /*!< ARMPLLCLK. */
+    kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */
 
-    kCLOCK_Usb1PllClk = 0x7U,     /*!< USB1PLLCLK. */
-    kCLOCK_Usb1PllPfd0Clk = 0x8U, /*!< USB1PLLPDF0CLK. */
-    kCLOCK_Usb1PllPfd1Clk = 0x9U, /*!< USB1PLLPFD1CLK. */
-    kCLOCK_Usb1PllPfd2Clk = 0xAU, /*!< USB1PLLPFD2CLK. */
-    kCLOCK_Usb1PllPfd3Clk = 0xBU, /*!< USB1PLLPFD3CLK. */
+    kCLOCK_Usb1PllClk = 0x8U,     /*!< USB1PLLCLK. */
+    kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */
+    kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */
+    kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */
+    kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */
 
-    kCLOCK_Usb2PllClk = 0xCU, /*!< USB2PLLCLK. */
+    kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */
 
-    kCLOCK_SysPllClk = 0xDU,      /*!< SYSPLLCLK. */
-    kCLOCK_SysPllPfd0Clk = 0xEU,  /*!< SYSPLLPDF0CLK. */
-    kCLOCK_SysPllPfd1Clk = 0xFU,  /*!< SYSPLLPFD1CLK. */
-    kCLOCK_SysPllPfd2Clk = 0x10U, /*!< SYSPLLPFD2CLK. */
-    kCLOCK_SysPllPfd3Clk = 0x11U, /*!< SYSPLLPFD3CLK. */
+    kCLOCK_SysPllClk = 0xEU,      /*!< SYSPLLCLK. */
+    kCLOCK_SysPllPfd0Clk = 0xFU,  /*!< SYSPLLPDF0CLK. */
+    kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */
+    kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */
+    kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */
 
-    kCLOCK_EnetPll0Clk = 0x12U, /*!< Enet PLLCLK ref_enetpll0. */
-    kCLOCK_EnetPll1Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll1. */
+    kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */
+    kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */
 
-    kCLOCK_AudioPllClk = 0x14U, /*!< Audio PLLCLK. */
-    kCLOCK_VideoPllClk = 0x15U, /*!< Video PLLCLK. */
+    kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */
+    kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */
 } clock_name_t;
 
 #define kCLOCK_CoreSysClk kCLOCK_CpuClk             /*!< For compatible with other platforms without CCM. */
@@ -778,8 +753,8 @@ typedef enum _clock_div
 /*! @brief USB clock source definition. */
 typedef enum _clock_usb_src
 {
-    kCLOCK_Usb480M = 0,                /*!< Use 480M.      */
-    kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not
+    kCLOCK_Usb480M = 0,                     /*!< Use 480M.      */
+    kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
                                             care the clock source. */
 } clock_usb_src_t;
 
@@ -822,6 +797,9 @@ typedef struct _clock_sys_pll_config
     uint32_t numerator;   /*!< 30 bit numerator of fractional loop divider.*/
     uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
     uint8_t src;          /*!< Pll clock source, reference _clock_pll_clk_src */
+    uint16_t ss_stop;     /*!< Stop value to get frequency change. */
+    uint8_t ss_enable;    /*!< Enable spread spectrum modulation */
+    uint16_t ss_step;     /*!< Step value to get frequency change step. */
 
 } clock_sys_pll_config_t;
 
@@ -1031,6 +1009,34 @@ static inline uint32_t CLOCK_GetOscFreq(void)
     return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq;
 }
 
+/*!
+ * @brief Gets the AHB clock frequency.
+ *
+ * @return  The AHB clock frequency value in hertz.
+ */
+uint32_t CLOCK_GetAhbFreq(void);
+
+/*!
+ * @brief Gets the SEMC clock frequency.
+ *
+ * @return  The SEMC clock frequency value in hertz.
+ */
+uint32_t CLOCK_GetSemcFreq(void);
+
+/*!
+ * @brief Gets the IPG clock frequency.
+ *
+ * @return  The IPG clock frequency value in hertz.
+ */
+uint32_t CLOCK_GetIpgFreq(void);
+
+/*!
+ * @brief Gets the PER clock frequency.
+ *
+ * @return  The PER clock frequency value in hertz.
+ */
+uint32_t CLOCK_GetPerClkFreq(void);
+
 /*!
  * @brief Gets the clock frequency for a specific clock name.
  *
@@ -1133,7 +1139,6 @@ void CLOCK_InitRcOsc24M(void);
 void CLOCK_DeinitRcOsc24M(void);
 /* @} */
 
-
 /*! @brief Enable USB HS clock.
  *
  * This function only enables the access to USB HS prepheral, upper layer

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_cmp.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cmp.c

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_cmp.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.cmp"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -81,6 +54,19 @@ static uint32_t CMP_GetInstance(CMP_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes the CMP.
+ *
+ * This function initializes the CMP module. The operations included are as follows.
+ * - Enabling the clock for CMP module.
+ * - Configuring the comparator.
+ * - Enabling the CMP module.
+ * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for
+ * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP.
+ *
+ * param base   CMP peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
 void CMP_Init(CMP_Type *base, const cmp_config_t *config)
 {
     assert(NULL != config);
@@ -132,6 +118,19 @@ void CMP_Init(CMP_Type *base, const cmp_config_t *config)
     CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */
 }
 
+/*!
+ * brief De-initializes the CMP module.
+ *
+ * This function de-initializes the CMP module. The operations included are as follows.
+ * - Disabling the CMP module.
+ * - Disabling the clock for CMP module.
+ *
+ * This function disables the clock for the CMP.
+ * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the
+ * clock for the CMP, ensure that all the CMP instances are not used.
+ *
+ * param base CMP peripheral base address.
+ */
 void CMP_Deinit(CMP_Type *base)
 {
     /* Disable the CMP module. */
@@ -143,10 +142,28 @@ void CMP_Deinit(CMP_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+* brief Initializes the CMP user configuration structure.
+*
+* This function initializes the user configuration structure to these default values.
+* code
+*   config->enableCmp           = true;
+*   config->hysteresisMode      = kCMP_HysteresisLevel0;
+*   config->enableHighSpeed     = false;
+*   config->enableInvertOutput  = false;
+*   config->useUnfilteredOutput = false;
+*   config->enablePinOut        = false;
+*   config->enableTriggerMode   = false;
+* endcode
+* param config Pointer to the configuration structure.
+*/
 void CMP_GetDefaultConfig(cmp_config_t *config)
 {
     assert(NULL != config);
 
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     config->enableCmp = true; /* Enable the CMP module after initialization. */
     config->hysteresisMode = kCMP_HysteresisLevel0;
     config->enableHighSpeed = false;
@@ -158,6 +175,17 @@ void CMP_GetDefaultConfig(cmp_config_t *config)
 #endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
 }
 
+/*!
+ * brief  Sets the input channels for the comparator.
+ *
+ * This function sets the input channels for the comparator.
+ * Note that two input channels cannot be set the same way in the application. When the user selects the same input
+ * from the analog mux to the positive and negative port, the comparator is disabled automatically.
+ *
+ * param  base            CMP peripheral base address.
+ * param  positiveChannel Positive side input channel number. Available range is 0-7.
+ * param  negativeChannel Negative side input channel number. Available range is 0-7.
+ */
 void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel)
 {
     uint8_t tmp8 = base->MUXCR;
@@ -168,6 +196,17 @@ void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negat
 }
 
 #if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
+/*!
+ * brief Enables/disables the DMA request for rising/falling events.
+ *
+ * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
+ * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from
+ * the CMP
+ * if the DMA is disabled.
+ *
+ * param base CMP peripheral base address.
+ * param enable Enables or disables the feature.
+ */
 void CMP_EnableDMA(CMP_Type *base, bool enable)
 {
     uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
@@ -184,6 +223,12 @@ void CMP_EnableDMA(CMP_Type *base, bool enable)
 }
 #endif /* FSL_FEATURE_CMP_HAS_DMA */
 
+/*!
+ * brief  Configures the filter.
+ *
+ * param  base   CMP peripheral base address.
+ * param  config Pointer to the configuration structure.
+ */
 void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
 {
     assert(NULL != config);
@@ -209,6 +254,12 @@ void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
     base->FPR = CMP_FPR_FILT_PER(config->filterPeriod);
 }
 
+/*!
+ * brief Configures the internal DAC.
+ *
+ * param base   CMP peripheral base address.
+ * param config Pointer to the configuration structure. "NULL" disables the feature.
+ */
 void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
 {
     uint8_t tmp8 = 0U;
@@ -230,6 +281,12 @@ void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
     base->DACCR = tmp8;
 }
 
+/*!
+ * brief Enables the interrupts.
+ *
+ * param base    CMP peripheral base address.
+ * param mask    Mask value for interrupts. See "_cmp_interrupt_enable".
+ */
 void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
 {
     uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
@@ -245,6 +302,12 @@ void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
     base->SCR = tmp8;
 }
 
+/*!
+ * brief Disables the interrupts.
+ *
+ * param base    CMP peripheral base address.
+ * param mask    Mask value for interrupts. See "_cmp_interrupt_enable".
+ */
 void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
 {
     uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
@@ -260,6 +323,13 @@ void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
     base->SCR = tmp8;
 }
 
+/*!
+ * brief  Gets the status flags.
+ *
+ * param  base     CMP peripheral base address.
+ *
+ * return          Mask value for the asserted flags. See "_cmp_status_flags".
+ */
 uint32_t CMP_GetStatusFlags(CMP_Type *base)
 {
     uint32_t ret32 = 0U;
@@ -279,6 +349,12 @@ uint32_t CMP_GetStatusFlags(CMP_Type *base)
     return ret32;
 }
 
+/*!
+ * brief Clears the status flags.
+ *
+ * param base     CMP peripheral base address.
+ * param mask     Mask value for the flags. See "_cmp_status_flags".
+ */
 void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)
 {
     uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_cmp.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_cmp.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_CMP_H_

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_common.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_common.c

@@ -1,45 +1,19 @@
 /*
-* The Clear BSD License
 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016 NXP
+ * Copyright 2016-2018 NXP
 * All rights reserved.
 *
-* 
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted (subject to the limitations in the disclaimer below) provided
-*  that the following conditions are met:
 *
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of the copyright holder nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* SPDX-License-Identifier: BSD-3-Clause
 */
 
 #include "fsl_common.h"
-#define SDK_MEM_MAGIC_NUMBER   12345U
+#define SDK_MEM_MAGIC_NUMBER 12345U
 
 typedef struct _mem_align_control_block
 {
-    uint16_t    identifier;     /*!< Identifier for the memory control block. */
-    uint16_t    offset;         /*!< offset from aligned adress to real address */
+    uint16_t identifier; /*!< Identifier for the memory control block. */
+    uint16_t offset;     /*!< offset from aligned address to real address */
 } mem_align_cb_t;
 
 /* Component ID definition, used by tools. */
@@ -47,13 +21,12 @@ typedef struct _mem_align_control_block
 #define FSL_COMPONENT_ID "platform.drivers.common"
 #endif
 
-
 #ifndef __GIC_PRIO_BITS
 #if defined(ENABLE_RAM_VECTOR_TABLE)
 uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
 {
 /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
     extern uint32_t Image$$VECTOR_ROM$$Base[];
     extern uint32_t Image$$VECTOR_RAM$$Base[];
     extern uint32_t Image$$RW_m_data$$Base[];
@@ -70,7 +43,7 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
     extern uint32_t __VECTOR_RAM[];
     extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
     uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) */
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
     uint32_t n;
     uint32_t ret;
     uint32_t irqMaskValue;
@@ -104,30 +77,22 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
 #endif /* ENABLE_RAM_VECTOR_TABLE. */
 #endif /* __GIC_PRIO_BITS. */
 
-#ifndef QN908XC_SERIES
 #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
 
 void EnableDeepSleepIRQ(IRQn_Type interrupt)
 {
     uint32_t intNumber = (uint32_t)interrupt;
 
-#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
     {
-        SYSCON->STARTERP1 = 1u << intNumber;
+        index++;
+        intNumber -= 32u;
     }
-#else
-    {
-        uint32_t index = 0;
-
-        while (intNumber >= 32u)
-        {
-            index++;
-            intNumber -= 32u;
-        }
 
-        SYSCON->STARTERSET[index] = 1u << intNumber;
-    }
-#endif                    /* FSL_FEATURE_STARTER_DISCONTINUOUS */
+    SYSCON->STARTERSET[index] = 1u << intNumber;
     EnableIRQ(interrupt); /* also enable interrupt at NVIC */
 }
 
@@ -136,28 +101,19 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt)
     uint32_t intNumber = (uint32_t)interrupt;
 
     DisableIRQ(interrupt); /* also disable interrupt at NVIC */
-#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
     {
-        SYSCON->STARTERP1 &= ~(1u << intNumber);
+        index++;
+        intNumber -= 32u;
     }
-#else
-    {
-        uint32_t index = 0;
 
-        while (intNumber >= 32u)
-        {
-            index++;
-            intNumber -= 32u;
-        }
-
-        SYSCON->STARTERCLR[index] = 1u << intNumber;
-    }
-#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
+    SYSCON->STARTERCLR[index] = 1u << intNumber;
 }
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
 #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
 
-#endif /* QN908XC_SERIES */
-
 void *SDK_Malloc(size_t size, size_t alignbytes)
 {
     mem_align_cb_t *p_cb = NULL;
@@ -189,4 +145,3 @@ void SDK_Free(void *ptr)
 
     free((void *)((uint32_t)ptr - p_cb->offset));
 }
-

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_common.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_common.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
  * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_COMMON_H_
@@ -64,8 +38,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief common driver version 2.0.0. */
-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief common driver version 2.0.1. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
 /* Debug console type definition. */
@@ -142,15 +116,39 @@ enum _status_groups
     kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */
     kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */
     kStatusGroup_MMDC = 71,                   /*!< Group number for MMDC status codes. */
-    kStatusGroup_MICFIL = 72,                 /*!< Group number for MIC status codes. */
+    kStatusGroup_PDM = 72,                    /*!< Group number for MIC status codes. */
     kStatusGroup_SDMA = 73,                   /*!< Group number for SDMA status codes. */
     kStatusGroup_ICS = 74,                    /*!< Group number for ICS status codes. */
     kStatusGroup_SPDIF = 75,                  /*!< Group number for SPDIF status codes. */
     kStatusGroup_LPC_MINISPI = 76,            /*!< Group number for LPC_MINISPI status codes. */
+    kStatusGroup_HASHCRYPT = 77,              /*!< Group number for Hashcrypt status codes */
+    kStatusGroup_LPC_SPI_SSP = 78,            /*!< Group number for LPC_SPI_SSP status codes. */
+    kStatusGroup_LPC_I2C_1 = 97,              /*!< Group number for LPC_I2C_1 status codes. */
     kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
     kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
-    kStatusGroup_SEMC = 100,                   /*!< Group number for SEMC status codes. */    
+    kStatusGroup_SEMC = 100,                  /*!< Group number for SEMC status codes. */    
     kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
+    kStatusGroup_IAP = 102,                   /*!< Group number for IAP status codes */
+
+    kStatusGroup_HAL_GPIO = 121,              /*!< Group number for HAL GPIO status codes. */
+    kStatusGroup_HAL_UART = 122,              /*!< Group number for HAL UART status codes. */
+    kStatusGroup_HAL_TIMER = 123,             /*!< Group number for HAL TIMER status codes. */
+    kStatusGroup_HAL_SPI = 124,               /*!< Group number for HAL SPI status codes. */
+    kStatusGroup_HAL_I2C = 125,               /*!< Group number for HAL I2C status codes. */
+    kStatusGroup_HAL_FLASH = 126,             /*!< Group number for HAL FLASH status codes. */
+    kStatusGroup_HAL_PWM = 127,               /*!< Group number for HAL PWM status codes. */
+    kStatusGroup_HAL_RNG = 128,               /*!< Group number for HAL RNG status codes. */
+    kStatusGroup_TIMERMANAGER = 135,          /*!< Group number for TiMER MANAGER status codes. */
+    kStatusGroup_SERIALMANAGER = 136,         /*!< Group number for SERIAL MANAGER status codes. */
+    kStatusGroup_LED = 137,                   /*!< Group number for LED status codes. */
+    kStatusGroup_BUTTON = 138,                /*!< Group number for BUTTON status codes. */
+    kStatusGroup_EXTERN_EEPROM = 139,         /*!< Group number for EXTERN EEPROM status codes. */
+    kStatusGroup_SHELL = 140,                 /*!< Group number for SHELL status codes. */
+    kStatusGroup_MEM_MANAGER = 141,           /*!< Group number for MEM MANAGER status codes. */
+    kStatusGroup_LIST = 142,                  /*!< Group number for List status codes. */
+    kStatusGroup_OSA = 143,                   /*!< Group number for OSA status codes. */
+    kStatusGroup_COMMON_TASK = 144,           /*!< Group number for Common task status codes. */
+    kStatusGroup_MSG = 145,                   /*!< Group number for messaging status codes. */
 };
 
 /*! @brief Generic status return codes. */
@@ -249,16 +247,16 @@ _Pragma("diag_suppress=Pm120")
 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
 #define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
 #endif
-#elif defined(__ARMCC_VERSION)
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
 /*! Macro to define a variable with alignbytes alignment */
-#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
 /*! Macro to define a variable with L1 d-cache line size alignment */
 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
 #endif
 /*! Macro to define a variable with L2 cache line size alignment */
 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
 #endif
 #elif defined(__GNUC__)
 /*! Macro to define a variable with alignbytes alignment */
@@ -295,7 +293,7 @@ _Pragma("diag_suppress=Pm120")
  */
 /* @{ */
 #if (defined(__ICCARM__))
-#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
 #define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
 #define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
@@ -306,25 +304,25 @@ _Pragma("diag_suppress=Pm120")
 #define AT_NONCACHEABLE_SECTION_INIT(var) var
 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
 #endif
-#elif(defined(__ARMCC_VERSION))
-#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
 #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
-    __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
+    __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
 #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
-    __attribute__((section("NonCacheable.init"))) __align(alignbytes) var
+    __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
 #else
 #define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
 #define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
 #endif
 #elif(defined(__GNUC__))
 /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
  * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
  */
-#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
 #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
 #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
     __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
@@ -352,7 +350,7 @@ _Pragma("diag_suppress=Pm120")
 #if (defined(__ICCARM__))
 #define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
 #define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
-#elif(defined(__ARMCC_VERSION))
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
 #define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
 #define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
 #elif(defined(__GNUC__))
@@ -365,7 +363,7 @@ _Pragma("diag_suppress=Pm120")
 #if (defined(__ICCARM__))
 #define AT_QUICKACCESS_SECTION_CODE(func) func
 #define AT_QUICKACCESS_SECTION_DATA(func) func
-#elif(defined(__ARMCC_VERSION))
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
 #define AT_QUICKACCESS_SECTION_CODE(func) func
 #define AT_QUICKACCESS_SECTION_DATA(func) func
 #elif(defined(__GNUC__))
@@ -377,6 +375,17 @@ _Pragma("diag_suppress=Pm120")
 #endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
 /* @} */
 
+/*! @name Ram Function */
+#if (defined(__ICCARM__))
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#elif(defined(__GNUC__))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+/* @} */
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -488,10 +497,10 @@ _Pragma("diag_suppress=Pm120")
     }
 
     /*!
-     * @brief Enaable the global IRQ
+     * @brief Enable the global IRQ
      *
      * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
-     * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+     * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
      * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
      *
      * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
@@ -516,7 +525,7 @@ _Pragma("diag_suppress=Pm120")
      */
     uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
 #endif /* ENABLE_RAM_VECTOR_TABLE. */
-
+		
 #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
     /*!
      * @brief Enable specific interrupt for wake-up from deep-sleep mode.
@@ -527,7 +536,7 @@ _Pragma("diag_suppress=Pm120")
      * those clocks (significantly increasing power consumption in the reduced power mode),
      * making these wake-ups possible.
      *
-     * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
+     * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
      *
      * @param interrupt The IRQ number.
      */
@@ -542,7 +551,7 @@ _Pragma("diag_suppress=Pm120")
      * those clocks (significantly increasing power consumption in the reduced power mode),
      * making these wake-ups possible.
      *
-     * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
+     * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
      *
      * @param interrupt The IRQ number.
      */

bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_csi.c

@@ -0,0 +1,1312 @@
+/*
+ * Copyright (c) 2017-2018, NXP Semiconductors, Inc.
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_csi.h"
+#if CSI_DRIVER_FRAG_MODE
+#include "fsl_cache.h"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.csi"
+#endif
+
+/* Two frame buffer loaded to CSI register at most. */
+#define CSI_MAX_ACTIVE_FRAME_NUM 2
+
+/* CSI driver only support RGB565 and YUV422 in fragment mode, 2 bytes per pixel. */
+#define CSI_FRAG_INPUT_BYTES_PER_PIXEL 2
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the instance from the base address
+ *
+ * @param base CSI peripheral base address
+ *
+ * @return The CSI module instance
+ */
+static uint32_t CSI_GetInstance(CSI_Type *base);
+
+#if !CSI_DRIVER_FRAG_MODE
+/*!
+ * @brief Get the delta value of two index in queue.
+ *
+ * @param startIdx Start index.
+ * @param endIdx End index.
+ *
+ * @return The delta between startIdx and endIdx in queue.
+ */
+static uint32_t CSI_TransferGetQueueDelta(uint32_t startIdx, uint32_t endIdx);
+
+/*!
+ * @brief Increase a index value in queue.
+ *
+ * This function increases the index value in the queue, if the index is out of
+ * the queue range, it is reset to 0.
+ *
+ * @param idx The index value to increase.
+ *
+ * @return The index value after increase.
+ */
+static uint32_t CSI_TransferIncreaseQueueIdx(uint32_t idx);
+
+/*!
+ * @brief Get the empty frame buffer count in queue.
+ *
+ * @param base CSI peripheral base address
+ * @param handle Pointer to CSI driver handle.
+ *
+ * @return Number of the empty frame buffer count in queue.
+ */
+static uint32_t CSI_TransferGetEmptyBufferCount(CSI_Type *base, csi_handle_t *handle);
+
+/*!
+ * @brief Load one empty frame buffer in queue to CSI module.
+ *
+ * Load one empty frame in queue to CSI module, this function could only be called
+ * when there is empty frame buffer in queue.
+ *
+ * @param base CSI peripheral base address
+ * @param handle Pointer to CSI driver handle.
+ */
+static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle);
+
+/* Typedef for interrupt handler. */
+typedef void (*csi_isr_t)(CSI_Type *base, csi_handle_t *handle);
+
+#else
+
+/* Typedef for interrupt handler to work in fragment mode. */
+typedef void (*csi_isr_t)(CSI_Type *base, csi_frag_handle_t *handle);
+#endif /* CSI_DRIVER_FRAG_MODE */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to CSI bases for each instance. */
+static CSI_Type *const s_csiBases[] = CSI_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to CSI clocks for each CSI submodule. */
+static const clock_ip_name_t s_csiClocks[] = CSI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/* Array for the CSI driver handle. */
+#if !CSI_DRIVER_FRAG_MODE
+static csi_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)];
+#else
+static csi_frag_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)];
+#endif
+
+/* Array of CSI IRQ number. */
+static const IRQn_Type s_csiIRQ[] = CSI_IRQS;
+
+/* CSI ISR for transactional APIs. */
+static csi_isr_t s_csiIsr;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t CSI_GetInstance(CSI_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_csiBases); instance++)
+    {
+        if (s_csiBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_csiBases));
+
+    return instance;
+}
+
+#if !CSI_DRIVER_FRAG_MODE
+static uint32_t CSI_TransferGetQueueDelta(uint32_t startIdx, uint32_t endIdx)
+{
+    if (endIdx >= startIdx)
+    {
+        return endIdx - startIdx;
+    }
+    else
+    {
+        return startIdx + CSI_DRIVER_ACTUAL_QUEUE_SIZE - endIdx;
+    }
+}
+
+static uint32_t CSI_TransferIncreaseQueueIdx(uint32_t idx)
+{
+    uint32_t ret;
+
+    /*
+     * Here not use the method:
+     * ret = (idx+1) % CSI_DRIVER_ACTUAL_QUEUE_SIZE;
+     *
+     * Because the mod function might be slow.
+     */
+
+    ret = idx + 1;
+
+    if (ret >= CSI_DRIVER_ACTUAL_QUEUE_SIZE)
+    {
+        ret = 0;
+    }
+
+    return ret;
+}
+
+static uint32_t CSI_TransferGetEmptyBufferCount(CSI_Type *base, csi_handle_t *handle)
+{
+    return CSI_TransferGetQueueDelta(handle->queueDrvReadIdx, handle->queueUserWriteIdx);
+}
+
+static void CSI_TransferLoadBufferToDevice(CSI_Type *base, csi_handle_t *handle)
+{
+    /* Load the frame buffer address to CSI register. */
+    CSI_SetRxBufferAddr(base, handle->nextBufferIdx, handle->frameBufferQueue[handle->queueDrvReadIdx]);
+
+    handle->queueDrvReadIdx = CSI_TransferIncreaseQueueIdx(handle->queueDrvReadIdx);
+    handle->activeBufferNum++;
+
+    /* There are two CSI buffers, so could use XOR to get the next index. */
+    handle->nextBufferIdx ^= 1U;
+}
+#endif /* CSI_DRIVER_FRAG_MODE */
+
+/*!
+ * brief Initialize the CSI.
+ *
+ * This function enables the CSI peripheral clock, and resets the CSI registers.
+ *
+ * param base CSI peripheral base address.
+ * param config Pointer to the configuration structure.
+ *
+ * retval kStatus_Success Initialize successfully.
+ * retval kStatus_InvalidArgument Initialize failed because of invalid argument.
+ */
+status_t CSI_Init(CSI_Type *base, const csi_config_t *config)
+{
+    assert(config);
+    uint32_t reg;
+    uint32_t imgWidth_Bytes;
+
+    imgWidth_Bytes = config->width * config->bytesPerPixel;
+
+    /* The image width and frame buffer pitch should be multiple of 8-bytes. */
+    if ((imgWidth_Bytes & 0x07) | ((uint32_t)config->linePitch_Bytes & 0x07))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance = CSI_GetInstance(base);
+    CLOCK_EnableClock(s_csiClocks[instance]);
+#endif
+
+    CSI_Reset(base);
+
+    /* Configure CSICR1. CSICR1 has been reset to the default value, so could write it directly. */
+    reg = ((uint32_t)config->workMode) | config->polarityFlags | CSI_CSICR1_FCC_MASK;
+
+    if (config->useExtVsync)
+    {
+        reg |= CSI_CSICR1_EXT_VSYNC_MASK;
+    }
+
+    base->CSICR1 = reg;
+
+    /*
+     * Generally, CSIIMAG_PARA[IMAGE_WIDTH] indicates how many data bus cycles per line.
+     * One special case is when receiving 24-bit pixels through 8-bit data bus, and
+     * CSICR3[ZERO_PACK_EN] is enabled, in this case, the CSIIMAG_PARA[IMAGE_WIDTH]
+     * should be set to the pixel number per line.
+     *
+     * Currently the CSI driver only support 8-bit data bus, so generally the
+     * CSIIMAG_PARA[IMAGE_WIDTH] is bytes number per line. When the CSICR3[ZERO_PACK_EN]
+     * is enabled, CSIIMAG_PARA[IMAGE_WIDTH] is pixel number per line.
+     *
+     * NOTE: The CSIIMAG_PARA[IMAGE_WIDTH] setting code should be updated if the
+     * driver is upgraded to support other data bus width.
+     */
+    if (4U == config->bytesPerPixel)
+    {
+        /* Enable zero pack. */
+        base->CSICR3 |= CSI_CSICR3_ZERO_PACK_EN_MASK;
+        /* Image parameter. */
+        base->CSIIMAG_PARA = ((uint32_t)(config->width) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT) |
+                             ((uint32_t)(config->height) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT);
+    }
+    else
+    {
+        /* Image parameter. */
+        base->CSIIMAG_PARA = ((uint32_t)(imgWidth_Bytes) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT) |
+                             ((uint32_t)(config->height) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT);
+    }
+
+    /* The CSI frame buffer bus is 8-byte width. */
+    base->CSIFBUF_PARA = (uint32_t)((config->linePitch_Bytes - imgWidth_Bytes) / 8U)
+                         << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT;
+
+    /* Enable auto ECC. */
+    base->CSICR3 |= CSI_CSICR3_ECC_AUTO_EN_MASK;
+
+    /*
+     * For better performance.
+     * The DMA burst size could be set to 16 * 8 byte, 8 * 8 byte, or 4 * 8 byte,
+     * choose the best burst size based on bytes per line.
+     */
+    if (!(imgWidth_Bytes % (8 * 16)))
+    {
+        base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(3U);
+        base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((2U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
+    }
+    else if (!(imgWidth_Bytes % (8 * 8)))
+    {
+        base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(2U);
+        base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((1U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
+    }
+    else
+    {
+        base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(1U);
+        base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((0U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
+    }
+
+    CSI_ReflashFifoDma(base, kCSI_RxFifo);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief De-initialize the CSI.
+ *
+ * This function disables the CSI peripheral clock.
+ *
+ * param base CSI peripheral base address.
+ */
+void CSI_Deinit(CSI_Type *base)
+{
+    /* Disable transfer first. */
+    CSI_Stop(base);
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance = CSI_GetInstance(base);
+    CLOCK_DisableClock(s_csiClocks[instance]);
+#endif
+}
+
+/*!
+ * brief Reset the CSI.
+ *
+ * This function resets the CSI peripheral registers to default status.
+ *
+ * param base CSI peripheral base address.
+ */
+void CSI_Reset(CSI_Type *base)
+{
+    uint32_t csisr;
+
+    /* Disable transfer first. */
+    CSI_Stop(base);
+
+    /* Disable DMA request. */
+    base->CSICR3 = 0U;
+
+    /* Reset the fame count. */
+    base->CSICR3 |= CSI_CSICR3_FRMCNT_RST_MASK;
+    while (base->CSICR3 & CSI_CSICR3_FRMCNT_RST_MASK)
+    {
+    }
+
+    /* Clear the RX FIFO. */
+    CSI_ClearFifo(base, kCSI_AllFifo);
+
+    /* Reflash DMA. */
+    CSI_ReflashFifoDma(base, kCSI_AllFifo);
+
+    /* Clear the status. */
+    csisr = base->CSISR;
+    base->CSISR = csisr;
+
+    /* Set the control registers to default value. */
+    base->CSICR1 = CSI_CSICR1_HSYNC_POL_MASK | CSI_CSICR1_EXT_VSYNC_MASK;
+    base->CSICR2 = 0U;
+    base->CSICR3 = 0U;
+#if defined(CSI_CSICR18_CSI_LCDIF_BUFFER_LINES)
+    base->CSICR18 = CSI_CSICR18_AHB_HPROT(0x0DU) | CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(0x02U);
+#else
+    base->CSICR18 = CSI_CSICR18_AHB_HPROT(0x0DU);
+#endif
+    base->CSIFBUF_PARA = 0U;
+    base->CSIIMAG_PARA = 0U;
+}
+
+/*!
+ * brief Get the default configuration for to initialize the CSI.
+ *
+ * The default configuration value is:
+ *
+ * code
+    config->width = 320U;
+    config->height = 240U;
+    config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge;
+    config->bytesPerPixel = 2U;
+    config->linePitch_Bytes = 320U * 2U;
+    config->workMode = kCSI_GatedClockMode;
+    config->dataBus = kCSI_DataBus8Bit;
+    config->useExtVsync = true;
+   endcode
+ *
+ * param config Pointer to the CSI configuration.
+ */
+void CSI_GetDefaultConfig(csi_config_t *config)
+{
+    assert(config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    config->width = 320U;
+    config->height = 240U;
+    config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge;
+    config->bytesPerPixel = 2U;
+    config->linePitch_Bytes = 320U * 2U;
+    config->workMode = kCSI_GatedClockMode;
+    config->dataBus = kCSI_DataBus8Bit;
+    config->useExtVsync = true;
+}
+
+/*!
+ * brief Set the RX frame buffer address.
+ *
+ * param base CSI peripheral base address.
+ * param index Buffer index.
+ * param addr Frame buffer address to set.
+ */
+void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr)
+{
+    if (index)
+    {
+        base->CSIDMASA_FB2 = addr;
+    }
+    else
+    {
+        base->CSIDMASA_FB1 = addr;
+    }
+}
+
+/*!
+ * brief Clear the CSI FIFO.
+ *
+ * This function clears the CSI FIFO.
+ *
+ * param base CSI peripheral base address.
+ * param fifo The FIFO to clear.
+ */
+void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo)
+{
+    uint32_t cr1;
+    uint32_t mask = 0U;
+
+    /* The FIFO could only be cleared when CSICR1[FCC] = 0, so first clear the FCC. */
+    cr1 = base->CSICR1;
+    base->CSICR1 = (cr1 & ~CSI_CSICR1_FCC_MASK);
+
+    if ((uint32_t)fifo & (uint32_t)kCSI_RxFifo)
+    {
+        mask |= CSI_CSICR1_CLR_RXFIFO_MASK;
+    }
+
+    if ((uint32_t)fifo & (uint32_t)kCSI_StatFifo)
+    {
+        mask |= CSI_CSICR1_CLR_STATFIFO_MASK;
+    }
+
+    base->CSICR1 = (cr1 & ~CSI_CSICR1_FCC_MASK) | mask;
+
+    /* Wait clear completed. */
+    while (base->CSICR1 & mask)
+    {
+    }
+
+    /* Recover the FCC. */
+    base->CSICR1 = cr1;
+}
+
+/*!
+ * brief Reflash the CSI FIFO DMA.
+ *
+ * This function reflashes the CSI FIFO DMA.
+ *
+ * For RXFIFO, there are two frame buffers. When the CSI module started, it saves
+ * the frames to frame buffer 0 then frame buffer 1, the two buffers will be
+ * written by turns. After reflash DMA using this function, the CSI is reset to
+ * save frame to buffer 0.
+ *
+ * param base CSI peripheral base address.
+ * param fifo The FIFO DMA to reflash.
+ */
+void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo)
+{
+    uint32_t cr3 = 0U;
+
+    if ((uint32_t)fifo & (uint32_t)kCSI_RxFifo)
+    {
+        cr3 |= CSI_CSICR3_DMA_REFLASH_RFF_MASK;
+    }
+
+    if ((uint32_t)fifo & (uint32_t)kCSI_StatFifo)
+    {
+        cr3 |= CSI_CSICR3_DMA_REFLASH_SFF_MASK;
+    }
+
+    base->CSICR3 |= cr3;
+
+    /* Wait clear completed. */
+    while (base->CSICR3 & cr3)
+    {
+    }
+}
+
+/*!
+ * brief Enable or disable the CSI FIFO DMA request.
+ *
+ * param base CSI peripheral base address.
+ * param fifo The FIFO DMA reques to enable or disable.
+ * param enable True to enable, false to disable.
+ */
+void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable)
+{
+    uint32_t cr3 = 0U;
+
+    if ((uint32_t)fifo & (uint32_t)kCSI_RxFifo)
+    {
+        cr3 |= CSI_CSICR3_DMA_REQ_EN_RFF_MASK;
+    }
+
+    if ((uint32_t)fifo & (uint32_t)kCSI_StatFifo)
+    {
+        cr3 |= CSI_CSICR3_DMA_REQ_EN_SFF_MASK;
+    }
+
+    if (enable)
+    {
+        base->CSICR3 |= cr3;
+    }
+    else
+    {
+        base->CSICR3 &= ~cr3;
+    }
+}
+
+/*!
+ * brief Enables CSI interrupt requests.
+ *
+ * param base CSI peripheral base address.
+ * param mask The interrupts to enable, pass in as OR'ed value of ref _csi_interrupt_enable.
+ */
+void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask)
+{
+    base->CSICR1 |= (mask & CSI_CSICR1_INT_EN_MASK);
+    base->CSICR3 |= (mask & CSI_CSICR3_INT_EN_MASK);
+    base->CSICR18 |= ((mask & CSI_CSICR18_INT_EN_MASK) >> 6U);
+}
+
+/*!
+ * brief Disable CSI interrupt requests.
+ *
+ * param base CSI peripheral base address.
+ * param mask The interrupts to disable, pass in as OR'ed value of ref _csi_interrupt_enable.
+ */
+void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask)
+{
+    base->CSICR1 &= ~(mask & CSI_CSICR1_INT_EN_MASK);
+    base->CSICR3 &= ~(mask & CSI_CSICR3_INT_EN_MASK);
+    base->CSICR18 &= ~((mask & CSI_CSICR18_INT_EN_MASK) >> 6U);
+}
+
+#if !CSI_DRIVER_FRAG_MODE
+/*!
+ * brief Initializes the CSI handle.
+ *
+ * This function initializes CSI handle, it should be called before any other
+ * CSI transactional functions.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the handle structure.
+ * param callback Callback function for CSI transfer.
+ * param userData Callback function parameter.
+ *
+ * retval kStatus_Success Handle created successfully.
+ */
+status_t CSI_TransferCreateHandle(CSI_Type *base,
+                                  csi_handle_t *handle,
+                                  csi_transfer_callback_t callback,
+                                  void *userData)
+{
+    assert(handle);
+    uint32_t instance;
+
+    memset(handle, 0, sizeof(*handle));
+
+    /* Set the callback and user data. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Get instance from peripheral base address. */
+    instance = CSI_GetInstance(base);
+
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_csiHandle[instance] = handle;
+
+    s_csiIsr = CSI_TransferHandleIRQ;
+
+    /* Enable interrupt. */
+    EnableIRQ(s_csiIRQ[instance]);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Start the transfer using transactional functions.
+ *
+ * When the empty frame buffers have been submit to CSI driver using function
+ * ref CSI_TransferSubmitEmptyBuffer, user could call this function to start
+ * the transfer. The incoming frame will be saved to the empty frame buffer,
+ * and user could be optionally notified through callback function.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the handle structure.
+ *
+ * retval kStatus_Success Started successfully.
+ * retval kStatus_CSI_NoEmptyBuffer Could not start because no empty frame buffer in queue.
+ */
+status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle)
+{
+    assert(handle);
+
+    uint32_t emptyBufferCount;
+
+    emptyBufferCount = CSI_TransferGetEmptyBufferCount(base, handle);
+
+    if (emptyBufferCount < 2U)
+    {
+        return kStatus_CSI_NoEmptyBuffer;
+    }
+
+    handle->nextBufferIdx = 0U;
+    handle->activeBufferNum = 0U;
+
+    /*
+     * Write to memory from first completed frame.
+     * DMA base addr switch at the edge of the first data of each frame, thus
+     * if one frame is broken, it could be reset at the next frame.
+     */
+    base->CSICR18 = (base->CSICR18 & ~CSI_CSICR18_MASK_OPTION_MASK) | CSI_CSICR18_MASK_OPTION(0) |
+                    CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK | CSI_CSICR18_BASEADDR_SWITCH_EN_MASK;
+
+    /* Load the frame buffer to CSI register, there are at least two empty buffers. */
+    CSI_TransferLoadBufferToDevice(base, handle);
+    CSI_TransferLoadBufferToDevice(base, handle);
+
+    /* After reflash DMA, the CSI saves frame to frame buffer 0. */
+    CSI_ReflashFifoDma(base, kCSI_RxFifo);
+
+    handle->transferStarted = true;
+    handle->transferOnGoing = true;
+
+    CSI_EnableInterrupts(base, kCSI_RxBuffer1DmaDoneInterruptEnable | kCSI_RxBuffer0DmaDoneInterruptEnable);
+
+    CSI_Start(base);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Stop the transfer using transactional functions.
+ *
+ * The driver does not clean the full frame buffers in queue. In other words, after
+ * calling this function, user still could get the full frame buffers in queue
+ * using function ref CSI_TransferGetFullBuffer.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the handle structure.
+ *
+ * retval kStatus_Success Stoped successfully.
+ */
+status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle)
+{
+    assert(handle);
+
+    CSI_Stop(base);
+    CSI_DisableInterrupts(base, kCSI_RxBuffer1DmaDoneInterruptEnable | kCSI_RxBuffer0DmaDoneInterruptEnable);
+
+    handle->transferStarted = false;
+    handle->transferOnGoing = false;
+
+    /* Stoped, reset the state flags. */
+    handle->queueDrvReadIdx = handle->queueDrvWriteIdx;
+    handle->activeBufferNum = 0U;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Submit empty frame buffer to queue.
+ *
+ * This function could be called before ref CSI_TransferStart or after ref
+ * CSI_TransferStart. If there is no room in queue to store the empty frame
+ * buffer, this function returns error.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the handle structure.
+ * param frameBuffer Empty frame buffer to submit.
+ *
+ * retval kStatus_Success Started successfully.
+ * retval kStatus_CSI_QueueFull Could not submit because there is no room in queue.
+ */
+status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t frameBuffer)
+{
+    uint32_t csicr1;
+
+    if (CSI_DRIVER_QUEUE_SIZE == CSI_TransferGetQueueDelta(handle->queueUserReadIdx, handle->queueUserWriteIdx))
+    {
+        return kStatus_CSI_QueueFull;
+    }
+
+    /* Disable the interrupt to protect the index information in handle. */
+    csicr1 = base->CSICR1;
+
+    base->CSICR1 = (csicr1 & ~(CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK | CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK));
+
+    /* Save the empty frame buffer address to queue. */
+    handle->frameBufferQueue[handle->queueUserWriteIdx] = frameBuffer;
+    handle->queueUserWriteIdx = CSI_TransferIncreaseQueueIdx(handle->queueUserWriteIdx);
+
+    base->CSICR1 = csicr1;
+
+    if (handle->transferStarted)
+    {
+        /*
+         * If user has started transfer using @ref CSI_TransferStart, and the CSI is
+         * stopped due to no empty frame buffer in queue, then start the CSI.
+         */
+        if ((!handle->transferOnGoing) && (CSI_TransferGetEmptyBufferCount(base, handle) >= 2U))
+        {
+            handle->transferOnGoing = true;
+            handle->nextBufferIdx = 0U;
+
+            /* Load the frame buffers to CSI module. */
+            CSI_TransferLoadBufferToDevice(base, handle);
+            CSI_TransferLoadBufferToDevice(base, handle);
+            CSI_ReflashFifoDma(base, kCSI_RxFifo);
+            CSI_Start(base);
+        }
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Get one full frame buffer from queue.
+ *
+ * After the transfer started using function ref CSI_TransferStart, the incoming
+ * frames will be saved to the empty frame buffers in queue. This function gets
+ * the full-filled frame buffer from the queue. If there is no full frame buffer
+ * in queue, this function returns error.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the handle structure.
+ * param frameBuffer Full frame buffer.
+ *
+ * retval kStatus_Success Started successfully.
+ * retval kStatus_CSI_NoFullBuffer There is no full frame buffer in queue.
+ */
+status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t *frameBuffer)
+{
+    uint32_t csicr1;
+
+    /* No full frame buffer. */
+    if (handle->queueUserReadIdx == handle->queueDrvWriteIdx)
+    {
+        return kStatus_CSI_NoFullBuffer;
+    }
+
+    /* Disable the interrupt to protect the index information in handle. */
+    csicr1 = base->CSICR1;
+
+    base->CSICR1 = (csicr1 & ~(CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK | CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK));
+
+    *frameBuffer = handle->frameBufferQueue[handle->queueUserReadIdx];
+
+    handle->queueUserReadIdx = CSI_TransferIncreaseQueueIdx(handle->queueUserReadIdx);
+
+    base->CSICR1 = csicr1;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief CSI IRQ handle function.
+ *
+ * This function handles the CSI IRQ request to work with CSI driver transactional
+ * APIs.
+ *
+ * param base CSI peripheral base address.
+ * param handle CSI handle pointer.
+ */
+void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle)
+{
+    uint32_t queueDrvWriteIdx;
+    uint32_t csisr = base->CSISR;
+
+    /* Clear the error flags. */
+    base->CSISR = csisr;
+
+    /*
+     * If both frame buffer 0 and frame buffer 1 flags assert, driver does not
+     * know which frame buffer ready just now, so reset the CSI transfer to
+     * start from frame buffer 0.
+     */
+    if ((csisr & (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK)) ==
+        (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK))
+    {
+        CSI_Stop(base);
+
+        /* Reset the active buffers. */
+        if (1 <= handle->activeBufferNum)
+        {
+            queueDrvWriteIdx = handle->queueDrvWriteIdx;
+
+            base->CSIDMASA_FB1 = handle->frameBufferQueue[queueDrvWriteIdx];
+
+            if (2U == handle->activeBufferNum)
+            {
+                queueDrvWriteIdx = CSI_TransferIncreaseQueueIdx(queueDrvWriteIdx);
+                base->CSIDMASA_FB2 = handle->frameBufferQueue[queueDrvWriteIdx];
+                handle->nextBufferIdx = 0U;
+            }
+            else
+            {
+                handle->nextBufferIdx = 1U;
+            }
+        }
+        CSI_ReflashFifoDma(base, kCSI_RxFifo);
+        CSI_Start(base);
+    }
+    else if (csisr & (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK))
+    {
+        handle->queueDrvWriteIdx = CSI_TransferIncreaseQueueIdx(handle->queueDrvWriteIdx);
+
+        handle->activeBufferNum--;
+
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_CSI_FrameDone, handle->userData);
+        }
+
+        /* No frame buffer to save incoming data, then stop the CSI module. */
+        if (!(handle->activeBufferNum))
+        {
+            CSI_Stop(base);
+            handle->transferOnGoing = false;
+        }
+        else
+        {
+            if (CSI_TransferGetEmptyBufferCount(base, handle))
+            {
+                CSI_TransferLoadBufferToDevice(base, handle);
+            }
+        }
+    }
+    else
+    {
+    }
+}
+
+#else /* CSI_DRIVER_FRAG_MODE */
+
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__asm void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count)
+{
+    /* clang-format off */
+    push    {r4-r7, lr}
+10
+    LDMIA    R1!, {r3-r6}
+    bfi      r7, r3, #0, #8  /* Y0 */
+    bfi      ip, r5, #0, #8  /* Y4 */
+    lsr      r3, r3, #16
+    lsr      r5, r5, #16
+    bfi      r7, r3, #8, #8  /* Y1 */
+    bfi      ip, r5, #8, #8  /* Y5 */
+    bfi      r7, r4, #16, #8 /* Y2 */
+    bfi      ip, r6, #16, #8 /* Y6 */
+    lsr      r4, r4, #16
+    lsr      r6, r6, #16
+    bfi      r7, r4, #24, #8 /* Y3 */
+    bfi      ip, r6, #24, #8 /* Y7 */
+    STMIA    r0!, {r7, ip}
+    subs     r2, #8
+    bne      %b10
+    pop      {r4-r7, pc}
+    /* clang-format on */
+}
+
+__asm void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count)
+{
+    /* clang-format off */
+    push    {r4-r7, lr}
+10
+    LDMIA    R1!, {r3-r6}
+    lsr      r3, r3, #8
+    lsr      r5, r5, #8
+    bfi      r7, r3, #0, #8  /* Y0 */
+    bfi      ip, r5, #0, #8  /* Y4 */
+    lsr      r3, r3, #16
+    lsr      r5, r5, #16
+    bfi      r7, r3, #8, #8  /* Y1 */
+    bfi      ip, r5, #8, #8  /* Y5 */
+    lsr      r4, r4, #8
+    lsr      r6, r6, #8
+    bfi      r7, r4, #16, #8 /* Y2 */
+    bfi      ip, r6, #16, #8 /* Y6 */
+    lsr      r4, r4, #16
+    lsr      r6, r6, #16
+    bfi      r7, r4, #24, #8 /* Y3 */
+    bfi      ip, r6, #24, #8 /* Y7 */
+    STMIA    r0!, {r7, ip}
+    subs     r2, #8
+    bne      %b10
+    pop      {r4-r7, pc}
+    /* clang-format on */
+}
+
+#elif(defined(__GNUC__) || defined(__ICCARM__))
+#if defined(__ICCARM__)
+#pragma diag_suppress = Pe940
+#endif
+__attribute__((naked)) void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count)
+{
+    /* clang-format off */
+    __asm volatile(
+        "    push    {r1-r7, r12, lr}  \n"
+        "loop0:                        \n"
+        "    ldmia   r1!, {r3-r6}      \n"
+        "    bfi     r7, r3, #0, #8    \n" /* Y0 */
+        "    bfi     r12, r5, #0, #8   \n" /* Y4 */
+        "    lsr     r3, r3, #16       \n"
+        "    lsr     r5, r5, #16       \n"
+        "    bfi     r7, r3, #8, #8    \n" /* Y1 */
+        "    bfi     r12, r5, #8, #8   \n" /* Y5 */
+        "    bfi     r7, r4, #16, #8   \n" /* Y2 */
+        "    bfi     r12, r6, #16, #8  \n" /* Y6 */
+        "    lsr     r4, r4, #16       \n"
+        "    lsr     r6, r6, #16       \n"
+        "    bfi     r7, r4, #24, #8   \n" /* Y3 */
+        "    bfi     r12, r6, #24, #8  \n" /* Y7 */
+        "    stmia   r0!, {r7, r12}    \n"
+        "    subs    r2, #8            \n"
+        "    bne     loop0             \n"
+        "    pop     {r1-r7, r12, pc}  \n");
+    /* clang-format on */
+}
+
+__attribute__((naked)) void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count)
+{
+    /* clang-format off */
+    __asm volatile(
+        "    push    {r1-r7, r12, lr}  \n"
+        "loop1:                        \n"
+        "    ldmia   r1!, {r3-r6}      \n"
+        "    lsr     r3, r3, #8        \n"
+        "    lsr     r5, r5, #8        \n"
+        "    bfi     r7, r3, #0, #8    \n" /* Y0 */
+        "    bfi     r12, r5, #0, #8   \n" /* Y4 */
+        "    lsr     r3, r3, #16       \n"
+        "    lsr     r5, r5, #16       \n"
+        "    bfi     r7, r3, #8, #8    \n" /* Y1 */
+        "    bfi     r12, r5, #8, #8   \n" /* Y5 */
+        "    lsr     r4, r4, #8        \n"
+        "    lsr     r6, r6, #8        \n"
+        "    bfi     r7, r4, #16, #8   \n" /* Y2 */
+        "    bfi     r12, r6, #16, #8  \n" /* Y6 */
+        "    lsr     r4, r4, #16       \n"
+        "    lsr     r6, r6, #16       \n"
+        "    bfi     r7, r4, #24, #8   \n" /* Y3 */
+        "    bfi     r12, r6, #24, #8  \n" /* Y7 */
+        "    stmia   r0!, {r7, r12}    \n"
+        "    subs    r2, #8            \n"
+        "    bne     loop1             \n"
+        "    pop     {r1-r7, r12, pc}  \n");
+    /* clang-format on */
+}
+#if defined(__ICCARM__)
+#pragma diag_default = Pe940
+#endif
+#else
+#error Toolchain not supported.
+#endif
+
+static void CSI_MemCopy(void *pDest, const void *pSrc, size_t cnt)
+{
+    memcpy(pDest, pSrc, cnt);
+}
+
+/*!
+ * brief Initialize the CSI to work in fragment mode.
+ *
+ * This function enables the CSI peripheral clock, and resets the CSI registers.
+ *
+ * param base CSI peripheral base address.
+ */
+void CSI_FragModeInit(CSI_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance = CSI_GetInstance(base);
+    CLOCK_EnableClock(s_csiClocks[instance]);
+#endif
+
+    CSI_Reset(base);
+}
+
+/*!
+ * brief De-initialize the CSI.
+ *
+ * This function disables the CSI peripheral clock.
+ *
+ * param base CSI peripheral base address.
+ */
+void CSI_FragModeDeinit(CSI_Type *base)
+{
+    CSI_Deinit(base);
+}
+
+/*!
+ * brief Create handle for CSI work in fragment mode.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the transactional handle.
+ * param config Pointer to the configuration structure.
+ * param callback Callback function for CSI transfer.
+ * param userData Callback function parameter.
+ *
+ * retval kStatus_Success Initialize successfully.
+ * retval kStatus_InvalidArgument Initialize failed because of invalid argument.
+ */
+status_t CSI_FragModeCreateHandle(CSI_Type *base,
+                                  csi_frag_handle_t *handle,
+                                  const csi_frag_config_t *config,
+                                  csi_frag_transfer_callback_t callback,
+                                  void *userData)
+{
+    assert(config);
+    uint32_t reg;
+    uint32_t instance;
+    uint32_t imgWidth_Bytes;
+
+    imgWidth_Bytes = config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
+
+    /* The image buffer line width should be multiple of 8-bytes. */
+    if ((imgWidth_Bytes & 0x07) != 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Camera frame height must be dividable by DMA buffer line. */
+    if (config->height % config->dmaBufferLine != 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    memset(handle, 0, sizeof(*handle));
+    handle->callback = callback;
+    handle->userData = userData;
+    handle->height = config->height;
+    handle->width = config->width;
+    handle->maxLinePerFrag = config->dmaBufferLine;
+    handle->dmaBytePerLine = config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
+    handle->isDmaBufferCachable = config->isDmaBufferCachable;
+
+    /* Get instance from peripheral base address. */
+    instance = CSI_GetInstance(base);
+    /* Save the handle in global variables to support the double weak mechanism. */
+    s_csiHandle[instance] = handle;
+
+    s_csiIsr = CSI_FragModeTransferHandleIRQ;
+
+    EnableIRQ(s_csiIRQ[instance]);
+
+    /* Configure CSICR1. CSICR1 has been reset to the default value, so could write it directly. */
+    reg = ((uint32_t)config->workMode) | config->polarityFlags | CSI_CSICR1_FCC_MASK;
+
+    if (config->useExtVsync)
+    {
+        reg |= CSI_CSICR1_EXT_VSYNC_MASK;
+    }
+
+    base->CSICR1 = reg;
+
+    /* No stride. */
+    base->CSIFBUF_PARA = 0;
+
+    /* Enable auto ECC. */
+    base->CSICR3 |= CSI_CSICR3_ECC_AUTO_EN_MASK;
+
+    /*
+     * For better performance.
+     * The DMA burst size could be set to 16 * 8 byte, 8 * 8 byte, or 4 * 8 byte,
+     * choose the best burst size based on bytes per line.
+     */
+    if (!(imgWidth_Bytes % (8 * 16)))
+    {
+        base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(3U);
+        base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((2U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
+    }
+    else if (!(imgWidth_Bytes % (8 * 8)))
+    {
+        base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(2U);
+        base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((1U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
+    }
+    else
+    {
+        base->CSICR2 = CSI_CSICR2_DMA_BURST_TYPE_RFF(1U);
+        base->CSICR3 = (CSI->CSICR3 & ~CSI_CSICR3_RxFF_LEVEL_MASK) | ((0U << CSI_CSICR3_RxFF_LEVEL_SHIFT));
+    }
+
+    base->CSIDMASA_FB1 = config->dmaBufferAddr0;
+    base->CSIDMASA_FB2 = config->dmaBufferAddr1;
+
+    if (handle->isDmaBufferCachable)
+    {
+        DCACHE_CleanInvalidateByRange(config->dmaBufferAddr0,
+                                      config->dmaBufferLine * config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
+        DCACHE_CleanInvalidateByRange(config->dmaBufferAddr1,
+                                      config->dmaBufferLine * config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Start to capture a image.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the transactional handle.
+ * param config Pointer to the capture configuration.
+ *
+ * retval kStatus_Success Initialize successfully.
+ * retval kStatus_InvalidArgument Initialize failed because of invalid argument.
+ */
+status_t CSI_FragModeTransferCaptureImage(CSI_Type *base,
+                                          csi_frag_handle_t *handle,
+                                          const csi_frag_capture_config_t *config)
+{
+    assert(config);
+
+    uint16_t windowWidth;
+
+    /*
+     * If no special window setting, capture full frame.
+     * If capture window, then capture 1 one each fragment.
+     */
+    if (config->window != NULL)
+    {
+        handle->windowULX = config->window->windowULX;
+        handle->windowULY = config->window->windowULY;
+        handle->windowLRX = config->window->windowLRX;
+        handle->windowLRY = config->window->windowLRY;
+        handle->linePerFrag = 1;
+    }
+    else
+    {
+        handle->windowULX = 0;
+        handle->windowULY = 0;
+        handle->windowLRX = handle->width - 1;
+        handle->windowLRY = handle->height - 1;
+        handle->linePerFrag = handle->maxLinePerFrag;
+    }
+
+    windowWidth = handle->windowLRX - handle->windowULX + 1;
+
+    if (config->outputGrayScale)
+    {
+        /* When output format is gray, the window width must be multiple value of 8. */
+        if (windowWidth % 8 != 0)
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        handle->datBytePerLine = windowWidth;
+        if (handle->inputFormat == kCSI_FragInputYUYV)
+        {
+            handle->copyFunc = CSI_ExtractYFromYUYV;
+        }
+        else
+        {
+            handle->copyFunc = CSI_ExtractYFromUYVY;
+        }
+    }
+    else
+    {
+        handle->datBytePerLine = windowWidth * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
+        handle->copyFunc = CSI_MemCopy;
+    }
+
+    handle->dmaCurLine = 0;
+    handle->outputBuffer = (uint32_t)config->buffer;
+    handle->datCurWriteAddr = (uint32_t)config->buffer;
+
+    /* Image parameter. */
+    base->CSIIMAG_PARA =
+        ((uint32_t)(handle->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT) |
+        ((uint32_t)(handle->linePerFrag) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT);
+
+    /*
+     * Write to memory from first completed frame.
+     * DMA base addr switch at dma transfer done.
+     */
+    base->CSICR18 = (base->CSICR18 & ~CSI_CSICR18_MASK_OPTION_MASK) | CSI_CSICR18_MASK_OPTION(0);
+
+    CSI_EnableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable |
+                                   kCSI_RxBuffer0DmaDoneInterruptEnable);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Abort image capture.
+ *
+ * Abort image capture initialized by ref CSI_FragModeTransferCaptureImage.
+ *
+ * param base CSI peripheral base address.
+ * param handle Pointer to the transactional handle.
+ */
+void CSI_FragModeTransferAbortCaptureImage(CSI_Type *base, csi_frag_handle_t *handle)
+{
+    CSI_Stop(base);
+    CSI_DisableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable |
+                                    kCSI_RxBuffer0DmaDoneInterruptEnable);
+}
+
+/*!
+ * brief CSI IRQ handle function.
+ *
+ * This function handles the CSI IRQ request to work with CSI driver fragment mode
+ * APIs.
+ *
+ * param base CSI peripheral base address.
+ * param handle CSI handle pointer.
+ */
+void CSI_FragModeTransferHandleIRQ(CSI_Type *base, csi_frag_handle_t *handle)
+{
+    uint32_t csisr = base->CSISR;
+    uint32_t dmaBufAddr;
+    uint16_t line;
+
+    /* Clear the error flags. */
+    base->CSISR = csisr;
+
+    /* Start of frame, clear the FIFO and start receiving. */
+    if (csisr & kCSI_StartOfFrameFlag)
+    {
+        /* Reflash the DMA and enable RX DMA request. */
+        base->CSICR3 |= (CSI_CSICR3_DMA_REFLASH_RFF_MASK | CSI_CSICR3_DMA_REQ_EN_RFF_MASK);
+        CSI_Start(base);
+        handle->dmaCurLine = 0;
+        handle->datCurWriteAddr = handle->outputBuffer;
+    }
+    else if ((csisr & (CSI_CSISR_DMA_TSF_DONE_FB2_MASK | CSI_CSISR_DMA_TSF_DONE_FB1_MASK)) != 0)
+    {
+        if ((csisr & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) == CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
+        {
+            dmaBufAddr = base->CSIDMASA_FB1;
+        }
+        else
+        {
+            dmaBufAddr = base->CSIDMASA_FB2;
+        }
+
+        if (handle->isDmaBufferCachable)
+        {
+            DCACHE_InvalidateByRange(dmaBufAddr, handle->dmaBytePerLine * handle->linePerFrag);
+        }
+
+        /* Copy from DMA buffer to user data buffer. */
+        dmaBufAddr += (handle->windowULX * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
+
+        for (line = 0; line < handle->linePerFrag; line++)
+        {
+            if (handle->dmaCurLine + line > handle->windowLRY)
+            {
+                /* out of window range */
+                break;
+            }
+            else if (handle->dmaCurLine + line >= handle->windowULY)
+            {
+                handle->copyFunc((void *)(handle->datCurWriteAddr), (void const *)dmaBufAddr, handle->datBytePerLine);
+                handle->datCurWriteAddr += handle->datBytePerLine;
+                dmaBufAddr += handle->dmaBytePerLine;
+            }
+            else
+            {
+            }
+        }
+
+        handle->dmaCurLine += handle->linePerFrag;
+
+        if (handle->dmaCurLine >= handle->height)
+        {
+            CSI_Stop(base);
+            CSI_DisableInterrupts(base, kCSI_StartOfFrameInterruptEnable | kCSI_RxBuffer1DmaDoneInterruptEnable |
+                                            kCSI_RxBuffer0DmaDoneInterruptEnable);
+
+            /* Image captured. Stop the CSI. */
+            if (handle->callback)
+            {
+                handle->callback(base, handle, kStatus_CSI_FrameDone, handle->userData);
+            }
+        }
+    }
+    else
+    {
+    }
+}
+#endif /* CSI_DRIVER_FRAG_MODE */
+
+#if defined(CSI)
+void CSI_DriverIRQHandler(void)
+{
+    s_csiIsr(CSI, s_csiHandle[0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(CSI0)
+void CSI0_DriverIRQHandler(void)
+{
+    s_csiIsr(CSI, s_csiHandle[0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_csi.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_csi.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
- * Copyright (c) 2017, NXP Semiconductors, Inc.
+ * Copyright (c) 2017-2018, NXP Semiconductors, Inc.
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_CSI_H_
@@ -48,7 +22,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_CSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+#define FSL_CSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
 /*@}*/
 
 /*! @brief Size of the frame buffer queue used in CSI transactional function. */
@@ -56,6 +30,11 @@
 #define CSI_DRIVER_QUEUE_SIZE 4U
 #endif
 
+/*! @brief Enable fragment capture function or not. */
+#ifndef CSI_DRIVER_FRAG_MODE
+#define CSI_DRIVER_FRAG_MODE 0U
+#endif
+
 /*
  * There is one empty room in queue, used to distinguish whether the queue
  * is full or empty. When header equals tail, the queue is empty; when header
@@ -126,8 +105,8 @@ enum _csi_polarity_flags
     kCSI_HsyncActiveHigh = CSI_CSICR1_HSYNC_POL_MASK,   /*!< HSYNC is active high. */
     kCSI_DataLatchOnRisingEdge = CSI_CSICR1_REDGE_MASK, /*!< Pixel data latched at rising edge of pixel clock. */
     kCSI_DataLatchOnFallingEdge = 0U,                   /*!< Pixel data latched at falling edge of pixel clock. */
-    kCSI_VsyncActiveHigh = 0U,                       /*!< VSYNC is active high. */
-    kCSI_VsyncActiveLow = CSI_CSICR1_SOF_POL_MASK,   /*!< VSYNC is active low. */
+    kCSI_VsyncActiveHigh = 0U,                          /*!< VSYNC is active high. */
+    kCSI_VsyncActiveLow = CSI_CSICR1_SOF_POL_MASK,      /*!< VSYNC is active low. */
 };
 
 /*! @brief Configuration to initialize the CSI module. */
@@ -258,6 +237,99 @@ struct _csi_handle
     void *userData;                   /*!< CSI callback function parameter.*/
 };
 
+#if CSI_DRIVER_FRAG_MODE
+
+/*! @brief Input pixel format when CSI works in fragment mode. */
+typedef enum _csi_frag_input_pixel_format
+{
+    kCSI_FragInputRGB565 = 0, /*!< Input pixel format is RGB565. */
+    kCSI_FragInputYUYV,       /*!< Input pixel format is YUV422 (Y-U-Y-V). */
+    kCSI_FragInputUYVY,       /*!< Input pixel format is YUV422 (U-Y-V-Y). */
+} csi_frag_input_pixel_format_t;
+
+/*! @brief Configuration for CSI module to work in fragment mode. */
+typedef struct _csi_frag_config
+{
+    uint16_t width;           /*!< Pixels of the input frame. */
+    uint16_t height;          /*!< Lines of the input frame.  */
+    uint32_t polarityFlags;   /*!< Timing signal polarity flags, OR'ed value of @ref _csi_polarity_flags. */
+    csi_work_mode_t workMode; /*!< CSI work mode. */
+    csi_data_bus_t dataBus;   /*!< Data bus width. */
+    bool useExtVsync;         /*!< In CCIR656 progressive mode, set true to use external VSYNC signal, set false
+                                to use internal VSYNC signal decoded from SOF. */
+    csi_frag_input_pixel_format_t inputFormat; /*!< Input pixel format. */
+
+    uint32_t dmaBufferAddr0;  /*!< Buffer 0 used for CSI DMA, must be double word aligned. */
+    uint32_t dmaBufferAddr1;  /*!< Buffer 1 used for CSI DMA, must be double word aligned. */
+    uint16_t dmaBufferLine;   /*!< Lines of each DMA buffer. The size of DMA buffer 0 and
+                                   buffer 1 must be the same. Camera frame height must be
+                                   dividable by this value. */
+    bool isDmaBufferCachable; /*!< Is DMA buffer cachable or not. */
+} csi_frag_config_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _csi_frag_handle csi_frag_handle_t;
+
+/*!
+ * @brief CSI fragment transfer callback function.
+ *
+ * When a new frame is received and saved to the frame buffer queue, the callback
+ * is called and the pass the status @ref kStatus_CSI_FrameDone to upper layer.
+ */
+typedef void (*csi_frag_transfer_callback_t)(CSI_Type *base,
+                                             csi_frag_handle_t *handle,
+                                             status_t status,
+                                             void *userData);
+
+/*!
+ * @brief Function to copy data from CSI DMA buffer to user buffer.
+ */
+typedef void (*csi_frag_copy_func_t)(void *pDest, const void *pSrc, size_t cnt);
+
+/*! @brief Handle for CSI module to work in fragment mode. */
+struct _csi_frag_handle
+{
+    uint16_t width;                            /*!< Pixels of the input frame. */
+    uint16_t height;                           /*!< Lines of the input frame.  */
+    uint16_t maxLinePerFrag;                   /*!< Max line saved per fragment. */
+    uint16_t linePerFrag;                      /*!< Actual line saved per fragment. */
+    uint16_t dmaBytePerLine;                   /*!< How many bytes DMA transfered each line. */
+    uint16_t datBytePerLine;                   /*!< How many bytes copied to user buffer each line. */
+    uint16_t dmaCurLine;                       /*!< Current line index in whole frame. */
+    uint16_t windowULX;                        /*!< X of windows upper left corner. */
+    uint16_t windowULY;                        /*!< Y of windows upper left corner. */
+    uint16_t windowLRX;                        /*!< X of windows lower right corner. */
+    uint16_t windowLRY;                        /*!< Y of windows lower right corner. */
+    uint32_t outputBuffer;                     /*!< Address of buffer to save the captured image. */
+    uint32_t datCurWriteAddr;                  /*!< Current write address to the user buffer. */
+    csi_frag_input_pixel_format_t inputFormat; /*!< Input pixel format. */
+
+    csi_frag_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                        /*!< CSI callback function parameter.*/
+    csi_frag_copy_func_t copyFunc;         /*!< Function to copy data from CSI DMA buffer to user buffer. */
+    bool isDmaBufferCachable;              /*!< Is DMA buffer cachable or not. */
+};
+
+/*! @brief Handle for CSI module to work in fragment mode. */
+typedef struct _csi_frag_window
+{
+    uint16_t windowULX; /*!< X of windows upper left corner. */
+    uint16_t windowULY; /*!< Y of windows upper left corner. */
+    uint16_t windowLRX; /*!< X of windows lower right corner. */
+    uint16_t windowLRY; /*!< Y of windows lower right corner. */
+} csi_frag_window_t;
+
+/*! @brief Handle for CSI module to work in fragment mode. */
+typedef struct _csi_frag_capture_config
+{
+    bool outputGrayScale;      /*!< Output gray scale image or not, could only enable when input format is YUV. */
+    uint32_t buffer;           /*!< Buffer to save the captured image. */
+    csi_frag_window_t *window; /*!< Capture window. Capture full frame if set this to NULL. When output format is gray,
+                                    the window width must be multiple value of 8. */
+} csi_frag_capture_config_t;
+
+#endif /* CSI_DRIVER_FRAG_MODE */
+
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -455,6 +527,7 @@ static inline void CSI_ClearStatusFlags(CSI_Type *base, uint32_t statusMask)
 }
 /* @} */
 
+#if !CSI_DRIVER_FRAG_MODE
 /*!
  * @name Transactional
  * @{
@@ -553,6 +626,88 @@ status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_
 void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle);
 /* @} */
 
+#else
+
+/*!
+ * @name Fragment mode
+ * @{
+ */
+
+/*!
+ * @brief Initialize the CSI to work in fragment mode.
+ *
+ * This function enables the CSI peripheral clock, and resets the CSI registers.
+ *
+ * @param base CSI peripheral base address.
+ */
+void CSI_FragModeInit(CSI_Type *base);
+
+/*!
+ * @brief De-initialize the CSI.
+ *
+ * This function disables the CSI peripheral clock.
+ *
+ * @param base CSI peripheral base address.
+ */
+void CSI_FragModeDeinit(CSI_Type *base);
+
+/*!
+ * @brief Create handle for CSI work in fragment mode.
+ *
+ * @param base CSI peripheral base address.
+ * @param handle Pointer to the transactional handle.
+ * @param config Pointer to the configuration structure.
+ * @param callback Callback function for CSI transfer.
+ * @param userData Callback function parameter.
+ *
+ * @retval kStatus_Success Initialize successfully.
+ * @retval kStatus_InvalidArgument Initialize failed because of invalid argument.
+ */
+status_t CSI_FragModeCreateHandle(CSI_Type *base,
+                                  csi_frag_handle_t *handle,
+                                  const csi_frag_config_t *config,
+                                  csi_frag_transfer_callback_t callback,
+                                  void *userData);
+
+/*!
+ * @brief Start to capture a image.
+ *
+ * @param base CSI peripheral base address.
+ * @param handle Pointer to the transactional handle.
+ * @param config Pointer to the capture configuration.
+ *
+ * @retval kStatus_Success Initialize successfully.
+ * @retval kStatus_InvalidArgument Initialize failed because of invalid argument.
+ */
+status_t CSI_FragModeTransferCaptureImage(CSI_Type *base,
+                                          csi_frag_handle_t *handle,
+                                          const csi_frag_capture_config_t *config);
+
+/*!
+ * @brief Abort image capture.
+ *
+ * Abort image capture initialized by @ref CSI_FragModeTransferCaptureImage.
+ *
+ * @param base CSI peripheral base address.
+ * @param handle Pointer to the transactional handle.
+ */
+void CSI_FragModeTransferAbortCaptureImage(CSI_Type *base, csi_frag_handle_t *handle);
+
+/*!
+ * @brief CSI IRQ handle function.
+ *
+ * This function handles the CSI IRQ request to work with CSI driver fragment mode
+ * APIs.
+ *
+ * @param base CSI peripheral base address.
+ * @param handle CSI handle pointer.
+ */
+void CSI_FragModeTransferHandleIRQ(CSI_Type *base, csi_frag_handle_t *handle);
+
+/* @} */
+
+#endif /* CSI_DRIVER_FRAG_MODE */
+
 #if defined(__cplusplus)
 }
 #endif

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dcdc.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcdc.c

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2017, NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_dcdc.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.dcdc_1"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -82,6 +55,11 @@ static uint32_t DCDC_GetInstance(DCDC_Type *base)
     return instance;
 }
 
+/*!
+* brief Enable the access to DCDC registers.
+*
+* param base DCDC peripheral base address.
+*/
 void DCDC_Init(DCDC_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -90,6 +68,11 @@ void DCDC_Init(DCDC_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+* brief Disable the access to DCDC registers.
+*
+* param base DCDC peripheral base address.
+*/
 void DCDC_Deinit(DCDC_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -98,6 +81,12 @@ void DCDC_Deinit(DCDC_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+* brief Configure the DCDC clock source.
+*
+* param base DCDC peripheral base address.
+* param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
+*/
 void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
 {
     uint32_t tmp32;
@@ -125,10 +114,31 @@ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
     base->REG0 = tmp32;
 }
 
+/*!
+* brief Get the default setting for detection configuration.
+*
+* The default configuration are set according to responding registers' setting when powered on.
+* They are:
+* code
+*   config->enableXtalokDetection = false;
+*   config->powerDownOverVoltageDetection = true;
+*   config->powerDownLowVlotageDetection = false;
+*   config->powerDownOverCurrentDetection = true;
+*   config->powerDownPeakCurrentDetection = true;
+*   config->powerDownZeroCrossDetection = true;
+*   config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
+*   config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
+* endcode
+*
+* param config Pointer to configuration structure. See to "dcdc_detection_config_t"
+*/
 void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
 {
     assert(NULL != config);
 
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     config->enableXtalokDetection = false;
     config->powerDownOverVoltageDetection = true;
     config->powerDownLowVlotageDetection = false;
@@ -139,6 +149,12 @@ void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
     config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
 }
 
+/*!
+* breif Configure the DCDC detection.
+*
+* param base DCDC peripheral base address.
+* param config Pointer to configuration structure. See to "dcdc_detection_config_t"
+*/
 void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
 {
     assert(NULL != config);
@@ -179,16 +195,39 @@ void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *con
     base->REG0 = tmp32;
 }
 
+/*!
+* brief Get the default setting for low power configuration.
+*
+* The default configuration are set according to responding registers' setting when powered on.
+* They are:
+* code
+*   config->enableOverloadDetection = true;
+*   config->enableAdjustHystereticValue = false;
+*   config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
+*   config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
+* endcode
+*
+* param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
+*/
 void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
 {
     assert(NULL != config);
 
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     config->enableOverloadDetection = true;
     config->enableAdjustHystereticValue = false;
     config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
     config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
 }
 
+/*!
+* brief Configure the DCDC low power.
+*
+* param base DCDC peripheral base address.
+* param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
+*/
 void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)
 {
     assert(NULL != config);
@@ -211,6 +250,12 @@ void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *conf
     base->REG0 = tmp32;
 }
 
+/*!
+* brief Get DCDC status flags.
+*
+* param base peripheral base address.
+* return Mask of asserted status flags. See to "_dcdc_status_flags_t".
+*/
 uint32_t DCDC_GetstatusFlags(DCDC_Type *base)
 {
     uint32_t tmp32 = 0U;
@@ -223,6 +268,12 @@ uint32_t DCDC_GetstatusFlags(DCDC_Type *base)
     return tmp32;
 }
 
+/*!
+* brief Reset current alert signal. Alert signal is generate by peak current detection.
+*
+* param base DCDC peripheral base address.
+* param enable Switcher to reset signal. True means reset signal. False means don't reset signal.
+*/
 void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable)
 {
     if (enable)
@@ -235,10 +286,31 @@ void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable)
     }
 }
 
+/*!
+* brief Get the default setting for loop control configuration.
+*
+* The default configuration are set according to responding registers' setting when powered on.
+* They are:
+* code
+*   config->enableCommonHysteresis = false;
+*   config->enableCommonThresholdDetection = false;
+*   config->enableInvertHysteresisSign = false;
+*   config->enableRCThresholdDetection = false;
+*   config->enableRCScaleCircuit = 0U;
+*   config->complementFeedForwardStep = 0U;
+*   config->controlParameterMagnitude = 2U;
+*   config->integralProportionalRatio = 2U;
+* endcode
+*
+* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
+*/
 void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
 {
     assert(NULL != config);
 
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     config->enableCommonHysteresis = false;
     config->enableCommonThresholdDetection = false;
     config->enableInvertHysteresisSign = false;
@@ -249,6 +321,12 @@ void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
     config->integralProportionalRatio = 2U;
 }
 
+/*!
+* brief Configure the DCDC loop control.
+*
+* param base DCDC peripheral base address.
+* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
+*/
 void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
 {
     assert(NULL != config);
@@ -287,6 +365,12 @@ void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t
     base->REG2 = tmp32;
 }
 
+/*!
+ * brief Configure for the min power.
+ *
+ * param base DCDC peripheral base address.
+ * param config Pointer to configuration structure. See to "dcdc_min_power_config_t".
+ */
 void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)
 {
     assert(NULL != config);
@@ -301,6 +385,18 @@ void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *conf
     base->REG3 = tmp32;
 }
 
+/*!
+* brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
+*
+* This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
+* stabled.
+* Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
+* back to run mode if it detects the current loading is larger than about 50 mA(typical value).
+*
+* param base DCDC peripheral base address.
+* param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
+* param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
+*/
 void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby)
 {
     uint32_t tmp32;
@@ -321,6 +417,12 @@ void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStan
     }
 }
 
+/*!
+* brief Configure the DCDC internal regulator.
+*
+* param base DCDC peripheral base address.
+* param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
+*/
 void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
 {
     assert(NULL != config);
@@ -337,6 +439,16 @@ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regula
     base->REG1 = tmp32;
 }
 
+/*!
+* brief Boot DCDC into DCM(discontinous conduction mode).
+*
+*  pwd_zcd=0x0;
+*  pwd_cmp_offset=0x0;
+*  dcdc_loopctrl_en_rcscale=0x3 or 0x5;
+*  DCM_set_ctrl=1'b1;
+*
+* param base DCDC peripheral base address.
+*/
 void DCDC_BootIntoDCM(DCDC_Type *base)
 {
     base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
@@ -344,6 +456,15 @@ void DCDC_BootIntoDCM(DCDC_Type *base)
                  DCDC_REG2_DCM_SET_CTRL_MASK;
 }
 
+/*!
+* brief Boot DCDC into CCM(continous conduction mode).
+*
+*  pwd_zcd=0x1;
+*  pwd_cmp_offset=0x0;
+*  dcdc_loopctrl_en_rcscale=0x3;
+*
+* param base DCDC peripheral base address.
+*/
 void DCDC_BootIntoCCM(DCDC_Type *base)
 {
     base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK;

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_dcdc.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcdc.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2017, NXP
  * All rights reserved.
  *
  * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef __FSL_DCDC_H__

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_dcp.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcp.c

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_dcp.h"
@@ -43,7 +17,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.dcp"
 #endif
 
-
 /*! Compile time sizeof() check */
 #define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused))
 
@@ -286,6 +259,24 @@ static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work
     return status;
 }
 
+/*!
+ * brief Set AES key to dcp_handle_t struct and optionally to DCP.
+ *
+ * Sets the AES key for encryption/decryption with the dcp_handle_t structure.
+ * The dcp_handle_t input argument specifies keySlot.
+ * If the keySlot is kDCP_OtpKey, the function will check the OTP_KEY_READY bit and will return it's ready to use
+ * status.
+ * For other keySlot selections, the function will copy and hold the key in dcp_handle_t struct.
+ * If the keySlot is one of the four DCP SRAM-based keys (one of kDCP_KeySlot0, kDCP_KeySlot1, kDCP_KeySlot2,
+ * kDCP_KeySlot3),
+ * this function will also load the supplied key to the specified keySlot in DCP.
+ *
+ * param   base DCP peripheral base address.
+ * param   handle Handle used for the request.
+ * param   key 0-mod-4 aligned pointer to AES key.
+ * param   keySize AES key size in bytes. Shall equal 16.
+ * return  status from set key operation
+ */
 status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize)
 {
     status_t status = kStatus_Fail;
@@ -336,6 +327,19 @@ status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key
     return status;
 }
 
+/*!
+ * brief Encrypts AES on one or multiple 128-bit block(s).
+ *
+ * Encrypts AES.
+ * The source plaintext and destination ciphertext can overlap in system memory.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return Status from encrypt operation
+ */
 status_t DCP_AES_EncryptEcb(
     DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size)
 {
@@ -355,6 +359,20 @@ status_t DCP_AES_EncryptEcb(
     return DCP_WaitForChannelComplete(base, handle);
 }
 
+/*!
+* brief Encrypts AES using the ECB block mode.
+*
+* Puts AES ECB encrypt work packet to DCP channel.
+*
+* param base DCP peripheral base address
+* param handle Handle used for this request.
+* param[out] dcpPacket Memory for the DCP work packet.
+* param plaintext Input plain text to encrypt.
+* param[out] ciphertext Output cipher text
+* param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+* return kStatus_Success The work packet has been scheduled at DCP channel.
+* return kStatus_DCP_Again The DCP channel is busy processing previous request.
+*/
 status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
                                        dcp_handle_t *handle,
                                        dcp_work_packet_t *dcpPacket,
@@ -368,7 +386,8 @@ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
         return kStatus_InvalidArgument;
     }
 
-    dcpPacket->control0 = 0x122u; /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
+    dcpPacket->control0 =
+        0x122u | (handle->swapConfig & 0xFC0000u); /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
     dcpPacket->sourceBufferAddress = (uint32_t)plaintext;
     dcpPacket->destinationBufferAddress = (uint32_t)ciphertext;
     dcpPacket->bufferSize = (uint32_t)size;
@@ -397,6 +416,19 @@ status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
     return dcp_schedule_work(base, handle, dcpPacket);
 }
 
+/*!
+ * brief Decrypts AES on one or multiple 128-bit block(s).
+ *
+ * Decrypts AES.
+ * The source ciphertext and destination plaintext can overlap in system memory.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param ciphertext Input plain text to encrypt
+ * param[out] plaintext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return Status from decrypt operation
+ */
 status_t DCP_AES_DecryptEcb(
     DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size)
 {
@@ -416,6 +448,20 @@ status_t DCP_AES_DecryptEcb(
     return DCP_WaitForChannelComplete(base, handle);
 }
 
+/*!
+ * brief Decrypts AES using ECB block mode.
+ *
+ * Puts AES ECB decrypt dcpPacket to DCP input job ring.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param[out] dcpPacket Memory for the DCP work packet.
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return kStatus_Success The work packet has been scheduled at DCP channel.
+ * return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
 status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
                                        dcp_handle_t *handle,
                                        dcp_work_packet_t *dcpPacket,
@@ -429,7 +475,7 @@ status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
         return kStatus_InvalidArgument;
     }
 
-    dcpPacket->control0 = 0x22u; /* ENABLE_CIPHER | DECR_SEMAPHORE */
+    dcpPacket->control0 = 0x22u | (handle->swapConfig & 0xFC0000u); /* ENABLE_CIPHER | DECR_SEMAPHORE */
     dcpPacket->sourceBufferAddress = (uint32_t)ciphertext;
     dcpPacket->destinationBufferAddress = (uint32_t)plaintext;
     dcpPacket->bufferSize = (uint32_t)size;
@@ -458,6 +504,20 @@ status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
     return dcp_schedule_work(base, handle, dcpPacket);
 }
 
+/*!
+ * brief Encrypts AES using CBC block mode.
+ *
+ * Encrypts AES using CBC block mode.
+ * The source plaintext and destination ciphertext can overlap in system memory.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * return Status from encrypt operation
+ */
 status_t DCP_AES_EncryptCbc(DCP_Type *base,
                             dcp_handle_t *handle,
                             const uint8_t *plaintext,
@@ -481,6 +541,21 @@ status_t DCP_AES_EncryptCbc(DCP_Type *base,
     return DCP_WaitForChannelComplete(base, handle);
 }
 
+/*!
+ * brief Encrypts AES using CBC block mode.
+ *
+ * Puts AES CBC encrypt dcpPacket to DCP input job ring.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request. Specifies jobRing.
+ * param[out] dcpPacket Memory for the DCP work packet.
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * return kStatus_Success The work packet has been scheduled at DCP channel.
+ * return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
 status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
                                        dcp_handle_t *handle,
                                        dcp_work_packet_t *dcpPacket,
@@ -495,8 +570,9 @@ status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
         return kStatus_InvalidArgument;
     }
 
-    dcpPacket->control0 = 0x322u; /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
-    dcpPacket->control1 = 0x10u;  /* CBC */
+    dcpPacket->control0 =
+        0x322u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
+    dcpPacket->control1 = 0x10u;                   /* CBC */
     dcpPacket->sourceBufferAddress = (uint32_t)plaintext;
     dcpPacket->destinationBufferAddress = (uint32_t)ciphertext;
     dcpPacket->bufferSize = (uint32_t)size;
@@ -530,6 +606,20 @@ status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
     return dcp_schedule_work(base, handle, dcpPacket);
 }
 
+/*!
+ * brief Decrypts AES using CBC block mode.
+ *
+ * Decrypts AES using CBC block mode.
+ * The source ciphertext and destination plaintext can overlap in system memory.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * return Status from decrypt operation
+ */
 status_t DCP_AES_DecryptCbc(DCP_Type *base,
                             dcp_handle_t *handle,
                             const uint8_t *ciphertext,
@@ -553,6 +643,21 @@ status_t DCP_AES_DecryptCbc(DCP_Type *base,
     return DCP_WaitForChannelComplete(base, handle);
 }
 
+/*!
+ * brief Decrypts AES using CBC block mode.
+ *
+ * Puts AES CBC decrypt dcpPacket to DCP input job ring.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request. Specifies jobRing.
+ * param[out] dcpPacket Memory for the DCP work packet.
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * return kStatus_Success The work packet has been scheduled at DCP channel.
+ * return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
 status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
                                        dcp_handle_t *handle,
                                        dcp_work_packet_t *dcpPacket,
@@ -567,8 +672,8 @@ status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
         return kStatus_InvalidArgument;
     }
 
-    dcpPacket->control0 = 0x222u; /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */
-    dcpPacket->control1 = 0x10u;  /* CBC */
+    dcpPacket->control0 = 0x222u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */
+    dcpPacket->control1 = 0x10u;                                     /* CBC */
     dcpPacket->sourceBufferAddress = (uint32_t)ciphertext;
     dcpPacket->destinationBufferAddress = (uint32_t)plaintext;
     dcpPacket->bufferSize = (uint32_t)size;
@@ -602,12 +707,29 @@ status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
     return dcp_schedule_work(base, handle, dcpPacket);
 }
 
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the DCP configuration structure to a default value. The default
+ * values are as follows.
+ *   dcpConfig->gatherResidualWrites = true;
+ *   dcpConfig->enableContextCaching = true;
+ *   dcpConfig->enableContextSwitching = true;
+ *   dcpConfig->enableChannnel = kDCP_chEnableAll;
+ *   dcpConfig->enableChannelInterrupt = kDCP_chIntDisable;
+ *
+ * param[out] config Pointer to configuration structure.
+ */
 void DCP_GetDefaultConfig(dcp_config_t *config)
 {
     /* ENABLE_CONTEXT_CACHING is disabled by default as the DCP Hash driver uses
      * dcp_hash_save_running_hash() and dcp_hash_restore_running_hash() to support
      * Hash context switch (different messages interleaved) on the same channel.
      */
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     dcp_config_t userConfig = {
         true, false, true, kDCP_chEnableAll, kDCP_chIntDisable,
     };
@@ -615,6 +737,14 @@ void DCP_GetDefaultConfig(dcp_config_t *config)
     *config = userConfig;
 }
 
+/*!
+ * brief   Enables clock to and enables DCP
+ *
+ * Enable DCP clock and configure DCP.
+ *
+ * param base DCP base address
+ * param config Pointer to configuration structure.
+ */
 void DCP_Init(DCP_Type *base, const dcp_config_t *config)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -639,6 +769,13 @@ void DCP_Init(DCP_Type *base, const dcp_config_t *config)
     base->CONTEXT = (uint32_t)&s_dcpContextSwitchingBuffer;
 }
 
+/*!
+ * brief   Disable DCP clock
+ *
+ * Reset DCP and Disable DCP clock.
+ *
+ * param base DCP base address
+ */
 void DCP_Deinit(DCP_Type *base)
 {
     base->CTRL = 0xF0800000u; /* reset value */
@@ -649,6 +786,16 @@ void DCP_Deinit(DCP_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Poll and wait on DCP channel.
+ *
+ * Polls the specified DCP channel until current it completes activity.
+ *
+ * param   base DCP peripheral base address.
+ * param   handle Specifies DCP channel.
+ * return  kStatus_Success When data processing completes without error.
+ * return  kStatus_Fail When error occurs.
+ */
 status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle)
 {
     /* wait if our channel is still active */
@@ -754,7 +901,8 @@ static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ct
 static status_t dcp_hash_update_non_blocking(
     DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size)
 {
-    dcpPacket->control0 = ctxInternal->ctrl0 | kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR;
+    dcpPacket->control0 = ctxInternal->ctrl0 | (ctxInternal->handle->swapConfig & 0xFC0000u) |
+                          kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR;
     if (ctxInternal->algo == kDCP_Sha256)
     {
         dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_SHA256;
@@ -932,6 +1080,17 @@ static void dcp_hash_restore_running_hash(dcp_hash_ctx_internal_t *ctxInternal)
     }
 }
 
+/*!
+ * brief Initialize HASH context
+ *
+ * This function initializes the HASH.
+ *
+ * param base DCP peripheral base address
+ * param handle Specifies the DCP channel used for hashing.
+ * param[out] ctx Output hash context
+ * param algo Underlaying algorithm to use for hash computation.
+ * return Status of initialization
+ */
 status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo)
 {
     status_t status;
@@ -961,6 +1120,21 @@ status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx
     return status;
 }
 
+/*!
+ * brief Add data to current HASH
+ *
+ * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be
+ * hashed. The functions blocks. If it returns kStatus_Success, the running hash
+ * has been updated (DCP has processed the input data), so the memory at ref input pointer
+ * can be released back to system. The DCP context buffer is updated with the running hash
+ * and with all necessary information to support possible context switch.
+ *
+ * param base DCP peripheral base address
+ * param[in,out] ctx HASH context
+ * param input Input data
+ * param inputSize Size of input data in bytes
+ * return Status of the hash update operation
+ */
 status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize)
 {
     bool isUpdateState;
@@ -1014,6 +1188,17 @@ status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *inp
     return status;
 }
 
+/*!
+ * brief Finalize hashing
+ *
+ * Outputs the final hash (computed by DCP_HASH_Update()) and erases the context.
+ *
+ * param[in,out] ctx Input hash context
+ * param[out] output Output hash data
+ * param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of
+ * output[] buffer. On function return, it stores the number of updated output bytes.
+ * return Status of the hash finish operation
+ */
 status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize)
 {
     size_t algOutSize = 0;
@@ -1100,6 +1285,20 @@ status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, s
     return status;
 }
 
+/*!
+ * brief Create HASH on given data
+ *
+ * Perform the full SHA or CRC32 in one function call. The function is blocking.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for the request.
+ * param algo Underlaying algorithm to use for hash computation.
+ * param input Input data
+ * param inputSize Size of input data in bytes
+ * param[out] output Output hash data
+ * param[out] outputSize Output parameter storing the size of the output hash in bytes
+ * return Status of the one call hash operation.
+ */
 status_t DCP_HASH(DCP_Type *base,
                   dcp_handle_t *handle,
                   dcp_hash_algo_t algo,

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_dcp.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dcp.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
  * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_DCP_H_
@@ -53,15 +27,18 @@ enum _dcp_status
  */
 /*! @name Driver version */
 /*@{*/
-/*! @brief DCP driver version. Version 2.0.0.
+/*! @brief DCP driver version. Version 2.1.0.
  *
- * Current version: 2.0.0
+ * Current version: 2.1.0
  *
  * Change log:
+ * - Version 2.1.0
+ *   - Add byte/word swap feature for key, input and output data
+ *
  * - Version 2.0.0
  *   - Initial version
  */
-#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
 /*@}*/
 
 /*! @brief DCP channel enable.
@@ -114,6 +91,20 @@ typedef enum _dcp_key_slot
     kDCP_PayloadKey = 6U,   /*!< DCP payload key. */
 } dcp_key_slot_t;
 
+/*! @brief DCP key, input & output swap options
+ *
+ */
+typedef enum _dcp_swap
+{
+    kDCP_NoSwap = 0x0U,
+    kDCP_KeyByteSwap = 0x40000U,
+    kDCP_KeyWordSwap = 0x80000U,
+    kDCP_InputByteSwap = 0x100000U,
+    kDCP_InputWordSwap = 0x200000U,
+    kDCP_OutputByteSwap = 0x400000U,
+    kDCP_OutputWordSwap = 0x800000U,
+} dcp_swap_t;
+
 /*! @brief DCP's work packet. */
 typedef struct _dcp_work_packet
 {
@@ -132,6 +123,7 @@ typedef struct _dcp_handle
 {
     dcp_channel_t channel;  /*!< Specify DCP channel. */
     dcp_key_slot_t keySlot; /*!< For operations with key (such as AES encryption/decryption), specify DCP key slot. */
+    uint32_t swapConfig;    /*!< For configuration of key, input, output byte/word swap options */
     uint32_t keyWord[4];
     uint32_t iv[4];
 } dcp_handle_t;

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_dmamux.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dmamux.c

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_dmamux.h"
@@ -43,7 +17,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.dmamux"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -88,6 +61,14 @@ static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes the DMAMUX peripheral.
+ *
+ * This function ungates the DMAMUX clock.
+ *
+ * param base DMAMUX peripheral base address.
+ *
+ */
 void DMAMUX_Init(DMAMUX_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -95,6 +76,13 @@ void DMAMUX_Init(DMAMUX_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Deinitializes the DMAMUX peripheral.
+ *
+ * This function gates the DMAMUX clock.
+ *
+ * param base DMAMUX peripheral base address.
+ */
 void DMAMUX_Deinit(DMAMUX_Type *base)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_dmamux.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_dmamux.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_DMAMUX_H_

bsp/imxrt/Libraries/imxrt1021/devices/MIMXRT1021/drivers/fsl_edma.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_edma.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2018 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_EDMA_H_
@@ -49,7 +23,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief eDMA driver version */
-#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2. */
+#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */
 /*@}*/
 
 /*! @brief Compute the offset unit from DCHPRI3 */
@@ -147,7 +121,7 @@ enum _edma_error_status_flags
 #if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
     kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */
 #endif
-    kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
+    kEDMA_ValidFlag = (int)DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
 };
 
 /*! @brief eDMA interrupt source */
@@ -239,7 +213,7 @@ typedef struct _edma_tcd
     __IO uint32_t DADDR;     /*!< DADDR register, used for destination address */
     __IO uint16_t DOFF;      /*!< DOFF register, used for destination offset */
     __IO uint16_t CITER;     /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/
-    __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */
+    __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */
     __IO uint16_t CSR;       /*!< CSR register, for TCD control status */
     __IO uint16_t BITER;     /*!< BITER register, begin minor loop count. */
 } edma_tcd_t;
@@ -255,10 +229,10 @@ struct _edma_handle;
  * all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.
  *
  * @param handle EDMA handle pointer, users shall not touch the values inside.
- * @param userData The callback user paramter pointer. Users can use this paramter to involve things users need to
+ * @param userData The callback user parameter pointer. Users can use this parameter to involve things users need to
  *                 change in EDMA callback function.
  * @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter
- *                     gather mode, this paramter shows is the current transfer block in EDMA regsiter is done. As the
+ *                     gather mode, this parameter shows is the current transfer block in EDMA register is done. As the
  *                     load of core is different, it will be different if the new tcd loaded into EDMA registers while
  *                     this callback called. If true, it always means new tcd still not loaded into registers, while
  *                     false means new tcd already loaded into registers.
@@ -799,7 +773,7 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel);
  * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used
  * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block
  * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer.
- * Users need to preapre tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
+ * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
  *
  * @param handle eDMA handle pointer.
  * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_elcdif.c → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_elcdif.c

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2017, NXP Semiconductors, Inc.
  * All rights reserved.
  *
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_elcdif.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.elcdif"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -117,6 +90,15 @@ static uint32_t ELCDIF_GetInstance(LCDIF_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initializes the eLCDIF to work in RGB mode (DOTCLK mode).
+ *
+ * This function ungates the eLCDIF clock and configures the eLCDIF peripheral according
+ * to the configuration structure.
+ *
+ * param base eLCDIF peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
 void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config)
 {
     assert(config);
@@ -164,10 +146,38 @@ void ELCDIF_RgbModeInit(LCDIF_Type *base, const elcdif_rgb_mode_config_t *config
     base->NEXT_BUF = config->bufferAddr;
 }
 
+/*!
+ * brief Gets the eLCDIF default configuration structure for RGB (DOTCLK) mode.
+ *
+ * This function sets the configuration structure to default values.
+ * The default configuration is set to the following values.
+ * code
+    config->panelWidth = 480U;
+    config->panelHeight = 272U;
+    config->hsw = 41;
+    config->hfp = 4;
+    config->hbp = 8;
+    config->vsw = 10;
+    config->vfp = 4;
+    config->vbp = 2;
+    config->polarityFlags = kELCDIF_VsyncActiveLow |
+                            kELCDIF_HsyncActiveLow |
+                            kELCDIF_DataEnableActiveLow |
+                            kELCDIF_DriveDataOnFallingClkEdge;
+    config->bufferAddr = 0U;
+    config->pixelFormat = kELCDIF_PixelFormatRGB888;
+    config->dataBus = kELCDIF_DataBus24Bit;
+    code
+ *
+ * param config Pointer to the eLCDIF configuration structure.
+ */
 void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
 {
     assert(config);
 
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     config->panelWidth = 480U;
     config->panelHeight = 272U;
     config->hsw = 41;
@@ -183,6 +193,11 @@ void ELCDIF_RgbModeGetDefaultConfig(elcdif_rgb_mode_config_t *config)
     config->dataBus = kELCDIF_DataBus24Bit;
 }
 
+/*!
+ * brief Deinitializes the eLCDIF peripheral.
+ *
+ * param base eLCDIF peripheral base address.
+ */
 void ELCDIF_Deinit(LCDIF_Type *base)
 {
     ELCDIF_Reset(base);
@@ -197,6 +212,11 @@ void ELCDIF_Deinit(LCDIF_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Stop display in RGB (DOTCLK) mode and wait until finished.
+ *
+ * param base eLCDIF peripheral base address.
+ */
 void ELCDIF_RgbModeStop(LCDIF_Type *base)
 {
     base->CTRL_CLR = LCDIF_CTRL_DOTCLK_MODE_MASK;
@@ -207,6 +227,11 @@ void ELCDIF_RgbModeStop(LCDIF_Type *base)
     }
 }
 
+/*!
+ * brief Reset the eLCDIF peripheral.
+ *
+ * param base eLCDIF peripheral base address.
+ */
 void ELCDIF_Reset(LCDIF_Type *base)
 {
     volatile uint32_t i = 0x100;
@@ -237,6 +262,12 @@ void ELCDIF_Reset(LCDIF_Type *base)
 }
 
 #if !(defined(FSL_FEATURE_LCDIF_HAS_NO_AS) && FSL_FEATURE_LCDIF_HAS_NO_AS)
+/*!
+ * brief Set the configuration for alpha surface buffer.
+ *
+ * param base eLCDIF peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
 void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer_config_t *config)
 {
     assert(config);
@@ -246,6 +277,12 @@ void ELCDIF_SetAlphaSurfaceBufferConfig(LCDIF_Type *base, const elcdif_as_buffer
     base->AS_NEXT_BUF = config->bufferAddr;
 }
 
+/*!
+ * brief Set the alpha surface blending configuration.
+ *
+ * param base eLCDIF peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
 void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_config_t *config)
 {
     assert(config);
@@ -267,6 +304,20 @@ void ELCDIF_SetAlphaSurfaceBlendConfig(LCDIF_Type *base, const elcdif_as_blend_c
 #endif /* FSL_FEATURE_LCDIF_HAS_NO_AS */
 
 #if (defined(FSL_FEATURE_LCDIF_HAS_LUT) && FSL_FEATURE_LCDIF_HAS_LUT)
+/*!
+ * brief Load the LUT value.
+ *
+ * This function loads the LUT value to the specific LUT memory, user can
+ * specify the start entry index.
+ *
+ * param base eLCDIF peripheral base address.
+ * param lut Which LUT to load.
+ * param startIndex The start index of the LUT entry to update.
+ * param lutData The LUT data to load.
+ * param count Count of p lutData.
+ * retval kStatus_Success Initialization success.
+ * retval kStatus_InvalidArgument Wrong argument.
+ */
 status_t ELCDIF_UpdateLut(
     LCDIF_Type *base, elcdif_lut_t lut, uint16_t startIndex, const uint32_t *lutData, uint16_t count)
 {

bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_elcdif.h → bsp/imxrt/Libraries/MIMXRT1050/MIMXRT1052/drivers/fsl_elcdif.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2017, NXP Semiconductors, Inc.
  * All rights reserved.
  *
  * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_ELCDIF_H_