first console project

bsp/maxim/MAX32660_EVSYS/.config

@@ -54,6 +54,7 @@ CONFIG_RT_USING_MEMPOOL=y
 # CONFIG_RT_USING_NOHEAP is not set
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
 # CONFIG_RT_USING_MEMTRACE is not set
 CONFIG_RT_USING_HEAP=y
 
@@ -63,9 +64,7 @@ CONFIG_RT_USING_HEAP=y
 CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
-CONFIG_RT_USING_CONSOLE=y
-CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+# CONFIG_RT_USING_CONSOLE is not set
 CONFIG_RT_VER_NUM=0x40003
 # CONFIG_RT_USING_CPU_FFS is not set
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@@ -73,10 +72,8 @@ CONFIG_RT_VER_NUM=0x40003
 #
 # RT-Thread Components
 #
-CONFIG_RT_USING_COMPONENTS_INIT=y
-CONFIG_RT_USING_USER_MAIN=y
-CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
-CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_COMPONENTS_INIT is not set
+# CONFIG_RT_USING_USER_MAIN is not set
 
 #
 # C++ features
@@ -86,21 +83,7 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
 #
 # Command shell
 #
-CONFIG_RT_USING_FINSH=y
-CONFIG_FINSH_THREAD_NAME="tshell"
-CONFIG_FINSH_USING_HISTORY=y
-CONFIG_FINSH_HISTORY_LINES=5
-CONFIG_FINSH_USING_SYMTAB=y
-CONFIG_FINSH_USING_DESCRIPTION=y
-# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
-# CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-CONFIG_FINSH_USING_MSH_ONLY=y
-CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_FINSH is not set
 
 #
 # Device virtual file system
@@ -297,6 +280,8 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_WAVPLAYER is not set
 # CONFIG_PKG_USING_TJPGD is not set
 # CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
 
 #
 # tools packages
@@ -311,6 +296,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
 # CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
 # CONFIG_PKG_USING_NR_MICRO_SHELL is not set
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
@@ -318,6 +304,8 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_GPS_RMC is not set
 # CONFIG_PKG_USING_URLENCODE is not set
 # CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
 
 #
 # system packages
@@ -344,10 +332,16 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_RAMDISK is not set
 # CONFIG_PKG_USING_MININI is not set
 # CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
 # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
 # CONFIG_PKG_USING_UC_CRC is not set
 # CONFIG_PKG_USING_UC_CLK is not set
 # CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_PPOOL is not set
 
 #
@@ -407,6 +401,10 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
 # CONFIG_PKG_USING_WK2124 is not set
 # CONFIG_PKG_USING_LY68L6400 is not set
 # CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_BSAL is not set
 
 #
 # miscellaneous packages
@@ -416,6 +414,7 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
@@ -436,63 +435,33 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_NNOM is not set
 # CONFIG_PKG_USING_LIBANN is not set
 # CONFIG_PKG_USING_ELAPACK is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
 # CONFIG_PKG_USING_VT100 is not set
-# CONFIG_PKG_USING_TETRIS is not set
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# games: games run on RT-Thread console
+#
 # CONFIG_PKG_USING_THREES is not set
 # CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
 # CONFIG_PKG_USING_LWGPS is not set
 # CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
 
 #
 # Hardware Drivers Config
 #
-CONFIG_SOC_NRF52840=y
-CONFIG_NRFX_CLOCK_ENABLED=1
-CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7
-CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1
-CONFIG_SOC_NORDIC=y
-
-#
-# Onboard Peripheral Drivers
-#
-CONFIG_BSP_USING_JLINK_TO_USART=y
-# CONFIG_BSP_USING_QSPI_FLASH is not set
+CONFIG_SOC_MAXIM=y
 
 #
 # On-chip Peripheral Drivers
 #
 CONFIG_BSP_USING_GPIO=y
-CONFIG_NRFX_GPIOTE_ENABLED=1
-# CONFIG_BSP_USING_SAADC is not set
-# CONFIG_BSP_USING_PWM is not set
-CONFIG_BSP_USING_UART=y
-CONFIG_NRFX_USING_UART=y
-# CONFIG_NRFX_USING_UARTE is not set
-CONFIG_NRFX_UART_ENABLED=1
-CONFIG_BSP_USING_UART0=y
-CONFIG_NRFX_UART0_ENABLED=1
-CONFIG_BSP_UART0_RX_PIN=8
-CONFIG_BSP_UART0_TX_PIN=6
-# CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_ON_CHIP_FLASH is not set
-
-#
-# On-chip flash config
-#
-CONFIG_MCU_FLASH_START_ADDRESS=0x00000000
-CONFIG_MCU_FLASH_SIZE_KB=1024
-CONFIG_MCU_SRAM_START_ADDRESS=0x20000000
-CONFIG_MCU_SRAM_SIZE_KB=256
-CONFIG_MCU_FLASH_PAGE_SIZE=0x1000
-# CONFIG_BSP_USING_WDT is not set
-# CONFIG_BSP_USING_ONCHIP_RTC is not set
-CONFIG_BLE_STACK_USING_NULL=y
-# CONFIG_BSP_USING_SOFTDEVICE is not set
-# CONFIG_BSP_USING_NIMBLE is not set

bsp/maxim/MAX32660_EVSYS/SConstruct

@@ -48,10 +48,10 @@ print(SDK_LIB)
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
 # include drivers
-objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
+#objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
 
 # include cmsis
-objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript')))
+#objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript')))
 
 # make a building
 DoBuilding(TARGET, objs)

bsp/maxim/MAX32660_EVSYS/applications/application.c

@@ -13,19 +13,24 @@
 #include <rtdevice.h>
 #define DK_BOARD_LED_1  13
 #define DK_BOARD_LED_2  14
+#include "gpio.h"
 
+const gpio_cfg_t led_pin[] = {
+    {PORT_0, PIN_13, GPIO_FUNC_OUT, GPIO_PAD_NONE},
+};
 int main(void)
 {
     int count = 1; 
-    rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT);
-    
+    GPIO_Config(&led_pin[0]);
+    //rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT);
+    GPIO_OutSet(&led_pin[0]);
     while (count++)
     {    
-        rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
+        //rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
         rt_thread_mdelay(500);
-        
-        rt_pin_write(DK_BOARD_LED_1, PIN_LOW);
-        rt_thread_mdelay(500);                    
+        GPIO_OutToggle(&led_pin[0]);
+        //rt_pin_write(DK_BOARD_LED_1, PIN_LOW);
+        //rt_thread_mdelay(500);                    
     }
     return RT_EOK;
 }

bsp/maxim/MAX32660_EVSYS/applications/drv_uart.c

@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-08     Supperthomas first version
+ */
+
+#include "board.h"
+#include "uart.h"
+#include "rtdevice.h"
+
+#define BUFF_SIZE           10
+uint8_t rxdata[BUFF_SIZE]={0};
+
+
+#define UART0_CONFIG                                                \
+    {                                                               \
+        .name = "uart0",                                            \
+        .Instance = MXC_UART_GET_UART(0),                                         \
+        .irq_type = MXC_UART_GET_IRQ(0),                                    \
+    }
+
+    
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = MXC_UART_GET_UART(1),                                         \
+        .irq_type = MXC_UART_GET_IRQ(1),                                    \
+    }
+
+struct mcu_uart_config
+{
+    const char *name;
+    mxc_uart_regs_t *Instance;
+    IRQn_Type irq_type;
+};
+
+struct mcu_uart
+{
+    mxc_uart_regs_t *handle;
+    struct mcu_uart_config *config;
+
+    rt_uint16_t uart_dma_flag;
+    struct rt_serial_device serial;
+};
+
+
+#ifdef RT_USING_SERIAL
+
+//#define DRV_DEBUG
+//#define LOG_TAG             "drv.usart"
+//#include <drv_log.h>
+
+#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1)
+
+#error "Please define at least one BSP_USING_UARTx"
+/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+enum
+{
+#ifdef BSP_USING_UART0
+    UART0_INDEX,
+#endif
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+
+};
+
+static struct mcu_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART0
+    UART0_CONFIG,
+#endif
+#ifdef BSP_USING_UART1
+    UART1_CONFIG,
+#endif
+};
+
+static struct mcu_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+
+#ifdef BSP_USING_UART1
+void UART1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    
+    rt_hw_serial_isr(&(uart_obj[UART1_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
+    /* leave interrupt */
+    uint32_t  intst = 0;
+    intst = MXC_UART1->int_fl;
+    MXC_UART1->int_fl = intst;
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_UART0
+void UART0_IRQHandler(void)
+{
+    //UART_Handler(MXC_UART0);
+    /* enter interrupt */
+    rt_interrupt_enter();
+    
+    rt_hw_serial_isr(&(uart_obj[UART0_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
+    /* leave interrupt */
+    uint32_t  intst = 0;
+    intst = MXC_UART0->int_fl;
+    MXC_UART0->int_fl = intst;
+    
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+
+static rt_err_t mcu_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    int error, i;
+    struct mcu_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    const sys_cfg_uart_t sys_uart_cfg = {
+        MAP_A,
+        UART_FLOW_DISABLE,
+    };
+    uart = rt_container_of(serial, struct mcu_uart, serial);
+    uart_cfg_t mcu_cfg;
+    uart->handle = uart->config->Instance;
+    mcu_cfg.baud = cfg->baud_rate;
+    mcu_cfg.stop = UART_STOP_1;
+    mcu_cfg.parity = UART_PARITY_DISABLE;
+    mcu_cfg.size = UART_DATA_SIZE_8_BITS;
+    mcu_cfg.flow = UART_FLOW_CTRL_EN;
+    mcu_cfg.pol = UART_FLOW_POL_EN;
+    
+    error= UART_Init(uart->handle, &mcu_cfg, &sys_uart_cfg);
+    
+     
+    return RT_EOK;
+}
+
+static rt_err_t mcu_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct mcu_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct mcu_uart, serial);
+
+    switch (cmd)
+    {
+    /* disable interrupt */
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+      //  NVIC_DisableIRQ(uart->config->irq_type);
+        NVIC_ClearPendingIRQ(uart->config->irq_type);
+        NVIC_DisableIRQ(uart->config->irq_type);
+        /* disable interrupt */
+        break;
+
+    /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+          NVIC_SetPriority(uart->config->irq_type, 1);
+          NVIC_EnableIRQ(uart->config->irq_type);
+    /* enable interrupt */
+          uart->handle->ctrl |=  0x05 << MXC_F_UART_CTRL_RX_TO_POS;
+          uart->handle->int_en |= MXC_F_UART_INT_EN_RX_FIFO_THRESH | MXC_F_UART_INT_EN_RX_TIMEOUT;
+#define UART_ER_IE (MXC_F_UART_INT_EN_RX_FRAME_ERROR | \
+                    MXC_F_UART_INT_EN_RX_PARITY_ERROR | \
+                    MXC_F_UART_INT_EN_RX_OVERRUN )
+              uart->handle->int_en |= UART_ER_IE;
+    
+          uart->handle->thresh_ctrl=MXC_UART_FIFO_DEPTH<<
+                      MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS;
+        break;
+
+#ifdef RT_SERIAL_USING_DMA
+    case RT_DEVICE_CTRL_CONFIG:
+        stm32_dma_config(serial, ctrl_arg);
+        break;
+#endif
+
+    case RT_DEVICE_CTRL_CLOSE:
+//        if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
+//        {
+//            RT_ASSERT(0)
+//        }
+        break;
+
+    }
+    return RT_EOK;
+}
+
+static int mcu_putc(struct rt_serial_device *serial, char c)
+{
+    struct mcu_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct mcu_uart, serial);
+    UART_WriteByte(uart->handle, c);
+    return 1;
+}
+
+static int mcu_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct mcu_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct mcu_uart, serial);
+
+    ch = -1;
+
+    if(UART_NumReadAvail(uart->handle))
+    {
+       ch = UART_ReadByte(uart->handle);
+    }
+
+    return ch;
+}
+
+
+
+
+
+static const struct rt_uart_ops mcu_uart_ops =
+{
+    .configure = mcu_configure,
+    .control = mcu_control,
+    .putc = mcu_putc,
+    .getc = mcu_getc,
+};
+
+int rt_hw_usart_init(void)
+{
+    rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct mcu_uart);
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t result = 0;
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        /* init UART object */
+        uart_obj[i].config = &uart_config[i];
+        uart_obj[i].serial.ops    = &mcu_uart_ops;
+        uart_obj[i].serial.config = config;
+
+        /* register UART device */
+        result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
+                                       RT_DEVICE_FLAG_RDWR
+                                       | RT_DEVICE_FLAG_INT_RX
+                                       | RT_DEVICE_FLAG_INT_TX
+                                       , NULL);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+//INIT_BOARD_EXPORT(rt_hw_usart_init);
+#endif /* RT_USING_SERIAL */

bsp/maxim/MAX32660_EVSYS/applications/drv_usart.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018.10.30     SummerGift   first version
+ * 2019.03.05     whj4674672   add stm32h7
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
+ */
+
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
+
+int rt_hw_usart_init(void);
+
+#endif  /* __DRV_USART_H__ */

bsp/maxim/MAX32660_EVSYS/board/Kconfig

@@ -1,502 +1,28 @@
 menu "Hardware Drivers Config"
 
-config SOC_NRF52840
+config SOC_MAX32660
     bool
-    config SOC_NRF52840
+    config SOC_MAX32660
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
-    default y
-    config NRFX_CLOCK_ENABLED
-    int 
-    default 1
-    config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
-    int 
-    default 7
-    config NRFX_CLOCK_CONFIG_LF_SRC
-    int 
-    default 1  
-
     
-config SOC_NORDIC
+config SOC_MAXIM
     bool 
-    config SOC_NORDIC
+    config SOC_MAXIM
     default y
 
-menu "Onboard Peripheral Drivers"
-    config BSP_USING_JLINK_TO_USART
-        bool "Enable JLINK TO USART (uart0|RX_PIN:8|TX_PIN:6)"
-        select BSP_USING_UART
-        select BSP_USING_UART0
-        default y
-
-    menuconfig BSP_USING_QSPI_FLASH
-        select PKG_USING_FAL
-        bool "Enable QSPI FLASH(MX25R64 8MB)"
-        default n
-
-        if BSP_USING_QSPI_FLASH
-            config NRFX_QSPI_ENABLED
-            int 
-            default 1
-            config BSP_QSPI_SCK_PIN
-                int "QSPI SCK pin number"
-                range 0 31
-                default 19
-            config BSP_QSPI_CSN_PIN
-                int "QSPI CSN pin number"
-                range 0 31
-                default 17
-            config BSP_QSPI_IO0_PIN
-                int "QSPI IO0 pin number"
-                range 0 31
-                default 20
-            config BSP_QSPI_IO1_PIN
-                int "QSPI IO1 pin number"
-                range 0 31
-                default 21
-            config BSP_QSPI_IO2_PIN
-                int "QSPI IO2 pin number"
-                range 0 31
-                default 22
-            config BSP_QSPI_IO3_PIN
-                int "QSPI IO3 pin number"
-                range 0 31
-                default 23
-            config QSPI_FLASH_SIZE_KB 
-                int "QSPI FLASH SIZE, DEFAULT size 8192 KB"
-                default 8192
-        endif
-endmenu
-
 menu "On-chip Peripheral Drivers"
     config BSP_USING_GPIO
         bool "Enable GPIO"
         select RT_USING_PIN
         default y
-    if BSP_USING_GPIO
-        config NRFX_GPIOTE_ENABLED
-        int 
-        default 1  
-    endif
-    config BSP_USING_SAADC
-        bool "Enable SAADC"
-        select RT_USING_ADC
-        default n
-        if BSP_USING_SAADC
-                config NRFX_SAADC_ENABLED
-                int 
-                default 1  
-        endif
-    menuconfig BSP_USING_PWM
-        bool "Enable PWM"
-        select RT_USING_PWM
-        default n
-        if BSP_USING_PWM
-                config NRFX_PWM_ENABLED
-                int 
-                default 1
-                config BSP_USING_PWM0
-                    bool "Enable PWM0 bus"
-                    default y
-                if BSP_USING_PWM0
-                    config NRFX_PWM0_ENABLED
-                    int 
-                    default 1
-                    config BSP_USING_PWM0_CH0
-                        int "PWM0 channel 0 pin number set"
-                        range 0 47
-                        default 13
-                    config BSP_USING_PWM0_CH1
-                        int "PWM0 channel 1 pin number set"
-                        range 0 47
-                        default 14
-                    config BSP_USING_PWM0_CH2
-                        int "PWM0 channel 2 pin number set"
-                        range 0 47
-                        default 15
-                    config BSP_USING_PWM0_CH3
-                        int "PWM0 channel 3 pin number set"
-                        range 0 47
-                        default 16
-                endif
-                config BSP_USING_PWM1
-                    bool "Enable PWM1 bus"
-                    default n
-                if BSP_USING_PWM1
-                    config NRFX_PWM1_ENABLED
-                    int 
-                    default 1
-                    config BSP_USING_PWM1_CH0
-                        int "PWM1 channel 0 pin number set"
-                        range 0 47
-                        default 13
-                    config BSP_USING_PWM1_CH1
-                        int "PWM1 channel 1 pin number set"
-                        range 0 47
-                        default 14
-                    config BSP_USING_PWM1_CH2
-                        int "PWM1 channel 2 pin number set"
-                        range 0 47
-                        default 15
-                    config BSP_USING_PWM1_CH3
-                        int "PWM1 channel 3 pin number set"
-                        range 0 47
-                        default 16
-                endif
-                config BSP_USING_PWM2
-                    bool "Enable PWM2 bus"
-                    default n
-                if BSP_USING_PWM2
-                    config NRFX_PWM2_ENABLED
-                    int 
-                    default 1
-                    config BSP_USING_PWM2_CH0
-                        int "PWM2 channel 0 pin number set"
-                        range 0 47
-                        default 13
-                    config BSP_USING_PWM2_CH1
-                        int "PWM2 channel 1 pin number set"
-                        range 0 47
-                        default 14
-                    config BSP_USING_PWM2_CH2
-                        int "PWM2 channel 2 pin number set"
-                        range 0 47
-                        default 15
-                    config BSP_USING_PWM2_CH3
-                        int "PWM2 channel 3 pin number set"
-                        range 0 47
-                        default 16
-                endif
-                config BSP_USING_PWM3
-                    bool "Enable PWM3 bus"
-                    default n
-                if BSP_USING_PWM3
-                    config NRFX_PWM3_ENABLED
-                    int 
-                    default 1
-                    config BSP_USING_PWM3_CH0
-                        int "PWM3 channel 0 pin number set"
-                        range 0 47
-                        default 13
-                    config BSP_USING_PWM3_CH1
-                        int "PWM3 channel 1 pin number set"
-                        range 0 47
-                        default 14
-                    config BSP_USING_PWM3_CH2
-                        int "PWM3 channel 2 pin number set"
-                        range 0 47
-                        default 15
-                    config BSP_USING_PWM3_CH3
-                        int "PWM3 channel 3 pin number set"
-                        range 0 47
-                        default 16
-                endif
-        endif
-
-    
-    config BSP_USING_UART
-		bool "Enable UART"
-        default y
-        select RT_USING_SERIAL
-		if BSP_USING_UART
-		choice
-		prompt "UART or UARTE"
-		default NRFX_USING_UART
-		help
-			Select the UART or UARTE
-		config NRFX_USING_UART
-			bool "UART"
-		
-		config NRFX_USING_UARTE
-			bool "UARTE"
-		endchoice
-		endif
-        if BSP_USING_UART&&NRFX_USING_UART
-            config NRFX_UART_ENABLED
-            int 
-            default 1
-
-            config BSP_USING_UART0
-                bool "Enable UART0"
-                default y 
-                if BSP_USING_UART0
-                    config NRFX_UART0_ENABLED
-                    int 
-                    default 1
-                    config BSP_UART0_RX_PIN
-                        int "uart0 rx pin number"
-                        range 0 31
-                        default 8
-                    config BSP_UART0_TX_PIN
-                        int "uart0 tx pin number"
-                        range 0 31
-                        default 6
-                endif
-        endif
-        if BSP_USING_UART&&NRFX_USING_UARTE
-            config NRFX_UARTE_ENABLED
-            int 
-            default 1
-
-            config BSP_USING_UART0
-                bool "Enable UARTE0"
-                default n 
-                if BSP_USING_UART0
-                    config NRFX_UARTE0_ENABLED
-                    int 
-                    default 1
-                    config BSP_UART0_RX_PIN
-                        int "uarte0 rx pin number"
-                        range 0 31
-                        default 8
-                    config BSP_UART0_TX_PIN
-                        int "uarte0 tx pin number"
-                        range 0 31
-                        default 6
-                endif
-            config BSP_USING_UART1
-                bool "Enable UARTE1"
-                default n 
-                if BSP_USING_UART1
-                    config NRFX_UARTE1_ENABLED
-                    int 
-                    default 1
-                    config BSP_UART1_RX_PIN
-                        int "uarte1 rx pin number"
-                        range 0 31
-                        default 7
-                    config BSP_UART1_TX_PIN
-                        int "uarte1 tx pin number"
-                        range 0 31
-                        default 5
-                endif
-        endif
-    config BSP_USING_I2C
-        bool "Enable I2C"
-        select RT_USING_I2C
-        default n
-        if BSP_USING_I2C
-            config NRFX_TWIM_ENABLED
-            int 
-            default 1
-            config BSP_USING_I2C0
-                bool "Enable I2C0 bus"
-                default n
-            if BSP_USING_I2C0
-                config NRFX_TWIM0_ENABLED
-                int 
-                default 1
-                config BSP_I2C0_SCL_PIN
-                    int "i2c0 scl pin number"
-                    range 0 31
-                    default 27
-                config BSP_I2C0_SDA_PIN
-                    int "I2C0 sda pin number"
-                    range 0 31
-                    default 26
-            endif
-            config BSP_USING_I2C1
-                bool "Enable I2C1 bus"
-                default n
-            if BSP_USING_I2C1
-                config NRFX_TWIM1_ENABLED
-                int 
-                default 1
-                config BSP_I2C1_SCL_PIN
-                    int "i2c1 scl pin number"
-                    range 0 31
-                    default 3
-                config BSP_I2C1_SDA_PIN
-                    int "I2C1 sda pin number"
-                    range 0 31
-                    default 2
-            endif
-        endif
-    config BSP_USING_SPI
-        bool "Enable SPI"
-        select RT_USING_PIN
-        default y
-
-        if BSP_USING_SPI
-            config NRFX_SPI_ENABLED
-            int 
-            default 1
-            config BSP_USING_SPI0
-                bool "Enable SPI0 bus"
-                default y
-            if BSP_USING_SPI0
-                config NRFX_SPI0_ENABLED
-                    int "Enable SPI0 instance"
-                    default 1
-                config BSP_SPI0_SCK_PIN
-                    int "SPI0 sck pin number set"
-                    range 0 47
-                    default 28
-                config BSP_SPI0_MOSI_PIN
-                    int "SPI0 mosi pin number set"
-                    range 0 47
-                    default 29
-                config BSP_SPI0_MISO_PIN
-                    int "SPI0 miso pin number set"
-                    range 0 47
-                    default 30
-                config BSP_SPI0_SS_PIN
-                    int "SPI0 ss pin number set"
-                    range 0 47
-                    default 31
-            endif
-
-            config BSP_USING_SPI1
-                bool "Enable SPI1 bus"
-                default n
-            if BSP_USING_SPI1
-                config NRFX_SPI1_ENABLED
-                    int "Enable SPI1 instance"
-                    default 1
-                config BSP_SPI1_SCK_PIN
-                    int "SPI0 sck pin number set"
-                    range 0 47
-                    default 28
-                config BSP_SPI1_MOSI_PIN
-                    int "SPI0 mosi pin number set"
-                    range 0 47
-                    default 29
-                config BSP_SPI1_MISO_PIN
-                    int "SPI0 miso pin number set"
-                    range 0 47
-                    default 30
-                config BSP_SPI1_SS_PIN
-                    int "SPI0 ss pin number set"
-                    range 0 47
-                    default 31
-            endif
-
-            config BSP_USING_SPI2
-                bool "Enable SPI2 bus"
-                default n
-            if BSP_USING_SPI2
-                config NRFX_SPI2_ENABLED
-                    int "Enable SPI2 instance"
-                    default 1
-                config BSP_SPI2_SCK_PIN
-                    int "SPI0 sck pin number set"
-                    range 0 47
-                    default 28
-                config BSP_SPI2_MOSI_PIN
-                    int "SPI0 mosi pin number set"
-                    range 0 47
-                    default 29
-                config BSP_SPI2_MISO_PIN
-                    int "SPI0 miso pin number set"
-                    range 0 47
-                    default 30
-                config BSP_SPI2_SS_PIN
-                    int "SPI0 ss pin number set"
-                    range 0 47
-                    default 31
-            endif
-
-        endif
     config BSP_USING_ON_CHIP_FLASH
         select PKG_USING_FAL
         bool "Enable on-chip FLASH"
         default n
 
-    menu "On-chip flash config"
-
-        config MCU_FLASH_START_ADDRESS  
-            hex "MCU FLASH START ADDRESS"
-            default 0x00000000
-
-        config MCU_FLASH_SIZE_KB  
-            int "MCU FLASH SIZE, MAX size 1024 KB"
-            range 1 1024
-            default 1024		
-
-        config MCU_SRAM_START_ADDRESS 
-            hex "MCU RAM START ADDRESS"
-            default 0x20000000
-
-        config MCU_SRAM_SIZE_KB 
-            int "MCU RAM SIZE, MAX size 256 KB"
-            range 1 256
-            default 256
-
-        config MCU_FLASH_PAGE_SIZE 
-            hex "MCU FLASH PAGE SIZE, please not change,nrfx default is 0x1000"
-            range 0x1000 0x1000
-            default 0x1000
-	endmenu
-    config BSP_USING_WDT
-        bool "Enable WDT"
-        select RT_USING_WDT
-        default n
-    if BSP_USING_WDT
-        config NRFX_WDT_ENABLED
-        int
-        default 1
-        config NRFX_WDT0_ENABLED
-        int
-        default 1
-        config NRFX_WDT_CONFIG_NO_IRQ
-        int
-        default 1
-    endif
-
-    menuconfig BSP_USING_ONCHIP_RTC
-    bool "Enable RTC"
-    select RT_USING_RTC
-    select RT_USING_LIBC
-    default n
-    if BSP_USING_ONCHIP_RTC
-        config NRFX_CLOCK_ENABLED
-        int 
-        default 1
-        config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
-        int
-        default 7
-        config NRFX_RTC_ENABLED
-        int 
-        default 1
-        config NRFX_RTC0_ENABLED
-        int
-        default 1
-        config NRFX_RTC1_ENABLED
-        int
-        default 1
-        config NRFX_RTC2_ENABLED
-        int
-        default 1
-        config RTC_INSTANCE_ID
-        int 
-        default 2
-        config RTC_INSTANCE_ID
-            int "select RTC instance id, must be 0, 1, 2"
-            range 0 2
-            default 2
-    endif
-
 endmenu
 
-choice
-prompt "BLE STACK"
-default BLE_STACK_USING_NULL
-help
-    Select the ble stack
-
-config BLE_STACK_USING_NULL
-    bool "not use the ble stack"
-
-config  BSP_USING_SOFTDEVICE
-    select PKG_USING_NRF5X_SDK
-    bool "Nordic softdevice(perpheral)"
-
-config BSP_USING_NIMBLE
-    select PKG_USING_NIMBLE
-    select PKG_NIMBLE_BSP_NRF52840
-    bool "use nimble stack(iot)"
-endchoice
-
 
 endmenu
 

bsp/maxim/MAX32660_EVSYS/board/board.c

@@ -10,11 +10,12 @@
  */
 #include <rtthread.h>
 #include <rthw.h>
-#include <nrfx_systick.h>
-
+#include <stdio.h>
 #include "board.h"
-#include "drv_uart.h"
-#include <nrfx_clock.h>
+#include "mxc_sys.h"
+#ifdef RT_USING_SERIAL
+#include "drv_usart.h"
+#endif
 
 /**
  * This is the timer interrupt service routine.
@@ -31,63 +32,49 @@ void SysTick_Handler(void)
     rt_interrupt_leave();
 }
 
-static void clk_event_handler(nrfx_clock_evt_type_t event){}
-
 void SysTick_Configuration(void)
 {
-    nrfx_clock_init(clk_event_handler);
-    nrfx_clock_enable();
-    nrfx_clock_lfclk_start();
-    /* Set interrupt priority */
-    NVIC_SetPriority(SysTick_IRQn, 0xf);
-
-    /* Configure SysTick to interrupt at the requested rate. */
-    nrf_systick_load_set(SystemCoreClock / RT_TICK_PER_SECOND);
-    nrf_systick_val_clear();
-    nrf_systick_csr_set(NRF_SYSTICK_CSR_CLKSOURCE_CPU | NRF_SYSTICK_CSR_TICKINT_ENABLE
-                        | NRF_SYSTICK_CSR_ENABLE);
+    uint32_t error;
+    error = SYS_SysTick_Config(SYS_SysTick_GetFreq()/RT_TICK_PER_SECOND, 1, MXC_TMR0);
 
+    if (error != E_NO_ERROR) {
+        printf("ERROR: Ticks is not valid");
+    }
 }
 
+mxc_uart_regs_t *ConsoleUART = MXC_UART_GET_UART(1);
+
+const sys_cfg_uart_t console_uart_sys_cfg = {
+    MAP_A,
+    UART_FLOW_DISABLE,
+};
+
 
 void rt_hw_board_init(void)
 {
-    rt_hw_interrupt_enable(0);
+   // rt_hw_interrupt_enable(0);
     // sd_power_dcdc_mode_set(NRF_POWER_DCDC_ENABLE);
     /* Activate deep sleep mode */
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 
     SysTick_Configuration();
 
 #if defined(RT_USING_HEAP)
-    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+    rt_system_heap_init((void *)(0x20000000+16*1024), (void *)(0x20000000+64*1024));
 #endif
-
+   
 #ifdef RT_USING_SERIAL
-    rt_hw_uart_init();
+    rt_hw_usart_init();
 #endif
-
+    
 #ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-
+    
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
+    
 
-#ifdef BSP_USING_SOFTDEVICE
-    extern uint32_t  Image$$RW_IRAM1$$Base;
-    uint32_t const *const m_ram_start  = &Image$$RW_IRAM1$$Base;
-    if ((uint32_t)m_ram_start == 0x20000000)
-    {
-        rt_kprintf("\r\n using softdevice the RAM couldn't be %p,please use the templete from package\r\n", m_ram_start);
-        while (1);
-    }
-    else
-    {
-        rt_kprintf("\r\n using softdevice the RAM at %p\r\n", m_ram_start);
-    }
-#endif
 
 }
 

bsp/maxim/MAX32660_EVSYS/board/board.h

@@ -3,7 +3,6 @@
 
 #include <rtthread.h>
 #include <rthw.h>
-#include "nrf.h"
 
 #define MCU_FLASH_SIZE MCU_FLASH_SIZE_KB*1024
 #define MCU_FLASH_END_ADDRESS        ((uint32_t)(MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE))

bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.sct

@@ -2,13 +2,14 @@
 ; *** Scatter-Loading Description File generated by uVision ***
 ; *************************************************************
 
-LR_IROM1 0x00000000 0x100000  {    ; load region size_region
-  ER_IROM1 0x00000000 0x100000  {  ; load address = execution address
+LR_IROM1 0x00000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00040000  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
+   .ANY (+XO)
   }
-  RW_IRAM1 0x20000000 0x40000  {  ; RW data
+  RW_IRAM1 0x20000000 0x00018000  {  ; RW data
    .ANY (+RW +ZI)
   }
 }

bsp/maxim/MAX32660_EVSYS/board/nrfx_config.h

@@ -1,47 +0,0 @@
-/**
- * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#ifndef NRFX_CONFIG_H__
-#define NRFX_CONFIG_H__
-
-// TODO - temporary redirection
-#include <sdk_config.h>
-
-#endif // NRFX_CONFIG_H__

bsp/maxim/MAX32660_EVSYS/board/nrfx_glue.h

@@ -1,269 +0,0 @@
-/*
- * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef NRFX_GLUE_H__
-#define NRFX_GLUE_H__
-
-// THIS IS A TEMPLATE FILE.
-// It should be copied to a suitable location within the host environment into
-// which nrfx is integrated, and the following macros should be provided with
-// appropriate implementations.
-// And this comment should be removed from the customized file.
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include <stdbool.h>
-#include "nrf.h"
-/**
- * @defgroup nrfx_glue nrfx_glue.h
- * @{
- * @ingroup nrfx
- *
- * @brief This file contains macros that should be implemented according to
- *        the needs of the host environment into which @em nrfx is integrated.
- */
-
-// Uncomment this line to use the standard MDK way of binding IRQ handlers
-// at linking time.
-#include <soc/nrfx_irqs.h>
-
-//------------------------------------------------------------------------------
-
-/**
- * @brief Macro for placing a runtime assertion.
- *
- * @param expression Expression to be evaluated.
- */
-#define NRFX_ASSERT(expression)
-
-/**
- * @brief Macro for placing a compile time assertion.
- *
- * @param expression Expression to be evaluated.
- */
-#define NRFX_STATIC_ASSERT(expression)
-
-//------------------------------------------------------------------------------
-
-/**
- * @brief Macro for setting the priority of a specific IRQ.
- *
- * @param irq_number IRQ number.
- * @param priority   Priority to be set.
- */
-#define NRFX_IRQ_PRIORITY_SET(irq_number, priority)     NVIC_SetPriority(irq_number, priority)
-
-/**
- * @brief Macro for enabling a specific IRQ.
- *
- * @param irq_number IRQ number.
- */
-#define NRFX_IRQ_ENABLE(irq_number)     NVIC_EnableIRQ(irq_number)
-
-/**
- * @brief Macro for checking if a specific IRQ is enabled.
- *
- * @param irq_number IRQ number.
- *
- * @retval true  If the IRQ is enabled.
- * @retval false Otherwise.
- */
-#define NRFX_IRQ_IS_ENABLED(irq_number)  _NRFX_IRQ_IS_ENABLED(irq_number)
-static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number)
-{
-    return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32)));
-}
-
-
-/**
- * @brief Macro for disabling a specific IRQ.
- *
- * @param irq_number IRQ number.
- */
-#define NRFX_IRQ_DISABLE(irq_number)  _NRFX_IRQ_DISABLE(irq_number)
-static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number)
-{
-    NVIC_DisableIRQ(irq_number);
-}
-
-
-/**
- * @brief Macro for setting a specific IRQ as pending.
- *
- * @param irq_number IRQ number.
- */
-#define NRFX_IRQ_PENDING_SET(irq_number)
-
-/**
- * @brief Macro for clearing the pending status of a specific IRQ.
- *
- * @param irq_number IRQ number.
- */
-#define NRFX_IRQ_PENDING_CLEAR(irq_number)
-
-/**
- * @brief Macro for checking the pending status of a specific IRQ.
- *
- * @retval true  If the IRQ is pending.
- * @retval false Otherwise.
- */
-#define NRFX_IRQ_IS_PENDING(irq_number)
-
-/** @brief Macro for entering into a critical section. */
-#define NRFX_CRITICAL_SECTION_ENTER()
-
-/** @brief Macro for exiting from a critical section. */
-#define NRFX_CRITICAL_SECTION_EXIT()
-
-//------------------------------------------------------------------------------
-
-/**
- * @brief When set to a non-zero value, this macro specifies that
- *        @ref nrfx_coredep_delay_us uses a precise DWT-based solution.
- *        A compilation error is generated if the DWT unit is not present
- *        in the SoC used.
- */
-#define NRFX_DELAY_DWT_BASED    0
-
-/**
- * @brief Macro for delaying the code execution for at least the specified time.
- *
- * @param us_time Number of microseconds to wait.
- */
-#define NRFX_DELAY_US(us_time)
-
-//------------------------------------------------------------------------------
-
-/** @brief Atomic 32-bit unsigned type. */
-#define nrfx_atomic_t
-
-/**
- * @brief Macro for storing a value to an atomic object and returning its previous value.
- *
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value  Value to store.
- *
- * @return Previous value of the atomic object.
- */
-#define NRFX_ATOMIC_FETCH_STORE(p_data, value)
-
-/**
- * @brief Macro for running a bitwise OR operation on an atomic object and returning its previous value.
- *
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value  Value of the second operand in the OR operation.
- *
- * @return Previous value of the atomic object.
- */
-#define NRFX_ATOMIC_FETCH_OR(p_data, value)
-
-/**
- * @brief Macro for running a bitwise AND operation on an atomic object
- *        and returning its previous value.
- *
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value  Value of the second operand in the AND operation.
- *
- * @return Previous value of the atomic object.
- */
-#define NRFX_ATOMIC_FETCH_AND(p_data, value)
-
-/**
- * @brief Macro for running a bitwise XOR operation on an atomic object
- *        and returning its previous value.
- *
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value  Value of the second operand in the XOR operation.
- *
- * @return Previous value of the atomic object.
- */
-#define NRFX_ATOMIC_FETCH_XOR(p_data, value)
-
-/**
- * @brief Macro for running an addition operation on an atomic object
- *        and returning its previous value.
- *
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value  Value of the second operand in the ADD operation.
- *
- * @return Previous value of the atomic object.
- */
-#define NRFX_ATOMIC_FETCH_ADD(p_data, value)
-
-/**
- * @brief Macro for running a subtraction operation on an atomic object
- *        and returning its previous value.
- *
- * @param[in] p_data Atomic memory pointer.
- * @param[in] value  Value of the second operand in the SUB operation.
- *
- * @return Previous value of the atomic object.
- */
-#define NRFX_ATOMIC_FETCH_SUB(p_data, value)
-
-//------------------------------------------------------------------------------
-
-/**
- * @brief When set to a non-zero value, this macro specifies that the
- *        @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined
- *        in a customized way and the default definitions from @c <nrfx_error.h>
- *        should not be used.
- */
-#define NRFX_CUSTOM_ERROR_CODES 0
-
-//------------------------------------------------------------------------------
-
-/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */
-#define NRFX_DPPI_CHANNELS_USED  0
-
-/** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */
-#define NRFX_DPPI_GROUPS_USED    0
-
-/** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */
-#define NRFX_PPI_CHANNELS_USED  0
-
-/** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */
-#define NRFX_PPI_GROUPS_USED    0
-
-/** @brief Bitmask that defines EGU instances that are reserved for use outside of the nrfx library. */
-#define NRFX_EGUS_USED          0
-
-/** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */
-#define NRFX_TIMERS_USED        0
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // NRFX_GLUE_H__

bsp/maxim/MAX32660_EVSYS/board/nrfx_log.h

@@ -1,135 +0,0 @@
-/*
- * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef NRFX_LOG_H__
-#define NRFX_LOG_H__
-
-// THIS IS A TEMPLATE FILE.
-// It should be copied to a suitable location within the host environment into
-// which nrfx is integrated, and the following macros should be provided with
-// appropriate implementations.
-// And this comment should be removed from the customized file.
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup nrfx_log nrfx_log.h
- * @{
- * @ingroup nrfx
- *
- * @brief This file contains macros that should be implemented according to
- *        the needs of the host environment into which @em nrfx is integrated.
- */
-
-/**
- * @brief Macro for logging a message with the severity level ERROR.
- *
- * @param format printf-style format string, optionally followed by arguments
- *               to be formatted and inserted in the resulting string.
- */
-#define NRFX_LOG_ERROR(format, ...)
-
-/**
- * @brief Macro for logging a message with the severity level WARNING.
- *
- * @param format printf-style format string, optionally followed by arguments
- *               to be formatted and inserted in the resulting string.
- */
-#define NRFX_LOG_WARNING(format, ...)
-
-/**
- * @brief Macro for logging a message with the severity level INFO.
- *
- * @param format printf-style format string, optionally followed by arguments
- *               to be formatted and inserted in the resulting string.
- */
-#define NRFX_LOG_INFO(format, ...)
-
-/**
- * @brief Macro for logging a message with the severity level DEBUG.
- *
- * @param format printf-style format string, optionally followed by arguments
- *               to be formatted and inserted in the resulting string.
- */
-#define NRFX_LOG_DEBUG(format, ...)
-
-
-/**
- * @brief Macro for logging a memory dump with the severity level ERROR.
- *
- * @param[in] p_memory Pointer to the memory region to be dumped.
- * @param[in] length   Length of the memory region in bytes.
- */
-#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length)
-
-/**
- * @brief Macro for logging a memory dump with the severity level WARNING.
- *
- * @param[in] p_memory Pointer to the memory region to be dumped.
- * @param[in] length   Length of the memory region in bytes.
- */
-#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length)
-
-/**
- * @brief Macro for logging a memory dump with the severity level INFO.
- *
- * @param[in] p_memory Pointer to the memory region to be dumped.
- * @param[in] length   Length of the memory region in bytes.
- */
-#define NRFX_LOG_HEXDUMP_INFO(p_memory, length)
-
-/**
- * @brief Macro for logging a memory dump with the severity level DEBUG.
- *
- * @param[in] p_memory Pointer to the memory region to be dumped.
- * @param[in] length   Length of the memory region in bytes.
- */
-#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length)
-
-
-/**
- * @brief Macro for getting the textual representation of a given error code.
- *
- * @param[in] error_code Error code.
- *
- * @return String containing the textual representation of the error code.
- */
-#define NRFX_LOG_ERROR_STRING_GET(error_code)
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // NRFX_LOG_H__

bsp/maxim/MAX32660_EVSYS/board/sdk_config.h

@@ -1,11704 +0,0 @@
-/**
- * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- *    list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form, except as embedded into a Nordic
- *    Semiconductor ASA integrated circuit in a product or a software update for
- *    such product, must reproduce the above copyright notice, this list of
- *    conditions and the following disclaimer in the documentation and/or other
- *    materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- *    contributors may be used to endorse or promote products derived from this
- *    software without specific prior written permission.
- *
- * 4. This software, with or without modification, must only be used with a
- *    Nordic Semiconductor ASA integrated circuit.
- *
- * 5. Any software provided in binary form under this license must not be reverse
- *    engineered, decompiled, modified and/or disassembled.
- *
- * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-
-
-#ifndef SDK_CONFIG_H
-#define SDK_CONFIG_H
-// <<< Use Configuration Wizard in Context Menu >>>\n
-#ifdef USE_APP_CONFIG
-#include "app_config.h"
-#endif
-// <h> nRF_BLE 
-
-#include <rtconfig.h>
-//==========================================================
-// <q> BLE_ADVERTISING_ENABLED  - ble_advertising - Advertising module
- 
-
-#ifndef BLE_ADVERTISING_ENABLED
-#define BLE_ADVERTISING_ENABLED 0
-#endif
-
-// <q> BLE_DTM_ENABLED  - ble_dtm - Module for testing RF/PHY using DTM commands
- 
-
-#ifndef BLE_DTM_ENABLED
-#define BLE_DTM_ENABLED 0
-#endif
-
-// <q> BLE_RACP_ENABLED  - ble_racp - Record Access Control Point library
- 
-
-#ifndef BLE_RACP_ENABLED
-#define BLE_RACP_ENABLED 0
-#endif
-
-// <e> NRF_BLE_QWR_ENABLED - nrf_ble_qwr - Queued writes support module (prepare/execute write)
-//==========================================================
-#ifndef NRF_BLE_QWR_ENABLED
-#define NRF_BLE_QWR_ENABLED 0
-#endif
-// <o> NRF_BLE_QWR_MAX_ATTR - Maximum number of attribute handles that can be registered. This number must be adjusted according to the number of attributes for which Queued Writes will be enabled. If it is zero, the module will reject all Queued Write requests. 
-#ifndef NRF_BLE_QWR_MAX_ATTR
-#define NRF_BLE_QWR_MAX_ATTR 0
-#endif
-
-// </e>
-
-// <e> PEER_MANAGER_ENABLED - peer_manager - Peer Manager
-//==========================================================
-#ifndef PEER_MANAGER_ENABLED
-#define PEER_MANAGER_ENABLED 0
-#endif
-// <o> PM_MAX_REGISTRANTS - Number of event handlers that can be registered. 
-#ifndef PM_MAX_REGISTRANTS
-#define PM_MAX_REGISTRANTS 3
-#endif
-
-// <o> PM_FLASH_BUFFERS - Number of internal buffers for flash operations. 
-// <i> Decrease this value to lower RAM usage.
-
-#ifndef PM_FLASH_BUFFERS
-#define PM_FLASH_BUFFERS 4
-#endif
-
-// <q> PM_CENTRAL_ENABLED  - Enable/disable central-specific Peer Manager functionality.
- 
-
-// <i> Enable/disable central-specific Peer Manager functionality.
-
-#ifndef PM_CENTRAL_ENABLED
-#define PM_CENTRAL_ENABLED 1
-#endif
-
-// <q> PM_SERVICE_CHANGED_ENABLED  - Enable/disable the service changed management for GATT server in Peer Manager.
- 
-
-// <i> If not using a GATT server, or using a server wihout a service changed characteristic,
-// <i> disable this to save code space.
-
-#ifndef PM_SERVICE_CHANGED_ENABLED
-#define PM_SERVICE_CHANGED_ENABLED 1
-#endif
-
-// <q> PM_PEER_RANKS_ENABLED  - Enable/disable the peer rank management in Peer Manager.
- 
-
-// <i> Set this to false to save code space if not using the peer rank API.
-
-#ifndef PM_PEER_RANKS_ENABLED
-#define PM_PEER_RANKS_ENABLED 1
-#endif
-
-// <q> PM_LESC_ENABLED  - Enable/disable LESC support in Peer Manager.
- 
-
-// <i> If set to true, you need to call nrf_ble_lesc_request_handler() in the main loop to respond to LESC-related BLE events. If LESC support is not required, set this to false to save code space.
-
-#ifndef PM_LESC_ENABLED
-#define PM_LESC_ENABLED 0
-#endif
-
-// <e> PM_RA_PROTECTION_ENABLED - Enable/disable protection against repeated pairing attempts in Peer Manager.
-//==========================================================
-#ifndef PM_RA_PROTECTION_ENABLED
-#define PM_RA_PROTECTION_ENABLED 0
-#endif
-// <o> PM_RA_PROTECTION_TRACKED_PEERS_NUM - Maximum number of peers whose authorization status can be tracked. 
-#ifndef PM_RA_PROTECTION_TRACKED_PEERS_NUM
-#define PM_RA_PROTECTION_TRACKED_PEERS_NUM 8
-#endif
-
-// <o> PM_RA_PROTECTION_MIN_WAIT_INTERVAL - Minimum waiting interval (in ms) before a new pairing attempt can be initiated. 
-#ifndef PM_RA_PROTECTION_MIN_WAIT_INTERVAL
-#define PM_RA_PROTECTION_MIN_WAIT_INTERVAL 4000
-#endif
-
-// <o> PM_RA_PROTECTION_MAX_WAIT_INTERVAL - Maximum waiting interval (in ms) before a new pairing attempt can be initiated. 
-#ifndef PM_RA_PROTECTION_MAX_WAIT_INTERVAL
-#define PM_RA_PROTECTION_MAX_WAIT_INTERVAL 64000
-#endif
-
-// <o> PM_RA_PROTECTION_REWARD_PERIOD - Reward period (in ms). 
-// <i> The waiting interval is gradually decreased when no new failed pairing attempts are made during reward period.
-
-#ifndef PM_RA_PROTECTION_REWARD_PERIOD
-#define PM_RA_PROTECTION_REWARD_PERIOD 10000
-#endif
-
-// </e>
-
-// <o> PM_HANDLER_SEC_DELAY_MS - Delay before starting security. 
-// <i>  This might be necessary for interoperability reasons, especially as peripheral.
-
-#ifndef PM_HANDLER_SEC_DELAY_MS
-#define PM_HANDLER_SEC_DELAY_MS 0
-#endif
-
-// </e>
-
-// </h> 
-//==========================================================
-
-// <h> nRF_BLE_Services 
-
-//==========================================================
-// <q> BLE_ANCS_C_ENABLED  - ble_ancs_c - Apple Notification Service Client
- 
-
-#ifndef BLE_ANCS_C_ENABLED
-#define BLE_ANCS_C_ENABLED 0
-#endif
-
-// <q> BLE_ANS_C_ENABLED  - ble_ans_c - Alert Notification Service Client
- 
-
-#ifndef BLE_ANS_C_ENABLED
-#define BLE_ANS_C_ENABLED 0
-#endif
-
-// <q> BLE_BAS_C_ENABLED  - ble_bas_c - Battery Service Client
- 
-
-#ifndef BLE_BAS_C_ENABLED
-#define BLE_BAS_C_ENABLED 0
-#endif
-
-// <e> BLE_BAS_ENABLED - ble_bas - Battery Service
-//==========================================================
-#ifndef BLE_BAS_ENABLED
-#define BLE_BAS_ENABLED 0
-#endif
-// <e> BLE_BAS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef BLE_BAS_CONFIG_LOG_ENABLED
-#define BLE_BAS_CONFIG_LOG_ENABLED 0
-#endif
-// <o> BLE_BAS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef BLE_BAS_CONFIG_LOG_LEVEL
-#define BLE_BAS_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> BLE_BAS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef BLE_BAS_CONFIG_INFO_COLOR
-#define BLE_BAS_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> BLE_BAS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef BLE_BAS_CONFIG_DEBUG_COLOR
-#define BLE_BAS_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <q> BLE_CSCS_ENABLED  - ble_cscs - Cycling Speed and Cadence Service
- 
-
-#ifndef BLE_CSCS_ENABLED
-#define BLE_CSCS_ENABLED 0
-#endif
-
-// <q> BLE_CTS_C_ENABLED  - ble_cts_c - Current Time Service Client
- 
-
-#ifndef BLE_CTS_C_ENABLED
-#define BLE_CTS_C_ENABLED 0
-#endif
-
-// <q> BLE_DIS_ENABLED  - ble_dis - Device Information Service
- 
-
-#ifndef BLE_DIS_ENABLED
-#define BLE_DIS_ENABLED 0
-#endif
-
-// <q> BLE_GLS_ENABLED  - ble_gls - Glucose Service
- 
-
-#ifndef BLE_GLS_ENABLED
-#define BLE_GLS_ENABLED 0
-#endif
-
-// <q> BLE_HIDS_ENABLED  - ble_hids - Human Interface Device Service
- 
-
-#ifndef BLE_HIDS_ENABLED
-#define BLE_HIDS_ENABLED 0
-#endif
-
-// <q> BLE_HRS_C_ENABLED  - ble_hrs_c - Heart Rate Service Client
- 
-
-#ifndef BLE_HRS_C_ENABLED
-#define BLE_HRS_C_ENABLED 0
-#endif
-
-// <q> BLE_HRS_ENABLED  - ble_hrs - Heart Rate Service
- 
-
-#ifndef BLE_HRS_ENABLED
-#define BLE_HRS_ENABLED 0
-#endif
-
-// <q> BLE_HTS_ENABLED  - ble_hts - Health Thermometer Service
- 
-
-#ifndef BLE_HTS_ENABLED
-#define BLE_HTS_ENABLED 0
-#endif
-
-// <q> BLE_IAS_C_ENABLED  - ble_ias_c - Immediate Alert Service Client
- 
-
-#ifndef BLE_IAS_C_ENABLED
-#define BLE_IAS_C_ENABLED 0
-#endif
-
-// <e> BLE_IAS_ENABLED - ble_ias - Immediate Alert Service
-//==========================================================
-#ifndef BLE_IAS_ENABLED
-#define BLE_IAS_ENABLED 0
-#endif
-// <e> BLE_IAS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef BLE_IAS_CONFIG_LOG_ENABLED
-#define BLE_IAS_CONFIG_LOG_ENABLED 0
-#endif
-// <o> BLE_IAS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef BLE_IAS_CONFIG_LOG_LEVEL
-#define BLE_IAS_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> BLE_IAS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef BLE_IAS_CONFIG_INFO_COLOR
-#define BLE_IAS_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> BLE_IAS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef BLE_IAS_CONFIG_DEBUG_COLOR
-#define BLE_IAS_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <q> BLE_LBS_C_ENABLED  - ble_lbs_c - Nordic LED Button Service Client
- 
-
-#ifndef BLE_LBS_C_ENABLED
-#define BLE_LBS_C_ENABLED 0
-#endif
-
-// <q> BLE_LBS_ENABLED  - ble_lbs - LED Button Service
- 
-
-#ifndef BLE_LBS_ENABLED
-#define BLE_LBS_ENABLED 0
-#endif
-
-// <q> BLE_LLS_ENABLED  - ble_lls - Link Loss Service
- 
-
-#ifndef BLE_LLS_ENABLED
-#define BLE_LLS_ENABLED 0
-#endif
-
-// <q> BLE_NUS_C_ENABLED  - ble_nus_c - Nordic UART Central Service
- 
-
-#ifndef BLE_NUS_C_ENABLED
-#define BLE_NUS_C_ENABLED 0
-#endif
-
-// <e> BLE_NUS_ENABLED - ble_nus - Nordic UART Service
-//==========================================================
-#ifndef BLE_NUS_ENABLED
-#define BLE_NUS_ENABLED 0
-#endif
-// <e> BLE_NUS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef BLE_NUS_CONFIG_LOG_ENABLED
-#define BLE_NUS_CONFIG_LOG_ENABLED 0
-#endif
-// <o> BLE_NUS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef BLE_NUS_CONFIG_LOG_LEVEL
-#define BLE_NUS_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> BLE_NUS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef BLE_NUS_CONFIG_INFO_COLOR
-#define BLE_NUS_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> BLE_NUS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef BLE_NUS_CONFIG_DEBUG_COLOR
-#define BLE_NUS_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <q> BLE_RSCS_C_ENABLED  - ble_rscs_c - Running Speed and Cadence Client
- 
-
-#ifndef BLE_RSCS_C_ENABLED
-#define BLE_RSCS_C_ENABLED 0
-#endif
-
-// <q> BLE_RSCS_ENABLED  - ble_rscs - Running Speed and Cadence Service
- 
-
-#ifndef BLE_RSCS_ENABLED
-#define BLE_RSCS_ENABLED 0
-#endif
-
-// <q> BLE_TPS_ENABLED  - ble_tps - TX Power Service
- 
-
-#ifndef BLE_TPS_ENABLED
-#define BLE_TPS_ENABLED 0
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> nRF_Core 
-
-//==========================================================
-// <e> NRF_MPU_LIB_ENABLED - nrf_mpu_lib - Module for MPU
-//==========================================================
-#ifndef NRF_MPU_LIB_ENABLED
-#define NRF_MPU_LIB_ENABLED 0
-#endif
-// <q> NRF_MPU_LIB_CLI_CMDS  - Enable CLI commands specific to the module.
- 
-
-#ifndef NRF_MPU_LIB_CLI_CMDS
-#define NRF_MPU_LIB_CLI_CMDS 0
-#endif
-
-// </e>
-
-// <e> NRF_STACK_GUARD_ENABLED - nrf_stack_guard - Stack guard
-//==========================================================
-#ifndef NRF_STACK_GUARD_ENABLED
-#define NRF_STACK_GUARD_ENABLED 0
-#endif
-// <o> NRF_STACK_GUARD_CONFIG_SIZE  - Size of the stack guard.
- 
-// <5=> 32 bytes 
-// <6=> 64 bytes 
-// <7=> 128 bytes 
-// <8=> 256 bytes 
-// <9=> 512 bytes 
-// <10=> 1024 bytes 
-// <11=> 2048 bytes 
-// <12=> 4096 bytes 
-
-#ifndef NRF_STACK_GUARD_CONFIG_SIZE
-#define NRF_STACK_GUARD_CONFIG_SIZE 7
-#endif
-
-// </e>
-
-// </h> 
-//==========================================================
-
-// <h> nRF_Crypto 
-
-//==========================================================
-// <e> NRF_CRYPTO_ENABLED - nrf_crypto - Cryptography library.
-//==========================================================
-#ifndef NRF_CRYPTO_ENABLED
-#define NRF_CRYPTO_ENABLED 1
-#endif
-// <o> NRF_CRYPTO_ALLOCATOR  - Memory allocator
- 
-
-// <i> Choose memory allocator used by nrf_crypto. Default is alloca if possible or nrf_malloc otherwise. If 'User macros' are selected, the user has to create 'nrf_crypto_allocator.h' file that contains NRF_CRYPTO_ALLOC, NRF_CRYPTO_FREE, and NRF_CRYPTO_ALLOC_ON_STACK.
-// <0=> Default 
-// <1=> User macros 
-// <2=> On stack (alloca) 
-// <3=> C dynamic memory (malloc) 
-// <4=> SDK Memory Manager (nrf_malloc) 
-
-#ifndef NRF_CRYPTO_ALLOCATOR
-#define NRF_CRYPTO_ALLOCATOR 0
-#endif
-
-// <e> NRF_CRYPTO_BACKEND_CC310_BL_ENABLED - Enable the ARM Cryptocell CC310 reduced backend.
-
-// <i> The CC310 hardware-accelerated cryptography backend with reduced functionality and footprint (only available on nRF52840).
-//==========================================================
-#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_BL_ENABLED 0
-#endif
-// <q> NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED  - Enable the secp224r1 elliptic curve support using CC310_BL.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED 0
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED  - Enable the secp256r1 elliptic curve support using CC310_BL.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED  - CC310_BL SHA-256 hash functionality.
- 
-
-// <i> CC310_BL backend implementation for hardware-accelerated SHA-256.
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED  - nrf_cc310_bl buffers to RAM before running hash operation
- 
-
-// <i> Enabling this makes hashing of addresses in FLASH range possible. Size of buffer allocated for hashing is set by NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED 0
-#endif
-
-// <o> NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - nrf_cc310_bl hash outputs digests in little endian 
-// <i> Makes the nrf_cc310_bl hash functions output digests in little endian format. Only for use in nRF SDK DFU!
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE
-#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE 4096
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED  - Enable Interrupts while support using CC310 bl.
- 
-
-// <i> Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED 1
-#endif
-
-// </e>
-
-// <e> NRF_CRYPTO_BACKEND_CC310_ENABLED - Enable the ARM Cryptocell CC310 backend.
-
-// <i> The CC310 hardware-accelerated cryptography backend (only available on nRF52840).
-//==========================================================
-#ifndef NRF_CRYPTO_BACKEND_CC310_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ENABLED 0
-#endif
-// <q> NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED  - Enable the AES CBC mode using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED  - Enable the AES CTR mode using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED  - Enable the AES ECB mode using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED  - Enable the AES CBC_MAC mode using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED  - Enable the AES CMAC mode using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED  - Enable the AES CCM mode using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED  - Enable the AES CCM* mode using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED  - Enable the CHACHA-POLY mode using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED  - Enable the secp160r1 elliptic curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED  - Enable the secp160r2 elliptic curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED  - Enable the secp192r1 elliptic curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED  - Enable the secp224r1 elliptic curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED  - Enable the secp256r1 elliptic curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED  - Enable the secp384r1 elliptic curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED  - Enable the secp521r1 elliptic curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED  - Enable the secp160k1 elliptic curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED  - Enable the secp192k1 elliptic curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED  - Enable the secp224k1 elliptic curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED  - Enable the secp256k1 elliptic curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED  - Enable the Curve25519 curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED  - Enable the Ed25519 curve support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED  - CC310 SHA-256 hash functionality.
- 
-
-// <i> CC310 backend implementation for hardware-accelerated SHA-256.
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED  - CC310 SHA-512 hash functionality
- 
-
-// <i> CC310 backend implementation for SHA-512 (in software).
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED  - CC310 HMAC using SHA-256
- 
-
-// <i> CC310 backend implementation for HMAC using hardware-accelerated SHA-256.
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED  - CC310 HMAC using SHA-512
- 
-
-// <i> CC310 backend implementation for HMAC using SHA-512 (in software).
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED  - Enable RNG support using CC310.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED  - Enable Interrupts while support using CC310.
- 
-
-// <i> Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used
-
-#ifndef NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED
-#define NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED 1
-#endif
-
-// </e>
-
-// <e> NRF_CRYPTO_BACKEND_CIFRA_ENABLED - Enable the Cifra backend.
-//==========================================================
-#ifndef NRF_CRYPTO_BACKEND_CIFRA_ENABLED
-#define NRF_CRYPTO_BACKEND_CIFRA_ENABLED 0
-#endif
-// <q> NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED  - Enable the AES EAX mode using Cifra.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED
-#define NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED 1
-#endif
-
-// </e>
-
-// <e> NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED - Enable the mbed TLS backend.
-//==========================================================
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED 0
-#endif
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED  - Enable the AES CBC mode mbed TLS.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED  - Enable the AES CTR mode using mbed TLS.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED  - Enable the AES CFB mode using mbed TLS.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED  - Enable the AES ECB mode using mbed TLS.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED  - Enable the AES CBC MAC mode using mbed TLS.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED  - Enable the AES CMAC mode using mbed TLS.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED  - Enable the AES CCM mode using mbed TLS.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED  - Enable the AES GCM mode using mbed TLS.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED  - Enable secp192r1 (NIST 192-bit) curve
- 
-
-// <i> Enable this setting if you need secp192r1 (NIST 192-bit) support using MBEDTLS
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED  - Enable secp224r1 (NIST 224-bit) curve
- 
-
-// <i> Enable this setting if you need secp224r1 (NIST 224-bit) support using MBEDTLS
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED  - Enable secp256r1 (NIST 256-bit) curve
- 
-
-// <i> Enable this setting if you need secp256r1 (NIST 256-bit) support using MBEDTLS
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED  - Enable secp384r1 (NIST 384-bit) curve
- 
-
-// <i> Enable this setting if you need secp384r1 (NIST 384-bit) support using MBEDTLS
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED  - Enable secp521r1 (NIST 521-bit) curve
- 
-
-// <i> Enable this setting if you need secp521r1 (NIST 521-bit) support using MBEDTLS
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED  - Enable secp192k1 (Koblitz 192-bit) curve
- 
-
-// <i> Enable this setting if you need secp192k1 (Koblitz 192-bit) support using MBEDTLS
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED  - Enable secp224k1 (Koblitz 224-bit) curve
- 
-
-// <i> Enable this setting if you need secp224k1 (Koblitz 224-bit) support using MBEDTLS
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED  - Enable secp256k1 (Koblitz 256-bit) curve
- 
-
-// <i> Enable this setting if you need secp256k1 (Koblitz 256-bit) support using MBEDTLS
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED  - Enable bp256r1 (Brainpool 256-bit) curve
- 
-
-// <i> Enable this setting if you need bp256r1 (Brainpool 256-bit) support using MBEDTLS
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED  - Enable bp384r1 (Brainpool 384-bit) curve
- 
-
-// <i> Enable this setting if you need bp384r1 (Brainpool 384-bit) support using MBEDTLS
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED  - Enable bp512r1 (Brainpool 512-bit) curve
- 
-
-// <i> Enable this setting if you need bp512r1 (Brainpool 512-bit) support using MBEDTLS
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED  - Enable Curve25519 curve
- 
-
-// <i> Enable this setting if you need Curve25519 support using MBEDTLS
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED  - Enable mbed TLS SHA-256 hash functionality.
- 
-
-// <i> mbed TLS backend implementation for SHA-256.
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED  - Enable mbed TLS SHA-512 hash functionality.
- 
-
-// <i> mbed TLS backend implementation for SHA-512.
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED  - Enable mbed TLS HMAC using SHA-256.
- 
-
-// <i> mbed TLS backend implementation for HMAC using SHA-256.
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED  - Enable mbed TLS HMAC using SHA-512.
- 
-
-// <i> mbed TLS backend implementation for HMAC using SHA-512.
-
-#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED
-#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED 1
-#endif
-
-// </e>
-
-// <e> NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED - Enable the micro-ecc backend.
-//==========================================================
-#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED
-#define NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED 0
-#endif
-// <q> NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED  - Enable secp192r1 (NIST 192-bit) curve
- 
-
-// <i> Enable this setting if you need secp192r1 (NIST 192-bit) support using micro-ecc
-
-#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED
-#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED  - Enable secp224r1 (NIST 224-bit) curve
- 
-
-// <i> Enable this setting if you need secp224r1 (NIST 224-bit) support using micro-ecc
-
-#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED
-#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED  - Enable secp256r1 (NIST 256-bit) curve
- 
-
-// <i> Enable this setting if you need secp256r1 (NIST 256-bit) support using micro-ecc
-
-#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED
-#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED  - Enable secp256k1 (Koblitz 256-bit) curve
- 
-
-// <i> Enable this setting if you need secp256k1 (Koblitz 256-bit) support using micro-ecc
-
-#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED
-#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED 1
-#endif
-
-// </e>
-
-// <e> NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED - Enable the nRF HW RNG backend.
-
-// <i> The nRF HW backend provide access to RNG peripheral in nRF5x devices.
-//==========================================================
-#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED
-#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 0
-#endif
-// <q> NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED  - Enable mbed TLS CTR-DRBG algorithm.
- 
-
-// <i> Enable mbed TLS CTR-DRBG standardized by NIST (NIST SP 800-90A Rev. 1). The nRF HW RNG is used as an entropy source for seeding.
-
-#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED
-#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED 1
-#endif
-
-// </e>
-
-// <e> NRF_CRYPTO_BACKEND_NRF_SW_ENABLED - Enable the legacy nRFx sw for crypto.
-
-// <i> The nRF SW cryptography backend (only used in bootloader context).
-//==========================================================
-#ifndef NRF_CRYPTO_BACKEND_NRF_SW_ENABLED
-#define NRF_CRYPTO_BACKEND_NRF_SW_ENABLED 0
-#endif
-// <q> NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED  - nRF SW hash backend support for SHA-256
- 
-
-// <i> The nRF SW backend provide access to nRF SDK legacy hash implementation of SHA-256.
-
-#ifndef NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED
-#define NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED 1
-#endif
-
-// </e>
-
-// <e> NRF_CRYPTO_BACKEND_OBERON_ENABLED - Enable the Oberon backend
-
-// <i> The Oberon backend
-//==========================================================
-#ifndef NRF_CRYPTO_BACKEND_OBERON_ENABLED
-#define NRF_CRYPTO_BACKEND_OBERON_ENABLED 0
-#endif
-// <q> NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED  - Enable the CHACHA-POLY mode using Oberon.
- 
-
-#ifndef NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED
-#define NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED  - Enable secp256r1 curve
- 
-
-// <i> Enable this setting if you need secp256r1 curve support using Oberon library
-
-#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED
-#define NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED  - Enable Curve25519 ECDH
- 
-
-// <i> Enable this setting if you need Curve25519 ECDH support using Oberon library
-
-#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED
-#define NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED  - Enable Ed25519 signature scheme
- 
-
-// <i> Enable this setting if you need Ed25519 support using Oberon library
-
-#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED
-#define NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED  - Oberon SHA-256 hash functionality
- 
-
-// <i> Oberon backend implementation for SHA-256.
-
-#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED
-#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED  - Oberon SHA-512 hash functionality
- 
-
-// <i> Oberon backend implementation for SHA-512.
-
-#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED
-#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED  - Oberon HMAC using SHA-256
- 
-
-// <i> Oberon backend implementation for HMAC using SHA-256.
-
-#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED
-#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED 1
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED  - Oberon HMAC using SHA-512
- 
-
-// <i> Oberon backend implementation for HMAC using SHA-512.
-
-#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED
-#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED 1
-#endif
-
-// </e>
-
-// <e> NRF_CRYPTO_BACKEND_OPTIGA_ENABLED - Enable the nrf_crypto Optiga Trust X backend.
-
-// <i> Enables the nrf_crypto backend for Optiga Trust X devices.
-//==========================================================
-#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ENABLED
-#define NRF_CRYPTO_BACKEND_OPTIGA_ENABLED 0
-#endif
-// <q> NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED  - Optiga backend support for RNG
- 
-
-// <i> The Optiga backend provide external chip RNG.
-
-#ifndef NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED
-#define NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED 0
-#endif
-
-// <q> NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED  - Optiga backend support for ECC secp256r1
- 
-
-// <i> The Optiga backend provide external chip ECC using secp256r1.
-
-#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED
-#define NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED 1
-#endif
-
-// </e>
-
-// <q> NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED  - Big-endian byte order in raw Curve25519 data
- 
-
-// <i> Enable big-endian byte order in Curve25519 API, if set to 1. Use little-endian, if set to 0.
-
-#ifndef NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED
-#define NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED 0
-#endif
-
-// </e>
-
-// </h> 
-//==========================================================
-
-// <h> nRF_DFU 
-
-//==========================================================
-// <h> ble_dfu - Device Firmware Update
-
-//==========================================================
-// <q> BLE_DFU_ENABLED  - Enable DFU Service.
- 
-
-#ifndef BLE_DFU_ENABLED
-#define BLE_DFU_ENABLED 0
-#endif
-
-// <q> NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS  - Buttonless DFU supports bonds.
- 
-
-#ifndef NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS
-#define NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS 0
-#endif
-
-// </h> 
-//==========================================================
-
-// </h> 
-//==========================================================
-
-// <h> nRF_Drivers 
-
-//==========================================================
-// <e> COMP_ENABLED - nrf_drv_comp - COMP peripheral driver - legacy layer
-//==========================================================
-#ifndef COMP_ENABLED
-#define COMP_ENABLED 0
-#endif
-// <o> COMP_CONFIG_REF  - Reference voltage
- 
-// <0=> Internal 1.2V 
-// <1=> Internal 1.8V 
-// <2=> Internal 2.4V 
-// <4=> VDD 
-// <7=> ARef 
-
-#ifndef COMP_CONFIG_REF
-#define COMP_CONFIG_REF 1
-#endif
-
-// <o> COMP_CONFIG_MAIN_MODE  - Main mode
- 
-// <0=> Single ended 
-// <1=> Differential 
-
-#ifndef COMP_CONFIG_MAIN_MODE
-#define COMP_CONFIG_MAIN_MODE 0
-#endif
-
-// <o> COMP_CONFIG_SPEED_MODE  - Speed mode
- 
-// <0=> Low power 
-// <1=> Normal 
-// <2=> High speed 
-
-#ifndef COMP_CONFIG_SPEED_MODE
-#define COMP_CONFIG_SPEED_MODE 2
-#endif
-
-// <o> COMP_CONFIG_HYST  - Hystheresis
- 
-// <0=> No 
-// <1=> 50mV 
-
-#ifndef COMP_CONFIG_HYST
-#define COMP_CONFIG_HYST 0
-#endif
-
-// <o> COMP_CONFIG_ISOURCE  - Current Source
- 
-// <0=> Off 
-// <1=> 2.5 uA 
-// <2=> 5 uA 
-// <3=> 10 uA 
-
-#ifndef COMP_CONFIG_ISOURCE
-#define COMP_CONFIG_ISOURCE 0
-#endif
-
-// <o> COMP_CONFIG_INPUT  - Analog input
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef COMP_CONFIG_INPUT
-#define COMP_CONFIG_INPUT 0
-#endif
-
-// <o> COMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef COMP_CONFIG_IRQ_PRIORITY
-#define COMP_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// </e>
-
-// <q> EGU_ENABLED  - nrf_drv_swi - SWI(EGU) peripheral driver - legacy layer
- 
-
-#ifndef EGU_ENABLED
-#define EGU_ENABLED 0
-#endif
-
-// <e> GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver - legacy layer
-//==========================================================
-#ifndef GPIOTE_ENABLED
-#define GPIOTE_ENABLED 0
-#endif
-// <o> GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins 
-#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
-#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
-#endif
-
-// <o> GPIOTE_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef GPIOTE_CONFIG_IRQ_PRIORITY
-#define GPIOTE_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// </e>
-
-// <e> I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver - legacy layer
-//==========================================================
-#ifndef I2S_ENABLED
-#define I2S_ENABLED 0
-#endif
-// <o> I2S_CONFIG_SCK_PIN - SCK pin  <0-31> 
-
-
-#ifndef I2S_CONFIG_SCK_PIN
-#define I2S_CONFIG_SCK_PIN 31
-#endif
-
-// <o> I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31> 
-
-
-#ifndef I2S_CONFIG_LRCK_PIN
-#define I2S_CONFIG_LRCK_PIN 30
-#endif
-
-// <o> I2S_CONFIG_MCK_PIN - MCK pin 
-#ifndef I2S_CONFIG_MCK_PIN
-#define I2S_CONFIG_MCK_PIN 255
-#endif
-
-// <o> I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31> 
-
-
-#ifndef I2S_CONFIG_SDOUT_PIN
-#define I2S_CONFIG_SDOUT_PIN 29
-#endif
-
-// <o> I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31> 
-
-
-#ifndef I2S_CONFIG_SDIN_PIN
-#define I2S_CONFIG_SDIN_PIN 28
-#endif
-
-// <o> I2S_CONFIG_MASTER  - Mode
- 
-// <0=> Master 
-// <1=> Slave 
-
-#ifndef I2S_CONFIG_MASTER
-#define I2S_CONFIG_MASTER 0
-#endif
-
-// <o> I2S_CONFIG_FORMAT  - Format
- 
-// <0=> I2S 
-// <1=> Aligned 
-
-#ifndef I2S_CONFIG_FORMAT
-#define I2S_CONFIG_FORMAT 0
-#endif
-
-// <o> I2S_CONFIG_ALIGN  - Alignment
- 
-// <0=> Left 
-// <1=> Right 
-
-#ifndef I2S_CONFIG_ALIGN
-#define I2S_CONFIG_ALIGN 0
-#endif
-
-// <o> I2S_CONFIG_SWIDTH  - Sample width (bits)
- 
-// <0=> 8 
-// <1=> 16 
-// <2=> 24 
-
-#ifndef I2S_CONFIG_SWIDTH
-#define I2S_CONFIG_SWIDTH 1
-#endif
-
-// <o> I2S_CONFIG_CHANNELS  - Channels
- 
-// <0=> Stereo 
-// <1=> Left 
-// <2=> Right 
-
-#ifndef I2S_CONFIG_CHANNELS
-#define I2S_CONFIG_CHANNELS 1
-#endif
-
-// <o> I2S_CONFIG_MCK_SETUP  - MCK behavior
- 
-// <0=> Disabled 
-// <2147483648=> 32MHz/2 
-// <1342177280=> 32MHz/3 
-// <1073741824=> 32MHz/4 
-// <805306368=> 32MHz/5 
-// <671088640=> 32MHz/6 
-// <536870912=> 32MHz/8 
-// <402653184=> 32MHz/10 
-// <369098752=> 32MHz/11 
-// <285212672=> 32MHz/15 
-// <268435456=> 32MHz/16 
-// <201326592=> 32MHz/21 
-// <184549376=> 32MHz/23 
-// <142606336=> 32MHz/30 
-// <138412032=> 32MHz/31 
-// <134217728=> 32MHz/32 
-// <100663296=> 32MHz/42 
-// <68157440=> 32MHz/63 
-// <34340864=> 32MHz/125 
-
-#ifndef I2S_CONFIG_MCK_SETUP
-#define I2S_CONFIG_MCK_SETUP 536870912
-#endif
-
-// <o> I2S_CONFIG_RATIO  - MCK/LRCK ratio
- 
-// <0=> 32x 
-// <1=> 48x 
-// <2=> 64x 
-// <3=> 96x 
-// <4=> 128x 
-// <5=> 192x 
-// <6=> 256x 
-// <7=> 384x 
-// <8=> 512x 
-
-#ifndef I2S_CONFIG_RATIO
-#define I2S_CONFIG_RATIO 2000
-#endif
-
-// <o> I2S_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef I2S_CONFIG_IRQ_PRIORITY
-#define I2S_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef I2S_CONFIG_LOG_ENABLED
-#define I2S_CONFIG_LOG_ENABLED 0
-#endif
-// <o> I2S_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef I2S_CONFIG_LOG_LEVEL
-#define I2S_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> I2S_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef I2S_CONFIG_INFO_COLOR
-#define I2S_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> I2S_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef I2S_CONFIG_DEBUG_COLOR
-#define I2S_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver - legacy layer
-//==========================================================
-#ifndef LPCOMP_ENABLED
-#define LPCOMP_ENABLED 0
-#endif
-// <o> LPCOMP_CONFIG_REFERENCE  - Reference voltage
- 
-// <0=> Supply 1/8 
-// <1=> Supply 2/8 
-// <2=> Supply 3/8 
-// <3=> Supply 4/8 
-// <4=> Supply 5/8 
-// <5=> Supply 6/8 
-// <6=> Supply 7/8 
-// <8=> Supply 1/16 (nRF52) 
-// <9=> Supply 3/16 (nRF52) 
-// <10=> Supply 5/16 (nRF52) 
-// <11=> Supply 7/16 (nRF52) 
-// <12=> Supply 9/16 (nRF52) 
-// <13=> Supply 11/16 (nRF52) 
-// <14=> Supply 13/16 (nRF52) 
-// <15=> Supply 15/16 (nRF52) 
-// <7=> External Ref 0 
-// <65543=> External Ref 1 
-
-#ifndef LPCOMP_CONFIG_REFERENCE
-#define LPCOMP_CONFIG_REFERENCE 3
-#endif
-
-// <o> LPCOMP_CONFIG_DETECTION  - Detection
- 
-// <0=> Crossing 
-// <1=> Up 
-// <2=> Down 
-
-#ifndef LPCOMP_CONFIG_DETECTION
-#define LPCOMP_CONFIG_DETECTION 2
-#endif
-
-// <o> LPCOMP_CONFIG_INPUT  - Analog input
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef LPCOMP_CONFIG_INPUT
-#define LPCOMP_CONFIG_INPUT 0
-#endif
-
-// <q> LPCOMP_CONFIG_HYST  - Hysteresis
- 
-
-#ifndef LPCOMP_CONFIG_HYST
-#define LPCOMP_CONFIG_HYST 0
-#endif
-
-// <o> LPCOMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef LPCOMP_CONFIG_IRQ_PRIORITY
-#define LPCOMP_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// </e>
-
-// <e> NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver
-//==========================================================
-#ifndef NRFX_CLOCK_ENABLED
-#define NRFX_CLOCK_ENABLED 0
-#endif
-// <o> NRFX_CLOCK_CONFIG_LF_SRC  - LF Clock Source
- 
-// <0=> RC 
-// <1=> XTAL 
-// <2=> Synth 
-// <131073=> External Low Swing 
-// <196609=> External Full Swing 
-
-#ifndef NRFX_CLOCK_CONFIG_LF_SRC
-#define NRFX_CLOCK_CONFIG_LF_SRC 1
-#endif
-
-// <o> NRFX_CLOCK_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY
-#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED
-#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_CLOCK_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
-#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_CLOCK_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR
-#define NRFX_CLOCK_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_CLOCK_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR
-#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver
-//==========================================================
-#ifndef NRFX_COMP_ENABLED
-#define NRFX_COMP_ENABLED 0
-#endif
-// <o> NRFX_COMP_CONFIG_REF  - Reference voltage
- 
-// <0=> Internal 1.2V 
-// <1=> Internal 1.8V 
-// <2=> Internal 2.4V 
-// <4=> VDD 
-// <7=> ARef 
-
-#ifndef NRFX_COMP_CONFIG_REF
-#define NRFX_COMP_CONFIG_REF 1
-#endif
-
-// <o> NRFX_COMP_CONFIG_MAIN_MODE  - Main mode
- 
-// <0=> Single ended 
-// <1=> Differential 
-
-#ifndef NRFX_COMP_CONFIG_MAIN_MODE
-#define NRFX_COMP_CONFIG_MAIN_MODE 0
-#endif
-
-// <o> NRFX_COMP_CONFIG_SPEED_MODE  - Speed mode
- 
-// <0=> Low power 
-// <1=> Normal 
-// <2=> High speed 
-
-#ifndef NRFX_COMP_CONFIG_SPEED_MODE
-#define NRFX_COMP_CONFIG_SPEED_MODE 2
-#endif
-
-// <o> NRFX_COMP_CONFIG_HYST  - Hystheresis
- 
-// <0=> No 
-// <1=> 50mV 
-
-#ifndef NRFX_COMP_CONFIG_HYST
-#define NRFX_COMP_CONFIG_HYST 0
-#endif
-
-// <o> NRFX_COMP_CONFIG_ISOURCE  - Current Source
- 
-// <0=> Off 
-// <1=> 2.5 uA 
-// <2=> 5 uA 
-// <3=> 10 uA 
-
-#ifndef NRFX_COMP_CONFIG_ISOURCE
-#define NRFX_COMP_CONFIG_ISOURCE 0
-#endif
-
-// <o> NRFX_COMP_CONFIG_INPUT  - Analog input
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_COMP_CONFIG_INPUT
-#define NRFX_COMP_CONFIG_INPUT 0
-#endif
-
-// <o> NRFX_COMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY
-#define NRFX_COMP_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_COMP_CONFIG_LOG_ENABLED
-#define NRFX_COMP_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_COMP_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_COMP_CONFIG_LOG_LEVEL
-#define NRFX_COMP_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_COMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_COMP_CONFIG_INFO_COLOR
-#define NRFX_COMP_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_COMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR
-#define NRFX_COMP_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver
-//==========================================================
-#ifndef NRFX_GPIOTE_ENABLED
-#define NRFX_GPIOTE_ENABLED 0
-#endif
-// <o> NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins 
-#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
-#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
-#endif
-
-// <o> NRFX_GPIOTE_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY
-#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
-#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_GPIOTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
-#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_GPIOTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR
-#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_GPIOTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR
-#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver
-//==========================================================
-#ifndef NRFX_I2S_ENABLED
-#define NRFX_I2S_ENABLED 0
-#endif
-// <o> NRFX_I2S_CONFIG_SCK_PIN - SCK pin  <0-31> 
-
-
-#ifndef NRFX_I2S_CONFIG_SCK_PIN
-#define NRFX_I2S_CONFIG_SCK_PIN 31
-#endif
-
-// <o> NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31> 
-
-
-#ifndef NRFX_I2S_CONFIG_LRCK_PIN
-#define NRFX_I2S_CONFIG_LRCK_PIN 30
-#endif
-
-// <o> NRFX_I2S_CONFIG_MCK_PIN - MCK pin 
-#ifndef NRFX_I2S_CONFIG_MCK_PIN
-#define NRFX_I2S_CONFIG_MCK_PIN 255
-#endif
-
-// <o> NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31> 
-
-
-#ifndef NRFX_I2S_CONFIG_SDOUT_PIN
-#define NRFX_I2S_CONFIG_SDOUT_PIN 29
-#endif
-
-// <o> NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31> 
-
-
-#ifndef NRFX_I2S_CONFIG_SDIN_PIN
-#define NRFX_I2S_CONFIG_SDIN_PIN 28
-#endif
-
-// <o> NRFX_I2S_CONFIG_MASTER  - Mode
- 
-// <0=> Master 
-// <1=> Slave 
-
-#ifndef NRFX_I2S_CONFIG_MASTER
-#define NRFX_I2S_CONFIG_MASTER 0
-#endif
-
-// <o> NRFX_I2S_CONFIG_FORMAT  - Format
- 
-// <0=> I2S 
-// <1=> Aligned 
-
-#ifndef NRFX_I2S_CONFIG_FORMAT
-#define NRFX_I2S_CONFIG_FORMAT 0
-#endif
-
-// <o> NRFX_I2S_CONFIG_ALIGN  - Alignment
- 
-// <0=> Left 
-// <1=> Right 
-
-#ifndef NRFX_I2S_CONFIG_ALIGN
-#define NRFX_I2S_CONFIG_ALIGN 0
-#endif
-
-// <o> NRFX_I2S_CONFIG_SWIDTH  - Sample width (bits)
- 
-// <0=> 8 
-// <1=> 16 
-// <2=> 24 
-
-#ifndef NRFX_I2S_CONFIG_SWIDTH
-#define NRFX_I2S_CONFIG_SWIDTH 1
-#endif
-
-// <o> NRFX_I2S_CONFIG_CHANNELS  - Channels
- 
-// <0=> Stereo 
-// <1=> Left 
-// <2=> Right 
-
-#ifndef NRFX_I2S_CONFIG_CHANNELS
-#define NRFX_I2S_CONFIG_CHANNELS 1
-#endif
-
-// <o> NRFX_I2S_CONFIG_MCK_SETUP  - MCK behavior
- 
-// <0=> Disabled 
-// <2147483648=> 32MHz/2 
-// <1342177280=> 32MHz/3 
-// <1073741824=> 32MHz/4 
-// <805306368=> 32MHz/5 
-// <671088640=> 32MHz/6 
-// <536870912=> 32MHz/8 
-// <402653184=> 32MHz/10 
-// <369098752=> 32MHz/11 
-// <285212672=> 32MHz/15 
-// <268435456=> 32MHz/16 
-// <201326592=> 32MHz/21 
-// <184549376=> 32MHz/23 
-// <142606336=> 32MHz/30 
-// <138412032=> 32MHz/31 
-// <134217728=> 32MHz/32 
-// <100663296=> 32MHz/42 
-// <68157440=> 32MHz/63 
-// <34340864=> 32MHz/125 
-
-#ifndef NRFX_I2S_CONFIG_MCK_SETUP
-#define NRFX_I2S_CONFIG_MCK_SETUP 536870912
-#endif
-
-// <o> NRFX_I2S_CONFIG_RATIO  - MCK/LRCK ratio
- 
-// <0=> 32x 
-// <1=> 48x 
-// <2=> 64x 
-// <3=> 96x 
-// <4=> 128x 
-// <5=> 192x 
-// <6=> 256x 
-// <7=> 384x 
-// <8=> 512x 
-
-#ifndef NRFX_I2S_CONFIG_RATIO
-#define NRFX_I2S_CONFIG_RATIO 2000
-#endif
-
-// <o> NRFX_I2S_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_I2S_CONFIG_IRQ_PRIORITY
-#define NRFX_I2S_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
-#define NRFX_I2S_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_I2S_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
-#define NRFX_I2S_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_I2S_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_I2S_CONFIG_INFO_COLOR
-#define NRFX_I2S_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_I2S_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR
-#define NRFX_I2S_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver
-//==========================================================
-#ifndef NRFX_LPCOMP_ENABLED
-#define NRFX_LPCOMP_ENABLED 0
-#endif
-// <o> NRFX_LPCOMP_CONFIG_REFERENCE  - Reference voltage
- 
-// <0=> Supply 1/8 
-// <1=> Supply 2/8 
-// <2=> Supply 3/8 
-// <3=> Supply 4/8 
-// <4=> Supply 5/8 
-// <5=> Supply 6/8 
-// <6=> Supply 7/8 
-// <8=> Supply 1/16 (nRF52) 
-// <9=> Supply 3/16 (nRF52) 
-// <10=> Supply 5/16 (nRF52) 
-// <11=> Supply 7/16 (nRF52) 
-// <12=> Supply 9/16 (nRF52) 
-// <13=> Supply 11/16 (nRF52) 
-// <14=> Supply 13/16 (nRF52) 
-// <15=> Supply 15/16 (nRF52) 
-// <7=> External Ref 0 
-// <65543=> External Ref 1 
-
-#ifndef NRFX_LPCOMP_CONFIG_REFERENCE
-#define NRFX_LPCOMP_CONFIG_REFERENCE 3
-#endif
-
-// <o> NRFX_LPCOMP_CONFIG_DETECTION  - Detection
- 
-// <0=> Crossing 
-// <1=> Up 
-// <2=> Down 
-
-#ifndef NRFX_LPCOMP_CONFIG_DETECTION
-#define NRFX_LPCOMP_CONFIG_DETECTION 2
-#endif
-
-// <o> NRFX_LPCOMP_CONFIG_INPUT  - Analog input
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_LPCOMP_CONFIG_INPUT
-#define NRFX_LPCOMP_CONFIG_INPUT 0
-#endif
-
-// <q> NRFX_LPCOMP_CONFIG_HYST  - Hysteresis
- 
-
-#ifndef NRFX_LPCOMP_CONFIG_HYST
-#define NRFX_LPCOMP_CONFIG_HYST 0
-#endif
-
-// <o> NRFX_LPCOMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY
-#define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED
-#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_LPCOMP_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
-#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_LPCOMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR
-#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_LPCOMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR
-#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_NFCT_ENABLED - nrfx_nfct - NFCT peripheral driver
-//==========================================================
-#ifndef NRFX_NFCT_ENABLED
-#define NRFX_NFCT_ENABLED 0
-#endif
-// <o> NRFX_NFCT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_NFCT_CONFIG_IRQ_PRIORITY
-#define NRFX_NFCT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_NFCT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED
-#define NRFX_NFCT_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_NFCT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL
-#define NRFX_NFCT_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_NFCT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_NFCT_CONFIG_INFO_COLOR
-#define NRFX_NFCT_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_NFCT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_NFCT_CONFIG_DEBUG_COLOR
-#define NRFX_NFCT_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver
-//==========================================================
-#ifndef NRFX_PDM_ENABLED
-#define NRFX_PDM_ENABLED 0
-#endif
-// <o> NRFX_PDM_CONFIG_MODE  - Mode
- 
-// <0=> Stereo 
-// <1=> Mono 
-
-#ifndef NRFX_PDM_CONFIG_MODE
-#define NRFX_PDM_CONFIG_MODE 1
-#endif
-
-// <o> NRFX_PDM_CONFIG_EDGE  - Edge
- 
-// <0=> Left falling 
-// <1=> Left rising 
-
-#ifndef NRFX_PDM_CONFIG_EDGE
-#define NRFX_PDM_CONFIG_EDGE 0
-#endif
-
-// <o> NRFX_PDM_CONFIG_CLOCK_FREQ  - Clock frequency
- 
-// <134217728=> 1000k 
-// <138412032=> 1032k (default) 
-// <142606336=> 1067k 
-
-#ifndef NRFX_PDM_CONFIG_CLOCK_FREQ
-#define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032
-#endif
-
-// <o> NRFX_PDM_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY
-#define NRFX_PDM_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
-#define NRFX_PDM_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_PDM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
-#define NRFX_PDM_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_PDM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_PDM_CONFIG_INFO_COLOR
-#define NRFX_PDM_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_PDM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR
-#define NRFX_PDM_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver
-//==========================================================
-#ifndef NRFX_POWER_ENABLED
-#define NRFX_POWER_ENABLED 0
-#endif
-// <o> NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-// <q> NRFX_POWER_CONFIG_DEFAULT_DCDCEN  - The default configuration of main DCDC regulator
- 
-
-// <i> This settings means only that components for DCDC regulator are installed and it can be enabled.
-
-#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN
-#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0
-#endif
-
-// <q> NRFX_POWER_CONFIG_DEFAULT_DCDCENHV  - The default configuration of High Voltage DCDC regulator
- 
-
-// <i> This settings means only that components for DCDC regulator are installed and it can be enabled.
-
-#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV
-#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0
-#endif
-
-// </e>
-
-// <e> NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator
-//==========================================================
-#ifndef NRFX_PPI_ENABLED
-#define NRFX_PPI_ENABLED 0
-#endif
-// <e> NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_PPI_CONFIG_LOG_ENABLED
-#define NRFX_PPI_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_PPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_PPI_CONFIG_LOG_LEVEL
-#define NRFX_PPI_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_PPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_PPI_CONFIG_INFO_COLOR
-#define NRFX_PPI_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_PPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR
-#define NRFX_PPI_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver
-//==========================================================
-#ifndef NRFX_PWM_ENABLED
-#define NRFX_PWM_ENABLED 0
-#endif
-// <q> NRFX_PWM0_ENABLED  - Enable PWM0 instance
- 
-
-#ifndef NRFX_PWM0_ENABLED
-#define NRFX_PWM0_ENABLED 0
-#endif
-
-// <q> NRFX_PWM1_ENABLED  - Enable PWM1 instance
- 
-
-#ifndef NRFX_PWM1_ENABLED
-#define NRFX_PWM1_ENABLED 0
-#endif
-
-// <q> NRFX_PWM2_ENABLED  - Enable PWM2 instance
- 
-
-#ifndef NRFX_PWM2_ENABLED
-#define NRFX_PWM2_ENABLED 0
-#endif
-
-// <q> NRFX_PWM3_ENABLED  - Enable PWM3 instance
- 
-
-#ifndef NRFX_PWM3_ENABLED
-#define NRFX_PWM3_ENABLED 0
-#endif
-
-// <o> NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31> 
-
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN
-#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31
-#endif
-
-// <o> NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31> 
-
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN
-#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31
-#endif
-
-// <o> NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31> 
-
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN
-#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31
-#endif
-
-// <o> NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31> 
-
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN
-#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31
-#endif
-
-// <o> NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK  - Base clock
- 
-// <0=> 16 MHz 
-// <1=> 8 MHz 
-// <2=> 4 MHz 
-// <3=> 2 MHz 
-// <4=> 1 MHz 
-// <5=> 500 kHz 
-// <6=> 250 kHz 
-// <7=> 125 kHz 
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK
-#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4
-#endif
-
-// <o> NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE  - Count mode
- 
-// <0=> Up 
-// <1=> Up and Down 
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE
-#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0
-#endif
-
-// <o> NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value 
-#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE
-#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000
-#endif
-
-// <o> NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE  - Load mode
- 
-// <0=> Common 
-// <1=> Grouped 
-// <2=> Individual 
-// <3=> Waveform 
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE
-#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0
-#endif
-
-// <o> NRFX_PWM_DEFAULT_CONFIG_STEP_MODE  - Step mode
- 
-// <0=> Auto 
-// <1=> Triggered 
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE
-#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0
-#endif
-
-// <o> NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
-#define NRFX_PWM_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_PWM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
-#define NRFX_PWM_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_PWM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_PWM_CONFIG_INFO_COLOR
-#define NRFX_PWM_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_PWM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR
-#define NRFX_PWM_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver
-//==========================================================
-#ifndef NRFX_QDEC_ENABLED
-#define NRFX_QDEC_ENABLED 0
-#endif
-// <o> NRFX_QDEC_CONFIG_REPORTPER  - Report period
- 
-// <0=> 10 Samples 
-// <1=> 40 Samples 
-// <2=> 80 Samples 
-// <3=> 120 Samples 
-// <4=> 160 Samples 
-// <5=> 200 Samples 
-// <6=> 240 Samples 
-// <7=> 280 Samples 
-
-#ifndef NRFX_QDEC_CONFIG_REPORTPER
-#define NRFX_QDEC_CONFIG_REPORTPER 0
-#endif
-
-// <o> NRFX_QDEC_CONFIG_SAMPLEPER  - Sample period
- 
-// <0=> 128 us 
-// <1=> 256 us 
-// <2=> 512 us 
-// <3=> 1024 us 
-// <4=> 2048 us 
-// <5=> 4096 us 
-// <6=> 8192 us 
-// <7=> 16384 us 
-
-#ifndef NRFX_QDEC_CONFIG_SAMPLEPER
-#define NRFX_QDEC_CONFIG_SAMPLEPER 7
-#endif
-
-// <o> NRFX_QDEC_CONFIG_PIO_A - A pin  <0-31> 
-
-
-#ifndef NRFX_QDEC_CONFIG_PIO_A
-#define NRFX_QDEC_CONFIG_PIO_A 31
-#endif
-
-// <o> NRFX_QDEC_CONFIG_PIO_B - B pin  <0-31> 
-
-
-#ifndef NRFX_QDEC_CONFIG_PIO_B
-#define NRFX_QDEC_CONFIG_PIO_B 31
-#endif
-
-// <o> NRFX_QDEC_CONFIG_PIO_LED - LED pin  <0-31> 
-
-
-#ifndef NRFX_QDEC_CONFIG_PIO_LED
-#define NRFX_QDEC_CONFIG_PIO_LED 31
-#endif
-
-// <o> NRFX_QDEC_CONFIG_LEDPRE - LED pre 
-#ifndef NRFX_QDEC_CONFIG_LEDPRE
-#define NRFX_QDEC_CONFIG_LEDPRE 511
-#endif
-
-// <o> NRFX_QDEC_CONFIG_LEDPOL  - LED polarity
- 
-// <0=> Active low 
-// <1=> Active high 
-
-#ifndef NRFX_QDEC_CONFIG_LEDPOL
-#define NRFX_QDEC_CONFIG_LEDPOL 1
-#endif
-
-// <q> NRFX_QDEC_CONFIG_DBFEN  - Debouncing enable
- 
-
-#ifndef NRFX_QDEC_CONFIG_DBFEN
-#define NRFX_QDEC_CONFIG_DBFEN 0
-#endif
-
-// <q> NRFX_QDEC_CONFIG_SAMPLE_INTEN  - Sample ready interrupt enable
- 
-
-#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN
-#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0
-#endif
-
-// <o> NRFX_QDEC_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY
-#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED
-#define NRFX_QDEC_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_QDEC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
-#define NRFX_QDEC_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_QDEC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_QDEC_CONFIG_INFO_COLOR
-#define NRFX_QDEC_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_QDEC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR
-#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver
-//==========================================================
-#ifndef NRFX_QSPI_ENABLED
-#define NRFX_QSPI_ENABLED 0
-#endif
-// <o> NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255> 
-
-
-#ifndef NRFX_QSPI_CONFIG_SCK_DELAY
-#define NRFX_QSPI_CONFIG_SCK_DELAY 1
-#endif
-
-// <o> NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. 
-#ifndef NRFX_QSPI_CONFIG_XIP_OFFSET
-#define NRFX_QSPI_CONFIG_XIP_OFFSET 0
-#endif
-
-// <o> NRFX_QSPI_CONFIG_READOC  - Number of data lines and opcode used for reading.
- 
-// <0=> FastRead 
-// <1=> Read2O 
-// <2=> Read2IO 
-// <3=> Read4O 
-// <4=> Read4IO 
-
-#ifndef NRFX_QSPI_CONFIG_READOC
-#define NRFX_QSPI_CONFIG_READOC 0
-#endif
-
-// <o> NRFX_QSPI_CONFIG_WRITEOC  - Number of data lines and opcode used for writing.
- 
-// <0=> PP 
-// <1=> PP2O 
-// <2=> PP4O 
-// <3=> PP4IO 
-
-#ifndef NRFX_QSPI_CONFIG_WRITEOC
-#define NRFX_QSPI_CONFIG_WRITEOC 0
-#endif
-
-// <o> NRFX_QSPI_CONFIG_ADDRMODE  - Addressing mode.
- 
-// <0=> 24bit 
-// <1=> 32bit 
-
-#ifndef NRFX_QSPI_CONFIG_ADDRMODE
-#define NRFX_QSPI_CONFIG_ADDRMODE 0
-#endif
-
-// <o> NRFX_QSPI_CONFIG_MODE  - SPI mode.
- 
-// <0=> Mode 0 
-// <1=> Mode 1 
-
-#ifndef NRFX_QSPI_CONFIG_MODE
-#define NRFX_QSPI_CONFIG_MODE 0
-#endif
-
-// <o> NRFX_QSPI_CONFIG_FREQUENCY  - Frequency divider.
- 
-// <0=> 32MHz/1 
-// <1=> 32MHz/2 
-// <2=> 32MHz/3 
-// <3=> 32MHz/4 
-// <4=> 32MHz/5 
-// <5=> 32MHz/6 
-// <6=> 32MHz/7 
-// <7=> 32MHz/8 
-// <8=> 32MHz/9 
-// <9=> 32MHz/10 
-// <10=> 32MHz/11 
-// <11=> 32MHz/12 
-// <12=> 32MHz/13 
-// <13=> 32MHz/14 
-// <14=> 32MHz/15 
-// <15=> 32MHz/16 
-
-#ifndef NRFX_QSPI_CONFIG_FREQUENCY
-#define NRFX_QSPI_CONFIG_FREQUENCY 15
-#endif
-
-// <s> NRFX_QSPI_PIN_SCK - SCK pin value.
-#ifndef NRFX_QSPI_PIN_SCK
-#define NRFX_QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED
-#endif
-
-// <s> NRFX_QSPI_PIN_CSN - CSN pin value.
-#ifndef NRFX_QSPI_PIN_CSN
-#define NRFX_QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED
-#endif
-
-// <s> NRFX_QSPI_PIN_IO0 - IO0 pin value.
-#ifndef NRFX_QSPI_PIN_IO0
-#define NRFX_QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED
-#endif
-
-// <s> NRFX_QSPI_PIN_IO1 - IO1 pin value.
-#ifndef NRFX_QSPI_PIN_IO1
-#define NRFX_QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED
-#endif
-
-// <s> NRFX_QSPI_PIN_IO2 - IO2 pin value.
-#ifndef NRFX_QSPI_PIN_IO2
-#define NRFX_QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED
-#endif
-
-// <s> NRFX_QSPI_PIN_IO3 - IO3 pin value.
-#ifndef NRFX_QSPI_PIN_IO3
-#define NRFX_QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED
-#endif
-
-// <o> NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// </e>
-
-// <e> NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver
-//==========================================================
-#ifndef NRFX_RNG_ENABLED
-#define NRFX_RNG_ENABLED 0
-#endif
-// <q> NRFX_RNG_CONFIG_ERROR_CORRECTION  - Error correction
- 
-
-#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION
-#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1
-#endif
-
-// <o> NRFX_RNG_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY
-#define NRFX_RNG_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_RNG_CONFIG_LOG_ENABLED
-#define NRFX_RNG_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_RNG_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_RNG_CONFIG_LOG_LEVEL
-#define NRFX_RNG_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_RNG_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_RNG_CONFIG_INFO_COLOR
-#define NRFX_RNG_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_RNG_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR
-#define NRFX_RNG_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver
-//==========================================================
-#ifndef NRFX_RTC_ENABLED
-#define NRFX_RTC_ENABLED 0
-#endif
-// <q> NRFX_RTC0_ENABLED  - Enable RTC0 instance
- 
-
-#ifndef NRFX_RTC0_ENABLED
-#define NRFX_RTC0_ENABLED 0
-#endif
-
-// <q> NRFX_RTC1_ENABLED  - Enable RTC1 instance
- 
-
-#ifndef NRFX_RTC1_ENABLED
-#define NRFX_RTC1_ENABLED 0
-#endif
-
-// <q> NRFX_RTC2_ENABLED  - Enable RTC2 instance
- 
-
-#ifndef NRFX_RTC2_ENABLED
-#define NRFX_RTC2_ENABLED 0
-#endif
-
-// <o> NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt 
-#ifndef NRFX_RTC_MAXIMUM_LATENCY_US
-#define NRFX_RTC_MAXIMUM_LATENCY_US 2000
-#endif
-
-// <o> NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768> 
-
-
-#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY
-#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768
-#endif
-
-// <q> NRFX_RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
- 
-
-#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE
-#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0
-#endif
-
-// <o> NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
-#define NRFX_RTC_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_RTC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
-#define NRFX_RTC_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_RTC_CONFIG_INFO_COLOR
-#define NRFX_RTC_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR
-#define NRFX_RTC_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver
-//==========================================================
-#ifndef NRFX_SAADC_ENABLED
-#define NRFX_SAADC_ENABLED 0
-#endif
-// <o> NRFX_SAADC_CONFIG_RESOLUTION  - Resolution
- 
-// <0=> 8 bit 
-// <1=> 10 bit 
-// <2=> 12 bit 
-// <3=> 14 bit 
-
-#ifndef NRFX_SAADC_CONFIG_RESOLUTION
-#define NRFX_SAADC_CONFIG_RESOLUTION 1
-#endif
-
-// <o> NRFX_SAADC_CONFIG_OVERSAMPLE  - Sample period
- 
-// <0=> Disabled 
-// <1=> 2x 
-// <2=> 4x 
-// <3=> 8x 
-// <4=> 16x 
-// <5=> 32x 
-// <6=> 64x 
-// <7=> 128x 
-// <8=> 256x 
-
-#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE
-#define NRFX_SAADC_CONFIG_OVERSAMPLE 0
-#endif
-
-// <q> NRFX_SAADC_CONFIG_LP_MODE  - Enabling low power mode
- 
-
-#ifndef NRFX_SAADC_CONFIG_LP_MODE
-#define NRFX_SAADC_CONFIG_LP_MODE 0
-#endif
-
-// <o> NRFX_SAADC_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY
-#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
-#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_SAADC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
-#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_SAADC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_SAADC_CONFIG_INFO_COLOR
-#define NRFX_SAADC_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_SAADC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR
-#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver
-//==========================================================
-#ifndef NRFX_SPIM_ENABLED
-#define NRFX_SPIM_ENABLED 0
-#endif
-// <q> NRFX_SPIM0_ENABLED  - Enable SPIM0 instance
- 
-
-#ifndef NRFX_SPIM0_ENABLED
-#define NRFX_SPIM0_ENABLED 0
-#endif
-
-// <q> NRFX_SPIM1_ENABLED  - Enable SPIM1 instance
- 
-
-#ifndef NRFX_SPIM1_ENABLED
-#define NRFX_SPIM1_ENABLED 0
-#endif
-
-// <q> NRFX_SPIM2_ENABLED  - Enable SPIM2 instance
- 
-
-#ifndef NRFX_SPIM2_ENABLED
-#define NRFX_SPIM2_ENABLED 0
-#endif
-
-// <q> NRFX_SPIM3_ENABLED  - Enable SPIM3 instance
- 
-
-#ifndef NRFX_SPIM3_ENABLED
-#define NRFX_SPIM3_ENABLED 0
-#endif
-
-// <q> NRFX_SPIM_EXTENDED_ENABLED  - Enable extended SPIM features
- 
-
-#ifndef NRFX_SPIM_EXTENDED_ENABLED
-#define NRFX_SPIM_EXTENDED_ENABLED 0
-#endif
-
-// <o> NRFX_SPIM_MISO_PULL_CFG  - MISO pin pull configuration.
- 
-// <0=> NRF_GPIO_PIN_NOPULL 
-// <1=> NRF_GPIO_PIN_PULLDOWN 
-// <3=> NRF_GPIO_PIN_PULLUP 
-
-#ifndef NRFX_SPIM_MISO_PULL_CFG
-#define NRFX_SPIM_MISO_PULL_CFG 1
-#endif
-
-// <o> NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
-#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_SPIM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
-#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_SPIM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_SPIM_CONFIG_INFO_COLOR
-#define NRFX_SPIM_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_SPIM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR
-#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
-//==========================================================
-#ifndef NRFX_SPIS_ENABLED
-#define NRFX_SPIS_ENABLED 0
-#endif
-// <q> NRFX_SPIS0_ENABLED  - Enable SPIS0 instance
- 
-
-#ifndef NRFX_SPIS0_ENABLED
-#define NRFX_SPIS0_ENABLED 0
-#endif
-
-// <q> NRFX_SPIS1_ENABLED  - Enable SPIS1 instance
- 
-
-#ifndef NRFX_SPIS1_ENABLED
-#define NRFX_SPIS1_ENABLED 0
-#endif
-
-// <q> NRFX_SPIS2_ENABLED  - Enable SPIS2 instance
- 
-
-#ifndef NRFX_SPIS2_ENABLED
-#define NRFX_SPIS2_ENABLED 0
-#endif
-
-// <o> NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <o> NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255> 
-
-
-#ifndef NRFX_SPIS_DEFAULT_DEF
-#define NRFX_SPIS_DEFAULT_DEF 255
-#endif
-
-// <o> NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255> 
-
-
-#ifndef NRFX_SPIS_DEFAULT_ORC
-#define NRFX_SPIS_DEFAULT_ORC 255
-#endif
-
-// <e> NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
-#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_SPIS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
-#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_SPIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_SPIS_CONFIG_INFO_COLOR
-#define NRFX_SPIS_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_SPIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR
-#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
-//==========================================================
-#ifndef NRFX_SPI_ENABLED
-#define NRFX_SPI_ENABLED 0
-#endif
-// <q> NRFX_SPI0_ENABLED  - Enable SPI0 instance
- 
-
-#ifndef NRFX_SPI0_ENABLED
-#define NRFX_SPI0_ENABLED 0
-#endif
-
-// <q> NRFX_SPI1_ENABLED  - Enable SPI1 instance
- 
-
-#ifndef NRFX_SPI1_ENABLED
-#define NRFX_SPI1_ENABLED 0
-#endif
-
-// <q> NRFX_SPI2_ENABLED  - Enable SPI2 instance
- 
-
-#ifndef NRFX_SPI2_ENABLED
-#define NRFX_SPI2_ENABLED 0
-#endif
-
-// <o> NRFX_SPI_MISO_PULL_CFG  - MISO pin pull configuration.
- 
-// <0=> NRF_GPIO_PIN_NOPULL 
-// <1=> NRF_GPIO_PIN_PULLDOWN 
-// <3=> NRF_GPIO_PIN_PULLUP 
-
-#ifndef NRFX_SPI_MISO_PULL_CFG
-#define NRFX_SPI_MISO_PULL_CFG 1
-#endif
-
-// <o> NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SPI_CONFIG_LOG_ENABLED
-#define NRFX_SPI_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_SPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_SPI_CONFIG_LOG_LEVEL
-#define NRFX_SPI_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_SPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_SPI_CONFIG_INFO_COLOR
-#define NRFX_SPI_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_SPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR
-#define NRFX_SPI_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator
-//==========================================================
-#ifndef NRFX_SWI_ENABLED
-#define NRFX_SWI_ENABLED 0
-#endif
-// <q> NRFX_EGU_ENABLED  - Enable EGU support
- 
-
-#ifndef NRFX_EGU_ENABLED
-#define NRFX_EGU_ENABLED 0
-#endif
-
-// <q> NRFX_SWI0_DISABLED  - Exclude SWI0 from being utilized by the driver
- 
-
-#ifndef NRFX_SWI0_DISABLED
-#define NRFX_SWI0_DISABLED 0
-#endif
-
-// <q> NRFX_SWI1_DISABLED  - Exclude SWI1 from being utilized by the driver
- 
-
-#ifndef NRFX_SWI1_DISABLED
-#define NRFX_SWI1_DISABLED 0
-#endif
-
-// <q> NRFX_SWI2_DISABLED  - Exclude SWI2 from being utilized by the driver
- 
-
-#ifndef NRFX_SWI2_DISABLED
-#define NRFX_SWI2_DISABLED 0
-#endif
-
-// <q> NRFX_SWI3_DISABLED  - Exclude SWI3 from being utilized by the driver
- 
-
-#ifndef NRFX_SWI3_DISABLED
-#define NRFX_SWI3_DISABLED 0
-#endif
-
-// <q> NRFX_SWI4_DISABLED  - Exclude SWI4 from being utilized by the driver
- 
-
-#ifndef NRFX_SWI4_DISABLED
-#define NRFX_SWI4_DISABLED 0
-#endif
-
-// <q> NRFX_SWI5_DISABLED  - Exclude SWI5 from being utilized by the driver
- 
-
-#ifndef NRFX_SWI5_DISABLED
-#define NRFX_SWI5_DISABLED 0
-#endif
-
-// <e> NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_SWI_CONFIG_LOG_ENABLED
-#define NRFX_SWI_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_SWI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_SWI_CONFIG_LOG_LEVEL
-#define NRFX_SWI_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_SWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_SWI_CONFIG_INFO_COLOR
-#define NRFX_SWI_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_SWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR
-#define NRFX_SWI_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver
-//==========================================================
-#ifndef NRFX_TIMER_ENABLED
-#define NRFX_TIMER_ENABLED 0
-#endif
-// <q> NRFX_TIMER0_ENABLED  - Enable TIMER0 instance
- 
-
-#ifndef NRFX_TIMER0_ENABLED
-#define NRFX_TIMER0_ENABLED 0
-#endif
-
-// <q> NRFX_TIMER1_ENABLED  - Enable TIMER1 instance
- 
-
-#ifndef NRFX_TIMER1_ENABLED
-#define NRFX_TIMER1_ENABLED 0
-#endif
-
-// <q> NRFX_TIMER2_ENABLED  - Enable TIMER2 instance
- 
-
-#ifndef NRFX_TIMER2_ENABLED
-#define NRFX_TIMER2_ENABLED 0
-#endif
-
-// <q> NRFX_TIMER3_ENABLED  - Enable TIMER3 instance
- 
-
-#ifndef NRFX_TIMER3_ENABLED
-#define NRFX_TIMER3_ENABLED 0
-#endif
-
-// <q> NRFX_TIMER4_ENABLED  - Enable TIMER4 instance
- 
-
-#ifndef NRFX_TIMER4_ENABLED
-#define NRFX_TIMER4_ENABLED 0
-#endif
-
-// <o> NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY  - Timer frequency if in Timer mode
- 
-// <0=> 16 MHz 
-// <1=> 8 MHz 
-// <2=> 4 MHz 
-// <3=> 2 MHz 
-// <4=> 1 MHz 
-// <5=> 500 kHz 
-// <6=> 250 kHz 
-// <7=> 125 kHz 
-// <8=> 62.5 kHz 
-// <9=> 31.25 kHz 
-
-#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY
-#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0
-#endif
-
-// <o> NRFX_TIMER_DEFAULT_CONFIG_MODE  - Timer mode or operation
- 
-// <0=> Timer 
-// <1=> Counter 
-
-#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE
-#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0
-#endif
-
-// <o> NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH  - Timer counter bit width
- 
-// <0=> 16 bit 
-// <1=> 8 bit 
-// <2=> 24 bit 
-// <3=> 32 bit 
-
-#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH
-#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
-#endif
-
-// <o> NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
-#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_TIMER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
-#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_TIMER_CONFIG_INFO_COLOR
-#define NRFX_TIMER_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR
-#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver
-//==========================================================
-#ifndef NRFX_TWIM_ENABLED
-#define NRFX_TWIM_ENABLED 0
-#endif
-// <q> NRFX_TWIM0_ENABLED  - Enable TWIM0 instance
- 
-
-#ifndef NRFX_TWIM0_ENABLED
-#define NRFX_TWIM0_ENABLED 0
-#endif
-
-// <q> NRFX_TWIM1_ENABLED  - Enable TWIM1 instance
- 
-
-#ifndef NRFX_TWIM1_ENABLED
-#define NRFX_TWIM1_ENABLED 0
-#endif
-
-// <o> NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY  - Frequency
- 
-// <26738688=> 100k 
-// <67108864=> 250k 
-// <104857600=> 400k 
-
-#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY
-#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688
-#endif
-
-// <q> NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
- 
-
-#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT
-#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
-#endif
-
-// <o> NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
-#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_TWIM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
-#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_TWIM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_TWIM_CONFIG_INFO_COLOR
-#define NRFX_TWIM_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_TWIM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR
-#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver
-//==========================================================
-#ifndef NRFX_TWIS_ENABLED
-#define NRFX_TWIS_ENABLED 0
-#endif
-// <q> NRFX_TWIS0_ENABLED  - Enable TWIS0 instance
- 
-
-#ifndef NRFX_TWIS0_ENABLED
-#define NRFX_TWIS0_ENABLED 0
-#endif
-
-// <q> NRFX_TWIS1_ENABLED  - Enable TWIS1 instance
- 
-
-#ifndef NRFX_TWIS1_ENABLED
-#define NRFX_TWIS1_ENABLED 0
-#endif
-
-// <q> NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY  - Assume that any instance would be initialized only once
- 
-
-// <i> Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
-
-#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
-#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
-#endif
-
-// <q> NRFX_TWIS_NO_SYNC_MODE  - Remove support for synchronous mode
- 
-
-// <i> Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
-
-#ifndef NRFX_TWIS_NO_SYNC_MODE
-#define NRFX_TWIS_NO_SYNC_MODE 0
-#endif
-
-// <o> NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0 
-#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0
-#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0
-#endif
-
-// <o> NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1 
-#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1
-#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0
-#endif
-
-// <o> NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL  - SCL pin pull configuration
- 
-// <0=> Disabled 
-// <1=> Pull down 
-// <3=> Pull up 
-
-#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL
-#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0
-#endif
-
-// <o> NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL  - SDA pin pull configuration
- 
-// <0=> Disabled 
-// <1=> Pull down 
-// <3=> Pull up 
-
-#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL
-#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0
-#endif
-
-// <o> NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
-#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_TWIS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
-#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_TWIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_TWIS_CONFIG_INFO_COLOR
-#define NRFX_TWIS_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_TWIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR
-#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver
-//==========================================================
-#ifndef NRFX_TWI_ENABLED
-#define NRFX_TWI_ENABLED 0
-#endif
-// <q> NRFX_TWI0_ENABLED  - Enable TWI0 instance
- 
-
-#ifndef NRFX_TWI0_ENABLED
-#define NRFX_TWI0_ENABLED 0
-#endif
-
-// <q> NRFX_TWI1_ENABLED  - Enable TWI1 instance
- 
-
-#ifndef NRFX_TWI1_ENABLED
-#define NRFX_TWI1_ENABLED 0
-#endif
-
-// <o> NRFX_TWI_DEFAULT_CONFIG_FREQUENCY  - Frequency
- 
-// <26738688=> 100k 
-// <67108864=> 250k 
-// <104857600=> 400k 
-
-#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY
-#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688
-#endif
-
-// <q> NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
- 
-
-#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
-#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
-#endif
-
-// <o> NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_TWI_CONFIG_LOG_ENABLED
-#define NRFX_TWI_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_TWI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_TWI_CONFIG_LOG_LEVEL
-#define NRFX_TWI_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_TWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_TWI_CONFIG_INFO_COLOR
-#define NRFX_TWI_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_TWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR
-#define NRFX_TWI_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver
-//==========================================================
-#ifndef NRFX_UARTE_ENABLED
-#define NRFX_UARTE_ENABLED 0
-#endif
-// <o> NRFX_UARTE0_ENABLED - Enable UARTE0 instance 
-#ifndef NRFX_UARTE0_ENABLED
-#define NRFX_UARTE0_ENABLED 0
-#endif
-
-// <o> NRFX_UARTE1_ENABLED - Enable UARTE1 instance 
-#ifndef NRFX_UARTE1_ENABLED
-#define NRFX_UARTE1_ENABLED 0
-#endif
-
-// <o> NRFX_UARTE_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
- 
-// <0=> Disabled 
-// <1=> Enabled 
-
-#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC
-#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0
-#endif
-
-// <o> NRFX_UARTE_DEFAULT_CONFIG_PARITY  - Parity
- 
-// <0=> Excluded 
-// <14=> Included 
-
-#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY
-#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0
-#endif
-
-// <o> NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
- 
-// <323584=> 1200 baud 
-// <643072=> 2400 baud 
-// <1290240=> 4800 baud 
-// <2576384=> 9600 baud 
-// <3862528=> 14400 baud 
-// <5152768=> 19200 baud 
-// <7716864=> 28800 baud 
-// <8388608=> 31250 baud 
-// <10289152=> 38400 baud 
-// <15007744=> 56000 baud 
-// <15400960=> 57600 baud 
-// <20615168=> 76800 baud 
-// <30801920=> 115200 baud 
-// <61865984=> 230400 baud 
-// <67108864=> 250000 baud 
-// <121634816=> 460800 baud 
-// <251658240=> 921600 baud 
-// <268435456=> 1000000 baud 
-
-#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE
-#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920
-#endif
-
-// <o> NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
-#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_UARTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
-#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_UARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_UARTE_CONFIG_INFO_COLOR
-#define NRFX_UARTE_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_UARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR
-#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver
-//==========================================================
-#ifndef NRFX_UART_ENABLED
-#define NRFX_UART_ENABLED 0
-#endif
-// <o> NRFX_UART0_ENABLED - Enable UART0 instance 
-#ifndef NRFX_UART0_ENABLED
-#define NRFX_UART0_ENABLED 0
-#endif
-
-// <o> NRFX_UART_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
- 
-// <0=> Disabled 
-// <1=> Enabled 
-
-#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC
-#define NRFX_UART_DEFAULT_CONFIG_HWFC 0
-#endif
-
-// <o> NRFX_UART_DEFAULT_CONFIG_PARITY  - Parity
- 
-// <0=> Excluded 
-// <14=> Included 
-
-#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY
-#define NRFX_UART_DEFAULT_CONFIG_PARITY 0
-#endif
-
-// <o> NRFX_UART_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
- 
-// <323584=> 1200 baud 
-// <643072=> 2400 baud 
-// <1290240=> 4800 baud 
-// <2576384=> 9600 baud 
-// <3866624=> 14400 baud 
-// <5152768=> 19200 baud 
-// <7729152=> 28800 baud 
-// <8388608=> 31250 baud 
-// <10309632=> 38400 baud 
-// <15007744=> 56000 baud 
-// <15462400=> 57600 baud 
-// <20615168=> 76800 baud 
-// <30924800=> 115200 baud 
-// <61845504=> 230400 baud 
-// <67108864=> 250000 baud 
-// <123695104=> 460800 baud 
-// <247386112=> 921600 baud 
-// <268435456=> 1000000 baud 
-
-#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE
-#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800
-#endif
-
-// <o> NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
-#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 4
-#endif
-
-// <e> NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_UART_CONFIG_LOG_ENABLED
-#define NRFX_UART_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_UART_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_UART_CONFIG_LOG_LEVEL
-#define NRFX_UART_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_UART_CONFIG_INFO_COLOR
-#define NRFX_UART_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_UART_CONFIG_DEBUG_COLOR
-#define NRFX_UART_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRFX_USBD_ENABLED - nrfx_usbd - USBD peripheral driver
-//==========================================================
-#ifndef NRFX_USBD_ENABLED
-#define NRFX_USBD_ENABLED 0
-#endif
-// <o> NRFX_USBD_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_USBD_CONFIG_IRQ_PRIORITY
-#define NRFX_USBD_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <o> NRFX_USBD_CONFIG_DMASCHEDULER_MODE  - USBD DMA scheduler working scheme
- 
-// <0=> Prioritized access 
-// <1=> Round Robin 
-
-#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_MODE
-#define NRFX_USBD_CONFIG_DMASCHEDULER_MODE 0
-#endif
-
-// <q> NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST  - Give priority to isochronous transfers
- 
-
-// <i> This option gives priority to isochronous transfers.
-// <i> Enabling it assures that isochronous transfers are always processed,
-// <i> even if multiple other transfers are pending.
-// <i> Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm
-// <i> function is called, so the option is independent of the algorithm chosen.
-
-#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST
-#define NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1
-#endif
-
-// <q> NRFX_USBD_CONFIG_ISO_IN_ZLP  - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
- 
-
-// <i> If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
-// <i> Else, there will be no response.
-
-#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP
-#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0
-#endif
-
-// </e>
-
-// <e> NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver
-//==========================================================
-#ifndef NRFX_WDT_ENABLED
-#define NRFX_WDT_ENABLED 0
-#endif
-// <o> NRFX_WDT_CONFIG_BEHAVIOUR  - WDT behavior in CPU SLEEP or HALT mode
- 
-// <1=> Run in SLEEP, Pause in HALT 
-// <8=> Pause in SLEEP, Run in HALT 
-// <9=> Run in SLEEP and HALT 
-// <0=> Pause in SLEEP and HALT 
-
-#ifndef NRFX_WDT_CONFIG_BEHAVIOUR
-#define NRFX_WDT_CONFIG_BEHAVIOUR 1
-#endif
-
-// <o> NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295> 
-
-
-#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE
-#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000
-#endif
-
-// <o> NRFX_WDT_CONFIG_NO_IRQ  - Remove WDT IRQ handling from WDT driver
- 
-// <0=> Include WDT IRQ handling 
-// <1=> Remove WDT IRQ handling 
-
-#ifndef NRFX_WDT_CONFIG_NO_IRQ
-#define NRFX_WDT_CONFIG_NO_IRQ 0
-#endif
-
-// <o> NRFX_WDT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY
-#define NRFX_WDT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
-#define NRFX_WDT_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_WDT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
-#define NRFX_WDT_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_WDT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_WDT_CONFIG_INFO_COLOR
-#define NRFX_WDT_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_WDT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR
-#define NRFX_WDT_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRF_CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver - legacy layer
-//==========================================================
-#ifndef NRF_CLOCK_ENABLED
-#define NRF_CLOCK_ENABLED 0
-#endif
-// <o> CLOCK_CONFIG_LF_SRC  - LF Clock Source
- 
-// <0=> RC 
-// <1=> XTAL 
-// <2=> Synth 
-// <131073=> External Low Swing 
-// <196609=> External Full Swing 
-
-#ifndef CLOCK_CONFIG_LF_SRC
-#define CLOCK_CONFIG_LF_SRC 1
-#endif
-
-// <q> CLOCK_CONFIG_LF_CAL_ENABLED  - Calibration enable for LF Clock Source
- 
-
-#ifndef CLOCK_CONFIG_LF_CAL_ENABLED
-#define CLOCK_CONFIG_LF_CAL_ENABLED 0
-#endif
-
-// <o> CLOCK_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef CLOCK_CONFIG_IRQ_PRIORITY
-#define CLOCK_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// </e>
-
-// <e> PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver - legacy layer
-//==========================================================
-#ifndef PDM_ENABLED
-#define PDM_ENABLED 0
-#endif
-// <o> PDM_CONFIG_MODE  - Mode
- 
-// <0=> Stereo 
-// <1=> Mono 
-
-#ifndef PDM_CONFIG_MODE
-#define PDM_CONFIG_MODE 1
-#endif
-
-// <o> PDM_CONFIG_EDGE  - Edge
- 
-// <0=> Left falling 
-// <1=> Left rising 
-
-#ifndef PDM_CONFIG_EDGE
-#define PDM_CONFIG_EDGE 0
-#endif
-
-// <o> PDM_CONFIG_CLOCK_FREQ  - Clock frequency
- 
-// <134217728=> 1000k 
-// <138412032=> 1032k (default) 
-// <142606336=> 1067k 
-
-#ifndef PDM_CONFIG_CLOCK_FREQ
-#define PDM_CONFIG_CLOCK_FREQ 138412032
-#endif
-
-// <o> PDM_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef PDM_CONFIG_IRQ_PRIORITY
-#define PDM_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// </e>
-
-// <e> POWER_ENABLED - nrf_drv_power - POWER peripheral driver - legacy layer
-//==========================================================
-#ifndef POWER_ENABLED
-#define POWER_ENABLED 0
-#endif
-// <o> POWER_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef POWER_CONFIG_IRQ_PRIORITY
-#define POWER_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <q> POWER_CONFIG_DEFAULT_DCDCEN  - The default configuration of main DCDC regulator
- 
-
-// <i> This settings means only that components for DCDC regulator are installed and it can be enabled.
-
-#ifndef POWER_CONFIG_DEFAULT_DCDCEN
-#define POWER_CONFIG_DEFAULT_DCDCEN 0
-#endif
-
-// <q> POWER_CONFIG_DEFAULT_DCDCENHV  - The default configuration of High Voltage DCDC regulator
- 
-
-// <i> This settings means only that components for DCDC regulator are installed and it can be enabled.
-
-#ifndef POWER_CONFIG_DEFAULT_DCDCENHV
-#define POWER_CONFIG_DEFAULT_DCDCENHV 0
-#endif
-
-// </e>
-
-// <q> PPI_ENABLED  - nrf_drv_ppi - PPI peripheral driver - legacy layer
- 
-
-#ifndef PPI_ENABLED
-#define PPI_ENABLED 0
-#endif
-
-// <e> PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver - legacy layer
-//==========================================================
-#ifndef PWM_ENABLED
-#define PWM_ENABLED 0
-#endif
-// <o> PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31> 
-
-
-#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN
-#define PWM_DEFAULT_CONFIG_OUT0_PIN 31
-#endif
-
-// <o> PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31> 
-
-
-#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN
-#define PWM_DEFAULT_CONFIG_OUT1_PIN 31
-#endif
-
-// <o> PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31> 
-
-
-#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN
-#define PWM_DEFAULT_CONFIG_OUT2_PIN 31
-#endif
-
-// <o> PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31> 
-
-
-#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN
-#define PWM_DEFAULT_CONFIG_OUT3_PIN 31
-#endif
-
-// <o> PWM_DEFAULT_CONFIG_BASE_CLOCK  - Base clock
- 
-// <0=> 16 MHz 
-// <1=> 8 MHz 
-// <2=> 4 MHz 
-// <3=> 2 MHz 
-// <4=> 1 MHz 
-// <5=> 500 kHz 
-// <6=> 250 kHz 
-// <7=> 125 kHz 
-
-#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK
-#define PWM_DEFAULT_CONFIG_BASE_CLOCK 4
-#endif
-
-// <o> PWM_DEFAULT_CONFIG_COUNT_MODE  - Count mode
- 
-// <0=> Up 
-// <1=> Up and Down 
-
-#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE
-#define PWM_DEFAULT_CONFIG_COUNT_MODE 0
-#endif
-
-// <o> PWM_DEFAULT_CONFIG_TOP_VALUE - Top value 
-#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE
-#define PWM_DEFAULT_CONFIG_TOP_VALUE 1000
-#endif
-
-// <o> PWM_DEFAULT_CONFIG_LOAD_MODE  - Load mode
- 
-// <0=> Common 
-// <1=> Grouped 
-// <2=> Individual 
-// <3=> Waveform 
-
-#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE
-#define PWM_DEFAULT_CONFIG_LOAD_MODE 0
-#endif
-
-// <o> PWM_DEFAULT_CONFIG_STEP_MODE  - Step mode
- 
-// <0=> Auto 
-// <1=> Triggered 
-
-#ifndef PWM_DEFAULT_CONFIG_STEP_MODE
-#define PWM_DEFAULT_CONFIG_STEP_MODE 0
-#endif
-
-// <o> PWM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <q> PWM0_ENABLED  - Enable PWM0 instance
- 
-
-#ifndef PWM0_ENABLED
-#define PWM0_ENABLED 0
-#endif
-
-// <q> PWM1_ENABLED  - Enable PWM1 instance
- 
-
-#ifndef PWM1_ENABLED
-#define PWM1_ENABLED 0
-#endif
-
-// <q> PWM2_ENABLED  - Enable PWM2 instance
- 
-
-#ifndef PWM2_ENABLED
-#define PWM2_ENABLED 0
-#endif
-
-// <q> PWM3_ENABLED  - Enable PWM3 instance
- 
-
-#ifndef PWM3_ENABLED
-#define PWM3_ENABLED 0
-#endif
-
-// </e>
-
-// <e> QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver - legacy layer
-//==========================================================
-#ifndef QDEC_ENABLED
-#define QDEC_ENABLED 0
-#endif
-// <o> QDEC_CONFIG_REPORTPER  - Report period
- 
-// <0=> 10 Samples 
-// <1=> 40 Samples 
-// <2=> 80 Samples 
-// <3=> 120 Samples 
-// <4=> 160 Samples 
-// <5=> 200 Samples 
-// <6=> 240 Samples 
-// <7=> 280 Samples 
-
-#ifndef QDEC_CONFIG_REPORTPER
-#define QDEC_CONFIG_REPORTPER 0
-#endif
-
-// <o> QDEC_CONFIG_SAMPLEPER  - Sample period
- 
-// <0=> 128 us 
-// <1=> 256 us 
-// <2=> 512 us 
-// <3=> 1024 us 
-// <4=> 2048 us 
-// <5=> 4096 us 
-// <6=> 8192 us 
-// <7=> 16384 us 
-
-#ifndef QDEC_CONFIG_SAMPLEPER
-#define QDEC_CONFIG_SAMPLEPER 7
-#endif
-
-// <o> QDEC_CONFIG_PIO_A - A pin  <0-31> 
-
-
-#ifndef QDEC_CONFIG_PIO_A
-#define QDEC_CONFIG_PIO_A 31
-#endif
-
-// <o> QDEC_CONFIG_PIO_B - B pin  <0-31> 
-
-
-#ifndef QDEC_CONFIG_PIO_B
-#define QDEC_CONFIG_PIO_B 31
-#endif
-
-// <o> QDEC_CONFIG_PIO_LED - LED pin  <0-31> 
-
-
-#ifndef QDEC_CONFIG_PIO_LED
-#define QDEC_CONFIG_PIO_LED 31
-#endif
-
-// <o> QDEC_CONFIG_LEDPRE - LED pre 
-#ifndef QDEC_CONFIG_LEDPRE
-#define QDEC_CONFIG_LEDPRE 511
-#endif
-
-// <o> QDEC_CONFIG_LEDPOL  - LED polarity
- 
-// <0=> Active low 
-// <1=> Active high 
-
-#ifndef QDEC_CONFIG_LEDPOL
-#define QDEC_CONFIG_LEDPOL 1
-#endif
-
-// <q> QDEC_CONFIG_DBFEN  - Debouncing enable
- 
-
-#ifndef QDEC_CONFIG_DBFEN
-#define QDEC_CONFIG_DBFEN 0
-#endif
-
-// <q> QDEC_CONFIG_SAMPLE_INTEN  - Sample ready interrupt enable
- 
-
-#ifndef QDEC_CONFIG_SAMPLE_INTEN
-#define QDEC_CONFIG_SAMPLE_INTEN 0
-#endif
-
-// <o> QDEC_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef QDEC_CONFIG_IRQ_PRIORITY
-#define QDEC_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// </e>
-
-// <e> QSPI_ENABLED - nrf_drv_qspi - QSPI peripheral driver - legacy layer
-//==========================================================
-#ifndef QSPI_ENABLED
-#define QSPI_ENABLED 0
-#endif
-// <o> QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255> 
-
-
-#ifndef QSPI_CONFIG_SCK_DELAY
-#define QSPI_CONFIG_SCK_DELAY 1
-#endif
-
-// <o> QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. 
-#ifndef QSPI_CONFIG_XIP_OFFSET
-#define QSPI_CONFIG_XIP_OFFSET 0
-#endif
-
-// <o> QSPI_CONFIG_READOC  - Number of data lines and opcode used for reading.
- 
-// <0=> FastRead 
-// <1=> Read2O 
-// <2=> Read2IO 
-// <3=> Read4O 
-// <4=> Read4IO 
-
-#ifndef QSPI_CONFIG_READOC
-#define QSPI_CONFIG_READOC 0
-#endif
-
-// <o> QSPI_CONFIG_WRITEOC  - Number of data lines and opcode used for writing.
- 
-// <0=> PP 
-// <1=> PP2O 
-// <2=> PP4O 
-// <3=> PP4IO 
-
-#ifndef QSPI_CONFIG_WRITEOC
-#define QSPI_CONFIG_WRITEOC 0
-#endif
-
-// <o> QSPI_CONFIG_ADDRMODE  - Addressing mode.
- 
-// <0=> 24bit 
-// <1=> 32bit 
-
-#ifndef QSPI_CONFIG_ADDRMODE
-#define QSPI_CONFIG_ADDRMODE 0
-#endif
-
-// <o> QSPI_CONFIG_MODE  - SPI mode.
- 
-// <0=> Mode 0 
-// <1=> Mode 1 
-
-#ifndef QSPI_CONFIG_MODE
-#define QSPI_CONFIG_MODE 0
-#endif
-
-// <o> QSPI_CONFIG_FREQUENCY  - Frequency divider.
- 
-// <0=> 32MHz/1 
-// <1=> 32MHz/2 
-// <2=> 32MHz/3 
-// <3=> 32MHz/4 
-// <4=> 32MHz/5 
-// <5=> 32MHz/6 
-// <6=> 32MHz/7 
-// <7=> 32MHz/8 
-// <8=> 32MHz/9 
-// <9=> 32MHz/10 
-// <10=> 32MHz/11 
-// <11=> 32MHz/12 
-// <12=> 32MHz/13 
-// <13=> 32MHz/14 
-// <14=> 32MHz/15 
-// <15=> 32MHz/16 
-
-#ifndef QSPI_CONFIG_FREQUENCY
-#define QSPI_CONFIG_FREQUENCY 15
-#endif
-
-// <s> QSPI_PIN_SCK - SCK pin value.
-#ifndef QSPI_PIN_SCK
-#define QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED
-#endif
-
-// <s> QSPI_PIN_CSN - CSN pin value.
-#ifndef QSPI_PIN_CSN
-#define QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED
-#endif
-
-// <s> QSPI_PIN_IO0 - IO0 pin value.
-#ifndef QSPI_PIN_IO0
-#define QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED
-#endif
-
-// <s> QSPI_PIN_IO1 - IO1 pin value.
-#ifndef QSPI_PIN_IO1
-#define QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED
-#endif
-
-// <s> QSPI_PIN_IO2 - IO2 pin value.
-#ifndef QSPI_PIN_IO2
-#define QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED
-#endif
-
-// <s> QSPI_PIN_IO3 - IO3 pin value.
-#ifndef QSPI_PIN_IO3
-#define QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED
-#endif
-
-// <o> QSPI_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef QSPI_CONFIG_IRQ_PRIORITY
-#define QSPI_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// </e>
-
-// <e> RNG_ENABLED - nrf_drv_rng - RNG peripheral driver - legacy layer
-//==========================================================
-#ifndef RNG_ENABLED
-#define RNG_ENABLED 0
-#endif
-// <q> RNG_CONFIG_ERROR_CORRECTION  - Error correction
- 
-
-#ifndef RNG_CONFIG_ERROR_CORRECTION
-#define RNG_CONFIG_ERROR_CORRECTION 1
-#endif
-
-// <o> RNG_CONFIG_POOL_SIZE - Pool size 
-#ifndef RNG_CONFIG_POOL_SIZE
-#define RNG_CONFIG_POOL_SIZE 64
-#endif
-
-// <o> RNG_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef RNG_CONFIG_IRQ_PRIORITY
-#define RNG_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// </e>
-
-// <e> RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver - legacy layer
-//==========================================================
-#ifndef RTC_ENABLED
-#define RTC_ENABLED 0
-#endif
-// <o> RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768> 
-
-
-#ifndef RTC_DEFAULT_CONFIG_FREQUENCY
-#define RTC_DEFAULT_CONFIG_FREQUENCY 32768
-#endif
-
-// <q> RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
- 
-
-#ifndef RTC_DEFAULT_CONFIG_RELIABLE
-#define RTC_DEFAULT_CONFIG_RELIABLE 0
-#endif
-
-// <o> RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <q> RTC0_ENABLED  - Enable RTC0 instance
- 
-
-#ifndef RTC0_ENABLED
-#define RTC0_ENABLED 0
-#endif
-
-// <q> RTC1_ENABLED  - Enable RTC1 instance
- 
-
-#ifndef RTC1_ENABLED
-#define RTC1_ENABLED 0
-#endif
-
-// <q> RTC2_ENABLED  - Enable RTC2 instance
- 
-
-#ifndef RTC2_ENABLED
-#define RTC2_ENABLED 0
-#endif
-
-// <o> NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt 
-#ifndef NRF_MAXIMUM_LATENCY_US
-#define NRF_MAXIMUM_LATENCY_US 2000
-#endif
-
-// </e>
-
-// <e> SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver - legacy layer
-//==========================================================
-#ifndef SAADC_ENABLED
-#define SAADC_ENABLED 0
-#endif
-// <o> SAADC_CONFIG_RESOLUTION  - Resolution
- 
-// <0=> 8 bit 
-// <1=> 10 bit 
-// <2=> 12 bit 
-// <3=> 14 bit 
-
-#ifndef SAADC_CONFIG_RESOLUTION
-#define SAADC_CONFIG_RESOLUTION 1
-#endif
-
-// <o> SAADC_CONFIG_OVERSAMPLE  - Sample period
- 
-// <0=> Disabled 
-// <1=> 2x 
-// <2=> 4x 
-// <3=> 8x 
-// <4=> 16x 
-// <5=> 32x 
-// <6=> 64x 
-// <7=> 128x 
-// <8=> 256x 
-
-#ifndef SAADC_CONFIG_OVERSAMPLE
-#define SAADC_CONFIG_OVERSAMPLE 0
-#endif
-
-// <q> SAADC_CONFIG_LP_MODE  - Enabling low power mode
- 
-
-#ifndef SAADC_CONFIG_LP_MODE
-#define SAADC_CONFIG_LP_MODE 0
-#endif
-
-// <o> SAADC_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef SAADC_CONFIG_IRQ_PRIORITY
-#define SAADC_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// </e>
-
-// <e> SPIS_ENABLED - nrf_drv_spis - SPIS peripheral driver - legacy layer
-//==========================================================
-#ifndef SPIS_ENABLED
-#define SPIS_ENABLED 0
-#endif
-// <o> SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <o> SPIS_DEFAULT_MODE  - Mode
- 
-// <0=> MODE_0 
-// <1=> MODE_1 
-// <2=> MODE_2 
-// <3=> MODE_3 
-
-#ifndef SPIS_DEFAULT_MODE
-#define SPIS_DEFAULT_MODE 0
-#endif
-
-// <o> SPIS_DEFAULT_BIT_ORDER  - SPIS default bit order
- 
-// <0=> MSB first 
-// <1=> LSB first 
-
-#ifndef SPIS_DEFAULT_BIT_ORDER
-#define SPIS_DEFAULT_BIT_ORDER 0
-#endif
-
-// <o> SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255> 
-
-
-#ifndef SPIS_DEFAULT_DEF
-#define SPIS_DEFAULT_DEF 255
-#endif
-
-// <o> SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255> 
-
-
-#ifndef SPIS_DEFAULT_ORC
-#define SPIS_DEFAULT_ORC 255
-#endif
-
-// <q> SPIS0_ENABLED  - Enable SPIS0 instance
- 
-
-#ifndef SPIS0_ENABLED
-#define SPIS0_ENABLED 0
-#endif
-
-// <q> SPIS1_ENABLED  - Enable SPIS1 instance
- 
-
-#ifndef SPIS1_ENABLED
-#define SPIS1_ENABLED 0
-#endif
-
-// <q> SPIS2_ENABLED  - Enable SPIS2 instance
- 
-
-#ifndef SPIS2_ENABLED
-#define SPIS2_ENABLED 0
-#endif
-
-// </e>
-
-// <e> SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver - legacy layer
-//==========================================================
-#ifndef SPI_ENABLED
-#define SPI_ENABLED 0
-#endif
-// <o> SPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <o> NRF_SPI_DRV_MISO_PULLUP_CFG  - MISO PIN pull-up configuration.
- 
-// <0=> NRF_GPIO_PIN_NOPULL 
-// <1=> NRF_GPIO_PIN_PULLDOWN 
-// <3=> NRF_GPIO_PIN_PULLUP 
-
-#ifndef NRF_SPI_DRV_MISO_PULLUP_CFG
-#define NRF_SPI_DRV_MISO_PULLUP_CFG 1
-#endif
-
-// <e> SPI0_ENABLED - Enable SPI0 instance
-//==========================================================
-#ifndef SPI0_ENABLED
-#define SPI0_ENABLED 0
-#endif
-// <q> SPI0_USE_EASY_DMA  - Use EasyDMA
- 
-
-#ifndef SPI0_USE_EASY_DMA
-#define SPI0_USE_EASY_DMA 1
-#endif
-
-// </e>
-
-// <e> SPI1_ENABLED - Enable SPI1 instance
-//==========================================================
-#ifndef SPI1_ENABLED
-#define SPI1_ENABLED 0
-#endif
-// <q> SPI1_USE_EASY_DMA  - Use EasyDMA
- 
-
-#ifndef SPI1_USE_EASY_DMA
-#define SPI1_USE_EASY_DMA 1
-#endif
-
-// </e>
-
-// <e> SPI2_ENABLED - Enable SPI2 instance
-//==========================================================
-#ifndef SPI2_ENABLED
-#define SPI2_ENABLED 0
-#endif
-// <q> SPI2_USE_EASY_DMA  - Use EasyDMA
- 
-
-#ifndef SPI2_USE_EASY_DMA
-#define SPI2_USE_EASY_DMA 1
-#endif
-
-// </e>
-
-// </e>
-
-// <e> TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver - legacy layer
-//==========================================================
-#ifndef TIMER_ENABLED
-#define TIMER_ENABLED 0
-#endif
-// <o> TIMER_DEFAULT_CONFIG_FREQUENCY  - Timer frequency if in Timer mode
- 
-// <0=> 16 MHz 
-// <1=> 8 MHz 
-// <2=> 4 MHz 
-// <3=> 2 MHz 
-// <4=> 1 MHz 
-// <5=> 500 kHz 
-// <6=> 250 kHz 
-// <7=> 125 kHz 
-// <8=> 62.5 kHz 
-// <9=> 31.25 kHz 
-
-#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY
-#define TIMER_DEFAULT_CONFIG_FREQUENCY 0
-#endif
-
-// <o> TIMER_DEFAULT_CONFIG_MODE  - Timer mode or operation
- 
-// <0=> Timer 
-// <1=> Counter 
-
-#ifndef TIMER_DEFAULT_CONFIG_MODE
-#define TIMER_DEFAULT_CONFIG_MODE 0
-#endif
-
-// <o> TIMER_DEFAULT_CONFIG_BIT_WIDTH  - Timer counter bit width
- 
-// <0=> 16 bit 
-// <1=> 8 bit 
-// <2=> 24 bit 
-// <3=> 32 bit 
-
-#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH
-#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
-#endif
-
-// <o> TIMER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
-#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <q> TIMER0_ENABLED  - Enable TIMER0 instance
- 
-
-#ifndef TIMER0_ENABLED
-#define TIMER0_ENABLED 0
-#endif
-
-// <q> TIMER1_ENABLED  - Enable TIMER1 instance
- 
-
-#ifndef TIMER1_ENABLED
-#define TIMER1_ENABLED 0
-#endif
-
-// <q> TIMER2_ENABLED  - Enable TIMER2 instance
- 
-
-#ifndef TIMER2_ENABLED
-#define TIMER2_ENABLED 0
-#endif
-
-// <q> TIMER3_ENABLED  - Enable TIMER3 instance
- 
-
-#ifndef TIMER3_ENABLED
-#define TIMER3_ENABLED 0
-#endif
-
-// <q> TIMER4_ENABLED  - Enable TIMER4 instance
- 
-
-#ifndef TIMER4_ENABLED
-#define TIMER4_ENABLED 0
-#endif
-
-// </e>
-
-// <e> TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver - legacy layer
-//==========================================================
-#ifndef TWIS_ENABLED
-#define TWIS_ENABLED 0
-#endif
-// <q> TWIS0_ENABLED  - Enable TWIS0 instance
- 
-
-#ifndef TWIS0_ENABLED
-#define TWIS0_ENABLED 0
-#endif
-
-// <q> TWIS1_ENABLED  - Enable TWIS1 instance
- 
-
-#ifndef TWIS1_ENABLED
-#define TWIS1_ENABLED 0
-#endif
-
-// <q> TWIS_ASSUME_INIT_AFTER_RESET_ONLY  - Assume that any instance would be initialized only once
- 
-
-// <i> Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
-
-#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY
-#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
-#endif
-
-// <q> TWIS_NO_SYNC_MODE  - Remove support for synchronous mode
- 
-
-// <i> Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
-
-#ifndef TWIS_NO_SYNC_MODE
-#define TWIS_NO_SYNC_MODE 0
-#endif
-
-// <o> TWIS_DEFAULT_CONFIG_ADDR0 - Address0 
-#ifndef TWIS_DEFAULT_CONFIG_ADDR0
-#define TWIS_DEFAULT_CONFIG_ADDR0 0
-#endif
-
-// <o> TWIS_DEFAULT_CONFIG_ADDR1 - Address1 
-#ifndef TWIS_DEFAULT_CONFIG_ADDR1
-#define TWIS_DEFAULT_CONFIG_ADDR1 0
-#endif
-
-// <o> TWIS_DEFAULT_CONFIG_SCL_PULL  - SCL pin pull configuration
- 
-// <0=> Disabled 
-// <1=> Pull down 
-// <3=> Pull up 
-
-#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL
-#define TWIS_DEFAULT_CONFIG_SCL_PULL 0
-#endif
-
-// <o> TWIS_DEFAULT_CONFIG_SDA_PULL  - SDA pin pull configuration
- 
-// <0=> Disabled 
-// <1=> Pull down 
-// <3=> Pull up 
-
-#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL
-#define TWIS_DEFAULT_CONFIG_SDA_PULL 0
-#endif
-
-// <o> TWIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// </e>
-
-// <e> TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver - legacy layer
-//==========================================================
-#ifndef TWI_ENABLED
-#define TWI_ENABLED 0
-#endif
-// <o> TWI_DEFAULT_CONFIG_FREQUENCY  - Frequency
- 
-// <26738688=> 100k 
-// <67108864=> 250k 
-// <104857600=> 400k 
-
-#ifndef TWI_DEFAULT_CONFIG_FREQUENCY
-#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688
-#endif
-
-// <q> TWI_DEFAULT_CONFIG_CLR_BUS_INIT  - Enables bus clearing procedure during init
- 
-
-#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT
-#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0
-#endif
-
-// <q> TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
- 
-
-#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
-#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
-#endif
-
-// <o> TWI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <e> TWI0_ENABLED - Enable TWI0 instance
-//==========================================================
-#ifndef TWI0_ENABLED
-#define TWI0_ENABLED 0
-#endif
-// <q> TWI0_USE_EASY_DMA  - Use EasyDMA (if present)
- 
-
-#ifndef TWI0_USE_EASY_DMA
-#define TWI0_USE_EASY_DMA 0
-#endif
-
-// </e>
-
-// <e> TWI1_ENABLED - Enable TWI1 instance
-//==========================================================
-#ifndef TWI1_ENABLED
-#define TWI1_ENABLED 0
-#endif
-// <q> TWI1_USE_EASY_DMA  - Use EasyDMA (if present)
- 
-
-#ifndef TWI1_USE_EASY_DMA
-#define TWI1_USE_EASY_DMA 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver - legacy layer
-//==========================================================
-#ifndef UART_ENABLED
-#define UART_ENABLED 0
-#endif
-// <o> UART_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
- 
-// <0=> Disabled 
-// <1=> Enabled 
-
-#ifndef UART_DEFAULT_CONFIG_HWFC
-#define UART_DEFAULT_CONFIG_HWFC 0
-#endif
-
-// <o> UART_DEFAULT_CONFIG_PARITY  - Parity
- 
-// <0=> Excluded 
-// <14=> Included 
-
-#ifndef UART_DEFAULT_CONFIG_PARITY
-#define UART_DEFAULT_CONFIG_PARITY 0
-#endif
-
-// <o> UART_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
- 
-// <323584=> 1200 baud 
-// <643072=> 2400 baud 
-// <1290240=> 4800 baud 
-// <2576384=> 9600 baud 
-// <3862528=> 14400 baud 
-// <5152768=> 19200 baud 
-// <7716864=> 28800 baud 
-// <10289152=> 38400 baud 
-// <15400960=> 57600 baud 
-// <20615168=> 76800 baud 
-// <30801920=> 115200 baud 
-// <61865984=> 230400 baud 
-// <67108864=> 250000 baud 
-// <121634816=> 460800 baud 
-// <251658240=> 921600 baud 
-// <268435456=> 1000000 baud 
-
-#ifndef UART_DEFAULT_CONFIG_BAUDRATE
-#define UART_DEFAULT_CONFIG_BAUDRATE 30801920
-#endif
-
-// <o> UART_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY
-#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <q> UART_EASY_DMA_SUPPORT  - Driver supporting EasyDMA
- 
-
-#ifndef UART_EASY_DMA_SUPPORT
-#define UART_EASY_DMA_SUPPORT 1
-#endif
-
-// <q> UART_LEGACY_SUPPORT  - Driver supporting Legacy mode
- 
-
-#ifndef UART_LEGACY_SUPPORT
-#define UART_LEGACY_SUPPORT 1
-#endif
-
-// <e> UART0_ENABLED - Enable UART0 instance
-//==========================================================
-#ifndef UART0_ENABLED
-#define UART0_ENABLED 0
-#endif
-// <q> UART0_CONFIG_USE_EASY_DMA  - Default setting for using EasyDMA
- 
-
-#ifndef UART0_CONFIG_USE_EASY_DMA
-#define UART0_CONFIG_USE_EASY_DMA 1
-#endif
-
-// </e>
-
-// <e> UART1_ENABLED - Enable UART1 instance
-//==========================================================
-#ifndef UART1_ENABLED
-#define UART1_ENABLED 0
-#endif
-// </e>
-
-// </e>
-
-// <e> USBD_ENABLED - nrf_drv_usbd - Software Component
-//==========================================================
-#ifndef USBD_ENABLED
-#define USBD_ENABLED 0
-#endif
-// <o> USBD_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef USBD_CONFIG_IRQ_PRIORITY
-#define USBD_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <o> USBD_CONFIG_DMASCHEDULER_MODE  - USBD SMA scheduler working scheme
- 
-// <0=> Prioritized access 
-// <1=> Round Robin 
-
-#ifndef USBD_CONFIG_DMASCHEDULER_MODE
-#define USBD_CONFIG_DMASCHEDULER_MODE 0
-#endif
-
-// <q> USBD_CONFIG_DMASCHEDULER_ISO_BOOST  - Give priority to isochronous transfers
- 
-
-// <i> This option gives priority to isochronous transfers.
-// <i> Enabling it assures that isochronous transfers are always processed,
-// <i> even if multiple other transfers are pending.
-// <i> Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm
-// <i> function is called, so the option is independent of the algorithm chosen.
-
-#ifndef USBD_CONFIG_DMASCHEDULER_ISO_BOOST
-#define USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1
-#endif
-
-// <q> USBD_CONFIG_ISO_IN_ZLP  - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
- 
-
-// <i> If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
-// <i> Else, there will be no response.
-// <i> NOTE: This option does not work on Engineering A chip.
-
-#ifndef USBD_CONFIG_ISO_IN_ZLP
-#define USBD_CONFIG_ISO_IN_ZLP 0
-#endif
-
-// </e>
-
-// <e> WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver - legacy layer
-//==========================================================
-#ifndef WDT_ENABLED
-#define WDT_ENABLED 0
-#endif
-// <o> WDT_CONFIG_BEHAVIOUR  - WDT behavior in CPU SLEEP or HALT mode
- 
-// <1=> Run in SLEEP, Pause in HALT 
-// <8=> Pause in SLEEP, Run in HALT 
-// <9=> Run in SLEEP and HALT 
-// <0=> Pause in SLEEP and HALT 
-
-#ifndef WDT_CONFIG_BEHAVIOUR
-#define WDT_CONFIG_BEHAVIOUR 1
-#endif
-
-// <o> WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295> 
-
-
-#ifndef WDT_CONFIG_RELOAD_VALUE
-#define WDT_CONFIG_RELOAD_VALUE 2000
-#endif
-
-// <o> WDT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef WDT_CONFIG_IRQ_PRIORITY
-#define WDT_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// </e>
-
-// </h> 
-//==========================================================
-
-// <h> nRF_Drivers_External 
-
-//==========================================================
-// <q> NRF_TWI_SENSOR_ENABLED  - nrf_twi_sensor - nRF TWI Sensor module
- 
-
-#ifndef NRF_TWI_SENSOR_ENABLED
-#define NRF_TWI_SENSOR_ENABLED 0
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> nRF_Libraries 
-
-//==========================================================
-// <q> APP_GPIOTE_ENABLED  - app_gpiote - GPIOTE events dispatcher
- 
-
-#ifndef APP_GPIOTE_ENABLED
-#define APP_GPIOTE_ENABLED 0
-#endif
-
-// <q> APP_PWM_ENABLED  - app_pwm - PWM functionality
- 
-
-#ifndef APP_PWM_ENABLED
-#define APP_PWM_ENABLED 0
-#endif
-
-// <e> APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler
-//==========================================================
-#ifndef APP_SCHEDULER_ENABLED
-#define APP_SCHEDULER_ENABLED 0
-#endif
-// <q> APP_SCHEDULER_WITH_PAUSE  - Enabling pause feature
- 
-
-#ifndef APP_SCHEDULER_WITH_PAUSE
-#define APP_SCHEDULER_WITH_PAUSE 0
-#endif
-
-// <q> APP_SCHEDULER_WITH_PROFILER  - Enabling scheduler profiling
- 
-
-#ifndef APP_SCHEDULER_WITH_PROFILER
-#define APP_SCHEDULER_WITH_PROFILER 0
-#endif
-
-// </e>
-
-// <e> APP_SDCARD_ENABLED - app_sdcard - SD/MMC card support using SPI
-//==========================================================
-#ifndef APP_SDCARD_ENABLED
-#define APP_SDCARD_ENABLED 0
-#endif
-// <o> APP_SDCARD_SPI_INSTANCE  - SPI instance used
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-
-#ifndef APP_SDCARD_SPI_INSTANCE
-#define APP_SDCARD_SPI_INSTANCE 0
-#endif
-
-// <o> APP_SDCARD_FREQ_INIT  - SPI frequency
- 
-// <33554432=> 125 kHz 
-// <67108864=> 250 kHz 
-// <134217728=> 500 kHz 
-// <268435456=> 1 MHz 
-// <536870912=> 2 MHz 
-// <1073741824=> 4 MHz 
-// <2147483648=> 8 MHz 
-
-#ifndef APP_SDCARD_FREQ_INIT
-#define APP_SDCARD_FREQ_INIT 67108864
-#endif
-
-// <o> APP_SDCARD_FREQ_DATA  - SPI frequency
- 
-// <33554432=> 125 kHz 
-// <67108864=> 250 kHz 
-// <134217728=> 500 kHz 
-// <268435456=> 1 MHz 
-// <536870912=> 2 MHz 
-// <1073741824=> 4 MHz 
-// <2147483648=> 8 MHz 
-
-#ifndef APP_SDCARD_FREQ_DATA
-#define APP_SDCARD_FREQ_DATA 1073741824
-#endif
-
-// </e>
-
-// <e> APP_TIMER_ENABLED - app_timer - Application timer functionality
-//==========================================================
-#ifndef APP_TIMER_ENABLED
-#define APP_TIMER_ENABLED 0
-#endif
-// <o> APP_TIMER_CONFIG_RTC_FREQUENCY  - Configure RTC prescaler.
- 
-// <0=> 32768 Hz 
-// <1=> 16384 Hz 
-// <3=> 8192 Hz 
-// <7=> 4096 Hz 
-// <15=> 2048 Hz 
-// <31=> 1024 Hz 
-
-#ifndef APP_TIMER_CONFIG_RTC_FREQUENCY
-#define APP_TIMER_CONFIG_RTC_FREQUENCY 1
-#endif
-
-// <o> APP_TIMER_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-
-// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
-
-#ifndef APP_TIMER_CONFIG_IRQ_PRIORITY
-#define APP_TIMER_CONFIG_IRQ_PRIORITY 6
-#endif
-
-// <o> APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue. 
-// <i> Size of the queue depends on how many timers are used
-// <i> in the system, how often timers are started and overall
-// <i> system latency. If queue size is too small app_timer calls
-// <i> will fail.
-
-#ifndef APP_TIMER_CONFIG_OP_QUEUE_SIZE
-#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10
-#endif
-
-// <q> APP_TIMER_CONFIG_USE_SCHEDULER  - Enable scheduling app_timer events to app_scheduler
- 
-
-#ifndef APP_TIMER_CONFIG_USE_SCHEDULER
-#define APP_TIMER_CONFIG_USE_SCHEDULER 0
-#endif
-
-// <q> APP_TIMER_KEEPS_RTC_ACTIVE  - Enable RTC always on
- 
-
-// <i> If option is enabled RTC is kept running even if there is no active timers.
-// <i> This option can be used when app_timer is used for timestamping.
-
-#ifndef APP_TIMER_KEEPS_RTC_ACTIVE
-#define APP_TIMER_KEEPS_RTC_ACTIVE 0
-#endif
-
-// <o> APP_TIMER_SAFE_WINDOW_MS - Maximum possible latency (in milliseconds) of handling app_timer event. 
-// <i> Maximum possible timeout that can be set is reduced by safe window.
-// <i> Example: RTC frequency 16384 Hz, maximum possible timeout 1024 seconds - APP_TIMER_SAFE_WINDOW_MS.
-// <i> Since RTC is not stopped when processor is halted in debugging session, this value
-// <i> must cover it if debugging is needed. It is possible to halt processor for APP_TIMER_SAFE_WINDOW_MS
-// <i> without corrupting app_timer behavior.
-
-#ifndef APP_TIMER_SAFE_WINDOW_MS
-#define APP_TIMER_SAFE_WINDOW_MS 300000
-#endif
-
-// <h> App Timer Legacy configuration - Legacy configuration.
-
-//==========================================================
-// <q> APP_TIMER_WITH_PROFILER  - Enable app_timer profiling
- 
-
-#ifndef APP_TIMER_WITH_PROFILER
-#define APP_TIMER_WITH_PROFILER 0
-#endif
-
-// <q> APP_TIMER_CONFIG_SWI_NUMBER  - Configure SWI instance used.
- 
-
-#ifndef APP_TIMER_CONFIG_SWI_NUMBER
-#define APP_TIMER_CONFIG_SWI_NUMBER 0
-#endif
-
-// </h> 
-//==========================================================
-
-// </e>
-
-// <q> APP_USBD_AUDIO_ENABLED  - app_usbd_audio - USB AUDIO class
- 
-
-#ifndef APP_USBD_AUDIO_ENABLED
-#define APP_USBD_AUDIO_ENABLED 0
-#endif
-
-// <e> APP_USBD_ENABLED - app_usbd - USB Device library
-//==========================================================
-#ifndef APP_USBD_ENABLED
-#define APP_USBD_ENABLED 0
-#endif
-// <o> APP_USBD_VID - Vendor ID.  <0x0000-0xFFFF> 
-
-
-// <i> Note: This value is not editable in Configuration Wizard.
-// <i> Vendor ID ordered from USB IF: http://www.usb.org/developers/vendor/
-
-#ifndef APP_USBD_VID
-#define APP_USBD_VID 0
-#endif
-
-// <o> APP_USBD_PID - Product ID.  <0x0000-0xFFFF> 
-
-
-// <i> Note: This value is not editable in Configuration Wizard.
-// <i> Selected Product ID
-
-#ifndef APP_USBD_PID
-#define APP_USBD_PID 0
-#endif
-
-// <o> APP_USBD_DEVICE_VER_MAJOR - Major device version  <0-99> 
-
-
-// <i> Major device version, will be converted automatically to BCD notation. Use just decimal values.
-
-#ifndef APP_USBD_DEVICE_VER_MAJOR
-#define APP_USBD_DEVICE_VER_MAJOR 1
-#endif
-
-// <o> APP_USBD_DEVICE_VER_MINOR - Minor device version  <0-9> 
-
-
-// <i> Minor device version, will be converted automatically to BCD notation. Use just decimal values.
-
-#ifndef APP_USBD_DEVICE_VER_MINOR
-#define APP_USBD_DEVICE_VER_MINOR 0
-#endif
-
-// <o> APP_USBD_DEVICE_VER_SUB - Sub-minor device version  <0-9> 
-
-
-// <i> Sub-minor device version, will be converted automatically to BCD notation. Use just decimal values.
-
-#ifndef APP_USBD_DEVICE_VER_SUB
-#define APP_USBD_DEVICE_VER_SUB 0
-#endif
-
-// <q> APP_USBD_CONFIG_SELF_POWERED  - Self-powered device, as opposed to bus-powered.
- 
-
-#ifndef APP_USBD_CONFIG_SELF_POWERED
-#define APP_USBD_CONFIG_SELF_POWERED 1
-#endif
-
-// <o> APP_USBD_CONFIG_MAX_POWER - MaxPower field in configuration descriptor in milliamps.  <0-500> 
-
-
-#ifndef APP_USBD_CONFIG_MAX_POWER
-#define APP_USBD_CONFIG_MAX_POWER 100
-#endif
-
-// <q> APP_USBD_CONFIG_POWER_EVENTS_PROCESS  - Process power events.
- 
-
-// <i> Enable processing power events in USB event handler.
-
-#ifndef APP_USBD_CONFIG_POWER_EVENTS_PROCESS
-#define APP_USBD_CONFIG_POWER_EVENTS_PROCESS 1
-#endif
-
-// <e> APP_USBD_CONFIG_EVENT_QUEUE_ENABLE - Enable event queue.
-
-// <i> This is the default configuration when all the events are placed into internal queue.
-// <i> Disable it when an external queue is used like app_scheduler or if you wish to process all events inside interrupts.
-// <i> Processing all events from the interrupt level adds requirement not to call any functions that modifies the USBD library state from the context higher than USB interrupt context.
-// <i> Functions that modify USBD state are functions for sleep, wakeup, start, stop, enable, and disable.
-//==========================================================
-#ifndef APP_USBD_CONFIG_EVENT_QUEUE_ENABLE
-#define APP_USBD_CONFIG_EVENT_QUEUE_ENABLE 1
-#endif
-// <o> APP_USBD_CONFIG_EVENT_QUEUE_SIZE - The size of the event queue.  <16-64> 
-
-
-// <i> The size of the queue for the events that would be processed in the main loop.
-
-#ifndef APP_USBD_CONFIG_EVENT_QUEUE_SIZE
-#define APP_USBD_CONFIG_EVENT_QUEUE_SIZE 32
-#endif
-
-// <o> APP_USBD_CONFIG_SOF_HANDLING_MODE  - Change SOF events handling mode.
- 
-
-// <i> Normal queue   - SOF events are pushed normally into the event queue.
-// <i> Compress queue - SOF events are counted and binded with other events or executed when the queue is empty.
-// <i>                  This prevents the queue from filling up with SOF events.
-// <i> Interrupt      - SOF events are processed in interrupt.
-// <0=> Normal queue 
-// <1=> Compress queue 
-// <2=> Interrupt 
-
-#ifndef APP_USBD_CONFIG_SOF_HANDLING_MODE
-#define APP_USBD_CONFIG_SOF_HANDLING_MODE 1
-#endif
-
-// </e>
-
-// <q> APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE  - Provide a function that generates timestamps for logs based on the current SOF.
- 
-
-// <i> The function app_usbd_sof_timestamp_get is implemented if the logger is enabled. 
-// <i> Use it when initializing the logger. 
-// <i> SOF processing is always enabled when this configuration parameter is active. 
-// <i> Note: This option is configured outside of APP_USBD_CONFIG_LOG_ENABLED. 
-// <i> This means that it works even if the logging in this very module is disabled. 
-
-#ifndef APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE
-#define APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE 0
-#endif
-
-// <o> APP_USBD_CONFIG_DESC_STRING_SIZE - Maximum size of the NULL-terminated string of the string descriptor.  <31-254> 
-
-
-// <i> 31 characters can be stored in the internal USB buffer used for transfers.
-// <i> Any value higher than 31 creates an additional buffer just for descriptor strings.
-
-#ifndef APP_USBD_CONFIG_DESC_STRING_SIZE
-#define APP_USBD_CONFIG_DESC_STRING_SIZE 31
-#endif
-
-// <q> APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED  - Enable UTF8 conversion.
- 
-
-// <i> Enable UTF8-encoded characters. In normal processing, only ASCII characters are available.
-
-#ifndef APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED
-#define APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED 0
-#endif
-
-// <s> APP_USBD_STRINGS_LANGIDS - Supported languages identifiers.
-
-// <i> Note: This value is not editable in Configuration Wizard.
-// <i> Comma-separated list of supported languages.
-#ifndef APP_USBD_STRINGS_LANGIDS
-#define APP_USBD_STRINGS_LANGIDS APP_USBD_LANG_AND_SUBLANG(APP_USBD_LANG_ENGLISH, APP_USBD_SUBLANG_ENGLISH_US)
-#endif
-
-// <e> APP_USBD_STRING_ID_MANUFACTURER - Define manufacturer string ID.
-
-// <i> Setting ID to 0 disables the string.
-//==========================================================
-#ifndef APP_USBD_STRING_ID_MANUFACTURER
-#define APP_USBD_STRING_ID_MANUFACTURER 1
-#endif
-// <q> APP_USBD_STRINGS_MANUFACTURER_EXTERN  - Define whether @ref APP_USBD_STRINGS_MANUFACTURER is created by macro or declared as a global variable.
- 
-
-#ifndef APP_USBD_STRINGS_MANUFACTURER_EXTERN
-#define APP_USBD_STRINGS_MANUFACTURER_EXTERN 0
-#endif
-
-// <s> APP_USBD_STRINGS_MANUFACTURER - String descriptor for the manufacturer name.
-
-// <i> Note: This value is not editable in Configuration Wizard.
-// <i> Comma-separated list of manufacturer names for each defined language.
-// <i> Use @ref APP_USBD_STRING_DESC macro to create string descriptor from a NULL-terminated string.
-// <i> Use @ref APP_USBD_STRING_RAW8_DESC macro to create string descriptor from comma-separated uint8_t values.
-// <i> Use @ref APP_USBD_STRING_RAW16_DESC macro to create string descriptor from comma-separated uint16_t values.
-// <i> Alternatively, configure the macro to point to any internal variable pointer that already contains the descriptor.
-// <i> Setting string to NULL disables that string.
-// <i> The order of manufacturer names must be the same like in @ref APP_USBD_STRINGS_LANGIDS.
-#ifndef APP_USBD_STRINGS_MANUFACTURER
-#define APP_USBD_STRINGS_MANUFACTURER APP_USBD_STRING_DESC("Nordic Semiconductor")
-#endif
-
-// </e>
-
-// <e> APP_USBD_STRING_ID_PRODUCT - Define product string ID.
-
-// <i> Setting ID to 0 disables the string.
-//==========================================================
-#ifndef APP_USBD_STRING_ID_PRODUCT
-#define APP_USBD_STRING_ID_PRODUCT 2
-#endif
-// <q> APP_USBD_STRINGS_PRODUCT_EXTERN  - Define whether @ref APP_USBD_STRINGS_PRODUCT is created by macro or declared as a global variable.
- 
-
-#ifndef APP_USBD_STRINGS_PRODUCT_EXTERN
-#define APP_USBD_STRINGS_PRODUCT_EXTERN 0
-#endif
-
-// <s> APP_USBD_STRINGS_PRODUCT - String descriptor for the product name.
-
-// <i> Note: This value is not editable in Configuration Wizard.
-// <i> List of product names that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER.
-#ifndef APP_USBD_STRINGS_PRODUCT
-#define APP_USBD_STRINGS_PRODUCT APP_USBD_STRING_DESC("nRF52 USB Product")
-#endif
-
-// </e>
-
-// <e> APP_USBD_STRING_ID_SERIAL - Define serial number string ID.
-
-// <i> Setting ID to 0 disables the string.
-//==========================================================
-#ifndef APP_USBD_STRING_ID_SERIAL
-#define APP_USBD_STRING_ID_SERIAL 3
-#endif
-// <q> APP_USBD_STRING_SERIAL_EXTERN  - Define whether @ref APP_USBD_STRING_SERIAL is created by macro or declared as a global variable.
- 
-
-#ifndef APP_USBD_STRING_SERIAL_EXTERN
-#define APP_USBD_STRING_SERIAL_EXTERN 0
-#endif
-
-// <s> APP_USBD_STRING_SERIAL - String descriptor for the serial number.
-
-// <i> Note: This value is not editable in Configuration Wizard.
-// <i> Serial number that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER.
-#ifndef APP_USBD_STRING_SERIAL
-#define APP_USBD_STRING_SERIAL APP_USBD_STRING_DESC("000000000000")
-#endif
-
-// </e>
-
-// <e> APP_USBD_STRING_ID_CONFIGURATION - Define configuration string ID.
-
-// <i> Setting ID to 0 disables the string.
-//==========================================================
-#ifndef APP_USBD_STRING_ID_CONFIGURATION
-#define APP_USBD_STRING_ID_CONFIGURATION 4
-#endif
-// <q> APP_USBD_STRING_CONFIGURATION_EXTERN  - Define whether @ref APP_USBD_STRINGS_CONFIGURATION is created by macro or declared as global variable.
- 
-
-#ifndef APP_USBD_STRING_CONFIGURATION_EXTERN
-#define APP_USBD_STRING_CONFIGURATION_EXTERN 0
-#endif
-
-// <s> APP_USBD_STRINGS_CONFIGURATION - String descriptor for the device configuration.
-
-// <i> Note: This value is not editable in Configuration Wizard.
-// <i> Configuration string that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER.
-#ifndef APP_USBD_STRINGS_CONFIGURATION
-#define APP_USBD_STRINGS_CONFIGURATION APP_USBD_STRING_DESC("Default configuration")
-#endif
-
-// </e>
-
-// <s> APP_USBD_STRINGS_USER - Default values for user strings.
-
-// <i> Note: This value is not editable in Configuration Wizard.
-// <i> This value stores all application specific user strings with the default initialization.
-// <i> The setup is done by X-macros.
-// <i> Expected macro parameters:
-// <i> @code
-// <i> X(mnemonic, [=str_idx], ...)
-// <i> @endcode
-// <i> - @c mnemonic: Mnemonic of the string descriptor that would be added to
-// <i>                @ref app_usbd_string_desc_idx_t enumerator.
-// <i> - @c str_idx : String index value, can be set or left empty.
-// <i>                For example, WinUSB driver requires descriptor to be present on 0xEE index.
-// <i>                Then use X(USBD_STRING_WINUSB, =0xEE, (APP_USBD_STRING_DESC(...)))
-// <i> - @c ...     : List of string descriptors for each defined language.
-#ifndef APP_USBD_STRINGS_USER
-#define APP_USBD_STRINGS_USER X(APP_USER_1, , APP_USBD_STRING_DESC("User 1"))
-#endif
-
-// </e>
-
-// <e> APP_USBD_HID_ENABLED - app_usbd_hid - USB HID class
-//==========================================================
-#ifndef APP_USBD_HID_ENABLED
-#define APP_USBD_HID_ENABLED 0
-#endif
-// <o> APP_USBD_HID_DEFAULT_IDLE_RATE - Default idle rate for HID class.   <0-255> 
-
-
-// <i> 0 means indefinite duration, any other value is multiplied by 4 milliseconds. Refer to Chapter 7.2.4 of HID 1.11 Specification.
-
-#ifndef APP_USBD_HID_DEFAULT_IDLE_RATE
-#define APP_USBD_HID_DEFAULT_IDLE_RATE 0
-#endif
-
-// <o> APP_USBD_HID_REPORT_IDLE_TABLE_SIZE - Size of idle rate table.   <1-255> 
-
-
-// <i> Must be higher than the highest report ID used.
-
-#ifndef APP_USBD_HID_REPORT_IDLE_TABLE_SIZE
-#define APP_USBD_HID_REPORT_IDLE_TABLE_SIZE 4
-#endif
-
-// </e>
-
-// <q> APP_USBD_HID_GENERIC_ENABLED  - app_usbd_hid_generic - USB HID generic
- 
-
-#ifndef APP_USBD_HID_GENERIC_ENABLED
-#define APP_USBD_HID_GENERIC_ENABLED 0
-#endif
-
-// <q> APP_USBD_HID_KBD_ENABLED  - app_usbd_hid_kbd - USB HID keyboard
- 
-
-#ifndef APP_USBD_HID_KBD_ENABLED
-#define APP_USBD_HID_KBD_ENABLED 0
-#endif
-
-// <q> APP_USBD_HID_MOUSE_ENABLED  - app_usbd_hid_mouse - USB HID mouse
- 
-
-#ifndef APP_USBD_HID_MOUSE_ENABLED
-#define APP_USBD_HID_MOUSE_ENABLED 0
-#endif
-
-// <q> APP_USBD_MSC_ENABLED  - app_usbd_msc - USB MSC class
- 
-
-#ifndef APP_USBD_MSC_ENABLED
-#define APP_USBD_MSC_ENABLED 0
-#endif
-
-// <q> CRC16_ENABLED  - crc16 - CRC16 calculation routines
- 
-
-#ifndef CRC16_ENABLED
-#define CRC16_ENABLED 0
-#endif
-
-// <q> CRC32_ENABLED  - crc32 - CRC32 calculation routines
- 
-
-#ifndef CRC32_ENABLED
-#define CRC32_ENABLED 0
-#endif
-
-// <q> ECC_ENABLED  - ecc - Elliptic Curve Cryptography Library
- 
-
-#ifndef ECC_ENABLED
-#define ECC_ENABLED 0
-#endif
-
-// <e> FDS_ENABLED - fds - Flash data storage module
-//==========================================================
-#ifndef FDS_ENABLED
-#define FDS_ENABLED 0
-#endif
-// <h> Pages - Virtual page settings
-
-// <i> Configure the number of virtual pages to use and their size.
-//==========================================================
-// <o> FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. 
-// <i> One of the virtual pages is reserved by the system for garbage collection.
-// <i> Therefore, the minimum is two virtual pages: one page to store data and one page to be used by the system for garbage collection.
-// <i> The total amount of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES * @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes.
-
-#ifndef FDS_VIRTUAL_PAGES
-#define FDS_VIRTUAL_PAGES 3
-#endif
-
-// <o> FDS_VIRTUAL_PAGE_SIZE  - The size of a virtual flash page.
- 
-
-// <i> Expressed in number of 4-byte words.
-// <i> By default, a virtual page is the same size as a physical page.
-// <i> The size of a virtual page must be a multiple of the size of a physical page.
-// <1024=> 1024 
-// <2048=> 2048 
-
-#ifndef FDS_VIRTUAL_PAGE_SIZE
-#define FDS_VIRTUAL_PAGE_SIZE 1024
-#endif
-
-// <o> FDS_VIRTUAL_PAGES_RESERVED - The number of virtual flash pages that are used by other modules. 
-// <i> FDS module stores its data in the last pages of the flash memory.
-// <i> By setting this value, you can move flash end address used by the FDS.
-// <i> As a result the reserved space can be used by other modules.
-
-#ifndef FDS_VIRTUAL_PAGES_RESERVED
-#define FDS_VIRTUAL_PAGES_RESERVED 0
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> Backend - Backend configuration
-
-// <i> Configure which nrf_fstorage backend is used by FDS to write to flash.
-//==========================================================
-// <o> FDS_BACKEND  - FDS flash backend.
- 
-
-// <i> NRF_FSTORAGE_SD uses the nrf_fstorage_sd backend implementation using the SoftDevice API. Use this if you have a SoftDevice present.
-// <i> NRF_FSTORAGE_NVMC uses the nrf_fstorage_nvmc implementation. Use this setting if you don't use the SoftDevice.
-// <1=> NRF_FSTORAGE_NVMC 
-// <2=> NRF_FSTORAGE_SD 
-
-#ifndef FDS_BACKEND
-#define FDS_BACKEND 2
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> Queue - Queue settings
-
-//==========================================================
-// <o> FDS_OP_QUEUE_SIZE - Size of the internal queue. 
-// <i> Increase this value if you frequently get synchronous FDS_ERR_NO_SPACE_IN_QUEUES errors.
-
-#ifndef FDS_OP_QUEUE_SIZE
-#define FDS_OP_QUEUE_SIZE 4
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> CRC - CRC functionality
-
-//==========================================================
-// <e> FDS_CRC_CHECK_ON_READ - Enable CRC checks.
-
-// <i> Save a record's CRC when it is written to flash and check it when the record is opened.
-// <i> Records with an incorrect CRC can still be 'seen' by the user using FDS functions, but they cannot be opened.
-// <i> Additionally, they will not be garbage collected until they are deleted.
-//==========================================================
-#ifndef FDS_CRC_CHECK_ON_READ
-#define FDS_CRC_CHECK_ON_READ 0
-#endif
-// <o> FDS_CRC_CHECK_ON_WRITE  - Perform a CRC check on newly written records.
- 
-
-// <i> Perform a CRC check on newly written records.
-// <i> This setting can be used to make sure that the record data was not altered while being written to flash.
-// <1=> Enabled 
-// <0=> Disabled 
-
-#ifndef FDS_CRC_CHECK_ON_WRITE
-#define FDS_CRC_CHECK_ON_WRITE 0
-#endif
-
-// </e>
-
-// </h> 
-//==========================================================
-
-// <h> Users - Number of users
-
-//==========================================================
-// <o> FDS_MAX_USERS - Maximum number of callbacks that can be registered. 
-#ifndef FDS_MAX_USERS
-#define FDS_MAX_USERS 4
-#endif
-
-// </h> 
-//==========================================================
-
-// </e>
-
-// <q> HARDFAULT_HANDLER_ENABLED  - hardfault_default - HardFault default handler for debugging and release
- 
-
-#ifndef HARDFAULT_HANDLER_ENABLED
-#define HARDFAULT_HANDLER_ENABLED 0
-#endif
-
-// <e> HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI
-//==========================================================
-#ifndef HCI_MEM_POOL_ENABLED
-#define HCI_MEM_POOL_ENABLED 0
-#endif
-// <o> HCI_TX_BUF_SIZE - TX buffer size in bytes. 
-#ifndef HCI_TX_BUF_SIZE
-#define HCI_TX_BUF_SIZE 600
-#endif
-
-// <o> HCI_RX_BUF_SIZE - RX buffer size in bytes. 
-#ifndef HCI_RX_BUF_SIZE
-#define HCI_RX_BUF_SIZE 600
-#endif
-
-// <o> HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. 
-#ifndef HCI_RX_BUF_QUEUE_SIZE
-#define HCI_RX_BUF_QUEUE_SIZE 4
-#endif
-
-// </e>
-
-// <e> HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI
-//==========================================================
-#ifndef HCI_SLIP_ENABLED
-#define HCI_SLIP_ENABLED 0
-#endif
-// <o> HCI_UART_BAUDRATE  - Default Baudrate
- 
-// <323584=> 1200 baud 
-// <643072=> 2400 baud 
-// <1290240=> 4800 baud 
-// <2576384=> 9600 baud 
-// <3862528=> 14400 baud 
-// <5152768=> 19200 baud 
-// <7716864=> 28800 baud 
-// <10289152=> 38400 baud 
-// <15400960=> 57600 baud 
-// <20615168=> 76800 baud 
-// <30801920=> 115200 baud 
-// <61865984=> 230400 baud 
-// <67108864=> 250000 baud 
-// <121634816=> 460800 baud 
-// <251658240=> 921600 baud 
-// <268435456=> 1000000 baud 
-
-#ifndef HCI_UART_BAUDRATE
-#define HCI_UART_BAUDRATE 30801920
-#endif
-
-// <o> HCI_UART_FLOW_CONTROL  - Hardware Flow Control
- 
-// <0=> Disabled 
-// <1=> Enabled 
-
-#ifndef HCI_UART_FLOW_CONTROL
-#define HCI_UART_FLOW_CONTROL 0
-#endif
-
-// <o> HCI_UART_RX_PIN - UART RX pin 
-#ifndef HCI_UART_RX_PIN
-#define HCI_UART_RX_PIN 31
-#endif
-
-// <o> HCI_UART_TX_PIN - UART TX pin 
-#ifndef HCI_UART_TX_PIN
-#define HCI_UART_TX_PIN 31
-#endif
-
-// <o> HCI_UART_RTS_PIN - UART RTS pin 
-#ifndef HCI_UART_RTS_PIN
-#define HCI_UART_RTS_PIN 31
-#endif
-
-// <o> HCI_UART_CTS_PIN - UART CTS pin 
-#ifndef HCI_UART_CTS_PIN
-#define HCI_UART_CTS_PIN 31
-#endif
-
-// </e>
-
-// <e> HCI_TRANSPORT_ENABLED - hci_transport - HCI transport
-//==========================================================
-#ifndef HCI_TRANSPORT_ENABLED
-#define HCI_TRANSPORT_ENABLED 0
-#endif
-// <o> HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. 
-#ifndef HCI_MAX_PACKET_SIZE_IN_BITS
-#define HCI_MAX_PACKET_SIZE_IN_BITS 8000
-#endif
-
-// </e>
-
-// <q> LED_SOFTBLINK_ENABLED  - led_softblink - led_softblink module
- 
-
-#ifndef LED_SOFTBLINK_ENABLED
-#define LED_SOFTBLINK_ENABLED 0
-#endif
-
-// <q> LOW_POWER_PWM_ENABLED  - low_power_pwm - low_power_pwm module
- 
-
-#ifndef LOW_POWER_PWM_ENABLED
-#define LOW_POWER_PWM_ENABLED 0
-#endif
-
-// <e> MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator
-//==========================================================
-#ifndef MEM_MANAGER_ENABLED
-#define MEM_MANAGER_ENABLED 0
-#endif
-// <o> MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block.  <0-255> 
-
-
-#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT
-#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1
-#endif
-
-// <o> MEMORY_MANAGER_SMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'small' block. 
-// <i>  Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE
-#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32
-#endif
-
-// <o> MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block.  <0-255> 
-
-
-#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT
-#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0
-#endif
-
-// <o> MEMORY_MANAGER_MEDIUM_BLOCK_SIZE -  Size of each memory blocks identified as 'medium' block. 
-// <i>  Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE
-#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256
-#endif
-
-// <o> MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block.  <0-255> 
-
-
-#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT
-#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0
-#endif
-
-// <o> MEMORY_MANAGER_LARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'large' block. 
-// <i>  Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE
-#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256
-#endif
-
-// <o> MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block.  <0-255> 
-
-
-#ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT
-#define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0
-#endif
-
-// <o> MEMORY_MANAGER_XLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra large' block. 
-// <i>  Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE
-#define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320
-#endif
-
-// <o> MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block.  <0-255> 
-
-
-#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT
-#define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0
-#endif
-
-// <o> MEMORY_MANAGER_XXLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra large' block. 
-// <i>  Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE
-#define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444
-#endif
-
-// <o> MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block.  <0-255> 
-
-
-#ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT
-#define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0
-#endif
-
-// <o> MEMORY_MANAGER_XSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra small' block. 
-// <i>  Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE
-#define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64
-#endif
-
-// <o> MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block.  <0-255> 
-
-
-#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT
-#define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0
-#endif
-
-// <o> MEMORY_MANAGER_XXSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra small' block. 
-// <i>  Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE
-#define MEMORY_MANAGER_XXSMALL_BLOCK_SIZE 32
-#endif
-
-// <e> MEM_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef MEM_MANAGER_CONFIG_LOG_ENABLED
-#define MEM_MANAGER_CONFIG_LOG_ENABLED 0
-#endif
-// <o> MEM_MANAGER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef MEM_MANAGER_CONFIG_LOG_LEVEL
-#define MEM_MANAGER_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> MEM_MANAGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef MEM_MANAGER_CONFIG_INFO_COLOR
-#define MEM_MANAGER_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> MEM_MANAGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef MEM_MANAGER_CONFIG_DEBUG_COLOR
-#define MEM_MANAGER_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <q> MEM_MANAGER_DISABLE_API_PARAM_CHECK  - Disable API parameter checks in the module.
- 
-
-#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK
-#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0
-#endif
-
-// </e>
-
-// <e> NRF_BALLOC_ENABLED - nrf_balloc - Block allocator module
-//==========================================================
-#ifndef NRF_BALLOC_ENABLED
-#define NRF_BALLOC_ENABLED 1
-#endif
-// <e> NRF_BALLOC_CONFIG_DEBUG_ENABLED - Enables debug mode in the module.
-//==========================================================
-#ifndef NRF_BALLOC_CONFIG_DEBUG_ENABLED
-#define NRF_BALLOC_CONFIG_DEBUG_ENABLED 0
-#endif
-// <o> NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard.  <0-255> 
-
-
-#ifndef NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS
-#define NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS 1
-#endif
-
-// <o> NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard.  <0-255> 
-
-
-#ifndef NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS
-#define NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS 1
-#endif
-
-// <q> NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED  - Enables basic checks in this module.
- 
-
-#ifndef NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED
-#define NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED 0
-#endif
-
-// <q> NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED  - Enables double memory free check in this module.
- 
-
-#ifndef NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED
-#define NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED 0
-#endif
-
-// <q> NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED  - Enables free memory corruption check in this module.
- 
-
-#ifndef NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED
-#define NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED 0
-#endif
-
-// <q> NRF_BALLOC_CLI_CMDS  - Enable CLI commands specific to the module
- 
-
-#ifndef NRF_BALLOC_CLI_CMDS
-#define NRF_BALLOC_CLI_CMDS 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRF_CSENSE_ENABLED - nrf_csense - Capacitive sensor module
-//==========================================================
-#ifndef NRF_CSENSE_ENABLED
-#define NRF_CSENSE_ENABLED 0
-#endif
-// <o> NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched. 
-#ifndef NRF_CSENSE_PAD_HYSTERESIS
-#define NRF_CSENSE_PAD_HYSTERESIS 15
-#endif
-
-// <o> NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step. 
-#ifndef NRF_CSENSE_PAD_DEVIATION
-#define NRF_CSENSE_PAD_DEVIATION 70
-#endif
-
-// <o> NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account. 
-#ifndef NRF_CSENSE_MIN_PAD_VALUE
-#define NRF_CSENSE_MIN_PAD_VALUE 20
-#endif
-
-// <o> NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. 
-#ifndef NRF_CSENSE_MAX_PADS_NUMBER
-#define NRF_CSENSE_MAX_PADS_NUMBER 20
-#endif
-
-// <o> NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement. 
-#ifndef NRF_CSENSE_MAX_VALUE
-#define NRF_CSENSE_MAX_VALUE 1000
-#endif
-
-// <o> NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module. 
-// <i> This is used when capacitive sensor does not use COMP.
-
-#ifndef NRF_CSENSE_OUTPUT_PIN
-#define NRF_CSENSE_OUTPUT_PIN 26
-#endif
-
-// </e>
-
-// <e> NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor low-level module
-//==========================================================
-#ifndef NRF_DRV_CSENSE_ENABLED
-#define NRF_DRV_CSENSE_ENABLED 0
-#endif
-// <e> USE_COMP - Use the comparator to implement the capacitive sensor driver.
-
-// <i> Due to Anomaly 84, COMP I_SOURCE is not functional. It has too high a varation.
-//==========================================================
-#ifndef USE_COMP
-#define USE_COMP 0
-#endif
-// <o> TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51). 
-#ifndef TIMER0_FOR_CSENSE
-#define TIMER0_FOR_CSENSE 1
-#endif
-
-// <o> TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51). 
-#ifndef TIMER1_FOR_CSENSE
-#define TIMER1_FOR_CSENSE 2
-#endif
-
-// <o> MEASUREMENT_PERIOD - Single measurement period. 
-// <i> Time of a single measurement can be calculated as
-// <i> T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ).
-// <i> I_SOURCE, VUP, and VDOWN are values used to initialize COMP and C is the capacitance of the used pad.
-
-#ifndef MEASUREMENT_PERIOD
-#define MEASUREMENT_PERIOD 20
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NRF_FSTORAGE_ENABLED - nrf_fstorage - Flash abstraction library
-//==========================================================
-#ifndef NRF_FSTORAGE_ENABLED
-#define NRF_FSTORAGE_ENABLED 0
-#endif
-// <h> nrf_fstorage - Common settings
-
-// <i> Common settings to all fstorage implementations
-//==========================================================
-// <q> NRF_FSTORAGE_PARAM_CHECK_DISABLED  - Disable user input validation
- 
-
-// <i> If selected, use ASSERT to validate user input.
-// <i> This effectively removes user input validation in production code.
-// <i> Recommended setting: OFF, only enable this setting if size is a major concern.
-
-#ifndef NRF_FSTORAGE_PARAM_CHECK_DISABLED
-#define NRF_FSTORAGE_PARAM_CHECK_DISABLED 0
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> nrf_fstorage_sd - Implementation using the SoftDevice
-
-// <i> Configuration options for the fstorage implementation using the SoftDevice
-//==========================================================
-// <o> NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations 
-// <i> Increase this value if API calls frequently return the error @ref NRF_ERROR_NO_MEM.
-
-#ifndef NRF_FSTORAGE_SD_QUEUE_SIZE
-#define NRF_FSTORAGE_SD_QUEUE_SIZE 4
-#endif
-
-// <o> NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy 
-// <i> Increase this value if events frequently return the @ref NRF_ERROR_TIMEOUT error.
-// <i> The SoftDevice might fail to schedule flash access due to high BLE activity.
-
-#ifndef NRF_FSTORAGE_SD_MAX_RETRIES
-#define NRF_FSTORAGE_SD_MAX_RETRIES 8
-#endif
-
-// <o> NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation 
-// <i> This value must be a multiple of four.
-// <i> Lowering this value can increase the chances of the SoftDevice being able to execute flash operations in between radio activity.
-// <i> This value is bound by the maximum number of bytes that can be written to flash in a single call to @ref sd_flash_write.
-// <i> That is 1024 bytes for nRF51 ICs and 4096 bytes for nRF52 ICs.
-
-#ifndef NRF_FSTORAGE_SD_MAX_WRITE_SIZE
-#define NRF_FSTORAGE_SD_MAX_WRITE_SIZE 4096
-#endif
-
-// </h> 
-//==========================================================
-
-// </e>
-
-// <q> NRF_GFX_ENABLED  - nrf_gfx - GFX module
- 
-
-#ifndef NRF_GFX_ENABLED
-#define NRF_GFX_ENABLED 0
-#endif
-
-// <q> NRF_MEMOBJ_ENABLED  - nrf_memobj - Linked memory allocator module
- 
-
-#ifndef NRF_MEMOBJ_ENABLED
-#define NRF_MEMOBJ_ENABLED 1
-#endif
-
-// <e> NRF_PWR_MGMT_ENABLED - nrf_pwr_mgmt - Power management module
-//==========================================================
-#ifndef NRF_PWR_MGMT_ENABLED
-#define NRF_PWR_MGMT_ENABLED 0
-#endif
-// <e> NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED - Enables pin debug in the module.
-
-// <i> Selected pin will be set when CPU is in sleep mode.
-//==========================================================
-#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED
-#define NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED 0
-#endif
-// <o> NRF_PWR_MGMT_SLEEP_DEBUG_PIN  - Pin number
- 
-// <0=> 0 (P0.0) 
-// <1=> 1 (P0.1) 
-// <2=> 2 (P0.2) 
-// <3=> 3 (P0.3) 
-// <4=> 4 (P0.4) 
-// <5=> 5 (P0.5) 
-// <6=> 6 (P0.6) 
-// <7=> 7 (P0.7) 
-// <8=> 8 (P0.8) 
-// <9=> 9 (P0.9) 
-// <10=> 10 (P0.10) 
-// <11=> 11 (P0.11) 
-// <12=> 12 (P0.12) 
-// <13=> 13 (P0.13) 
-// <14=> 14 (P0.14) 
-// <15=> 15 (P0.15) 
-// <16=> 16 (P0.16) 
-// <17=> 17 (P0.17) 
-// <18=> 18 (P0.18) 
-// <19=> 19 (P0.19) 
-// <20=> 20 (P0.20) 
-// <21=> 21 (P0.21) 
-// <22=> 22 (P0.22) 
-// <23=> 23 (P0.23) 
-// <24=> 24 (P0.24) 
-// <25=> 25 (P0.25) 
-// <26=> 26 (P0.26) 
-// <27=> 27 (P0.27) 
-// <28=> 28 (P0.28) 
-// <29=> 29 (P0.29) 
-// <30=> 30 (P0.30) 
-// <31=> 31 (P0.31) 
-// <32=> 32 (P1.0) 
-// <33=> 33 (P1.1) 
-// <34=> 34 (P1.2) 
-// <35=> 35 (P1.3) 
-// <36=> 36 (P1.4) 
-// <37=> 37 (P1.5) 
-// <38=> 38 (P1.6) 
-// <39=> 39 (P1.7) 
-// <40=> 40 (P1.8) 
-// <41=> 41 (P1.9) 
-// <42=> 42 (P1.10) 
-// <43=> 43 (P1.11) 
-// <44=> 44 (P1.12) 
-// <45=> 45 (P1.13) 
-// <46=> 46 (P1.14) 
-// <47=> 47 (P1.15) 
-// <4294967295=> Not connected 
-
-#ifndef NRF_PWR_MGMT_SLEEP_DEBUG_PIN
-#define NRF_PWR_MGMT_SLEEP_DEBUG_PIN 31
-#endif
-
-// </e>
-
-// <q> NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED  - Enables CPU usage monitor.
- 
-
-// <i> Module will trace percentage of CPU usage in one second intervals.
-
-#ifndef NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED
-#define NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED 0
-#endif
-
-// <e> NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED - Enable standby timeout.
-//==========================================================
-#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED
-#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED 0
-#endif
-// <o> NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S - Standby timeout (in seconds). 
-// <i> Shutdown procedure will begin no earlier than after this number of seconds.
-
-#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S
-#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S 3
-#endif
-
-// </e>
-
-// <q> NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED  - Enables FPU event cleaning.
- 
-
-#ifndef NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED
-#define NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED 0
-#endif
-
-// <q> NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY  - Blocked shutdown procedure will be retried every second.
- 
-
-#ifndef NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY
-#define NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY 0
-#endif
-
-// <q> NRF_PWR_MGMT_CONFIG_USE_SCHEDULER  - Module will use @ref app_scheduler.
- 
-
-#ifndef NRF_PWR_MGMT_CONFIG_USE_SCHEDULER
-#define NRF_PWR_MGMT_CONFIG_USE_SCHEDULER 0
-#endif
-
-// <o> NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT - The number of priorities for module handlers. 
-// <i> The number of stages of the shutdown process.
-
-#ifndef NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT
-#define NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT 3
-#endif
-
-// </e>
-
-// <e> NRF_QUEUE_ENABLED - nrf_queue - Queue module
-//==========================================================
-#ifndef NRF_QUEUE_ENABLED
-#define NRF_QUEUE_ENABLED 0
-#endif
-// <q> NRF_QUEUE_CLI_CMDS  - Enable CLI commands specific to the module
- 
-
-#ifndef NRF_QUEUE_CLI_CMDS
-#define NRF_QUEUE_CLI_CMDS 0
-#endif
-
-// </e>
-
-// <q> NRF_SECTION_ITER_ENABLED  - nrf_section_iter - Section iterator
- 
-
-#ifndef NRF_SECTION_ITER_ENABLED
-#define NRF_SECTION_ITER_ENABLED 1
-#endif
-
-// <q> NRF_SORTLIST_ENABLED  - nrf_sortlist - Sorted list
- 
-
-#ifndef NRF_SORTLIST_ENABLED
-#define NRF_SORTLIST_ENABLED 1
-#endif
-
-// <q> NRF_SPI_MNGR_ENABLED  - nrf_spi_mngr - SPI transaction manager
- 
-
-#ifndef NRF_SPI_MNGR_ENABLED
-#define NRF_SPI_MNGR_ENABLED 0
-#endif
-
-// <q> NRF_STRERROR_ENABLED  - nrf_strerror - Library for converting error code to string.
- 
-
-#ifndef NRF_STRERROR_ENABLED
-#define NRF_STRERROR_ENABLED 1
-#endif
-
-// <q> NRF_TWI_MNGR_ENABLED  - nrf_twi_mngr - TWI transaction manager
- 
-
-#ifndef NRF_TWI_MNGR_ENABLED
-#define NRF_TWI_MNGR_ENABLED 0
-#endif
-
-// <q> SLIP_ENABLED  - slip - SLIP encoding and decoding
- 
-
-#ifndef SLIP_ENABLED
-#define SLIP_ENABLED 0
-#endif
-
-// <e> TASK_MANAGER_ENABLED - task_manager - Task manager.
-//==========================================================
-#ifndef TASK_MANAGER_ENABLED
-#define TASK_MANAGER_ENABLED 0
-#endif
-// <q> TASK_MANAGER_CLI_CMDS  - Enable CLI commands specific to the module
- 
-
-#ifndef TASK_MANAGER_CLI_CMDS
-#define TASK_MANAGER_CLI_CMDS 0
-#endif
-
-// <o> TASK_MANAGER_CONFIG_MAX_TASKS - Maximum number of tasks which can be created 
-#ifndef TASK_MANAGER_CONFIG_MAX_TASKS
-#define TASK_MANAGER_CONFIG_MAX_TASKS 2
-#endif
-
-// <o> TASK_MANAGER_CONFIG_STACK_SIZE - Stack size for every task (power of 2) 
-#ifndef TASK_MANAGER_CONFIG_STACK_SIZE
-#define TASK_MANAGER_CONFIG_STACK_SIZE 1024
-#endif
-
-// <q> TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED  - Enable stack profiling.
- 
-
-#ifndef TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED
-#define TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED 1
-#endif
-
-// <o> TASK_MANAGER_CONFIG_STACK_GUARD  - Configures stack guard.
- 
-// <0=> Disabled 
-// <4=> 32 bytes 
-// <5=> 64 bytes 
-// <6=> 128 bytes 
-// <7=> 256 bytes 
-// <8=> 512 bytes 
-
-#ifndef TASK_MANAGER_CONFIG_STACK_GUARD
-#define TASK_MANAGER_CONFIG_STACK_GUARD 7
-#endif
-
-// </e>
-
-// <h> app_button - buttons handling module
-
-//==========================================================
-// <q> BUTTON_ENABLED  - Enables Button module
- 
-
-#ifndef BUTTON_ENABLED
-#define BUTTON_ENABLED 0
-#endif
-
-// <q> BUTTON_HIGH_ACCURACY_ENABLED  - Enables GPIOTE high accuracy for buttons
- 
-
-#ifndef BUTTON_HIGH_ACCURACY_ENABLED
-#define BUTTON_HIGH_ACCURACY_ENABLED 0
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> app_usbd_cdc_acm - USB CDC ACM class
-
-//==========================================================
-// <q> APP_USBD_CDC_ACM_ENABLED  - Enabling USBD CDC ACM Class library
- 
-
-#ifndef APP_USBD_CDC_ACM_ENABLED
-#define APP_USBD_CDC_ACM_ENABLED 0
-#endif
-
-// <q> APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE  - Send ZLP on write with same size as endpoint
- 
-
-// <i> If enabled, CDC ACM class will automatically send a zero length packet after transfer which has the same size as endpoint.
-// <i> This may limit throughput if a lot of binary data is sent, but in terminal mode operation it makes sure that the data is always displayed right after it is sent.
-
-#ifndef APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE
-#define APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE 1
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> nrf_cli - Command line interface
-
-//==========================================================
-// <q> NRF_CLI_ENABLED  - Enable/disable the CLI module.
- 
-
-#ifndef NRF_CLI_ENABLED
-#define NRF_CLI_ENABLED 0
-#endif
-
-// <o> NRF_CLI_ARGC_MAX - Maximum number of parameters passed to the command handler. 
-#ifndef NRF_CLI_ARGC_MAX
-#define NRF_CLI_ARGC_MAX 12
-#endif
-
-// <q> NRF_CLI_BUILD_IN_CMDS_ENABLED  - CLI built-in commands.
- 
-
-#ifndef NRF_CLI_BUILD_IN_CMDS_ENABLED
-#define NRF_CLI_BUILD_IN_CMDS_ENABLED 1
-#endif
-
-// <o> NRF_CLI_CMD_BUFF_SIZE - Maximum buffer size for a single command. 
-#ifndef NRF_CLI_CMD_BUFF_SIZE
-#define NRF_CLI_CMD_BUFF_SIZE 128
-#endif
-
-// <q> NRF_CLI_ECHO_STATUS  - CLI echo status. If set, echo is ON.
- 
-
-#ifndef NRF_CLI_ECHO_STATUS
-#define NRF_CLI_ECHO_STATUS 1
-#endif
-
-// <q> NRF_CLI_WILDCARD_ENABLED  - Enable wildcard functionality for CLI commands.
- 
-
-#ifndef NRF_CLI_WILDCARD_ENABLED
-#define NRF_CLI_WILDCARD_ENABLED 0
-#endif
-
-// <q> NRF_CLI_METAKEYS_ENABLED  - Enable additional control keys for CLI commands like ctrl+a, ctrl+e, ctrl+w, ctrl+u
- 
-
-#ifndef NRF_CLI_METAKEYS_ENABLED
-#define NRF_CLI_METAKEYS_ENABLED 0
-#endif
-
-// <o> NRF_CLI_PRINTF_BUFF_SIZE - Maximum print buffer size. 
-#ifndef NRF_CLI_PRINTF_BUFF_SIZE
-#define NRF_CLI_PRINTF_BUFF_SIZE 23
-#endif
-
-// <e> NRF_CLI_HISTORY_ENABLED - Enable CLI history mode.
-//==========================================================
-#ifndef NRF_CLI_HISTORY_ENABLED
-#define NRF_CLI_HISTORY_ENABLED 1
-#endif
-// <o> NRF_CLI_HISTORY_ELEMENT_SIZE - Size of one memory object reserved for CLI history. 
-#ifndef NRF_CLI_HISTORY_ELEMENT_SIZE
-#define NRF_CLI_HISTORY_ELEMENT_SIZE 32
-#endif
-
-// <o> NRF_CLI_HISTORY_ELEMENT_COUNT - Number of history memory objects. 
-#ifndef NRF_CLI_HISTORY_ELEMENT_COUNT
-#define NRF_CLI_HISTORY_ELEMENT_COUNT 8
-#endif
-
-// </e>
-
-// <q> NRF_CLI_VT100_COLORS_ENABLED  - CLI VT100 colors.
- 
-
-#ifndef NRF_CLI_VT100_COLORS_ENABLED
-#define NRF_CLI_VT100_COLORS_ENABLED 1
-#endif
-
-// <q> NRF_CLI_STATISTICS_ENABLED  - Enable CLI statistics.
- 
-
-#ifndef NRF_CLI_STATISTICS_ENABLED
-#define NRF_CLI_STATISTICS_ENABLED 1
-#endif
-
-// <q> NRF_CLI_LOG_BACKEND  - Enable logger backend interface.
- 
-
-#ifndef NRF_CLI_LOG_BACKEND
-#define NRF_CLI_LOG_BACKEND 1
-#endif
-
-// <q> NRF_CLI_USES_TASK_MANAGER_ENABLED  - Enable CLI to use task_manager
- 
-
-#ifndef NRF_CLI_USES_TASK_MANAGER_ENABLED
-#define NRF_CLI_USES_TASK_MANAGER_ENABLED 0
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> nrf_fprintf - fprintf function.
-
-//==========================================================
-// <q> NRF_FPRINTF_ENABLED  - Enable/disable fprintf module.
- 
-
-#ifndef NRF_FPRINTF_ENABLED
-#define NRF_FPRINTF_ENABLED 1
-#endif
-
-// <q> NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED  - For each printed LF, function will add CR.
- 
-
-#ifndef NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED
-#define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 1
-#endif
-
-// <q> NRF_FPRINTF_DOUBLE_ENABLED  - Enable IEEE-754 double precision formatting.
- 
-
-#ifndef NRF_FPRINTF_DOUBLE_ENABLED
-#define NRF_FPRINTF_DOUBLE_ENABLED 0
-#endif
-
-// </h> 
-//==========================================================
-
-// </h> 
-//==========================================================
-
-// <h> nRF_Log 
-
-//==========================================================
-// <e> NRF_LOG_ENABLED - nrf_log - Logger
-//==========================================================
-#ifndef NRF_LOG_ENABLED
-#define NRF_LOG_ENABLED 0
-#endif
-// <h> Log message pool - Configuration of log message pool
-
-//==========================================================
-// <o> NRF_LOG_MSGPOOL_ELEMENT_SIZE - Size of a single element in the pool of memory objects. 
-// <i> If a small value is set, then performance of logs processing
-// <i> is degraded because data is fragmented. Bigger value impacts
-// <i> RAM memory utilization. The size is set to fit a message with
-// <i> a timestamp and up to 2 arguments in a single memory object.
-
-#ifndef NRF_LOG_MSGPOOL_ELEMENT_SIZE
-#define NRF_LOG_MSGPOOL_ELEMENT_SIZE 20
-#endif
-
-// <o> NRF_LOG_MSGPOOL_ELEMENT_COUNT - Number of elements in the pool of memory objects 
-// <i> If a small value is set, then it may lead to a deadlock
-// <i> in certain cases if backend has high latency and holds
-// <i> multiple messages for long time. Bigger value impacts
-// <i> RAM memory usage.
-
-#ifndef NRF_LOG_MSGPOOL_ELEMENT_COUNT
-#define NRF_LOG_MSGPOOL_ELEMENT_COUNT 8
-#endif
-
-// </h> 
-//==========================================================
-
-// <q> NRF_LOG_ALLOW_OVERFLOW  - Configures behavior when circular buffer is full.
- 
-
-// <i> If set then oldest logs are overwritten. Otherwise a 
-// <i> marker is injected informing about overflow.
-
-#ifndef NRF_LOG_ALLOW_OVERFLOW
-#define NRF_LOG_ALLOW_OVERFLOW 1
-#endif
-
-// <o> NRF_LOG_BUFSIZE  - Size of the buffer for storing logs (in bytes).
- 
-
-// <i> Must be power of 2 and multiple of 4.
-// <i> If NRF_LOG_DEFERRED = 0 then buffer size can be reduced to minimum.
-// <128=> 128 
-// <256=> 256 
-// <512=> 512 
-// <1024=> 1024 
-// <2048=> 2048 
-// <4096=> 4096 
-// <8192=> 8192 
-// <16384=> 16384 
-
-#ifndef NRF_LOG_BUFSIZE
-#define NRF_LOG_BUFSIZE 1024
-#endif
-
-// <q> NRF_LOG_CLI_CMDS  - Enable CLI commands for the module.
- 
-
-#ifndef NRF_LOG_CLI_CMDS
-#define NRF_LOG_CLI_CMDS 0
-#endif
-
-// <o> NRF_LOG_DEFAULT_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_LOG_DEFAULT_LEVEL
-#define NRF_LOG_DEFAULT_LEVEL 3
-#endif
-
-// <q> NRF_LOG_DEFERRED  - Enable deffered logger.
- 
-
-// <i> Log data is buffered and can be processed in idle.
-
-#ifndef NRF_LOG_DEFERRED
-#define NRF_LOG_DEFERRED 1
-#endif
-
-// <q> NRF_LOG_FILTERS_ENABLED  - Enable dynamic filtering of logs.
- 
-
-#ifndef NRF_LOG_FILTERS_ENABLED
-#define NRF_LOG_FILTERS_ENABLED 0
-#endif
-
-// <q> NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED  - Enable use of critical region for non deffered mode when flushing logs.
- 
-
-// <i> When enabled NRF_LOG_FLUSH is called from critical section when non deffered mode is used.
-// <i> Log output will never be corrupted as access to the log backend is exclusive
-// <i> but system will spend significant amount of time in critical section
-
-#ifndef NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED
-#define NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED 0
-#endif
-
-// <o> NRF_LOG_STR_PUSH_BUFFER_SIZE  - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH.
- 
-// <16=> 16 
-// <32=> 32 
-// <64=> 64 
-// <128=> 128 
-// <256=> 256 
-// <512=> 512 
-// <1024=> 1024 
-
-#ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE
-#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128
-#endif
-
-// <o> NRF_LOG_STR_PUSH_BUFFER_SIZE  - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH.
- 
-// <16=> 16 
-// <32=> 32 
-// <64=> 64 
-// <128=> 128 
-// <256=> 256 
-// <512=> 512 
-// <1024=> 1024 
-
-#ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE
-#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128
-#endif
-
-// <e> NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string
-//==========================================================
-#ifndef NRF_LOG_USES_COLORS
-#define NRF_LOG_USES_COLORS 0
-#endif
-// <o> NRF_LOG_COLOR_DEFAULT  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_LOG_COLOR_DEFAULT
-#define NRF_LOG_COLOR_DEFAULT 0
-#endif
-
-// <o> NRF_LOG_ERROR_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_LOG_ERROR_COLOR
-#define NRF_LOG_ERROR_COLOR 2
-#endif
-
-// <o> NRF_LOG_WARNING_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_LOG_WARNING_COLOR
-#define NRF_LOG_WARNING_COLOR 4
-#endif
-
-// </e>
-
-// <e> NRF_LOG_USES_TIMESTAMP - Enable timestamping
-
-// <i> Function for getting the timestamp is provided by the user
-//==========================================================
-#ifndef NRF_LOG_USES_TIMESTAMP
-#define NRF_LOG_USES_TIMESTAMP 0
-#endif
-// <o> NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY - Default frequency of the timestamp (in Hz) or 0 to use app_timer frequency. 
-#ifndef NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY
-#define NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY 0
-#endif
-
-// </e>
-
-// <h> nrf_log module configuration 
-
-//==========================================================
-// <h> nrf_log in nRF_Core 
-
-//==========================================================
-// <e> NRF_MPU_LIB_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_MPU_LIB_CONFIG_LOG_ENABLED
-#define NRF_MPU_LIB_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_MPU_LIB_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_MPU_LIB_CONFIG_LOG_LEVEL
-#define NRF_MPU_LIB_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_MPU_LIB_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_MPU_LIB_CONFIG_INFO_COLOR
-#define NRF_MPU_LIB_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_MPU_LIB_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_MPU_LIB_CONFIG_DEBUG_COLOR
-#define NRF_MPU_LIB_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_STACK_GUARD_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_STACK_GUARD_CONFIG_LOG_ENABLED
-#define NRF_STACK_GUARD_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_STACK_GUARD_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_STACK_GUARD_CONFIG_LOG_LEVEL
-#define NRF_STACK_GUARD_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_STACK_GUARD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_STACK_GUARD_CONFIG_INFO_COLOR
-#define NRF_STACK_GUARD_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_STACK_GUARD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_STACK_GUARD_CONFIG_DEBUG_COLOR
-#define NRF_STACK_GUARD_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> TASK_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef TASK_MANAGER_CONFIG_LOG_ENABLED
-#define TASK_MANAGER_CONFIG_LOG_ENABLED 0
-#endif
-// <o> TASK_MANAGER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef TASK_MANAGER_CONFIG_LOG_LEVEL
-#define TASK_MANAGER_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> TASK_MANAGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef TASK_MANAGER_CONFIG_INFO_COLOR
-#define TASK_MANAGER_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> TASK_MANAGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef TASK_MANAGER_CONFIG_DEBUG_COLOR
-#define TASK_MANAGER_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </h> 
-//==========================================================
-
-// <h> nrf_log in nRF_Drivers 
-
-//==========================================================
-// <e> CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef CLOCK_CONFIG_LOG_ENABLED
-#define CLOCK_CONFIG_LOG_ENABLED 0
-#endif
-// <o> CLOCK_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef CLOCK_CONFIG_LOG_LEVEL
-#define CLOCK_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> CLOCK_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef CLOCK_CONFIG_INFO_COLOR
-#define CLOCK_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> CLOCK_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef CLOCK_CONFIG_DEBUG_COLOR
-#define CLOCK_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> COMP_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef COMP_CONFIG_LOG_ENABLED
-#define COMP_CONFIG_LOG_ENABLED 0
-#endif
-// <o> COMP_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef COMP_CONFIG_LOG_LEVEL
-#define COMP_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> COMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef COMP_CONFIG_INFO_COLOR
-#define COMP_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> COMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef COMP_CONFIG_DEBUG_COLOR
-#define COMP_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef GPIOTE_CONFIG_LOG_ENABLED
-#define GPIOTE_CONFIG_LOG_ENABLED 0
-#endif
-// <o> GPIOTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef GPIOTE_CONFIG_LOG_LEVEL
-#define GPIOTE_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> GPIOTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef GPIOTE_CONFIG_INFO_COLOR
-#define GPIOTE_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> GPIOTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef GPIOTE_CONFIG_DEBUG_COLOR
-#define GPIOTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef LPCOMP_CONFIG_LOG_ENABLED
-#define LPCOMP_CONFIG_LOG_ENABLED 0
-#endif
-// <o> LPCOMP_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef LPCOMP_CONFIG_LOG_LEVEL
-#define LPCOMP_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> LPCOMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef LPCOMP_CONFIG_INFO_COLOR
-#define LPCOMP_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> LPCOMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef LPCOMP_CONFIG_DEBUG_COLOR
-#define LPCOMP_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> MAX3421E_HOST_CONFIG_LOG_ENABLED - Enable logging in the module
-//==========================================================
-#ifndef MAX3421E_HOST_CONFIG_LOG_ENABLED
-#define MAX3421E_HOST_CONFIG_LOG_ENABLED 0
-#endif
-// <o> MAX3421E_HOST_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef MAX3421E_HOST_CONFIG_LOG_LEVEL
-#define MAX3421E_HOST_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> MAX3421E_HOST_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef MAX3421E_HOST_CONFIG_INFO_COLOR
-#define MAX3421E_HOST_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> MAX3421E_HOST_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef MAX3421E_HOST_CONFIG_DEBUG_COLOR
-#define MAX3421E_HOST_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRFX_USBD_CONFIG_LOG_ENABLED - Enable logging in the module
-//==========================================================
-#ifndef NRFX_USBD_CONFIG_LOG_ENABLED
-#define NRFX_USBD_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRFX_USBD_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRFX_USBD_CONFIG_LOG_LEVEL
-#define NRFX_USBD_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRFX_USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_USBD_CONFIG_INFO_COLOR
-#define NRFX_USBD_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRFX_USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRFX_USBD_CONFIG_DEBUG_COLOR
-#define NRFX_USBD_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef PDM_CONFIG_LOG_ENABLED
-#define PDM_CONFIG_LOG_ENABLED 0
-#endif
-// <o> PDM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef PDM_CONFIG_LOG_LEVEL
-#define PDM_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> PDM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef PDM_CONFIG_INFO_COLOR
-#define PDM_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> PDM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef PDM_CONFIG_DEBUG_COLOR
-#define PDM_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> PPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef PPI_CONFIG_LOG_ENABLED
-#define PPI_CONFIG_LOG_ENABLED 0
-#endif
-// <o> PPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef PPI_CONFIG_LOG_LEVEL
-#define PPI_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> PPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef PPI_CONFIG_INFO_COLOR
-#define PPI_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> PPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef PPI_CONFIG_DEBUG_COLOR
-#define PPI_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef PWM_CONFIG_LOG_ENABLED
-#define PWM_CONFIG_LOG_ENABLED 0
-#endif
-// <o> PWM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef PWM_CONFIG_LOG_LEVEL
-#define PWM_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> PWM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef PWM_CONFIG_INFO_COLOR
-#define PWM_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> PWM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef PWM_CONFIG_DEBUG_COLOR
-#define PWM_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> QDEC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef QDEC_CONFIG_LOG_ENABLED
-#define QDEC_CONFIG_LOG_ENABLED 0
-#endif
-// <o> QDEC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef QDEC_CONFIG_LOG_LEVEL
-#define QDEC_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> QDEC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef QDEC_CONFIG_INFO_COLOR
-#define QDEC_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> QDEC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef QDEC_CONFIG_DEBUG_COLOR
-#define QDEC_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> RNG_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef RNG_CONFIG_LOG_ENABLED
-#define RNG_CONFIG_LOG_ENABLED 0
-#endif
-// <o> RNG_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef RNG_CONFIG_LOG_LEVEL
-#define RNG_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> RNG_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef RNG_CONFIG_INFO_COLOR
-#define RNG_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> RNG_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef RNG_CONFIG_DEBUG_COLOR
-#define RNG_CONFIG_DEBUG_COLOR 0
-#endif
-
-// <q> RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED  - Enables logging of random numbers.
- 
-
-#ifndef RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED
-#define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0
-#endif
-
-// </e>
-
-// <e> RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef RTC_CONFIG_LOG_ENABLED
-#define RTC_CONFIG_LOG_ENABLED 0
-#endif
-// <o> RTC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef RTC_CONFIG_LOG_LEVEL
-#define RTC_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef RTC_CONFIG_INFO_COLOR
-#define RTC_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef RTC_CONFIG_DEBUG_COLOR
-#define RTC_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef SAADC_CONFIG_LOG_ENABLED
-#define SAADC_CONFIG_LOG_ENABLED 0
-#endif
-// <o> SAADC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef SAADC_CONFIG_LOG_LEVEL
-#define SAADC_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> SAADC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef SAADC_CONFIG_INFO_COLOR
-#define SAADC_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> SAADC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef SAADC_CONFIG_DEBUG_COLOR
-#define SAADC_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef SPIS_CONFIG_LOG_ENABLED
-#define SPIS_CONFIG_LOG_ENABLED 0
-#endif
-// <o> SPIS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef SPIS_CONFIG_LOG_LEVEL
-#define SPIS_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> SPIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef SPIS_CONFIG_INFO_COLOR
-#define SPIS_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> SPIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef SPIS_CONFIG_DEBUG_COLOR
-#define SPIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> SPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef SPI_CONFIG_LOG_ENABLED
-#define SPI_CONFIG_LOG_ENABLED 0
-#endif
-// <o> SPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef SPI_CONFIG_LOG_LEVEL
-#define SPI_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> SPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef SPI_CONFIG_INFO_COLOR
-#define SPI_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> SPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef SPI_CONFIG_DEBUG_COLOR
-#define SPI_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef TIMER_CONFIG_LOG_ENABLED
-#define TIMER_CONFIG_LOG_ENABLED 0
-#endif
-// <o> TIMER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef TIMER_CONFIG_LOG_LEVEL
-#define TIMER_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef TIMER_CONFIG_INFO_COLOR
-#define TIMER_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef TIMER_CONFIG_DEBUG_COLOR
-#define TIMER_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef TWIS_CONFIG_LOG_ENABLED
-#define TWIS_CONFIG_LOG_ENABLED 0
-#endif
-// <o> TWIS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef TWIS_CONFIG_LOG_LEVEL
-#define TWIS_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> TWIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef TWIS_CONFIG_INFO_COLOR
-#define TWIS_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> TWIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef TWIS_CONFIG_DEBUG_COLOR
-#define TWIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> TWI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef TWI_CONFIG_LOG_ENABLED
-#define TWI_CONFIG_LOG_ENABLED 0
-#endif
-// <o> TWI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef TWI_CONFIG_LOG_LEVEL
-#define TWI_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> TWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef TWI_CONFIG_INFO_COLOR
-#define TWI_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> TWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef TWI_CONFIG_DEBUG_COLOR
-#define TWI_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> UART_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef UART_CONFIG_LOG_ENABLED
-#define UART_CONFIG_LOG_ENABLED 0
-#endif
-// <o> UART_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef UART_CONFIG_LOG_LEVEL
-#define UART_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef UART_CONFIG_INFO_COLOR
-#define UART_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef UART_CONFIG_DEBUG_COLOR
-#define UART_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> USBD_CONFIG_LOG_ENABLED - Enable logging in the module
-//==========================================================
-#ifndef USBD_CONFIG_LOG_ENABLED
-#define USBD_CONFIG_LOG_ENABLED 0
-#endif
-// <o> USBD_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef USBD_CONFIG_LOG_LEVEL
-#define USBD_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef USBD_CONFIG_INFO_COLOR
-#define USBD_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef USBD_CONFIG_DEBUG_COLOR
-#define USBD_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef WDT_CONFIG_LOG_ENABLED
-#define WDT_CONFIG_LOG_ENABLED 0
-#endif
-// <o> WDT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef WDT_CONFIG_LOG_LEVEL
-#define WDT_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> WDT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef WDT_CONFIG_INFO_COLOR
-#define WDT_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> WDT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef WDT_CONFIG_DEBUG_COLOR
-#define WDT_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </h> 
-//==========================================================
-
-// <h> nrf_log in nRF_Libraries 
-
-//==========================================================
-// <e> APP_BUTTON_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef APP_BUTTON_CONFIG_LOG_ENABLED
-#define APP_BUTTON_CONFIG_LOG_ENABLED 0
-#endif
-// <o> APP_BUTTON_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef APP_BUTTON_CONFIG_LOG_LEVEL
-#define APP_BUTTON_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
- 
-
-// <i> If module generates a lot of logs, initial log level can
-// <i> be decreased to prevent flooding. Severity level can be
-// <i> increased on instance basis.
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL
-#define APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL 3
-#endif
-
-// <o> APP_BUTTON_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_BUTTON_CONFIG_INFO_COLOR
-#define APP_BUTTON_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> APP_BUTTON_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_BUTTON_CONFIG_DEBUG_COLOR
-#define APP_BUTTON_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> APP_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef APP_TIMER_CONFIG_LOG_ENABLED
-#define APP_TIMER_CONFIG_LOG_ENABLED 0
-#endif
-// <o> APP_TIMER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef APP_TIMER_CONFIG_LOG_LEVEL
-#define APP_TIMER_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> APP_TIMER_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
- 
-
-// <i> If module generates a lot of logs, initial log level can
-// <i> be decreased to prevent flooding. Severity level can be
-// <i> increased on instance basis.
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef APP_TIMER_CONFIG_INITIAL_LOG_LEVEL
-#define APP_TIMER_CONFIG_INITIAL_LOG_LEVEL 3
-#endif
-
-// <o> APP_TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_TIMER_CONFIG_INFO_COLOR
-#define APP_TIMER_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> APP_TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_TIMER_CONFIG_DEBUG_COLOR
-#define APP_TIMER_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED
-#define APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED 0
-#endif
-// <o> APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL
-#define APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> APP_USBD_CDC_ACM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_USBD_CDC_ACM_CONFIG_INFO_COLOR
-#define APP_USBD_CDC_ACM_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR
-#define APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> APP_USBD_CONFIG_LOG_ENABLED - Enable logging in the module.
-//==========================================================
-#ifndef APP_USBD_CONFIG_LOG_ENABLED
-#define APP_USBD_CONFIG_LOG_ENABLED 0
-#endif
-// <o> APP_USBD_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef APP_USBD_CONFIG_LOG_LEVEL
-#define APP_USBD_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> APP_USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_USBD_CONFIG_INFO_COLOR
-#define APP_USBD_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> APP_USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_USBD_CONFIG_DEBUG_COLOR
-#define APP_USBD_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> APP_USBD_DUMMY_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef APP_USBD_DUMMY_CONFIG_LOG_ENABLED
-#define APP_USBD_DUMMY_CONFIG_LOG_ENABLED 0
-#endif
-// <o> APP_USBD_DUMMY_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef APP_USBD_DUMMY_CONFIG_LOG_LEVEL
-#define APP_USBD_DUMMY_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> APP_USBD_DUMMY_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_USBD_DUMMY_CONFIG_INFO_COLOR
-#define APP_USBD_DUMMY_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> APP_USBD_DUMMY_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_USBD_DUMMY_CONFIG_DEBUG_COLOR
-#define APP_USBD_DUMMY_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> APP_USBD_MSC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef APP_USBD_MSC_CONFIG_LOG_ENABLED
-#define APP_USBD_MSC_CONFIG_LOG_ENABLED 0
-#endif
-// <o> APP_USBD_MSC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef APP_USBD_MSC_CONFIG_LOG_LEVEL
-#define APP_USBD_MSC_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> APP_USBD_MSC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_USBD_MSC_CONFIG_INFO_COLOR
-#define APP_USBD_MSC_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> APP_USBD_MSC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_USBD_MSC_CONFIG_DEBUG_COLOR
-#define APP_USBD_MSC_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED
-#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED 0
-#endif
-// <o> APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL
-#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR
-#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR
-#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_ATFIFO_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_ATFIFO_CONFIG_LOG_ENABLED
-#define NRF_ATFIFO_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_ATFIFO_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_ATFIFO_CONFIG_LOG_LEVEL
-#define NRF_ATFIFO_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL
-#define NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL 3
-#endif
-
-// <o> NRF_ATFIFO_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_ATFIFO_CONFIG_INFO_COLOR
-#define NRF_ATFIFO_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_ATFIFO_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_ATFIFO_CONFIG_DEBUG_COLOR
-#define NRF_ATFIFO_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_BALLOC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_BALLOC_CONFIG_LOG_ENABLED
-#define NRF_BALLOC_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_BALLOC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_BALLOC_CONFIG_LOG_LEVEL
-#define NRF_BALLOC_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
- 
-
-// <i> If module generates a lot of logs, initial log level can
-// <i> be decreased to prevent flooding. Severity level can be
-// <i> increased on instance basis.
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL
-#define NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL 3
-#endif
-
-// <o> NRF_BALLOC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_BALLOC_CONFIG_INFO_COLOR
-#define NRF_BALLOC_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_BALLOC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_BALLOC_CONFIG_DEBUG_COLOR
-#define NRF_BALLOC_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED
-#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL
-#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL
-#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL 3
-#endif
-
-// <o> NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR
-#define NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR
-#define NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED
-#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL
-#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL
-#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL 3
-#endif
-
-// <o> NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR
-#define NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR
-#define NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED
-#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL
-#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL
-#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL 3
-#endif
-
-// <o> NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR
-#define NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR
-#define NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED
-#define NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL
-#define NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_CLI_BLE_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_CLI_BLE_UART_CONFIG_INFO_COLOR
-#define NRF_CLI_BLE_UART_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR
-#define NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED
-#define NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL
-#define NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR
-#define NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR
-#define NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_CLI_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_CLI_UART_CONFIG_LOG_ENABLED
-#define NRF_CLI_UART_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_CLI_UART_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_CLI_UART_CONFIG_LOG_LEVEL
-#define NRF_CLI_UART_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_CLI_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_CLI_UART_CONFIG_INFO_COLOR
-#define NRF_CLI_UART_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_CLI_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_CLI_UART_CONFIG_DEBUG_COLOR
-#define NRF_CLI_UART_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_LIBUARTE_CONFIG_LOG_ENABLED
-#define NRF_LIBUARTE_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_LIBUARTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_LIBUARTE_CONFIG_LOG_LEVEL
-#define NRF_LIBUARTE_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_LIBUARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_LIBUARTE_CONFIG_INFO_COLOR
-#define NRF_LIBUARTE_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_LIBUARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_LIBUARTE_CONFIG_DEBUG_COLOR
-#define NRF_LIBUARTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_MEMOBJ_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_MEMOBJ_CONFIG_LOG_ENABLED
-#define NRF_MEMOBJ_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_MEMOBJ_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_MEMOBJ_CONFIG_LOG_LEVEL
-#define NRF_MEMOBJ_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_MEMOBJ_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_MEMOBJ_CONFIG_INFO_COLOR
-#define NRF_MEMOBJ_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_MEMOBJ_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_MEMOBJ_CONFIG_DEBUG_COLOR
-#define NRF_MEMOBJ_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_PWR_MGMT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_PWR_MGMT_CONFIG_LOG_ENABLED
-#define NRF_PWR_MGMT_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_PWR_MGMT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_PWR_MGMT_CONFIG_LOG_LEVEL
-#define NRF_PWR_MGMT_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_PWR_MGMT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_PWR_MGMT_CONFIG_INFO_COLOR
-#define NRF_PWR_MGMT_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_PWR_MGMT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_COLOR
-#define NRF_PWR_MGMT_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_QUEUE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_QUEUE_CONFIG_LOG_ENABLED
-#define NRF_QUEUE_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_QUEUE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_QUEUE_CONFIG_LOG_LEVEL
-#define NRF_QUEUE_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL
-#define NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL 3
-#endif
-
-// <o> NRF_QUEUE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_QUEUE_CONFIG_INFO_COLOR
-#define NRF_QUEUE_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_QUEUE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_QUEUE_CONFIG_DEBUG_COLOR
-#define NRF_QUEUE_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_SDH_ANT_LOG_ENABLED - Enable logging in SoftDevice handler (ANT) module.
-//==========================================================
-#ifndef NRF_SDH_ANT_LOG_ENABLED
-#define NRF_SDH_ANT_LOG_ENABLED 0
-#endif
-// <o> NRF_SDH_ANT_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_SDH_ANT_LOG_LEVEL
-#define NRF_SDH_ANT_LOG_LEVEL 3
-#endif
-
-// <o> NRF_SDH_ANT_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_SDH_ANT_INFO_COLOR
-#define NRF_SDH_ANT_INFO_COLOR 0
-#endif
-
-// <o> NRF_SDH_ANT_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_SDH_ANT_DEBUG_COLOR
-#define NRF_SDH_ANT_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_SDH_BLE_LOG_ENABLED - Enable logging in SoftDevice handler (BLE) module.
-//==========================================================
-#ifndef NRF_SDH_BLE_LOG_ENABLED
-#define NRF_SDH_BLE_LOG_ENABLED 1
-#endif
-// <o> NRF_SDH_BLE_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_SDH_BLE_LOG_LEVEL
-#define NRF_SDH_BLE_LOG_LEVEL 3
-#endif
-
-// <o> NRF_SDH_BLE_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_SDH_BLE_INFO_COLOR
-#define NRF_SDH_BLE_INFO_COLOR 0
-#endif
-
-// <o> NRF_SDH_BLE_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_SDH_BLE_DEBUG_COLOR
-#define NRF_SDH_BLE_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_SDH_LOG_ENABLED - Enable logging in SoftDevice handler module.
-//==========================================================
-#ifndef NRF_SDH_LOG_ENABLED
-#define NRF_SDH_LOG_ENABLED 1
-#endif
-// <o> NRF_SDH_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_SDH_LOG_LEVEL
-#define NRF_SDH_LOG_LEVEL 3
-#endif
-
-// <o> NRF_SDH_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_SDH_INFO_COLOR
-#define NRF_SDH_INFO_COLOR 0
-#endif
-
-// <o> NRF_SDH_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_SDH_DEBUG_COLOR
-#define NRF_SDH_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_SDH_SOC_LOG_ENABLED - Enable logging in SoftDevice handler (SoC) module.
-//==========================================================
-#ifndef NRF_SDH_SOC_LOG_ENABLED
-#define NRF_SDH_SOC_LOG_ENABLED 1
-#endif
-// <o> NRF_SDH_SOC_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_SDH_SOC_LOG_LEVEL
-#define NRF_SDH_SOC_LOG_LEVEL 3
-#endif
-
-// <o> NRF_SDH_SOC_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_SDH_SOC_INFO_COLOR
-#define NRF_SDH_SOC_INFO_COLOR 0
-#endif
-
-// <o> NRF_SDH_SOC_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_SDH_SOC_DEBUG_COLOR
-#define NRF_SDH_SOC_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_SORTLIST_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_SORTLIST_CONFIG_LOG_ENABLED
-#define NRF_SORTLIST_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_SORTLIST_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_SORTLIST_CONFIG_LOG_LEVEL
-#define NRF_SORTLIST_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_SORTLIST_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_SORTLIST_CONFIG_INFO_COLOR
-#define NRF_SORTLIST_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_SORTLIST_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_SORTLIST_CONFIG_DEBUG_COLOR
-#define NRF_SORTLIST_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> NRF_TWI_SENSOR_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NRF_TWI_SENSOR_CONFIG_LOG_ENABLED
-#define NRF_TWI_SENSOR_CONFIG_LOG_ENABLED 0
-#endif
-// <o> NRF_TWI_SENSOR_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NRF_TWI_SENSOR_CONFIG_LOG_LEVEL
-#define NRF_TWI_SENSOR_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> NRF_TWI_SENSOR_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_TWI_SENSOR_CONFIG_INFO_COLOR
-#define NRF_TWI_SENSOR_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR
-#define NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <e> PM_LOG_ENABLED - Enable logging in Peer Manager and its submodules.
-//==========================================================
-#ifndef PM_LOG_ENABLED
-#define PM_LOG_ENABLED 1
-#endif
-// <o> PM_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef PM_LOG_LEVEL
-#define PM_LOG_LEVEL 3
-#endif
-
-// <o> PM_LOG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef PM_LOG_INFO_COLOR
-#define PM_LOG_INFO_COLOR 0
-#endif
-
-// <o> PM_LOG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef PM_LOG_DEBUG_COLOR
-#define PM_LOG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </h> 
-//==========================================================
-
-// <h> nrf_log in nRF_Serialization 
-
-//==========================================================
-// <e> SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED
-#define SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED 0
-#endif
-// <o> SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL
-#define SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL 3
-#endif
-
-// <o> SER_HAL_TRANSPORT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef SER_HAL_TRANSPORT_CONFIG_INFO_COLOR
-#define SER_HAL_TRANSPORT_CONFIG_INFO_COLOR 0
-#endif
-
-// <o> SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR
-#define SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </h> 
-//==========================================================
-
-// </h> 
-//==========================================================
-
-// </e>
-
-// <q> NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED  - nrf_log_str_formatter - Log string formatter
- 
-
-#ifndef NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED
-#define NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED 1
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> nRF_NFC 
-
-//==========================================================
-// <q> NFC_AC_REC_ENABLED  - nfc_ac_rec - NFC NDEF Alternative Carrier record encoder
- 
-
-#ifndef NFC_AC_REC_ENABLED
-#define NFC_AC_REC_ENABLED 0
-#endif
-
-// <q> NFC_AC_REC_PARSER_ENABLED  - nfc_ac_rec_parser - Alternative Carrier record parser
- 
-
-#ifndef NFC_AC_REC_PARSER_ENABLED
-#define NFC_AC_REC_PARSER_ENABLED 0
-#endif
-
-// <e> NFC_BLE_OOB_ADVDATA_ENABLED - nfc_ble_oob_advdata - AD data for OOB pairing encoder
-//==========================================================
-#ifndef NFC_BLE_OOB_ADVDATA_ENABLED
-#define NFC_BLE_OOB_ADVDATA_ENABLED 0
-#endif
-// <o> ADVANCED_ADVDATA_SUPPORT  - Non-mandatory AD types for BLE OOB pairing are encoded inside the NDEF message (e.g. service UUIDs)
- 
-// <1=> Enabled 
-// <0=> Disabled 
-
-#ifndef ADVANCED_ADVDATA_SUPPORT
-#define ADVANCED_ADVDATA_SUPPORT 0
-#endif
-
-// </e>
-
-// <q> NFC_BLE_OOB_ADVDATA_PARSER_ENABLED  - nfc_ble_oob_advdata_parser - BLE OOB pairing AD data parser
- 
-
-#ifndef NFC_BLE_OOB_ADVDATA_PARSER_ENABLED
-#define NFC_BLE_OOB_ADVDATA_PARSER_ENABLED 0
-#endif
-
-// <e> NFC_BLE_PAIR_LIB_ENABLED - nfc_ble_pair_lib - Library parameters
-//==========================================================
-#ifndef NFC_BLE_PAIR_LIB_ENABLED
-#define NFC_BLE_PAIR_LIB_ENABLED 0
-#endif
-// <e> NFC_BLE_PAIR_LIB_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NFC_BLE_PAIR_LIB_LOG_ENABLED
-#define NFC_BLE_PAIR_LIB_LOG_ENABLED 0
-#endif
-// <o> NFC_BLE_PAIR_LIB_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NFC_BLE_PAIR_LIB_LOG_LEVEL
-#define NFC_BLE_PAIR_LIB_LOG_LEVEL 3
-#endif
-
-// <o> NFC_BLE_PAIR_LIB_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NFC_BLE_PAIR_LIB_INFO_COLOR
-#define NFC_BLE_PAIR_LIB_INFO_COLOR 0
-#endif
-
-// <o> NFC_BLE_PAIR_LIB_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NFC_BLE_PAIR_LIB_DEBUG_COLOR
-#define NFC_BLE_PAIR_LIB_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// <h> NFC_BLE_PAIR_LIB_SECURITY_PARAMETERS - Common Peer Manager security parameters.
-
-//==========================================================
-// <e> BLE_NFC_SEC_PARAM_BOND - Enables device bonding.
-
-// <i> If bonding is enabled at least one of the BLE_NFC_SEC_PARAM_KDIST options must be enabled.
-//==========================================================
-#ifndef BLE_NFC_SEC_PARAM_BOND
-#define BLE_NFC_SEC_PARAM_BOND 1
-#endif
-// <q> BLE_NFC_SEC_PARAM_KDIST_OWN_ENC  - Enables Long Term Key and Master Identification distribution by device.
- 
-
-#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ENC
-#define BLE_NFC_SEC_PARAM_KDIST_OWN_ENC 1
-#endif
-
-// <q> BLE_NFC_SEC_PARAM_KDIST_OWN_ID  - Enables Identity Resolving Key and Identity Address Information distribution by device.
- 
-
-#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ID
-#define BLE_NFC_SEC_PARAM_KDIST_OWN_ID 1
-#endif
-
-// <q> BLE_NFC_SEC_PARAM_KDIST_PEER_ENC  - Enables Long Term Key and Master Identification distribution by peer.
- 
-
-#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ENC
-#define BLE_NFC_SEC_PARAM_KDIST_PEER_ENC 1
-#endif
-
-// <q> BLE_NFC_SEC_PARAM_KDIST_PEER_ID  - Enables Identity Resolving Key and Identity Address Information distribution by peer.
- 
-
-#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ID
-#define BLE_NFC_SEC_PARAM_KDIST_PEER_ID 1
-#endif
-
-// </e>
-
-// <o> BLE_NFC_SEC_PARAM_MIN_KEY_SIZE  - Minimal size of a security key.
- 
-// <7=> 7 
-// <8=> 8 
-// <9=> 9 
-// <10=> 10 
-// <11=> 11 
-// <12=> 12 
-// <13=> 13 
-// <14=> 14 
-// <15=> 15 
-// <16=> 16 
-
-#ifndef BLE_NFC_SEC_PARAM_MIN_KEY_SIZE
-#define BLE_NFC_SEC_PARAM_MIN_KEY_SIZE 7
-#endif
-
-// <o> BLE_NFC_SEC_PARAM_MAX_KEY_SIZE  - Maximal size of a security key.
- 
-// <7=> 7 
-// <8=> 8 
-// <9=> 9 
-// <10=> 10 
-// <11=> 11 
-// <12=> 12 
-// <13=> 13 
-// <14=> 14 
-// <15=> 15 
-// <16=> 16 
-
-#ifndef BLE_NFC_SEC_PARAM_MAX_KEY_SIZE
-#define BLE_NFC_SEC_PARAM_MAX_KEY_SIZE 16
-#endif
-
-// </h> 
-//==========================================================
-
-// </e>
-
-// <q> NFC_BLE_PAIR_MSG_ENABLED  - nfc_ble_pair_msg - NDEF message for OOB pairing encoder
- 
-
-#ifndef NFC_BLE_PAIR_MSG_ENABLED
-#define NFC_BLE_PAIR_MSG_ENABLED 0
-#endif
-
-// <q> NFC_CH_COMMON_ENABLED  - nfc_ble_pair_common - OOB pairing common data
- 
-
-#ifndef NFC_CH_COMMON_ENABLED
-#define NFC_CH_COMMON_ENABLED 0
-#endif
-
-// <q> NFC_EP_OOB_REC_ENABLED  - nfc_ep_oob_rec - EP record for BLE pairing encoder
- 
-
-#ifndef NFC_EP_OOB_REC_ENABLED
-#define NFC_EP_OOB_REC_ENABLED 0
-#endif
-
-// <q> NFC_HS_REC_ENABLED  - nfc_hs_rec - Handover Select NDEF record encoder
- 
-
-#ifndef NFC_HS_REC_ENABLED
-#define NFC_HS_REC_ENABLED 0
-#endif
-
-// <q> NFC_LE_OOB_REC_ENABLED  - nfc_le_oob_rec - LE record for BLE pairing encoder
- 
-
-#ifndef NFC_LE_OOB_REC_ENABLED
-#define NFC_LE_OOB_REC_ENABLED 0
-#endif
-
-// <q> NFC_LE_OOB_REC_PARSER_ENABLED  - nfc_le_oob_rec_parser - LE record parser
- 
-
-#ifndef NFC_LE_OOB_REC_PARSER_ENABLED
-#define NFC_LE_OOB_REC_PARSER_ENABLED 0
-#endif
-
-// <q> NFC_NDEF_LAUNCHAPP_MSG_ENABLED  - nfc_launchapp_msg - Encoding data for NDEF Application Launching message for NFC Tag
- 
-
-#ifndef NFC_NDEF_LAUNCHAPP_MSG_ENABLED
-#define NFC_NDEF_LAUNCHAPP_MSG_ENABLED 0
-#endif
-
-// <q> NFC_NDEF_LAUNCHAPP_REC_ENABLED  - nfc_launchapp_rec - Encoding data for NDEF Application Launching record for NFC Tag
- 
-
-#ifndef NFC_NDEF_LAUNCHAPP_REC_ENABLED
-#define NFC_NDEF_LAUNCHAPP_REC_ENABLED 0
-#endif
-
-// <e> NFC_NDEF_MSG_ENABLED - nfc_ndef_msg - NFC NDEF Message generator module
-//==========================================================
-#ifndef NFC_NDEF_MSG_ENABLED
-#define NFC_NDEF_MSG_ENABLED 0
-#endif
-// <o> NFC_NDEF_MSG_TAG_TYPE  - NFC Tag Type
- 
-// <2=> Type 2 Tag 
-// <4=> Type 4 Tag 
-
-#ifndef NFC_NDEF_MSG_TAG_TYPE
-#define NFC_NDEF_MSG_TAG_TYPE 2
-#endif
-
-// </e>
-
-// <e> NFC_NDEF_MSG_PARSER_ENABLED - nfc_ndef_msg_parser - NFC NDEF message parser module
-//==========================================================
-#ifndef NFC_NDEF_MSG_PARSER_ENABLED
-#define NFC_NDEF_MSG_PARSER_ENABLED 0
-#endif
-// <e> NFC_NDEF_MSG_PARSER_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NFC_NDEF_MSG_PARSER_LOG_ENABLED
-#define NFC_NDEF_MSG_PARSER_LOG_ENABLED 0
-#endif
-// <o> NFC_NDEF_MSG_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NFC_NDEF_MSG_PARSER_LOG_LEVEL
-#define NFC_NDEF_MSG_PARSER_LOG_LEVEL 3
-#endif
-
-// <o> NFC_NDEF_MSG_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NFC_NDEF_MSG_PARSER_INFO_COLOR
-#define NFC_NDEF_MSG_PARSER_INFO_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <q> NFC_NDEF_RECORD_ENABLED  - nfc_ndef_record - NFC NDEF Record generator module
- 
-
-#ifndef NFC_NDEF_RECORD_ENABLED
-#define NFC_NDEF_RECORD_ENABLED 0
-#endif
-
-// <e> NFC_NDEF_RECORD_PARSER_ENABLED - nfc_ndef_record_parser - NFC NDEF Record parser module
-//==========================================================
-#ifndef NFC_NDEF_RECORD_PARSER_ENABLED
-#define NFC_NDEF_RECORD_PARSER_ENABLED 0
-#endif
-// <e> NFC_NDEF_RECORD_PARSER_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NFC_NDEF_RECORD_PARSER_LOG_ENABLED
-#define NFC_NDEF_RECORD_PARSER_LOG_ENABLED 0
-#endif
-// <o> NFC_NDEF_RECORD_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NFC_NDEF_RECORD_PARSER_LOG_LEVEL
-#define NFC_NDEF_RECORD_PARSER_LOG_LEVEL 3
-#endif
-
-// <o> NFC_NDEF_RECORD_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NFC_NDEF_RECORD_PARSER_INFO_COLOR
-#define NFC_NDEF_RECORD_PARSER_INFO_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <q> NFC_NDEF_TEXT_RECORD_ENABLED  - nfc_text_rec - Encoding data for a text record for NFC Tag
- 
-
-#ifndef NFC_NDEF_TEXT_RECORD_ENABLED
-#define NFC_NDEF_TEXT_RECORD_ENABLED 0
-#endif
-
-// <q> NFC_NDEF_URI_MSG_ENABLED  - nfc_uri_msg - Encoding data for NDEF message with URI record for NFC Tag
- 
-
-#ifndef NFC_NDEF_URI_MSG_ENABLED
-#define NFC_NDEF_URI_MSG_ENABLED 0
-#endif
-
-// <q> NFC_NDEF_URI_REC_ENABLED  - nfc_uri_rec - Encoding data for a URI record for NFC Tag
- 
-
-#ifndef NFC_NDEF_URI_REC_ENABLED
-#define NFC_NDEF_URI_REC_ENABLED 0
-#endif
-
-// <e> NFC_PLATFORM_ENABLED - nfc_platform - NFC platform module for Clock control.
-//==========================================================
-#ifndef NFC_PLATFORM_ENABLED
-#define NFC_PLATFORM_ENABLED 0
-#endif
-// <e> NFC_PLATFORM_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NFC_PLATFORM_LOG_ENABLED
-#define NFC_PLATFORM_LOG_ENABLED 0
-#endif
-// <o> NFC_PLATFORM_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NFC_PLATFORM_LOG_LEVEL
-#define NFC_PLATFORM_LOG_LEVEL 3
-#endif
-
-// <o> NFC_PLATFORM_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NFC_PLATFORM_INFO_COLOR
-#define NFC_PLATFORM_INFO_COLOR 0
-#endif
-
-// <o> NFC_PLATFORM_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NFC_PLATFORM_DEBUG_COLOR
-#define NFC_PLATFORM_DEBUG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NFC_T2T_PARSER_ENABLED - nfc_type_2_tag_parser - Parser for decoding Type 2 Tag data
-//==========================================================
-#ifndef NFC_T2T_PARSER_ENABLED
-#define NFC_T2T_PARSER_ENABLED 0
-#endif
-// <e> NFC_T2T_PARSER_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NFC_T2T_PARSER_LOG_ENABLED
-#define NFC_T2T_PARSER_LOG_ENABLED 0
-#endif
-// <o> NFC_T2T_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NFC_T2T_PARSER_LOG_LEVEL
-#define NFC_T2T_PARSER_LOG_LEVEL 3
-#endif
-
-// <o> NFC_T2T_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NFC_T2T_PARSER_INFO_COLOR
-#define NFC_T2T_PARSER_INFO_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NFC_T4T_APDU_ENABLED - nfc_t4t_apdu - APDU encoder/decoder for Type 4 Tag
-//==========================================================
-#ifndef NFC_T4T_APDU_ENABLED
-#define NFC_T4T_APDU_ENABLED 0
-#endif
-// <e> NFC_T4T_APDU_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NFC_T4T_APDU_LOG_ENABLED
-#define NFC_T4T_APDU_LOG_ENABLED 0
-#endif
-// <o> NFC_T4T_APDU_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NFC_T4T_APDU_LOG_LEVEL
-#define NFC_T4T_APDU_LOG_LEVEL 3
-#endif
-
-// <o> NFC_T4T_APDU_LOG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NFC_T4T_APDU_LOG_COLOR
-#define NFC_T4T_APDU_LOG_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NFC_T4T_CC_FILE_PARSER_ENABLED - nfc_t4t_cc_file - Capability Container file for Type 4 Tag
-//==========================================================
-#ifndef NFC_T4T_CC_FILE_PARSER_ENABLED
-#define NFC_T4T_CC_FILE_PARSER_ENABLED 0
-#endif
-// <e> NFC_T4T_CC_FILE_PARSER_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NFC_T4T_CC_FILE_PARSER_LOG_ENABLED
-#define NFC_T4T_CC_FILE_PARSER_LOG_ENABLED 0
-#endif
-// <o> NFC_T4T_CC_FILE_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NFC_T4T_CC_FILE_PARSER_LOG_LEVEL
-#define NFC_T4T_CC_FILE_PARSER_LOG_LEVEL 3
-#endif
-
-// <o> NFC_T4T_CC_FILE_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NFC_T4T_CC_FILE_PARSER_INFO_COLOR
-#define NFC_T4T_CC_FILE_PARSER_INFO_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// <e> NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED - nfc_t4t_hl_detection_procedures - NDEF Detection Procedure for Type 4 Tag
-//==========================================================
-#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED
-#define NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED 0
-#endif
-// <e> NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED
-#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED 0
-#endif
-// <o> NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL
-#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL 3
-#endif
-
-// <o> NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR
-#define NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR 0
-#endif
-
-// </e>
-
-// <o> APDU_BUFF_SIZE - Size (in bytes) of the buffer for APDU storage 
-#ifndef APDU_BUFF_SIZE
-#define APDU_BUFF_SIZE 250
-#endif
-
-// <o> CC_STORAGE_BUFF_SIZE - Size (in bytes) of the buffer for CC file storage 
-#ifndef CC_STORAGE_BUFF_SIZE
-#define CC_STORAGE_BUFF_SIZE 64
-#endif
-
-// </e>
-
-// <e> NFC_T4T_TLV_BLOCK_PARSER_ENABLED - nfc_t4t_tlv_block - TLV block for Type 4 Tag
-//==========================================================
-#ifndef NFC_T4T_TLV_BLOCK_PARSER_ENABLED
-#define NFC_T4T_TLV_BLOCK_PARSER_ENABLED 0
-#endif
-// <e> NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED
-#define NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED 0
-#endif
-// <o> NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
-
-#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL
-#define NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL 3
-#endif
-
-// <o> NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
-
-#ifndef NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR
-#define NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR 0
-#endif
-
-// </e>
-
-// </e>
-
-// </h> 
-//==========================================================
-
-// <h> nRF_SoftDevice 
-
-//==========================================================
-// <e> NRF_SDH_BLE_ENABLED - nrf_sdh_ble - SoftDevice BLE event handler
-//==========================================================
-#ifndef NRF_SDH_BLE_ENABLED
-#define NRF_SDH_BLE_ENABLED 0
-#endif
-// <h> BLE Stack configuration - Stack configuration parameters
-
-// <i> The SoftDevice handler will configure the stack with these parameters when calling @ref nrf_sdh_ble_default_cfg_set.
-// <i> Other libraries might depend on these values; keep them up-to-date even if you are not explicitely calling @ref nrf_sdh_ble_default_cfg_set.
-//==========================================================
-// <o> NRF_SDH_BLE_GAP_DATA_LENGTH   <27-251> 
-
-
-// <i> Requested BLE GAP data length to be negotiated.
-
-#ifndef NRF_SDH_BLE_GAP_DATA_LENGTH
-#define NRF_SDH_BLE_GAP_DATA_LENGTH 27
-#endif
-
-// <o> NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links. 
-#ifndef NRF_SDH_BLE_PERIPHERAL_LINK_COUNT
-#define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT 0
-#endif
-
-// <o> NRF_SDH_BLE_CENTRAL_LINK_COUNT - Maximum number of central links. 
-#ifndef NRF_SDH_BLE_CENTRAL_LINK_COUNT
-#define NRF_SDH_BLE_CENTRAL_LINK_COUNT 0
-#endif
-
-// <o> NRF_SDH_BLE_TOTAL_LINK_COUNT - Total link count. 
-// <i> Maximum number of total concurrent connections using the default configuration.
-
-#ifndef NRF_SDH_BLE_TOTAL_LINK_COUNT
-#define NRF_SDH_BLE_TOTAL_LINK_COUNT 1
-#endif
-
-// <o> NRF_SDH_BLE_GAP_EVENT_LENGTH - GAP event length. 
-// <i> The time set aside for this connection on every connection interval in 1.25 ms units.
-
-#ifndef NRF_SDH_BLE_GAP_EVENT_LENGTH
-#define NRF_SDH_BLE_GAP_EVENT_LENGTH 6
-#endif
-
-// <o> NRF_SDH_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size. 
-#ifndef NRF_SDH_BLE_GATT_MAX_MTU_SIZE
-#define NRF_SDH_BLE_GATT_MAX_MTU_SIZE 23
-#endif
-
-// <o> NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE - Attribute Table size in bytes. The size must be a multiple of 4. 
-#ifndef NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE
-#define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE 1408
-#endif
-
-// <o> NRF_SDH_BLE_VS_UUID_COUNT - The number of vendor-specific UUIDs. 
-#ifndef NRF_SDH_BLE_VS_UUID_COUNT
-#define NRF_SDH_BLE_VS_UUID_COUNT 0
-#endif
-
-// <q> NRF_SDH_BLE_SERVICE_CHANGED  - Include the Service Changed characteristic in the Attribute Table.
- 
-
-#ifndef NRF_SDH_BLE_SERVICE_CHANGED
-#define NRF_SDH_BLE_SERVICE_CHANGED 0
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> BLE Observers - Observers and priority levels
-
-//==========================================================
-// <o> NRF_SDH_BLE_OBSERVER_PRIO_LEVELS - Total number of priority levels for BLE observers. 
-// <i> This setting configures the number of priority levels available for BLE event handlers.
-// <i> The priority level of a handler determines the order in which it receives events, with respect to other handlers.
-
-#ifndef NRF_SDH_BLE_OBSERVER_PRIO_LEVELS
-#define NRF_SDH_BLE_OBSERVER_PRIO_LEVELS 4
-#endif
-
-// <h> BLE Observers priorities - Invididual priorities
-
-//==========================================================
-// <o> BLE_ADV_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Advertising module.
-
-#ifndef BLE_ADV_BLE_OBSERVER_PRIO
-#define BLE_ADV_BLE_OBSERVER_PRIO 1
-#endif
-
-// <o> BLE_ANCS_C_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Apple Notification Service Client.
-
-#ifndef BLE_ANCS_C_BLE_OBSERVER_PRIO
-#define BLE_ANCS_C_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_ANS_C_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Alert Notification Service Client.
-
-#ifndef BLE_ANS_C_BLE_OBSERVER_PRIO
-#define BLE_ANS_C_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_BAS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Battery Service.
-
-#ifndef BLE_BAS_BLE_OBSERVER_PRIO
-#define BLE_BAS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_BAS_C_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Battery Service Client.
-
-#ifndef BLE_BAS_C_BLE_OBSERVER_PRIO
-#define BLE_BAS_C_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_BPS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Blood Pressure Service.
-
-#ifndef BLE_BPS_BLE_OBSERVER_PRIO
-#define BLE_BPS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_CONN_PARAMS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Connection parameters module.
-
-#ifndef BLE_CONN_PARAMS_BLE_OBSERVER_PRIO
-#define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO 1
-#endif
-
-// <o> BLE_CONN_STATE_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Connection State module.
-
-#ifndef BLE_CONN_STATE_BLE_OBSERVER_PRIO
-#define BLE_CONN_STATE_BLE_OBSERVER_PRIO 0
-#endif
-
-// <o> BLE_CSCS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Cycling Speed and Cadence Service.
-
-#ifndef BLE_CSCS_BLE_OBSERVER_PRIO
-#define BLE_CSCS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_CTS_C_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Current Time Service Client.
-
-#ifndef BLE_CTS_C_BLE_OBSERVER_PRIO
-#define BLE_CTS_C_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_DB_DISC_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Database Discovery module.
-
-#ifndef BLE_DB_DISC_BLE_OBSERVER_PRIO
-#define BLE_DB_DISC_BLE_OBSERVER_PRIO 1
-#endif
-
-// <o> BLE_DFU_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the DFU Service.
-
-#ifndef BLE_DFU_BLE_OBSERVER_PRIO
-#define BLE_DFU_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_DIS_C_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Device Information Client.
-
-#ifndef BLE_DIS_C_BLE_OBSERVER_PRIO
-#define BLE_DIS_C_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_GLS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Glucose Service.
-
-#ifndef BLE_GLS_BLE_OBSERVER_PRIO
-#define BLE_GLS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_HIDS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Human Interface Device Service.
-
-#ifndef BLE_HIDS_BLE_OBSERVER_PRIO
-#define BLE_HIDS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_HRS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Heart Rate Service.
-
-#ifndef BLE_HRS_BLE_OBSERVER_PRIO
-#define BLE_HRS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_HRS_C_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Heart Rate Service Client.
-
-#ifndef BLE_HRS_C_BLE_OBSERVER_PRIO
-#define BLE_HRS_C_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_HTS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Health Thermometer Service.
-
-#ifndef BLE_HTS_BLE_OBSERVER_PRIO
-#define BLE_HTS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_IAS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Immediate Alert Service.
-
-#ifndef BLE_IAS_BLE_OBSERVER_PRIO
-#define BLE_IAS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_IAS_C_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Immediate Alert Service Client.
-
-#ifndef BLE_IAS_C_BLE_OBSERVER_PRIO
-#define BLE_IAS_C_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_LBS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the LED Button Service.
-
-#ifndef BLE_LBS_BLE_OBSERVER_PRIO
-#define BLE_LBS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_LBS_C_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the LED Button Service Client.
-
-#ifndef BLE_LBS_C_BLE_OBSERVER_PRIO
-#define BLE_LBS_C_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_LLS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Link Loss Service.
-
-#ifndef BLE_LLS_BLE_OBSERVER_PRIO
-#define BLE_LLS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_LNS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Location Navigation Service.
-
-#ifndef BLE_LNS_BLE_OBSERVER_PRIO
-#define BLE_LNS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_NUS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the UART Service.
-
-#ifndef BLE_NUS_BLE_OBSERVER_PRIO
-#define BLE_NUS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_NUS_C_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the UART Central Service.
-
-#ifndef BLE_NUS_C_BLE_OBSERVER_PRIO
-#define BLE_NUS_C_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_OTS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Object transfer service.
-
-#ifndef BLE_OTS_BLE_OBSERVER_PRIO
-#define BLE_OTS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_OTS_C_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Object transfer service client.
-
-#ifndef BLE_OTS_C_BLE_OBSERVER_PRIO
-#define BLE_OTS_C_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_RSCS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Running Speed and Cadence Service.
-
-#ifndef BLE_RSCS_BLE_OBSERVER_PRIO
-#define BLE_RSCS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_RSCS_C_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Running Speed and Cadence Client.
-
-#ifndef BLE_RSCS_C_BLE_OBSERVER_PRIO
-#define BLE_RSCS_C_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BLE_TPS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the TX Power Service.
-
-#ifndef BLE_TPS_BLE_OBSERVER_PRIO
-#define BLE_TPS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> BSP_BTN_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Button Control module.
-
-#ifndef BSP_BTN_BLE_OBSERVER_PRIO
-#define BSP_BTN_BLE_OBSERVER_PRIO 1
-#endif
-
-// <o> NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the NFC pairing library.
-
-#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
-#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
-#endif
-
-// <o> NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the NFC pairing library.
-
-#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
-#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
-#endif
-
-// <o> NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the NFC pairing library.
-
-#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
-#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
-#endif
-
-// <o> NRF_BLE_BMS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Bond Management Service.
-
-#ifndef NRF_BLE_BMS_BLE_OBSERVER_PRIO
-#define NRF_BLE_BMS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> NRF_BLE_CGMS_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Contiuon Glucose Monitoring Service.
-
-#ifndef NRF_BLE_CGMS_BLE_OBSERVER_PRIO
-#define NRF_BLE_CGMS_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> NRF_BLE_ES_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Eddystone module.
-
-#ifndef NRF_BLE_ES_BLE_OBSERVER_PRIO
-#define NRF_BLE_ES_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the GATT Service Client.
-
-#ifndef NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO
-#define NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> NRF_BLE_GATT_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the GATT module.
-
-#ifndef NRF_BLE_GATT_BLE_OBSERVER_PRIO
-#define NRF_BLE_GATT_BLE_OBSERVER_PRIO 1
-#endif
-
-// <o> NRF_BLE_GQ_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the GATT Queue module.
-
-#ifndef NRF_BLE_GQ_BLE_OBSERVER_PRIO
-#define NRF_BLE_GQ_BLE_OBSERVER_PRIO 1
-#endif
-
-// <o> NRF_BLE_QWR_BLE_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the Queued writes module.
-
-#ifndef NRF_BLE_QWR_BLE_OBSERVER_PRIO
-#define NRF_BLE_QWR_BLE_OBSERVER_PRIO 2
-#endif
-
-// <o> NRF_BLE_SCAN_OBSERVER_PRIO  
-// <i> Priority for dispatching the BLE events to the Scanning Module.
-
-#ifndef NRF_BLE_SCAN_OBSERVER_PRIO
-#define NRF_BLE_SCAN_OBSERVER_PRIO 1
-#endif
-
-// <o> PM_BLE_OBSERVER_PRIO - Priority with which BLE events are dispatched to the Peer Manager module. 
-#ifndef PM_BLE_OBSERVER_PRIO
-#define PM_BLE_OBSERVER_PRIO 1
-#endif
-
-// </h> 
-//==========================================================
-
-// </h> 
-//==========================================================
-
-
-// </e>
-
-// <e> NRF_SDH_ENABLED - nrf_sdh - SoftDevice handler
-//==========================================================
-#ifndef NRF_SDH_ENABLED
-#define NRF_SDH_ENABLED 0
-#endif
-// <h> Dispatch model 
-
-// <i> This setting configures how Stack events are dispatched to the application.
-//==========================================================
-// <o> NRF_SDH_DISPATCH_MODEL
- 
-
-// <i> NRF_SDH_DISPATCH_MODEL_INTERRUPT: SoftDevice events are passed to the application from the interrupt context.
-// <i> NRF_SDH_DISPATCH_MODEL_APPSH: SoftDevice events are scheduled using @ref app_scheduler.
-// <i> NRF_SDH_DISPATCH_MODEL_POLLING: SoftDevice events are to be fetched manually.
-// <0=> NRF_SDH_DISPATCH_MODEL_INTERRUPT 
-// <1=> NRF_SDH_DISPATCH_MODEL_APPSH 
-// <2=> NRF_SDH_DISPATCH_MODEL_POLLING 
-
-#ifndef NRF_SDH_DISPATCH_MODEL
-#define NRF_SDH_DISPATCH_MODEL 0
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> Clock - SoftDevice clock configuration
-
-//==========================================================
-// <o> NRF_SDH_CLOCK_LF_SRC  - SoftDevice clock source.
- 
-// <0=> NRF_CLOCK_LF_SRC_RC 
-// <1=> NRF_CLOCK_LF_SRC_XTAL 
-// <2=> NRF_CLOCK_LF_SRC_SYNTH 
-
-#ifndef NRF_SDH_CLOCK_LF_SRC
-#define NRF_SDH_CLOCK_LF_SRC 1
-#endif
-
-// <o> NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. 
-#ifndef NRF_SDH_CLOCK_LF_RC_CTIV
-#define NRF_SDH_CLOCK_LF_RC_CTIV 0
-#endif
-
-// <o> NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature. 
-// <i> How often (in number of calibration intervals) the RC oscillator shall be calibrated
-// <i>  if the temperature has not changed.
-
-#ifndef NRF_SDH_CLOCK_LF_RC_TEMP_CTIV
-#define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 0
-#endif
-
-// <o> NRF_SDH_CLOCK_LF_ACCURACY  - External clock accuracy used in the LL to compute timing.
- 
-// <0=> NRF_CLOCK_LF_ACCURACY_250_PPM 
-// <1=> NRF_CLOCK_LF_ACCURACY_500_PPM 
-// <2=> NRF_CLOCK_LF_ACCURACY_150_PPM 
-// <3=> NRF_CLOCK_LF_ACCURACY_100_PPM 
-// <4=> NRF_CLOCK_LF_ACCURACY_75_PPM 
-// <5=> NRF_CLOCK_LF_ACCURACY_50_PPM 
-// <6=> NRF_CLOCK_LF_ACCURACY_30_PPM 
-// <7=> NRF_CLOCK_LF_ACCURACY_20_PPM 
-// <8=> NRF_CLOCK_LF_ACCURACY_10_PPM 
-// <9=> NRF_CLOCK_LF_ACCURACY_5_PPM 
-// <10=> NRF_CLOCK_LF_ACCURACY_2_PPM 
-// <11=> NRF_CLOCK_LF_ACCURACY_1_PPM 
-
-#ifndef NRF_SDH_CLOCK_LF_ACCURACY
-#define NRF_SDH_CLOCK_LF_ACCURACY 7
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> SDH Observers - Observers and priority levels
-
-//==========================================================
-// <o> NRF_SDH_REQ_OBSERVER_PRIO_LEVELS - Total number of priority levels for request observers. 
-// <i> This setting configures the number of priority levels available for the SoftDevice request event handlers.
-// <i> The priority level of a handler determines the order in which it receives events, with respect to other handlers.
-
-#ifndef NRF_SDH_REQ_OBSERVER_PRIO_LEVELS
-#define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS 2
-#endif
-
-// <o> NRF_SDH_STATE_OBSERVER_PRIO_LEVELS - Total number of priority levels for state observers. 
-// <i> This setting configures the number of priority levels available for the SoftDevice state event handlers.
-// <i> The priority level of a handler determines the order in which it receives events, with respect to other handlers.
-
-#ifndef NRF_SDH_STATE_OBSERVER_PRIO_LEVELS
-#define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS 2
-#endif
-
-// <o> NRF_SDH_STACK_OBSERVER_PRIO_LEVELS - Total number of priority levels for stack event observers. 
-// <i> This setting configures the number of priority levels available for the SoftDevice stack event handlers (ANT, BLE, SoC).
-// <i> The priority level of a handler determines the order in which it receives events, with respect to other handlers.
-
-#ifndef NRF_SDH_STACK_OBSERVER_PRIO_LEVELS
-#define NRF_SDH_STACK_OBSERVER_PRIO_LEVELS 2
-#endif
-
-
-// <h> State Observers priorities - Invididual priorities
-
-//==========================================================
-// <o> CLOCK_CONFIG_STATE_OBSERVER_PRIO  
-// <i> Priority with which state events are dispatched to the Clock driver.
-
-#ifndef CLOCK_CONFIG_STATE_OBSERVER_PRIO
-#define CLOCK_CONFIG_STATE_OBSERVER_PRIO 0
-#endif
-
-// <o> POWER_CONFIG_STATE_OBSERVER_PRIO  
-// <i> Priority with which state events are dispatched to the Power driver.
-
-#ifndef POWER_CONFIG_STATE_OBSERVER_PRIO
-#define POWER_CONFIG_STATE_OBSERVER_PRIO 0
-#endif
-
-// <o> RNG_CONFIG_STATE_OBSERVER_PRIO  
-// <i> Priority with which state events are dispatched to this module.
-
-#ifndef RNG_CONFIG_STATE_OBSERVER_PRIO
-#define RNG_CONFIG_STATE_OBSERVER_PRIO 0
-#endif
-
-// </h> 
-//==========================================================
-
-// <h> Stack Event Observers priorities - Invididual priorities
-
-//==========================================================
-// <o> NRF_SDH_ANT_STACK_OBSERVER_PRIO  
-// <i> This setting configures the priority with which ANT events are processed with respect to other events coming from the stack.
-// <i> Modify this setting if you need to have ANT events dispatched before or after other stack events, such as BLE or SoC.
-// <i> Zero is the highest priority.
-
-#ifndef NRF_SDH_ANT_STACK_OBSERVER_PRIO
-#define NRF_SDH_ANT_STACK_OBSERVER_PRIO 0
-#endif
-
-// <o> NRF_SDH_BLE_STACK_OBSERVER_PRIO  
-// <i> This setting configures the priority with which BLE events are processed with respect to other events coming from the stack.
-// <i> Modify this setting if you need to have BLE events dispatched before or after other stack events, such as ANT or SoC.
-// <i> Zero is the highest priority.
-
-#ifndef NRF_SDH_BLE_STACK_OBSERVER_PRIO
-#define NRF_SDH_BLE_STACK_OBSERVER_PRIO 0
-#endif
-
-// <o> NRF_SDH_SOC_STACK_OBSERVER_PRIO  
-// <i> This setting configures the priority with which SoC events are processed with respect to other events coming from the stack.
-// <i> Modify this setting if you need to have SoC events dispatched before or after other stack events, such as ANT or BLE.
-// <i> Zero is the highest priority.
-
-#ifndef NRF_SDH_SOC_STACK_OBSERVER_PRIO
-#define NRF_SDH_SOC_STACK_OBSERVER_PRIO 0
-#endif
-
-// </h> 
-//==========================================================
-
-// </h> 
-//==========================================================
-
-
-// </e>
-
-// <e> NRF_SDH_SOC_ENABLED - nrf_sdh_soc - SoftDevice SoC event handler
-//==========================================================
-#ifndef NRF_SDH_SOC_ENABLED
-#define NRF_SDH_SOC_ENABLED 0
-#endif
-// <h> SoC Observers - Observers and priority levels
-
-//==========================================================
-// <o> NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers. 
-// <i> This setting configures the number of priority levels available for the SoC event handlers.
-// <i> The priority level of a handler determines the order in which it receives events, with respect to other handlers.
-
-#ifndef NRF_SDH_SOC_OBSERVER_PRIO_LEVELS
-#define NRF_SDH_SOC_OBSERVER_PRIO_LEVELS 2
-#endif
-
-// <h> SoC Observers priorities - Invididual priorities
-
-//==========================================================
-// <o> BLE_DFU_SOC_OBSERVER_PRIO  
-// <i> Priority with which BLE events are dispatched to the DFU Service.
-
-#ifndef BLE_DFU_SOC_OBSERVER_PRIO
-#define BLE_DFU_SOC_OBSERVER_PRIO 1
-#endif
-
-// <o> CLOCK_CONFIG_SOC_OBSERVER_PRIO  
-// <i> Priority with which SoC events are dispatched to the Clock driver.
-
-#ifndef CLOCK_CONFIG_SOC_OBSERVER_PRIO
-#define CLOCK_CONFIG_SOC_OBSERVER_PRIO 0
-#endif
-
-// <o> POWER_CONFIG_SOC_OBSERVER_PRIO  
-// <i> Priority with which SoC events are dispatched to the Power driver.
-
-#ifndef POWER_CONFIG_SOC_OBSERVER_PRIO
-#define POWER_CONFIG_SOC_OBSERVER_PRIO 0
-#endif
-
-// </h> 
-//==========================================================
-
-// </h> 
-//==========================================================
-
-// <e> NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
-//==========================================================
-#ifndef NRFX_NVMC_ENABLED
-#define NRFX_NVMC_ENABLED 1
-#endif
-// </e>
-
-//==========================================================
-#ifndef NRFX_SYSTICK_ENABLED
-#define NRFX_SYSTICK_ENABLED 1
-#endif
-// <<< end of configuration section >>>
-#endif //SDK_CONFIG_H
-

bsp/maxim/MAX32660_EVSYS/project.uvprojx

@@ -14,16 +14,16 @@
       <uAC6>0</uAC6>
       <TargetOption>
         <TargetCommonOption>
-          <Device>nRF52840_xxAA</Device>
-          <Vendor>Nordic Semiconductor</Vendor>
-          <PackID>NordicSemiconductor.nRF_DeviceFamilyPack.8.32.1</PackID>
-          <PackURL>http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/</PackURL>
-          <Cpu>IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
+          <Device>MAX32660</Device>
+          <Vendor>Maxim</Vendor>
+          <PackID>Maxim.MAX32660.1.2.0</PackID>
+          <PackURL>http://www.mxim.net/microcontroller/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
           <StartupFile></StartupFile>
-          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm))</FlashDriverDll>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MAX32660 -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM))</FlashDriverDll>
           <DeviceId>0</DeviceId>
-          <RegisterFile>$$Device:nRF52840_xxAA$Device\Include\nrf.h</RegisterFile>
+          <RegisterFile>$$Device:MAX32660$Libraries\Device\Maxim\MAX32660\Include\max32660.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
@@ -33,7 +33,7 @@
           <SLE66CMisc></SLE66CMisc>
           <SLE66AMisc></SLE66AMisc>
           <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:nRF52840_xxAA$SVD\nrf52840.svd</SFDFile>
+          <SFDFile>$$Device:MAX32660$SVD\MAX32660\max32660.svd</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
           <BinPath></BinPath>
@@ -110,11 +110,11 @@
         </CommonProperty>
         <DllOption>
           <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDllArguments> </SimDllArguments>
           <SimDlgDll>DCM.DLL</SimDlgDll>
           <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDllArguments></TargetDllArguments>
           <TargetDlgDll>TCM.DLL</TargetDlgDll>
           <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
         </DllOption>
@@ -188,7 +188,7 @@
             <hadIRAM2>0</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
-            <useUlib>0</useUlib>
+            <useUlib>1</useUlib>
             <EndSel>0</EndSel>
             <uLtcg>0</uLtcg>
             <nSecure>0</nSecure>
@@ -245,12 +245,12 @@
               <IRAM>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x40000</Size>
+                <Size>0x18000</Size>
               </IRAM>
               <IROM>
                 <Type>1</Type>
                 <StartAddress>0x0</StartAddress>
-                <Size>0x100000</Size>
+                <Size>0x40000</Size>
               </IROM>
               <XRAM>
                 <Type>0</Type>
@@ -275,7 +275,7 @@
               <OCR_RVCT4>
                 <Type>1</Type>
                 <StartAddress>0x0</StartAddress>
-                <Size>0x100000</Size>
+                <Size>0x40000</Size>
               </OCR_RVCT4>
               <OCR_RVCT5>
                 <Type>1</Type>
@@ -300,7 +300,7 @@
               <OCR_RVCT9>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x40000</Size>
+                <Size>0x18000</Size>
               </OCR_RVCT9>
               <OCR_RVCT10>
                 <Type>0</Type>
@@ -315,7 +315,7 @@
             <Optim>1</Optim>
             <oTime>0</oTime>
             <SplitLS>0</SplitLS>
-            <OneElfS>1</OneElfS>
+            <OneElfS>0</OneElfS>
             <Strict>0</Strict>
             <EnumInt>0</EnumInt>
             <PlainCh>0</PlainCh>
@@ -336,9 +336,9 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls>--reduce_paths</MiscControls>
-              <Define>NRF52840_XXAA, USE_APP_CONFIG, RT_USING_ARM_LIBC</Define>
+              <Define>USE_APP_CONFIG, RT_USING_ARM_LIBC, __RTTHREAD__</Define>
               <Undefine></Undefine>
-              <IncludePath>.;..\..\..\include;applications;.;board;..\libraries\drivers;packages\nrfx-v2.1.0;packages\nrfx-v2.1.0\drivers;packages\nrfx-v2.1.0\drivers\include;packages\nrfx-v2.1.0\mdk;packages\nrfx-v2.1.0\hal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\cmsis\include</IncludePath>
+              <IncludePath>applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\CMSIS;..\libraries\MAX32660PeriphDriver\Include;..\..\..\components\finsh</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -369,7 +369,7 @@
             <TextAddressRange>0x00000000</TextAddressRange>
             <DataAddressRange>0x20000000</DataAddressRange>
             <pXoBase></pXoBase>
-            <ScatterFile></ScatterFile>
+            <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
             <IncludeLibs></IncludeLibs>
             <IncludeLibsPath></IncludeLibsPath>
             <Misc></Misc>
@@ -379,81 +379,6 @@
         </TargetArmAds>
       </TargetOption>
       <Groups>
-        <Group>
-          <GroupName>Kernel</GroupName>
-          <Files>
-            <File>
-              <FileName>clock.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\clock.c</FilePath>
-            </File>
-            <File>
-              <FileName>components.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\components.c</FilePath>
-            </File>
-            <File>
-              <FileName>device.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\device.c</FilePath>
-            </File>
-            <File>
-              <FileName>idle.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\idle.c</FilePath>
-            </File>
-            <File>
-              <FileName>ipc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\ipc.c</FilePath>
-            </File>
-            <File>
-              <FileName>irq.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\irq.c</FilePath>
-            </File>
-            <File>
-              <FileName>kservice.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\kservice.c</FilePath>
-            </File>
-            <File>
-              <FileName>mem.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\mem.c</FilePath>
-            </File>
-            <File>
-              <FileName>mempool.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\mempool.c</FilePath>
-            </File>
-            <File>
-              <FileName>object.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\object.c</FilePath>
-            </File>
-            <File>
-              <FileName>scheduler.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\scheduler.c</FilePath>
-            </File>
-            <File>
-              <FileName>signal.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\signal.c</FilePath>
-            </File>
-            <File>
-              <FileName>thread.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\thread.c</FilePath>
-            </File>
-            <File>
-              <FileName>timer.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\src\timer.c</FilePath>
-            </File>
-          </Files>
-        </Group>
         <Group>
           <GroupName>Applications</GroupName>
           <Files>
@@ -462,215 +387,110 @@
               <FileType>1</FileType>
               <FilePath>applications\application.c</FilePath>
             </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Drivers</GroupName>
-          <Files>
-            <File>
-              <FileName>board.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>board\board.c</FilePath>
-            </File>
-            <File>
-              <FileName>drv_uart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\drivers\drv_uart.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>nrfx</GroupName>
-          <Files>
-            <File>
-              <FileName>nrfx_adc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_adc.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_clock.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_clock.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_comp.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_comp.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_dppi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_dppi.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_egu.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_egu.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_gpiote.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_gpiote.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_i2s.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_i2s.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_ipc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_ipc.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_lpcomp.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_lpcomp.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_nfct.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_nfct.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_nvmc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_nvmc.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_pdm.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_pdm.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_power.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_power.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_ppi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_ppi.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_pwm.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_pwm.c</FilePath>
-            </File>
-            <File>
-              <FileName>nrfx_qdec.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_qdec.c</FilePath>
-            </File>
             <File>
-              <FileName>nrfx_qspi.c</FileName>
+              <FileName>system_max32660.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_qspi.c</FilePath>
+              <FilePath>..\libraries\CMSIS\system_max32660.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_rng.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_rng.c</FilePath>
+              <FileName>startup_max32660.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\libraries\CMSIS\startup_max32660.s</FilePath>
             </File>
             <File>
-              <FileName>nrfx_rtc.c</FileName>
+              <FileName>mxc_sys.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_rtc.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_sys.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_saadc.c</FileName>
+              <FileName>mxc_assert.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_saadc.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_assert.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_spi.c</FileName>
+              <FileName>mxc_delay.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_spi.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_delay.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_spim.c</FileName>
+              <FileName>mxc_lock.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_spim.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_lock.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_spis.c</FileName>
+              <FileName>mxc_pins.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_spis.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_pins.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_systick.c</FileName>
+              <FileName>nvic_table.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_systick.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\nvic_table.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_temp.c</FileName>
+              <FileName>flc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_temp.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\flc.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_timer.c</FileName>
+              <FileName>icc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_timer.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\icc.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_twi.c</FileName>
+              <FileName>lp.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_twi.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\lp.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_twi_twim.c</FileName>
+              <FileName>gpio.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_twi_twim.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\gpio.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_twim.c</FileName>
+              <FileName>rtc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_twim.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\rtc.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_twis.c</FileName>
+              <FileName>tmr.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_twis.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\tmr.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_uart.c</FileName>
+              <FileName>tmr_utils.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_uart.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\tmr_utils.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_uarte.c</FileName>
+              <FileName>uart.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_uarte.c</FilePath>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\uart.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_usbd.c</FileName>
+              <FileName>drv_uart.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_usbd.c</FilePath>
+              <FilePath>.\applications\drv_uart.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_usbreg.c</FileName>
+              <FileName>shell.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_usbreg.c</FilePath>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
             </File>
             <File>
-              <FileName>nrfx_wdt.c</FileName>
+              <FileName>cmd.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\drivers\src\nrfx_wdt.c</FilePath>
+              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
             </File>
             <File>
-              <FileName>system_nrf52840.c</FileName>
+              <FileName>msh.c</FileName>
               <FileType>1</FileType>
-              <FilePath>packages\nrfx-v2.1.0\mdk\system_nrf52840.c</FilePath>
-            </File>
-            <File>
-              <FileName>arm_startup_nrf52840.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>packages\nrfx-v2.1.0\mdk\arm_startup_nrf52840.s</FilePath>
+              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
             </File>
           </Files>
         </Group>
         <Group>
-          <GroupName>cpu</GroupName>
+          <GroupName>CPU</GroupName>
           <Files>
             <File>
               <FileName>backtrace.c</FileName>
@@ -750,22 +570,82 @@
           </Files>
         </Group>
         <Group>
-          <GroupName>finsh</GroupName>
+          <GroupName>Drivers</GroupName>
           <Files>
             <File>
-              <FileName>shell.c</FileName>
+              <FileName>board.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+              <FilePath>board\board.c</FilePath>
             </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
             <File>
-              <FileName>cmd.c</FileName>
+              <FileName>clock.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
+              <FilePath>..\..\..\src\clock.c</FilePath>
             </File>
             <File>
-              <FileName>msh.c</FileName>
+              <FileName>components.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
+              <FilePath>..\..\..\src\components.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\timer.c</FilePath>
             </File>
           </Files>
         </Group>

bsp/maxim/MAX32660_EVSYS/rtconfig.h

@@ -1,6 +1,32 @@
 #ifndef RT_CONFIG_H__
 #define RT_CONFIG_H__
 
+#define RT_USING_USER_MAIN
+#define RT_TICK_PER_SECOND 1000
+#define BSP_USING_UART1
+#define BSP_USING_UART0
+#define RT_USING_COMPONENTS_INIT
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 256
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_USING_MSH_ONLY
+#define FINSH_ARG_MAX 10
+
+
 /* Automatically generated file; DO NOT EDIT. */
 /* RT-Thread Configuration */
 
@@ -10,7 +36,8 @@
 #define RT_ALIGN_SIZE 4
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 100
+
+
 #define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
 #define RT_USING_IDLE_HOOK
@@ -38,36 +65,16 @@
 /* Kernel Device Object */
 
 #define RT_USING_DEVICE
-#define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 128
-#define RT_CONSOLE_DEVICE_NAME "uart0"
 #define RT_VER_NUM 0x40003
 
 /* RT-Thread Components */
 
-#define RT_USING_COMPONENTS_INIT
-#define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 2048
-#define RT_MAIN_THREAD_PRIORITY 10
 
 /* C++ features */
 
 
 /* Command shell */
 
-#define RT_USING_FINSH
-#define FINSH_THREAD_NAME "tshell"
-#define FINSH_USING_HISTORY
-#define FINSH_HISTORY_LINES 5
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
-#define FINSH_CMD_SIZE 80
-#define FINSH_USING_MSH
-#define FINSH_USING_MSH_DEFAULT
-#define FINSH_USING_MSH_ONLY
-#define FINSH_ARG_MAX 10
 
 /* Device virtual file system */
 
@@ -138,6 +145,9 @@
 /* system packages */
 
 
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
 /* peripheral libraries and drivers */
 
 #define PKG_USING_NRFX
@@ -149,37 +159,15 @@
 /* samples: kernel and components samples */
 
 
-/* Hardware Drivers Config */
+/* games: games run on RT-Thread console */
 
-#define SOC_NRF52840
-#define NRFX_CLOCK_ENABLED 1
-#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#define NRFX_CLOCK_CONFIG_LF_SRC 1
-#define SOC_NORDIC
 
-/* Onboard Peripheral Drivers */
+/* Hardware Drivers Config */
 
-#define BSP_USING_JLINK_TO_USART
+#define SOC_MAXIM
 
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO
-#define NRFX_GPIOTE_ENABLED 1
-#define BSP_USING_UART
-#define NRFX_USING_UART
-#define NRFX_UART_ENABLED 1
-#define BSP_USING_UART0
-#define NRFX_UART0_ENABLED 1
-#define BSP_UART0_RX_PIN 8
-#define BSP_UART0_TX_PIN 6
-
-/* On-chip flash config */
-
-#define MCU_FLASH_START_ADDRESS 0x00000000
-#define MCU_FLASH_SIZE_KB 1024
-#define MCU_SRAM_START_ADDRESS 0x20000000
-#define MCU_SRAM_SIZE_KB 256
-#define MCU_FLASH_PAGE_SIZE 0x1000
-#define BLE_STACK_USING_NULL
 
 #endif

bsp/maxim/MAX32660_EVSYS/template.uvoptx

@@ -77,7 +77,7 @@
         <tvExpOptDlg>0</tvExpOptDlg>
         <IsCurrentTarget>1</IsCurrentTarget>
       </OPTFL>
-      <CpuCode>5</CpuCode>
+      <CpuCode>255</CpuCode>
       <DebugOpt>
         <uSim>0</uSim>
         <uTrg>1</uTrg>
@@ -103,7 +103,7 @@
         <bEvRecOn>1</bEvRecOn>
         <bSchkAxf>0</bSchkAxf>
         <bTchkAxf>0</bTchkAxf>
-        <nTsel>4</nTsel>
+        <nTsel>3</nTsel>
         <sDll></sDll>
         <sDllPa></sDllPa>
         <sDlgDll></sDlgDll>
@@ -114,18 +114,18 @@
         <tDlgDll></tDlgDll>
         <tDlgPa></tDlgPa>
         <tIfile></tIfile>
-        <pMon>Segger\JL2CM3.dll</pMon>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
       </DebugOpt>
       <TargetDriverDllRegistry>
         <SetRegEntry>
           <Number>0</Number>
-          <Key>JL2CM3</Key>
-          <Name>-U683349164 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"CMSIS-DAP" -U04440000e28e0cd70000000000000000 -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0MAX32660.FLM -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM)</Name>
         </SetRegEntry>
         <SetRegEntry>
           <Number>0</Number>
           <Key>UL2CM3</Key>
-          <Name>UL2CM3(-S0 -C0 -P0 )  -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
+          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0MAX32660 -FL040000 -FS00 -FP0($$Device:MAX32660$Flash\MAX32660.FLM)</Name>
         </SetRegEntry>
       </TargetDriverDllRegistry>
       <Breakpoint/>

bsp/maxim/MAX32660_EVSYS/template.uvprojx

@@ -14,16 +14,16 @@
       <uAC6>0</uAC6>
       <TargetOption>
         <TargetCommonOption>
-          <Device>nRF52840_xxAA</Device>
-          <Vendor>Nordic Semiconductor</Vendor>
-          <PackID>NordicSemiconductor.nRF_DeviceFamilyPack.8.32.1</PackID>
-          <PackURL>http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/</PackURL>
-          <Cpu>IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
+          <Device>MAX32660</Device>
+          <Vendor>Maxim</Vendor>
+          <PackID>Maxim.MAX32660.1.2.0</PackID>
+          <PackURL>http://www.mxim.net/microcontroller/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
           <StartupFile></StartupFile>
-          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm))</FlashDriverDll>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MAX32660 -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM))</FlashDriverDll>
           <DeviceId>0</DeviceId>
-          <RegisterFile>$$Device:nRF52840_xxAA$Device\Include\nrf.h</RegisterFile>
+          <RegisterFile>$$Device:MAX32660$Libraries\Device\Maxim\MAX32660\Include\max32660.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
@@ -33,7 +33,7 @@
           <SLE66CMisc></SLE66CMisc>
           <SLE66AMisc></SLE66AMisc>
           <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:nRF52840_xxAA$SVD\nrf52840.svd</SFDFile>
+          <SFDFile>$$Device:MAX32660$SVD\MAX32660\max32660.svd</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
           <BinPath></BinPath>
@@ -110,11 +110,11 @@
         </CommonProperty>
         <DllOption>
           <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDllArguments> </SimDllArguments>
           <SimDlgDll>DCM.DLL</SimDlgDll>
           <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDllArguments></TargetDllArguments>
           <TargetDlgDll>TCM.DLL</TargetDlgDll>
           <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
         </DllOption>
@@ -245,12 +245,12 @@
               <IRAM>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x40000</Size>
+                <Size>0x18000</Size>
               </IRAM>
               <IROM>
                 <Type>1</Type>
                 <StartAddress>0x0</StartAddress>
-                <Size>0x100000</Size>
+                <Size>0x40000</Size>
               </IROM>
               <XRAM>
                 <Type>0</Type>
@@ -275,7 +275,7 @@
               <OCR_RVCT4>
                 <Type>1</Type>
                 <StartAddress>0x0</StartAddress>
-                <Size>0x100000</Size>
+                <Size>0x40000</Size>
               </OCR_RVCT4>
               <OCR_RVCT5>
                 <Type>1</Type>
@@ -300,7 +300,7 @@
               <OCR_RVCT9>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x40000</Size>
+                <Size>0x18000</Size>
               </OCR_RVCT9>
               <OCR_RVCT10>
                 <Type>0</Type>
@@ -315,7 +315,7 @@
             <Optim>1</Optim>
             <oTime>0</oTime>
             <SplitLS>0</SplitLS>
-            <OneElfS>1</OneElfS>
+            <OneElfS>0</OneElfS>
             <Strict>0</Strict>
             <EnumInt>0</EnumInt>
             <PlainCh>0</PlainCh>
@@ -336,7 +336,7 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls>--reduce_paths</MiscControls>
-              <Define>BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S140 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74</Define>
+              <Define></Define>
               <Undefine></Undefine>
               <IncludePath></IncludePath>
             </VariousControls>
@@ -372,7 +372,7 @@
             <ScatterFile></ScatterFile>
             <IncludeLibs></IncludeLibs>
             <IncludeLibsPath></IncludeLibsPath>
-            <Misc>--diag_suppress 6330</Misc>
+            <Misc></Misc>
             <LinkerInputFile></LinkerInputFile>
             <DisabledWarnings></DisabledWarnings>
           </LDads>

bsp/maxim/libraries/CMSIS/RTE_Components.h

@@ -0,0 +1,24 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'Hello_World' 
+ * Target:  'Debug' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "max32660.h"
+
+#define BOARD EvKit_V1 /* Target Board */
+#define RTE_USING_FINSH
+#define TARGET 32660   /* Target Device Part Number */
+               #define TARGET_REV 0x4131 /* Target Device Revision Number */
+
+#endif /* RTE_COMPONENTS_H */

bsp/maxim/libraries/CMSIS/cmsis_armcc.h

@@ -0,0 +1,885 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.2.1
+ * @date     26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+  /* __ARM_ARCH_8_1M_MAIN__  not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __ARM_FEATURE_DSP         1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __memory_changed()
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

bsp/maxim/libraries/CMSIS/cmsis_armclang.h

@@ -0,0 +1,1467 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.3.1
+ * @date     26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF)
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+          (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+          (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+          (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
+           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
+           
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
+           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define     __SADD8                 __builtin_arm_sadd8
+#define     __QADD8                 __builtin_arm_qadd8
+#define     __SHADD8                __builtin_arm_shadd8
+#define     __UADD8                 __builtin_arm_uadd8
+#define     __UQADD8                __builtin_arm_uqadd8
+#define     __UHADD8                __builtin_arm_uhadd8
+#define     __SSUB8                 __builtin_arm_ssub8
+#define     __QSUB8                 __builtin_arm_qsub8
+#define     __SHSUB8                __builtin_arm_shsub8
+#define     __USUB8                 __builtin_arm_usub8
+#define     __UQSUB8                __builtin_arm_uqsub8
+#define     __UHSUB8                __builtin_arm_uhsub8
+#define     __SADD16                __builtin_arm_sadd16
+#define     __QADD16                __builtin_arm_qadd16
+#define     __SHADD16               __builtin_arm_shadd16
+#define     __UADD16                __builtin_arm_uadd16
+#define     __UQADD16               __builtin_arm_uqadd16
+#define     __UHADD16               __builtin_arm_uhadd16
+#define     __SSUB16                __builtin_arm_ssub16
+#define     __QSUB16                __builtin_arm_qsub16
+#define     __SHSUB16               __builtin_arm_shsub16
+#define     __USUB16                __builtin_arm_usub16
+#define     __UQSUB16               __builtin_arm_uqsub16
+#define     __UHSUB16               __builtin_arm_uhsub16
+#define     __SASX                  __builtin_arm_sasx
+#define     __QASX                  __builtin_arm_qasx
+#define     __SHASX                 __builtin_arm_shasx
+#define     __UASX                  __builtin_arm_uasx
+#define     __UQASX                 __builtin_arm_uqasx
+#define     __UHASX                 __builtin_arm_uhasx
+#define     __SSAX                  __builtin_arm_ssax
+#define     __QSAX                  __builtin_arm_qsax
+#define     __SHSAX                 __builtin_arm_shsax
+#define     __USAX                  __builtin_arm_usax
+#define     __UQSAX                 __builtin_arm_uqsax
+#define     __UHSAX                 __builtin_arm_uhsax
+#define     __USAD8                 __builtin_arm_usad8
+#define     __USADA8                __builtin_arm_usada8
+#define     __SSAT16                __builtin_arm_ssat16
+#define     __USAT16                __builtin_arm_usat16
+#define     __UXTB16                __builtin_arm_uxtb16
+#define     __UXTAB16               __builtin_arm_uxtab16
+#define     __SXTB16                __builtin_arm_sxtb16
+#define     __SXTAB16               __builtin_arm_sxtab16
+#define     __SMUAD                 __builtin_arm_smuad
+#define     __SMUADX                __builtin_arm_smuadx
+#define     __SMLAD                 __builtin_arm_smlad
+#define     __SMLADX                __builtin_arm_smladx
+#define     __SMLALD                __builtin_arm_smlald
+#define     __SMLALDX               __builtin_arm_smlaldx
+#define     __SMUSD                 __builtin_arm_smusd
+#define     __SMUSDX                __builtin_arm_smusdx
+#define     __SMLSD                 __builtin_arm_smlsd
+#define     __SMLSDX                __builtin_arm_smlsdx
+#define     __SMLSLD                __builtin_arm_smlsld
+#define     __SMLSLDX               __builtin_arm_smlsldx
+#define     __SEL                   __builtin_arm_sel
+#define     __QADD                  __builtin_arm_qadd
+#define     __QSUB                  __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */

bsp/maxim/libraries/CMSIS/cmsis_armclang_ltm.h

@@ -0,0 +1,1893 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang_ltm.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V1.3.0
+ * @date     26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF)
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */

bsp/maxim/libraries/CMSIS/cmsis_compiler.h

@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/maxim/libraries/CMSIS/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.4
+ * @date     23. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/maxim/libraries/CMSIS/core_cm4.h

@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.1.1
+ * @date     27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT             1U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+  
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[32U];
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/maxim/libraries/CMSIS/max32660.h

@@ -0,0 +1,403 @@
+/**
+ * @file    max32660.h
+ * @brief   Device-specific perhiperal header file
+ */
+
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+#ifndef _MAX32660_REGS_H_
+#define _MAX32660_REGS_H_
+
+#ifndef TARGET_NUM
+#define TARGET_NUM  32660
+#endif
+
+#include <stdint.h>
+
+#ifndef  FALSE
+#define  FALSE      (0)
+#endif
+
+#ifndef  TRUE
+#define  TRUE       (1)
+#endif
+
+#if !defined (__GNUC__)
+#define CMSIS_VECTAB_VIRTUAL
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
+#endif /* !__GNUC__ */
+
+/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
+#if defined ( __GNUC__ ) /* GCC */
+#define __weak __attribute__((weak))
+
+#elif defined ( __CC_ARM) /* Keil */
+
+#define inline __inline
+#pragma anon_unions
+
+#endif
+
+typedef enum {
+    NonMaskableInt_IRQn    = -14,
+    HardFault_IRQn         = -13,
+    MemoryManagement_IRQn  = -12,
+    BusFault_IRQn          = -11,
+    UsageFault_IRQn        = -10,
+    SVCall_IRQn            = -5,
+    DebugMonitor_IRQn      = -4,
+    PendSV_IRQn            = -2,
+    SysTick_IRQn           = -1,
+
+    /* Device-specific interrupt sources (external to ARM core)                 */
+    /*                      table entry number                                  */
+    /*                      ||||                                                */
+    /*                      ||||  table offset address                          */
+    /*                      vvvv  vvvvvv                                        */
+
+    PF_IRQn = 0,         /* 0x10  0x0040  16: Power Fail */
+    WDT0_IRQn,           /* 0x11  0x0044  17: Watchdog 0 */
+    RSV00_IRQn,          /* 0x12  0x0048  18: RSV00 */
+    RTC_IRQn,            /* 0x13  0x004C  19: RTC */
+    RSV1_IRQn,           /* 0x14  0x0050  20: RSV1 */
+    TMR0_IRQn,           /* 0x15  0x0054  21: Timer 0 */
+    TMR1_IRQn,           /* 0x16  0x0058  22: Timer 1 */
+    TMR2_IRQn,           /* 0x17  0x005C  23: Timer 2 */
+    RSV02_IRQn,          /* 0x18  0x0060  24: RSV02 */
+    RSV03_IRQn,          /* 0x19  0x0064  25: RSV03 */
+    RSV04_IRQn,          /* 0x1A  0x0068  26: RSV04 */
+    RSV05_IRQn,          /* 0x1B  0x006C  27: RSV05 */
+    RSV06_IRQn,          /* 0x1C  0x0070  28: RSV06 */
+    I2C0_IRQn,           /* 0x1D  0x0074  29: I2C0 */
+    UART0_IRQn,          /* 0x1E  0x0078  30: UART 0 */
+    UART1_IRQn,          /* 0x1F  0x007C  31: UART 1 */
+    SPI17Y_IRQn,         /* 0x20  0x0080  32: SPI17Y */
+    SPIMSS_IRQn,         /* 0x21  0x0084  33: SPIMSS */
+    RSV07_IRQn,          /* 0x22  0x0088  34: RSV07 */
+    RSV08_IRQn,          /* 0x23  0x008C  35: RSV08 */
+    RSV09_IRQn,          /* 0x24  0x0090  36: RSV09 */
+    RSV10_IRQn,          /* 0x25  0x0094  37: RSV10 */
+    RSV11_IRQn,          /* 0x26  0x0098  38: RSV11 */
+    FLC_IRQn,            /* 0x27  0x009C  39: FLC */
+    GPIO0_IRQn,          /* 0x28  0x00A0  40: GPIO0 */
+    RSV12_IRQn,          /* 0x29  0x00A4  41: RSV12 */
+    RSV13_IRQn,          /* 0x2A  0x00A8  42: RSV13 */
+    RSV14_IRQn,          /* 0x2B  0x00AC  43: RSV14 */
+    DMA0_IRQn,           /* 0x2C  0x00B0  44: DMA0 */
+    DMA1_IRQn,           /* 0x2D  0x00B4  45: DMA1 */
+    DMA2_IRQn,           /* 0x2E  0x00B8  46: DMA2 */
+    DMA3_IRQn,           /* 0x2F  0x00BC  47: DMA3 */
+    RSV15_IRQn,          /* 0x30  0x00C0  48: RSV15 */
+    RSV16_IRQn,          /* 0x31  0x00C4  49: RSV16 */
+    RSV17_IRQn,          /* 0x32  0x00C8  50: RSV17 */
+    RSV18_IRQn,          /* 0x33  0x00CC  51: RSV18 */
+    I2C1_IRQn,           /* 0x34  0x00D0  52: I2C1 */
+    RSV19_IRQn,          /* 0x35  0x00D4  53: RSV19 */
+    RSV20_IRQn,          /* 0x36  0x00D8  54: RSV20 */
+    RSV21_IRQn,          /* 0x37  0x00DC  55: RSV21 */
+    RSV22_IRQn,          /* 0x38  0x00E0  56: RSV22 */
+    RSV23_IRQn,          /* 0x39  0x00E4  57: RSV23 */
+    RSV24_IRQn,          /* 0x3A  0x00E8  58: RSV24 */
+    RSV25_IRQn,          /* 0x3B  0x00EC  59: RSV25 */
+    RSV26_IRQn,          /* 0x3C  0x00F0  60: RSV26 */
+    RSV27_IRQn,          /* 0x3D  0x00F4  61: RSV27 */
+    RSV28_IRQn,          /* 0x3E  0x00F8  62: RSV28 */
+    RSV29_IRQn,          /* 0x3F  0x00FC  63: RSV29 */
+    RSV30_IRQn,          /* 0x40  0x0100  64: RSV30 */
+    RSV31_IRQn,          /* 0x41  0x0104  65: RSV31 */
+    RSV32_IRQn,          /* 0x42  0x0108  66: RSV32 */
+    RSV33_IRQn,          /* 0x43  0x010C  67: RSV33 */
+    RSV34_IRQn,          /* 0x44  0x0110  68: RSV34 */
+    RSV35_IRQn,          /* 0x45  0x0114  69: RSV35 */
+    GPIOWAKE_IRQn,       /* 0x46  0x0118  70: GPIO Wakeup */
+    MXC_IRQ_EXT_COUNT,
+} IRQn_Type;
+
+#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* ----------------------  Configuration of the Cortex-M Processor and Core Peripherals  ---------------------- */
+#define __CM4_REV                       0x0100          /*!< Cortex-M4 Core Revision                                */
+#define __MPU_PRESENT                   1               /*!< MPU present or not                                     */
+#define __NVIC_PRIO_BITS                3               /*!< Number of Bits used for Priority Levels                */
+#define __Vendor_SysTickConfig          0               /*!< Set to 1 if different SysTick Config is used           */
+#define __FPU_PRESENT                   1               /*!< FPU present or not                                     */
+
+#include <core_cm4.h>                                   /*!< Cortex-M4 processor and core peripherals               */
+#include "system_max32660.h"                            /*!< System Header                                          */
+
+
+/* ================================================================================ */
+/* ==================       Device Specific Memory Section       ================== */
+/* ================================================================================ */
+
+#define MXC_FLASH_MEM_BASE              0x00000000UL
+#define MXC_FLASH_PAGE_SIZE             0x00002000UL
+#define MXC_FLASH_MEM_SIZE              0x00040000UL
+#define MXC_INFO_MEM_BASE               0x00040000UL
+#define MXC_INFO_MEM_SIZE               0x00001000UL
+#define MXC_SRAM_MEM_BASE               0x20000000UL
+#define MXC_SRAM_MEM_SIZE               0x00018000UL
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+/*
+   Base addresses and configuration settings for all MAX32660 peripheral modules.
+*/
+
+/******************************************************************************/
+/*                                                             Global control */
+#define MXC_BASE_GCR                    ((uint32_t)0x40000000UL)
+#define MXC_GCR                         ((mxc_gcr_regs_t*)MXC_BASE_GCR)
+
+/******************************************************************************/
+/*                                            Non-battery backed SI Registers */
+#define MXC_BASE_SIR                    ((uint32_t)0x40000400UL)
+#define MXC_SIR                         ((mxc_sir_regs_t*)MXC_BASE_SIR)
+
+/******************************************************************************/
+/*                                                                   Watchdog */
+#define MXC_BASE_WDT0                   ((uint32_t)0x40003000UL)
+#define MXC_WDT0                        ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
+
+/******************************************************************************/
+/*                                                            Real Time Clock */
+#define MXC_BASE_RTC                    ((uint32_t)0x40006000UL)
+#define MXC_RTC                         ((mxc_rtc_regs_t*)MXC_BASE_RTC)
+
+/******************************************************************************/
+/*                                                            Power Sequencer */
+#define MXC_BASE_PWRSEQ                 ((uint32_t)0x40006800UL)
+#define MXC_PWRSEQ                      ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
+
+
+/******************************************************************************/
+/*                                                                       GPIO */
+#define MXC_CFG_GPIO_INSTANCES          (1)
+#define MXC_CFG_GPIO_PINS_PORT          (14)
+
+#define MXC_BASE_GPIO0                  ((uint32_t)0x40008000UL)
+#define MXC_GPIO0                       ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
+
+#define MXC_GPIO_GET_IDX(p)             ((p) == MXC_GPIO0 ? 0 :-1)
+
+#define MXC_GPIO_GET_GPIO(i)            ((i) == 0 ? MXC_GPIO0 : 0)
+
+#define MXC_GPIO_GET_IRQ(i)             ((i) == 0 ? GPIO0_IRQn : 0)
+
+/******************************************************************************/
+/*                                                                      Timer */
+#define MXC_CFG_TMR_INSTANCES           (3)
+
+#define MXC_BASE_TMR0                   ((uint32_t)0x40010000UL)
+#define MXC_TMR0                        ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
+#define MXC_BASE_TMR1                   ((uint32_t)0x40011000UL)
+#define MXC_TMR1                        ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
+#define MXC_BASE_TMR2                   ((uint32_t)0x40012000UL)
+#define MXC_TMR2                        ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
+
+#define MXC_TMR_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? TMR0_IRQn :     \
+                                            (i) == 1 ? TMR1_IRQn :             \
+                                            (i) == 2 ? TMR2_IRQn : 0)
+
+#define MXC_TMR_GET_BASE(i)             ((i) == 0 ? MXC_BASE_TMR0 :            \
+                                            (i) == 1 ? MXC_BASE_TMR1 :         \
+                                            (i) == 2 ? MXC_BASE_TMR2 : 0)
+
+#define MXC_TMR_GET_TMR(i)              ((i) == 0 ? MXC_TMR0 :                 \
+                                            (i) == 1 ? MXC_TMR1 :              \
+                                            (i) == 2 ? MXC_TMR2 : 0)
+
+#define MXC_TMR_GET_IDX(p)              ((p) == MXC_TMR0 ? 0 :                 \
+                                            (p) == MXC_TMR1 ? 1 :              \
+                                            (p) == MXC_TMR2 ? 2 : -1)
+
+/******************************************************************************/
+/*                                                                    SPIMSS  */
+
+#define MXC_SPIMSS_INSTANCES            (1)
+#define MXC_SPIMSS_FIFO_DEPTH           (8)
+
+#define MXC_BASE_SPIMSS                ((uint32_t)0x40019000UL)
+#define MXC_SPIMSS                     ((mxc_spimss_regs_t*)MXC_BASE_SPIMSS)
+
+#define MXC_SPIMSS_GET_IDX(p)            ((p) == MXC_SPIMSS ? 0 :  -1)
+#define MXC_SPIMSS_GET_SPI(i)            ((i) == 0 ? MXC_SPIMSS :   0)
+
+/******************************************************************************/
+/*                                                                        I2C */
+#define MXC_I2C_INSTANCES               (2)
+#define MXC_I2C_FIFO_DEPTH              (8)
+
+#define MXC_BASE_I2C0                   ((uint32_t)0x4001D000UL)
+#define MXC_I2C0                        ((mxc_i2c_regs_t*)MXC_BASE_I2C0)
+#define MXC_BASE_I2C1                   ((uint32_t)0x4001E000UL)
+#define MXC_I2C1                        ((mxc_i2c_regs_t*)MXC_BASE_I2C1)
+
+#define MXC_I2C_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? I2C0_IRQn :     \
+                                            (i) == 1 ? I2C1_IRQn : 0)
+
+#define MXC_I2C_GET_BASE(i)             ((i) == 0 ? MXC_BASE_I2C0 :            \
+                                            (i) == 1 ? MXC_BASE_I2C1 : 0)
+
+#define MXC_I2C_GET_I2C(i)              ((i) == 0 ? MXC_I2C0 :                 \
+                                            (i) == 1 ? MXC_I2C1 : 0)
+
+#define MXC_I2C_GET_IDX(p)              ((p) == MXC_I2C0 ? 0 :                 \
+                                            (p) == MXC_I2C1 ? 1 : -1)
+
+/******************************************************************************/
+/*                                                                        DMA */
+#define MXC_DMA_CHANNELS                (4)
+
+#define MXC_BASE_DMA                    ((uint32_t)0x40028000UL)
+#define MXC_DMA                         ((mxc_dma_regs_t*)MXC_BASE_DMA)
+
+/******************************************************************************/
+/*                                                                        FLC */
+#define MXC_BASE_FLC                    ((uint32_t)0x40029000UL)
+#define MXC_FLC                         ((mxc_flc_regs_t*)MXC_BASE_FLC)
+
+/******************************************************************************/
+/*                                                          Instruction Cache */
+#define MXC_BASE_ICC                    ((uint32_t)0x4002A000UL)
+#define MXC_ICC                         ((mxc_icc_regs_t*)MXC_BASE_ICC)
+
+/******************************************************************************/
+/*                                               UART / Serial Port Interface */
+
+#define MXC_UART_INSTANCES              (2)
+#define MXC_UART_FIFO_DEPTH             (8)
+
+#define MXC_BASE_UART0                  ((uint32_t)0x40042000UL)
+#define MXC_UART0                       ((mxc_uart_regs_t*)MXC_BASE_UART0)
+#define MXC_BASE_UART1                  ((uint32_t)0x40043000UL)
+#define MXC_UART1                       ((mxc_uart_regs_t*)MXC_BASE_UART1)
+
+#define MXC_UART_GET_IRQ(i)             (IRQn_Type)((i) == 0 ? UART0_IRQn :    \
+                                            (i) == 1 ? UART1_IRQn : 0)
+
+#define MXC_UART_GET_BASE(i)            ((i) == 0 ? MXC_BASE_UART0 :           \
+                                            (i) == 1 ? MXC_BASE_UART1 : 0)
+
+#define MXC_UART_GET_UART(i)            ((i) == 0 ? MXC_UART0 :                \
+                                            (i) == 1 ? MXC_UART1 : 0)
+
+#define MXC_UART_GET_IDX(p)             ((p) == MXC_UART0 ? 0 :                \
+                                            (p) == MXC_UART1 ? 1 : -1)
+
+/******************************************************************************/
+/*                                                                        SPI */
+
+
+#define MXC_SPI17Y_INSTANCES               (4)
+#define MXC_SPI17Y_SS_INSTANCES            (1)
+#define MXC_SPI17Y_FIFO_DEPTH              (32)
+
+#define MXC_BASE_SPI17Y                   ((uint32_t)0x40046000UL)
+#define MXC_SPI17Y                        ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y)
+
+#define MXC_SPI17Y_GET_IDX(p)               ((p) == MXC_SPI17Y ? 0 :  -1)
+
+#define MXC_SPI17Y_GET_BASE(i)             ((i) == 0 ? MXC_BASE_SPI17Y :  0)
+
+#define MXC_SPI17Y_GET_SPI17Y(i)             ((i) == 0 ? MXC_SPI17Y :   0)
+
+/******************************************************************************/
+/*                                                               Bit Shifting */
+
+#define MXC_F_BIT_0                     (1 << 0)
+#define MXC_F_BIT_1                     (1 << 1)
+#define MXC_F_BIT_2                     (1 << 2)
+#define MXC_F_BIT_3                     (1 << 3)
+#define MXC_F_BIT_4                     (1 << 4)
+#define MXC_F_BIT_5                     (1 << 5)
+#define MXC_F_BIT_6                     (1 << 6)
+#define MXC_F_BIT_7                     (1 << 7)
+#define MXC_F_BIT_8                     (1 << 8)
+#define MXC_F_BIT_9                     (1 << 9)
+#define MXC_F_BIT_10                    (1 << 10)
+#define MXC_F_BIT_11                    (1 << 11)
+#define MXC_F_BIT_12                    (1 << 12)
+#define MXC_F_BIT_13                    (1 << 13)
+#define MXC_F_BIT_14                    (1 << 14)
+#define MXC_F_BIT_15                    (1 << 15)
+#define MXC_F_BIT_16                    (1 << 16)
+#define MXC_F_BIT_17                    (1 << 17)
+#define MXC_F_BIT_18                    (1 << 18)
+#define MXC_F_BIT_19                    (1 << 19)
+#define MXC_F_BIT_20                    (1 << 20)
+#define MXC_F_BIT_21                    (1 << 21)
+#define MXC_F_BIT_22                    (1 << 22)
+#define MXC_F_BIT_23                    (1 << 23)
+#define MXC_F_BIT_24                    (1 << 24)
+#define MXC_F_BIT_25                    (1 << 25)
+#define MXC_F_BIT_26                    (1 << 26)
+#define MXC_F_BIT_27                    (1 << 27)
+#define MXC_F_BIT_28                    (1 << 28)
+#define MXC_F_BIT_29                    (1 << 29)
+#define MXC_F_BIT_30                    (1 << 30)
+#define MXC_F_BIT_31                    (1 << 31)
+
+/******************************************************************************/
+/*                                                               Bit Banding  */
+
+#define BITBAND(reg, bit)               ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
+                                            (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
+
+#define MXC_CLRBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
+#define MXC_SETBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
+#define MXC_GETBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit))
+
+#define MXC_SETFIELD(reg, mask, value)  (reg = (reg & ~mask) | (value & mask))
+
+/******************************************************************************/
+/*                                                                  SCB CPACR */
+
+/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
+#define SCB_CPACR_CP10_Pos              20                              /*!< SCB CPACR: Coprocessor 10 Position */
+#define SCB_CPACR_CP10_Msk              (0x3UL << SCB_CPACR_CP10_Pos)   /*!< SCB CPACR: Coprocessor 10 Mask */
+#define SCB_CPACR_CP11_Pos              22                              /*!< SCB CPACR: Coprocessor 11 Position */
+#define SCB_CPACR_CP11_Msk              (0x3UL << SCB_CPACR_CP11_Pos)   /*!< SCB CPACR: Coprocessor 11 Mask */
+
+#endif  /* _MAX32660_REGS_H_ */

bsp/maxim/libraries/CMSIS/mpu_armv7.h

@@ -0,0 +1,275 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.1.1
+ * @date     10. February 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

bsp/maxim/libraries/CMSIS/mxc_config.h

@@ -0,0 +1,53 @@
+/**
+ * @file       mxc_config.h
+ * @brief      Top-level include file for device configuration.
+ */
+ 
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
+ * $Revision: 36818 $
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_CONFIG_H
+#define _MXC_CONFIG_H
+
+#if !defined __GNUC__
+#include "RTE_Components.h"
+#endif /* not __GNUC__ */
+
+#include "mxc_device.h"
+#include "mxc_errors.h"
+#include "mxc_pins.h"
+
+#endif /* _CONFIG_H */

bsp/maxim/libraries/CMSIS/startup_max32660.s

@@ -0,0 +1,373 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ ;
+ ; Permission is hereby granted, free of charge, to any person obtaining a
+ ; copy of this software and associated documentation files (the "Software"),
+ ; to deal in the Software without restriction, including without limitation
+ ; the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ ; and/or sell copies of the Software, and to permit persons to whom the
+ ; Software is furnished to do so, subject to the following conditions:
+ ;
+ ; The above copyright notice and this permission notice shall be included
+ ; in all copies or substantial portions of the Software.
+ ;
+ ; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ ; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ ; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ ; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ ; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ ; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ ; OTHER DEALINGS IN THE SOFTWARE.
+ ;
+ ; Except as contained in this notice, the name of Maxim Integrated
+ ; Products, Inc. shall not be used except as stated in the Maxim Integrated
+ ; Products, Inc. Branding Policy.
+ ;
+ ; The mere transfer of this software does not imply any licenses
+ ; of trade secrets, proprietary technology, copyrights, patents,
+ ; trademarks, maskwork rights, or any other form of intellectual
+ ; property whatsoever. Maxim Integrated Products, Inc. retains all
+ ; ownership rights.
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; To map FreeRTOS function names to their CMSIS equivalents add following lines to FreeRTOSConfig.h
+; #define vPortSVCHandler SVC_Handler
+; #define xPortPendSVHandler PendSV_Handler
+; #define xPortSysTickHandler SysTick_Handler
+; *------- <<< Use Configuration Wizard in Context Menu to Modify Stack Size and Heap Size. >>> ----
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00001000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    ; Name used with Keil Configuration Wizard and Keil MicroLib
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+                EXPORT  __isr_vector
+                IMPORT  SysTick_Handler
+
+__isr_vector    DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; Device-specific Interrupts
+                DCD     PF_IRQHandler             ; 0x10  0x0040  16: Power Fail
+                DCD     WDT0_IRQHandler           ; 0x11  0x0044  17: Watchdog 0
+                DCD     RSV00_IRQHandler          ; 0x12  0x0048  18: RSV00
+                DCD     RTC_IRQHandler            ; 0x13  0x004C  19: RTC
+                DCD     RSV01_IRQHandler          ; 0x14  0x0050  20: RSV1
+                DCD     TMR0_IRQHandler           ; 0x15  0x0054  21: Timer 0
+                DCD     TMR1_IRQHandler           ; 0x16  0x0058  22: Timer 1
+                DCD     TMR2_IRQHandler           ; 0x17  0x005C  23: Timer 2
+                DCD     RSV02_IRQHandler          ; 0x18  0x0060  24: RSV02
+                DCD     RSV03_IRQHandler          ; 0x19  0x0064  25: RSV03
+                DCD     RSV04_IRQHandler          ; 0x1A  0x0068  26: RSV04
+                DCD     RSV05_IRQHandler          ; 0x1B  0x006C  27: RSV05
+                DCD     RSV06_IRQHandler          ; 0x1C  0x0070  28: RSV06
+                DCD     I2C0_IRQHandler           ; 0x1D  0x0074  29: I2C0
+                DCD     UART0_IRQHandler          ; 0x1E  0x0078  30: UART 0
+                DCD     UART1_IRQHandler          ; 0x1F  0x007C  31: UART 1
+                DCD     SPI0_IRQHandler           ; 0x20  0x0080  32: SPIY17
+                DCD     SPI1_IRQHandler           ; 0x21  0x0084  33: SPIMSS
+                DCD     RSV07_IRQHandler          ; 0x22  0x0088  34: RSV07
+                DCD     RSV08_IRQHandler          ; 0x23  0x008C  35: RSV08
+                DCD     RSV09_IRQHandler          ; 0x24  0x0090  36: RSV09
+                DCD     RSV10_IRQHandler          ; 0x25  0x0094  37: RSV10
+                DCD     RSV11_IRQHandler          ; 0x26  0x0098  38: RSV11
+                DCD     FLC_IRQHandler            ; 0x27  0x009C  39: FLC
+                DCD     GPIO0_IRQHandler          ; 0x28  0x00A0  40: GPIO0
+                DCD     RSV12_IRQHandler          ; 0x29  0x00A4  41: RSV12
+                DCD     RSV13_IRQHandler          ; 0x2A  0x00A8  42: RSV13
+                DCD     RSV14_IRQHandler          ; 0x2B  0x00AC  43: RSV14
+                DCD     DMA0_IRQHandler           ; 0x2C  0x00B0  44: DMA0
+                DCD     DMA1_IRQHandler           ; 0x2D  0x00B4  45: DMA1
+                DCD     DMA2_IRQHandler           ; 0x2E  0x00B8  46: DMA2
+                DCD     DMA3_IRQHandler           ; 0x2F  0x00BC  47: DMA3
+                DCD     RSV15_IRQHandler          ; 0x30  0x00C0  48: RSV15
+                DCD     RSV16_IRQHandler          ; 0x31  0x00C4  49: RSV16
+                DCD     RSV17_IRQHandler          ; 0x32  0x00C8  50: RSV17
+                DCD     RSV18_IRQHandler          ; 0x33  0x00CC  51: RSV18
+                DCD     I2C1_IRQHandler           ; 0x34  0x00D0  52: I2C1
+                DCD     RSV19_IRQHandler          ; 0x35  0x00D4  53: RSV19
+                DCD     RSV20_IRQHandler          ; 0x36  0x00D8  54: RSV20
+                DCD     RSV21_IRQHandler          ; 0x37  0x00DC  55: RSV21
+                DCD     RSV22_IRQHandler          ; 0x38  0x00E0  56: RSV22
+                DCD     RSV23_IRQHandler          ; 0x39  0x00E4  57: RSV23
+                DCD     RSV24_IRQHandler          ; 0x3A  0x00E8  58: RSV24
+                DCD     RSV25_IRQHandler          ; 0x3B  0x00EC  59: RSV25
+                DCD     RSV26_IRQHandler          ; 0x3C  0x00F0  60: RSV26
+                DCD     RSV27_IRQHandler          ; 0x3D  0x00F4  61: RSV27
+                DCD     RSV28_IRQHandler          ; 0x3E  0x00F8  62: RSV28
+                DCD     RSV29_IRQHandler          ; 0x3F  0x00FC  63: RSV29
+                DCD     RSV30_IRQHandler          ; 0x40  0x0100  64: RSV30
+                DCD     RSV31_IRQHandler          ; 0x41  0x0104  65: RSV31
+                DCD     RSV32_IRQHandler          ; 0x42  0x0108  66: RSV32
+                DCD     RSV33_IRQHandler          ; 0x43  0x010C  67: RSV33
+                DCD     RSV34_IRQHandler          ; 0x44  0x0110  68: RSV34
+                DCD     RSV35_IRQHandler          ; 0x45  0x0114  69: RSV35
+                DCD     GPIOWAKE_IRQHandler       ; 0x46  0x0118  70: GPIO Wakeup
+__isr_vector_end
+
+__isr_vector_size       EQU  __isr_vector_end - __isr_vector
+__Vectors       EQU     __isr_vector
+__Vectors_End   EQU     __isr_vector_end
+__Vectors_Size  EQU     __isr_vector_size
+
+                AREA    |.text|, CODE, READONLY
+
+Reset_Handler   PROC
+                EXPORT Reset_Handler                    [WEAK]
+                IMPORT PreInit
+                ;IMPORT SystemInit
+                IMPORT __main
+                LDR     R0, =PreInit            ; Call to PreInit (prior to RAM initialization)
+                BLX     R0
+                LDR     R0, =__main             ; SystemInit() is called from post scatter memory initialization in function  $Sub$$__main_after_scatterload - system_max32660.c
+                BX      R0
+__SPIN
+                WFI
+                BL __SPIN
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler             [WEAK]
+                B       .
+                ENDP
+
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler       [WEAK]
+                B       .
+                ENDP
+
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler       [WEAK]
+                B       .
+                ENDP
+
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler        [WEAK]
+                B       .
+                ENDP
+
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler      [WEAK]
+                B       .
+                ENDP
+
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler             [WEAK]
+                B       .
+                ENDP
+
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler        [WEAK]
+                B       .
+                ENDP
+
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler          [WEAK]
+                B       .
+                ENDP
+Default_Handler\
+                PROC
+                ; MAX32660 Device-specific Interrupts
+                EXPORT PF_IRQHandler            [WEAK] ;  0x10  0x0040  16: Power Fail
+                EXPORT WDT0_IRQHandler          [WEAK] ;  0x11  0x0044  17: Watchdog 0
+                EXPORT RSV00_IRQHandler         [WEAK] ;  0x12  0x0048  18: RSV00
+                EXPORT RTC_IRQHandler           [WEAK] ;  0x13  0x004C  19: RTC
+                EXPORT RSV01_IRQHandler         [WEAK] ;  0x14  0x0050  20: RSV01
+                EXPORT TMR0_IRQHandler          [WEAK] ;  0x15  0x0054  21: Timer 0
+                EXPORT TMR1_IRQHandler          [WEAK] ;  0x16  0x0058  22: Timer 1
+                EXPORT TMR2_IRQHandler          [WEAK] ;  0x17  0x005C  23: Timer 2
+                EXPORT RSV02_IRQHandler         [WEAK] ;  0x18  0x0060  24: RSV02
+                EXPORT RSV03_IRQHandler         [WEAK] ;  0x19  0x0064  25: RSV03
+                EXPORT RSV04_IRQHandler         [WEAK] ;  0x1A  0x0068  26: RSV04
+                EXPORT RSV05_IRQHandler         [WEAK] ;  0x1B  0x006C  27: RSV05
+                EXPORT RSV06_IRQHandler         [WEAK] ;  0x1C  0x0070  28: RSV06
+                EXPORT I2C0_IRQHandler          [WEAK] ;  0x1D  0x0074  29: I2C0
+                EXPORT UART0_IRQHandler         [WEAK] ;  0x1E  0x0078  30: UART 0
+                EXPORT UART1_IRQHandler         [WEAK] ;  0x1F  0x007C  31: UART 1
+                EXPORT SPI0_IRQHandler          [WEAK] ;  0x20  0x0080  32: SPIY17
+                EXPORT SPI1_IRQHandler          [WEAK] ;  0x21  0x0084  33: SPIMSS
+                EXPORT RSV07_IRQHandler         [WEAK] ;  0x22  0x0088  34: RSV07
+                EXPORT RSV08_IRQHandler         [WEAK] ;  0x23  0x008C  35: RSV08
+                EXPORT RSV09_IRQHandler         [WEAK] ;  0x24  0x0090  36: RSV09
+                EXPORT RSV10_IRQHandler         [WEAK] ;  0x25  0x0094  37: RSV10
+                EXPORT RSV11_IRQHandler         [WEAK] ;  0x26  0x0098  38: RSV11
+                EXPORT FLC_IRQHandler           [WEAK] ;  0x27  0x009C  39: FLC
+                EXPORT GPIO0_IRQHandler         [WEAK] ;  0x28  0x00A0  40: GPIO0
+                EXPORT RSV12_IRQHandler         [WEAK] ;  0x29  0x00A4  41: RSV12
+                EXPORT RSV13_IRQHandler         [WEAK] ;  0x2A  0x00A8  42: RSV13
+                EXPORT RSV14_IRQHandler         [WEAK] ;  0x2B  0x00AC  43: RSV14
+                EXPORT DMA0_IRQHandler          [WEAK] ;  0x2C  0x00B0  44: DMA0
+                EXPORT DMA1_IRQHandler          [WEAK] ;  0x2D  0x00B4  45: DMA1
+                EXPORT DMA2_IRQHandler          [WEAK] ;  0x2E  0x00B8  46: DMA2
+                EXPORT DMA3_IRQHandler          [WEAK] ;  0x2F  0x00BC  47: DMA3
+                EXPORT RSV15_IRQHandler         [WEAK] ;  0x30  0x00C0  48: RSV15
+                EXPORT RSV16_IRQHandler         [WEAK] ;  0x31  0x00C4  49: RSV16
+                EXPORT RSV17_IRQHandler         [WEAK] ;  0x32  0x00C8  50: RSV17
+                EXPORT RSV18_IRQHandler         [WEAK] ;  0x33  0x00CC  51: RSV18
+                EXPORT I2C1_IRQHandler          [WEAK] ;  0x34  0x00D0  52: I2C1
+                EXPORT RSV19_IRQHandler         [WEAK] ;  0x35  0x00D4  53: RSV19
+                EXPORT RSV20_IRQHandler         [WEAK] ;  0x36  0x00D8  54: RSV20
+                EXPORT RSV21_IRQHandler         [WEAK] ;  0x37  0x00DC  55: RSV21
+                EXPORT RSV22_IRQHandler         [WEAK] ;  0x38  0x00E0  56: RSV22
+                EXPORT RSV23_IRQHandler         [WEAK] ;  0x39  0x00E4  57: RSV23
+                EXPORT RSV24_IRQHandler         [WEAK] ;  0x3A  0x00E8  58: RSV24
+                EXPORT RSV25_IRQHandler         [WEAK] ;  0x3B  0x00EC  59: RSV25
+                EXPORT RSV26_IRQHandler         [WEAK] ;  0x3C  0x00F0  60: RSV26
+                EXPORT RSV27_IRQHandler         [WEAK] ;  0x3D  0x00F4  61: RSV27
+                EXPORT RSV28_IRQHandler         [WEAK] ;  0x3E  0x00F8  62: RSV28
+                EXPORT RSV29_IRQHandler         [WEAK] ;  0x3F  0x00FC  63: RSV29
+                EXPORT RSV30_IRQHandler         [WEAK] ;  0x40  0x0100  64: RSV30
+                EXPORT RSV31_IRQHandler         [WEAK] ;  0x41  0x0104  65: RSV31
+                EXPORT RSV32_IRQHandler         [WEAK] ;  0x42  0x0108  66: RSV32
+                EXPORT RSV33_IRQHandler         [WEAK] ;  0x43  0x010C  67: RSV33
+                EXPORT RSV34_IRQHandler         [WEAK] ;  0x44  0x0110  68: RSV34
+                EXPORT RSV35_IRQHandler         [WEAK] ;  0x45  0x0114  69: RSV35
+                EXPORT GPIOWAKE_IRQHandler      [WEAK] ;  0x46  0x0118  70: GPIO Wakeup
+
+;*******************************************************************************
+; Default handler implementations
+;*******************************************************************************
+PF_IRQHandler                                   ;  0x10  0x0040  16: Power Fail
+WDT0_IRQHandler                                 ;  0x11  0x0044  17: Watchdog 0
+RSV00_IRQHandler                                ;  0x12  0x0048  18: RSV00
+RTC_IRQHandler                                  ;  0x13  0x004C  19: RTC
+RSV01_IRQHandler                                ;  0x14  0x0050  20: RSV01
+TMR0_IRQHandler                                 ;  0x15  0x0054  21: Timer 0
+TMR1_IRQHandler                                 ;  0x16  0x0058  22: Timer 1
+TMR2_IRQHandler                                 ;  0x17  0x005C  23: Timer 2
+RSV02_IRQHandler                                ;  0x18  0x0060  24: RSV02
+RSV03_IRQHandler                                ;  0x19  0x0064  25: RSV03
+RSV04_IRQHandler                                ;  0x1A  0x0068  26: RSV04
+RSV05_IRQHandler                                ;  0x1B  0x006C  27: RSV05
+RSV06_IRQHandler                                ;  0x1C  0x0070  28: RSV06
+I2C0_IRQHandler                                 ;  0x1D  0x0074  29: I2C0
+UART0_IRQHandler                                ;  0x1E  0x0078  30: UART 0
+UART1_IRQHandler                                ;  0x1F  0x007C  31: UART 1
+SPI0_IRQHandler                                 ;  0x20  0x0080  32: SPI0
+SPI1_IRQHandler                                 ;  0x21  0x0084  33: SPI1
+RSV07_IRQHandler                                ;  0x22  0x0088  34: RSV07
+RSV08_IRQHandler                                ;  0x23  0x008C  35: RSV08
+RSV09_IRQHandler                                ;  0x24  0x0090  36: RSV09
+RSV10_IRQHandler                                ;  0x25  0x0094  37: RSV10
+RSV11_IRQHandler                                ;  0x26  0x0098  38: RSV11
+FLC_IRQHandler                                  ;  0x27  0x009C  39: FLC
+GPIO0_IRQHandler                                ;  0x28  0x00A0  40: GPIO0
+RSV12_IRQHandler                                ;  0x29  0x00A4  41: RSV12
+RSV13_IRQHandler                                ;  0x2A  0x00A8  42: RSV13
+RSV14_IRQHandler                                ;  0x2B  0x00AC  43: RSV14
+DMA0_IRQHandler                                 ;  0x2C  0x00B0  44: DMA0
+DMA1_IRQHandler                                 ;  0x2D  0x00B4  45: DMA1
+DMA2_IRQHandler                                 ;  0x2E  0x00B8  46: DMA2
+DMA3_IRQHandler                                 ;  0x2F  0x00BC  47: DMA3
+RSV15_IRQHandler                                ;  0x30  0x00C0  48: RSV15
+RSV16_IRQHandler                                ;  0x31  0x00C4  49: RSV16
+RSV17_IRQHandler                                ;  0x32  0x00C8  50: RSV17
+RSV18_IRQHandler                                ;  0x33  0x00CC  51: RSV18
+I2C1_IRQHandler                                 ;  0x34  0x00D0  52: I2C1
+RSV19_IRQHandler                                ;  0x35  0x00D4  53: RSV19
+RSV20_IRQHandler                                ;  0x36  0x00D8  54: RSV20
+RSV21_IRQHandler                                ;  0x37  0x00DC  55: RSV21
+RSV22_IRQHandler                                ;  0x38  0x00E0  56: RSV22
+RSV23_IRQHandler                                ;  0x39  0x00E4  57: RSV23
+RSV24_IRQHandler                                ;  0x3A  0x00E8  58: RSV24
+RSV25_IRQHandler                                ;  0x3B  0x00EC  59: RSV25
+RSV26_IRQHandler                                ;  0x3C  0x00F0  60: RSV26
+RSV27_IRQHandler                                ;  0x3D  0x00F4  61: RSV27
+RSV28_IRQHandler                                ;  0x3E  0x00F8  62: RSV28
+RSV29_IRQHandler                                ;  0x3F  0x00FC  63: RSV29
+RSV30_IRQHandler                                ;  0x40  0x0100  64: RSV30
+RSV31_IRQHandler                                ;  0x41  0x0104  65: RSV31
+RSV32_IRQHandler                                ;  0x42  0x0108  66: RSV32
+RSV33_IRQHandler                                ;  0x43  0x010C  67: RSV33
+RSV34_IRQHandler                                ;  0x44  0x0110  68: RSV34
+RSV35_IRQHandler                                ;  0x45  0x0114  69: RSV35
+GPIOWAKE_IRQHandler                             ;  0x46  0x0118  70: GPIO Wakeup
+
+                B       .
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap\
+                PROC
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, = (Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+                END
+
+;;;;;;;;;;;;;;;;;;;;;;;;;
+;; End of file.
+;;;;;;;;;;;;;;;;;;;;;;;;;

bsp/maxim/libraries/CMSIS/system_max32660.c

@@ -0,0 +1,167 @@
+/**
+ * @file       system_max32660.c
+ * @brief      System-level initialization implementation file
+ */
+
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "max32660.h"
+#include "gcr_regs.h"
+#include "pwrseq_regs.h"
+#include "tmr_regs.h"
+#include "wdt_regs.h"
+#include "mxc_sys.h"
+
+extern void (* const __isr_vector[])(void);
+uint32_t SystemCoreClock = HIRC96_FREQ;
+
+__weak void SystemCoreClockUpdate(void)
+{
+    uint32_t base_freq, div, clk_src,ovr;
+
+    // Get the clock source and frequency
+    clk_src = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_CLKSEL);
+    
+    if (clk_src == MXC_S_GCR_CLKCN_CLKSEL_HFXIN) {
+        base_freq = HFX_FREQ;
+    } else {
+	if (clk_src == MXC_S_GCR_CLKCN_CLKSEL_NANORING) {
+	    base_freq = NANORING_FREQ;
+	} else {
+	    ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
+	    if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
+		base_freq = HIRC96_FREQ/4;
+	    } else {
+		if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
+		    base_freq = HIRC96_FREQ/2;
+		} else {
+		    base_freq = HIRC96_FREQ;
+		}
+	    }
+	}
+    }
+
+    // Get the clock divider
+    div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS;
+
+    SystemCoreClock = base_freq >> div;
+}
+
+/* This function is called before C runtime initialization and can be
+ * implemented by the application for early initializations. If a value other
+ * than '0' is returned, the C runtime initialization will be skipped.
+ *
+ * You may over-ride this function in your program by defining a custom
+ *  PreInit(), but care should be taken to reproduce the initilization steps
+ *  or a non-functional system may result.
+ */
+__weak int PreInit(void)
+{
+    /* Do nothing */
+    return 0;
+}
+
+/* This function can be implemented by the application to initialize the board */
+__weak int Board_Init(void)
+{
+    /* Do nothing */
+    return 0;
+}
+
+/* This function is called just before control is transferred to main().
+ *
+ * You may over-ride this function in your program by defining a custom
+ *  SystemInit(), but care should be taken to reproduce the initialization
+ *  steps or a non-functional system may result.
+ */
+__weak void SystemInit(void)
+{
+    /* Configure the interrupt controller to use the application vector table in */
+    /* the application space */
+    /* IAR & Keil must set vector table after all memory initialization. */
+    SCB->VTOR = (unsigned long)__isr_vector;
+
+    MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN;  /* Turn off watchdog. Application can re-enable as needed. */
+
+    /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
+    /* Grant full access, per "Table B3-24 CPACR bit assignments". */
+    /* DDI0403D "ARMv7-M Architecture Reference Manual" */
+    SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
+    __DSB();
+    __ISB();
+
+    /* Switch system clock to HIRC */
+    SYS_Clock_Select(SYS_CLOCK_HIRC, MXC_TMR0);
+
+    /* Disable clocks to peripherals by default to reduce power */
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_DMA);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_SPI17Y);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_SPIMSS);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_UART0);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_UART1);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C0);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_T0);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_T1);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_T2);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C1);
+    
+    Board_Init();
+}
+
+#if defined ( __CC_ARM )
+/* Global variable initialization does not occur until post scatterload in Keil tools.*/
+
+/* External function called after our post scatterload function implementation. */
+extern void $Super$$__main_after_scatterload(void);
+
+/**
+ * @brief   Initialization function for SystemCoreClock and Board_Init.
+ * @details $Sub$$__main_after_scatterload is called during system startup in the Keil
+ *          toolset. Global variable and static variable space must be set up by the compiler
+ *          prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init
+ *          require global memory for variable storage and are called from this function in
+ *          the Keil tool chain.
+ */
+void $Sub$$__main_after_scatterload(void)
+{
+    SystemInit();
+    $Super$$__main_after_scatterload();
+}
+#endif /* __CC_ARM */

bsp/maxim/libraries/CMSIS/system_max32660.h

@@ -0,0 +1,93 @@
+/**
+ * @file    system_max32660.h
+ * @brief   System-specific header file
+ */
+
+
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+#ifndef _SYSTEM_MAX32660_H_
+#define _SYSTEM_MAX32660_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+
+#ifndef HFX_FREQ
+#define HFX_FREQ                32768
+#endif
+
+#ifndef NANORING_FREQ
+#define NANORING_FREQ           8000
+#endif
+
+#ifndef HIRC96_FREQ
+#define HIRC96_FREQ             96000000
+#endif
+
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */
+#ifndef PeripheralClock
+#define         PeripheralClock     (SystemCoreClock /2)    /*!< Peripheral Clock Frequency */
+#endif
+
+/*
+ * Initialize the system
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/*
+ * Update SystemCoreClock variable
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_MAX32660_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/dma.h

@@ -0,0 +1,317 @@
+/**
+ * @file
+ * @brief   Direct Memory Access (DMA) driver function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-07-01 11:06:19 -0500 (Mon, 01 Jul 2019) $
+ * $Revision: 44383 $
+ *
+ *************************************************************************** */
+
+#ifndef _DMA_H_
+#define _DMA_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "dma_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup dma Direct Memory Access (DMA)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * Enumeration for the DMA Channel's priority level.
+ */
+typedef enum {
+    DMA_PRIO_HIGH = MXC_S_DMA_CFG_PRI_HIGH,         /**< High Priority */
+    DMA_PRIO_MEDHIGH = MXC_S_DMA_CFG_PRI_MEDHIGH,   /**< Medium High Priority */
+    DMA_PRIO_MEDLOW = MXC_S_DMA_CFG_PRI_MEDLOW,     /**< Medium Low Priority */
+    DMA_PRIO_LOW = MXC_S_DMA_CFG_PRI_LOW,           /**< Low Priority */
+} dma_priority_t;
+
+/** @brief DMA request select */
+typedef enum {
+    DMA_REQSEL_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM,        /**< Memory to Memory DMA Request Selection */
+    DMA_REQSEL_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX,            /**< SPI0 Receive DMA Request Selection */
+    DMA_REQSEL_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX,            /**< SPI1 Receive DMA Request Selection */
+    DMA_REQSEL_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX,          /**< UART0 Receive DMA Request Selection */
+    DMA_REQSEL_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX,          /**< UART1 Receive DMA Request Selection */
+    DMA_REQSEL_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX,            /**< I2C0 Receive DMA Request Selection */
+    DMA_REQSEL_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX,            /**< I2C1 Receive DMA Request Selection */
+    DMA_REQSEL_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX,            /**< SPI0 Transmit DMA Request Selection */
+    DMA_REQSEL_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX,            /**< SPI1 Transmit DMA Request Selection */
+    DMA_REQSEL_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX,          /**< UART0 Transmit DMA Request Selection */
+    DMA_REQSEL_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX,          /**< UART1 Transmit DMA Request Selection */
+    DMA_REQSEL_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX,            /**< I2C0 Transmit DMA Request Selection */
+    DMA_REQSEL_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX,            /**< I2C1 Transmit DMA Request Selection */
+} dma_reqsel_t;
+
+/** @brief Enumeration for the DMA prescaler */
+typedef enum {
+    DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS,     /**< Prescaler disabled */
+    DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256,   /**< Divide by 256 */
+    DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K,   /**< Divide by 65,536 */
+    DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M,   /**< Divide by 16,777,216 */
+} dma_prescale_t;
+
+/** @brief Enumeration for the DMA timeout value */
+typedef enum {
+    DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4,        /**< DMA timeout of 4 clocks */
+    DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8,        /**< DMA timeout of 8 clocks */
+    DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16,      /**< DMA timeout of 16 clocks */
+    DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32,      /**< DMA timeout of 32 clocks */
+    DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64,      /**< DMA timeout of 64 clocks */
+    DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128,    /**< DMA timeout of 128 clocks */
+    DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256,    /**< DMA timeout of 256 clocks */
+    DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512,    /**< DMA timeout of 512 clocks */
+} dma_timeout_t;
+
+/** @brief DMA transfer data width */
+typedef enum {
+    /* Using the '_V_' define instead of the '_S_' since these same values will be used to 
+       specify the DSTWD also.  The API functions will shift the value the correct amount 
+       prior to writing the cfg register. */
+    DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE,          /**< DMA transfer in bytes */
+    DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD,  /**< DMA transfer in 16-bit half-words */
+    DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD,          /**< DMA transfer in 32-bit words */
+} dma_width_t;
+
+/** @brief Convenience defines for options */
+#define DMA_FALSE 0 /**< Define for passing 0 to DMA functions */
+#define DMA_TRUE  1 /**< Define for passing 1 to DMA functions */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Initialize DMA resources
+ * @details    This initialization is required before using the DMA driver functions.
+ * @return     #E_NO_ERROR if successful
+ */
+int DMA_Init(void);
+
+
+/**
+ * @brief      Request DMA channel
+ * @details    Returns a handle to the first free DMA channel, which can be used via API calls
+ *             or direct access to channel registers using the DMA_GetCHRegs(int ch) function.
+ * @return     Non-negative channel handle (inclusive of zero).
+ * @return     #E_NONE_AVAIL    All channels in use.
+ * @return     #E_BAD_STATE     DMA is not initialized, call DMA_Init() first.
+ * @return     #E_BUSY          DMA is currently busy (locked), try again later.
+ */
+int DMA_AcquireChannel(void);
+
+/**
+ * @brief      Release DMA channel
+ * @details    Stops any DMA operation on the channel and returns it to the pool of free channels.
+ *
+ * @param          ch   channel handle to release
+ *
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int DMA_ReleaseChannel(int ch);
+
+/**
+ * @brief      Configure the DMA channel
+ * @details    Configures the channel, which was previously requested by DMA_Getchannel()
+ *
+ * @param      ch           The channel to configure
+ * @param      prio         The channel's priority
+ * @param      reqsel       Select the DMA request line
+ * @param      reqwait_en   The enable delay before request
+ * @param      tosel        The transfer timer timeout select
+ * @param      pssel        The transfer timer prescale select
+ * @param      srcwd        The size of the read transactions
+ * @param      srcinc_en    Enable auto-increment source pointer
+ * @param      dstwd        The size of write transactions
+ * @param      dstinc_en    Enable auto-increment destination pointer
+ * @param      burst_size   The number of bytes transferred in one transaction
+ * @param      chdis_inten  The channel disable interrupt enable
+ * @param      ctz_inten    The count-to-zero interrupt enable
+ *
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_ConfigChannel(int ch,
+                      dma_priority_t prio,
+                      dma_reqsel_t reqsel, unsigned int reqwait_en,
+                      dma_timeout_t tosel, dma_prescale_t pssel,
+                      dma_width_t srcwd, unsigned int srcinc_en,
+                      dma_width_t dstwd, unsigned int dstinc_en,
+                      unsigned int burst_size, unsigned int chdis_inten,
+                      unsigned int ctz_inten);
+
+/**
+ * @brief      Set channel source, destination, and count for transfer
+ * @param      ch   channel handle
+ * @param      src_addr  source address (*)
+ * @param      dst_addr  destination address (*)
+ * @param      count  number of bytes to transfer
+ * @details    This function is used to set the source and destination addresses and the number
+ *             of bytes to transfer using the channel, @p ch.
+ * @note       Unless the channel request select is #DMA_REQSEL_MEMTOMEM,
+ *             either src_addr or dst_addr will be ignored by the DMA engine.
+ *             In these cases, the address is a don't-care. See the User's
+ *             Guide for more information.
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_SetSrcDstCnt(int ch,
+                     void *src_addr,
+                     void *dst_addr,
+                     unsigned int count);
+
+/**
+ * @brief      Set channel reload values
+ * @param      ch   channel handle
+ * @param      src_addr_reload  source address
+ * @param      dst_addr_reload  destination address
+ * @param      count_reload  number of bytes to transfer
+ * @details    This function will set the values which will be loaded after the
+ *             channel count register reaches zero. After enabling, call with
+ *             count_reload set to zero to disable reload.
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_SetReload(int ch,
+                  void *src_addr_reload,
+                  void *dst_addr_reload,
+                  unsigned int count_reload);
+
+/**
+ * @brief      Set channel interrupt callback
+ * @param      ch        channel handle
+ * @param      callback  Pointer to a function to call when the channel
+ *                       interrupt flag is set and interrupts are enabled or
+ *                       when DMA is shutdown by the driver.
+ * @details    Configures the channel interrupt callback. The @p callback
+ *             function is called for two conditions:
+ *               -# When the channel's interrupt flag is set and DMA interrupts
+ *                  are enabled.
+ *               -# If the driver calls the DMA_Shutdown() function. The
+ *                  callback function prototype is:
+ * @code
+ *             void callback_fn(int ch, int reason);
+ * @endcode
+ *             @p ch indicates the channel that generated the callback, @p
+ *             reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN
+ *             if the DMA is being shutdown.
+ *
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_SetCallback(int ch, void (*callback)(int, int));
+
+/**
+ * @brief      Enable channel interrupt
+ * @param      ch   channel handle
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_EnableInterrupt(int ch);
+
+/**
+ * @brief      Disable channel interrupt
+ * @param      ch   channel handle
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_DisableInterrupt(int ch);
+
+/**
+ * @brief Read channel interrupt flags
+ * @param      ch channel handle
+ * @param      fl flags to get
+ * @return    #E_BAD_PARAM if an unused or invalid channel handle
+ * @return    #E_NO_ERROR otherwise
+ */
+int DMA_GetFlags(int ch, unsigned int *fl);
+
+/**
+ * @brief      Clear channel interrupt flags
+ * @param      ch   channel handle
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_ClearFlags(int ch);
+
+/**
+ * @brief      Start transfer
+ * @param      ch   channel handle
+ * @details    Start the DMA channel transfer, assumes that DMA_SetSrcDstCnt() has been called beforehand.
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_Start(int ch);
+
+/**
+ * @brief      Stop DMA transfer, irrespective of status (complete or in-progress)
+ * @param      ch   channel handle
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_Stop(int ch);
+
+/**
+ * @brief      Get a pointer to the DMA channel registers
+ * @param      ch   channel handle
+ * @details    If direct access to DMA channel registers is required, this
+ *             function can be used on a channel handle returned by DMA_AcquireChannel().
+ * @return     NULL if an unused or invalid channel handle, or a valid pointer otherwise
+ */
+mxc_dma_ch_regs_t *DMA_GetCHRegs(int ch);
+
+/**
+ * @brief      Interrupt handler function
+ * @param      ch   channel handle
+ * @details    Call this function as the ISR for each DMA channel under driver control.
+ *             Interrupt flags for channel ch will be automatically cleared before return.
+ * @return     NULL if an unused or invalid channel handle, or a valid pointer otherwise
+ */
+void DMA_Handler(int ch);
+
+/**@} end of group dma */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DMA_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/flc.h

@@ -0,0 +1,200 @@
+/**
+ * @file
+ * @brief      Flash Controler driver.
+ * @details    This driver can be used to operate on the embedded flash memory.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-06-05 16:53:29 -0500 (Wed, 05 Jun 2019) $
+ * $Revision: 43696 $
+ *
+ *************************************************************************** */
+
+#ifndef _FLC_H_
+#define _FLC_H_
+
+/* **** Includes **** */
+#include "flc_regs.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup flc Flash Controller
+ * @ingroup periphlibs
+ * @{
+ */
+
+/***** Definitions *****/
+
+/// Bit mask that can be used to find the starting address of a page in flash
+#define MXC_FLASH_PAGE_MASK         ~(MXC_FLASH_PAGE_SIZE - 1)
+
+/// Calculate the address of a page in flash from the page number
+#define MXC_FLASH_PAGE_ADDR(page)   (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
+
+/***** Function Prototypes *****/
+
+/**
+ * @brief      Initializes the flash controller for erase/write operations
+ * @param      sys_cfg      Reserved for future use.  Use NULL as this parameter's value.  
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int FLC_Init(const sys_cfg_flc_t *sys_cfg);
+  
+/**
+ * @brief      Checks if Flash controller is busy.
+ * @details    Reading or executing from flash is not possible if flash is busy
+ *             with an erase or write operation.
+ * @return     If non-zero, flash operation is in progress
+ */
+int FLC_Busy(void);
+  
+/**
+ * @brief      Erases the entire flash array.
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int FLC_MassErase(void);
+
+/**
+ * @brief      Erases the page of flash at the specified address.
+ * @param      address  Any address within the page to erase.
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int FLC_PageErase(uint32_t address);
+
+/**
+ * @brief      Page erase from start to end address.
+ * @note       All data within the selected pages will be erased.
+ * @param      start  Any address within the first page to erase.
+ * @param      end    Any address within the last page to erase.
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int FLC_Erase(uint32_t start, uint32_t end);
+
+/**
+ * @brief      Erase from start to end address.  Restoring any flash page contents outside the given range.
+ * @param      start    Starting address to erase, inclusive.
+ * @param      end      Ending address to erase, exclusive.
+ * @param      buffer   Data buffer to restore data in beginning and ending pages.
+ * @param      length   Length of given buffer.
+ * 
+ * @note       Buffer should be appropriate size to store all of the data remaining in the 
+ * first and last pages. length should be greater than or equal to 
+ * (start % MXC_FLASH_PAGE_SIZE) and ((MXC_FLASH_PAGE_SIZE - (end % MXC_FLASH_PAGE_SIZE)) % MXC_FLASH_PAGE_SIZE).
+ * 
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int FLC_BufferErase(uint32_t start, uint32_t end, uint8_t *buffer, unsigned length);
+
+/**
+ * @brief      Writes the specified 32-bit value to flash.
+ * @param      address  32-bit aligned address in flash to write.
+ * @param      data     value to be written to flash.
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int FLC_Write32(uint32_t address, uint32_t data);
+
+/**
+ * @brief      Writes the specified 128-bits of data to flash.
+ * @param      address  128-bit aligned address in flash to write.
+ * @param      data     pointer to data to be written to flash.
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int FLC_Write128(uint32_t address, uint32_t *data);
+
+/**
+ * @brief      Writes data to flash.
+ * @param      address  Address in flash to start writing from.
+ * @param      length   Number of bytes to be written.
+ * @param      buffer   Pointer to data to be written to flash.
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int FLC_Write(uint32_t address, uint32_t length, uint8_t *buffer);
+
+/**
+ * @brief      Enable flash interrupts
+ * @param      mask   Interrupts to enable
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int FLC_EnableInt(uint32_t mask);
+
+/**
+ * @brief      Disable flash interrupts
+ * @param      mask   Interrupts to disable
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int FLC_DisableInt(uint32_t mask);
+
+/**
+ * @brief      Retrieve flash interrupt flags
+ * @return     Mask of active flags.
+ */
+int FLC_GetFlags(void);
+
+/**
+ * @brief      Clear flash interrupt flags
+ * @note       Provide the bit position to clear, even if the flag is write-0-to-clear
+ * @param      mask Mask of flags to clear
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int FLC_ClearFlags(uint32_t mask);
+
+/**
+ * @brief      Unlock info block
+ *
+ * @return     #E_NO_ERROR If function is successful.
+ */
+int FLC_UnlockInfoBlock(void);
+
+/**
+ * @brief      Lock info block
+ *
+ * @return     #E_NO_ERROR If function is successful.
+ */
+int FLC_LockInfoBlock(void);
+/**@} end of group flc */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLC_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/gpio.h

@@ -0,0 +1,295 @@
+/**
+ * @file    gpio.h
+ * @brief   General-Purpose Input/Output (GPIO) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+/* **** Includes **** */
+#include "gpio_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup gpio General-Purpose Input/Output (GPIO)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/* **** Definitions **** */
+/**
+ * @defgroup gpio_port_pin Port and Pin Definitions
+ * @ingroup gpio
+ * @{
+ * @defgroup gpio_port Port Definitions
+ * @ingroup gpio_port_pin
+ * @{
+ */
+#define PORT_0      ((uint32_t)(0UL))             /**< Port 0  Define*/
+#define PORT_1      ((uint32_t)(1UL))             /**< Port 1  Define*/
+#define PORT_2      ((uint32_t)(2UL))             /**< Port 2  Define*/
+#define PORT_3      ((uint32_t)(3UL))             /**< Port 3  Define*/
+#define PORT_4      ((uint32_t)(4UL))             /**< Port 4  Define*/
+/**@} end of gpio_port group*/
+/**
+ * @defgroup gpio_pin Pin Definitions
+ * @ingroup gpio_port_pin
+ * @{
+ */
+#define PIN_0       ((uint32_t)(1UL << 0))       /**< Pin 0 Define */
+#define PIN_1       ((uint32_t)(1UL << 1))       /**< Pin 1 Define */
+#define PIN_2       ((uint32_t)(1UL << 2))       /**< Pin 2 Define */
+#define PIN_3       ((uint32_t)(1UL << 3))       /**< Pin 3 Define */
+#define PIN_4       ((uint32_t)(1UL << 4))       /**< Pin 4 Define */
+#define PIN_5       ((uint32_t)(1UL << 5))       /**< Pin 5 Define */
+#define PIN_6       ((uint32_t)(1UL << 6))       /**< Pin 6 Define */
+#define PIN_7       ((uint32_t)(1UL << 7))       /**< Pin 7 Define */
+#define PIN_8       ((uint32_t)(1UL << 8))       /**< Pin 8 Define */
+#define PIN_9       ((uint32_t)(1UL << 9))       /**< Pin 9 Define */
+#define PIN_10      ((uint32_t)(1UL << 10))       /**< Pin 10 Define */
+#define PIN_11      ((uint32_t)(1UL << 11))       /**< Pin 11 Define */
+#define PIN_12      ((uint32_t)(1UL << 12))       /**< Pin 12 Define */
+#define PIN_13      ((uint32_t)(1UL << 13))       /**< Pin 13 Define */
+#define PIN_14      ((uint32_t)(1UL << 14))       /**< Pin 14 Define */
+#define PIN_15      ((uint32_t)(1UL << 15))       /**< Pin 15 Define */
+#define PIN_16      ((uint32_t)(1UL << 16))       /**< Pin 16 Define */
+#define PIN_17      ((uint32_t)(1UL << 17))       /**< Pin 17 Define */
+#define PIN_18      ((uint32_t)(1UL << 18))       /**< Pin 18 Define */
+#define PIN_19      ((uint32_t)(1UL << 19))       /**< Pin 19 Define */
+#define PIN_20      ((uint32_t)(1UL << 20))       /**< Pin 20 Define */
+#define PIN_21      ((uint32_t)(1UL << 21))       /**< Pin 21 Define */
+#define PIN_22      ((uint32_t)(1UL << 22))       /**< Pin 22 Define */
+#define PIN_23      ((uint32_t)(1UL << 23))       /**< Pin 23 Define */
+#define PIN_24      ((uint32_t)(1UL << 24))       /**< Pin 24 Define */
+#define PIN_25      ((uint32_t)(1UL << 25))       /**< Pin 25 Define */
+#define PIN_26      ((uint32_t)(1UL << 26))       /**< Pin 26 Define */
+#define PIN_27      ((uint32_t)(1UL << 27))       /**< Pin 27 Define */
+#define PIN_28      ((uint32_t)(1UL << 28))       /**< Pin 28 Define */
+#define PIN_29      ((uint32_t)(1UL << 29))       /**< Pin 29 Define */
+#define PIN_30      ((uint32_t)(1UL << 30))       /**< Pin 30 Define */
+#define PIN_31      ((uint32_t)(1UL << 31))       /**< Pin 31 Define */
+/**@} end of gpio_pin group */
+/**@} end of gpio_port_pin group */
+
+/**
+ * Enumeration type for the GPIO Function Type
+ */
+typedef enum {
+    GPIO_FUNC_IN,       /**< GPIO Input */
+    GPIO_FUNC_OUT,      /**< GPIO Output */
+    GPIO_FUNC_ALT1,     /**< Alternate Function Selection */
+    GPIO_FUNC_ALT2,     /**< Alternate Function Selection */
+    GPIO_FUNC_ALT3,     /**< Alternate Function Selection */
+    GPIO_FUNC_ALT4,     /**< Alternate Function Selection */
+} gpio_func_t;
+
+/**
+ * Enumeration type for the type of GPIO pad on a given pin.
+ */
+typedef enum {
+    GPIO_PAD_NONE,          /**< No pull-up or pull-down */
+    GPIO_PAD_PULL_UP,       /**< Set pad to weak pull-up */
+    GPIO_PAD_PULL_DOWN,     /**< Set pad to weak pull-down */
+} gpio_pad_t;
+
+/**
+ * Structure type for configuring a GPIO port.
+ */
+typedef struct {
+    uint32_t port;          /**< Index of GPIO port */
+    uint32_t mask;          /**< Pin mask (multiple pins may be set) */
+    gpio_func_t func;       /**< Function type */
+    gpio_pad_t pad;         /**< Pad type */
+} gpio_cfg_t;
+
+/**
+ * Enumeration type for the interrupt modes.
+ */
+typedef enum {
+  GPIO_INT_LEVEL = 0,   /**< Interrupt is level sensitive */
+  GPIO_INT_EDGE = 1     /**< Interrupt is edge sensitive */
+} gpio_int_mode_t;
+
+/**
+ * Enumeration type for the interrupt polarity.
+ */
+typedef enum {
+  GPIO_INT_FALLING = 0,                 /**< Interrupt triggers on falling edge */
+  GPIO_INT_HIGH = GPIO_INT_FALLING,     /**< Interrupt triggers when level is high */
+  GPIO_INT_RISING,                      /**< Interrupt triggers on rising edge */
+  GPIO_INT_LOW = GPIO_INT_RISING,       /**< Interrupt triggers when level is low */
+  GPIO_INT_BOTH                         /**< Interrupt triggers on either edge */
+} gpio_int_pol_t;
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Initialize GPIO.
+ * @return     #E_NO_ERROR if everything is successful.
+ */
+int GPIO_Init(void);
+
+/**
+ * @brief      Configure GPIO pin(s).
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ * @return     #E_NO_ERROR if everything is successful.
+ */
+int GPIO_Config(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Gets the pin(s) input state.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ * @return     The requested pin state.
+ */
+uint32_t GPIO_InGet(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Sets the pin(s) to a high level output.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ *
+ */
+void GPIO_OutSet(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Clears the pin(s) to a low level output.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ *
+ */
+void GPIO_OutClr(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Gets the pin(s) output state.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ *
+ * @return     The state of the requested pin.
+ *
+ */
+uint32_t GPIO_OutGet(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Write the pin(s) to a desired output level.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ * @param      val   Desired output level of the pin(s). This will be masked
+ *                   with the configuration mask.
+ */
+void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val);
+
+/**
+ * @brief      Toggles the the pin(s) output level.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ *
+ */
+void GPIO_OutToggle(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Configure GPIO interrupt(s)
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ * @param      mode  Requested interrupt mode.
+ * @param      pol   Requested interrupt polarity.
+ * @return     #E_NO_ERROR if everything is successful.
+ */
+int GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode, gpio_int_pol_t pol);
+
+/**
+ * @brief      Enables the specified GPIO interrupt
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ *
+ */
+void GPIO_IntEnable(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Disables the specified GPIO interrupt.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ */
+void GPIO_IntDisable(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Gets the interrupt(s) status on a GPIO pin.
+ * @param      cfg   Pointer to configuration structure describing the pin
+ *                   for which the status is being requested.
+ * @return     The requested interrupt status.
+ */
+uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Clears the interrupt(s) status on a GPIO pin.
+ * @param      cfg   Pointer to configuration structure describing the pin
+ *                   to clear the interrupt state of.
+ */
+void GPIO_IntClr(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Type alias for a GPIO callback function with prototype:
+ * @code
+    void callback_fn(void *cbdata);
+ * @endcode
+ * @param      cbdata  A void pointer to the data type as registered when
+ *                     GPIO_RegisterCallback() was called.
+ */
+typedef void (*gpio_callback_fn)(void *cbdata);
+
+/**
+ * @brief      Registers a callback for the interrupt on a given port and pin.
+ * @param      cfg       Pointer to configuration structure describing the pin
+ * @param      callback  A pointer to a function of type \c #gpio_callback_fn.
+ * @param      cbdata    The parameter to be passed to the callback function, #gpio_callback_fn, when an interrupt occurs.
+ *
+ */
+void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn callback, void *cbdata);
+
+/**
+ * @brief      GPIO IRQ Handler. @note If a callback is registered for a given
+ *             interrupt, the callback function will be called.
+ *
+ * @param      port number of the port that generated the interrupt service routine.
+ *
+ */
+void GPIO_Handler(unsigned int port);
+
+/**@} end of group gpio */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GPIO_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/i2c.h

@@ -0,0 +1,250 @@
+/**
+ * @file    i2c.h
+ * @brief   Inter-integrated circuit (I2C) communications interface driver.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-06-28 09:42:42 -0500 (Fri, 28 Jun 2019) $
+ * $Revision: 44330 $
+ *
+ *************************************************************************** */
+
+#ifndef _I2C_H_
+#define _I2C_H_
+
+#include <stdint.h>
+#include "i2c_regs.h"
+#include "mxc_sys.h"
+
+/**
+ * @defgroup i2c I2C
+ * @ingroup periphlibs
+ * @{
+ */
+
+/***** Definitions *****/
+
+/// @brief I2C Speed Modes
+typedef enum {
+    I2C_STD_MODE        = 100000,       //!< 100KHz Bus Speed 
+    I2C_FAST_MODE       = 400000,       //!< 400KHz Bus Speed 
+    I2C_FASTPLUS_MODE   = 1000000,      //!< 1MHz   Bus Speed
+    I2C_HS_MODE         = 3400000       //!< 3.4MHz Bus Speed 
+} i2c_speed_t;
+
+//State for Master
+typedef enum {
+    I2C_STATE_READING = 0,
+    I2C_STATE_WRITING = 1
+} i2c_state_t;
+
+// @brief Enable/Disable TXFIFO Autoflush mode
+typedef enum {
+    I2C_AUTOFLUSH_ENABLE   = 0,
+    I2C_AUTOFLUSH_DISABLE  = 1 
+} i2c_autoflush_disable_t;
+
+// @brief I2C Transaction request.
+typedef struct i2c_req i2c_req_t;
+struct i2c_req {
+
+    uint8_t addr;                  /**< @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
+                                     *     Only supports 7-bit addressing. LSb of the given address
+                                     *     will be used as the read/write bit, the @p addr <b>will 
+                                     *     not be shifted</b>. Used for <em>both master</em> and 
+                                     *     @em slave transactions. @endparblock
+                                     */
+    const uint8_t *tx_data;          ///< Data for mater write/slave read.
+    uint8_t *rx_data;                ///< Data for master read/slave write.
+    unsigned tx_len;                 ///< Length of tx data.
+    unsigned rx_len;                 ///< Length of rx.
+    unsigned tx_num;                 ///< Number of tx bytes sent.
+    unsigned rx_num;                 ///< Number of rx bytes sent.
+    i2c_state_t state;               ///< Read or Write.
+
+    /**
+     * @details     0 to send a stop bit at the end of the transaction, 
+                    otherwise send a restart. Only used in master trasnactions.
+     */
+    int restart;                   /**< @parblock Restart or stop bit indicator. 
+                                     *    @arg 0 to send a stop bit at the end of the transaction
+                                     *    @arg Non-zero to send a restart at end of the transaction
+                                     *    @note Only used for Master transactions.
+                                     *    @endparblock
+                                     */ 
+    i2c_autoflush_disable_t sw_autoflush_disable;       ///< Enable/Disable autoflush.
+
+    /**
+     * @brief   Callback for asynchronous request.
+     * @param   i2c_req_t*  Pointer to the transaction request.
+     * @param   int         Error code.
+     */
+    void (*callback)(i2c_req_t*, int);
+};
+
+/***** Function Prototypes *****/
+
+/**
+ * @brief   Initialize and enable I2C.
+ * @param      i2c     Pointer to I2C peripheral registers.
+ * @param      i2cspeed desired speed (I2C mode)
+ * @param      sys_cfg System configuration object
+ * @returns \c #E_NO_ERROR if everything is successful, 
+ *             @ref MXC_Error_Codes if an error occurred.
+ */
+int I2C_Init(mxc_i2c_regs_t * i2c, i2c_speed_t i2cspeed, const sys_cfg_i2c_t* sys_cfg);
+
+/**
+ * @brief   Shutdown I2C module.
+ * @param   i2c    Pointer to the I2C registers.
+ * @returns #E_NO_ERROR I2C shutdown successfully, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int I2C_Shutdown(mxc_i2c_regs_t *i2c);
+
+/**
+ * @brief   Master write data. Will block until transaction is complete.
+ * @param   i2c         Pointer to I2C regs.
+ * @param   addr        @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
+ *                          Only supports 7-bit addressing. LSb of the given address
+ *                          will be used as the read/write bit, the \p addr <b>will 
+ *                          not be shifted</b>. Used for <em>both master</em> and 
+ *                          @em slave transactions.    @endparblock                                 
+ * @param   data        Data to be written.
+ * @param   len         Number of bytes to Write.
+ * @param   restart     0 to send a stop bit at the end of the transaction, 
+                        otherwise send a restart.
+ * @returns Bytes transacted if everything is successful, 
+ *              @ref MXC_Error_Codes if an error occurred.
+ */
+int I2C_MasterWrite(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* data, int len, int restart);
+
+/**
+ * @brief   Master read data. Will block until transaction is complete.
+ * @param   i2c         Pointer to I2C regs.
+ * @param   addr        @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
+ *                          Only supports 7-bit addressing. LSb of the given address
+ *                          will be used as the read/write bit, the @p addr <b>will 
+ *                          not be shifted</b>. Used for <em>both master</em> and 
+ *                          @em slave transactions.  @endparblock
+ * @param   data        Data to be written.
+ * @param   len         Number of bytes to Write.
+ * @param   restart     0 to send a stop bit at the end of the transaction, 
+                        otherwise send a restart.
+ * @returns Bytes transacted if everything is successful, @ref MXC_Error_Codes if an error occurred.
+ */
+int I2C_MasterRead(mxc_i2c_regs_t *i2c, uint8_t addr, uint8_t* data, int len, int restart);
+
+/**
+ * @brief   Slave read data. Will block until transaction is complete.
+ * @param   i2c         Pointer to I2C regs.
+ * @param   addr        @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
+ *                          Only supports 7-bit addressing. LSb of the given address
+ *                          will be used as the read/write bit, the @p addr <b>will 
+ *                          not be shifted</b>. Used for <em>both master</em> and 
+ *                          @em slave transactions.  @endparblock
+ * @param   read_data   Buffer that the master will read from.
+ * @param   read_len    Number of bytes the master can read.
+ * @param   write_data  Buffer that the master will write to.
+ * @param   write_len   Number of bytes the master can write.
+ * @param   tx_num      Number of bytes transmitted by the slave.
+ * @param   rx_num      Number of bytes received by the slave.
+ * @param   sw_autoflush_disable      TX Autoflush enabled by default.Set this bit to disable autoflush manually.
+ * @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred.
+ */
+int I2C_Slave(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* read_data, 
+              int read_len, uint8_t* write_data, int write_len, int* tx_num, 
+              int* rx_num, i2c_autoflush_disable_t sw_autoflush_disable);
+
+/**
+ * @brief   Master Read and Write Asynchronous.
+ * @param   i2c         Pointer to I2C regs.
+ * @param   req         Request for an I2C transaction.
+ * @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred.
+ */
+int I2C_MasterAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req);
+
+/**
+ * @brief   Slave Read and Write Asynchronous.
+ * @param   i2c         Pointer to I2C regs.
+ * @param   req         Request for an I2C transaction.
+ * @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred.
+ */
+int I2C_SlaveAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req);
+/**
+ * @brief   I2C interrupt handler.
+ * @details This function should be called by the application from the interrupt
+ *          handler if I2C interrupts are enabled. Alternately, this function
+ *          can be periodically called by the application if I2C interrupts are
+ *          disabled.
+ * @param   i2c         Base address of the I2C module.
+ */
+void I2C_Handler(mxc_i2c_regs_t *i2c);
+
+/**
+ * @brief   Drain all of the data in the RXFIFO.
+ * @param   i2c     Pointer to I2C regs.
+ */
+void I2C_DrainRX(mxc_i2c_regs_t *i2c);
+
+/**
+ * @brief   Drain all of the data in the TXFIFO.
+ * @param   i2c     Pointer to I2C regs.
+ */
+void I2C_DrainTX(mxc_i2c_regs_t *i2c);
+
+/**
+ * @brief   Abort Async request based on the request you want to abort.
+ * @param   req     Pointer to I2C Transaction.
+ */
+int I2C_AbortAsync(i2c_req_t *req);
+
+/**
+ * @brief      Enable and Set Timeout 
+ *
+ * @param      i2c   pointer to I2C regs
+ * @param[in]  us    micro seconds to delay
+ *
+ * @return     E_NO_ERROR or E_BAD_PARAM if delay is to long.
+ */
+int I2C_SetTimeout(mxc_i2c_regs_t *i2c, int us);
+
+/**
+ * @brief      clear and disable timeout
+ *
+ * @param      i2c   pointer to I2C regs
+ */
+void I2C_ClearTimeout(mxc_i2c_regs_t *i2c);
+
+/**@} end of group i2c */
+#endif /* _I2C_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/i2s.h

@@ -0,0 +1,179 @@
+/**
+ * @file    i2s.h
+ * @brief   I2S (Inter-Integrated Sound) driver function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ *************************************************************************** */
+
+#ifndef _I2S_H_
+#define _I2S_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "dma.h"
+#include "spimss_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup i2s Inter-Integrated Sound (I2S)
+ * @ingroup spi
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/** @brief I2S audio directions */
+typedef enum {
+    AUDIO_OUT = 1,
+    AUDIO_IN = 2,
+} i2s_direction_t;
+
+/** @brief I2S Configuration Struct */
+typedef struct {
+    uint8_t                     left_justify;
+    uint8_t                     mono_audio;
+    i2s_direction_t             audio_direction;
+    unsigned int                sample_rate;
+    unsigned int                start_immediately;
+    void                        *dma_src_addr;
+    void                        *dma_dst_addr;
+    unsigned int                dma_cnt;
+    unsigned int                dma_reload_en;
+} i2s_cfg_t;
+  
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Initialize I2S resources 
+ * @param      cfg          I2S Configuration Struct
+ * @param      dma_ctz_cb   Optional function to be called when the DMA completes 
+                            a transfer. Set to NULL if unused.
+ * @param      sys_cfg_i2s  System configuration object
+ * @details    This initialization is required before using the I2S driver functions.
+ * @return   \c #E_NO_ERROR if successful
+ */
+int I2S_Init(const i2s_cfg_t *cfg, void (*dma_ctz_cb)(int, int), const sys_cfg_i2s_t* sys_cfg_i2s);
+
+/**
+ * @brief      Release I2S
+ * @details    De-configures the I2S protocol and stops DMA request
+ * @return   \c #E_BAD_PARAM if DMA cannot be stopped, #E_NO_ERROR otherwise
+ */  
+int I2S_Shutdown(void);
+
+/**
+ * @brief      Mute I2S Output
+ * @details    Sets I2S data to zero, continues sending clock and accessing DMA
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_Mute(void);
+
+/**
+ * @brief      Unmute I2S Output
+ * @details    Restores I2S data
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_Unmute(void);
+
+/**
+ * @brief      Pause I2S Output
+ * @details    Similar to mute, but stops FIFO and DMA access, clocks continue
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_Pause(void);
+
+/**
+ * @brief      Unpause I2S Output
+ * @details    Similar to mute, but restarts FIFO and DMA access
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_Unpause(void);
+
+/**
+ * @brief      Stops I2S Output
+ * @details    Similar to pause, but also halts clock
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_Stop(void);
+
+/**
+ * @brief      Starts I2S Output
+ * @details    Starts I2S Output, automatically called by configure if requested
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_Start(void);
+
+/**
+ * @brief      Clears DMA Interrupt Flags
+ * @details    Clears the DMA Interrupt flags, should be called at the end of a dma_ctz_cb
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_DMA_ClearFlags(void);
+
+/**
+ * @brief      Set DMA Addr (Source or Dest) and bytes to transfer
+ * @param      src_addr The address to read data from (Audio Out)
+ * @param      dst_addr The address to write data to (Audio In)    
+ * @param      count    The length of the transfer in bytes
+ * @details    Sets the address to read/write data in memory and the length of
+ *             the transfer. The unused addr parameter is ignored.
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count);
+
+/**
+ * @brief      Sets the DMA reload address and count
+ * @param      src_addr The address to read data from (Audio Out)
+ * @param      dst_addr The address to write data to (Audio In)    
+ * @param      count    The length of the transfer in bytes
+ * @details    If DMA reload is enabled, when the DMA has transfered $count bytes
+ *             (a CTZ event occurs) the src, dst, and count registers will be 
+ *             set to these. The DMA reload flag clears after a reload occurs.
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count);
+/**@} end of group i2s */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _I2S_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/icc.h

@@ -0,0 +1,97 @@
+/**
+ * @file    icc.h
+ * @brief   Instruction Controller Cache(ICC) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _ICC_H_
+#define _ICC_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+#include "icc_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup icc Internal Cache Controller (ICC)
+ * @ingroup periphlibs
+ * @{
+ */ 
+
+/**
+ * @brief Enumeration type for the Cache ID Register
+ */
+typedef enum {
+    ICC_CACHE_ID_RELNUM,	// Identifies the RTL release version
+    ICC_CACHE_ID_PARTNUM,	// Specifies the value of C_ID Port Number
+    ICC_CACHE_ID_CCHID		// Specifies the value of Cache ID
+} icc_cache_id_t;
+
+/**
+ * @brief	Reads the data from the Cache Id Register.
+ * @param	cid	Enumeration type for Cache Id Register.
+ * @retval	Returns the contents of Cache Id Register. 
+ */
+int ICC_ID(icc_cache_id_t cid);
+
+/**
+ * @brief	Enable the instruction cache controller.
+ */
+void ICC_Enable(void);
+
+/**
+ * @brief	Disable the instruction cache controller.
+ */
+void ICC_Disable(void);
+
+/**
+ * @brief	Flush the instruction cache controller.
+ */
+void ICC_Flush(void);
+
+/**@} end of group icc */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ICC_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/lp.h

@@ -0,0 +1,341 @@
+/**
+ * @file    lp.h
+ * @brief   Low power function prototypes and data types.
+ */
+
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-09-26 08:48:30 -0500 (Wed, 26 Sep 2018) $
+ * $Revision: 38105 $
+ *
+ *************************************************************************** */
+ 
+// Define to prevent redundant inclusion 
+#ifndef _LP_H_
+#define _LP_H_
+
+/***** Includes *****/
+#include "gpio.h"
+#include "pwrseq_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */
+typedef enum {
+    LP_OVR_0_9       = MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V,         /**< Reset DMA */
+    LP_OVR_1_0       = MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V,         /**< Reset DMA */
+    LP_OVR_1_1       = MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V,         /**< Reset DMA */
+} lp_ovr_t;
+
+/**
+ * @brief 	   Clears the low power wakeup flags
+ */	
+void LP_ClearWakeStatus(void);
+
+/**
+ * @brief      Enables power to RAM addresses 0x20010000-0x20017FFF.
+ */
+void LP_EnableSRAM3(void);
+
+/**
+ * @brief      Enables power to RAM addresses 0x20008000-0x2000FFFF.
+ */
+void LP_EnableSRAM2(void);
+
+/**
+ * @brief      Enables power to RAM addresses 0x20004000-0x20007FFF.
+ */
+void LP_EnableSRAM1(void);
+
+/**
+ * @brief      Enables power to RAM addresses 0x20000000-0x20003FFF.
+ */
+void LP_EnableSRAM0(void);
+
+/**
+ * @brief      Disables power to RAM addresses 0x20010000-0x20017FFF. The contents of the RAM are destroyed.
+ */
+void LP_DisableSRAM3(void);
+
+/**
+ * @brief      Disables power to RAM addresses 0x20008000-0x2000FFFF. The contents of the RAM are destroyed.
+ */
+void LP_DisableSRAM2(void);
+
+/**
+ * @brief      Disables power to RAM addresses 0x20004000-0x20007FFF. The contents of the RAM are destroyed.
+ */
+void LP_DisableSRAM1(void);
+
+/**
+ * @brief      Disables power to RAM addresses 0x20000000-0x20003FFF. The contents of the RAM are destroyed.
+ */
+void LP_DisableSRAM0(void);
+
+/**
+ * @brief      Places the instruction cache in light sleep mode. Data will be unavailable for read/write operations but will be retained.
+ */
+void LP_EnableICacheLightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20010000 to 0x20017FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
+ */
+void LP_EnableSysRAM3LightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20008000 to 0x2000FFFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
+ */
+void LP_EnableSysRAM2LightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20004000 to 0x20007FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
+ */
+void LP_EnableSysRAM1LightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20000000 to 0x20003FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
+ */
+void LP_EnableSysRAM0LightSleep(void);
+
+/**
+ * @brief      Places the instruction cache in active mode.
+ */
+void LP_DisableICacheLightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20010000 to 0x20017FFF of the RAM in active mode.
+ */
+void LP_DisableSysRAM3LightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20008000 to 0x2000FFFF of the RAM in active mode.
+ */
+void LP_DisableSysRAM2LightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20004000 to 0x20007FFF of the RAM in active mode.
+ */
+void LP_DisableSysRAM1LightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20000000 to 0x20003FFF of the RAM in active mode.
+ */
+void LP_DisableSysRAM0LightSleep(void);
+
+/**
+ * @brief      Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.  
+ *             Call this function multiple times to enable pins on multiple ports.  This function does not configure
+ *             the GPIO pins nor does it setup their interrupt functionality.
+ * @param      wu_pins      The port and pins to configure as wakeup sources.  Only the gpio and mask fields of the
+ *                          structure are used.  The func and pad fields are ignored.
+ */
+void LP_EnableGPIOWakeup(const gpio_cfg_t *wu_pins);
+
+/**
+ * @brief      Disables the selected GPIO port and its selected pins as a wake up source.  
+ *             Call this function multiple times to disable pins on multiple ports.
+ * @param      wu_pins      The port and pins to disable as wakeup sources.  Only the gpio and mask fields of the
+ *                          structure are used.  The func and pad fields are ignored.
+ */
+void LP_DisableGPIOWakeup(const gpio_cfg_t *wu_pins);
+
+/**
+ * @brief      Enables the RTC alarm to wake up the device from any low power mode.  
+ */
+void LP_EnableRTCAlarmWakeup(void);
+
+/**
+ * @brief      Disables the RTC alarm from waking up the device.  
+ */
+void LP_DisableRTCAlarmWakeup(void);
+
+/**
+ * @brief      Places the device into SLEEP mode.  This function returns once any interrupt occurs. 
+ * @note 	   LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
+ */
+void LP_EnterSleepMode(void);
+
+/**
+ * @brief      Places the device into DEEPSLEEP mode.  This function returns once an RTC or external interrupt occur. 
+ * @note      LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
+*/
+void LP_EnterDeepSleepMode(void);
+
+/**
+ * @brief      Places the device into BACKUP mode.  CPU state is not maintained in this mode, so this function never returns.  
+ *             Instead, the device will restart once an RTC or external interrupt occur. 
+ * @note       LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
+ */
+void LP_EnterBackupMode(void);
+
+/**
+ * @brief      Places the device into Shutdown mode.  CPU state is not maintained in this mode, so this function never returns.  
+ *             Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur. 
+ */
+void LP_EnterShutDownMode(void);
+
+/**
+ * @brief      Set operating voltage and change the clock to match the new voltage. 
+ * @param	   system reset configuration struct
+ */
+void LP_SetOperatingVoltage(lp_ovr_t ovr);
+
+/**
+ * @brief      Enables Data Retention to RAM addresses 0x20000000-0x20003FFF.
+ */
+void LP_EnableSRamRet0(void);
+
+/**
+ * @brief      Disables Data Retention to RAM addresses 0x20000000-0x20003FFF. 
+ */
+void LP_DisableSRamRet0(void);
+
+/**
+ * @brief      Enables Data Retention to RAM addresses 0x20004000-0x20007FFF.
+ */
+void LP_EnableSRamRet1(void);
+
+/**
+ * @brief      Disables Data Retention to RAM addresses 0x20004000-0x20007FFF.
+ */
+void LP_DisableSRamRet1(void);
+
+/**
+ * @brief      Enables Data Retention to RAM addresses 0x20008000-0x2000FFFF.
+ */
+void LP_EnableSRamRet2(void);
+
+/**
+ * @brief      Disables Data Retention to RAM addresses 0x20008000-0x2000FFFF.
+ */
+void LP_DisableSRamRet2(void);
+
+/**
+ * @brief      Enables Data Retention to RAM addresses 0x20010000-0x20017FFF.
+ */
+void LP_EnableSRamRet3(void);
+
+/**
+ * @brief      Disables Data Retention to RAM addresses 0x20010000-0x20017FFF.
+ */
+void LP_DisableSRamRet3(void);
+
+/**
+ * @brief      Enables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time.
+ */
+void LP_EnableBlockDetect(void);
+
+/**
+ * @brief      Disables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time
+ */
+void LP_DisableBlockDetect(void);
+
+/**
+ * @brief      RAM Retention Regulator Enable for BACKUP Mode
+ */
+void LP_EnableRamRetReg(void);
+
+/**
+ * @brief      RAM Retention Regulator Disabels for BACKUP Mode
+ */
+void LP_DisableRamRetReg(void);
+
+/**
+ * @brief      Enables Fast wake up from deepsleep 
+ */
+void LP_EnableFastWk(void);
+
+/**
+ * @brief      Disables Fast wake up from deepsleep
+ */
+void LP_DisableFastWk(void);
+
+/**
+ * @brief      Turns on band gap during deepsleep and backup mode. 
+ */
+void LP_EnableBandGap(void);
+
+/**
+ * @brief      Turns off band gap during deepsleep and backup mode.
+ */
+void LP_DisableBandGap(void);
+
+/**
+ * @brief     Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
+ */
+void LP_EnableVCorePORSignal(void);
+
+/**
+ * @brief     Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode 
+ */
+void LP_DisableVCorePORSignal(void);
+
+/**
+ * @brief     Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
+ */
+void LP_EnableLDO(void);
+
+/**
+ * @brief     Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode 
+ */
+void LP_DisableLDO(void);
+
+/**
+ * @brief     Enables V CORE Supply Voltage Monitor 
+ */
+void LP_EnableVCoreSVM(void);
+
+/**
+ * @brief     Disables V CORE Supply Voltage Monitor 
+ */
+void LP_DisableVCoreSVM(void);
+
+
+/**
+ * @brief     Enables VDDIO Power-On-Reset Monitor 
+ */
+void LP_EnableVDDIOPorMonitor(void);
+
+/**
+ * @brief     Disables VDDIO Power-On-Reset Monitor  
+ */
+void LP_DisableVDDIOPorMonitor(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LP_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/mxc_assert.h

@@ -0,0 +1,113 @@
+/**
+ * @file
+ * @brief      Assertion checks for debugging.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $ 
+ * $Revision: 36818 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_ASSERT_H_
+#define _MXC_ASSERT_H_
+
+/* **** Includes **** */
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup    syscfg
+ * @defgroup   mxc_assertions Assertion Checks for Debugging
+ * @brief      Assertion checks for debugging.
+ * @{
+ */ 
+/* **** Definitions **** */
+/**
+ * @note       To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ *             defined. 
+ */
+///@cond
+#ifdef MXC_ASSERT_ENABLE
+/**
+ * Macro that checks the expression for true and generates an assertion.
+ * @note       To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ *             defined.
+ */
+#define MXC_ASSERT(expr)                                \
+if (!(expr))                                            \
+{                                                       \
+    mxc_assert(#expr, __FILE__, __LINE__);              \
+}
+/**
+ * Macro that generates an assertion with the message "FAIL".
+ * @note       To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ *             defined.
+ */
+#define MXC_ASSERT_FAIL() mxc_assert("FAIL", __FILE__, __LINE__);
+#else
+#define MXC_ASSERT(expr)
+#define MXC_ASSERT_FAIL()
+#endif
+///@endcond
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Assert an error when the given expression fails during debugging.
+ * @param      expr  String with the expression that failed the assertion.
+ * @param      file  File containing the failed assertion.
+ * @param      line  Line number for the failed assertion.
+ * @note       This is defined as a weak function and can be overridden at the
+ *             application layer to print the debugging information. 
+ *             @code 
+ *             printf("%s, file: %s, line %d\n", expr, file, line);
+ *             @endcode
+ * @note       To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ *             defined. 
+ */
+void mxc_assert(const char *expr, const char *file, int line);
+
+/**@} end of group MXC_Assertions*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_ASSERT_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/mxc_config.h

@@ -0,0 +1,53 @@
+/**
+ * @file       mxc_config.h
+ * @brief      Top-level include file for device configuration.
+ */
+ 
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
+ * $Revision: 36818 $
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_CONFIG_H
+#define _MXC_CONFIG_H
+
+#if !defined __GNUC__
+#include "RTE_Components.h"
+#endif /* not __GNUC__ */
+
+#include "mxc_device.h"
+#include "mxc_errors.h"
+#include "mxc_pins.h"
+
+#endif /* _CONFIG_H */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/mxc_delay.h

@@ -0,0 +1,124 @@
+/**
+ * @file
+ * @brief    Asynchronous delay routines based on the SysTick Timer.
+*/
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-11-05 09:52:05 -0600 (Mon, 05 Nov 2018) $ 
+ * $Revision: 38934 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _DELAY_H_
+#define _DELAY_H_
+
+/**
+ * @defgroup    MXC_delay Delay Utility Functions 
+ * @ingroup     devicelibs 
+ * @brief       Asynchronous delay routines based on the SysTick Timer
+ * @{
+ */ 
+
+/***** Definitions *****/
+/**
+ * Macro used to specify a microsecond timing parameter in seconds.
+ * \code
+ * x = SEC(3) // 3 seconds -> x = 3,000,000 
+ * \endcode
+ */
+#define MXC_DELAY_SEC(s)            (((unsigned long)s) * 1000000UL)  
+/**
+ * Macro used to specify a microsecond timing parameter in milliseconds.
+ * \code
+ * x = MSEC(3) // 3ms -> x = 3,000
+ * \endcode
+ */
+#define MXC_DELAY_MSEC(ms)          (ms * 1000UL)
+/**
+ * Macro used to specify a microsecond timing parameter.
+ * \code
+ * x = USEC(3) // 3us -> x = 3
+ * \endcode
+ */
+#define MXC_DELAY_USEC(us)          (us)
+
+/***** Function Prototypes *****/
+
+/**
+ * @brief      Blocks and delays for the specified number of microseconds.
+ * @details    Uses the SysTick to create the requested delay. If the SysTick is
+ *             running, the current settings will be used. If the SysTick is not
+ *             running, it will be started.
+ * @param      us    microseconds to delay
+ * @return     #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int mxc_delay(unsigned long us);
+
+/**
+ * @brief      Starts a non-blocking delay for the specified number of
+ *             microseconds.
+ * @details    Uses the SysTick to time the requested delay. If the SysTick is
+ *             running, the current settings will be used. If the SysTick is not
+ *             running, it will be started.
+ * @note       mxc_delay_handler() must be called from the SysTick interrupt service
+ *             routine or at a rate greater than the SysTick overflow rate.
+ * @param      us    microseconds to delay
+ * @return     #E_NO_ERROR if no errors, #E_BUSY if currently servicing another
+ *             delay request.
+ */
+int mxc_delay_start(unsigned long us);
+
+/**
+ * @brief      Returns the status of a non-blocking delay request
+ * @pre        Start the asynchronous delay by calling mxc_delay_start().
+ * @return     #E_BUSY until the requested delay time has expired.
+ */
+int mxc_delay_check(void);
+
+/**
+ * @brief      Stops an asynchronous delay previously started.
+ * @pre        Start the asynchronous delay by calling mxc_delay_start().
+ */
+void mxc_delay_stop(void);
+
+/**
+ * @brief      Processes the delay interrupt.
+ * @details    This function must be called from the SysTick IRQ or polled at a
+ *             rate greater than the SysTick overflow rate.
+ */
+void mxc_delay_handler(void);
+
+/**@} end of group MXC_delay */
+
+#endif /* _DELAY_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/mxc_errors.h

@@ -0,0 +1,94 @@
+/**
+ * @file
+ * @brief    List of common error return codes for Maxim Integrated libraries. 
+*/
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $ 
+ * $Revision: 36818 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_ERRORS_H_
+#define _MXC_ERRORS_H_
+
+/**
+ * @ingroup syscfg
+ * @defgroup MXC_Error_Codes Error Codes
+ * @brief      A list of common error codes used by the API.
+ * @note       A Negative Error Convention is used to avoid conflict with
+ *             positive, Non-Error, returns. 
+ * @{
+ */ 
+
+/** No Error */
+#define		E_NO_ERROR		0
+/** No Error, success */
+#define		E_SUCCESS		0
+/** Pointer is NULL */ 
+#define		E_NULL_PTR		-1
+/** No such device */
+#define		E_NO_DEVICE		-2
+/** Parameter not acceptable */
+#define		E_BAD_PARAM		-3
+/** Value not valid or allowed */
+#define		E_INVALID		-4
+/** Module not initialized */
+#define		E_UNINITIALIZED	-5
+/** Busy now, try again later */
+#define		E_BUSY			-6
+/** Operation not allowed in current state */
+#define		E_BAD_STATE		-7
+/** Generic error */
+#define		E_UNKNOWN		-8
+/** General communications error */
+#define		E_COMM_ERR		-9
+/** Operation timed out */
+#define		E_TIME_OUT		-10
+/** Expected response did not occur */
+#define		E_NO_RESPONSE	-11
+/** Operations resulted in unexpected overflow */
+#define		E_OVERFLOW		-12
+/** Operations resulted in unexpected underflow */
+#define     E_UNDERFLOW     -13
+/** Data or resource not available at this time */
+#define		E_NONE_AVAIL	-14
+/** Event was shutdown */
+#define		E_SHUTDOWN		-15
+/** Event was aborted */
+#define     E_ABORT         -16
+/** The requested operation is not supported */
+#define		E_NOT_SUPPORTED	-17
+/**@} end of MXC_Error_Codes group */
+ 
+#endif /* _MXC_ERRORS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/mxc_lock.h

@@ -0,0 +1,94 @@
+/**
+ * @file
+ * @brief    Exclusive access lock utility functions.
+*/
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
+ * $Revision: 36818 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_LOCK_H_
+#define _MXC_LOCK_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup    syscfg
+ * @defgroup   mxc_lock_utilities Exclusive Access Locks
+ * @brief      Lock functions to obtain and release a variable for exclusive
+ *             access. These functions are marked interrupt safe if they are
+ *             interrupt safe.
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Attempts to acquire the lock.
+ * @details    This in an interrupt safe function that can be used as a mutex.
+ *             The lock variable must remain in scope until the lock is
+ *             released. Will not block if another thread has already acquired
+ *             the lock.
+ * @param      lock   Pointer to variable that is used for the lock.
+ * @param      value  Value to be place in the lock. Can not be 0.
+ *
+ * @return     #E_NO_ERROR if everything successful, #E_BUSY if lock is taken.
+ */
+int mxc_get_lock(uint32_t *lock, uint32_t value);
+
+/**
+ * @brief         Free the given lock.
+ * @param[in,out] lock  Pointer to the variable used for the lock. When the lock
+ *                      is free, the value pointed to by @p lock is set to zero.
+ */
+void mxc_free_lock(uint32_t *lock);
+
+/**@} end of group mxc_lock_utilities */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_LOCK_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/mxc_pins.h

@@ -0,0 +1,91 @@
+ /**
+ * @file       mxc_pins.h
+ * @brief      This file contains constant pin configurations for the peripherals.
+ */
+
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
+ * $Revision: 36818 $
+ *
+ **************************************************************************** */
+ 
+/* Define to prevent redundant inclusion */ 
+#ifndef _MXC_PINS_H_
+#define _MXC_PINS_H_
+
+/* **** Includes **** */
+#include "gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* **** Global Variables **** */
+
+// Predefined GPIO Configurations
+
+/*****  @brief TIMER pins *****/
+extern const gpio_cfg_t gpio_cfg_tmr0;
+
+/***** @brief UART pins *****/
+extern const gpio_cfg_t gpio_cfg_uart0rtscts;
+extern const gpio_cfg_t gpio_cfg_uart0a;
+extern const gpio_cfg_t gpio_cfg_uart1rtscts;
+extern const gpio_cfg_t gpio_cfg_uart1a;
+extern const gpio_cfg_t gpio_cfg_uart1b;
+extern const gpio_cfg_t gpio_cfg_uart1c;
+extern const gpio_cfg_t gpio_cfg_uart2;
+
+/***** @brief I2C pins *****/
+extern const gpio_cfg_t gpio_cfg_i2c0;
+extern const gpio_cfg_t gpio_cfg_i2c1;
+
+/***** @brief SPI/I2S pins *****/
+extern const gpio_cfg_t gpio_cfg_spi17y;    // SPI0A
+extern const gpio_cfg_t gpio_cfg_spimss1a;  // SPI1A
+extern const gpio_cfg_t gpio_cfg_spimss1b;  // SPI1B
+extern const gpio_cfg_t gpio_cfg_i2s1a;     // same port as SPI1A
+extern const gpio_cfg_t gpio_cfg_i2s1b;     // same port as SPI1B
+
+/***** @brief SWD pins *****/
+extern const gpio_cfg_t gpio_cfg_swd;
+
+/***** @brief RTC pins *****/
+extern const gpio_cfg_t gpio_cfg_rtc;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_PINS_H_ */
+

bsp/maxim/libraries/MAX32660PeriphDriver/Include/mxc_sys.h

@@ -0,0 +1,450 @@
+/**
+ * @file
+ * @brief   System level header file.
+ */
+
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-04-15 09:35:40 -0500 (Mon, 15 Apr 2019) $
+ * $Revision: 42499 $
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_SYS_H_
+#define _MXC_SYS_H_
+
+#include "mxc_config.h"
+#include "uart_regs.h"
+#include "i2c_regs.h"
+#include "gcr_regs.h"
+#include "tmr_regs.h"
+#include "icc_regs.h"
+#include "spi17y_regs.h"
+#include "spimss_regs.h"
+#include "gpio.h"
+#include "flc_regs.h"
+#include "dma.h"
+#include "wdt_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if defined ( __CC_ARM ) /* Suppressing the warning: "enum value is out of range of int" for Keil */
+#pragma push
+#pragma diag_suppress 66
+#endif /* __CC_ARM */
+
+/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */
+typedef enum {
+    SYS_RESET0_DMA       = MXC_F_GCR_RSTR0_DMA,         /**< Reset DMA */
+    SYS_RESET0_WDT       = MXC_F_GCR_RSTR0_WDT,         /**< Reset WDT */
+    SYS_RESET0_GPIO0     = MXC_F_GCR_RSTR0_GPIO0,       /**< Reset GPIO0 */
+    SYS_RESET0_TIMER0    = MXC_F_GCR_RSTR0_TIMER0,      /**< Reset TIMER0 */
+    SYS_RESET0_TIMER1    = MXC_F_GCR_RSTR0_TIMER1,      /**< Reset TIMER1 */
+    SYS_RESET0_TIMER2    = MXC_F_GCR_RSTR0_TIMER2,      /**< Reset TIMER2 */
+    SYS_RESET0_UART0     = MXC_F_GCR_RSTR0_UART0,       /**< Reset UART0 */
+    SYS_RESET0_UART1     = MXC_F_GCR_RSTR0_UART1,       /**< Reset UART1 */
+    SYS_RESET0_SPI0      = MXC_F_GCR_RSTR0_SPI0,        /**< Reset SPI0 */
+    SYS_RESET0_SPI1      = MXC_F_GCR_RSTR0_SPI1,        /**< Reset SPI1 */
+    SYS_RESET0_I2C0      = MXC_F_GCR_RSTR0_I2C0,        /**< Reset I2C0 */
+    SYS_RESET0_RTC       = MXC_F_GCR_RSTR0_RTC,         /**< Reset RTC */
+    SYS_RESET0_SRST      = MXC_F_GCR_RSTR0_SRST,        /**< Soft reset */
+    SYS_RESET0_PRST      = MXC_F_GCR_RSTR0_PRST,        /**< Peripheral reset */
+    SYS_RESET0_SYSTEM    = MXC_F_GCR_RSTR0_SYSTEM,      /**< System reset */
+} sys_reset0_t;
+
+/** @brief System reset1 enumeration. Used in SYS_PeriphReset1 function */
+typedef enum {
+    SYS_RESET1_I2C1      = MXC_F_GCR_RSTR1_I2C1,        /**< Reset I2C1 */
+} sys_reset1_t;
+
+/** @brief System clock disable enumeration. Used in SYS_ClockDisable and SYS_ClockEnable functions */
+typedef enum {
+    SYS_PERIPH_CLOCK_GPIO0   = MXC_F_GCR_PERCKCN0_GPIO0D,     /**< Disable MXC_F_GCR_PERCKCN0_GPIO0D clock */
+    SYS_PERIPH_CLOCK_DMA     = MXC_F_GCR_PERCKCN0_DMAD,       /**< Disable MXC_F_GCR_PERCKCN0_DMAD clock */
+    SYS_PERIPH_CLOCK_SPI17Y  = MXC_F_GCR_PERCKCN0_SPI0D,      /**< Disable MXC_F_GCR_PERCKCN0_SPI0D clock */
+    SYS_PERIPH_CLOCK_SPIMSS  = MXC_F_GCR_PERCKCN0_SPI1D,      /**< Disable MXC_F_GCR_PERCKCN0_SPI1D clock */
+    SYS_PERIPH_CLOCK_UART0   = MXC_F_GCR_PERCKCN0_UART0D,     /**< Disable MXC_F_GCR_PERCKCN0_UART0D clock */
+    SYS_PERIPH_CLOCK_UART1   = MXC_F_GCR_PERCKCN0_UART1D,     /**< Disable MXC_F_GCR_PERCKCN0_UART1D clock */
+    SYS_PERIPH_CLOCK_I2C0    = MXC_F_GCR_PERCKCN0_I2C0D,      /**< Disable MXC_F_GCR_PERCKCN0_I2C0D clock */
+    SYS_PERIPH_CLOCK_T0      = MXC_F_GCR_PERCKCN0_T0D,        /**< Disable MXC_F_GCR_PERCKCN0_T0D clock */
+    SYS_PERIPH_CLOCK_T1      = MXC_F_GCR_PERCKCN0_T1D,        /**< Disable MXC_F_GCR_PERCKCN0_T1D clock */
+    SYS_PERIPH_CLOCK_T2      = MXC_F_GCR_PERCKCN0_T2D,        /**< Disable MXC_F_GCR_PERCKCN0_T2D clock */
+    SYS_PERIPH_CLOCK_I2C1    = MXC_F_GCR_PERCKCN0_I2C1D,      /**< Disable MXC_F_GCR_PERCKCN0_I2C1D clock */
+} sys_periph_clock_t;
+
+/** @brief Clock source */
+typedef enum {
+    SYS_CLOCK_NANORING      = MXC_V_GCR_CLKCN_CLKSEL_NANORING, /**< 8KHz nanoring on MAX32660 */
+    SYS_CLOCK_HFXIN         = MXC_V_GCR_CLKCN_CLKSEL_HFXIN,    /**< 32KHz on MAX32660 */
+    SYS_CLOCK_HFXIN_DIGITAL = 0x9,                             /**< External Clock Input*/
+    SYS_CLOCK_HIRC          = MXC_V_GCR_CLKCN_CLKSEL_HIRC,     /**< High Frequency Internal Oscillator */
+} sys_system_clock_t;
+
+typedef void* sys_cfg_t;
+
+typedef sys_cfg_t sys_cfg_i2c_t;
+typedef sys_cfg_t sys_cfg_flc_t;
+typedef sys_cfg_t sys_cfg_wdt_t;
+
+/** @brief Map control */
+typedef enum {
+    MAP_A,
+    MAP_B,
+    MAP_C,
+} sys_map_t;
+
+/** @brief UART Flow control */
+typedef enum {
+    UART_FLOW_DISABLE,
+    UART_FLOW_ENABLE,
+} sys_uart_flow_t;
+
+/** @brief UART system configuration object */
+typedef struct {
+    sys_map_t map;
+    sys_uart_flow_t flow_flag;
+} sys_cfg_uart_t;
+
+/** @brief SPI17Y system configuration object */
+typedef struct {
+    sys_map_t map;
+} sys_cfg_spi17y_t;
+
+/** @brief SPIMSS system configuration object */
+typedef struct {
+    sys_map_t map;
+} sys_cfg_spimss_t;
+
+/** @brief I2S system configuration object */
+typedef struct {
+    sys_map_t map;
+    dma_reqsel_t dma_reqsel_tx;
+    dma_reqsel_t dma_reqsel_rx;
+} sys_cfg_i2s_t;
+
+/** @brief TIMER system configuration object */ 
+typedef struct {
+   int out_en;
+} sys_cfg_tmr_t;
+
+/** @brief Real Time Clock system configuration object */
+typedef struct {
+    mxc_tmr_regs_t* tmr;
+}  sys_cfg_rtc_t;
+
+
+/** @brief Pulse Train System Configuration Object */
+typedef gpio_cfg_t sys_cfg_pt_t;
+
+#if defined ( __CC_ARM ) /* Restore the warning: "enum is out of int range" for Keil */
+#pragma pop
+#endif /* __CC_ARM */
+/***** Function Prototypes *****/
+/**
+ * @brief      Selects the system clock and enables it once ready
+ * @param      clock   Enumeration for desired clock.
+ * @param      tmr     Optional tmr pointer for timeout. NULL if undesired.
+ *
+ * @returns    #E_NO_ERROR is clock is succesfully selected
+ */
+int SYS_Clock_Select(sys_system_clock_t clock, mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief      Enables the selected peripheral clock.
+ * @param      clock   Enumeration for desired clock.
+ */
+void SYS_ClockEnable(sys_periph_clock_t clock);
+
+/**
+ * @brief      Disables the selected peripheral clock.
+ * @param      clock   Enumeration for desired clock.
+ */
+void SYS_ClockDisable(sys_periph_clock_t clock);
+
+/**
+ * @brief      Enables the external 32k oscillator.
+ * @param      sys_cfg system configuration object
+ *
+ * @returns    #E_NO_ERROR is successful, appropriate error otherwise
+ */
+int SYS_ClockEnable_X32K(sys_cfg_rtc_t *sys_cfg);
+
+/**
+ * @brief      Disables the external 32k oscillator.
+ *
+ * @returns    #E_NO_ERROR is successful, appropriate error otherwise
+ */
+int SYS_ClockDisable_X32K(void);
+
+/**
+ * @brief      System level initialization for UART module.
+ * @param      uart      Pointer to UART module registers
+ * @param      sys_cfg   System configuration object
+ *
+ * @returns    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_UART_Init(mxc_uart_regs_t *uart, const sys_cfg_uart_t* sys_cfg);
+
+/**
+ * @brief      System level shutdown for UART module
+ * @param      uart  Pointer to UART module registers
+ *
+ * @return     #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_UART_Shutdown(mxc_uart_regs_t *uart);
+
+/**
+ * @brief      System level initialization for I2C module.
+ * @param      i2c  Pointer to I2C module registers
+ * @param      sys_cfg  System configuration object
+ * 
+ * @returns    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_I2C_Init(mxc_i2c_regs_t *i2c,  const sys_cfg_i2c_t* sys_cfg);
+
+/**
+ * @brief      System level Shutdown for I2C module.
+ * @param      i2c    Pointer to I2C module registers
+ *
+ * @returns    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_I2C_Shutdown(mxc_i2c_regs_t *i2c);
+
+/**
+ * @brief      Init DMA system settings
+ *
+ * @returns    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_DMA_Init(void);
+
+/**
+ * @brief      Shutdown DMA system specific settings
+ *
+ * @returns    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_DMA_Shutdown(void);
+
+/**
+ * @brief Get the frequency of the I2C module source clock
+ * @param      spim  Unused, pointer to I2C module registers
+ *
+ * @returns    frequency in Hz
+ */
+unsigned SYS_I2C_GetFreq(mxc_i2c_regs_t *i2c);
+
+/**
+ * @brief Get the frequency of the Timer module source clock.
+ * @params     tmr  Unused, pointer to timer module registers
+ *
+ * @returns    frequency in Hz
+ */
+unsigned SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief Reset the peripherals and/or CPU in the rstr0 register.
+ * @param      Enumeration for what to reset. Can reset multiple items at once.
+ */
+void SYS_Reset0(sys_reset0_t reset);
+
+/**
+ * @brief Reset the peripherals and/or CPU in the rstr1 register.
+ * @param      Enumeration for what to reset. Can reset multiple items at once.
+ */
+void SYS_Reset1(sys_reset1_t reset);
+
+/**
+ * @brief Clear Cache and Line buffer.
+ */
+void SYS_Flash_Operation(void);
+
+/**
+ * @brief      Init TMR system settings
+ * @param      tmr Pointer to timer module registers
+ * @param      sys_cfg System configuration object
+ *
+ * @returns    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t* sys_cfg);
+
+/**
+ * @brief      Init flash system settings
+ * @param      sys_cfg System configuration object
+ *
+ * @returns    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_FLC_Init(const sys_cfg_flc_t* sys_cfg);
+
+/**
+ * @brief      Shutdown flash system specific settings
+ *
+ * @returns    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_FLC_Shutdown(void);
+
+/**
+ * @brief System level initialization for SPI17Y module.
+ * @param      spi pointer to spi module registers
+ * @param      sys_cfg System configuration object
+ *
+ * @returns    E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_SPI17Y_Init( mxc_spi17y_regs_t *spi, const sys_cfg_spi17y_t* sys_cfg);
+
+/**
+ * @brief System level shutdown for SPI17Y module
+ * @param      pointer to spi module registers
+ *
+ * @returns    E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_SPI17Y_Shutdown(mxc_spi17y_regs_t *spi);
+
+/**
+ * @brief System level initialization for SPIMSS module.
+ * @param      spi pointer to spi module registers
+ * @param      sys_cfg System configuration object
+ *
+ * @returns    E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_SPIMSS_Init(mxc_spimss_regs_t *spi, const sys_cfg_spimss_t* sys_cfg);
+
+/**
+ * @brief      System level shutdown for SPIMSS module
+ * @param      pointer to spi module registers
+ *
+ * @returns    E_NO_ERROR if everything is successful
+ */
+int SYS_SPIMSS_Shutdown(mxc_spimss_regs_t *spi);
+
+/**
+ * @brief      Shutdown Timer system specific settings
+ * @param      tmr pointer to timer module registers
+ *
+ * @returns    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_TMR_Shutdown(mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief      System level initialization for I2S Module
+ * @param      sys_cfg System configuration object
+ *
+ * @returns    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_I2S_Init(const sys_cfg_i2s_t* sys_cfg);
+
+/**
+ * @brief System level shutdown of I2S module
+ *
+ * @returns    #E_NO_ERROR if everything is successful
+ */
+int SYS_I2S_Shutdown(void);
+
+/**
+ * @brief      Get the frequency of the I2S module source clock
+ * @param      spimss  Pointer to I2S module registers
+ *
+ * @returns    frequency in Hz
+ */
+int SYS_I2S_GetFreq(mxc_spimss_regs_t *spimss);
+
+/**
+ * @brief      Init system settings for RTC square wave output.
+ * @param      sys_cfg  System configuration object
+ *
+ * @returns    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SYS_RTC_SqwavInit(const sys_cfg_rtc_t* sys_cfg);
+
+
+/**
+ * @brief      System Tick Configuration Helper
+ *
+ *             The function enables selection of the external clock source for
+ *             the System Tick Timer. It initializes the System Timer and its
+ *             interrupt, and starts the System Tick Timer. Counter is in free
+ *             running mode to generate periodic interrupts.
+ *
+ * @param      ticks    Number of ticks between two interrupts.
+ * @param      clk_src  Selects between default SystemClock or External Clock.
+ *                      - 0 Use external clock source
+ * @param tmr  Optional tmr pointer for timeout. NULL if undesired.
+ *                      - 1 SystemClock
+ *
+ * @return     #E_NO_ERROR  Function succeeded, of #E_INVALID if an invalid value is requested
+ */
+int SYS_SysTick_Config(uint32_t ticks, int clk_src, mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief      Disable System Tick timer
+ */
+void SYS_SysTick_Disable(void);
+
+/**
+ * @brief      Delay a requested number of SysTick Timer Ticks.
+ * @param      ticks  Number of System Ticks to delay.
+ * @note       This delay function is based on the clock used for the SysTick
+ *             timer if the SysTick timer is enabled. If the SysTick timer is
+ *             not enabled, the current SysTick registers are saved and the
+ *             timer will use the SystemClock as the source for the delay. The
+ *             delay is measured in clock ticks and is not based on the SysTick
+ *             interval.
+ *
+ * @return     #E_NO_ERROR if everything is successful
+ */
+int SYS_SysTick_Delay(uint32_t ticks);
+
+/**
+ * @brief      Get the frequency of the SysTick Timer
+ *
+ * @return     frequency in Hz
+ */
+uint32_t SYS_SysTick_GetFreq(void);
+
+/**
+ * @brief      Delay a requested number of microseconds.
+ * @param      us    Number of microseconds to delay.
+ * @note       Calls SYS_SysTick_Delay().
+ */
+void SYS_SysTick_DelayUs(uint32_t us);
+
+/**
+ * @brief      Init WDT system settings
+ * @param      wdt     watchdog registers
+ * @param      sys_cfg System configuration object
+ */
+int SYS_WDT_Init(mxc_wdt_regs_t* wdt, const sys_cfg_wdt_t* sys_cfg);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_SYS_H_*/
+

bsp/maxim/libraries/MAX32660PeriphDriver/Include/nvic_table.h

@@ -0,0 +1,89 @@
+/**
+ * @file  nvic_table.h
+ * @brief Interrupt vector table manipulation functions.
+ */
+
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2020-04-20 15:48:35 -0500 (Mon, 20 Apr 2020) $
+ * $Revision: 53144 $
+ *
+ ******************************************************************************/
+
+#ifndef _NVIC_TABLE_H
+#define _NVIC_TABLE_H
+
+#include "mxc_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup    syscfg
+ * @defgroup   nvic NVIC Table
+ * @brief      functions handling the nvic table.
+ * @{
+ */ 
+/**
+ * @brief Set an IRQ hander callback function.  If the IRQ table is in
+ * flash, this will copy it to RAM and set NVIC to RAM based table.
+ *
+ * @param irqn          ARM external IRQ number
+ * @param irq_callback  Function to be called at IRQ context
+ *
+ */
+void NVIC_SetVector(IRQn_Type irqn, void (*irq_callback)(void));
+
+/**
+ * @brief Copy NVIC vector table to RAM and set NVIC to RAM based table.
+ *
+ */
+void NVIC_SetRAM(void);
+
+/**
+ * @brief      Get Interrupt Vector
+ * @details    Reads an interrupt vector from interrupt vector table. The
+ *             interrupt number can be positive to specify a device specific
+ *             interrupt, or negative to specify a processor exception.
+ * @param[in]  IRQn  Interrupt number.
+ * @return     Address of interrupt handler function
+ */
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+/**@} end of group nvic */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _NVIC_TABLE_H */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/rtc.h

@@ -0,0 +1,242 @@
+/**
+ * @file
+ * @brief   Real Time Clock (RTC) functions and prototypes.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ * $Date: 2019-10-07 11:05:30 -0500 (Mon, 07 Oct 2019) $
+ * $Revision: 47429 $
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _RTC_H_
+#define _RTC_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+#include "mxc_config.h"
+#include "rtc_regs.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup rtc RTC
+ * @ingroup periphlibs
+ * @{
+ */
+
+/* **** Definitions **** */
+
+typedef enum {
+    SQUARE_WAVE_DISABLED, /**< Sq. wave output disabled */
+    SQUARE_WAVE_ENABLED,  /**< Sq. wave output enabled  */
+} rtc_sqwave_en_t;
+
+typedef enum {
+    F_1HZ   = MXC_S_RTC_CTRL_FT_FREQ1HZ,     /**< 1Hz (Compensated)   */
+    F_512HZ = MXC_S_RTC_CTRL_FT_FREQ512HZ,   /**< 512Hz (Compensated) */
+    F_4KHZ  = MXC_S_RTC_CTRL_FT_FREQ4KHZ,    /**< 4Khz                */
+    F_32KHZ = 32,                          /**< 32Khz               */
+} rtc_freq_sel_t;
+
+typedef enum {
+    NOISE_IMMUNE_MODE        = MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE,
+    QUIET_MODE               = MXC_S_RTC_CTRL_X32KMD_QUIETMODE,
+    QUIET_STOP_WARMUP_MODE   = MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP,
+    QUIET_STOP_NOWARMUP_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP,
+} rtc_osc_mode_t;
+
+/**
+ *@brief     Enables Time-of-Day's Alarm Interrupt
+ *@param     rtc    pointer to the rtc register structure
+ *@return    #E_SUCCESS=pass
+ *@return    #E_BAD_STATE=fail
+ *@return    #E_BUSY=Fail
+ */
+int RTC_EnableTimeofdayInterrupt(mxc_rtc_regs_t *rtc);
+
+/**
+ *@brief     Disable Time-of-Day's Alarm Interrupt
+ *@param     rtc    pointer to the rtc register structure
+ *@return    #E_SUCCESS=pass
+ *@return    #E_BAD_STATE=fail
+ *@return    #E_BUSY=Fail
+ */
+int RTC_DisableTimeofdayInterrupt(mxc_rtc_regs_t *rtc);
+
+/**
+ *@brief     Enables Sub-Second's Alarm Interrupt
+ *@param     rtc    pointer to the rtc register structure
+ *@return    #E_SUCCESS=pass
+ *@return    #E_BAD_STATE=fail
+ *@return    #E_BUSY=Fail
+ */
+int RTC_EnableSubsecondInterrupt(mxc_rtc_regs_t *rtc);
+
+/**
+ *@brief     Disable Sub-Second's Alarm Interrupt
+ *@param     rtc    pointer to the rtc register structure
+ *@return    #E_SUCCESS=pass
+ *@return    #E_BAD_STATE=fail
+ *@return    #E_BUSY=Fail
+ */
+int RTC_DisableSubsecondInterrupt(mxc_rtc_regs_t *rtc);
+
+/**
+ *@brief     Set Time-of-Day alarm value and enable Interrupt
+ *@param     rtc    pointer to the rtc register structure
+ *@param     ras    20-bit value 0-0xFFFFF
+ *@return    #E_SUCCESS=pass
+ *@return    #E_BAD_STATE=fail
+ *@return    #E_BUSY=Fail
+ */
+int RTC_SetTimeofdayAlarm(mxc_rtc_regs_t *rtc, uint32_t ras);
+
+/**
+ *@brief     Set Sub-Second alarm value and enable interrupt,
+ *@brief     this is to be called after the init_rtc() function
+ *@param     rtc    pointer to the rtc register structure
+ *@param     rssa   32-bit value 0-0xFFFFFFFF
+ *@return    #E_SUCCESS=pass
+ *@return    #E_BAD_STATE=fail
+ *@return    #E_BUSY=Fail
+ */
+int RTC_SetSubsecondAlarm(mxc_rtc_regs_t *rtc, uint32_t rssa);
+
+/**
+ *@brief     Enable/Start the Real Time Clock
+ *@param     rtc    pointer to the rtc register structure
+ *@return    #E_SUCCESS=Pass
+ *@return    #E_BUSY=Fail
+ */
+int RTC_EnableRTCE(mxc_rtc_regs_t *rtc);
+
+/**
+ *@brief     Disable/Stop the Real Time Clock
+ *@param     rtc    pointer to the rtc register structure
+ *@return    #E_SUCCESS=Pass
+ *@return    #E_BUSY=Fail
+ */
+int RTC_DisableRTCE(mxc_rtc_regs_t *rtc);
+
+/**
+ * @brief Initialize the sec and ssec registers and enable RTC
+ * @param      rtc pointer to the rtc register structure
+ * @param      sec set the RTC Sec counter (32-bit)
+ * @param      ssec set the RTC Sub-second counter (8-bit)
+ * @param      sys_cfg The system configuration
+ * @return #E_SUCCESS=pass
+ * @return #E_BAD_STATE=fail
+ */
+int RTC_Init(mxc_rtc_regs_t *rtc, uint32_t sec, uint8_t ssec, sys_cfg_rtc_t *sys_cfg);
+
+/**
+ * @brief Allow generation of Square Wave on the SQW pin
+ * @param      rtc pointer to the rtc register structure
+ * @param      sqe Enable/Disable square wave output
+ * @param      ft Frequency output selection
+ * @param      x32kmd 32KHz Oscillator mode
+ * @param      sys_cfg The system configuration
+ * @return #E_SUCCESS=Pass
+ * @return #E_BUSY=Fail
+ */
+int RTC_SquareWave(mxc_rtc_regs_t *rtc, rtc_sqwave_en_t sqe, rtc_freq_sel_t ft,
+                   rtc_osc_mode_t x32kmd, const sys_cfg_rtc_t* sys_cfg);
+
+/**
+ *@brief     Set Trim register value
+ *@param     rtc    pointer to the rtc register structure
+ *@param     trm    set the RTC Trim (8-bit, +/- 127)
+ *@return    #E_SUCCESS=Pass
+ *@return    #E_BUSY=Fail
+ */
+int RTC_Trim(mxc_rtc_regs_t *rtc, int8_t trm);
+
+/**
+ *@brief     Check if BUSY bit is 0.
+ *@return    #E_SUCCESS=Pass
+ *@return    #E_BUSY=Fail
+ */
+int RTC_CheckBusy(void);
+
+/**
+ *@brief     Gets Interrupt flags.
+ *@return    Interrupts flags that have not been cleared
+ */
+int RTC_GetFlags(void);
+
+/**
+ *@brief     Clear Interrupt flag.
+ *@param     flags the flags that need to be cleared
+ */
+int RTC_ClearFlags(int flags);
+
+/**
+ *@brief     Get SubSecond
+ *@return    Returns subsecond value
+ */
+int RTC_GetSubSecond(void);
+
+/**
+ * @brief Get Second
+ * @return returns Second value
+ */
+int RTC_GetSecond(void);
+
+/**
+ * @brief Read seconds, then subseconds, and finally seconds.  If RTC ready flag ever gets cleared during this sequence,
+   the RTC is in the middle of updating the counts and the user should come back later and try again.  If the first
+   read of the seconds register doesn't match the next read, then a subsecond overflow condition has happened and
+   another attempt to read the counts should be made.
+ * @param      sec    variable that will be changed to hold second value
+ * @param      subsec variable that will be changed to hold Subsecond value
+ * @return    #E_NO_ERROR=Pass
+ * @return    #E_BUSY=Fail
+ */
+int RTC_GetTime(uint32_t* sec, uint32_t* subsec);
+
+/**
+ *@brief    Check if RTC is already running
+ */
+int RTC_IsEnabled(void);
+
+#ifdef __cplusplus
+}
+#endif
+/**@} end of group rtc */
+
+#endif /* _RTC_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/spi.h

@@ -0,0 +1,259 @@
+ /**
+ * @file    spi.h
+ * @brief   Serial Peripheral Interface (SPIMSS) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-11-07 14:48:15 -0600 (Wed, 07 Nov 2018) $
+ * $Revision: 39010 $
+ *
+ *************************************************************************** */
+  
+/* Define to prevent redundant inclusion */ 
+#ifndef _SPI_H_
+#define _SPI_H_
+
+/* **** Includes **** */
+#include "spi17y_regs.h"
+#include "spimss_regs.h"
+#include "spimss.h"
+#include "spi17y.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup spi SPI
+ * @ingroup periphlibs
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * @brief Enums assigning numbers to SPI
+ */
+typedef enum {
+     SPI0A,   // SPI17Y (0A)
+     SPI1A,   // SPIMSS (1A)
+     SPI1B,   // SPIMSS (1B)
+}spi_type;
+
+
+/**
+ * @brief Renaming the SPI address names
+ */
+#define MXC_SPI0   MXC_SPI17Y   // SPI0A
+#define MXC_SPI1   MXC_SPIMSS   // SPI1A & SPI1B
+
+
+/**
+ * @brief Renaming Interrupt SPI Interrupt sources
+ */
+#define SPI0_IRQn SPI17Y_IRQn  // SPI0A
+#define SPI1_IRQn SPIMSS_IRQn  // SPI1A & SPI1B
+
+
+/**
+ * @brief Renaming SPI Width
+ */
+#define SPI0_WIDTH_1  SPI17Y_WIDTH_1  /**< 1 Data Line.       */
+#define SPI0_WIDTH_2  SPI17Y_WIDTH_2  /**< 2 Data Lines (x2). */
+#define SPI0_WIDTH_4  SPI17Y_WIDTH_4  /**< 4 Data Lines (x4). */
+
+/**
+ * @brief Renaming SPI Polarity
+ */
+#define SPI_POL_LOW   SPI17Y_POL_LOW    /**< Slave Select polarity Low.  */
+#define SPI_POL_HIGH  SPI17Y_POL_HIGH   /**< Slave Select polarity High. */
+
+/**
+ * @brief Structure type representing a SPI Master Transaction request.
+ */
+typedef struct spi_req spi_req_t;
+
+/**
+ * @brief Callback function type used in asynchronous SPI Master communication requests.
+ * @details The function declaration for the SPI Master callback is:
+ * @code
+ * void callback(spi_req_t * req, int error_code);
+ * @endcode
+ * |        |                                            |
+ * | -----: | :----------------------------------------- |
+ * | \p req |  Pointer to a #spi_req object representing the active SPI Master active transaction. |
+ * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
+ * @note Callback will execute in interrupt context
+ * @addtogroup spi_async
+ */
+typedef void (*spi_callback_fn)(void * req, int error_code);
+
+/**
+ * @brief      Structure definition for an SPI Master Transaction request.
+ * @note       When using this structure for an asynchronous operation, the
+ *             structure must remain allocated until the callback is completed.
+ * @addtogroup spi_async
+ */
+struct spi_req {
+    uint8_t         ssel;       /**< Slave select line to use. (Master only) */
+    uint8_t         deass;      /**< Non-zero to de-assert slave select after transaction. (Master only)*/
+    spi17y_sspol_t  ssel_pol;   /**< Slave select line polarity. */
+    const void      *tx_data;   /**< Pointer to a buffer to transmit data from. NULL if undesired. */
+    void            *rx_data;   /**< Pointer to a buffer to store data received. NULL if undesired.*/
+    spi17y_width_t  width;      /**< Number of data lines to use, see #spi17y_width_t. */
+    unsigned        len;        /**< Number of transfer units to send from the \p tx_data buffer. */
+    unsigned        bits;       /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
+    unsigned        rx_num;     /**< Number of bytes actually read into the \p rx_data buffer. */
+    unsigned        tx_num;     /**< Number of bytes actually sent from the \p tx_data buffer */
+    spi_callback_fn    callback;   /**< Callback function if desired, NULL otherwise */
+};
+
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief     Initialize the spi.
+ * @param     spi_name spi module to initialize.
+ * @param     mode     SPI mode for clock phase and polarity.
+ * @param     freq     Desired clock frequency.
+ *
+ * @return    #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI_Init(spi_type spi_name, unsigned mode, unsigned freq);
+
+/**
+ * @brief      Asynchronously read/write SPI Master data
+ *
+ * @param      spi_name  SPI instance being used
+ * @param      req   Pointer to spi request
+ *
+ * @return     #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI_MasterTransAsync(spi_type spi_name, spi_req_t *req);
+
+/**
+ * @brief     Execute a master transaction.
+ * @param     spi_name  SPI instance being used
+ * @param     req   Pointer to spi request
+ *
+ * @return    #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI_MasterTrans(spi_type spi_name, spi_req_t *req);
+
+/**
+ * @brief      Asynchronously read/write SPI Slave data
+ * @param      spi_name  SPI instance being used
+ * @param      req   Pointer to spi request
+ *
+ * @return    #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI_SlaveTransAsync(spi_type spi_name, spi_req_t *req);
+
+/**
+ * @brief     Execute a slave transaction.
+ * @param     spi_name  SPI instance being used
+ * @param     req   Pointer to spi request
+ *
+ * @return    #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI_SlaveTrans(spi_type spi_name, spi_req_t *req);
+
+/**
+ * @brief     Shutdown SPI module.
+ * @param     spi_name  SPI instance being used
+ *
+ * @return    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SPI_Shutdown(spi_type spi_name);
+
+
+/**
+ * @brief      Aborts an Asynchronous request
+ * @param      spi_name  SPI instance being used
+ * @param      req   Pointer to spi request
+ *
+ * @return     #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI_AbortAsync(spi_type spi_name, spi_req_t *req);
+
+/**
+ * @brief      Execute SPI transaction based on interrupt handler
+ * @param      spi_name  SPI instance being used
+ *
+ * @return     #E_NO_ERROR if successful, 
+ * @return     #E_BAD_PARAM otherwise
+ */
+int SPI_Handler(spi_type spi_name);
+
+/**
+ * @brief     Enable SPI
+ * @param     spi_name  Pointer to spi module.
+ *
+ * @return    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SPI_Enable(spi_type spi_name);
+
+/**
+ * @brief     Disable SPI
+ * @param     spi_name  Pointer to spi module.
+ *
+ * @return    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SPI_Disable(spi_type spi_name);
+
+/**
+ * @brief     Clear the TX and RX FIFO
+ * @param     spi_name  Pointer to spi module.
+ *
+ * @return    #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SPI_Clear_fifo(spi_type spi_name);
+
+//-------------------------------------------------------------------------------------------
+/**@} end of group spi */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SPI_H_ */
+
+
+

bsp/maxim/libraries/MAX32660PeriphDriver/Include/spi17y.h

@@ -0,0 +1,242 @@
+/**
+ * @file    spi17y.h
+ * @brief   Serial Peripheral Interface (SPI17Y) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _SPI17Y_H_
+#define _SPI17Y_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "spi17y_regs.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup spi17y SPI17Y
+ * @ingroup spi
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/** 
+ * Enumeration type for setting the number data lines to use for communication. 
+ */
+typedef enum {
+    SPI17Y_WIDTH_1 = 0,  /**< 1 Data Line.                        */
+    SPI17Y_WIDTH_2 = 1,  /**< 2 Data Lines (x2).                  */
+    SPI17Y_WIDTH_4 = 2   /**< 4 Data Lines (x4).                  */
+} spi17y_width_t;
+
+/** 
+ * Enumeration type for setting the polarity of ss lines. 
+ */
+typedef enum {
+    SPI17Y_POL_LOW  = 0, /**< Polarity Low.                        */
+    SPI17Y_POL_HIGH = 1  /**< Polarity High.                  */
+} spi17y_sspol_t;
+
+/** 
+ * Structure type representing a SPI17Y Master Transaction request.
+ */
+typedef struct spi17y_req spi17y_req_t;
+
+
+/**
+ * @brief Callback function type used in asynchronous SPI Master communication requests.
+ * @details The function declaration for the SPI Master callback is:
+ * @code 
+ * void callback(spi17y_req_t * req, int error_code);
+ * @endcode
+ * |        |                                            |
+ * | -----: | :----------------------------------------- |
+ * | \p req |  Pointer to a #spi_req object representing the active SPI Master active transaction. |
+ * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
+ * @note Callback will execute in interrupt context
+ * @addtogroup spi_async
+ */
+typedef void (*spi17y_callback_fn)(spi17y_req_t * req, int error_code);
+
+/**
+ * @brief      Structure definition for an SPI Master Transaction request.
+ * @note       When using this structure for an asynchronous operation, the
+ *             structure must remain allocated until the callback is completed.
+ * @addtogroup spi_async
+ */
+struct spi17y_req {
+    uint8_t            ssel;       /**< Slave select line to use. (Master only, ignored in slave mode) */
+    uint8_t            deass;      /**< Non-zero to de-assert slave select after transaction. (Master only, ignored in slave mode)*/
+    spi17y_sspol_t     ssel_pol;   /**< Slave select line polarity. */
+    const void         *tx_data;   /**< Pointer to a buffer to transmit data from. NULL if undesired. */
+    void               *rx_data;   /**< Pointer to a buffer to store data received. NULL if undesired.*/
+    spi17y_width_t     width;      /**< Number of data lines to use, see #spi17y_width_t. */
+    unsigned           len;        /**< Number of transfer units to send from the \p tx_data buffer. */
+    unsigned           bits;       /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
+    unsigned           rx_num;     /**< Number of bytes actually read into the \p rx_data buffer. */
+    unsigned           tx_num;     /**< Number of bytes actually sent from the \p tx_data buffer */
+    spi17y_callback_fn    callback;   /**< Callback function if desired, NULL otherwise */
+};
+
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief     Initialize the spi.
+ * @param     spi     Pointer to spi module to initialize.
+ * @param     mode    SPI mode for clock phase and polarity.
+ * @param     freq    Desired clock frequency.
+ * @param     sys_cfg System configuration object
+ *
+ * @return     #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI17Y_Init(mxc_spi17y_regs_t *spi, unsigned int mode, unsigned int freq, const sys_cfg_spi17y_t* sys_cfg);
+
+/**
+ * @brief      Shutdown SPI module.
+ * @param      spi  Pointer to SPI regs.
+ * 
+ * @return     #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI17Y_Shutdown(mxc_spi17y_regs_t *spi);
+
+/**
+ * @brief     Processing function for asynchronous SPI operations.  
+ *            This function must be called either from the SPI interrupt 
+ *            handler or periodically.
+ *
+ * @param     spi   Pointer to spi module.
+ */
+void SPI17Y_Handler(mxc_spi17y_regs_t *spi);
+
+/**
+ * @brief     Execute a master transaction.
+ *            This function will block until the transaction is complete.
+ * @param     spi   Pointer to spi module.
+ * @param     req   Pointer to spi request
+ * 
+ * @return     #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI17Y_MasterTrans(mxc_spi17y_regs_t *spi, spi17y_req_t *req);
+
+/**
+ * @brief     Execute a slave transaction.
+ *            This function will block until the transaction is complete.
+ * @param     spi   Pointer to spi module.
+ * @param     req   Pointer to spi request
+ * 
+ * @return     #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI17Y_SlaveTrans(mxc_spi17y_regs_t *spi, spi17y_req_t *req);
+
+/**
+ * @brief      Asynchronously read/write SPI Master data
+ *
+ * @param      spi   Pointer to spi module
+ * @param      req   Pointer to spi request
+ *
+ * @return     #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI17Y_MasterTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req);
+
+/**
+ * @brief      Asynchronously read/write SPI Slave data
+ *
+ * @param      spi   Pointer to spi module
+ * @param      req   Pointer to spi request
+ *
+ * @return     #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI17Y_SlaveTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req);
+
+/**
+ * @brief      Aborts an Asynchronous request
+ *
+ * @param      req   Pointer to spi request
+ * @return     #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPI17Y_AbortAsync(spi17y_req_t *req);
+
+/**
+ * @brief     Enable SPI
+ * @param     spi  Pointer to spi module.
+ *
+ * @return     #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+void SPI17Y_Enable(mxc_spi17y_regs_t* spi);
+
+/**
+ * @brief     Disable SPI.  Any pending asynchronous transactions will not
+ *            complete and their callbacks will not be executed.
+ * @param     spi  Pointer to spi module.
+ *
+ * @return     #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+void SPI17Y_Disable(mxc_spi17y_regs_t* spi);
+
+/**
+ * @brief     Clear the TX and RX FIFO
+ * @param     spi  Pointer to spi module.
+ *
+ * @return     #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+void SPI17Y_Clear_fifo(mxc_spi17y_regs_t* spi);
+
+
+/**@} end of group spi17y */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SPI17Y_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/spimss.h

@@ -0,0 +1,197 @@
+/**
+ * @file    spimss.h
+ * @brief   Serial Peripheral Interface (SPIMSS) function prototypes and data types.
+ */ 
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ *************************************************************************** */
+ 
+/* Define to prevent redundant inclusion */
+#ifndef _SPIMSS_H_
+#define _SPIMSS_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "mxc_sys.h"
+#include "spimss_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup spimss SPIMSS
+ * @ingroup spi
+ * @{
+ */
+
+/* **** Definitions **** */
+
+
+/** 
+ * @brief Enumeration type for setting the number data lines to use for communication.
+ */
+typedef enum {  // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED
+    DUMMY_1,    /**< NOT USED                */
+    DUMMY_2,    /**< NOT USED                */
+    DUMMY_3,    /**< NOT USED                */
+} spimss_width_t;
+
+/**
+ * @brief Structure type representing a SPI Master Transaction request.
+ */
+typedef struct spimss_req spimss_req_t;
+
+/**
+ * @brief Callback function type used in asynchronous SPI Master communication requests.
+ * @details The function declaration for the SPI Master callback is:
+ * @code 
+ * void callback(spi_req_t * req, int error_code);
+ * @endcode
+ * |        |                                            |
+ * | -----: | :----------------------------------------- |
+ * | \p req |  Pointer to a #spi_req object representing the active SPI Master active transaction. |
+ * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
+ * @note Callback will execute in interrupt context
+ * @addtogroup spi_async
+ */
+typedef void (*spimss_callback_fn)(spimss_req_t * req, int error_code);
+
+/**
+ * @brief      Structure definition for an SPI Master Transaction request.
+ * @note       When using this structure for an asynchronous operation, the
+ *             structure must remain allocated until the callback is completed.
+ * @addtogroup spi_async
+ */
+struct spimss_req {
+    uint8_t            ssel;       /**< Not Used*/
+    uint8_t            deass;      /**< Not Used*/
+    const void         *tx_data;   /**< Pointer to a buffer to transmit data from. NULL if undesired. */
+    void               *rx_data;   /**< Pointer to a buffer to store data received. NULL if undesired.*/
+    spimss_width_t     width;      /**< Not Used */
+    unsigned           len;        /**< Number of transfer units to send from the \p tx_data buffer. */
+    unsigned           bits;       /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
+    unsigned           rx_num;     /**< Number of bytes actually read into the \p rx_data buffer. */
+    unsigned           tx_num;     /**< Number of bytes actually sent from the \p tx_data buffer */
+    spimss_callback_fn callback;   /**< Callback function if desired, NULL otherwise */
+};
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief     Initialize the spi.
+ * @param     spi     Pointer to spi module to initialize.
+ * @param     mode    SPI mode for clock phase and polarity.
+ * @param     freq    Desired clock frequency.
+ * @param     sys_cfg System configuration object
+ *
+ * @return \c #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_cfg_spimss_t* sys_cfg);
+
+/**
+ * @brief      Shutdown SPI module.
+ * @param      spi  Pointer to SPI regs.
+ * 
+ * @return  \c #E_NO_ERROR if successful, appropriate error otherwise
+ */
+int SPIMSS_Shutdown(mxc_spimss_regs_t *spi);
+
+/**
+ * @brief     Execute a master transaction.
+ * @param     spi   Pointer to spi module.
+ * @param     req   Pointer to spi request
+ * 
+ * @return  \c #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, spimss_req_t *req);
+
+/**
+ * @brief      Execute SPI transaction based on interrupt handler
+ * @param      spi   The spi
+ *
+ */
+void SPIMSS_Handler(mxc_spimss_regs_t *spi);
+
+/**
+ * @brief     Execute a slave transaction.
+ * @param     spi   Pointer to spi module.
+ * @param     req   Pointer to spi request
+ * 
+ * @return  \c #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, spimss_req_t *req);
+
+/**
+ * @brief      Asynchronously read/write SPI Master data
+ *
+ * @param      spi   Pointer to spi module
+ * @param      req   Pointer to spi request
+ *
+ * @return  \c #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req);
+
+/**
+ * @brief      Asynchronously read/write SPI Slave data
+ *
+ * @param      spi   Pointer to spi module
+ * @param      req   Pointer to spi request
+ *
+ * @return  \c #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req);
+
+/**
+ * @brief      Aborts an Asynchronous request
+ *
+ * @param      req   Pointer to spi request
+ * @return  \c #E_NO_ERROR if successful, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPIMSS_AbortAsync(spimss_req_t *req);
+
+/**@} end of group spimss */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SPIMSS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/tmr.h

@@ -0,0 +1,265 @@
+/**
+ * @file    tmr.h
+ * @brief   Timer (TMR) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-09-11 14:32:22 -0500 (Wed, 11 Sep 2019) $
+ * $Revision: 46047 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _TMR_H_
+#define _TMR_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "tmr_regs.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup tmr Timer (TMR)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/**
+ * @brief Timer prescaler values
+ */
+typedef enum {
+    TMR_PRES_1      = MXC_S_TMR_CN_PRES_DIV1,           /// Divide input clock by 1
+    TMR_PRES_2      = MXC_S_TMR_CN_PRES_DIV2,           /// Divide input clock by 2
+    TMR_PRES_4      = MXC_S_TMR_CN_PRES_DIV4,           /// Divide input clock by 4
+    TMR_PRES_8      = MXC_S_TMR_CN_PRES_DIV8,           /// Divide input clock by 8
+    TMR_PRES_16     = MXC_S_TMR_CN_PRES_DIV16,          /// Divide input clock by 16
+    TMR_PRES_32     = MXC_S_TMR_CN_PRES_DIV32,          /// Divide input clock by 32
+    TMR_PRES_64     = MXC_S_TMR_CN_PRES_DIV64,          /// Divide input clock by 64
+    TMR_PRES_128    = MXC_S_TMR_CN_PRES_DIV128,         /// Divide input clock by 128
+    TMR_PRES_256    = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV1,  /// Divide input clock by 256
+    TMR_PRES_512    = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV2,  /// Divide input clock by 512
+    TMR_PRES_1024   = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV4,  /// Divide input clock by 1024
+    TMR_PRES_2048   = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV8,  /// Divide input clock by 2048
+    TMR_PRES_4096   = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV16  /// Divide input clock by 4096
+} tmr_pres_t;
+
+/**
+ * @brief Timer modes
+ */
+typedef enum {
+    TMR_MODE_ONESHOT          = MXC_V_TMR_CN_TMODE_ONESHOT,       /// Timer Mode ONESHOT
+    TMR_MODE_CONTINUOUS       = MXC_V_TMR_CN_TMODE_CONTINUOUS,    /// Timer Mode CONTINUOUS
+    TMR_MODE_COUNTER          = MXC_V_TMR_CN_TMODE_COUNTER,       /// Timer Mode COUNTER
+    TMR_MODE_PWM              = MXC_V_TMR_CN_TMODE_PWM,           /// Timer Mode PWM
+    TMR_MODE_CAPTURE          = MXC_V_TMR_CN_TMODE_CAPTURE,       /// Timer Mode CAPTURE
+    TMR_MODE_COMPARE          = MXC_V_TMR_CN_TMODE_COMPARE,       /// Timer Mode COMPARE
+    TMR_MODE_GATED            = MXC_V_TMR_CN_TMODE_GATED,         /// Timer Mode GATED
+    TMR_MODE_CAPTURE_COMPARE  = MXC_V_TMR_CN_TMODE_CAPTURECOMPARE /// Timer Mode CAPTURECOMPARE
+} tmr_mode_t;
+
+/**
+ * @brief Timer units of time enumeration
+ */
+typedef enum {
+    TMR_UNIT_NANOSEC = 0,       /**< Nanosecond Unit Indicator. */
+    TMR_UNIT_MICROSEC,          /**< Microsecond Unit Indicator. */
+    TMR_UNIT_MILLISEC,          /**< Millisecond Unit Indicator. */
+    TMR_UNIT_SEC,               /**< Second Unit Indicator. */
+} tmr_unit_t;
+
+/**
+ * @brief Timer Configuration
+ */
+typedef struct {
+    tmr_mode_t mode;    /// Desired timer mode
+    uint32_t cmp_cnt;   /// Compare register value in timer ticks
+    unsigned pol;       /// Polarity (0 or 1)
+} tmr_cfg_t;
+
+/**
+ * @brief Timer PWM Configuration
+ */
+typedef struct {
+    unsigned pol;       /// PWM polarity (0 or 1)
+    uint32_t per_cnt;   /// PWM period in timer ticks
+    uint32_t duty_cnt;  /// PWM duty in timer ticks
+} tmr_pwm_cfg_t;
+
+/* **** Definitions **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Initialize timer module clock.
+ * @param      tmr        Pointer to timer module to initialize.
+ * @param      pres       Prescaler value.
+ * @param      sys_cfg    System configuration object
+ * @return     #E_NO_ERROR if successful, error code otherwise.
+ */
+int TMR_Init(mxc_tmr_regs_t *tmr, tmr_pres_t pres, const sys_cfg_tmr_t* sys_cfg);
+
+/**
+ * @brief      Shutdown timer module clock.
+ * @param      tmr  Pointer to timer module to initialize.
+ * @return     #E_NO_ERROR if successful, error code otherwise.
+ */
+int TMR_Shutdown(mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief      Enable the timer.
+ * @param      tmr  Pointer to timer module to initialize.
+ */
+void TMR_Enable(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief      Disable the timer.
+ * @param      tmr  Pointer to timer module to initialize.
+ */
+void TMR_Disable(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief      Configure the timer.
+ * @param      tmr  Pointer to timer module to initialize.
+ * @param      cfg  Pointer to timer configuration struct.
+ * @return     #E_NO_ERROR if successful.
+ */
+int TMR_Config(mxc_tmr_regs_t *tmr, const tmr_cfg_t *cfg);
+
+/**
+ * @brief   Configure the timer for PWM operation.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @param   cfg     Pointer to timer PWM configuration struct.
+ * @note    Can cause a glitch if the Timer is currently running.
+ * @return  #E_BAD_PARAM if duty_cnt > per_cnt.
+ */
+int TMR_PWMConfig(mxc_tmr_regs_t *tmr, const tmr_pwm_cfg_t *cfg);
+
+/**
+ * @brief   Set the timer duty cycle.
+ * @param   tmr     Pointer to timer module to initialize
+ * @param   duty    New duty cycle count
+ * @note    Will block until safe to change the duty count.
+ * @return  #E_BAD_PARAM if duty_cnt > per_cnt.
+ */
+int TMR_PWMSetDuty(mxc_tmr_regs_t *tmr, uint32_t duty);
+
+/**
+ * @brief   Set the timer period.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @param   per     New period count.
+ * @note    Will block until safe to change the period count.
+ * @return  #E_BAD_PARAM if duty_cnt > per_cnt.
+ */
+int TMR_PWMSetPeriod(mxc_tmr_regs_t* tmr, uint32_t per);
+
+/**
+ * @brief   Get the timer compare count.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @return  Returns the current compare count.
+ */
+uint32_t TMR_GetCompare(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   Get the timer capture count.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @return  Returns the most recent capture count.
+ */
+uint32_t TMR_GetCapture(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   Get the timer count.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @return  Returns the current count.
+ */
+uint32_t TMR_GetCount(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   Clear the timer interrupt.
+ * @param   tmr     Pointer to timer module to initialize.
+ */
+void TMR_IntClear(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   Get the timer interrupt status.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @return  Returns the interrupt status. 1 if interrupt has occurred.
+ */
+uint32_t TMR_IntStatus(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief   Set the timer compare count.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @param   cmp_cnt New compare count.
+ * @note    This function does not protect against output glitches in PWM mode.
+ *          Use TMR_PWMSetPeriod when in PWM mode.
+ */
+void TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt);
+
+/**
+ * @brief   Set the timer count.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @param   cnt     New count.
+ */
+void TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt);
+
+/**
+ * @brief   Convert real time to timer ticks.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @param   time    Number of units of time.
+ * @param   units   Which units of time you want to convert.
+ * @param   ticks   Pointer to store the number of ticks calculated.
+ * @return  #E_NO_ERROR if successful, error code otherwise.
+ */
+int TMR_GetTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint32_t *ticks);
+
+/**
+ * @brief   Convert timer ticks to real time.
+ * @param   tmr     Pointer to timer module to initialize.
+ * @param   ticks   Number of ticks.
+ * @param   time    Pointer to store number of units of time.
+ * @param   units   Pointer to store the units that time represents.
+ * @return  #E_NO_ERROR if successful, error code otherwise.
+ */
+int TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, tmr_unit_t *units);
+
+/**@} end of group tmr */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TMR_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/tmr_utils.h

@@ -0,0 +1,146 @@
+/**
+ * @file       tmr_utils.h
+ * @brief      Timer utility function declarations
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-10-17 14:16:30 -0500 (Wed, 17 Oct 2018) $
+ * $Revision: 38560 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _TMR_UTILS_H
+#define _TMR_UTILS_H
+
+/***** Includes *****/
+#include "mxc_config.h"
+#include "tmr_regs.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup tmr
+ * @defgroup tmr_utils Timer Utility Functions
+ * @{
+ */
+ 
+/* **** Definitions **** */
+
+/** @def Macro to convert the parameter \p s from seconds to micro-seconds. */
+#define SEC(s)            (((unsigned long)s) * 1000000UL) 
+
+/** @def Macro to convert the parameter \p ms from milli-seconds to micro-seconds. */
+#define MSEC(ms)          (ms * 1000UL)
+
+/** @def Macro to convert the parameter \p us to micro-seconds. */
+#define USEC(us)          (us)
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Delays for the specified number of microseconds.
+ * @param      tmr   Which Timer instance to use
+ * @param      us    Number of microseconds to delay.
+ * @param      sys_cfg  System configuration object, identical to TMR_Init()
+ */
+void TMR_Delay(mxc_tmr_regs_t *tmr, unsigned long us, const sys_cfg_tmr_t *sys_cfg);
+
+/**
+ * @brief      Start the timeout time for the specified number of microseconds.
+ * @param      tmr     Which Timer instance to use
+ * @param      us      Number of microseconds in the timeout.
+ * @param      sys_cfg  System configuration object, identical to TMR_Init()
+ */
+void TMR_TO_Start(mxc_tmr_regs_t *tmr, unsigned long us, const sys_cfg_tmr_t *sys_cfg);
+
+/**
+ * @brief      Check if the timeout has occurred.
+ * @param      tmr   Which Timer instance to use
+ * @return     #E_NO_ERROR if the timeout has not occurred, #E_TIME_OUT if it has.
+ */
+int TMR_TO_Check(mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief      Stops the timer for the timeout.
+ * @param      tmr   Which Timer instance to use
+ */
+void TMR_TO_Stop(mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief      Clears the timeout flag.
+ * @param      tmr   Which Timer instance to use
+ */
+void TMR_TO_Clear(mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief      Get the number of microseconds elapsed since TMR_TO_Start().
+ * @param      tmr   Which Timer instance to use
+ * @return     Number of microseconds since TMR_TO_Start().
+ */
+unsigned int TMR_TO_Elapsed(mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief      Get the number of microseconds remaining in the timeout.
+ * @param      tmr   Which Timer instance to use
+ * @return     Number of microseconds until timeout.
+ */
+unsigned int TMR_TO_Remaining(mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief      Start the stopwatch.
+ * @note 	   This function does not handle overflows
+ * @param      tmr   Which Timer to use
+ * @param      sys_cfg  System configuration object, identical to TMR_Init()
+ */
+void TMR_SW_Start(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t *sys_cfg);
+
+/**
+ * @brief      Stop the stopwatch and return the number of microseconds that
+ *             have elapsed.
+ * @note 	   This function does not handle overflows
+ * @param      tmr   Which Timer instance to use
+ * @return     Number of microseconds since TMR_SW_Start().
+ */
+unsigned int TMR_SW_Stop(mxc_tmr_regs_t *tmr);
+  
+/**@} end of defgroup tmr_utils*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TMR_UTILS_H */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/uart.h

@@ -0,0 +1,364 @@
+/**
+ * @file
+ * @brief   This files defines the driver API including definitions, data types
+ *          and function prototypes.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-10-07 11:05:30 -0500 (Mon, 07 Oct 2019) $
+ * $Revision: 47429 $
+ *
+ *************************************************************************** */
+
+
+#ifndef _UART_H_
+#define _UART_H_
+
+/***** Includes *****/
+#include <stdint.h>
+#include "uart_regs.h"
+#include "mxc_sys.h"
+
+/***** Definitions *****/
+
+/**
+ * @brief      Alternate clock rate. (7.3728MHz) */
+#define UART_ALTERNATE_CLOCK_HZ 7372800
+/**
+ * @defgroup uart UART
+ * @ingroup periphlibs
+ * @{
+ */
+/**
+ * @brief Parity settings type */
+typedef enum {
+    UART_PARITY_DISABLE = 0,                                /**< Parity disabled */
+    UART_PARITY_EVEN_0  = (MXC_F_UART_CTRL_PARITY_EN |
+                           MXC_S_UART_CTRL_PARITY_EVEN |
+                           MXC_F_UART_CTRL_PARMD),          /**< Use for even parity 0 */
+    UART_PARITY_EVEN_1  = (MXC_F_UART_CTRL_PARITY_EN |
+                           MXC_S_UART_CTRL_PARITY_EVEN),    /**< Use for even parity 1 */
+    UART_PARITY_EVEN    = UART_PARITY_EVEN_1,               /**< Conventional even parity */
+    UART_PARITY_ODD_0   = (MXC_F_UART_CTRL_PARITY_EN |
+                           MXC_S_UART_CTRL_PARITY_ODD |
+                           MXC_F_UART_CTRL_PARMD),          /**< Use for odd parity 0 */
+    UART_PARITY_ODD_1   = (MXC_F_UART_CTRL_PARITY_EN |
+                           MXC_S_UART_CTRL_PARITY_ODD),     /**< Use for odd parity 1 */
+    UART_PARITY_ODD     = UART_PARITY_ODD_1,                /**< Conventional odd parity */
+    UART_PARITY_MARK_0  = (MXC_F_UART_CTRL_PARITY_EN |
+                           MXC_S_UART_CTRL_PARITY_MARK |
+                           MXC_F_UART_CTRL_PARMD),          /**< Use for mark parity 0 */
+    UART_PARITY_MARK_1  = (MXC_F_UART_CTRL_PARITY_EN |
+                           MXC_S_UART_CTRL_PARITY_MARK),    /**< Use for mark parity 1 */
+    UART_PARITY_MARK    = UART_PARITY_MARK_1,               /**< Conventional mark parity */
+    UART_PARITY_SPACE_0 = (MXC_F_UART_CTRL_PARITY_EN |
+                           MXC_S_UART_CTRL_PARITY_SPACE |
+                           MXC_F_UART_CTRL_PARMD),          /**< Use for space parity 0 */
+    UART_PARITY_SPACE_1 = (MXC_F_UART_CTRL_PARITY_EN |
+                           MXC_S_UART_CTRL_PARITY_SPACE),   /**< Use for space parity 1 */
+    UART_PARITY_SPACE   = UART_PARITY_SPACE_1,              /**< Conventional space parity */
+} uart_parity_t;
+
+/**
+ * @brief      Message size settings */
+typedef enum {
+    UART_DATA_SIZE_5_BITS = MXC_S_UART_CTRL_CHAR_SIZE_5,   /**< Data Size 5 Bits */
+    UART_DATA_SIZE_6_BITS = MXC_S_UART_CTRL_CHAR_SIZE_6,   /**< Data Size 6 Bits */
+    UART_DATA_SIZE_7_BITS = MXC_S_UART_CTRL_CHAR_SIZE_7,   /**< Data Size 7 Bits */
+    UART_DATA_SIZE_8_BITS = MXC_S_UART_CTRL_CHAR_SIZE_8,   /**< Data Size 8 Bits */
+} uart_size_t;
+
+/**
+ * @brief      Stop bit settings */
+typedef enum {
+    UART_STOP_1   = 0,                                      /**< UART Stop 1 clock cycle */
+    UART_STOP_1P5 = MXC_F_UART_CTRL_STOPBITS,               /**< UART Stop 1.5 clock cycle */
+    UART_STOP_2   = MXC_F_UART_CTRL_STOPBITS,               /**< UART Stop 2 clock cycle */
+} uart_stop_t;
+
+/**
+ * @brief      Flow control */
+typedef enum {
+    UART_FLOW_CTRL_DIS = 0,                                 /**< RTS/CTS flow is disabled */
+    UART_FLOW_CTRL_EN  = MXC_F_UART_CTRL_FLOW_CTRL,         /**< RTS/CTS flow is enabled */
+} uart_flow_ctrl_t;
+
+/**
+ * @brief      Flow control Polarity */
+typedef enum {
+    UART_FLOW_POL_DIS = 0,                                  /**< RTS/CTS asserted is low */
+    UART_FLOW_POL_EN  = MXC_F_UART_CTRL_FLOW_POL,           /**< RTS/CTS asserted is high */
+} uart_flow_pol_t;
+
+#if (TARGET != 32660)
+/**
+ * @brief      Clock Source Select */
+typedef enum {
+    UART_CLKSEL_SYSTEM = 0,                                 /**< Peripheral clock will be used as the bit rate clock */
+    UART_CLKSEL_ALTERNATE = MXC_F_UART_CTRL_CLKSEL,         /**< Use the device's alternate UART bit rate clock. */
+} uart_clksel_t;
+#endif
+
+/**
+ * @brief      UART configuration type. */
+typedef struct {
+    uart_parity_t parity;  /**        Configure parity checking */
+    uart_size_t size;      /**        Configure character size */
+    uart_stop_t stop;      /**        Configure the number of stop bits to use */
+    uart_flow_ctrl_t flow; /**        Configure hardware flow control */
+    uart_flow_pol_t pol;   /**        Configure hardware flow control */
+    uint32_t baud;         /**        Configure baud rate */
+#if (TARGET != 32660)
+    uart_clksel_t clksel;  /**        Configure hardware clock source */
+#endif
+} uart_cfg_t;
+
+/**
+ * @brief      Non-blocking UART transaction request. */
+typedef struct uart_req uart_req_t;
+struct uart_req {
+    uint8_t *data;    /**       Data buffer for characters */
+    int len;          /**       Length of characters in data to send or receive */
+    int num;          /**       Number of characters actually sent or received */
+
+    /**
+     * @brief   Callback for asynchronous request.
+     *
+     * @param   uart_req_t*  Pointer to the transaction request.
+     * @param   int          Error code.
+     *
+     */
+    void(*callback)(uart_req_t*, int);
+};
+
+
+/***** Functions Prototypes *****/
+
+
+/**
+ * @brief   Initialize and enable UART module.
+ * @param   uart        Pointer to the UART registers.
+ * @param   cfg         Pointer to UART configuration.
+ * @param   sys_cfg     Pointer to system configuration object
+ * @returns #E_NO_ERROR UART initialized successfully, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t* sys_cfg);
+
+/**
+ * @brief   Shutdown UART module.
+ * @param   uart    Pointer to the UART registers.
+ * @returns #E_NO_ERROR UART shutdown successfully, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int UART_Shutdown(mxc_uart_regs_t *uart);
+
+/**
+ * @brief      UART interrupt handler.
+ * @details    This function should be called by the application from the
+ *             interrupt handler if UART interrupts are enabled. Alternately,
+ *             this function can be periodically called by the application if
+ *             UART interrupts are disabled. It is only necessary to call this
+ *             when using asynchronous functions.
+ *
+ * @param      uart  Pointer to the UART registers.
+ */
+void UART_Handler(mxc_uart_regs_t *uart);
+
+/**
+ * @brief      Read UART data, <em>blocking</em> until transaction is complete.
+ *
+ * @param      uart  Pointer to the UART registers.
+ * @param      data  Pointer to buffer to save the data read.
+ * @param      len   Number of bytes to read.
+ * @param      num   Pointer to store the number of bytes actually read, pass NULL if not needed.
+ *
+ * @return     Number of bytes read, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int UART_Read(mxc_uart_regs_t *uart, uint8_t *data, int len, int *num);
+
+/**
+ * @brief      Write UART data. This function blocks until the write transaction
+ *             is complete.
+ * @param      uart  Pointer to the UART registers.
+ * @param      data  Pointer to buffer for write data.
+ * @param      len   Number of bytes to write.
+ * @note       This function will return once data has been put into FIFO, not necessarily
+ *             transmitted.
+ * @return     Number of bytes written if successful, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int UART_Write(mxc_uart_regs_t *uart, const uint8_t *data, int len);
+
+/**
+ * @brief      Asynchronously read UART data.
+ *
+ * @param      uart  Pointer to the UART registers.
+ * @param      req   Pointer to request for a UART transaction, see #uart_req.
+ * @note       Request struct must remain allocated until callback function specified in 'req' is called.
+ *
+ * @return     #E_NO_ERROR Asynchronous read successfully started, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req);
+
+/**
+ * @brief      Asynchronously write/transmit UART data.
+ *
+ * @param      uart  Pointer to the UART registers.
+ * @param      req   Request for a UART transaction, see #uart_req.
+ * @note       Request struct must remain allocated until callback function specified in 'req' is called.
+ *
+ * @return     #E_NO_ERROR Asynchronous write successfully started, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req);
+
+/**
+ * @brief      Read a single byte from the UART.
+ * @note       This function will block until a character is available.
+ *
+ * @param      uart  Pointer to the UART registers.
+ * @return     The byte read.
+ */
+uint8_t UART_ReadByte(mxc_uart_regs_t *uart);
+
+/**
+ * @brief      Write one byte at a time to the UART.
+ * @note       This function will block until the character has been placed in the transmit FIFO.
+ *             It may return before the character is actually transmitted.
+ *
+ * @param      uart  Pointer to the UART registers.
+ * @param      data  The byte to write.
+ */
+void UART_WriteByte(mxc_uart_regs_t *uart, uint8_t data);
+
+/**
+ * @brief      Check to see if the UART is busy.
+ *
+ * @param      uart  Pointer to the UART registers.
+ *
+ * @return     #E_NO_ERROR if the UART is idle, #E_BUSY if the UART is in use.
+ */
+int UART_Busy(mxc_uart_regs_t *uart);
+
+/**
+ * @brief      Prepare the UART for entry into a Low-Power mode (DEEPSLEEP/BACKUP).
+ * @details    Checks for any ongoing transactions. Disables interrupts if the
+ *             UART is idle.
+ *
+ * @param      uart         Pointer to the UART registers.
+ * @return     #E_NO_ERROR  UART is ready to enter Low-Power modes (DEEPSLEEP/BACKUP).
+ * @return     #E_BUSY      UART is active and busy and not ready to enter a
+ *                          Low-Power mode (DEEPSLEEP/BACKUP).
+ *
+ */
+int UART_PrepForSleep(mxc_uart_regs_t *uart);
+
+/**
+ * @brief      Abort asynchronous request.
+ *
+ * @param      req   Pointer to the request to abort. See #uart_req.
+ *
+ * @return     #E_NO_ERROR if the asynchronous request aborted successfully started, @ref
+ *             MXC_Error_Codes "error" if unsuccessful.
+ */
+int UART_AbortAsync(uart_req_t *req);
+
+/**
+ * @brief      Returns the number of bytes still pending transmission in the UART TX FIFO.
+ *
+ * @param      uart  Pointer to the UART registers.
+ *
+ * @return     Number of unused bytes in the TX FIFO.
+ */
+unsigned UART_NumWriteAvail(mxc_uart_regs_t *uart);
+
+/**
+ * @brief      Returns the number of bytes available to be read from the RX FIFO.
+ *
+ * @param      uart  Pointer to the UART registers.
+ *
+ * @return     The number of bytes available to read in the RX FIFO.
+ */
+unsigned UART_NumReadAvail(mxc_uart_regs_t *uart);
+
+/**
+ * @brief      Clears the specified interrupt flags.
+ *
+ * @param      uart  Pointer to the UART registers.
+ * @param      mask  Mask of the UART interrupts to clear, see
+ *                   @ref UART_INT_FL Register.
+ */
+void UART_ClearFlags(mxc_uart_regs_t *uart, uint32_t mask);
+
+/**
+ * @brief      Get the UART interrupt flags.
+ *
+ * @param      uart  Pointer to the UART registers.
+ *
+ * @return     Mask of active flags.
+ */
+unsigned UART_GetFlags(mxc_uart_regs_t *uart);
+
+/**
+ * @brief      Enables the UART.
+ * @note       This function does not change the existing UART configuration.
+ *
+ * @param      uart  Pointer to the UART registers.
+ */
+void UART_Enable(mxc_uart_regs_t *uart);
+
+/**
+ * @brief      Disables the UART.
+ * @note       This function does not change the existing UART configuration.
+ *
+ * @param      uart  Pointer to the UART registers.
+ */
+void UART_Disable(mxc_uart_regs_t *uart);
+
+/**
+ * @brief      Drains/empties and data in the RX FIFO, discarding any bytes not yet consumed.
+ *
+ * @param      uart  Pointer to the UART registers.
+ */
+void UART_DrainRX(mxc_uart_regs_t *uart);
+
+/**
+ * @brief      Drains/empties any data in the TX FIFO, discarding any bytes not yet transmitted.
+ *
+ * @param      uart  Pointer to the UART registers.
+ */
+void UART_DrainTX(mxc_uart_regs_t *uart);
+
+/**@} end of group uart */
+
+#endif /* _UART_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/wdt.h

@@ -0,0 +1,166 @@
+/**
+ * @file    wdt.h
+ * @brief   Watchdog timer (WDT) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2020-04-20 15:06:58 -0500 (Mon, 20 Apr 2020) $
+ * $Revision: 53142 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _WDT_H_
+#define _WDT_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+#include "mxc_config.h"
+#include "mxc_sys.h"
+#include "wdt_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup wdt Watchdog Timer (WDT)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/** @brief Watchdog period enumeration. 
+    Used to configure the period of the watchdog interrupt */
+typedef enum {
+    WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31, /**< Period 2^31 */
+    WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30, /**< Period 2^30 */
+    WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29, /**< Period 2^29 */
+    WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28, /**< Period 2^28 */
+    WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27, /**< Period 2^27 */
+    WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26, /**< Period 2^26 */
+    WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25, /**< Period 2^25 */
+    WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24, /**< Period 2^24 */
+    WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23, /**< Period 2^23 */
+    WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22, /**< Period 2^22 */
+    WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21, /**< Period 2^21 */
+    WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20, /**< Period 2^20 */
+    WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19, /**< Period 2^19 */
+    WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18, /**< Period 2^18 */
+    WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17, /**< Period 2^17 */
+    WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16, /**< Period 2^16 */
+} wdt_period_t;
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Initialize the Watchdog Timer
+ * @param      wdt      Pointer to the watchdog registers
+ * @param      sys_cfg  The system configuration object
+ */
+int WDT_Init(mxc_wdt_regs_t* wdt, sys_cfg_wdt_t sys_cfg);
+/**
+ * @brief       Set the period of the watchdog interrupt.
+ * @param       wdt     Pointer to watchdog registers.
+ * @param       period  Enumeration of the desired watchdog period.
+ */
+void WDT_SetIntPeriod(mxc_wdt_regs_t* wdt, wdt_period_t period);
+
+/**
+ * @brief       Set the period of the watchdog reset.
+ * @param       wdt     Pointer to watchdog registers.
+ * @param       period  Enumeration of the desired watchdog period.
+ */
+void WDT_SetResetPeriod(mxc_wdt_regs_t* wdt, wdt_period_t period);
+
+/**
+ * @brief       Enable the watchdog timer.
+ * @param       wdt     Pointer to watchdog registers.
+ * @param       enable  1 to enable the timer, 0 to disable.
+ */
+void WDT_Enable(mxc_wdt_regs_t* wdt, int enable);
+
+/**
+ * @brief       Enable the watchdog interrupt.
+ * @param       wdt     Pointer to watchdog registers.
+ * @param       enable  1 to enable the interrupt, 0 to disable.
+ */
+void WDT_EnableInt(mxc_wdt_regs_t* wdt, int enable);
+
+/**
+ * @brief       Enable the watchdog reset.
+ * @param       wdt     Pointer to watchdog registers.
+ * @param       enable  1 to enable the reset, 0 to disable.
+ */
+void WDT_EnableReset(mxc_wdt_regs_t* wdt, int enable);
+
+/**
+ * @brief       Reset the watchdog timer.
+ * @param       wdt     Pointer to watchdog registers.
+ */
+void WDT_ResetTimer(mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Get the status of the reset flag.
+ * @param       wdt     Pointer to watchdog registers.
+ * @returns     1 if the previous reset was caused by the watchdog, 0 otherwise.
+ */
+int WDT_GetResetFlag(mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Clears the reset flag.
+ * @param       wdt     Pointer to watchdog registers.
+ */
+void WDT_ClearResetFlag(mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief     Get the status of the interrupt flag.
+ * @param       wdt     Pointer to watchdog registers.
+ * @returns   1 if the interrupt is pending, 0 otherwise.
+ */
+int WDT_GetIntFlag(mxc_wdt_regs_t* wdt);
+
+/**
+ * @brief       Clears the interrupt flag.
+ * @param       wdt     Pointer to watchdog registers.
+ */
+void WDT_ClearIntFlag(mxc_wdt_regs_t* wdt);
+
+/**@} end of group wdt */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WDT_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Source/dma.c

@@ -0,0 +1,374 @@
+/* *****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-07-01 11:06:19 -0500 (Mon, 01 Jul 2019) $
+ * $Revision: 44383 $
+ *
+ **************************************************************************** */
+
+#include <stddef.h>
+#include <stdint.h>
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "dma.h"
+
+/*
+ * Structure type
+ */
+typedef struct {
+    unsigned int valid;         /* Flag to invalidate this resource */
+    unsigned int instance;      /* Hardware instance of this DMA controller */
+    unsigned int id;            /* Channel ID, which matches the index into the underlying hardware */
+    mxc_dma_ch_regs_t *regs;    /* Pointer to the registers for this channel */
+    void (*cb)(int, int);       /* Pointer to a callback function type */
+} dma_channel_t;
+
+#define CHECK_HANDLE(x) ((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid))
+
+/* DMA driver must be initialized once before use, and may not be initialized again without shutdown, as it is a shared resource */
+static unsigned int dma_initialized = 0;
+
+static dma_channel_t dma_resource[MXC_DMA_CHANNELS];
+
+static uint32_t dma_lock;
+
+/* Initialize DMA to known state */
+int DMA_Init(void)
+{
+    int i;
+    
+    if (dma_initialized) {
+        return E_BAD_STATE;
+    }
+    
+    /* Initialize any system-level DMA settings */
+    SYS_DMA_Init();
+    
+    /* Initialize mutex */
+    mxc_free_lock(&dma_lock);
+    if (mxc_get_lock(&dma_lock, 1) != E_NO_ERROR) {
+        return E_BUSY;
+    }
+    
+    /* Ensure all channels are disabled at start, clear flags, init handles */
+    MXC_DMA->cn = 0;
+    for (i = 0; i < MXC_DMA_CHANNELS; i++) {
+        dma_resource[i].valid = 0;
+        dma_resource[i].instance = 0;
+        dma_resource[i].id = i;
+        dma_resource[i].regs = (mxc_dma_ch_regs_t *)&MXC_DMA->ch[i];
+        dma_resource[i].regs->cfg = 0;
+        dma_resource[i].regs->st = dma_resource[i].regs->st;
+        
+        dma_resource[i].cb = NULL;
+    }
+    dma_initialized++;
+    mxc_free_lock(&dma_lock);
+    
+    return E_NO_ERROR;
+}
+
+/* Shut down DMA in an orderly manner, informing clients that their requests did not complete */
+int DMA_Shutdown(void)
+{
+    int i;
+    
+    if (!dma_initialized) {
+        /* Never initialized, so shutdown is not appropriate */
+        return E_BUSY;
+    }
+    
+    if (mxc_get_lock(&dma_lock, 1) != E_NO_ERROR) {
+        return E_BUSY;
+    }
+    
+    /* Prevent any new resource allocation by this API */
+    dma_initialized = 0;
+    /* Disable interrupts, preventing future callbacks */
+    MXC_DMA->cn = 0;
+    
+    /* For each channel:
+     *  - invalidate the handles held by clients
+     *  - stop any transfer in progress
+     */
+    for (i = 0; i < MXC_DMA_CHANNELS; i++) {
+        dma_resource[i].regs->cfg = 0;
+        if (dma_resource[i].valid) {
+            dma_resource[i].valid = 0;
+            if (dma_resource[i].cb != NULL) {
+                dma_resource[i].cb(i, E_SHUTDOWN);
+            }
+        }
+    }
+    
+    /* Disable any system-level DMA settings */
+    SYS_DMA_Shutdown();
+    
+    mxc_free_lock(&dma_lock);
+    
+    return E_NO_ERROR;
+}
+
+/* Request DMA channel */
+/* Once "owned", this channel may be used directly via the DMA_GetCHRegs(ch) pointer, or */
+/* configured via the API functions */
+int DMA_AcquireChannel(void)
+{
+    int i, channel;
+    
+    /* Check for initialization */
+    if (!dma_initialized) {
+        return E_BAD_STATE;
+    }
+    
+    /* If DMA is locked return busy */
+    if (mxc_get_lock(&dma_lock, 1) != E_NO_ERROR) {
+        return E_BUSY;
+    }
+    
+    /* Default is no channel available */
+    channel = E_NONE_AVAIL;
+    if (dma_initialized) {
+        for (i = 0; i < MXC_DMA_CHANNELS; i++) {
+            if (!dma_resource[i].valid) {
+                /* Found one */
+                channel = i;
+                dma_resource[i].valid = 1;
+                dma_resource[i].regs->cfg = 0;
+                dma_resource[i].regs->cnt_rld = 0; /* Used by DMA_Start() to conditionally set RLDEN */
+                break;
+            }
+        }
+    }
+    mxc_free_lock(&dma_lock);
+    
+    return channel;
+}
+
+/* Release DMA channel */
+/* Callbacks will not be called */
+int DMA_ReleaseChannel(int ch)
+{
+    if (CHECK_HANDLE(ch)) {
+        if (mxc_get_lock(&dma_lock, 1) != E_NO_ERROR) {
+            return E_BUSY;
+        }
+        dma_resource[ch].valid = 0;
+        dma_resource[ch].regs->cfg = 0;
+        dma_resource[ch].regs->st = dma_resource[ch].regs->st;
+        mxc_free_lock(&dma_lock);
+    } else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+/* Channel configuration */
+int DMA_ConfigChannel(int ch,
+                      dma_priority_t prio,
+                      dma_reqsel_t reqsel, unsigned int reqwait_en,
+                      dma_timeout_t tosel, dma_prescale_t pssel,
+                      dma_width_t srcwd, unsigned int srcinc_en,
+                      dma_width_t dstwd, unsigned int dstinc_en,
+                      unsigned int burst_size, unsigned int chdis_inten,
+                      unsigned int ctz_inten)
+{
+    if (CHECK_HANDLE(ch) && (burst_size > 0)) {
+        /* Designed to be safe, not speedy. Should not be called often */
+        dma_resource[ch].regs->cfg =
+            ((reqwait_en ? MXC_F_DMA_CFG_REQWAIT : 0) |
+             (srcinc_en ? MXC_F_DMA_CFG_SRCINC : 0)   |
+             (dstinc_en ? MXC_F_DMA_CFG_DSTINC : 0)   |
+             (chdis_inten ? MXC_F_DMA_CFG_CHDIEN : 0) |
+             (ctz_inten ? MXC_F_DMA_CFG_CTZIEN : 0)   |
+             prio |reqsel | tosel | pssel | 
+             (srcwd << MXC_F_DMA_CFG_SRCWD_POS) |
+             (dstwd << MXC_F_DMA_CFG_DSTWD_POS) |
+             (((burst_size - 1) << MXC_F_DMA_CFG_BRST_POS) & MXC_F_DMA_CFG_BRST));
+    } else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+/*
+ * DMA request selects for peripherals will override either src_addr or dst_addr.
+ * In these cases, the overridden address is a don't care and may be 0.
+ */
+int DMA_SetSrcDstCnt(int ch,
+                     void *src_addr,
+                     void *dst_addr,
+                     unsigned int count)
+{
+    if (CHECK_HANDLE(ch)) {
+        dma_resource[ch].regs->src = (unsigned int)src_addr;
+        dma_resource[ch].regs->dst = (unsigned int)dst_addr;
+        dma_resource[ch].regs->cnt = count;
+    } else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+/* Must set en_reload == 1 to have any effect */
+int DMA_SetReload(int ch,
+                  void *src_addr_reload,
+                  void *dst_addr_reload,
+                  unsigned int count_reload)
+{
+    if (CHECK_HANDLE(ch)) {
+        dma_resource[ch].regs->src_rld = (unsigned int)src_addr_reload;
+        dma_resource[ch].regs->dst_rld = (unsigned int)dst_addr_reload;
+        if (dma_resource[ch].regs->cfg & MXC_F_DMA_CFG_CHEN) {
+            /* If channel is already running, set RLDEN to enable next reload */
+            dma_resource[ch].regs->cnt_rld = MXC_F_DMA_CNT_RLD_RLDEN | count_reload;
+        } else {
+            /* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */
+            dma_resource[ch].regs->cnt_rld = count_reload;
+        }
+    } else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int DMA_SetCallback(int ch, void (*callback)(int, int))
+{
+    if (CHECK_HANDLE(ch)) {
+        /* Callback for interrupt handler, no checking is done, as NULL is valid for (none)  */
+        dma_resource[ch].cb = callback;
+    } else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+/* Interrupt enable/disable */
+int DMA_EnableInterrupt(int ch)
+{
+    if (CHECK_HANDLE(ch)) {
+        MXC_DMA->cn |= (1 << ch);
+    } else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int DMA_DisableInterrupt(int ch)
+{
+    if (CHECK_HANDLE(ch)) {
+        MXC_DMA->cn &= ~(1 << ch);
+    } else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+/* Channel interrupt flags */
+int DMA_GetFlags(int ch, unsigned int *fl)
+{
+    if (CHECK_HANDLE(ch) && fl) {
+        *fl = dma_resource[ch].regs->st;
+    } else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+int DMA_ClearFlags(int ch)
+{
+    if (CHECK_HANDLE(ch)) {
+        dma_resource[ch].regs->st = dma_resource[ch].regs->st;
+    } else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+/* Start channel */
+int DMA_Start(int ch)
+{
+    if (CHECK_HANDLE(ch)) {
+        DMA_ClearFlags(ch);
+        if (dma_resource[ch].regs->cnt_rld) {
+            dma_resource[ch].regs->cfg |= (MXC_F_DMA_CFG_CHEN | MXC_F_DMA_CFG_RLDEN);
+        } else {
+            dma_resource[ch].regs->cfg |= MXC_F_DMA_CFG_CHEN;
+        }
+    } else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+/* Stop channel */
+int DMA_Stop(int ch)
+{
+    if (CHECK_HANDLE(ch)) {
+        dma_resource[ch].regs->cfg &= ~MXC_F_DMA_CFG_CHEN;
+    } else {
+        return E_BAD_PARAM;
+    }
+    
+    return E_NO_ERROR;
+}
+
+/* Get pointer to registers, for advanced users */
+mxc_dma_ch_regs_t *DMA_GetCHRegs(int ch)
+{
+    if (CHECK_HANDLE(ch)) {
+        return dma_resource[ch].regs;
+    } else {
+        return NULL;
+    }
+}
+
+/* */
+void DMA_Handler(int ch)
+{
+    /* Do callback, if enabled */
+    if (dma_resource[ch].cb != NULL) {
+        dma_resource[ch].cb(ch, E_NO_ERROR);
+    }
+    DMA_ClearFlags(ch);
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/flc.c

@@ -0,0 +1,579 @@
+/**
+ * @file flc.h
+ * @brief      Flash Controler driver.
+ * @details    This driver can be used to operate on the embedded flash memory.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-06-05 16:53:29 -0500 (Wed, 05 Jun 2019) $
+ * $Revision: 43696 $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_config.h"
+#include "mxc_sys.h"
+#include "flc.h"
+#include "flc_regs.h"
+
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+// *****************************************************************************
+#if defined (__ICCARM__)
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+static int prepare_flc(void)
+{
+    // Set flash clock divider to generate a 1MHz clock from the APB clock
+    MXC_FLC->clkdiv = SystemCoreClock / 1000000;
+
+    /* Check if the flash controller is busy */
+    if (FLC_Busy()) {
+        return E_BUSY;
+    }
+
+    /* Clear stale errors */
+    if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
+        MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
+    }
+
+    /* Unlock flash */
+    MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_UNLOCK) | MXC_S_FLC_CN_UNLOCK_UNLOCKED;
+
+    return E_NO_ERROR;
+}
+
+// *****************************************************************************
+#if defined (__ICCARM__)
+// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_Init(const sys_cfg_flc_t *sys_cfg)
+{
+  SYS_FLC_Init(sys_cfg);
+
+  return E_NO_ERROR;
+}
+
+// *****************************************************************************
+#if defined (__ICCARM__)
+// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_Busy(void)
+{
+    return (MXC_FLC->cn & (MXC_F_FLC_CN_WR | MXC_F_FLC_CN_ME | MXC_F_FLC_CN_PGE));
+}
+
+// *****************************************************************************
+#if defined (__ICCARM__)
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_MassErase(void)
+{
+    int err;
+
+    if ((err = prepare_flc()) != E_NO_ERROR)
+        return err;
+
+    /* Write mass erase code */
+    MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_ERASE_CODE) | MXC_S_FLC_CN_ERASE_CODE_ERASEALL;
+
+    /* Issue mass erase command */
+    MXC_FLC->cn |= MXC_F_FLC_CN_ME;
+
+    /* Wait until flash operation is complete */
+    while (FLC_Busy());
+    /* Lock flash */
+    MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
+
+    /* Check access violations */
+    if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
+        MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
+        return E_BAD_STATE;
+    }
+
+    SYS_Flash_Operation();
+
+    return E_NO_ERROR;
+}
+
+// *****************************************************************************
+#if defined (__ICCARM__)
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_PageErase(uint32_t address)
+{
+    int err;
+
+    if ((err = prepare_flc()) != E_NO_ERROR)
+        return err;
+
+    // Align address on page boundary
+    address = address - (address % MXC_FLASH_PAGE_SIZE);
+
+    /* Write page erase code */
+    MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_ERASE_CODE) | MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE;
+    /* Issue page erase command */
+    MXC_FLC->addr = address;
+    MXC_FLC->cn |= MXC_F_FLC_CN_PGE;
+
+    /* Wait until flash operation is complete */
+    while (FLC_Busy());
+
+    /* Lock flash */
+    MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
+
+    /* Check access violations */
+    if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
+        MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
+        return E_BAD_STATE;
+    }
+
+    SYS_Flash_Operation();
+
+    return E_NO_ERROR;
+}
+
+// *****************************************************************************
+#if defined (__ICCARM__)
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_Erase(uint32_t start, uint32_t end)
+{
+    int retval;
+    uint32_t addr;
+
+    // Align start and end on page boundaries
+    start = start - (start % MXC_FLASH_PAGE_SIZE);
+    end = end - (end % MXC_FLASH_PAGE_SIZE);
+
+    for (addr = start; addr <= end; addr += MXC_FLASH_PAGE_SIZE) {
+        retval = FLC_PageErase(addr);
+        if (retval != E_NO_ERROR)  {
+            return retval;
+        }
+    }
+
+    return E_NO_ERROR;
+}
+
+// *****************************************************************************
+#if defined (__ICCARM__)
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_BufferErase(uint32_t start, uint32_t end, uint8_t *buffer, unsigned length)
+{
+    int retval;
+    uint32_t start_align, start_len, end_align, end_len;
+
+    // Align start and end on page boundaries, calculate length of data to buffer
+    start_align = start - (start % MXC_FLASH_PAGE_SIZE);
+    start_len = (start % MXC_FLASH_PAGE_SIZE);
+    end_align = end - (end % MXC_FLASH_PAGE_SIZE);
+    end_len = ((MXC_FLASH_PAGE_SIZE - (end % MXC_FLASH_PAGE_SIZE)) % MXC_FLASH_PAGE_SIZE);
+
+    // Make sure the length of buffer is sufficient
+    if ((length < start_len) || (length < end_len)) {
+        return E_BAD_PARAM;
+    }
+
+
+    // Start and end address are in the same page
+    if (start_align == end_align) {
+        if (length < (start_len + end_len)) {
+            return E_BAD_PARAM;
+        }
+
+        // Buffer first page data and last page data, erase and write
+        memcpy(buffer, (void*)start_align, start_len);
+        memcpy(&buffer[start_len], (void*)end, end_len);
+        retval = FLC_PageErase(start_align);
+        if (retval != E_NO_ERROR) {
+            return retval;
+        }
+
+        retval = FLC_Write(start_align, start_len, buffer);
+        if (retval != E_NO_ERROR) {
+            return retval;
+        }
+        retval = FLC_Write(end, end_len, &buffer[start_len]);
+        if (retval != E_NO_ERROR) {
+            return retval;
+        }
+
+        return E_NO_ERROR;
+    }
+
+    // Buffer, erase, and write the data in the first page
+    memcpy(buffer, (void*)start_align, start_len);
+    retval = FLC_PageErase(start_align);
+    if (retval != E_NO_ERROR) {
+        return retval;
+    }
+
+    retval = FLC_Write(start_align, start_len, buffer);
+    if (retval != E_NO_ERROR) {
+        return retval;
+    }
+
+    // Buffer, erase, and write the data in the last page
+    memcpy(buffer, (void*)end, end_len);
+    retval = FLC_PageErase(end_align);
+    if (retval != E_NO_ERROR) {
+        return retval;
+    }
+
+    retval = FLC_Write(end, end_len, buffer);
+    if (retval != E_NO_ERROR) {
+        return retval;
+    }
+
+    // Erase the remaining pages
+    if (start_align != end_align) {
+        return FLC_Erase((start_align + MXC_FLASH_PAGE_SIZE), (end_align - MXC_FLASH_PAGE_SIZE));
+    }
+
+    return E_NO_ERROR;
+}
+
+// *****************************************************************************
+#if defined (__ICCARM__)
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_Write32(uint32_t address, uint32_t data)
+{
+    int err;
+
+    // Address checked if it is byte addressable
+    if (address & 0x3) {
+        return E_BAD_PARAM;
+    }
+
+    if ((err = prepare_flc()) != E_NO_ERROR)
+        return err;
+
+    // write in 32-bit units
+    MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
+    MXC_FLC->cn &= ~MXC_F_FLC_CN_BRST;
+
+    // write the data
+    MXC_FLC->addr = address;
+    MXC_FLC->data[0] = data;
+    MXC_FLC->cn |= MXC_F_FLC_CN_WR;
+
+
+    /* Wait until flash operation is complete */
+    while (FLC_Busy()) {}
+
+    /* Lock flash */
+    MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
+
+    /* Check access violations */
+    if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
+        MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
+        return E_BAD_STATE;
+    }
+
+    SYS_Flash_Operation();
+
+    return E_NO_ERROR;
+}
+
+// *****************************************************************************
+#if defined (__ICCARM__)
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_Write128(uint32_t address, uint32_t *data)
+{
+    int err;
+
+    // Address checked if it is word addressable
+    if (address & 0xF) {
+        return E_BAD_PARAM;
+    }
+
+    if ((err = prepare_flc()) != E_NO_ERROR)
+        return err;
+
+    // write 128-bits
+    MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH;
+
+    // write the data
+    MXC_FLC->addr = address;
+    memcpy((void*)&MXC_FLC->data[0], data, 16);
+    MXC_FLC->cn |= MXC_F_FLC_CN_WR;
+
+    /* Wait until flash operation is complete */
+    while (FLC_Busy());
+
+    /* Lock flash */
+    MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
+
+    /* Check access violations */
+    if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
+        MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
+        return E_BAD_STATE;
+    }
+
+    SYS_Flash_Operation();
+
+    return E_NO_ERROR;
+}
+
+// *****************************************************************************
+#if defined (__ICCARM__)
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_Write(uint32_t address, uint32_t length, uint8_t *buffer)
+{
+    int err;
+    uint32_t bytes_written;
+    uint8_t current_data[4];
+
+    if ((err = prepare_flc()) != E_NO_ERROR)
+        return err;
+
+    // write in 32-bit units until we are 128-bit aligned
+    MXC_FLC->cn &= ~MXC_F_FLC_CN_BRST;
+    MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
+
+    // Align the address and read/write if we have to
+    if (address & 0x3) {
+
+        // Figure out how many bytes we have to write to round up the address
+        bytes_written = 4 - (address & 0x3);
+
+        // Save the data currently in the flash
+        memcpy(current_data, (void*)(address & (~0x3)), 4);
+
+        // Modify current_data to insert the data from buffer
+        memcpy(&current_data[4-bytes_written], buffer, bytes_written);
+
+        // Write the modified data
+        MXC_FLC->addr = address - (address % 4);
+        memcpy((void*)&MXC_FLC->data[0], &current_data, 4);
+        MXC_FLC->cn |= MXC_F_FLC_CN_WR;
+
+        /* Wait until flash operation is complete */
+        while (FLC_Busy());
+
+        address += bytes_written;
+        length -= bytes_written;
+        buffer += bytes_written;
+    }
+
+    while ( (length >= 4) && ((address & 0xF) != 0) ) {
+        MXC_FLC->addr = address;
+        memcpy((void*)&MXC_FLC->data[0], buffer, 4);
+        MXC_FLC->cn |= MXC_F_FLC_CN_WR;
+
+        /* Wait until flash operation is complete */
+        while (FLC_Busy());
+
+        address += 4;
+        length -= 4;
+        buffer += 4;
+    }
+
+    if (length >= 16) {
+
+        // write in 128-bit bursts while we can
+        MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH;
+
+        while (length >= 16) {
+            MXC_FLC->addr = address;
+            memcpy((void*)&MXC_FLC->data[0], buffer, 16);
+            MXC_FLC->cn |= MXC_F_FLC_CN_WR;
+
+            /* Wait until flash operation is complete */
+            while (FLC_Busy());
+
+            address += 16;
+            length -= 16;
+            buffer += 16;
+    }
+
+        // Return to 32-bit writes.
+        MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
+    }
+
+        while (length >= 4) {
+            MXC_FLC->addr = address;
+            memcpy((void*)&MXC_FLC->data[0], buffer, 4);
+            MXC_FLC->cn |= MXC_F_FLC_CN_WR;
+
+            /* Wait until flash operation is complete */
+            while (FLC_Busy());
+
+            address += 4;
+            length -= 4;
+            buffer += 4;
+        }
+
+    if (length > 0) {
+        // Save the data currently in the flash
+        memcpy(current_data, (void*)(address), 4);
+
+        // Modify current_data to insert the data from buffer
+        memcpy(current_data, buffer, length);
+
+        MXC_FLC->addr = address;
+        memcpy((void*)&MXC_FLC->data[0], current_data, 4);
+        MXC_FLC->cn |= MXC_F_FLC_CN_WR;
+
+        /* Wait until flash operation is complete */
+        while (FLC_Busy());
+    }
+
+    /* Lock flash */
+    MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
+
+    /* Check access violations */
+    if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
+        MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
+        return E_BAD_STATE;
+    }
+
+    SYS_Flash_Operation();
+
+    return E_NO_ERROR;
+}
+
+int FLC_EnableInt(uint32_t mask)
+{
+  uint32_t tmp;
+
+  mask &= (MXC_F_FLC_INTR_DONEIE |  MXC_F_FLC_INTR_AFIE);
+  if (!mask) {
+    /* No bits set? Wasn't something we can enable. */
+    return E_BAD_PARAM;
+  }
+
+  /* Careful with access_fail bit, as it is W0C */
+  tmp = MXC_FLC->intr | MXC_F_FLC_INTR_AF;
+  /* Don't lose done flag */
+  tmp &= ~(MXC_F_FLC_INTR_DONE);
+  /* Apply enables and write back */
+  MXC_FLC->intr = (tmp | mask);
+
+  return E_NO_ERROR;
+}
+
+int FLC_DisableInt(uint32_t mask)
+{
+  uint32_t tmp;
+
+  mask &= (MXC_F_FLC_INTR_DONEIE |  MXC_F_FLC_INTR_AFIE);
+  if (!mask) {
+    /* No bits set? Wasn't something we can disable. */
+    return E_BAD_PARAM;
+  }
+
+  /* Careful with access_fail bit, as it is W0C */
+  tmp = MXC_FLC->intr | MXC_F_FLC_INTR_AF;
+  /* Don't lose done flag */
+  tmp &= ~(MXC_F_FLC_INTR_DONE);
+  /* Apply disables and write back */
+  MXC_FLC->intr = (tmp & ~mask);
+
+  return E_NO_ERROR;
+}
+
+int FLC_GetFlags(void)
+{
+  return (MXC_FLC->intr & (MXC_F_FLC_INTR_DONE | MXC_F_FLC_INTR_AF));
+}
+
+int FLC_ClearFlags(uint32_t mask)
+{
+  mask &= (MXC_F_FLC_INTR_DONE | MXC_F_FLC_INTR_AF);
+  if (!mask) {
+    /* No bits set? Wasn't something we can clear. */
+    return E_BAD_PARAM;
+  }
+
+  // Both bits are write zero clear
+  MXC_FLC->intr ^= mask;
+
+  return E_NO_ERROR;
+}
+
+int FLC_UnlockInfoBlock()
+{
+    MXC_FLC->acntl = 0x3a7f5ca3;
+    MXC_FLC->acntl = 0xa1e34f20;
+    MXC_FLC->acntl = 0x9608b2c1;
+    return E_NO_ERROR;
+}
+
+int FLC_LockInfoBlock()
+{
+    MXC_FLC->acntl = 0xDEADBEEF;
+    return E_NO_ERROR;
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/gpio.c

@@ -0,0 +1,312 @@
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "gpio.h"
+#include <stddef.h>
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void *);
+static void *cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT];
+
+/* **** Functions **** */
+
+int GPIO_Init(void)
+{
+    int i;
+    int j;
+    
+    // Initialize call back arrays
+    for(i = 0; i < MXC_CFG_GPIO_INSTANCES; i++) {
+        for(j = 0; j < MXC_CFG_GPIO_PINS_PORT; j++) {
+            callback[i][j] = NULL;
+        }
+    }            
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+/*
+ *       GPIO_EN2 |  GPIO_EN1           |  GPIO_EN            |   Function
+ *  --------------|---------------------|---------------------|----------------------
+ *     0          |          0          |          0          |     Alternative 1
+ *     0          |          1          |          0          |     Alternative 2
+ *     1          |          0          |          0          |     Alternative 3
+ *     1          |          1          |          0          |     Alternative 4
+ *     0          |          0          |          1          |     GPIO (default)
+*/
+
+int GPIO_Config(const gpio_cfg_t *cfg)
+{
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
+
+    // Set the GPIO type
+    switch (cfg->func) {
+        case GPIO_FUNC_IN:
+            gpio->out_en_clr = cfg->mask;
+            gpio->en_set     = cfg->mask;
+            gpio->en1_clr    = cfg->mask;
+            gpio->en2_clr    = cfg->mask;
+            break;
+        case GPIO_FUNC_OUT:
+            gpio->out_en_set = cfg->mask;
+            gpio->en_set     = cfg->mask;
+            gpio->en1_clr    = cfg->mask;
+            gpio->en2_clr    = cfg->mask;
+            break;
+        case GPIO_FUNC_ALT1:
+            gpio->en_clr     = cfg->mask;
+            gpio->en1_clr    = cfg->mask;
+            gpio->en2_clr    = cfg->mask;
+            break;
+        case GPIO_FUNC_ALT2:
+            gpio->en_clr     = cfg->mask;
+            gpio->en1_set    = cfg->mask;
+            gpio->en2_clr    = cfg->mask;
+            break;
+        case GPIO_FUNC_ALT3:
+#if TARGET==32660
+            gpio->en_set     = cfg->mask;
+            gpio->en1_set    = cfg->mask;
+#else
+            gpio->en_clr     = cfg->mask;
+            gpio->en1_clr    = cfg->mask;
+            gpio->en2_set    = cfg->mask;
+#endif
+            break;
+        case GPIO_FUNC_ALT4:
+            gpio->en_clr     = cfg->mask;
+            gpio->en1_set    = cfg->mask;
+            gpio->en2_set    = cfg->mask;
+            break;
+        default:
+            return E_BAD_PARAM;
+    }
+
+    // Configure the pad
+    switch (cfg->pad) {
+        case GPIO_PAD_NONE:
+            gpio->pad_cfg1 &= ~cfg->mask;
+            gpio->pad_cfg2 &= ~cfg->mask;
+#if TARGET==32660
+            gpio->ps &= ~cfg->mask;
+#endif
+            break;
+        case GPIO_PAD_PULL_UP:
+            gpio->pad_cfg1 |=  cfg->mask;
+            gpio->pad_cfg2 &= ~cfg->mask;
+#if TARGET==32660
+            gpio->ps |= cfg->mask;
+#endif
+            break;
+        case GPIO_PAD_PULL_DOWN:
+            gpio->pad_cfg1 &= ~cfg->mask;
+            gpio->pad_cfg2 |=  cfg->mask;
+#if TARGET==32660
+            gpio->ps &= ~cfg->mask;
+#endif
+            break;
+        default:
+            return E_BAD_PARAM;
+    }
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+uint32_t GPIO_InGet(const gpio_cfg_t *cfg)
+{
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
+
+    return (gpio->in & cfg->mask);
+}
+
+/* ************************************************************************** */
+void GPIO_OutSet(const gpio_cfg_t *cfg)
+{
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
+
+    gpio->out_set = cfg->mask;
+}
+
+/* ************************************************************************** */
+void GPIO_OutClr(const gpio_cfg_t *cfg)
+{
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
+
+    gpio->out_clr = cfg->mask;
+}
+
+/* ************************************************************************** */
+uint32_t GPIO_OutGet(const gpio_cfg_t *cfg)
+{
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
+
+    return (gpio->out & cfg->mask);
+}
+
+/* ************************************************************************** */
+void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val)
+{
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
+
+    gpio->out = (gpio->out & ~cfg->mask) | (val & cfg->mask);
+}
+
+/* ************************************************************************** */
+void GPIO_OutToggle(const gpio_cfg_t *cfg)
+{
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
+
+    gpio->out ^= cfg->mask;
+}
+
+/* ************************************************************************** */
+int GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode, gpio_int_pol_t pol)
+{
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
+
+    switch (mode) {
+        case GPIO_INT_LEVEL:
+            gpio->int_mod &= ~cfg->mask;
+            break;
+        case GPIO_INT_EDGE:
+            gpio->int_mod |= cfg->mask;
+            break;
+        default:
+            return E_BAD_PARAM;
+    }
+
+    switch (pol) {
+        case GPIO_INT_FALLING:  /* GPIO_INT_HIGH */
+            gpio->int_pol &= ~cfg->mask;
+            gpio->int_dual_edge &= ~cfg->mask;
+        break;
+        case GPIO_INT_RISING:   /* GPIO_INT_LOW */
+            gpio->int_pol |= cfg->mask;
+            gpio->int_dual_edge &= ~cfg->mask;
+        break;
+        case GPIO_INT_BOTH:
+            gpio->int_dual_edge |= cfg->mask;
+        break;
+        default:
+            return E_BAD_PARAM;
+    }
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+void GPIO_IntEnable(const gpio_cfg_t *cfg)
+{
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
+
+    gpio->int_en_set = cfg->mask;
+}
+
+/* ************************************************************************** */
+void GPIO_IntDisable(const gpio_cfg_t *cfg)
+{
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
+
+    gpio->int_en_clr = cfg->mask;
+}
+
+/* ************************************************************************** */
+uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg)
+{
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
+
+    return (gpio->int_stat & cfg->mask);
+}
+
+/* ************************************************************************** */
+void GPIO_IntClr(const gpio_cfg_t *cfg)
+{
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
+
+    gpio->int_clr = cfg->mask;
+}
+
+/* ************************************************************************** */
+void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn func, void *cbdata)
+{
+    uint32_t mask;
+    unsigned int pin;
+
+    mask = cfg->mask;
+    pin = 0;
+
+    while (mask) {
+        if (mask & 1) {
+            callback[cfg->port][pin] = func;
+            cbparam[cfg->port][pin] = cbdata;
+        }
+        pin++;
+        mask >>= 1;
+    }
+}
+
+/* ************************************************************************** */
+void GPIO_Handler(unsigned int port)
+{
+    uint32_t stat;
+    unsigned int pin;
+
+    MXC_ASSERT(port < MXC_CFG_GPIO_INSTANCES);
+
+    mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port);
+
+    stat = gpio->int_stat;
+    gpio->int_clr = stat;
+
+    pin = 0;
+
+    while (stat) {
+        if (stat & 1) {
+            if(callback[port][pin]) {
+                callback[port][pin](cbparam[port][pin]);
+            }
+        }
+        pin++;
+        stat >>= 1;
+    }
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/i2c.c

@@ -0,0 +1,1060 @@
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2020-02-03 10:33:50 -0600 (Mon, 03 Feb 2020) $
+ * $Revision: 51326 $
+ *
+ *************************************************************************** */
+
+
+#include <stddef.h>
+#include <stdint.h>
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "i2c.h"
+#include <stdio.h>
+#include "mxc_delay.h"
+
+/* **** Definitions **** */
+#define I2C_ERROR   (MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | MXC_F_I2C_INT_FL0_ADDR_NACK_ER | \
+                    MXC_F_I2C_INT_FL0_DATA_ER | MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \
+                    MXC_F_I2C_INT_FL0_STOP_ER)
+#define MASTER 1
+#define SLAVE 0
+
+/* For high speed mode, if the I2C bus capacitance is greater than 100pF, set this value to ((capacitance - 100) / 3).
+   Otherwise leave it at 0. */
+#define HS_SCALE_FACTOR         (0)
+
+#define T_LOW_MIN     (160 + (160 * HS_SCALE_FACTOR / 100))   /* tLOW minimum in nanoseconds */
+#define T_HIGH_MIN    (60 + (60 * HS_SCALE_FACTOR / 100))     /* tHIGH minimum in nanoseconds */
+#define T_R_MAX_HS    (40 + (40 * HS_SCALE_FACTOR / 100))     /* tR maximum for high speed mode in nanoseconds */
+#define T_F_MAX_HS    (40 + (40 * HS_SCALE_FACTOR / 100))     /* tF maximum for high speed mode in nanoseconds */
+#define T_AF_MIN      (10 + (10 * HS_SCALE_FACTOR / 100))     /* tAF minimun in nanoseconds */
+
+/* **** Variable Declaration **** */
+
+// Saves the state of the non-blocking requests
+typedef struct {
+    i2c_req_t *req;
+    i2c_state_t state;
+    uint8_t num_wr;    // keep track of number of bytes loaded in the fifo during slave transmit
+} i2c_req_state_t;
+static i2c_req_state_t states[MXC_I2C_INSTANCES];
+
+/* **** Function Prototypes **** */
+static void I2C_MasterHandler(mxc_i2c_regs_t *i2c);
+static void I2C_SlaveHandler(mxc_i2c_regs_t *i2c);
+static void I2C_FreeCallback(int i2c_num, int error);
+static void I2C_Recover(mxc_i2c_regs_t *i2c);
+
+/* ************************************************************************** */
+static int I2C_Setspeed(mxc_i2c_regs_t * i2c, i2c_speed_t i2cspeed)
+{
+    uint32_t ticks, ticks_lo, ticks_hi;
+
+    if (i2cspeed == I2C_HS_MODE) {
+
+        uint32_t sys_freq, tPCLK, targBusFreq, tSCLmin, cklMin, ckhMin, ckh_cklMin;
+
+        /* Compute dividers for high speed mode. */
+        sys_freq = SYS_I2C_GetFreq(i2c);
+        MXC_ASSERT(sys_freq >= 1000);
+
+        tPCLK = 1000000 / (sys_freq / 1000);
+        MXC_ASSERT(tPCLK > 0)
+
+        targBusFreq = i2cspeed - ((i2cspeed/2) * HS_SCALE_FACTOR / 100);
+        if(targBusFreq < 1000) {
+            return E_BAD_PARAM;
+        }
+
+        tSCLmin = 1000000 / (targBusFreq / 1000);                                
+        cklMin = ((T_LOW_MIN + T_F_MAX_HS + (tPCLK - 1) - T_AF_MIN) / tPCLK) - 1;
+        ckhMin = ((T_HIGH_MIN + T_R_MAX_HS + (tPCLK - 1) - T_AF_MIN) / tPCLK) - 1;
+        ckh_cklMin = ((tSCLmin + (tPCLK - 1)) / tPCLK) - 2;
+
+        ticks_lo = (cklMin > (ckh_cklMin - ckhMin)) ? (cklMin) : (ckh_cklMin - ckhMin);
+        ticks_hi = ckhMin;
+
+        if((ticks_lo > (MXC_F_I2C_HS_CLK_HS_CLK_LO >> MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) ||
+           (ticks_hi > (MXC_F_I2C_HS_CLK_HS_CLK_HI >> MXC_F_I2C_HS_CLK_HS_CLK_HI_POS))) {
+            return E_BAD_PARAM;
+        }
+
+        /* Write results to destination registers. */
+        i2c->hs_clk = (ticks_lo << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS) | (ticks_hi <<
+                      MXC_F_I2C_HS_CLK_HS_CLK_HI_POS);
+
+        /* Still need to load dividers for the preamble that each high-speed transaction starts with.
+           Switch setting to fast mode and fall out of if statement. */
+        i2cspeed = I2C_FAST_MODE;
+    }
+    
+    /* Get the number of periph clocks needed to achieve selected speed. */
+    ticks = SYS_I2C_GetFreq(i2c) / i2cspeed;
+
+    /* For a 50% duty cycle, half the ticks will be spent high and half will be low. */
+    ticks_hi = (ticks >> 1) - 1;
+    ticks_lo = (ticks >> 1) - 1;
+
+    /* Account for rounding error in odd tick counts. */
+    if (ticks & 1) {
+        ticks_hi++;
+    }
+
+    /* Will results fit into 9 bit registers?  (ticks_hi will always be >= ticks_lo.  No need to check ticks_lo.) */
+    if (ticks_hi > 0x1FF) {
+        return E_BAD_PARAM;
+    }
+
+    /* 0 is an invalid value for the destination registers. (ticks_hi will always be >= ticks_lo.  No need to check ticks_hi.) */
+    if (ticks_lo == 0) {
+        return E_BAD_PARAM;
+    }
+
+    /* Write results to destination registers. */
+    i2c->clk_lo = ticks_lo;
+    i2c->clk_hi = ticks_hi;
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int I2C_Init(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed, const sys_cfg_i2c_t* sys_cfg)
+{
+    int err;
+    int idx = MXC_I2C_GET_IDX(i2c);
+    // Check the base pointer
+    MXC_ASSERT(idx >= 0);
+
+    // Set system level configurations
+    if ((err = SYS_I2C_Init(i2c, sys_cfg)) != E_NO_ERROR) {
+        return err;
+    }
+
+    // Always disable the HW autoflush on data NACK and let the SW handle the flushing.
+    i2c->tx_ctrl0 |= 0x20;
+
+    states[idx].num_wr = 0;
+
+    i2c->ctrl = 0;   // clear configuration bits
+    i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN;       // Enable I2C
+    i2c->master_ctrl = 0;  // clear master configuration bits
+    i2c->status = 0;   // clear status bits
+
+    /* If either SDA or SCL is already low, there is a problem.
+     * Try reclaiming the bus by sending clocks until we have control of the SDA line.
+     * Follow procedure defined in i2c spec.
+     */
+    if ((i2c->ctrl & (MXC_F_I2C_CTRL_SCL | MXC_F_I2C_CTRL_SDA)) !=
+            (MXC_F_I2C_CTRL_SCL | MXC_F_I2C_CTRL_SDA)) {
+
+        int i, have_control;
+
+        // Set SCL/SDA as software controlled.
+        i2c->ctrl |= MXC_F_I2C_CTRL_SW_OUT_EN;
+
+        // Try to get control of SDA.
+        for (i = 0; i < 16; i++) {
+            have_control = 1;
+
+            // Drive SCL low and check its state.
+            i2c->ctrl &= ~(MXC_F_I2C_CTRL_SCL_OUT);
+            mxc_delay(MXC_DELAY_USEC(5));
+            if ((i2c->ctrl & MXC_F_I2C_CTRL_SCL) == MXC_F_I2C_CTRL_SCL) {
+                have_control = 0;
+            }
+
+            // Drive SDA low and check its state.
+            i2c->ctrl &= ~(MXC_F_I2C_CTRL_SDA_OUT);
+            mxc_delay(MXC_DELAY_USEC(5));
+            if ((i2c->ctrl & MXC_F_I2C_CTRL_SDA) == MXC_F_I2C_CTRL_SDA) {
+                have_control = 0;
+            }
+
+            // Release SDA and check its state.
+            i2c->ctrl |= (MXC_F_I2C_CTRL_SDA_OUT);
+            mxc_delay(MXC_DELAY_USEC(5));
+            if ((i2c->ctrl & MXC_F_I2C_CTRL_SDA) != MXC_F_I2C_CTRL_SDA) {
+                have_control = 0;
+            }
+
+            // Release SCL and check its state.
+            i2c->ctrl |= (MXC_F_I2C_CTRL_SCL_OUT);
+            mxc_delay(MXC_DELAY_USEC(5));
+            if ((i2c->ctrl & MXC_F_I2C_CTRL_SCL) != MXC_F_I2C_CTRL_SCL) {
+                have_control = 0;
+            }
+
+            if (have_control) {
+                // Issue stop
+                // Drive SDA low.
+                i2c->ctrl &= ~(MXC_F_I2C_CTRL_SDA_OUT);
+                mxc_delay(MXC_DELAY_USEC(5));
+                // Release SDA.
+                i2c->ctrl |= (MXC_F_I2C_CTRL_SDA_OUT);
+                mxc_delay(MXC_DELAY_USEC(5));
+                break;
+            }
+        }
+
+        if (!have_control) {
+            return E_COMM_ERR;
+        }
+    }
+
+    i2c->ctrl = 0;   // clear configuration bits
+    i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN;       // Enable I2C
+    i2c->master_ctrl = 0;  // clear master configuration bits
+    i2c->status= 0;   // clear status bits
+
+    // Check for HS mode
+    if (i2cspeed == I2C_HS_MODE) {
+        i2c->ctrl |= MXC_F_I2C_CTRL_HS_MODE;    // Enable HS mode
+    }
+
+    // Disable and clear interrupts
+    i2c->int_en0 = 0;
+    i2c->int_en1 = 0;
+    i2c->int_fl0 = i2c->int_fl0;
+    i2c->int_fl1 = i2c->int_fl1;
+
+    i2c->timeout = 0x0;   // set timeout
+    i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; // clear the RX FIFO
+    i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; // clear the TX FIFO
+
+    return I2C_Setspeed(i2c, i2cspeed);
+}
+/* ************************************************************************** */
+int I2C_Shutdown(mxc_i2c_regs_t *i2c)
+{
+    int i2c_num, err;
+
+    // Check the base pointer
+    i2c_num = MXC_I2C_GET_IDX(i2c);
+    MXC_ASSERT(i2c_num >= 0);
+
+    // Disable and clear interrupts
+    i2c->int_en0 = 0;
+    i2c->int_en1 = 0;
+    i2c->int_fl0 = i2c->int_fl0;
+    i2c->int_fl1 = i2c->int_fl1;
+
+    i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; // clear the RX FIFO
+    i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; // clear the TX FIFO
+
+    // Call all of the pending callbacks for this I2C
+    if (states[i2c_num].req != NULL) {
+        I2C_Recover(i2c);
+        I2C_FreeCallback(i2c_num, E_SHUTDOWN);
+    }
+
+    i2c->ctrl = 0;
+    
+    // Clears system level configurations
+    if ((err = SYS_I2C_Shutdown(i2c)) != E_NO_ERROR) {
+        return err;
+    }
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int I2C_MasterWrite(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* data, int len, int restart)
+{
+    int save_len = len;
+
+    if (len == 0) {
+        return E_NO_ERROR;
+    }
+
+    // Clear the lock out bit (W1C) in case it is set.
+    i2c->int_fl0 = MXC_F_I2C_INT_FL0_TX_LOCK_OUT;
+    i2c->int_fl0 = i2c->int_fl0;
+
+    // Enable master mode
+    i2c->ctrl |= MXC_F_I2C_CTRL_MST;
+
+    // Load FIFO with slave address for WRITE and as much data as we can
+    while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {}
+    i2c->fifo = addr & ~(0x1);
+
+    while ((len > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+        i2c->fifo = *data++;
+        len--;
+    }
+
+    i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
+
+    // Write remaining data to FIFO
+    while (len > 0) {
+
+        // Check for errors
+        if (i2c->int_fl0 & I2C_ERROR) {
+            // Set the stop bit
+            i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
+            i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+             while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_STOP))) {}    
+
+            return E_COMM_ERR;
+        }
+
+        if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+            i2c->fifo = *data++;
+            len--;
+        }
+    }
+
+    if (restart)  {
+        i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
+    } else {
+        i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+    }
+
+    // Wait for Done or time out if enabled
+    while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_DONE | I2C_ERROR ))) {}    
+
+    i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
+
+    // Wait for Stop
+    if (!restart) {
+        while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_STOP ))) {}
+        
+        i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
+    }
+
+    // Check for errors
+    if (i2c->int_fl0 & I2C_ERROR) {
+        return E_COMM_ERR;
+    }
+
+    return save_len;
+}
+
+/* ************************************************************************** */
+int I2C_MasterRead(mxc_i2c_regs_t *i2c, uint8_t addr, uint8_t* data, int len, int restart)
+{
+    int save_len = len;
+
+    if (len == 0) {
+        return E_NO_ERROR;
+    }
+
+    if (len > 256) {
+        return E_BAD_PARAM;
+    }
+
+    i2c->int_fl0 = MXC_F_I2C_INT_FL0_TX_LOCK_OUT;
+    i2c->int_fl0 = i2c->int_fl0;
+
+    // Make sure the I2C has been initialized
+    if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
+        return E_UNINITIALIZED;
+    }
+
+    // Enable master mode
+    i2c->ctrl |= MXC_F_I2C_CTRL_MST;
+
+    // Set receive count
+    i2c->rx_ctrl1= len;
+
+    i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
+
+    // Load FIFO with slave address
+    while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {}
+    i2c->fifo = (addr | 1);
+
+
+    // Wait for all data to be received or error
+    while (len > 0) {
+
+        // Check for errors
+        if (i2c->int_fl0 & I2C_ERROR) {
+            // Set the stop bit
+            i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+            return E_COMM_ERR;
+        }
+
+        if (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
+            *data++ = i2c->fifo;
+            len--;
+        }
+    }
+
+    if (i2c->int_fl0 & I2C_ERROR) {
+        // Set the stop bit
+        i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+        return E_COMM_ERR;
+    }
+
+    if (restart)  {
+        i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
+    } else {
+        i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+    }
+
+    // Wait for Done or time out if enabled
+    while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_DONE | I2C_ERROR ))) {}    
+  
+    i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
+
+    // Wait for Stop
+    if (!restart) {
+        while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_STOP | I2C_ERROR))) {
+            
+        }
+        
+        i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
+    }
+
+    // Check for errors
+    if (i2c->int_fl0 & I2C_ERROR) {
+        return E_COMM_ERR;
+    }
+
+    return save_len;
+}
+
+/* ************************************************************************** */
+int I2C_Slave(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* read_data, int read_len,
+              uint8_t* write_data, int write_len, int* tx_num, int* rx_num,
+              i2c_autoflush_disable_t sw_autoflush_disable)
+{
+    int i2c_num;
+
+    i2c_num = MXC_I2C_GET_IDX(i2c);
+    if ((read_data == NULL) && (write_data == NULL)) {
+        return E_NULL_PTR;
+    }
+
+    // Make sure the I2C has been initialized
+    if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
+        return E_UNINITIALIZED;
+    }
+
+    if ((read_len == 0) && (write_len == 0)) {
+        return E_NO_ERROR;
+    }
+
+    if (mxc_get_lock((uint32_t*)&states[i2c_num].req, 1) != E_NO_ERROR) {
+        return E_BUSY;
+    }
+    // Disable master mode
+    i2c->ctrl &= ~MXC_F_I2C_CTRL_MST;
+
+    // Clear any previous errors
+    i2c->int_fl0 = i2c->int_fl0;
+    i2c->int_fl1 = i2c->int_fl1;
+
+    // Set the slave address
+    i2c->slave_addr = (addr >> 1);
+
+    // Wait for address match
+    while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH) && !(i2c->int_fl0 & I2C_ERROR)) {
+                
+    }
+    
+    i2c->int_fl0 = MXC_F_I2C_INT_FL0_ADDR_MATCH;
+    i2c->int_fl0 = MXC_F_I2C_INT_FL0_TX_LOCK_OUT;
+
+    if (i2c->int_fl0 & I2C_ERROR) {
+        if (!sw_autoflush_disable) {
+            i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
+            i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
+        }
+        mxc_free_lock((uint32_t*)&states[i2c_num]);
+        return E_COMM_ERR;
+    }
+
+    // See if we're reading or writing
+    if (i2c->ctrl & MXC_F_I2C_CTRL_READ) {
+        // This is the master read/slave write case
+        if (read_data == NULL || read_len == 0) {
+            mxc_free_lock((uint32_t*)&states[i2c_num]);
+            return E_NULL_PTR;
+        }
+
+        // Wait for all data to be received or error
+        while (read_len > 0) {
+
+            // Check for errors
+            if (i2c->int_fl0 & I2C_ERROR) {
+                *tx_num = states[i2c_num].num_wr - ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >> MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
+                states[i2c_num].num_wr = 0;
+                if (!sw_autoflush_disable) {
+                    i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
+                }
+                mxc_free_lock((uint32_t*)&states[i2c_num]);
+                return E_COMM_ERR;
+            }
+
+            // Check for nack from master
+            if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_TX_LOCK_OUT) {
+                break;
+            }
+
+            // Check for done bit
+            if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE) {
+                break;
+            }
+
+            if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+                i2c->fifo = *read_data++;
+                states[i2c_num].num_wr++;
+                read_len--;
+            }
+        }
+
+        // Wait for Done
+        while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {}
+
+        // Calculate number of bytes sent by the slave
+        *tx_num = states[i2c_num].num_wr - ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >> MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
+        states[i2c_num].num_wr = 0;
+        if (!sw_autoflush_disable) {
+            // Flush the TX FIFO
+            i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
+        }
+
+    } else {
+        // This is the master write/slave read case
+        if (write_data == NULL || write_len == 0) {
+            mxc_free_lock((uint32_t*)&states[i2c_num]);
+            return E_NULL_PTR;
+        }
+
+        // Wait for all data to be written or error
+        while (write_len > 0) {
+
+            // Check for errors
+            if (i2c->int_fl0 & I2C_ERROR) {
+                if (!sw_autoflush_disable) {
+                    i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
+                }
+                mxc_free_lock((uint32_t*)&states[i2c_num]);
+                return E_COMM_ERR;
+            }
+
+            // Check for done bit
+            if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE) {
+                break;
+            }
+
+            if (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
+                *write_data++ = i2c->fifo;
+                (*rx_num)++;
+                write_len--;
+            }
+        }
+
+        // Wait for Done
+        while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
+            
+        }
+        // Flush the FIFO
+        if (!sw_autoflush_disable) {
+            i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
+        }
+    }
+
+    // Check for errors
+    if (i2c->int_fl0 & I2C_ERROR) {
+        // Flush the FIFO
+        if (!sw_autoflush_disable) {
+            i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
+            i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
+        }
+        mxc_free_lock((uint32_t*)&states[i2c_num]);
+        return E_COMM_ERR;
+    }
+    mxc_free_lock((uint32_t*)&states[i2c_num]);
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int I2C_MasterAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req)
+{
+    int i2c_num;
+
+    i2c_num = MXC_I2C_GET_IDX(i2c);
+    if (req->state == I2C_STATE_READING) {
+        // Check the parameters
+        if (req->rx_len == 0) {
+            return E_NO_ERROR;
+        }
+        if (req->rx_data == NULL) {
+            return E_NULL_PTR;
+        }
+
+    } else {
+        // Check the parameters
+        if (req->tx_len == 0) {
+            return E_NO_ERROR;
+        }
+        if (req->tx_data == NULL) {
+            return E_NULL_PTR;
+        }
+    }
+
+    // Make sure the I2C has been initialized
+    if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
+        return E_UNINITIALIZED;
+    }
+
+    // Attempt to register this request
+    if (mxc_get_lock((uint32_t*)&states[i2c_num].req, (uint32_t)req) != E_NO_ERROR) {
+        return E_BUSY;
+    }
+    states[i2c_num].state = req->state;
+    states[i2c_num].req = req;
+
+    // Enable master mode
+    i2c->ctrl |= MXC_F_I2C_CTRL_MST;
+
+    // Clear the byte counters
+    req->tx_num = 0;
+    req->rx_num = 0;
+
+    // Disable and clear the interrupts
+    i2c->int_en0 = 0;
+    i2c->int_en1 = 0;
+    i2c->int_fl0 = i2c->int_fl0;
+    i2c->int_fl1 = i2c->int_fl1;
+
+    // Start the transaction
+    I2C_MasterHandler(i2c);
+    return E_NO_ERROR;
+}
+
+
+/* ************************************************************************** */
+static void I2C_MasterHandler(mxc_i2c_regs_t *i2c)
+{
+
+    uint32_t int0, inten0 = 0;
+    int rx_remain, tx_remain, i2c_num;
+    i2c_req_t *req;
+
+    i2c_num = MXC_I2C_GET_IDX(i2c);
+    req = states[i2c_num].req;
+
+    // Check for errors
+    int0 = i2c->int_fl0;
+    if (int0 & I2C_ERROR) {
+
+        // Set the done bit
+        i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
+        i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+
+        i2c->int_en0 = 0;
+        if (req->callback != NULL) {
+            I2C_Recover(i2c);
+            I2C_FreeCallback(i2c_num, E_COMM_ERR);
+        }
+        return;
+    }
+
+    rx_remain = req->rx_len - req->rx_num;
+    tx_remain = req->tx_len - req->tx_num;
+    if (req->restart) {
+        //  Check for DONE interrupt
+        if ((int0 & MXC_F_I2C_INT_FL0_DONE)) {
+            // Read out any data in the RX FIFO
+            while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
+                *(req->rx_data)++ = i2c->fifo;
+                req->rx_num++;
+                rx_remain--;
+            }
+            i2c->int_en0 = 0;
+            if (req->callback != NULL) {
+                I2C_Recover(i2c);
+                I2C_FreeCallback(i2c_num, E_NO_ERROR);
+            }
+            return;
+        }
+    } else {
+        // Check for STOP interrupt
+        if ((int0 & MXC_F_I2C_INT_FL0_STOP)) {
+            i2c->int_en0 = 0;
+            if (req->callback != NULL) {
+                I2C_Recover(i2c);
+                I2C_FreeCallback(i2c_num, E_NO_ERROR);
+            }
+
+            return;
+        }
+
+        // Check for DONE interrupt
+        if ((int0 & MXC_F_I2C_INT_FL0_DONE)) {
+            // Read out any data in the RX FIFO
+            while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
+                *(req->rx_data)++ = i2c->fifo;
+                req->rx_num++;
+                rx_remain--;
+            }
+
+            return;
+        }
+    }
+
+    // Clear the interrupts
+    i2c->int_fl0 = int0;
+
+    if (states[i2c_num].state == I2C_STATE_READING) {
+
+
+        // Read out any data in the RX FIFO
+        while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
+            *(req->rx_data)++ = i2c->fifo;
+            req->rx_num++;
+            rx_remain--;
+        }
+
+        // Load the slave address if we haven't already started reading the data
+        if (rx_remain == req->rx_len) {
+            i2c->fifo = (req->addr | 1);
+
+            // Set the RX Count
+            i2c->rx_ctrl1 = req->rx_len;
+
+            // Start transmission if idle
+            if (!(i2c->status & MXC_F_I2C_STATUS_BUS)) {
+                i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
+            }
+
+            // Set restart or stop
+            if (req->restart)  {
+                i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
+            } else {
+                i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+                inten0 |= MXC_F_I2C_INT_EN0_STOP;
+            }
+        }
+
+        // Set the RX threshold interrupt level
+        if (rx_remain >= (MXC_I2C_FIFO_DEPTH - 1)) {
+            i2c->rx_ctrl1 = ((i2c->rx_ctrl1 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
+                             (MXC_I2C_FIFO_DEPTH - 1) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
+
+            inten0 |= MXC_F_I2C_INT_EN0_RX_THRESH;
+        }else{
+            i2c->rx_ctrl1 = ((i2c->rx_ctrl1 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
+                             (rx_remain) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
+
+            inten0 |= MXC_F_I2C_INT_EN0_RX_THRESH;
+        }
+
+    } else {
+
+        // Load the slave address if we haven't already started writing the data
+        if (tx_remain == req->tx_len) {
+            i2c->fifo = req->addr;
+            // Start transmission if idle
+            if (!(i2c->status &  MXC_F_I2C_STATUS_BUS)) {
+                i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
+            }
+        }
+
+        // Fill the FIFO
+        while ((tx_remain > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+            i2c->fifo = *(req->tx_data)++;
+            req->tx_num++;
+            tx_remain--;
+        }
+
+        // Set the TX threshold interrupt level, or restart/stop
+        if (tx_remain) {
+            i2c->tx_ctrl1 = ((i2c->tx_ctrl1 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) | (1 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
+            inten0 |= MXC_F_I2C_INT_EN0_TX_THRESH;
+        }
+        // Set restart or stop if at the end of the transaction since these actions happen at the moment the bit is set.
+        else if (req->restart)  {
+            i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
+        } else {
+            i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+            inten0 |= MXC_F_I2C_INT_EN0_STOP;
+        }
+    }
+
+    inten0 |= (MXC_F_I2C_INT_EN0_DONE | I2C_ERROR);
+    i2c->int_en0 = inten0;
+}
+
+/* ************************************************************************** */
+int I2C_SlaveAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req)
+{
+    int i2c_num;
+
+    i2c_num = MXC_I2C_GET_IDX(i2c);
+
+    // Make sure the I2C has been initialized
+    if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
+        return E_UNINITIALIZED;
+    }
+
+    // Attempt to register this request
+    if (mxc_get_lock((uint32_t*)&states[i2c_num].req, (uint32_t)req) != E_NO_ERROR) {
+        return E_BUSY;
+    }
+
+    states[i2c_num].req = req;
+
+    // Set Slave Address
+    i2c->slave_addr = (req->addr >> 1);
+
+    // Clear the byte counters
+    req->tx_num = 0;
+    req->rx_num = 0;
+
+    // Disable and clear the interrupts
+    i2c->int_en0 = 0;
+    i2c->int_en1 = 0;
+    i2c->int_fl0 = i2c->int_fl0;
+    i2c->int_fl1 = i2c->int_fl1;
+    i2c->int_en0 |= MXC_F_I2C_INT_EN0_ADDR_MATCH;
+
+    return E_NO_ERROR;
+}
+/* ************************************************************************** */
+static void I2C_SlaveHandler(mxc_i2c_regs_t *i2c)
+{
+    uint32_t int0, inten0 = 0;
+    int rx_remain, tx_remain, i2c_num;
+    i2c_req_t *req;
+
+    i2c_num = MXC_I2C_GET_IDX(i2c);
+    req = states[i2c_num].req;
+
+    if ( i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH ) {
+        i2c->int_fl0 |=MXC_F_I2C_INT_EN0_STOP;
+    }
+
+    // Check for errors
+    int0 = i2c->int_fl0;
+    if (int0 & I2C_ERROR) {
+        i2c->int_en0 = 0;
+        // Calculate the number of bytes sent by the slave
+        req->tx_num = states[i2c_num].num_wr - ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >> MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
+
+        if (!req->sw_autoflush_disable) {
+            // Manually clear the TXFIFO
+            i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
+        }
+        states[i2c_num].num_wr = 0;
+        if (req->callback != NULL) {
+            I2C_Recover(i2c);
+            I2C_FreeCallback(i2c_num, E_COMM_ERR);
+        }
+        return;
+    }
+
+    rx_remain = req->rx_len - req->rx_num;
+    tx_remain = req->tx_len - states[i2c_num].num_wr;
+
+    //Check if Master Write has been called and if there is a rx_data buffer
+    if ((i2c->int_fl0 & MXC_F_I2C_INT_FL0_TX_LOCK_OUT) && !(i2c->ctrl & MXC_F_I2C_CTRL_READ)) {
+
+        i2c->int_en0 = 0;
+        if (req->rx_data == NULL) {
+            I2C_Recover(i2c);
+            I2C_FreeCallback(i2c_num, E_NULL_PTR);
+            return;
+        }
+    }
+
+    // Check for DONE interrupt
+    if (int0 & MXC_F_I2C_INT_EN0_DONE) {
+        // Read out any data in the RX FIFO
+        while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
+            *(req->rx_data)++ = i2c->fifo;
+            req->rx_num++;
+            rx_remain--;
+        }
+
+        // Calculate the number of bytes sent by the slave
+        req->tx_num = states[i2c_num].num_wr - ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >> MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
+
+        if (!req->sw_autoflush_disable) {
+            // Manually clear the TXFIFO
+            i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
+        }
+        states[i2c_num].num_wr = 0;
+        i2c->int_en0 = 0;
+        if (req->callback != NULL) {
+            if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP) {
+                I2C_Recover(i2c);
+            } else {    
+                i2c->int_fl0 = i2c->int_fl0;
+                i2c->int_fl1 = i2c->int_fl1;
+            }
+            I2C_FreeCallback(i2c_num, E_NO_ERROR);
+        }
+        return;
+    }
+
+    // Clear the interrupts
+    i2c->int_fl0 = int0;
+    if (i2c->ctrl & MXC_F_I2C_CTRL_READ) {
+
+        i2c->int_en0 = 0;
+        if (req->tx_data == NULL) {
+            I2C_Recover(i2c);
+            I2C_FreeCallback(i2c_num, E_NULL_PTR);
+            return;
+        }
+        // Fill the FIFO
+        while ((tx_remain > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+            i2c->fifo = *(req->tx_data)++;
+            states[i2c_num].num_wr++;
+            tx_remain--;
+        }
+
+        // Set the TX threshold interrupt level
+        if (tx_remain) {
+            i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) | (1 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
+            inten0 |= MXC_F_I2C_INT_EN0_TX_THRESH;
+        }
+
+    } else {
+        // Read out any data in the RX FIFO
+        while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
+            *(req->rx_data)++ = i2c->fifo;
+            req->rx_num++;
+            rx_remain--;
+        }
+
+        // Set the RX threshold interrupt level
+        if (rx_remain >= (MXC_I2C_FIFO_DEPTH - 1)) {
+            i2c->rx_ctrl0 = ((i2c->rx_ctrl0 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
+                             (MXC_I2C_FIFO_DEPTH - 1) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
+
+            inten0 |= MXC_F_I2C_INT_EN0_RX_THRESH;
+        }else{
+            i2c->rx_ctrl0 = ((i2c->rx_ctrl0 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
+                 (rx_remain) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
+
+            inten0 |= MXC_F_I2C_INT_EN0_RX_THRESH;
+        }
+
+    }
+    inten0 |= (MXC_F_I2C_INT_EN0_DONE | I2C_ERROR | MXC_F_I2C_INT_EN0_TX_LOCK_OUT);
+    i2c->int_en0 = inten0;
+}
+
+/* ************************************************************************** */
+void I2C_Handler(mxc_i2c_regs_t *i2c)
+{
+    if (i2c->ctrl & MXC_F_I2C_CTRL_MST && i2c->int_fl0) {
+        // Service master interrupts if we're in master mode
+        I2C_MasterHandler(i2c);
+    } else if (i2c->int_fl0 || i2c->int_fl1) {
+        // Service the slave interrupts
+        I2C_SlaveHandler(i2c);
+    }
+}
+
+/* ************************************************************************** */
+void I2C_DrainRX(mxc_i2c_regs_t *i2c)
+{
+    i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
+}
+
+/* ************************************************************************** */
+void I2C_DrainTX(mxc_i2c_regs_t *i2c)
+{
+    i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
+}
+/* ************************************************************************* */
+static void I2C_FreeCallback(int i2c_num, int error)
+{
+    // Save the request
+    i2c_req_t *temp_req = states[i2c_num].req;
+
+    mxc_free_lock((uint32_t*)&states[i2c_num].req);
+
+    // Callback if not NULL
+    if (temp_req->callback != NULL) {
+        temp_req->callback(temp_req, error);
+    }
+}
+
+/* ************************************************************************* */
+static void I2C_Recover(mxc_i2c_regs_t *i2c)
+{
+    // Disable and clear interrupts
+    i2c->int_en0 = 0;
+    i2c->int_en1 = 0;
+    i2c->int_fl0 = i2c->int_fl0;
+    i2c->int_fl1 = i2c->int_fl1;
+    i2c->ctrl = 0;
+    i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN;
+}
+
+/* ************************************************************************* */
+int I2C_AbortAsync(i2c_req_t *req)
+{
+    int i2c_num;
+    mxc_i2c_regs_t *i2c;
+
+    // Find the request, set to NULL
+    for (i2c_num = 0; i2c_num < MXC_I2C_INSTANCES; i2c_num++) {
+        if (req == states[i2c_num].req) {
+
+            i2c = MXC_I2C_GET_I2C(i2c_num);
+            I2C_Recover(i2c);
+            I2C_FreeCallback(i2c_num, E_ABORT);
+
+            return E_NO_ERROR;
+        }
+    }
+
+    return E_BAD_PARAM;
+}
+
+/* ************************************************************************* */
+int I2C_SetTimeout(mxc_i2c_regs_t *i2c, int us){
+    uint32_t timeout;
+    timeout = (PeripheralClock/1000000) * us;
+    if(timeout > 0xFFFF){
+        return E_BAD_PARAM;
+    }
+    i2c->timeout = timeout;
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+void I2C_ClearTimeout (mxc_i2c_regs_t *i2c)
+{
+    i2c->timeout = 0;
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/i2s.c

@@ -0,0 +1,216 @@
+/**
+ * @file    i2s.c
+ * @brief   Inter-Integrated Sound (I2S) driver implementation.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ *************************************************************************** */
+
+#include <stddef.h>
+#include <stdint.h>
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "dma.h"
+#include "i2s.h"
+
+#define I2S_CHANNELS 2
+#define I2S_WIDTH    16
+
+int dma_channel = -1;
+
+int I2S_Init(const i2s_cfg_t *cfg, void (*dma_ctz_cb)(int, int), const sys_cfg_i2s_t* sys_cfg_i2s)
+{
+    unsigned int i2s_clk, baud;
+    uint16_t clocks;
+    uint8_t ctz_en;
+    int err;
+
+    SYS_I2S_Init(sys_cfg_i2s);
+
+    /* Setup SPI_MSS as master, mode 0, 16 bit transfers as I2S Requires */
+    MXC_SPIMSS->ctrl = MXC_F_SPIMSS_CTRL_MMEN;
+    MXC_SPIMSS->mod = MXC_V_SPIMSS_MOD_NUMBITS_BITS16 | MXC_F_SPIMSS_MOD_SSIO;
+    MXC_SPIMSS->dma = MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8;
+
+    /* Setup I2S register from i2s_cfg_t */
+    MXC_SPIMSS->i2s_ctrl =  cfg->left_justify << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS |
+                            cfg->mono_audio << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS;
+
+    /* Determine divisor for baud rate generator */
+    baud = cfg->sample_rate*I2S_CHANNELS*I2S_WIDTH;
+
+    i2s_clk = SYS_I2S_GetFreq(MXC_SPIMSS);
+
+    if (i2s_clk/4 < baud) {
+        return E_BAD_PARAM;
+    }
+
+    clocks = i2s_clk / (2*baud);
+    MXC_SPIMSS->brg = clocks;
+
+    /* Prepare SPIMSS DMA register for DMA setup */
+    if (dma_ctz_cb == NULL) {
+        ctz_en = 0;
+    } else {
+        ctz_en = 1;
+    }
+
+    /* Initialize DMA */
+    if (cfg->audio_direction % 2) {
+        MXC_SPIMSS->dma |= MXC_F_SPIMSS_DMA_TX_DMA_EN | MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR;
+        if ((err = DMA_Init()) != E_NO_ERROR) {
+            if (err != E_BAD_STATE) {
+                return err;
+            }
+        }
+
+        if ((err = DMA_AcquireChannel()) < 0) {
+            return err;
+        }
+
+        dma_channel = err;
+
+        DMA_ConfigChannel(dma_channel, DMA_PRIO_MEDHIGH,
+              sys_cfg_i2s->dma_reqsel_tx, 1, DMA_TIMEOUT_512_CLK,
+              DMA_PRESCALE_DIV64K, DMA_WIDTH_HALFWORD, 1,
+              DMA_WIDTH_HALFWORD, 0, 16, 0, ctz_en);
+
+        if (ctz_en) {
+            DMA_SetCallback(dma_channel, dma_ctz_cb);
+            DMA_EnableInterrupt(dma_channel);
+        }
+    }
+    if (cfg->audio_direction / 2) {
+        MXC_SPIMSS->dma = MXC_F_SPIMSS_DMA_RX_DMA_EN | MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR;
+        if ((err = DMA_Init()) != E_NO_ERROR) {
+            if (err != E_BAD_STATE) {    //DMA already initialized
+                return err;
+            }
+        }
+
+        if ((err = DMA_AcquireChannel()) < 0) {
+            return err;
+        }
+
+        dma_channel = err;
+
+        DMA_ConfigChannel(dma_channel, DMA_PRIO_MEDHIGH,
+                        sys_cfg_i2s->dma_reqsel_rx, 1, DMA_TIMEOUT_512_CLK,
+                        DMA_PRESCALE_DIV64K, DMA_WIDTH_HALFWORD, 0,
+                        DMA_WIDTH_HALFWORD, 1, 8, 0, ctz_en);
+
+        if (ctz_en) {
+            DMA_SetCallback(dma_channel, dma_ctz_cb);
+            DMA_EnableInterrupt(dma_channel);
+        }
+    }
+
+    I2S_DMA_SetAddrCnt(cfg->dma_src_addr, cfg->dma_dst_addr, cfg->dma_cnt);
+    if (cfg->dma_reload_en) {
+        I2S_DMA_SetReload(cfg->dma_src_addr, cfg->dma_dst_addr, cfg->dma_cnt);
+    }
+
+    if (cfg->start_immediately) {
+        return I2S_Start();
+    }
+    return E_NO_ERROR;
+}
+
+int I2S_Shutdown(void)
+{
+    MXC_SPIMSS->ctrl = 0;
+    MXC_SPIMSS->i2s_ctrl = 0;
+    MXC_SPIMSS->brg = 0;
+    MXC_SPIMSS->mod = 0;
+    MXC_SPIMSS->dma = 0;
+    SYS_I2S_Shutdown();
+    return DMA_ReleaseChannel(dma_channel);
+}
+
+int I2S_Mute(void)
+{
+    MXC_SPIMSS->i2s_ctrl |= MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE;
+    return E_NO_ERROR;
+}
+
+int I2S_Unmute(void)
+{
+    MXC_SPIMSS->i2s_ctrl &= ~MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE;
+    return E_NO_ERROR;
+}
+
+int I2S_Pause(void)
+{
+    MXC_SPIMSS->i2s_ctrl |= MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE;
+    return E_NO_ERROR;
+}
+
+int I2S_Unpause(void)
+{
+    MXC_SPIMSS->i2s_ctrl &= ~MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE;
+    return E_NO_ERROR;
+}
+
+int I2S_Stop(void)
+{
+    MXC_SPIMSS->ctrl &= ~MXC_F_SPIMSS_CTRL_SPIEN;
+    MXC_SPIMSS->i2s_ctrl &= ~MXC_F_SPIMSS_I2S_CTRL_I2S_EN;
+    return DMA_Stop(dma_channel);
+}
+
+int I2S_Start(void)
+{
+    MXC_SPIMSS->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN;
+    MXC_SPIMSS->i2s_ctrl |= MXC_F_SPIMSS_I2S_CTRL_I2S_EN;
+    return DMA_Start(dma_channel);
+}
+
+int I2S_DMA_ClearFlags(void)
+{
+    return DMA_ClearFlags(dma_channel);
+}
+
+int I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count)
+{
+    return DMA_SetSrcDstCnt(dma_channel, src_addr, dst_addr, count);
+}
+
+int I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count)
+{
+    return DMA_SetReload(dma_channel, src_addr, dst_addr, count);
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/icc.c

@@ -0,0 +1,84 @@
+/* *****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <stdint.h>
+#include <stdio.h>
+#include "mxc_config.h"
+#include "mxc_errors.h"
+#include "icc_regs.h"
+#include "icc.h"
+
+static int ICC_Ready(void)
+{
+    return (MXC_ICC->cache_ctrl & MXC_F_ICC_CACHE_CTRL_CACHE_RDY);
+}
+
+int ICC_ID(icc_cache_id_t cid)
+{
+    switch (cid) {
+        case ICC_CACHE_ID_RELNUM:
+            return ((MXC_ICC->cache_id & MXC_F_ICC_CACHE_ID_RELNUM) >> MXC_F_ICC_CACHE_ID_RELNUM_POS);
+        case ICC_CACHE_ID_PARTNUM:
+            return ((MXC_ICC->cache_id & MXC_F_ICC_CACHE_ID_PARTNUM) >> MXC_F_ICC_CACHE_ID_PARTNUM_POS);
+        case ICC_CACHE_ID_CCHID:
+            return ((MXC_ICC->cache_id & MXC_F_ICC_CACHE_ID_CCHID) >> MXC_F_ICC_CACHE_ID_CCHID_POS);
+        default:
+            return E_BAD_PARAM;
+    }
+}
+
+void ICC_Enable(void)
+{
+    // Invalidate cache and wait until ready
+    MXC_ICC->invalidate = 1;
+    while (!(ICC_Ready()));
+    
+    // Enable Cache
+    MXC_ICC->cache_ctrl |= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
+}
+
+void ICC_Disable(void)
+{
+    // Disable Cache
+    MXC_ICC->cache_ctrl &= ~MXC_F_ICC_CACHE_CTRL_CACHE_EN;
+}
+
+void ICC_Flush(void)
+{
+    ICC_Disable();
+    ICC_Enable();
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/lp.c

@@ -0,0 +1,371 @@
+/**
+ * @file    lp.c
+ * @brief   Low power functions
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-10-07 11:05:30 -0500 (Mon, 07 Oct 2019) $
+ * $Revision: 47429 $
+ *
+ *************************************************************************** */
+
+
+/***** Includes *****/
+#include "lp.h"
+#include "pwrseq_regs.h"
+#include "mxc_errors.h"
+#include "gcr_regs.h"
+#include "mxc_config.h"
+#include "mxc_sys.h"
+#include "flc.h"
+#include "tmr_utils.h"
+
+/***** Functions *****/
+void LP_ClearWakeStatus(void)
+{
+    MXC_PWRSEQ->lp_wakefl = 0xFFFFFFFF;
+
+    /* These flags are slow to clear, so block until they do */
+    while(MXC_PWRSEQ->lp_wakefl & (MXC_PWRSEQ->lpwk_en));
+}
+
+void LP_EnableSRAM3(void)
+{
+    MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF;
+}
+
+void LP_DisableSRAM3(void)
+{
+    MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF;
+}
+
+void LP_EnableSRAM2(void)
+{
+    MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF;
+}
+
+void LP_DisableSRAM2(void)
+{
+    MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF;
+}
+
+void LP_EnableSRAM1(void)
+{
+    MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF;
+}
+
+void LP_DisableSRAM1(void)
+{
+    MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF;
+}
+
+void LP_EnableSRAM0(void)
+{
+    MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF;
+}
+
+void LP_DisableSRAM0(void)
+{
+    MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF;
+}
+
+void LP_EnableICacheLightSleep(void)
+{
+    MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_ICACHELS);
+}
+
+void LP_DisableICacheLightSleep(void)
+{
+    MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_ICACHELS);
+}
+
+void LP_EnableSysRAM3LightSleep(void)
+{
+    MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM3LS);
+}
+
+void LP_DisableSysRAM3LightSleep(void)
+{
+    MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM3LS);
+}
+
+void LP_EnableSysRAM2LightSleep(void)
+{
+    MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM2LS);
+}
+
+void LP_DisableSysRAM2LightSleep(void)
+{
+    MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM2LS);
+}
+
+void LP_EnableSysRAM1LightSleep(void)
+{
+    MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM1LS);
+}
+
+void LP_DisableSysRAM1LightSleep(void)
+{
+    MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM1LS);
+}
+
+void LP_EnableSysRAM0LightSleep(void)
+{
+    MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM0LS);
+}
+
+void LP_DisableSysRAM0LightSleep(void)
+{
+    MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM0LS);
+}
+
+void LP_EnableRTCAlarmWakeup(void)
+{
+    MXC_GCR->pm |= MXC_F_GCR_PM_RTCWKEN;
+}
+    
+void LP_DisableRTCAlarmWakeup(void)
+{
+    MXC_GCR->pm &= ~MXC_F_GCR_PM_RTCWKEN;
+}
+
+void LP_EnableGPIOWakeup(const gpio_cfg_t *wu_pins)
+{
+    MXC_GCR->pm |= MXC_F_GCR_PM_GPIOWKEN;
+    switch(wu_pins->port)
+    {
+      case 0: MXC_PWRSEQ->lpwk_en |= wu_pins->mask; break;
+    }
+}
+
+void LP_DisableGPIOWakeup(const gpio_cfg_t *wu_pins)
+{
+    switch(wu_pins->port)
+    {
+      case 0: MXC_PWRSEQ->lpwk_en &= ~wu_pins->mask; break;
+    }
+    
+    if(MXC_PWRSEQ->lpwk_en == 0)
+    {
+        MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIOWKEN;
+    }
+}
+
+void LP_EnterSleepMode(void)
+{    
+    // Clear SLEEPDEEP bit 
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+
+    // Go into Sleep mode and wait for an interrupt to wake the processor 
+    __WFI();
+}
+
+void LP_EnterDeepSleepMode(void)
+{    
+    // Set SLEEPDEEP bit 
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    // Auto-powerdown 96 MHz oscillator when in deep sleep 
+    MXC_GCR->pm |= MXC_F_GCR_PM_HIRCPD;
+    // Go into Deepsleep mode and wait for an interrupt to wake the processor 
+    __WFI();
+}
+
+void LP_EnterBackupMode(void)
+{    
+    MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
+    MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP;
+    while(1);
+}
+
+void LP_EnterShutdownMode(void)
+{
+    MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
+    MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN;
+    while(1);
+}
+void LP_SetOperatingVoltage(lp_ovr_t ovr)
+{
+    uint32_t div;
+
+    //Set flash wait state for any clock so its not to low after clock changes.
+    MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x5UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+    //set the OVR bits
+    MXC_PWRSEQ->lp_ctrl &= ~(MXC_F_PWRSEQ_LP_CTRL_OVR);
+    MXC_PWRSEQ->lp_ctrl |= ovr;
+
+    //Set LVE bit
+    if(ovr == LP_OVR_0_9){
+        MXC_FLC->cn |= MXC_F_FLC_CN_LVE;
+    }
+    else{
+        MXC_FLC->cn &= ~(MXC_F_FLC_CN_LVE);
+    }
+
+    // Update SystemCoreClock variable
+    SystemCoreClockUpdate();
+
+    // Get the clock divider
+    div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS;
+
+    //Set Flash Wait States
+    if(ovr == LP_OVR_0_9){
+
+        if(div == 0){
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        } else{
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        }
+
+    } else if( ovr == LP_OVR_1_0){  
+        if(div == 0){
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        } else{
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        }
+
+    } else {
+
+        if(div == 0){
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x4UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+        } else if(div == 1){
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        } else{
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        }
+    }
+
+}
+
+void LP_EnableSRamRet0(void){
+    MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0;
+}
+ 
+void LP_DisableSRamRet0(void){
+    MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0;
+}
+
+void LP_EnableSRamRet1(void){
+    MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1;
+}
+ 
+void LP_DisableSRamRet1(void){
+    MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1;
+}
+
+void LP_EnableSRamRet2(void){
+    MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2;
+}
+ 
+void LP_DisableSRamRet2(void){
+    MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2;
+}
+
+void LP_EnableSRamRet3(void){
+    MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3;
+}
+ 
+void LP_DisableSRamRet3(void){
+    MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3;
+}
+
+void LP_EnableBlockDetect(void){
+    MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS; 
+}
+
+void LP_DisableBlockDetect(void){
+    MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS; 
+}
+
+void LP_EnableRamRetReg(void){
+    MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RETREG_EN;
+}
+
+void LP_DisableRamRetReg(void){
+    MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RETREG_EN;
+}
+
+void LP_EnableFastWk(void){
+    MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN;
+}
+
+void LP_DisableFastWk(void){
+    MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN;
+}
+
+void LP_EnableBandGap(void){
+    MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_BG_OFF;
+}
+
+void LP_DisableBandGap(void){
+    MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_BG_OFF;
+}
+
+void LP_EnableVCorePORSignal(void){
+    MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS;
+}
+
+void LP_DisableVCorePORSignal(void){
+    MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS;
+}
+
+void LP_EnableLDO(void){
+    MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_LDO_DIS;
+}
+
+void LP_DisableLDO(void){
+    MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_LDO_DIS;
+}
+
+void LP_EnableVCoreSVM(void){
+    MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS;
+}
+
+void LP_DisableVCoreSVM(void){
+    MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS;
+}
+
+void LP_EnableVDDIOPorMonitoF(void){
+    MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS;
+}
+
+void LP_DisableVDDIOPorMonitor(void){
+    MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS;
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/mxc_assert.c

@@ -0,0 +1,50 @@
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
+ * $Revision: 36818 $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_config.h"
+
+/* **** Definitions **** */
+
+/* **** Globals *****/
+
+/* **** Functions **** */
+
+/* ************************************************************************** */
+__weak void mxc_assert(const char *expr, const char *file, int line)
+{
+    while (1) {}
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/mxc_delay.c

@@ -0,0 +1,179 @@
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Id: mxc_delay.c 36202 2018-07-16 21:06:02Z michael.bayern $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <stdint.h>
+#include "mxc_config.h"
+#include "mxc_delay.h"
+
+/* **** File Scope Variables **** */
+static uint32_t ctrl_save;
+static volatile uint64_t compare_value = 0;
+static volatile uint64_t curr_value;
+static volatile uint32_t reload;
+
+static void mxc_delay_init(unsigned long us);
+extern void SysTick_Handler(void);
+
+/* ************************************************************************** */
+__weak void SysTick_Handler(void) 
+{
+    mxc_delay_handler();
+}
+
+/* ************************************************************************** */
+void mxc_delay_handler(void)
+{
+    // Check and clear overflow flag
+    if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) {
+    	// Is a delay in progress?
+    	if(compare_value != 0) {
+    		curr_value += reload;
+    		if(curr_value >= compare_value)	{
+            	mxc_delay_stop();
+        	}
+        }
+    }
+}
+
+/* ************************************************************************** */
+static void mxc_delay_init(unsigned long us)
+{
+    uint32_t starttick, ticks;
+    
+    // Record the current tick value and clear the overflow flag
+    starttick = SysTick->VAL;
+    
+    // Save the state of control register (and clear the overflow flag)
+    ctrl_save = SysTick->CTRL & ~SysTick_CTRL_COUNTFLAG_Msk;
+    
+    // If the SysTick is not running, configure and start it
+    if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
+        SysTick->LOAD = SysTick_LOAD_RELOAD_Msk;
+        SysTick->VAL = SysTick_VAL_CURRENT_Msk;
+        SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk;
+        starttick = SysTick_VAL_CURRENT_Msk;
+        reload = SysTick_LOAD_RELOAD_Msk + 1;
+    } else {
+        reload = SysTick->LOAD + 1; // get the current reload value
+    }
+
+    // Calculate the total number of ticks to delay
+    ticks = (uint32_t)(((uint64_t)us * (uint64_t)SystemCoreClock) / 1000000);
+
+    compare_value = ticks + (reload - starttick);
+    curr_value = 0;
+    
+    if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
+        SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+    }
+}
+
+/* ************************************************************************** */
+int mxc_delay_start(unsigned long us)
+{
+    // Check if timeout currently ongoing
+    if (compare_value != 0) {
+        return E_BUSY;
+    }
+    
+    // Check if there is nothing to do
+    if (us == 0) {
+        return E_NO_ERROR;
+    }
+    
+    // Calculate the necessary delay and start the timer
+    mxc_delay_init(us);
+    
+    // Enable SysTick interrupt if necessary
+    if (compare_value != 0) {
+        SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    }
+    
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int mxc_delay_check(void)
+{
+    // Check if timeout currently ongoing
+    if (compare_value == 0) {
+        return E_NO_ERROR;
+    }
+    
+    if((curr_value + (reload - SysTick->VAL)) >= compare_value) {
+        mxc_delay_stop();
+        return E_NO_ERROR;
+    }
+
+    return E_BUSY;
+}
+
+/* ************************************************************************** */
+void mxc_delay_stop(void)
+{
+    SysTick->CTRL = ctrl_save;
+    compare_value = 0;
+}
+
+/* ************************************************************************** */
+int mxc_delay(unsigned long us)
+{
+    // Check if timeout currently ongoing
+    if (compare_value != 0) {
+        return E_BUSY;
+    }
+    
+    // Check if there is nothing to do
+    if (us == 0) {
+        return E_NO_ERROR;
+    }
+    
+    // Calculate the necessary delay and start the timer
+    mxc_delay_init(us);
+    
+    // Wait until the total number of ticks exceeds the compare value.
+    while ((curr_value + (reload - SysTick->VAL)) < compare_value) {
+        // If SysTick interrupts are enabled, COUNTFLAG will never be set here and
+        // curr_value will be incremented in the ISR. If SysTick interrupts are
+        // disabled, curr_value is incremented here.
+        if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) {
+	    	curr_value += reload;
+        }
+    }
+
+    mxc_delay_stop();
+    return E_NO_ERROR;
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/mxc_lock.c

@@ -0,0 +1,85 @@
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_LOCK_H_
+#define _MXC_LOCK_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "mxc_lock.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined ( __ICCARM__ )
+    #define MXC_LOCK_CAST unsigned int volatile *
+#else
+    #define MXC_LOCK_CAST volatile unsigned long *
+#endif
+
+/* ************************************************************************** */
+int mxc_get_lock(uint32_t *lock, uint32_t value)
+{
+    do {
+
+        // Return if the lock is taken by a different thread
+        if(__LDREXW((MXC_LOCK_CAST)lock) != 0) {
+            return E_BUSY;
+        }
+
+        // Attempt to take the lock
+    } while(__STREXW(value, (MXC_LOCK_CAST)lock) != 0);
+
+    // Do not start any other memory access until memory barrier is complete
+    __DMB();
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+void mxc_free_lock(uint32_t *lock)
+{
+    // Ensure memory operations complete before releasing lock
+    __DMB();
+    *lock = 0;
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _MXC_LOCK_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Source/mxc_pins.c

@@ -0,0 +1,79 @@
+ /**
+ * @file mxc_pins.c
+ * @brief      This file contains constant pin configurations for the peripherals.
+ */
+
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "gpio.h"
+#include "mxc_config.h"
+
+/**
+ * @ingroup MXC_pins
+ * @{
+ */
+
+/* **** TIMER pins **** */
+const gpio_cfg_t gpio_cfg_tmr0         =    { PORT_0, PIN_3, GPIO_FUNC_ALT3, GPIO_PAD_NONE };
+
+/* **** UART pins **** */
+const gpio_cfg_t gpio_cfg_uart0rtscts  =   { PORT_0, (PIN_6 | PIN_7), GPIO_FUNC_ALT2, GPIO_PAD_NONE };
+const gpio_cfg_t gpio_cfg_uart0a       =   { PORT_0, (PIN_4 | PIN_5), GPIO_FUNC_ALT2, GPIO_PAD_NONE };
+const gpio_cfg_t gpio_cfg_uart1rtscts  =   { PORT_0, (PIN_12 | PIN_13), GPIO_FUNC_ALT2, GPIO_PAD_NONE };
+const gpio_cfg_t gpio_cfg_uart1a       =   { PORT_0, (PIN_10 | PIN_11), GPIO_FUNC_ALT2, GPIO_PAD_NONE };
+const gpio_cfg_t gpio_cfg_uart1b       =   { PORT_0, (PIN_0 | PIN_1), GPIO_FUNC_ALT3, GPIO_PAD_NONE };
+const gpio_cfg_t gpio_cfg_uart1c       =   { PORT_0, (PIN_6 | PIN_7), GPIO_FUNC_ALT3, GPIO_PAD_NONE };
+
+/* **** I2C pins **** */
+const gpio_cfg_t gpio_cfg_i2c0         =   { PORT_0, (PIN_8 | PIN_9), GPIO_FUNC_ALT1, GPIO_PAD_PULL_UP };
+const gpio_cfg_t gpio_cfg_i2c1         =   { PORT_0, (PIN_2 | PIN_3), GPIO_FUNC_ALT1, GPIO_PAD_PULL_UP };
+
+/* **** SPI/I2S pins **** */
+const gpio_cfg_t gpio_cfg_spi17y       =   { PORT_0, (PIN_4 | PIN_5 | PIN_6 | PIN_7), GPIO_FUNC_ALT1, GPIO_PAD_NONE };          // SPI0A
+const gpio_cfg_t gpio_cfg_spimss1a     =   { PORT_0, (PIN_10  | PIN_11  | PIN_12  | PIN_13) , GPIO_FUNC_ALT1, GPIO_PAD_NONE };  // SPI1A
+const gpio_cfg_t gpio_cfg_spimss1b     =   { PORT_0, (PIN_0   | PIN_1   | PIN_2   | PIN_3 ) , GPIO_FUNC_ALT2, GPIO_PAD_NONE };  // SPI1B
+const gpio_cfg_t gpio_cfg_i2s1a        =   { PORT_0, (PIN_10  | PIN_11  | PIN_12  | PIN_13) , GPIO_FUNC_ALT1, GPIO_PAD_NONE };  // same port as SPI1A
+const gpio_cfg_t gpio_cfg_i2s1b        =   { PORT_0, (PIN_0   | PIN_1   | PIN_2   | PIN_3 ) , GPIO_FUNC_ALT2, GPIO_PAD_NONE };  // same port as SPI1B
+
+/* **** SWD pins **** */
+const gpio_cfg_t gpio_cfg_swd          =   { PORT_0, (PIN_0   | PIN_1   | PIN_2   | PIN_3 ) , GPIO_FUNC_ALT1, GPIO_PAD_NONE };
+
+/* **** RTC pins **** */
+const gpio_cfg_t gpio_cfg_rtc          =   { PORT_0, PIN_2, GPIO_FUNC_ALT3, GPIO_PAD_NONE };
+
+/**@} end of ingroup MXC_pins*/

bsp/maxim/libraries/MAX32660PeriphDriver/Source/mxc_sys.c

@@ -0,0 +1,721 @@
+/**
+ * @file    mxc_sys.c
+ * @brief   System level setup help
+ */
+
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2020-01-17 08:38:51 -0600 (Fri, 17 Jan 2020) $
+ * $Revision: 50772 $
+ *
+ ******************************************************************************/
+
+#include <stddef.h>
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "gpio.h"
+#include "mxc_pins.h"
+#include "gcr_regs.h"
+#include "tmr_regs.h"
+#include "pwrseq_regs.h"
+#include "spi17y_regs.h"
+#include "spimss_regs.h"
+#include "mxc_delay.h"
+#include "rtc.h"
+
+/**
+ * @ingroup MXC_sys
+ * @{
+ */
+
+/***** Definitions *****/
+#define SYS_CLOCK_TIMEOUT       MXC_DELAY_MSEC(1)
+
+#define SYS_RTC_CLK 32768UL
+
+/***** Functions ******/
+static int SYS_Clock_Timeout(uint32_t ready)
+{
+    // Start timeout, wait for ready
+    mxc_delay_start(SYS_CLOCK_TIMEOUT);
+    do {
+        if (MXC_GCR->clkcn & ready) {
+            mxc_delay_stop();
+            return E_NO_ERROR;
+        }
+    } while (mxc_delay_check() == E_BUSY);
+
+    return E_TIME_OUT;
+}
+
+/* ************************************************************************ */
+int SYS_Clock_Select(sys_system_clock_t clock, mxc_tmr_regs_t* tmr)
+{
+    uint32_t current_clock,ovr, div;
+
+    // Save the current system clock
+    current_clock = MXC_GCR->clkcn & MXC_F_GCR_CLKCN_CLKSEL;
+    // Set FWS higher than what the minimum for the fastest clock is
+    MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x5UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+    switch(clock) {
+        case SYS_CLOCK_NANORING:
+            // Set NANORING clock as System Clock
+            MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, MXC_S_GCR_CLKCN_CLKSEL_NANORING);
+
+        break;
+        case SYS_CLOCK_HFXIN:
+            // Enable 32k Oscillator
+            MXC_GCR->clkcn |=MXC_F_GCR_CLKCN_X32K_EN;
+
+            // Check if 32k clock is ready
+            if (SYS_Clock_Timeout(MXC_F_GCR_CLKCN_X32K_RDY) != E_NO_ERROR) {
+                return E_TIME_OUT;
+            }
+            MXC_RTC->ctrl |= MXC_F_RTC_CTRL_WE;      // Allow writing to registers
+
+            // Set 32k clock as System Clock
+            MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, MXC_S_GCR_CLKCN_CLKSEL_HFXIN);
+
+        break;
+
+        case SYS_CLOCK_HFXIN_DIGITAL:
+            // Enable 32k Oscillator
+            MXC_GCR->clkcn |=MXC_F_GCR_CLKCN_X32K_EN;
+
+            // Check if 32k clock is ready
+            if (SYS_Clock_Timeout(MXC_F_GCR_CLKCN_X32K_RDY) != E_NO_ERROR) {
+                return E_TIME_OUT;
+            }
+            MXC_RTC->ctrl |= MXC_F_RTC_CTRL_WE;      // Allow writing to registers
+            MXC_RTC->oscctrl |= MXC_F_RTC_OSCCTRL_BYPASS;  // To allow square wave driven on 32KIN
+            // Set 32k clock as System Clock
+            MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, MXC_S_GCR_CLKCN_CLKSEL_HFXIN);
+
+        break;
+        case SYS_CLOCK_HIRC:
+            // Enable 96MHz Clock
+            MXC_GCR->clkcn |=MXC_F_GCR_CLKCN_HIRC_EN;
+
+            // Check if 96MHz clock is ready
+            if (SYS_Clock_Timeout(MXC_F_GCR_CLKCN_HIRC_RDY) != E_NO_ERROR) {
+                return E_TIME_OUT;
+            }
+
+            // Set 96MHz clock as System Clock
+            MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, MXC_S_GCR_CLKCN_CLKSEL_HIRC);
+
+        break;
+        default:
+        return E_BAD_PARAM;
+    }
+
+    // Wait for system clock to be ready
+    if (SYS_Clock_Timeout(MXC_F_GCR_CLKCN_CKRDY) != E_NO_ERROR) {
+
+        // Restore the old system clock if timeout
+        MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, current_clock);
+
+        return E_TIME_OUT;
+    }
+
+    // Disable other clocks
+    switch(clock) {
+        case SYS_CLOCK_NANORING:
+            MXC_GCR->clkcn &= ~(MXC_F_GCR_CLKCN_HIRC_EN);
+        break;
+
+        case SYS_CLOCK_HFXIN:
+            MXC_GCR->clkcn &= ~(MXC_F_GCR_CLKCN_HIRC_EN);
+        break;
+
+        case SYS_CLOCK_HFXIN_DIGITAL:
+            MXC_GCR->clkcn &= ~(MXC_F_GCR_CLKCN_HIRC_EN);
+        break;
+
+        case SYS_CLOCK_HIRC:
+            //Don't disable 32KHz clock
+        break;
+    }
+
+    // Update the system core clock
+    SystemCoreClockUpdate();
+
+    // Get the clock divider
+    div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS;
+
+    //get ovr setting
+    ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
+
+    //Set flash wait settings
+    if(ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V){
+
+        if(div == 0){
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        } else{
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        }
+
+    } else if( ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V){
+        if(div == 0){
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        } else{
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        }
+
+    } else {
+
+        if(div == 0){
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x4UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        } else if(div == 1){
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        } else{
+            MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
+
+        }
+    }
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_ClockEnable_X32K(sys_cfg_rtc_t *sys_cfg)
+{
+    // Enable 32k Oscillator
+    MXC_GCR->clkcn |=MXC_F_GCR_CLKCN_X32K_EN;
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_ClockDisable_X32K()
+{
+    // Disable 32k Oscillator
+    MXC_GCR->clkcn &= (~MXC_F_GCR_CLKCN_X32K_EN);
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_UART_Init(mxc_uart_regs_t *uart, const sys_cfg_uart_t* sys_cfg)
+{
+        // Configure GPIO for UART
+    if (uart == MXC_UART0) {
+        SYS_ClockEnable(SYS_PERIPH_CLOCK_UART0);
+        if(sys_cfg->map == MAP_A){
+            GPIO_Config(&gpio_cfg_uart0a);
+        }
+        else{
+            return E_BAD_PARAM;
+        }
+        if(sys_cfg->flow_flag == UART_FLOW_ENABLE){
+            GPIO_Config(&gpio_cfg_uart0rtscts);
+        }
+    }
+    if (uart == MXC_UART1) {
+        SYS_ClockEnable(SYS_PERIPH_CLOCK_UART1);
+        if(sys_cfg->map == MAP_A){
+            GPIO_Config(&gpio_cfg_uart1a);
+        }
+        else if(sys_cfg->map == MAP_B){
+            GPIO_Config(&gpio_cfg_uart1b);
+        }
+        else if(sys_cfg->map == MAP_C){
+            GPIO_Config(&gpio_cfg_uart1c);
+        }
+        else{
+            return E_BAD_PARAM;
+        }
+        if(sys_cfg->flow_flag == UART_FLOW_ENABLE){
+            GPIO_Config(&gpio_cfg_uart1rtscts);
+        }
+    }
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_UART_Shutdown(mxc_uart_regs_t *uart)
+{
+    if (uart == MXC_UART0) {
+        SYS_ClockDisable(SYS_PERIPH_CLOCK_UART0);
+    }
+    else if (uart == MXC_UART1) {
+        SYS_ClockDisable(SYS_PERIPH_CLOCK_UART1);
+    }
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_I2C_Init(mxc_i2c_regs_t *i2c,  const sys_cfg_i2c_t* sys_cfg)
+{
+
+    // Configure GPIO for I2C
+    if (i2c == MXC_I2C0) {
+        SYS_ClockEnable(SYS_PERIPH_CLOCK_I2C0);
+        GPIO_Config(&gpio_cfg_i2c0);
+
+    } else if (i2c == MXC_I2C1) {
+        SYS_ClockEnable(SYS_PERIPH_CLOCK_I2C1);
+        GPIO_Config(&gpio_cfg_i2c1);
+    } else {
+        return E_NO_DEVICE;
+    }
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_I2C_Shutdown(mxc_i2c_regs_t *i2c)
+{
+    if (i2c == MXC_I2C0) {
+        gpio_cfg_t cfg = { gpio_cfg_i2c0.port, gpio_cfg_i2c0.mask, GPIO_FUNC_IN, GPIO_PAD_NONE };
+        SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C0);
+        GPIO_Config(&cfg);
+    } else if (i2c == MXC_I2C1) {
+        gpio_cfg_t cfg = { gpio_cfg_i2c1.port, gpio_cfg_i2c1.mask, GPIO_FUNC_IN, GPIO_PAD_NONE };
+        SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C1);
+        GPIO_Config(&cfg);
+    } else {
+        return E_NO_DEVICE;
+    }
+    // Clear registers
+    i2c->ctrl = 0;
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_DMA_Init(void)
+{
+    SYS_ClockEnable(SYS_PERIPH_CLOCK_DMA);
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_DMA_Shutdown(void)
+{
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_DMA);
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+unsigned SYS_I2C_GetFreq(mxc_i2c_regs_t *i2c)
+{
+    return PeripheralClock;
+}
+
+/* ************************************************************************ */
+unsigned SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr)
+{
+    return PeripheralClock;
+}
+
+/* ************************************************************************ */
+void SYS_Reset0(sys_reset0_t reset)
+{
+    MXC_GCR->rstr0 = reset;
+    while(MXC_GCR->rstr0 != 0x0) {}
+}
+
+/* ************************************************************************ */
+void SYS_Reset1(sys_reset1_t reset)
+{
+    MXC_GCR->rstr1 = reset;
+    while(MXC_GCR->rstr0 != 0x0) {}
+}
+
+/* ************************************************************************ */
+void SYS_ClockDisable(sys_periph_clock_t clock)
+{
+    /* The sys_periph_clock_t enum uses bit 27 (an unused bit in both perkcn registers)
+       to determine which of the two perckcn registers to write to. */
+    if (clock & (1<<27)) {
+        clock &= ~(1<<27);
+        MXC_GCR->perckcn1 |= clock;
+    } else {
+        MXC_GCR->perckcn0 |= clock;
+    }
+}
+
+/* ************************************************************************ */
+void SYS_ClockEnable(sys_periph_clock_t clock)
+{
+    /* The sys_periph_clock_t enum uses bit 27 (an unused bit in both perkcn registers)
+       to determine which of the two perckcn registers to write to. */
+    if (clock & (1<<27)) {
+        clock &= ~(1<<27);
+        MXC_GCR->perckcn1 &= ~(clock);
+    } else {
+        MXC_GCR->perckcn0 &= ~(clock);
+    }
+}
+
+/* ************************************************************************ */
+#if defined (__ICCARM__)
+#pragma optimize=none           /* Turn off optimizations for next function */
+#elif defined ( __CC_ARM )
+/* Keil MDK - Turn off optimizations after saving current state */
+#pragma push                    /* Save current optimization level */
+#pragma O0                      /* Optimization level 0 */
+#elif ( __GNUC__ )
+/* GCC - Turn off optimizations after saving current state */
+#pragma GCC push_options        /* Save current optimization level */
+#pragma GCC optimize ("O0")     /* Set optimization level to none for this function */
+#endif
+void SYS_Flash_Operation(void)
+{
+    volatile uint32_t *line_addr;
+    volatile uint32_t __attribute__ ((unused)) line;
+
+    // Clear the cache
+    MXC_ICC->cache_ctrl ^= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
+    MXC_ICC->cache_ctrl ^= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
+
+    // Clear the line fill buffer
+    line_addr = (uint32_t*)(MXC_FLASH_MEM_BASE);
+    line = *line_addr;
+
+    line_addr = (uint32_t*)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE);
+    line = *line_addr;
+}
+/* Set optimizations to the previous level. For IAR, the optimize none applies
+   only to the next function. Keil MDK and GNUC need state restored. */
+#if defined ( __CC_ARM )
+#pragma pop                     /* Restore Kiel MDK optimizations to saved level */
+#elif defined ( __GNUC__ )
+#pragma GCC pop_options         /* Restore GCC optimization level */
+#endif
+
+/* ************************************************************************ */
+int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t* sys_cfg)
+{
+    if(sys_cfg) {
+        if(sys_cfg->out_en) {
+
+            if (tmr == MXC_TMR0) {
+                GPIO_Config(&gpio_cfg_tmr0);
+            }
+        }
+    }
+
+    if (tmr == MXC_TMR0) {
+        SYS_ClockEnable(SYS_PERIPH_CLOCK_T0);
+    }
+    else if (tmr == MXC_TMR1) {
+        SYS_ClockEnable(SYS_PERIPH_CLOCK_T1);
+    }
+    else if (tmr == MXC_TMR2) {
+        SYS_ClockEnable(SYS_PERIPH_CLOCK_T2);
+    }
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_FLC_Init(const sys_cfg_flc_t* sys_cfg)
+{
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_FLC_Shutdown(void)
+{
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_SPI17Y_Init(mxc_spi17y_regs_t *spi, const sys_cfg_spi17y_t* sys_cfg)
+{
+    // Configure GPIO for spi17y
+    if (spi == MXC_SPI17Y) {
+        SYS_ClockEnable(SYS_PERIPH_CLOCK_SPI17Y);
+        if(sys_cfg->map == MAP_A){
+            GPIO_Config(&gpio_cfg_spi17y);
+             MXC_GPIO0->ds |= 0x0003BF0;
+        }else{
+            return E_BAD_PARAM;
+        }
+    } else {
+        return E_NO_DEVICE;
+    }
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_SPI17Y_Shutdown(mxc_spi17y_regs_t *spi)
+{
+    if (spi == MXC_SPI17Y) {
+        SYS_ClockDisable(SYS_PERIPH_CLOCK_SPI17Y);
+    }
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_SPIMSS_Init(mxc_spimss_regs_t *spi, const sys_cfg_spimss_t* sys_cfg)
+{
+    // Configure GPIO for spimss
+    if (spi == MXC_SPIMSS) {
+        SYS_ClockEnable(SYS_PERIPH_CLOCK_SPIMSS);
+        if(sys_cfg->map == MAP_A){
+            GPIO_Config(&gpio_cfg_spimss1a);  // SPI1A chosen
+        }else if(sys_cfg->map == MAP_B){
+            GPIO_Config(&gpio_cfg_spimss1b);  // SPI1B chosen
+        }else{
+            return E_BAD_PARAM;
+        }
+    } else {
+        return E_NO_DEVICE;
+    }
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_SPIMSS_Shutdown(mxc_spimss_regs_t *spi)
+{
+    if(spi == MXC_SPIMSS) {
+        SYS_ClockDisable(SYS_PERIPH_CLOCK_SPIMSS);
+    }
+    return E_NO_ERROR;
+}
+
+int SYS_TMR_Shutdown(mxc_tmr_regs_t *tmr)
+{
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_I2S_Init(const sys_cfg_i2s_t* sys_cfg)
+{
+    if(sys_cfg->map == MAP_A) {
+        GPIO_Config(&gpio_cfg_i2s1a);
+    }
+    else if(sys_cfg->map == MAP_B) {
+        GPIO_Config(&gpio_cfg_i2s1b);
+    }
+    else {
+        return E_BAD_PARAM;
+    }
+        SYS_ClockEnable(SYS_PERIPH_CLOCK_SPIMSS);
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_I2S_Shutdown(void)
+{
+        SYS_ClockDisable(SYS_PERIPH_CLOCK_SPIMSS);
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+int SYS_I2S_GetFreq(mxc_spimss_regs_t *spimss)
+{
+    return PeripheralClock;
+}
+
+/* ************************************************************************ */
+int SYS_RTC_SqwavInit(const sys_cfg_rtc_t* sys_cfg)
+{
+    GPIO_Config(&gpio_cfg_rtc);
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************ */
+uint32_t SYS_SysTick_GetFreq(void)
+{
+    // Determine is using internal (SystemCoreClock) or external (32768) clock
+    if ( (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) || !(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
+        return SystemCoreClock;
+    } else {
+        return SYS_RTC_CLK;
+    }
+}
+
+/* ************************************************************************ */
+int SYS_SysTick_Config(uint32_t ticks, int clk_src, mxc_tmr_regs_t* tmr)
+{
+
+    if(ticks == 0)
+        return E_BAD_PARAM;
+
+    // If SystemClock, call default CMSIS config and return
+    if (clk_src) {
+        return SysTick_Config(ticks);
+    } else { /* External clock source requested
+                enable RTC clock in run mode*/
+        RTC_Init(MXC_RTC, 0, 0, NULL);
+        RTC_EnableRTCE(MXC_RTC);
+
+        // Disable SysTick Timer
+        SysTick->CTRL = 0;
+        // Check reload value for valid
+        if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) {
+            // Reload value impossible
+            return E_BAD_PARAM;
+        }
+        // set reload register
+        SysTick->LOAD  = ticks - 1;
+
+        // set Priority for Systick Interrupt
+        NVIC_SetPriority(SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
+
+        // Load the SysTick Counter Value
+        SysTick->VAL   = 0;
+
+        // Enable SysTick IRQ and SysTick Timer leaving clock source as external
+        SysTick->CTRL  = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
+
+        // Function successful
+        return E_NO_ERROR;
+    }
+}
+
+/* ************************************************************************ */
+void SYS_SysTick_Disable(void)
+{
+    SysTick->CTRL = 0;
+}
+
+/* ************************************************************************ */
+int SYS_SysTick_Delay(uint32_t ticks)
+{
+    uint32_t cur_ticks, num_full, num_remain, previous_ticks, num_subtract, i;
+    uint32_t reload, value, ctrl;  // save/restore variables
+
+    if(ticks == 0)
+        return E_BAD_PARAM;
+
+    // If SysTick is not enabled we can take it for our delay
+    if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
+
+        // Save current state in case it's disabled but already configured, restore at return.
+        reload = SysTick->LOAD;
+        value = SysTick->VAL;
+        ctrl = SysTick->CTRL;
+
+        // get the number of ticks less than max RELOAD.
+        num_remain = ticks % SysTick_LOAD_RELOAD_Msk;
+
+        /* if ticks is < Max SysTick Reload num_full will be 0, otherwise it will
+           give us the number of max SysTicks cycles required */
+        num_full = (ticks - 1) / SysTick_LOAD_RELOAD_Msk;
+
+        // Do the required full systick countdowns
+        if (num_full) {
+            // load the max count value into systick
+            SysTick->LOAD = SysTick_LOAD_RELOAD_Msk;
+            // load the starting value
+            SysTick->VAL = 0;
+            // enable SysTick counter with SystemClock source internal, immediately forces LOAD register into VAL register
+            SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+            // CountFlag will get set when VAL reaches zero
+            for (i = num_full; i > 0; i--) {
+                do {
+                    cur_ticks = SysTick->CTRL;
+                } while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk));
+            }
+            // Disable systick
+            SysTick->CTRL = 0;
+        }
+        // Now handle the remainder of ticks
+        if (num_remain) {
+            SysTick->LOAD = num_remain;
+            SysTick->VAL = 0;
+            SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+            // wait for countflag to get set
+            do {
+                cur_ticks = SysTick->CTRL;
+            } while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk));
+            // Disable systick
+            SysTick->CTRL = 0;
+        }
+
+        // restore original state of SysTick and return
+        SysTick->LOAD = reload;
+        SysTick->VAL =  value;
+        SysTick->CTRL = ctrl;
+
+        return E_NO_ERROR;
+
+    } else { /* SysTick is enabled
+           When SysTick is enabled count flag can not be used
+           and the reload can not be changed.
+           Do not read the CTRL register -> clears count flag */
+
+        // Get the reload value for wrap/reload case
+        reload = SysTick->LOAD;
+
+        // Read the starting systick value
+        previous_ticks = SysTick->VAL;
+
+        do {
+            // get current SysTick value
+            cur_ticks = SysTick->VAL;
+            // Check for wrap/reload of timer countval
+            if (cur_ticks > previous_ticks) {
+                // subtract count to 0 (previous_ticks) and wrap (reload value - cur_ticks)
+                num_subtract = (previous_ticks + (reload - cur_ticks));
+            } else { /* standard case (no wrap)
+                        subtract off the number of ticks since last pass */
+                num_subtract = (previous_ticks - cur_ticks);
+            }
+            // check to see if we are done.
+            if (num_subtract >= ticks)
+                return E_NO_ERROR;
+            else
+                ticks -= num_subtract;
+            // cur_ticks becomes previous_ticks for next timer read.
+            previous_ticks = cur_ticks;
+        } while (ticks > 0);
+        // Should not ever be reached
+        return E_NO_ERROR;
+    }
+}
+
+/* ************************************************************************ */
+void SYS_SysTick_DelayUs(uint32_t us)
+{
+    SYS_SysTick_Delay((uint32_t)(((uint64_t)SYS_SysTick_GetFreq() * us) / 1000000));
+}
+
+/* ************************************************************************ */
+int SYS_WDT_Init(mxc_wdt_regs_t* wdt, const sys_cfg_wdt_t* sys_cfg)
+{
+    return E_NO_ERROR;
+}
+/**@} end of ingroup MXC_sys*/

bsp/maxim/libraries/MAX32660PeriphDriver/Source/nvic_table.c

@@ -0,0 +1,84 @@
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-06-05 16:53:29 -0500 (Wed, 05 Jun 2019) $
+ * $Revision: 43696 $
+ *
+ **************************************************************************** */
+
+
+#include "mxc_config.h"
+#include <string.h>
+#include "nvic_table.h"
+
+#if !defined (NVIC_USER_IRQ_OFFSET)
+    #define NVIC_USER_IRQ_OFFSET 16     /**! Offset for device specific IRQs */
+#endif
+
+/* RAM vector_table needs to be aligned with the size of the vector table */
+#if defined ( __ICCARM__ )
+    #pragma data_alignment = 512
+#else
+    __attribute__((aligned(512)))
+#endif
+static void (*ramVectorTable[MXC_IRQ_COUNT])(void);
+
+void NVIC_SetRAM(void)
+{
+#if defined (__ICCARM__)
+    extern void (* const __isr_vector[])(void);
+#else
+    /* should be defined in starup_<device>.S */
+    extern uint32_t __isr_vector[97];
+#endif
+    
+    memcpy(&ramVectorTable, &__isr_vector, sizeof(ramVectorTable));
+    SCB->VTOR = (uint32_t)&ramVectorTable;
+}
+
+void NVIC_SetVector(IRQn_Type irqn, void(*irq_handler)(void))
+{
+    int index = irqn + 16;  /* offset for externals */
+    
+    /* If not copied, do copy */
+    if (SCB->VTOR != (uint32_t)&ramVectorTable) {
+        NVIC_SetRAM();
+    }
+    
+    ramVectorTable[index] = irq_handler;
+    NVIC_EnableIRQ(irqn);
+}
+
+uint32_t NVIC_GetVector(IRQn_Type irqn)
+{
+    uint32_t *vectors = (uint32_t *)SCB->VTOR;
+    return vectors[(int32_t)irqn + NVIC_USER_IRQ_OFFSET];
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/rtc.c

@@ -0,0 +1,419 @@
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ **************************************************************************** */
+
+#include "mxc_config.h"
+#include "rtc_regs.h"
+#include "rtc.h"
+#include "mxc_sys.h"
+#include "mxc_delay.h"
+#include "gpio_regs.h"
+#include "mxc_errors.h"
+
+#if TARGET == 32650
+    #include "pwrseq_regs.h"
+#endif
+
+#define RTC_CTRL_RESET_DEFAULT (0x0000UL)
+#define RTC_IS_BUSY (MXC_RTC->ctrl & MXC_F_RTC_CTRL_BUSY)
+#define RTC_IS_ENABLED (MXC_RTC->ctrl & MXC_F_RTC_CTRL_RTCE)
+
+#define BUSY_TIMEOUT 1000   // Timeout counts for the Busy bit
+
+// *****************************************************************************
+int RTC_EnableTimeofdayInterrupt(mxc_rtc_regs_t *rtc)
+{
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl |= MXC_F_RTC_CTRL_ADE;   // Enable Time-of-day Interrupt
+    return E_SUCCESS;
+}
+
+// *****************************************************************************
+int RTC_DisableTimeofdayInterrupt(mxc_rtc_regs_t *rtc)
+{
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl &= ~MXC_F_RTC_CTRL_ADE;    // Disable Time-of-day Interrupt
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    return E_SUCCESS;
+}
+
+// *****************************************************************************
+int RTC_EnableSubsecondInterrupt(mxc_rtc_regs_t *rtc)
+{
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl |= MXC_F_RTC_CTRL_ASE;    // Enable Sub-Second Interrupt
+
+    return E_SUCCESS;
+}
+
+// *****************************************************************************
+int RTC_DisableSubsecondInterrupt(mxc_rtc_regs_t *rtc)
+{
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl &= ~MXC_F_RTC_CTRL_ASE;    // Alarm Sub-Second Interrupt disabled
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    return E_SUCCESS;
+}
+
+// *****************************************************************************
+int RTC_SetTimeofdayAlarm(mxc_rtc_regs_t *rtc, uint32_t ras)
+{
+    // ras can only be written if BUSY = 0 & (RTCE = 0 or ADE = 0);
+
+
+    if(RTC_DisableTimeofdayInterrupt(rtc) == E_BUSY) {
+        return E_BUSY;
+    }
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ras = (ras << MXC_F_RTC_RAS_RAS_POS) & MXC_F_RTC_RAS_RAS;
+
+    if(RTC_EnableTimeofdayInterrupt(rtc) == E_BUSY) {
+        return E_BUSY;
+    }
+
+    return E_SUCCESS;
+}
+
+// *****************************************************************************
+int RTC_SetSubsecondAlarm(mxc_rtc_regs_t *rtc, uint32_t rssa)
+{
+    // ras can only be written if BUSY = 0 & (RTCE = 0 or ASE = 0);
+
+    if(RTC_DisableSubsecondInterrupt(rtc) == E_BUSY) {
+        return E_BUSY;
+    }
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->rssa =  (rssa << MXC_F_RTC_RSSA_RSSA_POS) & MXC_F_RTC_RSSA_RSSA;
+
+    if(RTC_EnableSubsecondInterrupt(rtc) == E_BUSY) {
+        return E_BUSY;
+    }
+
+    return E_SUCCESS;
+}
+
+
+// *****************************************************************************
+int RTC_EnableRTCE(mxc_rtc_regs_t *rtc)
+{
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl |= MXC_F_RTC_CTRL_WE;       // Allow writing to registers
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+    // Can only write if WE=1 and BUSY=0
+    rtc->ctrl |= MXC_F_RTC_CTRL_RTCE;    // setting RTCE = 1
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl &= ~MXC_F_RTC_CTRL_WE;       // Prevent Writing...
+
+    return E_SUCCESS;
+}
+
+// *****************************************************************************
+int RTC_DisableRTCE(mxc_rtc_regs_t *rtc)
+{
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl |= MXC_F_RTC_CTRL_WE;      // Allow writing to registers
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    // Can only write if WE=1 and BUSY=0
+    rtc->ctrl &= ~MXC_F_RTC_CTRL_RTCE;  // setting RTCE = 0
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl &= ~MXC_F_RTC_CTRL_WE;       // Prevent Writing...
+
+    return E_SUCCESS;
+}
+
+
+// *****************************************************************************
+int RTC_Init(mxc_rtc_regs_t *rtc, uint32_t sec, uint8_t ssec, sys_cfg_rtc_t *sys_cfg)
+{
+#if((TARGET == 32650) || (TARGET == 32660))
+    SYS_ClockEnable_X32K(sys_cfg);
+#else
+    SYS_RTCClockEnable(sys_cfg);
+#endif
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl = MXC_F_RTC_CTRL_WE;        //  Allow Writes
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl = RTC_CTRL_RESET_DEFAULT;  // Start with a Clean Register
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl |= MXC_F_RTC_CTRL_WE;      // Set Write Enable, allow writing to reg.
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ssec = ssec;
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->sec = sec;
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl &= ~MXC_F_RTC_CTRL_WE;       // Prevent Writing...
+
+    return E_SUCCESS;
+}
+
+// *****************************************************************************
+int RTC_SquareWave(mxc_rtc_regs_t *rtc, rtc_sqwave_en_t sqe, rtc_freq_sel_t ft,
+                   rtc_osc_mode_t x32kmd, const sys_cfg_rtc_t* sys_cfg)
+{
+
+    SYS_RTC_SqwavInit(sys_cfg);  // Set the Output pins for the squarewave.
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl |= MXC_F_RTC_CTRL_WE;   // Allow writing to registers
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    if (sqe == SQUARE_WAVE_ENABLED) {
+        if (ft == F_32KHZ){        // if 32KHz output is selected...
+            rtc->oscctrl |= MXC_F_RTC_OSCCTRL_OUT32K;   // Enable 32KHz wave
+            if (RTC_CheckBusy()) {
+                return E_BUSY;
+            }
+            rtc->ctrl |= MXC_F_RTC_CTRL_SQE;                  // Enable output on the pin
+        } else {                  // if 1Hz, 512Hz, 4KHz output is selected
+
+            rtc->oscctrl &= ~MXC_F_RTC_OSCCTRL_OUT32K;  // Must make sure that the 32KHz is disabled
+            if (RTC_CheckBusy()) {
+                return E_BUSY;
+            }
+            rtc->ctrl &= ~(MXC_F_RTC_CTRL_FT | MXC_F_RTC_CTRL_X32KMD);
+            if (RTC_CheckBusy()) {
+                return E_BUSY;
+            }
+            rtc->ctrl |= (MXC_F_RTC_CTRL_SQE | ft | x32kmd);  // Enable Sq. wave,
+        }
+
+        if (RTC_CheckBusy()) {
+            return E_BUSY;
+        }
+        rtc->ctrl |= MXC_F_RTC_CTRL_RTCE;     // Enable Real Time Clock
+    } else { // Turn off the square wave output on the pin
+
+        rtc->oscctrl &= ~MXC_F_RTC_OSCCTRL_OUT32K;     // Must make sure that the 32KHz is disabled
+        if (RTC_CheckBusy()) {
+            return E_BUSY;
+        }
+        rtc->ctrl &= ~MXC_F_RTC_CTRL_SQE;  // No sq. wave output
+    }
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+    rtc->ctrl &= ~MXC_F_RTC_CTRL_WE;       // Disable Writing to register
+
+    return E_SUCCESS;
+}
+
+// *****************************************************************************
+int RTC_Trim(mxc_rtc_regs_t *rtc, int8_t trim)
+{
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    rtc->ctrl |= MXC_F_RTC_CTRL_WE;
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+
+    MXC_SETFIELD(rtc->trim, MXC_F_RTC_TRIM_TRIM, trim << MXC_F_RTC_TRIM_TRIM_POS);
+
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+    rtc->ctrl &= ~MXC_F_RTC_CTRL_WE;       // Disable Writing to register
+
+    return E_SUCCESS;
+}
+
+// *****************************************************************************
+int RTC_CheckBusy(void)
+{
+    // Time-out transfer if it takes > BUSY_TIMEOUT microseconds
+    mxc_delay_start(MXC_DELAY_USEC(BUSY_TIMEOUT));
+    while (RTC_IS_BUSY) {
+        if (mxc_delay_check() != E_BUSY){
+            return E_BUSY;
+        }
+    }
+    mxc_delay_stop();
+    return E_SUCCESS;
+}
+
+// *****************************************************************************
+int RTC_GetFlags(void)
+{
+    return MXC_RTC->ctrl & (MXC_F_RTC_CTRL_ALDF | MXC_F_RTC_CTRL_ALSF | MXC_F_RTC_CTRL_RDY);
+}
+
+// *****************************************************************************
+int RTC_ClearFlags(int flags)
+{
+    if (RTC_CheckBusy()) {
+        return E_BUSY;
+    }
+    MXC_RTC->ctrl &= ~(flags & (MXC_F_RTC_CTRL_ALDF | MXC_F_RTC_CTRL_ALSF | MXC_F_RTC_CTRL_RDY));
+
+    return E_SUCCESS;
+}
+
+// *****************************************************************************
+int RTC_GetSubSecond(void)
+{
+#if TARGET == 32650
+    int ssec;
+    if(ChipRevision > 0xA1){
+        ssec = ((MXC_PWRSEQ->lpcn >> 12)& 0xF00) | (MXC_RTC->ssec & 0xFF);
+    }else{
+        ssec = MXC_RTC->ssec;
+    }
+        return ssec;
+#else
+    return MXC_RTC->ssec;
+#endif
+}
+
+// *****************************************************************************
+int RTC_GetSecond(void)
+{
+    return MXC_RTC->sec;
+}
+
+// *****************************************************************************
+int RTC_GetTime(uint32_t* sec, uint32_t* subsec)
+{
+    uint32_t temp_sec;
+    do {
+        // Check if an update is about to happen.
+        if(!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {
+            return E_BUSY;
+        }
+
+        // Read the seconds count.
+        temp_sec = RTC_GetSecond();
+
+        // Check if an update is about to happen.
+        if(!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {
+            return E_BUSY;
+        }
+
+        // Read the sub-seconds count.
+        *subsec = RTC_GetSubSecond();
+
+        // Check if an update is about to happen.
+        if(!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {
+            return E_BUSY;
+        }
+
+        // Read the seconds count.
+        *sec = RTC_GetSecond();
+
+        // Repeat until a steady state is reached.
+    } while (temp_sec != *sec);
+
+    return E_NO_ERROR;
+}
+
+// *****************************************************************************
+int RTC_IsEnabled(void)
+{
+    return RTC_IS_ENABLED;
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/spi.c

@@ -0,0 +1,254 @@
+/**
+ * @file       spi.c
+ * @brief      This file contains the function implementations for the
+ *             Serial Peripheral Interface (SPIMSS) peripheral module.
+ */
+
+/* *****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-10-17 14:16:30 -0500 (Wed, 17 Oct 2018) $
+ * $Revision: 38560 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "spi.h"
+#include "mxc_sys.h"
+#include "spimss.h"
+#include "spi17y.h"
+
+/**
+ * @ingroup spi
+ * @{
+ */
+
+/***** Definitions *****/
+
+
+/***** Functions *****/
+
+
+/* ************************************************************************ */
+int SPI_Init(spi_type spi_name, unsigned mode, unsigned freq)
+{
+    sys_cfg_spimss_t spimss_cfg;
+    sys_cfg_spi17y_t spi17y_cfg;
+    int error = E_NO_ERROR;
+
+    if (spi_name == SPI0A) {
+        spi17y_cfg.map = MAP_A;
+        error = SPI17Y_Init(MXC_SPI17Y, mode, freq, &spi17y_cfg);
+
+    } else if(spi_name == SPI1A) {
+        spimss_cfg.map = MAP_A;
+        error = SPIMSS_Init(MXC_SPIMSS, mode, freq, &spimss_cfg);
+
+    } else if(spi_name == SPI1B) {
+        spimss_cfg.map = MAP_B;
+        error = SPIMSS_Init(MXC_SPIMSS, mode, freq, &spimss_cfg);
+
+    } else {
+        return E_BAD_PARAM;
+    }
+
+ return error;
+}
+
+/* ************************************************************************ */
+int SPI_MasterTransAsync(spi_type spi_name, spi_req_t *req)
+{
+    int error = E_NO_ERROR;
+
+    if (spi_name == SPI0A) {
+        error = SPI17Y_MasterTransAsync(MXC_SPI17Y,  (spi17y_req_t *) req);
+    
+    } else if((spi_name == SPI1A) || (spi_name == SPI1B)) {
+        error = SPIMSS_MasterTransAsync(MXC_SPIMSS,  (spimss_req_t *) req);
+
+    } else {
+        return E_BAD_PARAM;
+    }
+
+ return error;
+}
+
+
+/* ************************************************************************ */
+int SPI_MasterTrans(spi_type spi_name, spi_req_t *req)
+{
+    int error = E_NO_ERROR;
+
+    if (spi_name == SPI0A) {
+        error = SPI17Y_MasterTrans(MXC_SPI17Y, (spi17y_req_t *) req);
+
+    } else if((spi_name == SPI1A) || (spi_name == SPI1B)) {
+        error = SPIMSS_MasterTrans(MXC_SPIMSS, (spimss_req_t *) req);
+
+    } else {
+        return E_BAD_PARAM;
+    }
+
+ return error;
+}
+
+/* ************************************************************************ */
+int SPI_SlaveTrans(spi_type spi_name, spi_req_t *req)
+{
+    int error = E_NO_ERROR;
+
+    if (spi_name == SPI0A) {
+        error = SPI17Y_SlaveTrans(MXC_SPI17Y, (spi17y_req_t *) req); 
+
+    } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
+        error = SPIMSS_SlaveTrans(MXC_SPIMSS, (spimss_req_t *) req);
+
+    } else {
+        return E_BAD_PARAM;
+    }
+
+ return error;
+}
+
+/* ************************************************************************ */
+int SPI_SlaveTransAsync(spi_type spi_name, spi_req_t *req)
+{
+    int error = E_NO_ERROR;
+
+    if (spi_name == SPI0A) {
+        error = SPI17Y_SlaveTransAsync(MXC_SPI17Y, (spi17y_req_t *) req);
+
+    } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
+        error = SPIMSS_SlaveTransAsync(MXC_SPIMSS, (spimss_req_t *) req);
+     
+    } else {
+        return E_BAD_PARAM;
+    }
+
+ return error;
+}
+
+/* ************************************************************************ */
+int SPI_Shutdown(spi_type spi_name)
+{
+    int error = E_NO_ERROR;
+
+    if (spi_name == SPI0A) {
+        error = SPI17Y_Shutdown(MXC_SPI17Y);
+
+    } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
+        error = SPIMSS_Shutdown(MXC_SPIMSS);
+
+    } else {
+        return E_BAD_PARAM;
+    }
+
+ return error;
+}
+
+
+/* ************************************************************************ */
+int SPI_AbortAsync(spi_type spi_name, spi_req_t *req)
+{
+    int error = E_NO_ERROR;
+
+    if (spi_name == SPI0A) {
+        error = SPI17Y_AbortAsync((spi17y_req_t *) req);
+     
+    } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
+        error = SPIMSS_AbortAsync((spimss_req_t *) req);
+
+    } else {
+        return E_BAD_PARAM;
+    }
+
+ return error;
+}
+
+/* ************************************************************************ */
+int SPI_Handler(spi_type spi_name)
+{
+    if (spi_name == SPI0A) {
+        SPI17Y_Handler(MXC_SPI17Y);
+
+    } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
+        SPIMSS_Handler(MXC_SPIMSS);
+
+    } else {
+         return E_BAD_PARAM;
+    }
+
+ return E_NO_ERROR;
+}
+
+// *****************************************************************************
+int SPI_Enable(spi_type spi_name)
+{
+    if (spi_name == SPI0A) {
+        SPI17Y_Enable(MXC_SPI17Y);
+        
+    } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
+        return E_NOT_SUPPORTED; 
+    } else {
+        return E_BAD_PARAM;
+    }
+    return E_NO_ERROR;
+}
+
+// *****************************************************************************
+int SPI_Disable(spi_type spi_name)
+{
+    if (spi_name == SPI0A) {
+        SPI17Y_Disable(MXC_SPI17Y);
+        
+    } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
+         return E_NOT_SUPPORTED;  
+    } else {
+        return E_BAD_PARAM;
+    }
+    return E_NO_ERROR;
+}
+
+// *****************************************************************************
+int SPI_Clear_fifo(spi_type spi_name)
+{
+    if (spi_name == SPI0A) {
+        SPI17Y_Clear_fifo(MXC_SPI17Y);
+        
+    } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
+         return E_NOT_SUPPORTED;  
+    } else {
+        return E_BAD_PARAM;
+    }
+    return E_NO_ERROR;
+}
+
+/**@} end of group spi */

bsp/maxim/libraries/MAX32660PeriphDriver/Source/spi17y.c

@@ -0,0 +1,641 @@
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-06-25 10:15:10 -0500 (Tue, 25 Jun 2019) $
+ * $Revision: 44277 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "tmr_utils.h"
+#include "mxc_lock.h"
+#include "spi17y.h"
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+
+typedef struct {
+    spi17y_req_t *req;
+    int started;
+    unsigned last_size;
+    unsigned deass;
+} spi17y_req_state_t;
+
+static spi17y_req_state_t states[MXC_SPI17Y_INSTANCES];
+
+/* **** Functions **** */
+static int SPI17Y_TransSetup(mxc_spi17y_regs_t *spi, spi17y_req_t *req, int master);
+static int SPI17Y_MasterTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async);
+static int SPI17Y_TransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async);
+static int SPI17Y_SlaveTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async);
+
+/* ************************************************************************** */
+int SPI17Y_Init(mxc_spi17y_regs_t *spi, unsigned int mode, unsigned int freq,
+                const sys_cfg_spi17y_t* sys_cfg)
+{
+    uint32_t freq_div;
+    int spi_num, error, hi_clk, lo_clk, scale;
+    
+    spi_num = MXC_SPI17Y_GET_IDX(spi);
+    MXC_ASSERT(spi_num >= 0);
+    
+    if (mode > 3) {
+        return E_BAD_PARAM;
+    }
+    
+    if ((error = SYS_SPI17Y_Init(spi, sys_cfg)) != E_NO_ERROR) {
+        return error;
+    }
+    
+    states[spi_num].req = NULL;
+    states[spi_num].last_size = 0;
+    states[spi_num].deass = 1;
+    
+    // Enable SPI17Y
+    spi->ctrl0 = (MXC_F_SPI17Y_CTRL0_EN);
+    spi->ss_time = ((0x1 << MXC_F_SPI17Y_SS_TIME_PRE_POS) |
+                    (0x1 << MXC_F_SPI17Y_SS_TIME_POST_POS) |
+                    (0x1 << MXC_F_SPI17Y_SS_TIME_INACT_POS));
+                    
+    // Check if frequency is too high
+    if (freq > PeripheralClock) {
+        return E_BAD_PARAM;
+    }
+    
+    // Set the clock high and low
+    freq_div = PeripheralClock/ (freq);
+    hi_clk = freq_div/2;
+    lo_clk = freq_div/2;
+    scale = 0;
+    
+    if (freq_div %2) {
+        hi_clk +=1;
+    }
+    
+    while (hi_clk > 16 && scale < 9) {
+        hi_clk /= 2;
+        lo_clk /=2;
+        scale ++;
+    }
+    
+    spi->clk_cfg = ((lo_clk << MXC_F_SPI17Y_CLK_CFG_LO_POS) |
+                    (hi_clk << MXC_F_SPI17Y_CLK_CFG_HI_POS));
+                    
+    MXC_SETFIELD(spi->clk_cfg, MXC_F_SPI17Y_CLK_CFG_SCALE, (scale << MXC_F_SPI17Y_CLK_CFG_SCALE_POS));
+    
+    // Set the mode
+    spi->ctrl2 = (mode << MXC_F_SPI17Y_CTRL2_CPHA_POS);
+    
+    // Clear the interrupts
+    spi->int_fl = spi->int_fl;
+    
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int SPI17Y_Shutdown(mxc_spi17y_regs_t *spi)
+{
+    int spi_num, err;
+    spi17y_req_t *temp_req;
+    
+    // Disable and clear interrupts
+    spi->int_en = 0;
+    spi->int_fl = spi->int_fl;
+    
+    // Disable SPI17Y and FIFOS
+    spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
+    spi->dma &= ~(MXC_F_SPI17Y_DMA_TX_FIFO_EN | MXC_F_SPI17Y_DMA_RX_FIFO_EN);
+    
+    // Call all of the pending callbacks for this SPI17Y
+    spi_num = MXC_SPI17Y_GET_IDX(spi);
+    if (states[spi_num].req != NULL) {
+    
+        // Save the request
+        temp_req = states[spi_num].req;
+        
+        // Unlock this SPI17Y
+        mxc_free_lock((uint32_t*)&states[spi_num].req);
+        
+        // Callback if not NULL
+        if (temp_req->callback != NULL) {
+            temp_req->callback(temp_req, E_SHUTDOWN);
+        }
+    }
+    
+    // Clear registers
+    spi->ctrl0 = 0;
+    spi->ctrl1 = 0;
+    spi->ctrl2 = 0;
+    spi->ss_time = 0;
+    
+    // Clear system level configurations
+    if ((err = SYS_SPI17Y_Shutdown(spi)) != E_NO_ERROR) {
+        return err;
+    }
+    
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int SPI17Y_TransSetup(mxc_spi17y_regs_t *spi, spi17y_req_t *req, int master)
+{
+    int spi_num;
+    if ((req->tx_data == NULL) && (req->rx_data == NULL)) {
+        return E_BAD_PARAM;
+    }
+    
+    if ((req->width > SPI17Y_WIDTH_1) && (req->tx_data != NULL) && (req->rx_data != NULL)) {
+        return E_BAD_PARAM;
+    }
+    
+    // HW has problem with these two character sizes
+    if (req->bits == 1 || req->bits == 9) {
+        return E_BAD_PARAM;
+    }
+    spi_num = MXC_SPI17Y_GET_IDX(spi);
+    MXC_ASSERT(spi_num >= 0);
+    MXC_ASSERT(req->ssel < MXC_SPI17Y_SS_INSTANCES);
+    
+    req->tx_num = 0;
+    req->rx_num = 0;
+    
+    if (req->len == 0) {
+        return E_NO_ERROR;
+    }
+    
+    states[spi_num].req = req;
+    states[spi_num].started = 0;
+    
+    // HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive).
+    if (states[spi_num].deass == 1) {
+        spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
+    }
+    
+    if (master) {
+        // Enable master mode
+        
+        spi->ctrl0 |= MXC_F_SPI17Y_CTRL0_MASTER;
+        
+        // Setup the slave select
+        MXC_SETFIELD(spi->ctrl0, MXC_F_SPI17Y_CTRL0_SS, ((0x1 << req->ssel) << MXC_F_SPI17Y_CTRL0_SS_POS));
+        spi->ctrl2 |= ((req->ssel_pol << req->ssel)<<MXC_F_SPI17Y_CTRL2_SS_POL_POS);
+    } else {
+        // Enable slave mode
+        spi->ctrl0 &= ~MXC_F_SPI17Y_CTRL0_MASTER;
+        // Setup the slave select
+        spi->ctrl2 |= ((req->ssel_pol << 0)<<MXC_F_SPI17Y_CTRL2_SS_POL_POS);
+    }
+    
+    if ((req->bits != states[spi_num].last_size)) {
+        // Setup the character size
+        // Master should only change character size at the end of a transaction.  No restrictions on when slave can change.
+        if (!master || (!(spi->stat & MXC_F_SPI17Y_STAT_BUSY) && (states[spi_num].deass == 1)) || !(spi->ctrl0 & MXC_F_SPI17Y_CTRL0_EN)) {
+            //disable spi to change transfer size
+            spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
+            // set bit size
+            states[spi_num].last_size = req->bits;
+            if (req->bits <16) {
+                MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_NUMBITS, req->bits << MXC_F_SPI17Y_CTRL2_NUMBITS_POS);
+            } else {
+                MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_NUMBITS, 0 << MXC_F_SPI17Y_CTRL2_NUMBITS_POS);
+            }
+        } else {
+            // cant change transfer size while spi is busy
+            return E_BAD_STATE;
+        }
+    }
+    
+    // Setup the data width
+    if (req->width == SPI17Y_WIDTH_4) {
+        MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_DATA_WIDTH, MXC_S_SPI17Y_CTRL2_DATA_WIDTH_QUAD);
+    } else if (req->width == SPI17Y_WIDTH_2) {
+        MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_DATA_WIDTH, MXC_S_SPI17Y_CTRL2_DATA_WIDTH_DUAL);
+    } else {
+        MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_DATA_WIDTH, MXC_S_SPI17Y_CTRL2_DATA_WIDTH_MONO);
+    }
+    
+    // Setup the number of characters to transact
+    if (req->len > (MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR >> MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS)) {
+        return E_BAD_PARAM;
+    }
+    
+    if (req->rx_data != NULL) {
+        // The TX_NUM field is used for both RX and TX length when in 4-wire mode.
+        if(req->width == SPI17Y_WIDTH_1) {
+            MXC_SETFIELD(spi->ctrl1, MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR,
+                        req->len << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS);
+        } else {
+            MXC_SETFIELD(spi->ctrl1, MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR,
+                        req->len << MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS);
+        }
+        spi->dma |= MXC_F_SPI17Y_DMA_RX_FIFO_EN;
+    } else {
+        spi->ctrl1 &= ~(MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR);
+        spi->dma &= ~(MXC_F_SPI17Y_DMA_RX_FIFO_EN);
+    }
+
+    // Must use TXFIFO and NUM in full duplex
+    if (req->width == SPI17Y_WIDTH_1
+            && !((spi->ctrl2 & MXC_F_SPI17Y_CTRL2_THREE_WIRE)>> MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS)) {
+        
+        if (req->tx_data == NULL) {
+            // Must have something to send, so we'll use the rx_data buffer initialized to 0.
+            memset(req->rx_data, 0, (req->bits > 8 ? req->len << 1 : req->len));
+            req->tx_data = req->rx_data;
+            req->tx_num = 0;
+        }
+    }
+    
+    if(req->tx_data != NULL) {
+        MXC_SETFIELD(spi->ctrl1, MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR,
+                     req->len << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS);
+        spi->dma |= MXC_F_SPI17Y_DMA_TX_FIFO_EN;
+    } else {
+        spi->dma &= ~(MXC_F_SPI17Y_DMA_TX_FIFO_EN);
+    }
+    
+    spi->dma |= MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR | MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR;
+    spi->ctrl0 |= (MXC_F_SPI17Y_CTRL0_EN);
+    
+    states[spi_num].deass = req->deass;
+    // Clear master done flag
+    spi->int_fl = MXC_F_SPI17Y_INT_FL_M_DONE;
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+void SPI17Y_Handler(mxc_spi17y_regs_t *spi)
+{
+    int spi_num, rx_avail;
+    uint32_t flags;
+    
+    // Clear the interrupt flags
+    spi->int_en = 0;
+    flags = spi->int_fl;
+    spi->int_fl = flags;
+    
+    spi_num = MXC_SPI17Y_GET_IDX(spi);
+    // Figure out if this SPI17Y has an active request
+    if ((states[spi_num].req != NULL) && (flags)) {
+        if ((spi->ctrl0 & MXC_F_SPI17Y_CTRL0_MASTER)>> MXC_F_SPI17Y_CTRL0_MASTER_POS) {
+            do {
+                SPI17Y_MasterTransHandler(spi,  states[spi_num].req, 1);
+                rx_avail = (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_CNT) >> MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS;
+            } while ((states[spi_num].req->rx_data != NULL) && (rx_avail > (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL)
+                     >>MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS));
+                     
+        } else {
+            do {
+                SPI17Y_SlaveTransHandler(spi, states[spi_num].req, 1);
+                rx_avail = (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_CNT) >> MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS;
+            } while ((states[spi_num].req->rx_data != NULL) && (rx_avail > (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL)
+                     >>MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS));
+                     
+        }
+    }
+    
+}
+
+/* ************************************************************************** */
+int SPI17Y_MasterTrans(mxc_spi17y_regs_t *spi,spi17y_req_t *req)
+{
+    int error;
+    if ((error =SPI17Y_TransSetup(spi, req, 1)) != E_NO_ERROR) {
+        return error;
+    }
+    req->callback = NULL;
+    
+    while (SPI17Y_MasterTransHandler(spi,req,0)==0) {
+    }
+    
+    while (!(spi->int_fl & MXC_F_SPI17Y_INT_FL_M_DONE)) {
+        
+    }
+    
+    return E_NO_ERROR;
+}
+
+
+/* ************************************************************************** */
+int SPI17Y_SlaveTrans(mxc_spi17y_regs_t *spi, spi17y_req_t *req)
+{
+    int error;
+    if ((error =SPI17Y_TransSetup(spi, req,0)) != E_NO_ERROR) {
+        return error;
+    }
+    req->callback = NULL;
+    
+    while (SPI17Y_SlaveTransHandler(spi,req,0)==0) {
+        
+    }
+    
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int SPI17Y_MasterTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req)
+{
+    int error;
+    if ((error =SPI17Y_TransSetup(spi, req, 1))!= E_NO_ERROR) {
+        return error;
+    }
+    
+    SPI17Y_MasterTransHandler(spi,req, 1);
+    
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int SPI17Y_SlaveTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req)
+{
+    int error;
+    if ((error =SPI17Y_TransSetup(spi, req, 0)) != E_NO_ERROR) {
+        return error;
+    }
+    
+    SPI17Y_SlaveTransHandler(spi,req, 1);
+    
+    
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int SPI17Y_MasterTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req,uint8_t async)
+{
+    int retval;
+    int spi_num;
+    
+    spi_num = MXC_SPI17Y_GET_IDX(spi);
+    
+    // Leave slave select asserted at the end of the transaction
+    if (!req->deass) {
+        spi->ctrl0 |= MXC_F_SPI17Y_CTRL0_SS_CTRL;
+    }
+    
+    retval = SPI17Y_TransHandler(spi,req, async);
+    
+    if (!states[spi_num].started) {
+        spi->ctrl0 |= MXC_F_SPI17Y_CTRL0_START;
+        states[spi_num].started = 1;
+    }
+    
+    // Deassert slave select at the end of the transaction
+    if (req->deass) {
+        spi->ctrl0 &= ~MXC_F_SPI17Y_CTRL0_SS_CTRL;
+    }
+    
+    return retval;
+}
+
+/* ************************************************************************** */
+int SPI17Y_SlaveTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async)
+{
+    return SPI17Y_TransHandler(spi,req, async);
+}
+
+/* ************************************************************************** */
+// Returns non-zero if transactions is complete, or 0 if not.
+int SPI17Y_TransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async)
+{
+
+    unsigned tx_avail, rx_avail;
+    int remain, spi_num;
+    uint32_t int_en =0;
+    uint32_t length =0;
+    spi_num = MXC_SPI17Y_GET_IDX(spi);
+    
+    // Read/write 2x number of bytes if larger character size
+    if (req->bits > 8) {
+        length = req->len*2;
+    } else {
+        length = req->len;
+    }
+    
+    if (req->tx_data != NULL) {
+        // Need to know when all bytes are transmitted, so the callback can be triggered.
+        int_en |= MXC_F_SPI17Y_INT_EN_TX_EMPTY;
+    
+        // Calculate how many bytes we can write to the FIFO
+        tx_avail = MXC_SPI17Y_FIFO_DEPTH - ((spi->dma & MXC_F_SPI17Y_DMA_TX_FIFO_CNT) >>
+                                            MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS);
+        if ((length - req->tx_num) < tx_avail) {
+            tx_avail = (length - req->tx_num);
+        }
+        if (req->bits > 8) {
+            tx_avail &= ~(unsigned)0x1;
+        }
+        // Write the FIFO
+        while (tx_avail) {
+            if (tx_avail > 3) {
+                memcpy((void*)&spi->data32,&((uint8_t*)req->tx_data)[req->tx_num], 4);
+                
+                tx_avail -= 4;
+                req->tx_num += 4;
+                
+            } else if (tx_avail > 1) {
+                memcpy((void*)&spi->data16[0],&((uint8_t*)req->tx_data)[req->tx_num], 2);
+                
+                tx_avail -= 2;
+                req->tx_num += 2;
+                
+            } else if (req->bits<=8) {
+                spi->data8[0] = ((uint8_t*)req->tx_data)[req->tx_num++];
+                
+                tx_avail -= 1;
+            }
+        }
+    }
+    
+    remain = length - req->tx_num;
+    
+    // Set the TX interrupts
+    if (remain) {
+        if (remain > MXC_SPI17Y_FIFO_DEPTH) {
+            // Set the TX FIFO almost empty interrupt if we have to refill
+            spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL) |
+                        ((MXC_SPI17Y_FIFO_DEPTH) << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS));
+        } else {
+        
+            spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL) |
+                        ((remain) << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS));
+        }
+        int_en |= MXC_F_SPI17Y_INT_EN_TX_THRESH;
+        
+    }
+    // Break out if we've transmitted all the bytes and not receiving
+    if ((req->rx_data == NULL) && (req->tx_num == length) && ((spi->dma & MXC_F_SPI17Y_DMA_TX_FIFO_CNT) == 0)) {
+        spi->int_en = 0;
+        int_en = 0;
+        mxc_free_lock((uint32_t*)&states[spi_num].req);
+        // Callback if not NULL
+        if (req->callback != NULL) {
+            req->callback(req, E_NO_ERROR);
+        }
+        return 1;
+    }
+    
+    
+    // Read the RX FIFO
+    if (req->rx_data != NULL) {
+    
+        // Wait for there to be data in the RX FIFO
+        rx_avail = (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_CNT) >> MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS;
+        if ((length - req->rx_num) < rx_avail) {
+            rx_avail = (length - req->rx_num);
+        }
+        if (req->bits <= 8 || rx_avail >= 2) {
+            // Read from the FIFO
+            while (rx_avail) {
+                if (rx_avail > 3) {
+                    memcpy(&((uint8_t*)req->rx_data)[req->rx_num], (void*)&spi->data32, 4);
+                    rx_avail -= 4;
+                    req->rx_num += 4;
+                    
+                } else if (rx_avail > 1) {
+                    memcpy(&((uint8_t*)req->rx_data)[req->rx_num], (void*)&spi->data16[0], 2);
+                    rx_avail -= 2;
+                    req->rx_num += 2;
+                    
+                } else {
+                    ((uint8_t*)req->rx_data)[req->rx_num++] = spi->data8[0];
+                    rx_avail -= 1;
+                }
+                // Don't read less than 2 bytes if we are using greater than 8 bit characters
+                if (rx_avail == 1 && req->bits > 8) {
+                    break;
+                }
+            }
+        }
+        remain = length - req->rx_num;
+        if (remain) {
+            if (remain > MXC_SPI17Y_FIFO_DEPTH) {
+                spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL) |
+                            ((2) << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS));
+            } else {
+                spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL) |
+                            ((remain-1) << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS));
+            }
+            int_en |= MXC_F_SPI17Y_INT_EN_RX_THRESH;
+        }
+        
+        // Break out if we've received all the bytes and we're not transmitting
+        if ((req->tx_data == NULL) && (req->rx_num == length)) {
+            spi->int_en = 0;
+            int_en = 0;
+            mxc_free_lock((uint32_t*)&states[spi_num].req);
+            // Callback if not NULL
+            if (req->callback != NULL) {
+                req->callback(req, E_NO_ERROR);
+            }
+            return 1;
+        }
+    }
+    
+    // Break out once we've transmitted and received all of the data
+    if ((req->rx_num == length) && (req->tx_num == length) && ((spi->dma & MXC_F_SPI17Y_DMA_TX_FIFO_CNT) == 0)) {
+        spi->int_en = 0;
+        int_en = 0;
+        mxc_free_lock((uint32_t*)&states[spi_num].req);
+        // Callback if not NULL
+        if (req->callback != NULL) {
+            req->callback(req, E_NO_ERROR);
+        }
+        return 1;
+    }
+    if(async){
+        spi->int_en = int_en;
+    }
+    return 0;
+}
+
+/* ************************************************************************* */
+int SPI17Y_AbortAsync(spi17y_req_t *req)
+{
+    int spi_num;
+    mxc_spi17y_regs_t *spi;
+    
+    // Check the input parameters
+    if (req == NULL) {
+        return E_BAD_PARAM;
+    }
+    
+    // Find the request, set to NULL
+    for (spi_num = 0; spi_num < MXC_SPI17Y_INSTANCES; spi_num++) {
+        if (req == states[spi_num].req) {
+        
+            spi = MXC_SPI17Y_GET_SPI17Y(spi_num);
+            
+            // Disable interrupts, clear the flags
+            spi->int_en = 0;
+            spi->int_fl = spi->int_fl;
+            
+            // Reset the SPI17Y to cancel the on ongoing transaction
+            spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
+            spi->ctrl0 |= (MXC_F_SPI17Y_CTRL0_EN);
+            
+            // Unlock this SPI17Y
+            mxc_free_lock((uint32_t*)&states[spi_num].req);
+            
+            // Callback if not NULL
+            if (req->callback != NULL) {
+                req->callback(req, E_ABORT);
+            }
+            
+            return E_NO_ERROR;
+        }
+    }
+    
+    return E_BAD_PARAM;
+}
+
+// *****************************************************************************
+void SPI17Y_Enable(mxc_spi17y_regs_t* spi)
+{
+    spi->ctrl0 |= (MXC_F_SPI17Y_CTRL0_EN);
+}
+
+// *****************************************************************************
+void SPI17Y_Disable(mxc_spi17y_regs_t* spi)
+{
+    spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
+}
+
+// *****************************************************************************
+void SPI17Y_Clear_fifo(mxc_spi17y_regs_t* spi)
+{
+    spi->dma |= MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR | MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR;
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/spimss.c

@@ -0,0 +1,514 @@
+ /**
+ * @file       spimss.c
+ * @brief      This file contains the function implementations for the
+ *             Serial Peripheral Interface (SPIMSS) peripheral module.
+ */
+
+/* *****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-05-06 14:44:04 -0500 (Mon, 06 May 2019) $
+ * $Revision: 43157 $
+ *
+ **************************************************************************** */
+ 
+/* **** Includes **** */
+#include <string.h>
+#include <stdio.h>
+#include <stdint.h>
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "spimss.h"
+#include "mxc_lock.h"
+
+/**
+ * @ingroup spimss
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+typedef struct {
+    spimss_req_t *req;
+} spimss_req_state_t;
+
+static spimss_req_state_t states[MXC_SPIMSS_INSTANCES];
+
+
+/* **** Functions **** */
+static int SPIMSS_TransSetup(mxc_spimss_regs_t *spi, spimss_req_t *req, int master);
+static uint32_t SPIMSS_MasterTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req);
+static uint32_t SPIMSS_TransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req);
+static uint32_t SPIMSS_SlaveTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req);
+
+/* ************************************************************************** */
+int SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_cfg_spimss_t* sys_cfg)
+{
+    int spi_num, error;
+    unsigned int spimss_clk;
+    unsigned int pol, pha;  // Polarity and phase of the clock (SPI mode)
+
+    spi_num = MXC_SPIMSS_GET_IDX(spi);
+
+    MXC_ASSERT(spi_num >= 0);
+
+    if (mode > 3) {
+        return E_BAD_PARAM;
+    }
+
+    if ((error = SYS_SPIMSS_Init(spi, sys_cfg)) != E_NO_ERROR) {
+        return error;
+    }
+
+    states[spi_num].req = NULL;
+    spi->ctrl &=  ~(MXC_F_SPIMSS_CTRL_SPIEN);  // Keep the SPI Disabled (This is the SPI Start) 
+
+    // Check if frequency is too high
+    if (freq > PeripheralClock) {
+        return E_BAD_PARAM;
+    }
+
+     // Set the bit rate
+    spimss_clk = PeripheralClock;
+    spi->brg = (spimss_clk / freq) >> 1;
+
+    // Set the mode
+    pol = mode >> 1;  // Get the polarity out of the mode input value
+    pha = mode &  1;  // Get the phase out of the mode input value
+
+    spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_CTRL_CLKPOL)) | (pol << MXC_F_SPIMSS_CTRL_CLKPOL_POS);  // polarity
+					  
+    spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_CTRL_PHASE))  | (pha << MXC_F_SPIMSS_CTRL_PHASE_POS);   // phase
+
+    spi->status &= ~(MXC_F_SPIMSS_STATUS_IRQ);
+
+    return E_NO_ERROR;
+}
+/* ************************************************************************* */
+int SPIMSS_Shutdown(mxc_spimss_regs_t *spi)
+{
+    int spi_num, err;
+    spimss_req_t *temp_req;
+
+    // Disable and turn off the SPI transaction.
+    spi->ctrl = 0;    // Interrupts, SPI transaction all turned off
+    spi->status = 0;
+    spi->mod  = 0;
+
+    // Reset FIFO counters
+    spi->dma &= ~(MXC_F_SPIMSS_DMA_RX_FIFO_CNT|MXC_F_SPIMSS_DMA_TX_FIFO_CNT);
+
+    // Call all of the pending callbacks for this SPI
+    spi_num = MXC_SPIMSS_GET_IDX(spi);
+    if (states[spi_num].req != NULL) {
+
+        // Save the request
+        temp_req = states[spi_num].req;
+
+        // Unlock this SPI
+        mxc_free_lock((uint32_t*)&states[spi_num].req);
+
+        // Callback if not NULL
+        if (temp_req->callback != NULL) {
+            temp_req->callback(temp_req, E_SHUTDOWN);
+        }
+    }
+
+    spi->status = 0;
+
+    // Clear system level configurations
+    if ((err = SYS_SPIMSS_Shutdown(spi)) != E_NO_ERROR) {
+        return err;
+    }
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int SPIMSS_TransSetup(mxc_spimss_regs_t *spi, spimss_req_t *req, int master)
+{
+    int spi_num;
+
+    spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN);  // Make sure the Initiation 
+	                                          // of SPI Start is disabled.
+
+    spi->mod |= MXC_F_SPIMSS_MOD_TX_LJ;       // Making sure data is left 
+	                                          // justified.
+
+    if ((req->tx_data == NULL) && (req->rx_data == NULL)) {
+        return -1;
+    }
+
+    spi_num = MXC_SPIMSS_GET_IDX(spi);
+    MXC_ASSERT(spi_num >= 0);
+
+    if (req->len == 0) {
+        return 0;
+    }
+
+    req->tx_num = 0;
+    req->rx_num = 0;
+
+    if (mxc_get_lock((uint32_t*)&states[spi_num].req, (uint32_t)req) != E_NO_ERROR) {
+        return E_BUSY;
+    }
+
+    if (master) { // Enable master mode
+        spi->ctrl |= MXC_F_SPIMSS_CTRL_MMEN;     // SPI configured as master.
+        spi->mod |= MXC_F_SPIMSS_CTRL_MMEN;       // SSEL pin is an output.		
+    } else { // Enable slave mode
+        spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_MMEN);  // SPI configured as slave.
+        spi->mod &= ~(MXC_F_SPIMSS_CTRL_MMEN);    // SSEL pin is an input.		
+    }
+
+    // Setup the character size
+
+    if (req->bits <16) {
+        MXC_SETFIELD(spi->mod, MXC_F_SPIMSS_MOD_NUMBITS , req->bits <<  MXC_F_SPIMSS_MOD_NUMBITS_POS);
+		
+    } else {
+        MXC_SETFIELD(spi->mod, MXC_F_SPIMSS_MOD_NUMBITS , 0 <<  MXC_F_SPIMSS_MOD_NUMBITS_POS);
+		
+    }
+
+    // Setup the slave select
+    spi->mod |= MXC_F_SPIMSS_MOD_SSV; // Assert a high on Slave Select,
+                                      // to get the line ready for active low later
+
+    // Clear the TX and RX FIFO
+    spi->dma |= (MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR | MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR);
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+void SPIMSS_Handler(mxc_spimss_regs_t *spi)  // From the IRQ
+{
+    int spi_num;
+    uint32_t flags;
+    unsigned int int_enable;
+
+    flags = spi->status;
+    spi->status = flags;
+    spi->status|= 0x80;    // clear interrupt
+
+    spi_num = MXC_SPIMSS_GET_IDX(spi);
+
+    int_enable = 0;
+    if (states[spi_num].req != NULL) {
+        if ((spi->ctrl  & MXC_F_SPIMSS_CTRL_MMEN) >> MXC_F_SPIMSS_CTRL_MMEN_POS) {
+            int_enable = SPIMSS_MasterTransHandler(spi, states[spi_num].req);
+			
+        } else {
+            int_enable = SPIMSS_SlaveTransHandler(spi, states[spi_num].req);			
+        }
+    }
+
+    if (int_enable==1) {
+        spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE );
+		
+    }
+}
+
+/* ************************************************************************** */
+int SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, spimss_req_t *req)
+{
+    int error;
+
+    if ((error = SPIMSS_TransSetup(spi, req, 1)) != E_NO_ERROR) {
+        return error;
+    }
+	
+    req->callback = NULL;
+
+    spi->mod &= ~(MXC_F_SPIMSS_MOD_SSV);  // This will assert the Slave Select.
+    spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN;  // Enable/Start SPI
+    
+    while (SPIMSS_MasterTransHandler(spi,req)!=0) {
+    }
+
+    spi->mod |= MXC_F_SPIMSS_MOD_SSV;
+
+    spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Last of the SPIMSS value has been transmitted...
+                                             // stop the transmission...
+    return E_NO_ERROR;
+}
+
+
+/* ************************************************************************** */
+int SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, spimss_req_t *req)
+{
+    int error;
+ 
+    if ((error = SPIMSS_TransSetup(spi, req,0)) != E_NO_ERROR) {
+        return error;
+    }
+
+    while (SPIMSS_SlaveTransHandler(spi,req)!=0) {
+        spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN;  // Enable/Start SPI
+        while ((spi->status & MXC_F_SPIMSS_STATUS_TXST) == MXC_F_SPIMSS_STATUS_TXST) {}		
+     }
+
+    spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN);  // Last of the SPIMSS value has been transmitted...
+                                              // stop the transmission...
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req)
+{
+    int error;
+    uint8_t int_enable;
+    if ((error = SPIMSS_TransSetup(spi, req, 1) )!= E_NO_ERROR) {
+        return error;		
+    }
+
+    int_enable = SPIMSS_MasterTransHandler(spi,req);
+
+    spi->mod ^= MXC_F_SPIMSS_MOD_SSV;      // This will assert the Slave Select.
+
+    spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN;  // Enable/Start SPI
+
+    if (int_enable==1) {
+        spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
+    }
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req)
+{
+    int error;
+    uint8_t int_enable;
+    if ((error = SPIMSS_TransSetup(spi, req, 0)) != E_NO_ERROR) {
+        return error;
+    }
+
+    int_enable = SPIMSS_SlaveTransHandler(spi,req);
+
+    spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN;  // Enable/Start SPI
+
+    if (int_enable==1) {                   // Trigger a SPI Interrupt
+        spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE );
+    }
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+uint32_t SPIMSS_MasterTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req)
+{
+    unsigned start_set = 0;
+    uint32_t retval;
+
+    if (!start_set) {
+    start_set = 1;
+    retval = SPIMSS_TransHandler(spi,req);
+    }
+
+    return retval;
+}
+
+/* ************************************************************************** */
+uint32_t SPIMSS_SlaveTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req)
+{
+    return SPIMSS_TransHandler(spi,req);
+}
+
+/* ************************************************************************** */
+uint32_t SPIMSS_TransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req)
+{
+    unsigned tx_avail, rx_avail;
+    int remain, spi_num;
+    uint32_t int_en =0;
+    uint32_t length =req->len;
+
+
+    spi_num = MXC_SPIMSS_GET_IDX(spi);
+
+    // Read the RX FIFO
+   if (req->rx_data != NULL) {
+        // Wait for there to be data in the RX FIFO
+        rx_avail = ((spi->dma & MXC_F_SPIMSS_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS);
+        if ((length - req->rx_num) < rx_avail) {
+            rx_avail = (length - req->rx_num);
+        }
+
+       // Read from the FIFO
+        while (rx_avail) {
+
+            // Don't read less than 2 bytes if we are using greater than 8 bit characters
+            if (req->bits>8) {
+                ((uint16_t*)req->rx_data)[req->rx_num++] = spi->data16;
+                rx_avail -= 1;
+
+            } else {
+                ((uint8_t*)req->rx_data)[req->rx_num++] = spi->data8[0];
+                rx_avail -= 1;
+            }
+            rx_avail = ((spi->dma & MXC_F_SPIMSS_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS);
+            if ((length - req->rx_num) < rx_avail) {
+                rx_avail = (length - req->rx_num);
+            }
+        }
+        
+        remain = length - req->rx_num;
+
+        if (remain) {
+            if (remain > MXC_SPIMSS_FIFO_DEPTH) {
+                spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_RX_FIFO_CNT) | ((2) << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS));
+            } else {
+                spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_RX_FIFO_CNT) | ((remain-1) << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS));
+            }
+            
+            int_en = 1;
+        }
+
+        // Break out if we've received all the bytes and we're not transmitting
+        if ((req->tx_data == NULL) && (req->rx_num == length)) {
+            spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
+            int_en = 0;
+            mxc_free_lock((uint32_t*)&states[spi_num].req);
+            // Callback if not NULL
+            if (req->callback != NULL) {
+                req->callback(req, E_NO_ERROR);
+            }
+        }
+    }
+    // Note:- spi->dma shows the FIFO TX count and FIFO RX count in
+    // Words, while the calculation below is in bytes.
+    if (req->tx_data != NULL) {
+
+        if (req->tx_num < length) {
+
+            // Calculate how many bytes we can write to the FIFO (tx_avail holds that value)
+            tx_avail = MXC_SPIMSS_FIFO_DEPTH - (((spi->dma & MXC_F_SPIMSS_DMA_TX_FIFO_CNT) >> MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS));  // in bytes
+
+            if ((length - req->tx_num) < tx_avail) {
+                tx_avail = (length - req->tx_num);   // This is for the last spin
+            }
+            if (req->bits > 8) {
+                tx_avail &= ~(unsigned)0x1;
+            }
+            // Write the FIFO
+            while (tx_avail) {
+                if (req->bits >8) {
+                        spi->data16 = ((uint16_t*)req->tx_data)[req->tx_num++];
+
+                        tx_avail -= 1;
+                } else {
+                    spi->data8[0] = ((uint8_t*)req->tx_data)[req->tx_num++];
+                    tx_avail -=1;
+                }
+
+            }
+        }
+
+        remain = length - req->tx_num;
+
+        // If there are values remaining to be transmitted, this portion will get
+        // executed and int_en set, to indicate that this must spin and come back again...
+        if (remain) {
+            if (remain > MXC_SPIMSS_FIFO_DEPTH) {  //  more tx rounds will happen... Transfer the maximum,
+                spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_TX_FIFO_CNT) | ((MXC_SPIMSS_FIFO_DEPTH) << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS));
+            } else {  // only one more tx round will be done... Transfer whatever remains,
+                spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_TX_FIFO_CNT) | ((remain) << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS));
+            }
+            int_en = 1; // This will act as a trigger for the next round...
+        }
+
+        // Break out if we've transmitted all the bytes and not receiving
+        if ((req->rx_data == NULL) && (req->tx_num == length)) {
+            spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
+            int_en = 0;
+            mxc_free_lock((uint32_t*)&states[spi_num].req);
+            // Callback if not NULL
+            if (req->callback != NULL) {
+                req->callback(req, E_NO_ERROR);
+            }
+        }
+    }
+
+
+    // Break out once we've transmitted and received all of the data
+    if ((req->rx_num == length) && (req->tx_num == length)) {
+        spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
+        int_en = 0;
+        mxc_free_lock((uint32_t*)&states[spi_num].req);
+        // Callback if not NULL
+        if (req->callback != NULL) {
+            req->callback(req, E_NO_ERROR);
+        }
+    }
+
+    return int_en;
+}
+
+/* ************************************************************************* */
+int SPIMSS_AbortAsync(spimss_req_t *req)
+{
+    int spi_num;
+    mxc_spimss_regs_t *spi;
+
+    // Check the input parameters
+    if (req == NULL) {
+        return E_BAD_PARAM;
+    }
+
+    // Find the request, set to NULL
+    for (spi_num = 0; spi_num < MXC_SPIMSS_INSTANCES; spi_num++) {
+        if (req == states[spi_num].req) {
+
+            spi = MXC_SPIMSS_GET_SPI(spi_num);
+
+            // Disable interrupts, clear the flags
+            spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
+
+            // Disable and turn off the SPI transaction.
+        	spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN);
+
+            // Unlock this SPI
+            mxc_free_lock((uint32_t*)&states[spi_num].req);
+
+            // Callback if not NULL
+            if (req->callback != NULL) {
+                req->callback(req, E_ABORT);
+            }
+            return E_NO_ERROR;
+        }
+    }
+
+    return E_BAD_PARAM;
+}
+/**@} end of group spimss */

bsp/maxim/libraries/MAX32660PeriphDriver/Source/tmr.c

@@ -0,0 +1,307 @@
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-09-11 14:32:22 -0500 (Wed, 11 Sep 2019) $
+ * $Revision: 46047 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "tmr.h"
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+/* ************************************************************************** */
+int TMR_Init(mxc_tmr_regs_t *tmr, tmr_pres_t pres, const sys_cfg_tmr_t* sys_cfg)
+{
+    MXC_ASSERT(tmr);
+    
+    int err;
+    // System settigns
+    if((err=SYS_TMR_Init(tmr, sys_cfg)) !=E_NO_ERROR)
+    {
+        return err;
+    }
+    
+    // Disable timer and clear settings
+    tmr->cn = 0;
+    
+    // Clear interrupt flag
+    tmr->intr = MXC_F_TMR_INTR_IRQ_CLR;
+    
+    // Set the prescaler
+    tmr->cn = pres;
+
+    return err;
+}
+
+int TMR_Shutdown(mxc_tmr_regs_t *tmr)
+{
+    MXC_ASSERT(tmr);
+    
+    int err;
+    // System settigns
+    if((err=SYS_TMR_Shutdown(tmr)) !=E_NO_ERROR)
+    {
+        return err;
+    }
+    
+    // Disable timer and clear settings
+    tmr->cn = 0;
+    
+    return err;
+}
+
+/* ************************************************************************** */
+void TMR_Enable(mxc_tmr_regs_t* tmr)
+{
+    MXC_ASSERT(tmr);
+
+    tmr->cn |= MXC_F_TMR_CN_TEN;
+}
+
+/* ************************************************************************** */
+void TMR_Disable(mxc_tmr_regs_t* tmr)
+{
+    MXC_ASSERT(tmr);
+
+    tmr->cn &= ~(MXC_F_TMR_CN_TEN);
+}
+
+/* ************************************************************************** */
+int TMR_Config(mxc_tmr_regs_t *tmr, const tmr_cfg_t *cfg)
+{
+    MXC_ASSERT(tmr);
+    
+    // Configure the timer
+    tmr->cn = (tmr->cn & ~(MXC_F_TMR_CN_TMODE | MXC_F_TMR_CN_TPOL)) |
+              ((cfg->mode << MXC_F_TMR_CN_TMODE_POS) & MXC_F_TMR_CN_TMODE) |
+              ((cfg->pol << MXC_F_TMR_CN_TPOL_POS) & MXC_F_TMR_CN_TPOL);
+              
+    tmr->cnt = 0x1;
+    tmr->cmp = cfg->cmp_cnt;
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int TMR_PWMConfig(mxc_tmr_regs_t *tmr, const tmr_pwm_cfg_t *cfg)
+{
+    if (cfg->duty_cnt > cfg->per_cnt) {
+        return E_BAD_PARAM;
+    }
+    
+    // Configure the timer
+    tmr->cn = (tmr->cn & ~(MXC_F_TMR_CN_TMODE | MXC_F_TMR_CN_TPOL)) |
+              MXC_S_TMR_CN_TMODE_PWM | ((cfg->pol << MXC_F_TMR_CN_TPOL_POS) & MXC_F_TMR_CN_TPOL);
+              
+    tmr->cnt = 0x1;
+    tmr->cmp = cfg->per_cnt;
+    tmr->pwm = cfg->duty_cnt;
+    
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int TMR_PWMSetDuty(mxc_tmr_regs_t *tmr, uint32_t duty)
+{
+    uint32_t cnt;
+    
+    // Make sure the new Duty count is less than the period count
+    if (duty > tmr->cmp) {
+        return E_BAD_PARAM;
+    }
+    
+    cnt = tmr->cnt; // make sure order of volatile access is known.
+    // Avoid glitching the output
+    if (duty >= tmr->pwm) {
+        // Wait for the count to be in the range of 1 to tmr->pwm
+        while (cnt > tmr->pwm) {
+            cnt = tmr->cnt; // update the volatile access variable
+        }
+    } else {
+        // Wait for the count to pass tmr->pwm
+        while (cnt < tmr->pwm) {
+            cnt = tmr->cnt; // update the volatile access variable
+        }
+    }
+    tmr->pwm = duty;
+    
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+int TMR_PWMSetPeriod(mxc_tmr_regs_t *tmr, uint32_t per)
+{
+    // Make sure the new Duty count is less than the period count
+    if (tmr->pwm > per) {
+        return E_BAD_PARAM;
+    }
+    
+    // Wait for the count to be less than the new dut_cnt
+    while (tmr->cnt >= per) {}
+    tmr->cmp = per;
+    
+    return E_NO_ERROR;
+}
+
+
+/* ************************************************************************** */
+uint32_t TMR_GetCompare(mxc_tmr_regs_t* tmr)
+{
+    return tmr->cmp;
+}
+
+/* ************************************************************************** */
+uint32_t TMR_GetCapture(mxc_tmr_regs_t* tmr)
+{
+    return tmr->pwm;
+}
+
+/* ************************************************************************* */
+uint32_t TMR_GetCount(mxc_tmr_regs_t* tmr)
+{
+    return tmr->cnt;
+}
+
+/* ************************************************************************* */
+void TMR_IntClear(mxc_tmr_regs_t* tmr)
+{
+    tmr->intr = MXC_F_TMR_INTR_IRQ_CLR;
+}
+
+/* ************************************************************************* */
+uint32_t TMR_IntStatus(mxc_tmr_regs_t* tmr)
+{
+    return tmr->intr;
+}
+
+/* ************************************************************************* */
+void TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt)
+{
+    tmr->cmp = cmp_cnt;
+}
+
+/* ************************************************************************* */
+void TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt)
+{
+    tmr->cnt = cnt;
+}
+
+/* ************************************************************************* */
+int TMR_GetTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint32_t *ticks)
+{
+    uint32_t unit_div0, unit_div1;
+    uint32_t timerClock;
+    uint32_t prescale;
+    uint64_t temp_ticks;
+    
+    timerClock = SYS_TMR_GetFreq(tmr);
+    prescale = ((tmr->cn & MXC_F_TMR_CN_PRES) >> MXC_F_TMR_CN_PRES_POS) 
+        | (((tmr->cn & MXC_F_TMR_CN_PRES3) >> (MXC_F_TMR_CN_PRES3_POS))<<3);
+    
+    switch (units) {
+        case TMR_UNIT_NANOSEC:
+            unit_div0 = 1000000;
+            unit_div1 = 1000;
+            break;
+        case TMR_UNIT_MICROSEC:
+            unit_div0 = 1000;
+            unit_div1 = 1000;
+            break;
+        case TMR_UNIT_MILLISEC:
+            unit_div0 = 1;
+            unit_div1 = 1000;
+            break;
+        case TMR_UNIT_SEC:
+            unit_div0 = 1;
+            unit_div1 = 1;
+            break;
+        default:
+            return E_BAD_PARAM;
+    }
+    
+    temp_ticks = (uint64_t)time * (timerClock / unit_div0) / (unit_div1 * (1 << (prescale & 0xF)));
+    
+    //make sure ticks is within a 32 bit value
+    if (!(temp_ticks & 0xffffffff00000000)  && (temp_ticks & 0xffffffff)) {
+        *ticks = temp_ticks;
+        return E_NO_ERROR;
+    }
+    
+    return E_INVALID;
+}
+
+/* ************************************************************************* */
+int TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, tmr_unit_t *units)
+{
+    uint64_t temp_time = 0;
+    uint32_t timerClock = SYS_TMR_GetFreq(tmr);
+    uint32_t prescale = ((tmr->cn & MXC_F_TMR_CN_PRES) >> MXC_F_TMR_CN_PRES_POS) 
+        | (((tmr->cn & MXC_F_TMR_CN_PRES3) >> (MXC_F_TMR_CN_PRES3_POS))<<3);
+    
+    temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000000);
+    if (!(temp_time & 0xffffffff00000000)) {
+        *time = temp_time;
+        *units = TMR_UNIT_NANOSEC;
+        return E_NO_ERROR;
+    }
+    
+    temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000);
+    if (!(temp_time & 0xffffffff00000000)) {
+        *time = temp_time;
+        *units = TMR_UNIT_MICROSEC;
+        return E_NO_ERROR;
+    }
+    
+    temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / timerClock;
+    if (!(temp_time & 0xffffffff00000000)) {
+        *time = temp_time;
+        *units = TMR_UNIT_MILLISEC;
+        return E_NO_ERROR;
+    }
+    
+    temp_time = (uint64_t)ticks * (1 << (prescale & 0xF)) / timerClock;
+    if (!(temp_time & 0xffffffff00000000)) {
+        *time = temp_time;
+        *units = TMR_UNIT_SEC;
+        return E_NO_ERROR;
+    }
+    
+    return E_INVALID;
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/tmr_utils.c

@@ -0,0 +1,168 @@
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-10-17 14:16:30 -0500 (Wed, 17 Oct 2018) $
+ * $Revision: 38560 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <stddef.h>
+#include "mxc_assert.h"
+#include "tmr.h"
+#include "tmr_utils.h"
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+/* ************************************************************************** */
+void TMR_Delay(mxc_tmr_regs_t *tmr, unsigned long us, const sys_cfg_tmr_t *sys_cfg)
+{
+    // Return immediately if delay is 0
+    if (!us) {
+        return;
+    }
+    
+    TMR_TO_Start(tmr, us, sys_cfg);
+    
+    while (TMR_TO_Check(tmr) != E_TIME_OUT) {}
+}
+
+/* ************************************************************************** */
+void TMR_TO_Start(mxc_tmr_regs_t *tmr, unsigned long us, const sys_cfg_tmr_t *sys_cfg)
+{
+    uint64_t ticks;
+    int clk_shift = 0;
+    
+    ticks = (uint64_t)us * (uint64_t)PeripheralClock / (uint64_t)1000000;
+    while (ticks > 0xFFFFFFFFUL) {
+        ticks >>= 1;
+        ++clk_shift;
+    }
+    tmr_pres_t prescale = (tmr_pres_t)(clk_shift << MXC_F_TMR_CN_PRES_POS);
+
+    TMR_Init(tmr, prescale, sys_cfg);
+    
+    // Initialize the timer in one-shot mode
+    tmr_cfg_t cfg;
+    cfg.mode = TMR_MODE_ONESHOT;
+    cfg.cmp_cnt = ticks;
+    cfg.pol = 0;
+    
+    TMR_Disable(tmr);
+    TMR_Config(tmr, &cfg);
+    
+    TMR_IntClear(tmr);
+    TMR_Enable(tmr);
+}
+
+/* ************************************************************************** */
+int TMR_TO_Check(mxc_tmr_regs_t *tmr)
+{
+    if (TMR_IntStatus(tmr)) {
+        return E_TIME_OUT;
+    }
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+void TMR_TO_Stop(mxc_tmr_regs_t *tmr)
+{
+    TMR_Disable(tmr);
+    TMR_SetCount(tmr, 0x0);
+}
+
+/* ************************************************************************** */
+void TMR_TO_Clear(mxc_tmr_regs_t *tmr)
+{
+    TMR_IntClear(tmr);
+    TMR_SetCount(tmr, 0x0);
+}
+
+/* ************************************************************************** */
+unsigned int TMR_TO_Elapsed(mxc_tmr_regs_t *tmr)
+{
+    uint32_t elapsed;
+    tmr_unit_t units;
+    
+    TMR_GetTime(tmr, TMR_GetCount(tmr), &elapsed, &units);
+    
+    switch (units) {
+        case TMR_UNIT_NANOSEC:
+        default:
+            return (elapsed / 1000);
+        case TMR_UNIT_MICROSEC:
+            return (elapsed);
+        case TMR_UNIT_MILLISEC:
+            return (elapsed * 1000);
+        case TMR_UNIT_SEC:
+            return (elapsed * 1000000);
+    }
+}
+
+/* ************************************************************************** */
+unsigned int TMR_TO_Remaining(mxc_tmr_regs_t *tmr)
+{
+    uint32_t remaining_ticks, remaining_time;
+    tmr_unit_t units;
+    
+    remaining_ticks = TMR_GetCompare(tmr) - TMR_GetCount(tmr);
+    TMR_GetTime(tmr, remaining_ticks, &remaining_time, &units);
+    
+    switch (units) {
+        case TMR_UNIT_NANOSEC:
+        default:
+            return (remaining_time / 1000);
+        case TMR_UNIT_MICROSEC:
+            return (remaining_time);
+        case TMR_UNIT_MILLISEC:
+            return (remaining_time * 1000);
+        case TMR_UNIT_SEC:
+            return (remaining_time * 1000000);
+    }
+}
+
+/* ************************************************************************** */
+void TMR_SW_Start(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t *sys_cfg)
+{
+    TMR_TO_Start(tmr, 0xFFFFFFFF, sys_cfg);
+}
+
+/* ************************************************************************** */
+unsigned int TMR_SW_Stop(mxc_tmr_regs_t *tmr)
+{
+    unsigned int elapsed = TMR_TO_Elapsed(tmr);
+    TMR_TO_Stop(tmr);
+    return elapsed;
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/uart.c

@@ -0,0 +1,718 @@
+/* ****************************************************************************
+ * Copyright (C) 2014-2018 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2020-09-08 13:28:39 -0500 (Tue, 08 Sep 2020) $
+ * $Revision: 55611 $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <stdint.h>
+#include <string.h>
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "uart_regs.h"
+#include "uart.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+
+/* **** Definitions **** */
+
+#define UART_ER_IF (MXC_F_UART_INT_FL_RX_FRAME_ERROR | \
+                    MXC_F_UART_INT_FL_RX_PARITY_ERROR | \
+                    MXC_F_UART_INT_FL_RX_OVERRUN)
+
+#define UART_ER_IE (MXC_F_UART_INT_EN_RX_FRAME_ERROR | \
+                    MXC_F_UART_INT_EN_RX_PARITY_ERROR | \
+                    MXC_F_UART_INT_EN_RX_OVERRUN )
+
+#define UART_RX_IF (MXC_F_UART_INT_FL_RX_FIFO_THRESH)
+
+#define UART_RX_IE (MXC_F_UART_INT_EN_RX_FIFO_THRESH)
+
+#define UART_TX_IF (MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY | \
+                    MXC_F_UART_INT_FL_TX_FIFO_THRESH)
+
+#define UART_TX_IE (MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY | \
+                    MXC_F_UART_INT_EN_TX_FIFO_THRESH)
+
+#if (TARGET == 32660) || (TARGET == 32665)
+#define MAX_FACTOR 3
+#else
+#define MAX_FACTOR 7
+#endif
+
+/* **** File Scope Data **** */
+
+// Saves the state of the non-blocking read requests.
+static uart_req_t *rx_states[MXC_UART_INSTANCES];
+
+// Saves the state of the non-blocking write requests.
+static uart_req_t *tx_states[MXC_UART_INSTANCES];
+
+
+/* **** Functions **** */
+static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num);
+static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num,
+                             uint32_t flags);
+static uint32_t uart_error_check(mxc_uart_regs_t *uart);
+static void uart_error_clear(mxc_uart_regs_t *uart);
+
+/* ************************************************************************* */
+uint32_t uart_error_check(mxc_uart_regs_t *uart)
+{
+    return (uart->int_fl & UART_ER_IF);
+}
+
+/* ************************************************************************* */
+void uart_error_clear(mxc_uart_regs_t *uart)
+{
+    UART_ClearFlags(uart,UART_ER_IF);
+}
+
+/* ************************************************************************* */
+int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t* sys_cfg)
+{
+    int err;
+    int uart_num;
+    
+    uint32_t baud0 = 0, baud1 = 0,div;
+    int32_t factor = -1;
+    
+    // Get the state array index
+    uart_num = MXC_UART_GET_IDX(uart);
+    if (uart_num == -1) {
+        return E_BAD_PARAM;
+    }
+    
+    if ((err = SYS_UART_Init(uart, sys_cfg)) != E_NO_ERROR) {
+        return err;
+    }
+    
+    // Initialize state pointers
+    rx_states[uart_num] = NULL;
+    tx_states[uart_num] = NULL;
+    
+    // Drain FIFOs, enable UART, and set configuration
+    uart->ctrl = (MXC_F_UART_CTRL_ENABLE | cfg->parity | cfg->size | cfg->stop | cfg->flow | cfg->pol);
+    
+    // Set the baud rate
+    // Calculate divisor
+#if (TARGET != 32660)
+    uart->ctrl |=  cfg->clksel;
+    if (cfg->clksel == UART_CLKSEL_ALTERNATE) {
+        div = UART_ALTERNATE_CLOCK_HZ / ((cfg->baud)); 
+    } else {
+        div = PeripheralClock / ((cfg->baud));
+    }
+#else
+    div = PeripheralClock / ((cfg->baud));
+#endif
+    // Search for integer and fractional baud rate registers based on divisor
+    do {
+	factor += 1;
+	baud0 = div >> (7-factor); // divide by 128,64,32,16 to extract integer part
+	baud1 = ((div << factor) - (baud0 << 7)); //subtract factor corrected div - integer parts
+    } while ((baud0 == 0) && (factor < MAX_FACTOR));
+
+    uart->baud0 = ((factor << MXC_F_UART_BAUD0_FACTOR_POS) | baud0);
+#if (TARGET == 32660) || (TARGET == 32665) || (TARGET == 32650)
+    /* Erratum:
+     *   Hardware bug causes exact baud rates to generate framing error. Slightly mis-adjust timing
+     *   to help avoid this bug.
+     */
+    if (baud1 > 3) {
+	uart->baud1 = baud1 - 3;
+    } else {
+	uart->baud1 = baud1 + 3;
+    }
+#else
+    uart->baud1 = baud1;
+#endif
+
+    // Clear pending requests
+    rx_states[uart_num] = NULL;
+    tx_states[uart_num] = NULL;
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int UART_Shutdown(mxc_uart_regs_t *uart)
+{
+    int uart_num;
+    uart_req_t *temp_req;
+
+    // Get the state array index
+    uart_num = MXC_UART_GET_IDX(uart);
+    if (uart_num < 0) {
+        return E_BAD_PARAM;
+    }
+
+    // Disable interrupts
+    uart->int_en = 0;
+
+    // Flush RX and TX FIFOS
+    uart->ctrl |= (MXC_F_UART_CTRL_TX_FLUSH | MXC_F_UART_CTRL_RX_FLUSH);
+
+    // Call all of the pending callbacks for this UART
+    if(rx_states[uart_num] != NULL) {
+
+        // Save the request
+        temp_req = rx_states[uart_num];
+
+        // Unlock this UART to read
+        mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+        // Callback if not NULL
+        if (temp_req->callback != NULL) {
+            temp_req->callback(temp_req, E_SHUTDOWN);
+        }
+    }
+
+    if (tx_states[uart_num] != NULL) {
+
+        // Save the request
+        temp_req = tx_states[uart_num];
+
+        // Unlock this UART to write
+        mxc_free_lock((uint32_t*)&tx_states[uart_num]);
+
+        // Callback if not NULL
+        if (temp_req->callback != NULL) {
+            temp_req->callback(temp_req, E_SHUTDOWN);
+        }
+    }
+    // Wait for not busy
+    while (uart->status & (MXC_F_UART_STATUS_TX_BUSY | MXC_F_UART_STATUS_RX_BUSY)) {
+        
+    }
+
+    // Shutdown the UART
+    uart->ctrl = 0;
+    
+    // Shutdown any system level setup
+    SYS_UART_Shutdown(uart);
+
+    // Clear pending requests
+    rx_states[uart_num] = NULL;
+    tx_states[uart_num] = NULL;
+    
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+void UART_Handler(mxc_uart_regs_t *uart)
+{
+    int uart_num; // Holds the current index of rx_states or tx_states
+    uint32_t intst;
+
+    // Get the state array index
+    uart_num = MXC_UART_GET_IDX(uart);
+    if (uart_num == -1) {
+        return;
+    }
+
+    // Read and clear interrupts
+    intst = uart->int_fl;
+    uart->int_fl = intst;
+
+    // Read interrupt
+    if (intst & (UART_RX_IF | UART_ER_IF)) {
+        UART_ReadHandler(uart, rx_states[uart_num], uart_num, intst);
+    }
+
+    // Write Interrupt
+    if (intst & (UART_TX_IF | UART_ER_IF)) {
+        UART_WriteHandler(uart, tx_states[uart_num], uart_num);
+    }
+}
+
+/* ************************************************************************* */
+static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num)
+{
+    int remain, avail;
+    req = tx_states[uart_num];
+
+    if (req == NULL) {
+        // Nothing to do
+        uart->int_en &= ~MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY; // disable interrupt
+        return;
+    }
+
+    // Refill the TX FIFO
+    avail = UART_NumWriteAvail(uart);
+    remain = req->len - req->num;
+
+    while (avail && remain) {
+        uart->fifo = req->data[req->num++];
+        remain--;
+        avail--;
+    }
+
+    // See if we've sent all of the characters
+    if (req->len == req->num) {
+        // Disable interrupts
+        uart->int_en &= ~MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY;
+
+        // Deinit state before callback in case another is requested
+        tx_states[uart_num] = NULL;
+        mxc_free_lock((uint32_t*)&tx_states[uart_num]);
+
+        // Callback when we've written all the characters
+        if (req->callback != NULL) {
+            req->callback(req, E_NO_ERROR);
+        }
+    }
+    // Enable the interrupts
+    uart->int_en |= UART_TX_IE | UART_ER_IE;
+
+}
+
+/* ************************************************************************* */
+static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num,
+                             uint32_t flags)
+{
+    int remain, avail;
+
+    if (req == NULL) {
+        // Nothing to do
+        uart->int_en &= ~(UART_RX_IE | UART_ER_IE); // disable interrupts
+        return;
+    }
+    // Save the data in the FIFO while we still need data
+    avail = UART_NumReadAvail(uart);
+    remain = req->len - req->num;
+    while (avail && remain) {
+        req->data[req->num++] = uart->fifo;
+        remain--;
+        avail--;
+    }
+    // Check for errors
+    if (flags & MXC_F_UART_INT_FL_RX_OVERRUN) {
+
+        // Unlock this UART to read
+        mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+        if (req->callback != NULL) {
+            req->callback(req, E_OVERFLOW);
+        }
+
+        return;
+    }
+    if (flags & (MXC_F_UART_INT_FL_RX_FRAME_ERROR |
+                MXC_F_UART_INT_FL_RX_PARITY_ERROR)) {
+
+        // Unlock this UART to read
+        mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+        if (req->callback != NULL)         {
+            req->callback(req, E_COMM_ERR);
+        }
+
+        return;
+    }
+    // Check to see if we've received all of the characters.
+    if (req->num == req->len) {
+        // Disable interrupts
+        uart->int_en &= ~(UART_RX_IE | UART_ER_IE);
+
+        // Deinit state before callback in case another is requested
+        rx_states[uart_num] = NULL;
+
+        // Call the callback function
+        if (req->callback != NULL) {
+            req->callback(req, E_NO_ERROR);
+        }
+
+        return;
+    } else if (req->num > (req->len - MXC_UART_FIFO_DEPTH)) {
+        // Set RX threshold less than FIFO_DEPTH characters if needed
+        uart->thresh_ctrl = ((req->len - req->num)<<
+                       MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS);
+    } else {
+        uart->thresh_ctrl = MXC_UART_FIFO_DEPTH<<
+                      MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS;
+    }
+}
+
+/* ************************************************************************* */
+int UART_Read(mxc_uart_regs_t *uart, uint8_t *data, int len, int *num)
+{
+    int uart_num; // Holds the current index of rx_states
+    int char_read = 0; // Holds the number of characters successfully read
+    int error_code =0; // Holds the error to return while reading
+
+    // Get the state array index
+    uart_num = MXC_UART_GET_IDX(uart);
+    if (uart_num < 0) {
+        return E_BAD_PARAM;
+    }
+
+    // Check to make sure baud rate has been set
+    if (uart->baud0 == 0) {
+        return E_UNINITIALIZED;
+    }
+
+    // Check data pointer
+    if (data == NULL) {
+        return E_BAD_PARAM;
+    }
+
+    // Check if there is already a request in progress
+    if (rx_states[uart_num] != NULL) {
+        return E_BUSY;
+    }
+
+    // Lock this UART from reading
+    while (mxc_get_lock((uint32_t*)&rx_states[uart_num], 1) != E_NO_ERROR) {
+        
+    }
+
+    // Get bytes FIFO
+    while (char_read < len) {
+        // Wait for RXFIFO to not be empty
+        while (uart->status & MXC_F_UART_STATUS_RX_EMPTY) {
+            // Check for error
+            if (uart_error_check(uart) != E_NO_ERROR) {
+                if (uart->int_fl & MXC_F_UART_INT_FL_RX_OVERRUN) {
+                    error_code = E_OVERFLOW;
+                } else {
+                    error_code = E_COMM_ERR;
+                }
+
+                uart_error_clear(uart);
+                mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+                return error_code;
+            }
+        }
+        data[char_read] = uart->fifo;
+        char_read++;
+    }
+    if (num != NULL) {
+        *num = char_read;
+    }
+    // Unlock this UART to read
+    mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+    return char_read;
+}
+
+/* ************************************************************************* */
+uint8_t UART_ReadByte(mxc_uart_regs_t *uart)
+{
+
+    while (uart->status & MXC_F_UART_STATUS_RX_EMPTY) {}
+
+    return uart->fifo;
+}
+
+/* ************************************************************************* */
+int UART_Write(mxc_uart_regs_t *uart, const uint8_t *data, int len)
+{
+    int uart_num; // Holds the current index of tx_states
+    int char_written = 0;  // Holds the number of characters successfully written
+
+    // Get the state array index
+    uart_num = MXC_UART_GET_IDX(uart);
+    if (uart_num < 0) {
+        return E_BAD_PARAM;
+    }
+
+    // Check to make sure baud rate has been set
+    if (uart->baud0 == 0) {
+        return E_UNINITIALIZED;
+    }
+
+    // Check data pointer
+    if (data == NULL) {
+        return E_BAD_PARAM;
+    }
+
+    // Check if there is already a request in progress
+    if (tx_states[uart_num] != NULL) {
+        return E_BUSY;
+    }
+
+    // Lock this UART from writing
+    while (mxc_get_lock((uint32_t*)&tx_states[uart_num], 1) != E_NO_ERROR) {
+        
+    }
+
+    // Clear errors
+    uart_error_clear(uart);
+
+    // Put bytes into FIFO
+    while (char_written < len) {
+        UART_WriteByte(uart,data[char_written]);
+        char_written++;
+    }
+
+    // Unlock this UART to write
+    mxc_free_lock((uint32_t*)&tx_states[uart_num]);
+
+    return char_written;
+}
+
+/* ************************************************************************* */
+void UART_WriteByte(mxc_uart_regs_t *uart, uint8_t data)
+{
+
+    // Wait for TXFIFO if full
+    while (uart->status & MXC_F_UART_STATUS_TX_FULL) {
+        
+    }
+
+    // Put data into fifo
+    uart->fifo = data;
+}
+
+/* ************************************************************************* */
+int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req)
+{
+    int uart_num; // Holds the current index of tx_states
+    uint32_t flags;  // Holds the Interrupt flags
+
+    // Check data pointer
+    if (req == NULL) {
+        return E_BAD_PARAM;
+    }
+
+    // Get the state array index
+    uart_num = MXC_UART_GET_IDX(uart);
+    if (uart_num < 0) {
+        return E_BAD_PARAM;
+    }
+
+    if (req->data == NULL) {
+        return E_NULL_PTR;
+    }
+    // Check to make sure baud rate has been set
+    if (uart->baud0 == 0) {
+        return E_UNINITIALIZED;
+    }
+
+    // Check if there is already a request in progress
+    if (rx_states[uart_num] != NULL) {
+        return E_BUSY;
+    }
+
+    if (!(req->len > 0)) {
+        return E_NO_ERROR;
+    }
+
+    // Attempt to register this write request
+    if (mxc_get_lock((uint32_t*)&rx_states[uart_num], (uint32_t)req) != E_NO_ERROR) {
+        return E_BUSY;
+    }
+
+    // Clear the data counter
+    req->num = 0;
+
+    // Clear Interrupt Flags
+    flags = uart->int_fl;
+    uart->int_fl = flags;
+    UART_ReadHandler(uart,req,uart_num,flags);
+
+    // Enable the interrupts
+    uart->int_en |= UART_RX_IE | UART_ER_IE;
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req)
+{
+    int uart_num;  // Holds the current index of tx_states
+
+    // Check data pointer
+    if (req == NULL) {
+        return E_BAD_PARAM;
+    }
+
+    // Get the state array index
+    uart_num = MXC_UART_GET_IDX(uart);
+    if (uart_num < 0) {
+        return E_BAD_PARAM;
+    }
+
+    if (req->data == NULL) {
+        return E_NULL_PTR;
+    }
+    // Check to make sure baud rate has been set
+    if (uart->baud0 == 0) {
+        return E_UNINITIALIZED;
+    }
+
+    // Check if there is already a request in progress
+    if (tx_states[uart_num] != NULL) {
+        return E_BUSY;
+    }
+    if (!(req->len > 0)) {
+        return E_NO_ERROR;
+    }
+    // Attempt to register this write request
+    if (mxc_get_lock((uint32_t*)&tx_states[uart_num], (uint32_t)req) != E_NO_ERROR) {
+        return E_BUSY;
+    }
+
+    // Clear the data counter
+    req->num = 0;
+    UART_WriteHandler(uart, req, uart_num);
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int UART_Busy(mxc_uart_regs_t *uart)
+{
+    int uart_num = MXC_UART_GET_IDX(uart);  // Holds the current index of tx_states
+    MXC_ASSERT(uart_num >= 0);
+    if ((uart->status & MXC_F_UART_STATUS_TX_BUSY) || (uart->status & MXC_F_UART_STATUS_RX_BUSY)) {
+        return E_BUSY;
+    }
+    // Check to see if there are any ongoing transactions and the UART has room in its FIFO
+    if ((tx_states[uart_num] == NULL) &&
+            !(uart->status & MXC_F_UART_STATUS_TX_FULL)) {
+
+        return E_NO_ERROR;
+    }
+
+    return E_BUSY;
+}
+
+/* ************************************************************************* */
+int UART_PrepForSleep(mxc_uart_regs_t *uart)
+{
+    if (UART_Busy(uart) != E_NO_ERROR) {
+        return E_BUSY;
+    }
+
+    // Leave read interrupts enabled, if already enabled
+    uart->int_en &= (UART_RX_IE | UART_ER_IE);
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int UART_AbortAsync(uart_req_t *req)
+{
+    int uart_num;
+
+    // Figure out if this was a read or write request, find the request, set to NULL
+    for (uart_num = 0; uart_num < MXC_UART_INSTANCES; uart_num++) {
+        if (req == rx_states[uart_num]) {
+
+            // Disable read interrupts, clear flags.
+            MXC_UART_GET_UART(uart_num)->int_en &= ~(UART_RX_IE | UART_ER_IE);
+            MXC_UART_GET_UART(uart_num)->int_fl = (UART_RX_IF | UART_ER_IF);
+
+            // Unlock this UART to read
+            mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+            // Callback if not NULL
+            if (req->callback != NULL) {
+                req->callback(req, E_ABORT);
+            }
+
+            return E_NO_ERROR;
+        }
+
+        if (req == tx_states[uart_num]) {
+
+            // Disable write interrupts, clear flags.
+            MXC_UART_GET_UART(uart_num)->int_en &= ~(UART_TX_IE | UART_ER_IE);
+            MXC_UART_GET_UART(uart_num)->int_fl = (UART_TX_IF | UART_ER_IF);
+
+            // Unlock this UART to write
+            mxc_free_lock((uint32_t*)&tx_states[uart_num]);
+
+            // Callback if not NULL
+            if (req->callback != NULL) {
+                req->callback(req, E_ABORT);
+            }
+
+            return E_NO_ERROR;
+        }
+    }
+
+    return E_BAD_PARAM;
+}
+
+/* ************************************************************************* */
+unsigned UART_NumWriteAvail(mxc_uart_regs_t *uart)
+{
+    return MXC_UART_FIFO_DEPTH - ((uart->status & MXC_F_UART_STATUS_TX_FIFO_CNT) >>
+                                  MXC_F_UART_STATUS_TX_FIFO_CNT_POS);
+}
+
+/* ************************************************************************* */
+unsigned UART_NumReadAvail(mxc_uart_regs_t *uart)
+{
+    return ((uart->status & MXC_F_UART_STATUS_RX_FIFO_CNT) >>
+            MXC_F_UART_STATUS_RX_FIFO_CNT_POS);
+}
+
+/* ************************************************************************* */
+unsigned UART_GetFlags(mxc_uart_regs_t *uart)
+{
+    return (uart->int_fl);
+}
+
+/* ************************************************************************* */
+void UART_ClearFlags(mxc_uart_regs_t *uart, uint32_t mask)
+{
+    uart->int_fl = mask;
+}
+
+/* ************************************************************************* */
+void UART_Enable(mxc_uart_regs_t *uart)
+{
+    uart->ctrl |= MXC_F_UART_CTRL_ENABLE;
+}
+
+/* ************************************************************************* */
+void UART_Disable(mxc_uart_regs_t *uart)
+{
+    uart->ctrl &= ~MXC_F_UART_CTRL_ENABLE;
+}
+
+/* ************************************************************************* */
+void UART_DrainRX(mxc_uart_regs_t *uart)
+{
+    uart->ctrl |= MXC_F_UART_CTRL_RX_FLUSH;
+}
+
+/* ************************************************************************* */
+void UART_DrainTX(mxc_uart_regs_t *uart)
+{
+    uart->ctrl |= MXC_F_UART_CTRL_TX_FLUSH;
+}

bsp/maxim/libraries/MAX32660PeriphDriver/Source/wdt.c

@@ -0,0 +1,129 @@
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "mxc_errors.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "wdt.h"
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+/* ************************************************************************** */
+int WDT_Init(mxc_wdt_regs_t* wdt, sys_cfg_wdt_t sys_cfg)
+{
+    SYS_WDT_Init(wdt, sys_cfg);
+
+    return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+void WDT_SetIntPeriod(mxc_wdt_regs_t* wdt, wdt_period_t period)
+{
+    MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_CTRL_INT_PERIOD, period);
+}
+
+/* ************************************************************************** */
+void WDT_SetResetPeriod(mxc_wdt_regs_t* wdt, wdt_period_t period)
+{
+    MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_CTRL_RST_PERIOD, (period << (MXC_F_WDT_CTRL_RST_PERIOD_POS - MXC_F_WDT_CTRL_INT_PERIOD_POS)));
+}
+
+/* ************************************************************************** */
+void WDT_Enable(mxc_wdt_regs_t* wdt, int enable)
+{
+    if (enable) {
+        wdt->ctrl |= MXC_F_WDT_CTRL_WDT_EN;
+    } else {
+        wdt->ctrl &= ~(MXC_F_WDT_CTRL_WDT_EN);
+    }
+}
+
+/* ************************************************************************** */
+void WDT_EnableInt(mxc_wdt_regs_t* wdt, int enable)
+{
+    if (enable) {
+        wdt->ctrl |= MXC_F_WDT_CTRL_INT_EN;
+    } else {
+        wdt->ctrl &= ~(MXC_F_WDT_CTRL_INT_EN);
+    }
+}
+
+/* ************************************************************************** */
+void WDT_EnableReset(mxc_wdt_regs_t* wdt, int enable)
+{
+    if (enable) {
+        wdt->ctrl |= MXC_F_WDT_CTRL_RST_EN;
+    } else {
+        wdt->ctrl &= ~(MXC_F_WDT_CTRL_RST_EN);
+    }
+}
+
+/* ************************************************************************** */
+void WDT_ResetTimer(mxc_wdt_regs_t* wdt)
+{
+    wdt->rst = 0x00A5;
+    wdt->rst = 0x005A;
+}
+
+/* ************************************************************************** */
+int WDT_GetResetFlag(mxc_wdt_regs_t* wdt)
+{
+    return !!(wdt->ctrl & MXC_F_WDT_CTRL_RST_FLAG);
+}
+
+/* ************************************************************************** */
+void WDT_ClearResetFlag(mxc_wdt_regs_t* wdt)
+{
+    wdt->ctrl &= ~(MXC_F_WDT_CTRL_RST_FLAG);
+}
+
+/* ************************************************************************** */
+int WDT_GetIntFlag(mxc_wdt_regs_t* wdt)
+{
+    return !!(wdt->ctrl & MXC_F_WDT_CTRL_INT_FLAG);
+}
+
+/* ************************************************************************** */
+void WDT_ClearIntFlag(mxc_wdt_regs_t* wdt)
+{
+    wdt->ctrl &= ~(MXC_F_WDT_CTRL_INT_FLAG);
+}

bsp/maxim/libraries/MAX32660PeriphDriver/periphdriver.mk

@@ -0,0 +1,77 @@
+################################################################################
+ # Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ #
+ # Permission is hereby granted, free of charge, to any person obtaining a
+ # copy of this software and associated documentation files (the "Software"),
+ # to deal in the Software without restriction, including without limitation
+ # the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ # and/or sell copies of the Software, and to permit persons to whom the
+ # Software is furnished to do so, subject to the following conditions:
+ #
+ # The above copyright notice and this permission notice shall be included
+ # in all copies or substantial portions of the Software.
+ #
+ # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ # IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ # OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ # OTHER DEALINGS IN THE SOFTWARE.
+ #
+ # Except as contained in this notice, the name of Maxim Integrated
+ # Products, Inc. shall not be used except as stated in the Maxim Integrated
+ # Products, Inc. Branding Policy.
+ #
+ # The mere transfer of this software does not imply any licenses
+ # of trade secrets, proprietary technology, copyrights, patents,
+ # trademarks, maskwork rights, or any other form of intellectual
+ # property whatsoever. Maxim Integrated Products, Inc. retains all
+ # ownership rights.
+ #
+ # $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ 
+ # $Revision: 40072 $
+ #
+ ###############################################################################
+
+################################################################################
+# This file can be included in a project makefile to build the library for the 
+# project.
+################################################################################
+
+ifeq "$(PERIPH_DRIVER_DIR)" ""
+$(error "PERIPH_DRIVER_DIR must be specified")
+endif
+
+# Specify the build directory if not defined by the project
+ifeq "$(BUILD_DIR)" ""
+PERIPH_DRIVER_BUILD_DIR=$(CURDIR)/build/PeriphDriver
+else
+PERIPH_DRIVER_BUILD_DIR=$(BUILD_DIR)/PeriphDriver
+endif
+
+# Export paths needed by the peripheral driver makefile. Since the makefile to
+# build the library will execute in a different directory, paths must be
+# specified absolutely
+PERIPH_DRIVER_BUILD_DIR := ${abspath ${PERIPH_DRIVER_BUILD_DIR}}
+export TOOL_DIR := ${abspath ${TOOL_DIR}}
+export CMSIS_ROOT := ${abspath ${CMSIS_ROOT}}
+
+# Export other variables needed by the peripheral driver makefile
+export TARGET
+export COMPILER
+export TARGET_MAKEFILE
+export PROJ_CFLAGS
+export PROJ_LDFLAGS
+export MXC_OPTIMIZE_CFLAGS
+
+# Add to library list
+LIBS += ${PERIPH_DRIVER_BUILD_DIR}/PeriphDriver.a
+
+# Add to include directory list
+IPATH += ${PERIPH_DRIVER_DIR}/Include
+
+# Add rule to build the Driver Library
+${PERIPH_DRIVER_BUILD_DIR}/PeriphDriver.a: FORCE
+	$(MAKE) -C ${PERIPH_DRIVER_DIR} lib BUILD_DIR=${PERIPH_DRIVER_BUILD_DIR}
+