[n32] 增加多个BSP支持 (#6543)

add bsp n32g43xcl-stb,n32g45xcl-stb,n32g45xml-stb,n32g45xrl-stb,n32g457qel-stb,n32l40xcl-stb,n32l43xml-stb,n32l43xrl-stb,n32l436_evb,n32wb45xl-evb

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_common_tables.h

@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_common_tables.h
+ * Description:  Extern declaration for common tables
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_const_structs.h

@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_const_structs.h
+ * Description:  Constant structs that are initialized for user convenience.
+ *               For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_math.h

@@ -0,0 +1,7157 @@
+/******************************************************************************
+ * @file     arm_math.h
+ * @brief    Public header file for CMSIS DSP LibraryU
+ * @version  V1.5.3
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+   * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
+   * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
+   * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
+   * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
+   * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+   * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
+   *
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
+   *
+   * Preprocessor Macros
+   * ------------
+   *
+   * Each library project have different preprocessor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - ARM_MATH_ARMV8MxL:
+   *
+   * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
+   * on Armv8-M Mainline target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+   *
+   * - __DSP_PRESENT:
+   *
+   * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   *
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   *
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+  #include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+  #include "core_armv8mbl.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+  #include "core_armv8mml.h"
+  #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+    #define ARM_MATH_DSP
+  #endif
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31          (0x100)
+#define DELTA_Q15          0x5
+#define INDEX_MASK         0x0000003F
+#ifndef PI
+  #define PI               3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SPACING_Q31     0x400000
+#define TABLE_SPACING_Q15     0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING         0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if   defined ( __CC_ARM )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+#define __SIMD64(addr)        (*(int64_t **) & (addr))
+
+#if !defined (ARM_MATH_DSP)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
+                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
+                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+    q31_t out;
+    uint32_t tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t) (__CLZ( in) - 1));
+    }
+    else
+    {
+      signBits = ((uint32_t) (__CLZ(-in) - 1));
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >> 24);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0U; i < 2U; i++)
+    {
+      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+      tempVal = 0x7FFFFFFFu - tempVal;
+      /*      1.31 with exp 1 */
+      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1U);
+  }
+
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+    q15_t out = 0;
+    uint32_t tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t)(__CLZ( in) - 17));
+    }
+    else
+    {
+      signBits = ((uint32_t)(__CLZ(-in) - 17));
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >>  8);
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0U; i < 2U; i++)
+    {
+      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFFu - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+  }
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if !defined (ARM_MATH_DSP)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
+    q31_t r = 0, s = 0;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+  uint32_t x)
+  {
+    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
+  }
+
+  /*
+   * @brief C custom defined SMMLA for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+  int32_t x,
+  int32_t y,
+  int32_t sum)
+  {
+    return (sum + (int32_t) (((int64_t) x * y) >> 32));
+  }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed.
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in]  S          points to an instance of the Q15 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in]  S          points to an instance of the floating-point FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q15;
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_casd_df1_inst_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q31;
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]   pSrcA  points to the first input matrix structure
+   * @param[in]   pSrcB  points to the second input matrix structure
+   * @param[out]  pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  pSrc   points to the input matrix
+   * @param[in]  scale  scale factor
+   * @param[out] pDst   points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];     /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;          /**< The proportional gain. */
+    float32_t Ki;          /**< The integral gain. */
+    float32_t Kd;          /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] S               points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] S  is an instance of the floating-point PID Control structure
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] S   points to an instance of the Q31 PID Control structure
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] S  points to an instance of the q15 PID Control structure
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;        /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+    const arm_cfft_instance_q15 * S,
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+    const arm_cfft_instance_q31 * S,
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;             /**< length of the real sequence */
+    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+   arm_rfft_fast_instance_f32 * S,
+   uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    float32_t normalize;                 /**< normalizing factor. */
+    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;               /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q31_t normalize;                     /**< normalizing factor. */
+    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q15_t normalize;                     /**< normalizing factor. */
+    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  scale      scale factor to be applied
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q15(
+          q15_t * pSrcA,
+          uint32_t srcALen,
+          q15_t * pSrcB,
+          uint32_t srcBLen,
+          q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc  points to the block of input data.
+   * @param[out] pDst  points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   */
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.   The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S          points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages.
+ */
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize  number of samples to process per call.
+ */
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] S          points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to the state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] S          points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;         /**< step size that control filter coefficient updates. */
+    float32_t energy;     /**< saves previous frame energy. */
+    float32_t x0;         /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
+    q15_t energy;         /**< saves previous frame energy. */
+    q15_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta   input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cos output.
+   */
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal);
+
+
+  /**
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cosine output.
+   */
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] S   is an instance of the floating-point PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] S  points to an instance of the Q31 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31U);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] S   points to an instance of the Q15 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#if defined (ARM_MATH_DSP)
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+  }
+
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]  Ia       input three-phase coordinate <code>a</code>
+   * @param[in]  Ib       input three-phase coordinate <code>b</code>
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+  }
+
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output   rotor reference frame d
+   * @param[out] pIq     points to output   rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+  }
+
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output rotor reference frame d
+   * @param[out] pIq     points to output rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for   Q31 version
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
+   * @param[in]     x  input sample to process
+   * @return y processed output sample.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if (i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if ((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 +  i      * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q31 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (q31_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1U);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q15 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (int32_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (q15_t) (y >> 20);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q7 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+    if (index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (q7_t) (y >> 20);
+     }
+  }
+
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  sin(x).
+   */
+  float32_t arm_sin_f32(
+  float32_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q31_t arm_sin_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q15_t arm_sin_q15(
+  q15_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  cos(x).
+   */
+  float32_t arm_cos_f32(
+  float32_t x);
+
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q31_t arm_cos_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in    input value.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if (in >= 0.0f)
+    {
+
+#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0U;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0U)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] result     is output pointer
+   * @param[in]  index      is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q31 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q15 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q7 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate.
+  * @param[in]     Y  interpolation coordinate.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11U;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
+    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11U;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
+    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return ((q31_t)(acc << 2));
+  }
+
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return ((q15_t)(acc >> 36));
+  }
+
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return ((q7_t)(acc >> 40));
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if   defined ( __CC_ARM )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("push")         \
+       _Pragma ("O1")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_EXIT \
+       _Pragma ("pop")
+  #else
+    #define LOW_OPTIMIZATION_EXIT
+  #endif
+
+  /* Enter low optimization region - place directly above function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+  #define LOW_OPTIMIZATION_ENTER \
+       __attribute__(( optimize("-O1") ))
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define LOW_OPTIMIZATION_EXIT
+
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef   __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armcc.h

@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armclang.h

@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_compiler.h

@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_gcc.h

@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.4
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h

@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/core_cm4.h

@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/mpu_armv7.h

@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i)
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x.h

@@ -0,0 +1,7744 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_H__
+#define __N32G43X_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup N32G43x_Library_Basic
+ * @{
+ */
+
+#if !defined USE_STDPERIPH_DRIVER
+/*
+ * Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+#define USE_STDPERIPH_DRIVER
+#endif
+
+/*
+ * In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application
+
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined HSE_VALUE
+#define HSE_VALUE (8000000) /*!< Value of the External oscillator in Hz */
+#endif                      /* HSE_VALUE */
+
+/*
+ * In the following line adjust the External High Speed oscillator (HSE) Startup
+   Timeout value
+   */
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /*!< Time out for HSE start up */
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */
+#define MSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for MSI start up */
+
+#define MSI_VALUE_L0 (100000)  /*!< L0 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L1 (200000)  /*!< L1 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L2 (400000)  /*!< L2 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L3 (800000)  /*!< L3 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L4 (1000000) /*!< L4 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L5 (2000000) /*!< L5 Value of the Multi oscillator in Hz*/
+#define MSI_VALUE_L6 (4000000) /*!< L6 Value of the Multi oscillator in Hz*/
+
+#define HSI_VALUE (16000000) /*!< Value of the Internal oscillator in Hz*/
+
+#define __N32G43x_STDPERIPH_VERSION_MAIN (0x00) /*!< [31:24] main version */
+#define __N32G43x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __N32G43x_STDPERIPH_VERSION_SUB2 (0x07) /*!< [15:8]  sub2 version */
+#define __N32G43x_STDPERIPH_VERSION_RC   (0x00) /*!< [7:0]  release candidate */
+
+/**
+ * @brief N32G43x Standard Peripheral Library version number
+ */
+#define __N32G43x_STDPERIPH_VERSION                                                                                    \
+    ((__N32G43x_STDPERIPH_VERSION_MAIN << 24) | (__N32G43x_STDPERIPH_VERSION_SUB1 << 16)                               \
+     | (__N32G43x_STDPERIPH_VERSION_SUB2 << 8) | (__N32G43x_STDPERIPH_VERSION_RC))
+
+/*
+ * Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#ifdef N32G43X
+#define __MPU_PRESENT 1          /*!< N32G43x devices does not provide an MPU */
+#define __FPU_PRESENT 1          /*!< FPU present                            */
+#endif                           /* N32G43x */
+#define __NVIC_PRIO_BITS       4 /*!< N32G43x uses 4 Bits for the Priority Levels    */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief N32G43x Interrupt Number Definition
+ */
+typedef enum IRQn
+{
+    /******  Cortex-M4 Processor Exceptions Numbers ***************************************************/
+    NonMaskableInt_IRQn   = -14, /*!< 2 Non Maskable Interrupt                            */
+    HardFault_IRQn        = -13, /*!< 3 Hard Fault Interrupt                              */
+    MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt             */
+    BusFault_IRQn         = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt                     */
+    UsageFault_IRQn       = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt                   */
+    SVCall_IRQn           = -5,  /*!< 11 Cortex-M4 SV Call Interrupt                      */
+    DebugMonitor_IRQn     = -4,  /*!< 12 Cortex-M4 Debug Monitor Interrupt                */
+    PendSV_IRQn           = -2,  /*!< 14 Cortex-M4 Pend SV Interrupt                      */
+    SysTick_IRQn          = -1,  /*!< 15 Cortex-M4 System Tick Interrupt                  */
+
+    /******  N32G43x specific Interrupt Numbers ********************************************************/
+    WWDG_IRQn             = 0,  /*!< Window WatchDog Interrupt                            */
+    PVD_IRQn              = 1,  /*!< PVD through EXTI Line detection Interrupt            */
+    TAMPER_IRQn           = 2,  /*!< RTC Tamper interrupt or Timestamp through EXTI line 19 */
+    RTC_IRQn              = 3,  /*!< RTC wakeup timer through EXTI line 20                */
+    FLASH_IRQn            = 4,  /*!< FLASH global Interrupt                               */
+    RCC_IRQn              = 5,  /*!< RCC global Interrupt                                 */
+    EXTI0_IRQn            = 6,  /*!< EXTI Line0 Interrupt                                 */
+    EXTI1_IRQn            = 7,  /*!< EXTI Line1 Interrupt                                 */
+    EXTI2_IRQn            = 8,  /*!< EXTI Line2 Interrupt                                 */
+    EXTI3_IRQn            = 9,  /*!< EXTI Line3 Interrupt                                 */
+    EXTI4_IRQn            = 10, /*!< EXTI Line4 Interrupt                                 */
+    DMA_Channel1_IRQn     = 11, /*!< DMA Channel 1 global Interrupt                       */
+    DMA_Channel2_IRQn     = 12, /*!< DMA Channel 2 global Interrupt                       */
+    DMA_Channel3_IRQn     = 13, /*!< DMA Channel 3 global Interrupt                       */
+    DMA_Channel4_IRQn     = 14, /*!< DMA Channel 4 global Interrupt                       */
+    DMA_Channel5_IRQn     = 15, /*!< DMA Channel 5 global Interrupt                       */
+    DMA_Channel6_IRQn     = 16, /*!< DMA Channel 6 global Interrupt                       */
+    DMA_Channel7_IRQn     = 17, /*!< DMA Channel 7 global Interrupt                       */
+    DMA_Channel8_IRQn     = 18, /*!< DMA Channel 8 global Interrupt                       */
+    ADC_IRQn              = 19, /*!< ADC global Interrupt                                 */
+    USB_HP_IRQn           = 20, /*!< USB Device High Priority Interrupts                  */
+    USB_LP_IRQn           = 21, /*!< USB Device Low Priority Interrupts                   */
+    COMP_1_2_IRQn         = 22, /*!< COMP1 & COMP2 global Interrupt through EXTI line 21/22 */
+    EXTI9_5_IRQn          = 23, /*!< External Line[9:5] Interrupts                        */
+    TIM1_BRK_IRQn         = 24, /*!< TIM1 Break Interrupt                                 */
+    TIM1_UP_IRQn          = 25, /*!< TIM1 Update Interrupt                                */
+    TIM1_TRG_COM_IRQn     = 26, /*!< TIM1 Trigger and Commutation Interrupt               */
+    TIM1_CC_IRQn          = 27, /*!< TIM1 Capture Compare Interrupt                       */
+    TIM2_IRQn             = 28, /*!< TIM2 global Interrupt                                */
+    TIM3_IRQn             = 29, /*!< TIM3 global Interrupt                                */
+    TIM4_IRQn             = 30, /*!< TIM4 global Interrupt                                */
+    I2C1_EV_IRQn          = 31, /*!< I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn          = 32, /*!< I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn          = 33, /*!< I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn          = 34, /*!< I2C2 Error Interrupt                                 */
+    SPI1_IRQn             = 35, /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn             = 36, /*!< SPI2 global Interrupt                                */
+    USART1_IRQn           = 37, /*!< USART1 global Interrupt                              */
+    USART2_IRQn           = 38, /*!< USART2 global Interrupt                              */
+    USART3_IRQn           = 39, /*!< USART3 global Interrupt                              */
+    EXTI15_10_IRQn        = 40, /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn         = 41, /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn        = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+    TIM8_BRK_IRQn         = 43, /*!< TIM8 Break Interrupt                                 */
+    TIM8_UP_IRQn          = 44, /*!< TIM8 Update Interrupt                                */
+    TIM8_TRG_COM_IRQn     = 45, /*!< TIM8 Trigger and Commutation Interrupt               */
+    TIM8_CC_IRQn          = 46, /*!< TIM8 Capture Compare Interrupt                       */
+    UART4_IRQn            = 47, /*!< UART4 global Interrupt                               */
+    UART5_IRQn            = 48, /*!< UART5 global Interrupt                               */
+    LPUART_IRQn           = 49, /*!< LPUART global Interrupt                              */
+    TIM5_IRQn             = 50, /*!< TIM5 global Interrupt                                */
+    TIM6_IRQn             = 51, /*!< TIM6 global Interrupt                                */
+    TIM7_IRQn             = 52, /*!< TIM7 global Interrupt                                */
+    CAN_TX_IRQn           = 53, /*!< CAN TX Interrupt                                     */
+    CAN_RX0_IRQn          = 54, /*!< CAN RX0 Interrupt                                    */
+    CAN_RX1_IRQn          = 55, /*!< CAN RX1 Interrupt                                    */
+    CAN_SCE_IRQn          = 56, /*!< CAN SCE Interrupt                                    */
+    LPUART_WKUP_IRQn      = 57, /*!< LPUART wakeup interrupt through EXTI line 23         */
+    LPTIM_WKUP_IRQn       = 58, /*!< LPTIMER wakeup interrupt through EXTI line 24        */
+    SAC_IRQn              = 60, /*!< SAC global Interrupt                                 */
+    MMU_IRQn              = 61, /*!< MMU global Interrupt                                 */
+    TSC_IRQn              = 62, /*!< TSC global Interrupt                                 */
+    RAMC_PERR_IRQn        = 63, /*!< RAM parity error interrupt                           */
+    TIM9_IRQn             = 64, /*!< TIM9 global interrupt                                */
+    UCDR_IRQn             = 65, /*!< UCDR error interrupt                                 */
+} IRQn_Type;
+
+#include "core_cm4.h"
+#include "system_n32g43x.h"
+#include <stdint.h>
+#include <stdbool.h>
+
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef const int32_t sc32; /*!< Read Only */
+typedef const int16_t sc16; /*!< Read Only */
+typedef const int8_t sc8;   /*!< Read Only */
+
+typedef __IO int32_t vs32;
+typedef __IO int16_t vs16;
+typedef __IO int8_t vs8;
+
+typedef __I int32_t vsc32; /*!< Read Only */
+typedef __I int16_t vsc16; /*!< Read Only */
+typedef __I int8_t vsc8;   /*!< Read Only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+typedef const uint32_t uc32; /*!< Read Only */
+typedef const uint16_t uc16; /*!< Read Only */
+typedef const uint8_t uc8;   /*!< Read Only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t vu8;
+
+typedef __I uint32_t vuc32; /*!< Read Only */
+typedef __I uint16_t vuc16; /*!< Read Only */
+typedef __I uint8_t vuc8;   /*!< Read Only */
+typedef enum
+{
+    RESET = 0,
+    SET   = !RESET
+} FlagStatus,
+    INTStatus;
+
+typedef enum
+{
+    DISABLE = 0,
+    ENABLE  = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+    ERROR   = 0,
+    SUCCESS = !ERROR
+} ErrorStatus;
+
+/* N32G43x Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
+#define HSE_Value          HSE_VALUE
+#define HSI_Value          HSI_VALUE
+
+/**
+ * @brief Analog to Digital Converter
+ */
+typedef struct
+{
+    __IO uint32_t STS;
+    __IO uint32_t CTRL1;
+    __IO uint32_t CTRL2;
+    __IO uint32_t SAMPT1;
+    __IO uint32_t SAMPT2;
+    __IO uint32_t JOFFSET1;
+    __IO uint32_t JOFFSET2;
+    __IO uint32_t JOFFSET3;
+    __IO uint32_t JOFFSET4;
+    __IO uint32_t WDGHIGH;
+    __IO uint32_t WDGLOW;
+    __IO uint32_t RSEQ1;
+    __IO uint32_t RSEQ2;
+    __IO uint32_t RSEQ3;
+    __IO uint32_t JSEQ;
+    __IO uint32_t JDAT1;
+    __IO uint32_t JDAT2;
+    __IO uint32_t JDAT3;
+    __IO uint32_t JDAT4;
+    __IO uint32_t DAT;
+    __IO uint32_t DIFSEL;
+    __IO uint32_t CALFACT;
+    __IO uint32_t CTRL3;
+    __IO uint32_t SAMPT3;
+} ADC_Module;
+
+/**
+ * @brief OPAMP
+ */
+typedef struct
+{
+    __IO uint32_t CS1;
+    __IO uint32_t RES1[3];
+    __IO uint32_t CS2;
+    __IO uint32_t RES2[3];
+    __IO uint32_t LOCK;
+} OPAMP_Module;
+
+/**
+ * @brief COMP_Single
+ */
+typedef struct
+{
+    __IO uint32_t CTRL;
+    __IO uint32_t FILC;
+    __IO uint32_t FILP;
+} COMP_SingleType;
+
+/**
+ * @brief COMP
+ */
+typedef struct
+{
+    __IO uint32_t INTEN;
+    __IO uint32_t LPCKSEL;
+    __IO uint32_t WINMODE;
+    __IO uint32_t LOCK;
+    COMP_SingleType Cmp1;
+    __IO uint32_t RES;
+    COMP_SingleType Cmp2;
+    __IO uint32_t CMP2OSEL;
+    __IO uint32_t VREFSCL;
+    __IO uint32_t TEST;
+    __IO uint32_t INTSTS;
+} COMP_Module;
+
+/**
+ * @brief AFEC
+ */
+
+typedef struct
+{
+    __IO uint32_t TRIMR0;
+    __IO uint32_t TRIMR1;
+    __IO uint32_t TRIMR2;
+    __IO uint32_t TRIMR3;
+    __IO uint32_t TRIMR4;
+    __IO uint32_t TRIMR5;
+    __IO uint32_t TRIMR6;
+      __IO uint32_t TRIMR7;
+    __IO uint32_t TRIMR8;
+   //uint32_t RESERVED0;
+    __IO uint32_t TESTR0;
+    __IO uint32_t TESTR1;
+} AFEC_Module;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+    __IO uint32_t TMI;
+    __IO uint32_t TMDT;
+    __IO uint32_t TMDL;
+    __IO uint32_t TMDH;
+} CAN_TxMailBox_Param;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+    __IO uint32_t RMI;
+    __IO uint32_t RMDT;
+    __IO uint32_t RMDL;
+    __IO uint32_t RMDH;
+} CAN_FIFOMailBox_Param;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+    __IO uint32_t FR1;
+    __IO uint32_t FR2;
+} CAN_FilterRegister_Param;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+    __IO uint32_t MCTRL;
+    __IO uint32_t MSTS;
+    __IO uint32_t TSTS;
+    __IO uint32_t RFF0;
+    __IO uint32_t RFF1;
+    __IO uint32_t INTE;
+    __IO uint32_t ESTS;
+    __IO uint32_t BTIM;
+    uint32_t RESERVED0[88];
+    CAN_TxMailBox_Param sTxMailBox[3];
+    CAN_FIFOMailBox_Param sFIFOMailBox[2];
+    uint32_t RESERVED1[12];
+    __IO uint32_t FMC;
+    __IO uint32_t FM1;
+    uint32_t RESERVED2;
+    __IO uint32_t FS1;
+    uint32_t RESERVED3;
+    __IO uint32_t FFA1;
+    uint32_t RESERVED4;
+    __IO uint32_t FA1;
+    uint32_t RESERVED5[8];
+    CAN_FilterRegister_Param sFilterRegister[14];
+} CAN_Module;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+    __IO uint32_t CRC32DAT; /*!< CRC data register */
+    __IO uint8_t CRC32IDAT; /*!< CRC independent data register*/
+    uint8_t RESERVED0;
+    uint16_t RESERVED1;
+    __IO uint32_t CRC32CTRL; /*!< CRC control register */
+    __IO uint32_t CRC16CTRL;
+    __IO uint8_t CRC16DAT;
+    uint8_t RESERVED2;
+    uint16_t RESERVED3;
+    __IO uint16_t CRC16D;
+    uint16_t RESERVED4;
+    __IO uint8_t LRC;
+    uint8_t RESERVED5;
+    uint16_t RESERVED6;
+} CRC_Module;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+    __IO uint32_t CTRL;
+    __IO uint32_t SOTTR;
+    __IO uint32_t DR12CH;
+    __IO uint32_t DL12CH;
+    __IO uint32_t DR8CH;
+    __IO uint32_t DATO;
+
+} DAC_Module;
+/**
+ * @brief USB
+ */
+
+typedef struct
+{
+    __IO uint32_t EP0;
+    __IO uint32_t EP1;
+    __IO uint32_t EP2;
+    __IO uint32_t EP3;
+    __IO uint32_t EP4;
+    __IO uint32_t EP5;
+    __IO uint32_t EP6;
+    __IO uint32_t EP7;
+    __IO uint32_t Reserve20h;
+    __IO uint32_t Reserve24h;
+    __IO uint32_t Reserve28h;
+    __IO uint32_t Reserve2Ch;
+    __IO uint32_t Reserve30h;
+    __IO uint32_t Reserve34h;
+    __IO uint32_t Reserve38h;
+    __IO uint32_t Reserve3Ch;
+    __IO uint32_t CTRL;
+    __IO uint32_t STS;
+    __IO uint32_t FN;
+    __IO uint32_t ADDR;
+    __IO uint32_t BUFTAB;
+} USB_Module;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+    __IO uint32_t ID;
+    __IO uint32_t CTRL;
+} DBG_Module;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+    __IO uint32_t CHCFG;
+    __IO uint32_t TXNUM;
+    __IO uint32_t PADDR;
+    __IO uint32_t MADDR;
+    __IO uint32_t CHSEL;
+
+} DMA_ChannelType;
+
+typedef struct
+{
+    __IO uint32_t INTSTS;
+    __IO uint32_t INTCLR;
+    __IO DMA_ChannelType DMA_Channel[8];
+} DMA_Module;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+    __IO uint32_t IMASK;    /*offset 0x00*/
+    __IO uint32_t EMASK;    /*offset 0x04*/
+    __IO uint32_t RT_CFG;   /*offset 0x08*/
+    __IO uint32_t FT_CFG;   /*offset 0x0C*/
+    __IO uint32_t SWIE;     /*offset 0x10*/
+    __IO uint32_t PEND;     /*offset 0x14*/
+    __IO uint32_t TS_SEL;   /*offset 0x18*/
+} EXTI_Module;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+    __IO uint32_t AC;
+    __IO uint32_t KEYR;
+    __IO uint32_t OPTKEY;
+    __IO uint32_t STS;
+    __IO uint32_t CTRL;
+    __IO uint32_t ADD;
+    __IO uint32_t OB2;
+    __IO uint32_t OB;
+    __IO uint32_t WRP;
+    __IO uint32_t RESERVED0;
+    __IO uint32_t RESERVED1;
+    __IO uint32_t RESERVED2;
+    __IO uint32_t CAHR;
+} FLASH_Module;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+    __IO uint32_t USER_RDP;
+    __IO uint32_t Data1_Data0;
+    __IO uint32_t WRP1_WRP0;
+    __IO uint32_t WRP3_WRP2;
+    __IO uint32_t USER2_RDP2;
+} OB_Module;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+    __IO uint32_t PMODE;  /*offset 0x00*/
+    __IO uint32_t POTYPE; /*offset 0x04*/
+      __IO uint32_t SR;     /*offset 0x08*/
+    __IO uint32_t PUPD;  /*offset 0x0C*/
+    __IO uint32_t PID;   /*offset 0x10*/
+    __IO uint32_t POD;   /*offset 0x14*/
+    __IO uint32_t PBSC;  /*offset 0x18*/
+    __IO uint32_t PLOCK; /*offset 0x1C*/
+    __IO uint32_t AFL;   /*offset 0x20*/
+    __IO uint32_t AFH;   /*offset 0x24*/
+    __IO uint32_t PBC;   /*offset 0x28*/
+    __IO uint32_t DS;    /*offset 0x2C*/
+
+} GPIO_Module;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+    __IO uint32_t RMP_CFG;
+    __IO uint32_t EXTI_CFG[4];
+} AFIO_Module;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+    __IO uint16_t CTRL1;
+    uint16_t RESERVED0;
+    __IO uint16_t CTRL2;
+    uint16_t RESERVED1;
+    __IO uint16_t OADDR1;
+    uint16_t RESERVED2;
+    __IO uint16_t OADDR2;
+    uint16_t RESERVED3;
+    __IO uint16_t DAT;
+    uint16_t RESERVED4;
+    __IO uint16_t STS1;
+    uint16_t RESERVED5;
+    __IO uint16_t STS2;
+    uint16_t RESERVED6;
+    __IO uint16_t CLKCTRL;
+    uint16_t RESERVED7;
+    __IO uint16_t TMRISE;
+    uint16_t RESERVED8;
+} I2C_Module;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+    __IO uint32_t KEY;
+    __IO uint32_t PREDIV; /*!< IWDG PREDIV */
+    __IO uint32_t RELV;
+    __IO uint32_t STS;
+} IWDG_Module;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+    __IO uint32_t CTRL1;
+    __IO uint32_t CTRL2;
+    __IO uint32_t CTRL3;
+      __IO uint32_t STS1;
+      __IO uint32_t STS2;
+      __IO uint32_t STSCLR;
+} PWR_Module;
+
+/**
+ * @brief Low-Power Timer
+ */
+typedef struct
+{
+    __IO uint32_t INTSTS;
+  __IO uint32_t INTCLR;
+  __IO uint32_t INTEN;
+  __IO uint32_t CFG;
+    __IO uint32_t CTRL;
+  __IO uint32_t COMPx;
+  __IO uint32_t ARR;
+  __IO uint32_t CNT;
+
+} LPTIM_Module;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+    __IO uint32_t CTRL;
+    __IO uint32_t CFG;
+    __IO uint32_t CLKINT;
+    __IO uint32_t APB2PRST;
+    __IO uint32_t APB1PRST;
+    __IO uint32_t AHBPCLKEN;
+    __IO uint32_t APB2PCLKEN;
+    __IO uint32_t APB1PCLKEN;
+    __IO uint32_t LDCTRL;
+    __IO uint32_t CTRLSTS;
+    __IO uint32_t AHBPRST;
+    __IO uint32_t CFG2;
+    __IO uint32_t CFG3;
+    __IO uint32_t RDCTRL;
+    __IO uint32_t Reserve0;
+    __IO uint32_t Reserve1;
+    __IO uint32_t PLLHSIPRE;
+    __IO uint32_t SRAM_CTRLSTS;
+} RCC_Module;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+    __IO uint32_t TSH;         /*!< RTC time register,                                         Address offset: 0x00 */
+    __IO uint32_t DATE;        /*!< RTC date register,                                         Address offset: 0x04 */
+    __IO uint32_t CTRL;        /*!< RTC control register,                                      Address offset: 0x08 */
+    __IO uint32_t INITSTS;     /*!< RTC initialization and status register,                    Address offset: 0x0C */
+    __IO uint32_t PRE;         /*!< RTC prescaler register,                                    Address offset: 0x10 */
+    __IO uint32_t WKUPT;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+    uint32_t reserved0;        /*!< Reserved  */
+    __IO uint32_t ALARMA;      /*!< RTC alarm A register,                                      Address offset: 0x1C */
+    __IO uint32_t ALARMB;      /*!< RTC alarm B register,                                      Address offset: 0x20 */
+    __IO uint32_t WRP;         /*!< RTC write protection register,                             Address offset: 0x24 */
+    __IO uint32_t SUBS;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+    __IO uint32_t SCTRL;       /*!< RTC shift control register,                                Address offset: 0x2C */
+    __IO uint32_t TST;         /*!< RTC time stamp time register,                              Address offset: 0x30 */
+    __IO uint32_t TSD;         /*!< RTC time stamp date register,                              Address offset: 0x34 */
+    __IO uint32_t TSSS;        /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+    __IO uint32_t CALIB;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+    __IO uint32_t TMPCFG;     /*!< RTC tamper configuration register,                          Address offset: 0x40 */
+    __IO uint32_t ALRMASS;     /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+    __IO uint32_t ALRMBSS;     /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+    __IO uint32_t OPT;         /*!< RTC option register,                                       Address offset: 0x4C */
+    __IO uint32_t BKP1R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */
+    __IO uint32_t BKP2R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */
+    __IO uint32_t BKP3R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */
+    __IO uint32_t BKP4R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */
+    __IO uint32_t BKP5R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */
+    __IO uint32_t BKP6R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */
+    __IO uint32_t BKP7R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */
+    __IO uint32_t BKP8R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */
+    __IO uint32_t BKP9R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */
+    __IO uint32_t BKP10R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+    __IO uint32_t BKP11R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */
+    __IO uint32_t BKP12R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */
+    __IO uint32_t BKP13R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */
+    __IO uint32_t BKP14R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */
+    __IO uint32_t BKP15R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */
+    __IO uint32_t BKP16R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */
+    __IO uint32_t BKP17R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */
+    __IO uint32_t BKP18R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */
+    __IO uint32_t BKP19R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */
+    __IO uint32_t BKP20R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */
+    __IO uint32_t TSCWKUPCTRL; /*!< TSC register 1,                                            Address offset: 0xA0 */
+    __IO uint32_t TSCWKUPCNT;  /*!< TSC register 2,                                            Address offset: 0xA4 */
+} RTC_Module;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+    __IO uint16_t CTRL1;
+    uint16_t RESERVED0;
+    __IO uint16_t CTRL2;
+    uint16_t RESERVED1;
+    __IO uint16_t STS;
+    uint16_t RESERVED2;
+    __IO uint16_t DAT;
+    uint16_t RESERVED3;
+    __IO uint16_t CRCPOLY;
+    uint16_t RESERVED4;
+    __IO uint16_t CRCRDAT;
+    uint16_t RESERVED5;
+    __IO uint16_t CRCTDAT;
+    uint16_t RESERVED6;
+    __IO uint16_t I2SCFG;
+    uint16_t RESERVED7;
+    __IO uint16_t I2SPREDIV;
+    uint16_t RESERVED8;
+} SPI_Module;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+    __IO uint32_t CTRL1;
+    __IO uint32_t CTRL2;
+    __IO uint16_t SMCTRL;
+    uint16_t RESERVED1;
+    __IO uint16_t DINTEN;
+    uint16_t RESERVED2;
+    __IO uint32_t STS;
+    __IO uint16_t EVTGEN;
+    uint16_t RESERVED3;
+    __IO uint16_t CCMOD1;
+    uint16_t RESERVED4;
+    __IO uint16_t CCMOD2;
+    uint16_t RESERVED5;
+    __IO uint32_t CCEN;
+    __IO uint16_t CNT;
+    uint16_t RESERVED6;
+    __IO uint16_t PSC;
+    uint16_t RESERVED7;
+    __IO uint16_t AR;
+    uint16_t RESERVED8;
+    __IO uint16_t REPCNT;
+    uint16_t RESERVED9;
+    __IO uint16_t CCDAT1;
+    uint16_t RESERVED10;
+    __IO uint16_t CCDAT2;
+    uint16_t RESERVED11;
+    __IO uint16_t CCDAT3;
+    uint16_t RESERVED12;
+    __IO uint16_t CCDAT4;
+    uint16_t RESERVED13;
+    __IO uint16_t BKDT;
+    uint16_t RESERVED14;
+    __IO uint16_t DCTRL;
+    uint16_t RESERVED15;
+    __IO uint16_t DADDR;
+    uint16_t RESERVED16;
+    uint32_t RESERVED17;
+    __IO uint16_t CCMOD3;
+    uint16_t RESERVED18;
+    __IO uint16_t CCDAT5;
+    uint16_t RESERVED19;
+    __IO uint16_t CCDAT6;
+    uint16_t RESERVED20;
+} TIM_Module;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+    __IO uint16_t STS;
+    uint16_t RESERVED0;
+    __IO uint16_t DAT;
+    uint16_t RESERVED1;
+    __IO uint16_t BRCF;
+    uint16_t RESERVED2;
+    __IO uint16_t CTRL1;
+    uint16_t RESERVED3;
+    __IO uint16_t CTRL2;
+    uint16_t RESERVED4;
+    __IO uint16_t CTRL3;
+    uint16_t RESERVED5;
+    __IO uint16_t GTP;
+    uint16_t RESERVED6;
+} USART_Module;
+
+/**
+ * @brief Low-power Universal Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+   __IO uint16_t STS;
+   uint16_t RESERVED0;
+   __IO uint8_t INTEN;
+   uint8_t RESERVED1;
+   uint16_t RESERVED2;
+   __IO uint16_t CTRL;
+   uint16_t RESERVED3;
+   __IO uint16_t BRCFG1;
+   uint16_t RESERVED4;
+   __IO uint8_t DAT;
+   uint8_t RESERVED5;
+   uint16_t RESERVED6;
+   __IO uint8_t BRCFG2;
+   uint8_t RESERVED7;
+   uint16_t RESERVED8;
+   __IO uint32_t WUDAT;
+} LPUART_Module;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+    __IO uint32_t CTRL;
+    __IO uint32_t CFG;
+    __IO uint32_t STS;
+} WWDG_Module;
+
+/**
+ * @brief Touch Sensor Controller
+ */
+typedef struct
+{
+    __IO uint32_t CTRL;
+    __IO uint32_t CHNEN;
+    __IO uint32_t STS;
+    __IO uint32_t RESERVED;
+    __IO uint32_t ANA_CTRL;
+    __IO uint32_t ANA_SEL;
+    __IO uint32_t RESR[3];
+//    __IO uint32_t RESR0;
+//    __IO uint32_t RESR1;
+//    __IO uint32_t RESR2;
+    __IO uint32_t THRHD[24];
+//    __IO uint32_t THRHD0;
+//    __IO uint32_t THRHD1;
+//    __IO uint32_t THRHD2;
+//    __IO uint32_t THRHD3;
+//    __IO uint32_t THRHD4;
+//    __IO uint32_t THRHD5;
+//    __IO uint32_t THRHD6;
+//    __IO uint32_t THRHD7;
+//    __IO uint32_t THRHD8;
+//    __IO uint32_t THRHD9;
+//    __IO uint32_t THRHD10;
+//    __IO uint32_t THRHD11;
+//    __IO uint32_t THRHD12;
+//    __IO uint32_t THRHD13;
+//    __IO uint32_t THRHD14;
+//    __IO uint32_t THRHD15;
+//    __IO uint32_t THRHD16;
+//    __IO uint32_t THRHD17;
+//    __IO uint32_t THRHD18;
+//    __IO uint32_t THRHD19;
+//    __IO uint32_t THRHD20;
+//    __IO uint32_t THRHD21;
+//    __IO uint32_t THRHD22;
+//    __IO uint32_t THRHD23;
+
+} TSC_Module;
+
+#define FLASH_BASE  ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE   ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE   ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define UCID_BASE           ((uint32_t)0x1FFFF7C0) /*!< UCID Address : 0x1FFF_F7C0 */
+#define UCID_LENGTH         ((uint32_t)0x10)       /*!< UCID Length  : 16Bytes */
+#define UID_BASE            ((uint32_t)0x1FFFF7F0) /*!< UID Address  : 0x1FFF_F7F0 */
+#define UID_LENGTH          ((uint32_t)0x0C)       /*!< UID Length   : 12Bytes */
+#define DBGMCU_ID_BASE      ((uint32_t)0x1FFFF7FC) /*!< DBGMCU_ID Address */
+#define DBGMCU_ID_LENGTH    ((uint8_t)0x04)        /*!< DBGMCU_ID Length : 4 Bytes */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE (PERIPH_BASE)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE  (PERIPH_BASE + 0x18000)
+
+/* APB1 */
+#define TIM2_BASE          (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE          (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE          (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE          (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE          (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE          (APB1PERIPH_BASE + 0x1400)
+#define AFEC_BASE          (APB1PERIPH_BASE + 0x1800)
+#define OPAMP_BASE         (APB1PERIPH_BASE + 0x2000)
+#define COMP_BASE          (APB1PERIPH_BASE + 0x2400)
+#define RTC_BASE           (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE          (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE          (APB1PERIPH_BASE + 0x3000)
+#define TSC_BASE           (APB1PERIPH_BASE + 0x3400)
+#define TIM9_BASE          (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE        (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE        (APB1PERIPH_BASE + 0x4800)
+#define LPTIM_BASE         (APB1PERIPH_BASE + 0x4C00)
+#define LPUART_BASE        (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE          (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE          (APB1PERIPH_BASE + 0x5800)
+#define USB_BASE           (APB1PERIPH_BASE + 0x5C00)
+#define USB_SRAM_BASE      (APB1PERIPH_BASE + 0x6000)
+#define CAN_BASE           (APB1PERIPH_BASE + 0x6400)
+#define PWR_BASE           (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE           (APB1PERIPH_BASE + 0x7400)
+
+/* APB2 */
+#define AFIO_BASE          (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE          (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE         (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE         (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE         (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE         (APB2PERIPH_BASE + 0x1400)
+#define TIM1_BASE          (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE          (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE          (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE        (APB2PERIPH_BASE + 0x3800)
+#define SPI2_BASE          (APB2PERIPH_BASE + 0x3C00)
+#define UART4_BASE         (APB2PERIPH_BASE + 0x5000)
+#define UART5_BASE         (APB2PERIPH_BASE + 0x5400)
+
+/* AHB */
+#define DMA_BASE           (AHBPERIPH_BASE + 0x8000)
+#define DMA_CH1_BASE       (AHBPERIPH_BASE + 0x8008)
+#define DMA_CH2_BASE       (AHBPERIPH_BASE + 0x801C)
+#define DMA_CH3_BASE       (AHBPERIPH_BASE + 0x8030)
+#define DMA_CH4_BASE       (AHBPERIPH_BASE + 0x8044)
+#define DMA_CH5_BASE       (AHBPERIPH_BASE + 0x8058)
+#define DMA_CH6_BASE       (AHBPERIPH_BASE + 0x806C)
+#define DMA_CH7_BASE       (AHBPERIPH_BASE + 0x8080)
+#define DMA_CH8_BASE       (AHBPERIPH_BASE + 0x8094)
+#define ADC_BASE           (AHBPERIPH_BASE + 0x8800)
+#define RCC_BASE           (AHBPERIPH_BASE + 0x9000)
+#define FLASH_R_BASE       (AHBPERIPH_BASE + 0xA000) /*!< Flash registers base address */
+#define OB_BASE            ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */
+#define CRC_BASE           (AHBPERIPH_BASE + 0xB000)
+#define SAC_BASE           (AHBPERIPH_BASE + 0xC000)
+#define SAC_SRAM_BASE      (AHBPERIPH_BASE + 0xC400)
+#define MMU_BASE           (AHBPERIPH_BASE + 0xCC00)
+
+#define DBG_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+#define TIM2        ((TIM_Module*)TIM2_BASE)
+#define TIM3        ((TIM_Module*)TIM3_BASE)
+#define TIM4        ((TIM_Module*)TIM4_BASE)
+#define TIM5        ((TIM_Module*)TIM5_BASE)
+#define TIM6        ((TIM_Module*)TIM6_BASE)
+#define TIM7        ((TIM_Module*)TIM7_BASE)
+#define AFEC        ((AFEC_Module*)AFEC_BASE)
+#define OPAMP       ((OPAMP_Module*)OPAMP_BASE)
+#define COMP        ((COMP_Module*)COMP_BASE)
+#define RTC         ((RTC_Module*)RTC_BASE)
+#define WWDG        ((WWDG_Module*)WWDG_BASE)
+#define IWDG        ((IWDG_Module*)IWDG_BASE)
+#define TSC         ((TSC_Module*)TSC_BASE)
+#define TIM9        ((TIM_Module*)TIM9_BASE)
+#define USART2      ((USART_Module*)USART2_BASE)
+#define USART3      ((USART_Module*)USART3_BASE)
+#define LPTIM       ((LPTIM_Module*)LPTIM_BASE)
+#define LPUART      ((LPUART_Module*)LPUART_BASE)
+#define I2C1        ((I2C_Module*)I2C1_BASE)
+#define I2C2        ((I2C_Module*)I2C2_BASE)
+#define USB         ((USB_Module*)USB_BASE)
+#define CAN         ((CAN_Module*)CAN_BASE)
+#define PWR         ((PWR_Module*)PWR_BASE)
+#define DAC         ((DAC_Module*)DAC_BASE)
+#define AFIO        ((AFIO_Module*)AFIO_BASE)
+#define EXTI        ((EXTI_Module*)EXTI_BASE)
+#define GPIOA       ((GPIO_Module*)GPIOA_BASE)
+#define GPIOB       ((GPIO_Module*)GPIOB_BASE)
+#define GPIOC       ((GPIO_Module*)GPIOC_BASE)
+#define GPIOD       ((GPIO_Module*)GPIOD_BASE)
+#define TIM1        ((TIM_Module*)TIM1_BASE)
+#define SPI1        ((SPI_Module*)SPI1_BASE)
+#define TIM8        ((TIM_Module*)TIM8_BASE)
+#define USART1      ((USART_Module*)USART1_BASE)
+#define SPI2        ((SPI_Module*)SPI2_BASE)
+#define UART4       ((USART_Module*)UART4_BASE)
+#define UART5       ((USART_Module*)UART5_BASE)
+#define DMA         ((DMA_Module*)DMA_BASE)
+#define DMA_CH1     ((DMA_ChannelType*)DMA_CH1_BASE)
+#define DMA_CH2     ((DMA_ChannelType*)DMA_CH2_BASE)
+#define DMA_CH3     ((DMA_ChannelType*)DMA_CH3_BASE)
+#define DMA_CH4     ((DMA_ChannelType*)DMA_CH4_BASE)
+#define DMA_CH5     ((DMA_ChannelType*)DMA_CH5_BASE)
+#define DMA_CH6     ((DMA_ChannelType*)DMA_CH6_BASE)
+#define DMA_CH7     ((DMA_ChannelType*)DMA_CH7_BASE)
+#define DMA_CH8     ((DMA_ChannelType*)DMA_CH8_BASE)
+#define ADC         ((ADC_Module*)ADC_BASE)
+#define RCC         ((RCC_Module*)RCC_BASE)
+#define FLASH       ((FLASH_Module*)FLASH_R_BASE)
+#define OBT         ((OB_Module*)OB_BASE)
+#define CRC         ((CRC_Module*)CRC_BASE)
+
+#define DBG ((DBG_Module*)DBG_BASE)
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_CRC32DAT register  *********************/
+#define CRC32_DAT_DAT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_CRC32IDAT register  ********************/
+#define CRC32_IDAT_IDAT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CRC32CTRL register  ********************/
+#define CRC32_CTRL_RESET ((uint8_t)0x01) /*!< RESET bit */
+
+/********************  Bit definition for CRC16_CR register  ********************/
+#define CRC16_CTRL_LITTLE ((uint8_t)0x02)
+#define CRC16_CTRL_BIG    ((uint8_t)0xFD)
+
+#define CRC16_CTRL_RESET    ((uint8_t)0x04)
+#define CRC16_CTRL_NO_RESET ((uint8_t)0xFB)
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CTRL1 register  ********************/
+#define PWR_CTRL1_LPMSEL                       ((uint16_t)0x0007)     /*!< no low power mode entered */
+#define PWR_CTRL1_STOP2                        ((uint16_t)0x0002)     /*!< stop2 mode */
+#define PWR_CTRL1_STANDBY                      ((uint16_t)0x0003)     /*!< standby mode */
+
+
+#define PWR_CTRL1_DRBP                         ((uint16_t)0x0100)     /*!< Access to RTC and Backup registers enabled */
+
+#define PWR_CTRL1_MRSEL                        ((uint16_t)0x0600)     /*!< vddd Range Mask */
+#define PWR_CTRL1_MRSEL_bit0                   ((uint16_t)0x0200)     /*!< vddd Range MRSEL bit0 */
+#define PWR_CTRL1_MRSEL_bit1                   ((uint16_t)0x0400)     /*!< vddd Range MRSEL bit1 */
+#define PWR_CTRL1_MRSEL2                       ((uint16_t)0x0400)     /*!< vddd Range2=1.0 V */
+#define PWR_CTRL1_MRSEL1                       ((uint16_t)0x0600)     /*!< vddd Range1=1.1 V */
+#define PWR_CTRL1_LPREN                        ((uint16_t)0x4000)     /*!< When this bit is set, MR is turned off and LPR is used to run the main power domain. */
+#define PWR_CTRL1_MRSELMASK                    ((uint16_t)0x0600)     /*!< MR voltage mask */
+/********************  Bit definition for PWR_CTRL2 register  ********************/
+#define PWR_CTRL2_PVDEN                        ((uint16_t)0x0001)     /*!< Power voltage detector enable */
+#define PWR_CTRL2_PLS1                         ((uint16_t)0x0000)     /*!< voltage threshold around 2.1 V */
+#define PWR_CTRL2_PLS2                         ((uint16_t)0x0002)     /*!< voltage threshold around 2.25 V */
+#define PWR_CTRL2_PLS3                         ((uint16_t)0x0004)     /*!< voltage threshold around 2.4 V */
+#define PWR_CTRL2_PLS4                         ((uint16_t)0x0006)     /*!< voltage threshold around 2.55 V */
+#define PWR_CTRL2_PLS5                         ((uint16_t)0x0008)     /*!< voltage threshold around 2.7 V */
+#define PWR_CTRL2_PLS6                         ((uint16_t)0x000A)     /*!< voltage threshold around 2.85 V */
+#define PWR_CTRL2_PLS7                         ((uint16_t)0x000C)     /*!< voltage threshold around 2.95 V */
+#define PWR_CTRL2_PLS8                         ((uint16_t)0x000E)     /*!< external input analog voltage PVD_IN (compared internally to VREFINT) */
+
+#define PWR_CTRL2_PVDFLTEN                     ((uint16_t)0x0010)     /*!< Power voltage detector filter enable */
+
+
+/********************  Bit definition for PWR_CTRL3 register  ********************/
+#define PWR_CTRL3_WKUP0EN                      ((uint16_t)0x0001)     /*!< When this bit is set, WKUP0 pin is enable and triggers a wakeup from standby mode. */
+#define PWR_CTRL3_WKUP1EN                      ((uint16_t)0x0002)     /*!< When this bit is set, WKUP1 pin is enable and triggers a wakeup from standby mode. */
+#define PWR_CTRL3_WKUP2EN                      ((uint16_t)0x0004)     /*!< When this bit is set, WKUP2 pin is enable and triggers a wakeup from standby mode. */
+#define PWR_CTRL3_WKUP0PS                      ((uint16_t)0x0010)     /*!< falling edge wake up */
+#define PWR_CTRL3_WKUP1PS                      ((uint16_t)0x0020)     /*!< falling edge wake up */
+#define PWR_CTRL3_WKUP2PS                      ((uint16_t)0x0040)     /*!< falling edge wake up */
+#define PWR_CTRL3_BGDTLPR                      ((uint16_t)0x0100)     /*!< BANDGAP/BG_Buffer/IBIAS duty on in LPRUN */
+#define PWR_CTRL3_BGDTSTP2                     ((uint16_t)0x0200)     /*!< BANDGAP/BG_Buffer/IBIAS duty on in stop2 */
+#define PWR_CTRL3_BGDTSTBY                     ((uint16_t)0x0400)     /*!< BANDGAP/BG_Buffer/IBIAS duty on in standby */
+#define PWR_CTRL3_RAM1RET                      ((uint16_t)0x1000)     /*!< SRAM1 is powered by the LPR in stop2 mode */
+#define PWR_CTRL3_RAM2RET                      ((uint16_t)0x2000)     /*!< SRAM2 is powered by the LPR in standby mode */
+#define PWR_CTRL3_IWKUPLEN                      ((uint16_t)0x4000)    /*!< internal wakeup line enable */
+
+#define PWR_CTRL3_PBDTLPR                      ((uint32_t)0x10000)     /*!< PVDBOR duty on in LP RUN */
+#define PWR_CTRL3_PBDTSTP2                     ((uint32_t)0x20000)     /*!< PVDBOR duty on in STOP2 */
+#define PWR_CTRL3_PBDTSTBY                     ((uint32_t)0x40000)     /*!< PVDBOR is iduty on standby */
+#define PWR_CTRL3_PSTSTBY                      ((uint32_t)0x100000)     /*!< PAD in HI-Z state  */
+#define PWR_CTRL3_PSTSTP2                      ((uint32_t)0x200000)     /*!< PAD in HI-Z state  */
+
+#define PWR_CTRL3_RAMRETMASK                       ((uint16_t)0x3000)     /*!< SRAM1 and SRAM2 ENABLE */
+#define PWR_CTRL1_LPMSELMASK                       ((uint16_t)0x0007)     /*!< Low power mode selection */
+#define PWR_CTRL2_PLSMASK                          ((uint16_t)0x000E)     /*!< Low power mode selection */
+/********************  Bit definition for PWR_STS1 register  ********************/
+#define PWR_STS1_WKUPF0                         ((uint16_t)0x0001)     /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP1. */
+#define PWR_STS1_WKUPF1                         ((uint16_t)0x0002)     /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP2. */
+#define PWR_STS1_WKUPF2                         ((uint16_t)0x0004)     /*!< This bit is set when a wakeup event is detected on wakeup pin, WKUP3. */
+#define PWR_STS1_STBYF                          ((uint16_t)0x0100)     /*!< the device entered the standby mode */
+#define PWR_STS1_IWKUPF                         ((uint16_t)0x8000)     /*!< This bit is set when a wakeup is detected on the internal wakeup line. */
+
+/********************  Bit definition for PWR_STS2 register  ********************/
+#define PWR_STS2_LPRUNF                       ((uint16_t)0x0001)     /*!< MCU is in low power run mode */
+#define PWR_STS2_MRF                          ((uint16_t)0x0002)     /*!< voltage scaling ready */
+#define PWR_STS2_PVDO                         ((uint16_t)0x0004)     /*!< Power voltage detector output */
+
+/********************  Bit definition for PWR_STSCLR register  ********************/
+#define PWR_STSCLR_CLRWKUP0                        ((uint16_t)0x0001)     /*!< Setting this bit clears the WKPF1 flag in the PWR_STS1 register */
+#define PWR_STSCLR_CLRWKUP1                        ((uint16_t)0x0002)     /*!< Setting this bit clears the WKPF2 flag in the PWR_STS1 register */
+#define PWR_STSCLR_CLRWKUP2                        ((uint16_t)0x0004)     /*!< Setting this bit clears the WKPF3 flag in the PWR_STS1 register */
+#define PWR_STSCLR_CLRSTBY                         ((uint16_t)0x0100)     /*!< Setting this bit clears the SBF flag in the PWR_STS1 register */
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CTRL register  ********************/
+#define RCC_CTRL_HSIEN   ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CTRL_HSIRDF  ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CTRL_HSITRIM ((uint32_t)0x0000007C) /*!< Internal High Speed clock trimming */
+#define RCC_CTRL_HSICAL  ((uint32_t)0x0000FF80) /*!< Internal High Speed clock Calibration */
+#define RCC_CTRL_HSEEN   ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CTRL_HSERDF  ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CTRL_HSEBP   ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CTRL_CLKSSEN ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CTRL_PLLEN   ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CTRL_PLLRDF  ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFG register  *******************/
+/*!< SW configuration */
+#define RCC_CFG_SCLKSW   ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFG_SCLKSW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFG_SCLKSW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFG_SCLKSW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
+#define RCC_CFG_SCLKSW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
+#define RCC_CFG_SCLKSW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
+#define RCC_CFG_SCLKSW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFG_SCLKSTS   ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFG_SCLKSTS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFG_SCLKSTS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFG_SCLKSTS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
+#define RCC_CFG_SCLKSTS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
+
+/*!< AHBPRES configuration */
+#define RCC_CFG_AHBPRES   ((uint32_t)0x000000F0) /*!< AHBPRES[3:0] bits (AHB prescaler) */
+#define RCC_CFG_AHBPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFG_AHBPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFG_AHBPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFG_AHBPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFG_AHBPRES_DIV1   ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFG_AHBPRES_DIV2   ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFG_AHBPRES_DIV4   ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFG_AHBPRES_DIV8   ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFG_AHBPRES_DIV16  ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFG_AHBPRES_DIV64  ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFG_AHBPRES_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFG_AHBPRES_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFG_AHBPRES_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< APB1PRES configuration */
+#define RCC_CFG_APB1PRES   ((uint32_t)0x00000700) /*!< APB1PRES[2:0] bits (APB1 prescaler) */
+#define RCC_CFG_APB1PRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFG_APB1PRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFG_APB1PRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFG_APB1PRES_DIV1  ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFG_APB1PRES_DIV2  ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFG_APB1PRES_DIV4  ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFG_APB1PRES_DIV8  ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFG_APB1PRES_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< APB2PRES configuration */
+#define RCC_CFG_APB2PRES   ((uint32_t)0x00003800) /*!< APB2PRES[2:0] bits (APB2 prescaler) */
+#define RCC_CFG_APB2PRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFG_APB2PRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFG_APB2PRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFG_APB2PRES_DIV1  ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFG_APB2PRES_DIV2  ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFG_APB2PRES_DIV4  ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFG_APB2PRES_DIV8  ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFG_APB2PRES_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< PLLSRC configuration */
+#define RCC_CFG_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFG_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as PLL entry clock source */
+#define RCC_CFG_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
+
+/*!< PLLXTPRE configuration */
+#define RCC_CFG_PLLHSEPRES ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+#define RCC_CFG_PLLHSEPRES_HSE      ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFG_PLLHSEPRES_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFG_PLLMULFCT   ((uint32_t)0x083C0000) /*!< PLLMUL[4:0] bits (PLL multiplication factor) */
+#define RCC_CFG_PLLMULFCT_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFG_PLLMULFCT_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFG_PLLMULFCT_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFG_PLLMULFCT_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+#define RCC_CFG_PLLMULFCT_4 ((uint32_t)0x08000000) /*!< Bit 4 */
+
+#define RCC_CFG_PLLMULFCT2          ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFG_PLLMULFCT3          ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFG_PLLMULFCT4          ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFG_PLLMULFCT5          ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFG_PLLMULFCT6          ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFG_PLLMULFCT7          ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFG_PLLMULFCT8          ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFG_PLLMULFCT9          ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFG_PLLMULFCT10         ((uint32_t)0x00200000) /*!< PLL input clock*10 */
+#define RCC_CFG_PLLMULFCT11         ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFG_PLLMULFCT12         ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFG_PLLMULFCT13         ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFG_PLLMULFCT14         ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFG_PLLMULFCT15         ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFG_PLLMULFCT16         ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+#define RCC_CFG_PLLMULFCT16N        ((uint32_t)0x003C0000) /*!< PLL input clock*16 */
+#define RCC_CFG_PLLMULFCT17         ((uint32_t)0x08000000) /*!< PLL input clock*17 */
+#define RCC_CFG_PLLMULFCT18         ((uint32_t)0x08040000) /*!< PLL input clock*18 */
+#define RCC_CFG_PLLMULFCT19         ((uint32_t)0x08080000) /*!< PLL input clock*19 */
+#define RCC_CFG_PLLMULFCT20         ((uint32_t)0x080C0000) /*!< PLL input clock*20 */
+#define RCC_CFG_PLLMULFCT21         ((uint32_t)0x08100000) /*!< PLL input clock*21 */
+#define RCC_CFG_PLLMULFCT22         ((uint32_t)0x08140000) /*!< PLL input clock*22 */
+#define RCC_CFG_PLLMULFCT23         ((uint32_t)0x08180000) /*!< PLL input clock*23 */
+#define RCC_CFG_PLLMULFCT24         ((uint32_t)0x081C0000) /*!< PLL input clock*24 */
+#define RCC_CFG_PLLMULFCT25         ((uint32_t)0x08200000) /*!< PLL input clock*25 */
+#define RCC_CFG_PLLMULFCT26         ((uint32_t)0x08240000) /*!< PLL input clock*26 */
+#define RCC_CFG_PLLMULFCT27         ((uint32_t)0x08280000) /*!< PLL input clock*27 */
+#define RCC_CFG_PLLMULFCT28         ((uint32_t)0x082C0000) /*!< PLL input clock*28 */
+#define RCC_CFG_PLLMULFCT29         ((uint32_t)0x08300000) /*!< PLL input clock*29 */
+#define RCC_CFG_PLLMULFCT30         ((uint32_t)0x08340000) /*!< PLL input clock*30 */
+#define RCC_CFG_PLLMULFCT31         ((uint32_t)0x08380000) /*!< PLL input clock*31 */
+#define RCC_CFG_PLLMULFCT32         ((uint32_t)0x083C0000) /*!< PLL input clock*32 */
+
+/*!< USBPRES configuration */
+#define RCC_CFG_USBPRES   ((uint32_t)0x00C00000) /*!< USB Device prescaler */
+#define RCC_CFG_USBPRES_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define RCC_CFG_USBPRES_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define RCC_CFG_USBPRES_PLLDIV1_5 ((uint32_t)0x00000000) /*!< PLL clock is divided by 1.5 */
+#define RCC_CFG_USBPRES_PLLDIV1   ((uint32_t)0x00400000) /*!< PLL clock is not divided */
+#define RCC_CFG_USBPRES_PLLDIV2   ((uint32_t)0x00800000) /*!< PLL clock is divided by 2 */
+#define RCC_CFG_USBPRES_PLLDIV3   ((uint32_t)0x00C00000) /*!< PLL clock is divided by 3 */
+
+/*!< MCO configuration */
+#define RCC_CFG_MCO   ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFG_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFG_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFG_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define RCC_CFG_MCO_NOCLK  ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFG_MCO_LSI    ((uint32_t)0x01000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFG_MCO_LSE    ((uint32_t)0x02000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFG_MCO_MSI    ((uint32_t)0x03000000) /*!< MSI clock selected as MCO source */
+#define RCC_CFG_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFG_MCO_HSI    ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFG_MCO_HSE    ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source  */
+#define RCC_CFG_MCO_PLL    ((uint32_t)0x07000000) /*!< PLL clock selected as MCO source */
+
+/*!< MCOPRE configuration */
+#define RCC_CFG_MCOPRES   ((uint32_t)0xF0000000) /*!< MCOPRE[3:0] bits ( PLL prescaler set and cleared by
+                                                      software to generate MCOPRE clock.) */
+#define RCC_CFG_MCOPRES_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define RCC_CFG_MCOPRES_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+#define RCC_CFG_MCOPRES_2 ((uint32_t)0x40000000) /*!< Bit 2 */
+#define RCC_CFG_MCOPRES_3 ((uint32_t)0x80000000) /*!< Bit 3 */
+
+#define RCC_CFG_MCOPRES_PLLDIV1  ((uint32_t)0x00000000) /*!< PLL clock is not divided */
+#define RCC_CFG_MCOPRES_PLLDIV2  ((uint32_t)0x10000000) /*!< PLL clock is divided by 2 */
+#define RCC_CFG_MCOPRES_PLLDIV3  ((uint32_t)0x20000000) /*!< PLL clock is divided by 3 */
+#define RCC_CFG_MCOPRES_PLLDIV4  ((uint32_t)0x30000000) /*!< PLL clock is divided by 4 */
+#define RCC_CFG_MCOPRES_PLLDIV5  ((uint32_t)0x40000000) /*!< PLL clock is divided by 5 */
+#define RCC_CFG_MCOPRES_PLLDIV6  ((uint32_t)0x50000000) /*!< PLL clock is divided by 6 */
+#define RCC_CFG_MCOPRES_PLLDIV7  ((uint32_t)0x60000000) /*!< PLL clock is divided by 7 */
+#define RCC_CFG_MCOPRES_PLLDIV8  ((uint32_t)0x70000000) /*!< PLL clock is divided by 8 */
+#define RCC_CFG_MCOPRES_PLLDIV9  ((uint32_t)0x80000000) /*!< PLL clock is divided by 9 */
+#define RCC_CFG_MCOPRES_PLLDIV10 ((uint32_t)0x90000000) /*!< PLL clock is divided by 10 */
+#define RCC_CFG_MCOPRES_PLLDIV11 ((uint32_t)0xA0000000) /*!< PLL clock is divided by 11 */
+#define RCC_CFG_MCOPRES_PLLDIV12 ((uint32_t)0xB0000000) /*!< PLL clock is divided by 12 */
+#define RCC_CFG_MCOPRES_PLLDIV13 ((uint32_t)0xC0000000) /*!< PLL clock is divided by 13 */
+#define RCC_CFG_MCOPRES_PLLDIV14 ((uint32_t)0xD0000000) /*!< PLL clock is divided by 14 */
+#define RCC_CFG_MCOPRES_PLLDIV15 ((uint32_t)0xE0000000) /*!< PLL clock is divided by 15 */
+#define RCC_CFG_MCOPRES_PLLDIV16 ((uint32_t)0xF0000000) /*!< PLL clock is divided by 16 */
+
+/*!<******************  Bit definition for RCC_CLKINT register  ********************/
+#define RCC_CLKINT_LSIRDIF   ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CLKINT_LSERDIF   ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CLKINT_HSIRDIF   ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CLKINT_HSERDIF   ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CLKINT_PLLRDIF   ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CLKINT_BORIF     ((uint32_t)0x00000020) /*!< BOR Interrupt flag */
+#define RCC_CLKINT_MSIRDIF   ((uint32_t)0x00000040) /*!< MSI Ready Interrupt flag */
+#define RCC_CLKINT_CLKSSIF   ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CLKINT_LSIRDIEN  ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CLKINT_LSERDIEN  ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CLKINT_HSIRDIEN  ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CLKINT_HSERDIEN  ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CLKINT_PLLRDIEN  ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CLKINT_BORIEN    ((uint32_t)0x00002000) /*!< BOR Interrupt Enable */
+#define RCC_CLKINT_MSIRDIEN  ((uint32_t)0x00004000) /*!< MSI Ready Interrupt Enable */
+#define RCC_CLKINT_MSIRDICLR ((uint32_t)0x00008000) /*!< MSI Ready Interrupt Clear */
+#define RCC_CLKINT_LSIRDICLR ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CLKINT_LSERDICLR ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CLKINT_HSIRDICLR ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CLKINT_HSERDICLR ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CLKINT_PLLRDICLR ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CLKINT_BORICLR   ((uint32_t)0x00200000) /*!< BOR Interrupt Clear */
+#define RCC_CLKINT_CLKSSICLR ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+#define RCC_CLKINT_LSESSIF   ((uint32_t)0x01000000) /*!< LSE Security System Interrupt flag */
+#define RCC_CLKINT_LSESSIEN  ((uint32_t)0x02000000) /*!< LSE ecurity System Interrupt Enable */
+#define RCC_CLKINT_LSESSICLR ((uint32_t)0x04000000) /*!< LSE ecurity System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2PRST register  *****************/
+#define RCC_APB2PRST_AFIORST   ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
+#define RCC_APB2PRST_IOPARST   ((uint32_t)0x00000004) /*!< I/O port A reset */
+#define RCC_APB2PRST_IOPBRST   ((uint32_t)0x00000008) /*!< I/O port B reset */
+#define RCC_APB2PRST_IOPCRST   ((uint32_t)0x00000010) /*!< I/O port C reset */
+#define RCC_APB2PRST_IOPDRST   ((uint32_t)0x00000020) /*!< I/O port D reset */
+#define RCC_APB2PRST_TIM1RST   ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
+#define RCC_APB2PRST_SPI1RST   ((uint32_t)0x00001000) /*!< SPI 1 reset */
+#define RCC_APB2PRST_TIM8RST   ((uint32_t)0x00002000) /*!< TIM8 Timer reset */
+#define RCC_APB2PRST_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+#define RCC_APB2PRST_UART4RST  ((uint32_t)0x00020000) /*!< UART4 reset */
+#define RCC_APB2PRST_UART5RST  ((uint32_t)0x00040000) /*!< UART5 reset */
+#define RCC_APB2PRST_SPI2RST   ((uint32_t)0x00080000) /*!< SPI2 reset */
+
+/*****************  Bit definition for RCC_APB1PRST register  *****************/
+#define RCC_APB1PRST_TIM2RST   ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1PRST_TIM3RST   ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1PRST_TIM4RST   ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1PRST_TIM5RST   ((uint32_t)0x00000008) /*!< Timer 5 reset */
+#define RCC_APB1PRST_TIM6RST   ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1PRST_TIM7RST   ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1PRST_COMPRST   ((uint32_t)0x00000040) /*!< COMP reset */
+#define RCC_APB1PRST_TIM9RST   ((uint32_t)0x00000200) /*!< Timer 9 reset */
+#define RCC_APB1PRST_TSCRST    ((uint32_t)0x00000400) /*!< TSC reset */
+#define RCC_APB1PRST_WWDGRST   ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1PRST_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1PRST_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1PRST_I2C1RST   ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1PRST_I2C2RST   ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#define RCC_APB1PRST_USBRST    ((uint32_t)0x00800000) /*!< USB Device reset */
+#define RCC_APB1PRST_UCDRRST   ((uint32_t)0x01000000) /*!< UCDR reset */
+#define RCC_APB1PRST_CANRST    ((uint32_t)0x02000000) /*!< CAN reset */
+#define RCC_APB1PRST_PWRRST    ((uint32_t)0x10000000) /*!< Power interface reset */
+#define RCC_APB1PRST_DACRST    ((uint32_t)0x20000000) /*!< DAC interface reset */
+#define RCC_APB1PRST_OPARST    ((uint32_t)0x80000000) /*!< OPA interface reset */
+
+/******************  Bit definition for RCC_AHBPCLKEN register  ******************/
+#define RCC_AHBPCLKEN_DMAEN    ((uint32_t)0x00000001) /*!< DMA clock enable */
+#define RCC_AHBPCLKEN_SRAMEN   ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBPCLKEN_FLITFEN  ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBPCLKEN_CRCEN    ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBPCLKEN_RNGCEN   ((uint32_t)0x00000200) /*!< RNGC clock enable */
+#define RCC_AHBPCLKEN_SACEN    ((uint32_t)0x00000800) /*!< SAC clock enable */
+#define RCC_AHBPCLKEN_ADCEN    ((uint32_t)0x00001000) /*!< ADC clock enable */
+
+/******************  Bit definition for RCC_APB2PCLKEN register  *****************/
+#define RCC_APB2PCLKEN_AFIOEN   ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
+#define RCC_APB2PCLKEN_IOPAEN   ((uint32_t)0x00000004) /*!< I/O port A clock enable */
+#define RCC_APB2PCLKEN_IOPBEN   ((uint32_t)0x00000008) /*!< I/O port B clock enable */
+#define RCC_APB2PCLKEN_IOPCEN   ((uint32_t)0x00000010) /*!< I/O port C clock enable */
+#define RCC_APB2PCLKEN_IOPDEN   ((uint32_t)0x00000020) /*!< I/O port D clock enable */
+#define RCC_APB2PCLKEN_TIM1EN   ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
+#define RCC_APB2PCLKEN_SPI1EN   ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2PCLKEN_TIM8EN   ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */
+#define RCC_APB2PCLKEN_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2PCLKEN_UART4EN  ((uint32_t)0x00020000) /*!< UART4 clock enable */
+#define RCC_APB2PCLKEN_UART5EN  ((uint32_t)0x00040000) /*!< UART5 clock enable */
+#define RCC_APB2PCLKEN_SPI2EN   ((uint32_t)0x00080000) /*!< SPI2 clock enable */
+
+/*****************  Bit definition for RCC_APB1PCLKEN register  ******************/
+#define RCC_APB1PCLKEN_TIM2EN     ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1PCLKEN_TIM3EN     ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1PCLKEN_TIM4EN     ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1PCLKEN_TIM5EN     ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+#define RCC_APB1PCLKEN_TIM6EN     ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1PCLKEN_TIM7EN     ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1PCLKEN_COMPEN     ((uint32_t)0x00000040) /*!< COMP clock enable */
+#define RCC_APB1PCLKEN_COMPFILTEN ((uint32_t)0x00000080) /*!< COMPFILT clock enable */
+#define RCC_APB1PCLKEN_AFECEN     ((uint32_t)0x00000100) /*!< AFEC clock enable */
+#define RCC_APB1PCLKEN_TIM9EN     ((uint32_t)0x00000200) /*!< Timer 9 clock enable */
+#define RCC_APB1PCLKEN_TSCEN      ((uint32_t)0x00000400) /*!< TSC clock enable */
+#define RCC_APB1PCLKEN_WWDGEN     ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1PCLKEN_USART2EN   ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1PCLKEN_USART3EN   ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1PCLKEN_I2C1EN     ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1PCLKEN_I2C2EN     ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#define RCC_APB1PCLKEN_USBEN      ((uint32_t)0x00800000) /*!< USB Device clock enable */
+#define RCC_APB1PCLKEN_CANEN      ((uint32_t)0x02000000) /*!< CAN clock enable */
+#define RCC_APB1PCLKEN_PWREN      ((uint32_t)0x10000000) /*!< Power interface clock enable */
+#define RCC_APB1PCLKEN_DACEN      ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+#define RCC_APB1PCLKEN_OPAMPEN    ((uint32_t)0x80000000) /*!< OPAMP interface clock enable */
+
+/*******************  Bit definition for RCC_LDCTRL register  *******************/
+#define RCC_LDCTRL_LSEEN ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_LDCTRL_LSERD ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_LDCTRL_LSEBP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_LDCTRL_LSECLKSSEN ((uint32_t)0x00000008) /*!< LSE Security System enable */
+#define RCC_LDCTRL_LSECLKSSF  ((uint32_t)0x00000010) /*!< LSE Security System failure detection */
+#define RCC_LDCTRL_LSXSEL     ((uint32_t)0x00000020) /*!< LSXSEL bits (TSC clock source selection) */
+
+#define RCC_LDCTRL_RTCSEL   ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_LDCTRL_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_LDCTRL_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_LDCTRL_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_LDCTRL_RTCSEL_LSE     ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_LDCTRL_RTCSEL_LSI     ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_LDCTRL_RTCSEL_HSE     ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define RCC_LDCTRL_RTCEN     ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_LDCTRL_LDSFTRST  ((uint32_t)0x00010000) /*!< Low power domain software reset  */
+#define RCC_LDCTRL_BORRSTF   ((uint32_t)0x10000000) /*!< BOR reset flag */
+#define RCC_LDCTRL_LDEMCRSTF ((uint32_t)0x40000000) /*!< Low power EMC reset flag */
+
+/*******************  Bit definition for RCC_CTRLSTS register  ********************/
+#define RCC_CTRLSTS_LSIEN    ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CTRLSTS_LSIRD    ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CTRLSTS_MSIEN    ((uint32_t)0x00000004) /*!< Internal Multi Speed oscillator enable */
+#define RCC_CTRLSTS_MSIRD    ((uint32_t)0x00000008) /*!< Internal Multi Speed oscillator Ready */
+
+#define RCC_CTRLSTS_MSIRANGE   ((uint32_t)0x00000070) /*!< Internal Multi Speed oscillator Clock Range */
+#define RCC_CTRLSTS_MSIRANGE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CTRLSTS_MSIRANGE_1 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define RCC_CTRLSTS_MSIRANGE_2 ((uint32_t)0x00000040) /*!< Bit 0 */
+
+#define RCC_CTRLSTS_MSIRANGE_100KHz ((uint32_t)0x00000000) /*!< Internal Multi Speed oscillator output 100KHz */
+#define RCC_CTRLSTS_MSIRANGE_200KHz ((uint32_t)0x00000010) /*!< Internal Multi Speed oscillator output 200KHz */
+#define RCC_CTRLSTS_MSIRANGE_400KHz ((uint32_t)0x00000020) /*!< Internal Multi Speed oscillator output 400KHz */
+#define RCC_CTRLSTS_MSIRANGE_800KHz ((uint32_t)0x00000030) /*!< Internal Multi Speed oscillator output 800KHz */
+#define RCC_CTRLSTS_MSIRANGE_1MHz   ((uint32_t)0x00000040) /*!< Internal Multi Speed oscillator output 1MHz */
+#define RCC_CTRLSTS_MSIRANGE_2MHz   ((uint32_t)0x00000050) /*!< Internal Multi Speed oscillator output 2MHz */
+#define RCC_CTRLSTS_MSIRANGE_4MHz   ((uint32_t)0x00000060) /*!< Internal Multi Speed oscillator output 4MHz */
+
+#define RCC_CTRLSTS_MSICAL   ((uint32_t)0x00007F80) /*!< Internal Multi Speed clock Calibration */
+#define RCC_CTRLSTS_MSITRIM  ((uint32_t)0x007F8000) /*!< Internal Multi Speed clock trimming */
+#define RCC_CTRLSTS_RAMRSTF  ((uint32_t)0x00800000) /*!< RAM reset flag */
+#define RCC_CTRLSTS_RMRSTF   ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CTRLSTS_MMURSTF  ((uint32_t)0x02000000) /*!< MMU reset flag */
+#define RCC_CTRLSTS_PINRSTF  ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CTRLSTS_PORRSTF  ((uint32_t)0x08000000) /*!< POR reset flag */
+#define RCC_CTRLSTS_SFTRSTF  ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CTRLSTS_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CTRLSTS_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CTRLSTS_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/*******************  Bit definition for RCC_AHBPRST register  ****************/
+#define RCC_AHBRST_RNGCRST   ((uint32_t)0x00000200) /*!< RNGC reset */
+#define RCC_AHBRST_SACRST    ((uint32_t)0x00000800) /*!< SAC reset */
+#define RCC_AHBRST_ADCRST    ((uint32_t)0x00001000) /*!< ADC reset */
+
+/*******************  Bit definition for RCC_CFG2 register  ******************/
+/*!< ADCHPRE configuration */
+#define RCC_CFG2_ADCHPRES   ((uint32_t)0x0000000F) /*!< ADCHPRE[3:0] bits */
+#define RCC_CFG2_ADCHPRES_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFG2_ADCHPRES_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFG2_ADCHPRES_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFG2_ADCHPRES_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFG2_ADCHPRES_DIV1   ((uint32_t)0x00000000) /*!< HCLK clock divided by 1 */
+#define RCC_CFG2_ADCHPRES_DIV2   ((uint32_t)0x00000001) /*!< HCLK clock divided by 2 */
+#define RCC_CFG2_ADCHPRES_DIV4   ((uint32_t)0x00000002) /*!< HCLK clock divided by 4 */
+#define RCC_CFG2_ADCHPRES_DIV6   ((uint32_t)0x00000003) /*!< HCLK clock divided by 6 */
+#define RCC_CFG2_ADCHPRES_DIV8   ((uint32_t)0x00000004) /*!< HCLK clock divided by 8 */
+#define RCC_CFG2_ADCHPRES_DIV10  ((uint32_t)0x00000005) /*!< HCLK clock divided by 10 */
+#define RCC_CFG2_ADCHPRES_DIV12  ((uint32_t)0x00000006) /*!< HCLK clock divided by 12 */
+#define RCC_CFG2_ADCHPRES_DIV16  ((uint32_t)0x00000007) /*!< HCLK clock divided by 16 */
+#define RCC_CFG2_ADCHPRES_DIV32  ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */
+#define RCC_CFG2_ADCHPRES_OTHERS ((uint32_t)0x00000008) /*!< HCLK clock divided by 32 */
+
+/*!< ADCPLLPRES configuration */
+#define RCC_CFG2_ADCPLLPRES   ((uint32_t)0x000001F0) /*!< ADCPLLPRES[4:0] bits */
+#define RCC_CFG2_ADCPLLPRES_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFG2_ADCPLLPRES_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFG2_ADCPLLPRES_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFG2_ADCPLLPRES_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+#define RCC_CFG2_ADCPLLPRES_4 ((uint32_t)0x00000100) /*!< Bit 4 */
+
+#define RCC_CFG2_ADCPLLCLK_DISABLE  ((uint32_t)0xFFFFFEFF) /*!< ADC PLL clock Disable */
+#define RCC_CFG2_ADCPLLPRES_DIV1    ((uint32_t)0x00000100) /*!< PLL clock divided by 1 */
+#define RCC_CFG2_ADCPLLPRES_DIV2    ((uint32_t)0x00000110) /*!< PLL clock divided by 2 */
+#define RCC_CFG2_ADCPLLPRES_DIV4    ((uint32_t)0x00000120) /*!< PLL clock divided by 4 */
+#define RCC_CFG2_ADCPLLPRES_DIV6    ((uint32_t)0x00000130) /*!< PLL clock divided by 6 */
+#define RCC_CFG2_ADCPLLPRES_DIV8    ((uint32_t)0x00000140) /*!< PLL clock divided by 8 */
+#define RCC_CFG2_ADCPLLPRES_DIV10   ((uint32_t)0x00000150) /*!< PLL clock divided by 10 */
+#define RCC_CFG2_ADCPLLPRES_DIV12   ((uint32_t)0x00000160) /*!< PLL clock divided by 12 */
+#define RCC_CFG2_ADCPLLPRES_DIV16   ((uint32_t)0x00000170) /*!< PLL clock divided by 16 */
+#define RCC_CFG2_ADCPLLPRES_DIV32   ((uint32_t)0x00000180) /*!< PLL clock divided by 32 */
+#define RCC_CFG2_ADCPLLPRES_DIV64   ((uint32_t)0x00000190) /*!< PLL clock divided by 64 */
+#define RCC_CFG2_ADCPLLPRES_DIV128  ((uint32_t)0x000001A0) /*!< PLL clock divided by 128 */
+#define RCC_CFG2_ADCPLLPRES_DIV256  ((uint32_t)0x000001B0) /*!< PLL clock divided by 256 */
+#define RCC_CFG2_ADCPLLPRES_DIV256N ((uint32_t)0x000001C0) /*!< PLL clock divided by 256 */
+
+/*!< ADC1MPRE configuration */
+#define RCC_CFG2_ADC1MPRES   ((uint32_t)0x0001F000) /*!< ADC1MPRE[4:0] bits */
+#define RCC_CFG2_ADC1MPRES_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define RCC_CFG2_ADC1MPRES_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define RCC_CFG2_ADC1MPRES_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+#define RCC_CFG2_ADC1MPRES_3 ((uint32_t)0x00008000) /*!< Bit 3 */
+#define RCC_CFG2_ADC1MPRES_4 ((uint32_t)0x00010000) /*!< Bit 4 */
+
+#define RCC_CFG2_ADC1MPRES_DIV1  ((uint32_t)0x00000000) /*!< ADC1M source clock is divided by 1 */
+#define RCC_CFG2_ADC1MPRES_DIV2  ((uint32_t)0x00001000) /*!< ADC1M source clock is divided by 2 */
+#define RCC_CFG2_ADC1MPRES_DIV3  ((uint32_t)0x00002000) /*!< ADC1M source clock is divided by 3 */
+#define RCC_CFG2_ADC1MPRES_DIV4  ((uint32_t)0x00003000) /*!< ADC1M source clock is divided by 4 */
+#define RCC_CFG2_ADC1MPRES_DIV5  ((uint32_t)0x00004000) /*!< ADC1M source clock is divided by 5 */
+#define RCC_CFG2_ADC1MPRES_DIV6  ((uint32_t)0x00005000) /*!< ADC1M source clock is divided by 6 */
+#define RCC_CFG2_ADC1MPRES_DIV7  ((uint32_t)0x00006000) /*!< ADC1M source clock is divided by 7 */
+#define RCC_CFG2_ADC1MPRES_DIV8  ((uint32_t)0x00007000) /*!< ADC1M source clock is divided by 8 */
+#define RCC_CFG2_ADC1MPRES_DIV9  ((uint32_t)0x00008000) /*!< ADC1M source clock is divided by 9 */
+#define RCC_CFG2_ADC1MPRES_DIV10 ((uint32_t)0x00009000) /*!< ADC1M source clock is divided by 10 */
+#define RCC_CFG2_ADC1MPRES_DIV11 ((uint32_t)0x0000A000) /*!< ADC1M source clock is divided by 11 */
+#define RCC_CFG2_ADC1MPRES_DIV12 ((uint32_t)0x0000B000) /*!< ADC1M source clock is divided by 12 */
+#define RCC_CFG2_ADC1MPRES_DIV13 ((uint32_t)0x0000C000) /*!< ADC1M source clock is divided by 13 */
+#define RCC_CFG2_ADC1MPRES_DIV14 ((uint32_t)0x0000D000) /*!< ADC1M source clock is divided by 14 */
+#define RCC_CFG2_ADC1MPRES_DIV15 ((uint32_t)0x0000E000) /*!< ADC1M source clock is divided by 15 */
+#define RCC_CFG2_ADC1MPRES_DIV16 ((uint32_t)0x0000F000) /*!< ADC1M source clock is divided by 16 */
+#define RCC_CFG2_ADC1MPRES_DIV17 ((uint32_t)0x00010000) /*!< ADC1M source clock is divided by 17 */
+#define RCC_CFG2_ADC1MPRES_DIV18 ((uint32_t)0x00011000) /*!< ADC1M source clock is divided by 18 */
+#define RCC_CFG2_ADC1MPRES_DIV19 ((uint32_t)0x00012000) /*!< ADC1M source clock is divided by 19 */
+#define RCC_CFG2_ADC1MPRES_DIV20 ((uint32_t)0x00013000) /*!< ADC1M source clock is divided by 20 */
+#define RCC_CFG2_ADC1MPRES_DIV21 ((uint32_t)0x00014000) /*!< ADC1M source clock is divided by 21 */
+#define RCC_CFG2_ADC1MPRES_DIV22 ((uint32_t)0x00015000) /*!< ADC1M source clock is divided by 22 */
+#define RCC_CFG2_ADC1MPRES_DIV23 ((uint32_t)0x00016000) /*!< ADC1M source clock is divided by 23 */
+#define RCC_CFG2_ADC1MPRES_DIV24 ((uint32_t)0x00017000) /*!< ADC1M source clock is divided by 24 */
+#define RCC_CFG2_ADC1MPRES_DIV25 ((uint32_t)0x00018000) /*!< ADC1M source clock is divided by 25 */
+#define RCC_CFG2_ADC1MPRES_DIV26 ((uint32_t)0x00019000) /*!< ADC1M source clock is divided by 26 */
+#define RCC_CFG2_ADC1MPRES_DIV27 ((uint32_t)0x0001A000) /*!< ADC1M source clock is divided by 27 */
+#define RCC_CFG2_ADC1MPRES_DIV28 ((uint32_t)0x0001B000) /*!< ADC1M source clock is divided by 28 */
+#define RCC_CFG2_ADC1MPRES_DIV29 ((uint32_t)0x0001C000) /*!< ADC1M source clock is divided by 29 */
+#define RCC_CFG2_ADC1MPRES_DIV30 ((uint32_t)0x0001D000) /*!< ADC1M source clock is divided by 30 */
+#define RCC_CFG2_ADC1MPRES_DIV31 ((uint32_t)0x0001E000) /*!< ADC1M source clock is divided by 31 */
+#define RCC_CFG2_ADC1MPRES_DIV32 ((uint32_t)0x0001F000) /*!< ADC1M source clock is divided by 32 */
+
+/*!< ADC1MSEL configuration */
+#define RCC_CFG2_ADC1MSEL ((uint32_t)0x00020000) /*!< ADC1M clock source select */
+
+#define RCC_CFG2_ADC1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as ADC1M input clock */
+#define RCC_CFG2_ADC1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as ADC1M input clock */
+
+/*!< RNGCPRE configuration */
+#define RCC_CFG2_RNGCPRES   ((uint32_t)0x1F000000) /*!< RNGCPRE[4:0] bits */
+#define RCC_CFG2_RNGCPRES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFG2_RNGCPRES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFG2_RNGCPRES_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define RCC_CFG2_RNGCPRES_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define RCC_CFG2_RNGCPRES_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+
+#define RCC_CFG2_RNGCPRES_DIV1  ((uint32_t)0x00000000) /*!< SYSCLK source clock is divided by 1 */
+#define RCC_CFG2_RNGCPRES_DIV2  ((uint32_t)0x01000000) /*!< SYSCLK source clock is divided by 2 */
+#define RCC_CFG2_RNGCPRES_DIV3  ((uint32_t)0x02000000) /*!< SYSCLK source clock is divided by 3 */
+#define RCC_CFG2_RNGCPRES_DIV4  ((uint32_t)0x03000000) /*!< SYSCLK source clock is divided by 4 */
+#define RCC_CFG2_RNGCPRES_DIV5  ((uint32_t)0x04000000) /*!< SYSCLK source clock is divided by 5 */
+#define RCC_CFG2_RNGCPRES_DIV6  ((uint32_t)0x05000000) /*!< SYSCLK source clock is divided by 6 */
+#define RCC_CFG2_RNGCPRES_DIV7  ((uint32_t)0x06000000) /*!< SYSCLK source clock is divided by 7 */
+#define RCC_CFG2_RNGCPRES_DIV8  ((uint32_t)0x07000000) /*!< SYSCLK source clock is divided by 8 */
+#define RCC_CFG2_RNGCPRES_DIV9  ((uint32_t)0x08000000) /*!< SYSCLK source clock is divided by 9 */
+#define RCC_CFG2_RNGCPRES_DIV10 ((uint32_t)0x09000000) /*!< SYSCLK source clock is divided by 10 */
+#define RCC_CFG2_RNGCPRES_DIV11 ((uint32_t)0x0A000000) /*!< SYSCLK source clock is divided by 11 */
+#define RCC_CFG2_RNGCPRES_DIV12 ((uint32_t)0x0B000000) /*!< SYSCLK source clock is divided by 12 */
+#define RCC_CFG2_RNGCPRES_DIV13 ((uint32_t)0x0C000000) /*!< SYSCLK source clock is divided by 13 */
+#define RCC_CFG2_RNGCPRES_DIV14 ((uint32_t)0x0D000000) /*!< SYSCLK source clock is divided by 14 */
+#define RCC_CFG2_RNGCPRES_DIV15 ((uint32_t)0x0E000000) /*!< SYSCLK source clock is divided by 15 */
+#define RCC_CFG2_RNGCPRES_DIV16 ((uint32_t)0x0F000000) /*!< SYSCLK source clock is divided by 16 */
+#define RCC_CFG2_RNGCPRES_DIV17 ((uint32_t)0x10000000) /*!< SYSCLK source clock is divided by 17 */
+#define RCC_CFG2_RNGCPRES_DIV18 ((uint32_t)0x11000000) /*!< SYSCLK source clock is divided by 18 */
+#define RCC_CFG2_RNGCPRES_DIV19 ((uint32_t)0x12000000) /*!< SYSCLK source clock is divided by 19 */
+#define RCC_CFG2_RNGCPRES_DIV20 ((uint32_t)0x13000000) /*!< SYSCLK source clock is divided by 20 */
+#define RCC_CFG2_RNGCPRES_DIV21 ((uint32_t)0x14000000) /*!< SYSCLK source clock is divided by 21 */
+#define RCC_CFG2_RNGCPRES_DIV22 ((uint32_t)0x15000000) /*!< SYSCLK source clock is divided by 22 */
+#define RCC_CFG2_RNGCPRES_DIV23 ((uint32_t)0x16000000) /*!< SYSCLK source clock is divided by 23 */
+#define RCC_CFG2_RNGCPRES_DIV24 ((uint32_t)0x17000000) /*!< SYSCLK source clock is divided by 24 */
+#define RCC_CFG2_RNGCPRES_DIV25 ((uint32_t)0x18000000) /*!< SYSCLK source clock is divided by 25 */
+#define RCC_CFG2_RNGCPRES_DIV26 ((uint32_t)0x19000000) /*!< SYSCLK source clock is divided by 26 */
+#define RCC_CFG2_RNGCPRES_DIV27 ((uint32_t)0x1A000000) /*!< SYSCLK source clock is divided by 27 */
+#define RCC_CFG2_RNGCPRES_DIV28 ((uint32_t)0x1B000000) /*!< SYSCLK source clock is divided by 28 */
+#define RCC_CFG2_RNGCPRES_DIV29 ((uint32_t)0x1C000000) /*!< SYSCLK source clock is divided by 29 */
+#define RCC_CFG2_RNGCPRES_DIV30 ((uint32_t)0x1D000000) /*!< SYSCLK source clock is divided by 30 */
+#define RCC_CFG2_RNGCPRES_DIV31 ((uint32_t)0x1E000000) /*!< SYSCLK source clock is divided by 31 */
+#define RCC_CFG2_RNGCPRES_DIV32 ((uint32_t)0x1F000000) /*!< SYSCLK source clock is divided by 32 */
+
+/*!< TIMCLK_SEL configuration */
+#define RCC_CFG2_TIMCLKSEL ((uint32_t)0x20000000) /*!< Timer1/8 clock source select */
+
+#define RCC_CFG2_TIMCLKSEL_TIM18CLK ((uint32_t)0x00000000) /*!< Timer1/8 clock selected as tim1/8_clk input clock */
+#define RCC_CFG2_TIMCLKSEL_SYSCLK   ((uint32_t)0x20000000) /*!< Timer1/8 clock selected as sysclk input clock */
+
+/*******************  Bit definition for RCC_CFG3 register  ******************/
+/*!< UCDREN configuration */
+#define RCC_CFG3_UCDREN ((uint32_t)0x00000080) /*!< UCDR enable */
+
+#define RCC_CFG3_UCDREN_ENABLE  ((uint32_t)0x00000080) /*!< UCDREN enable */
+#define RCC_CFG3_UCDREN_DISABLE ((uint32_t)0x00000000) /*!< UCDREN disable */
+
+/*!< USBXTALESS configuration */
+#define RCC_CFG3_USBXTALESS ((uint32_t)0x00000100) /*!< UCDR enable */
+
+#define RCC_CFG3_USBXTALESS_LESSMODE ((uint32_t)0x00000100) /*!< USB Crystalless mode */
+#define RCC_CFG3_USBXTALESS_MODE     ((uint32_t)0x00000000) /*!< USB Crystal mode */
+
+/*!< UCDR300MSEL configuration */
+#define RCC_CFG3_UCDR300MSEL ((uint32_t)0x00000200) /*!< UCDR 300M Clock source */
+
+#define RCC_CFG3_UCDR300MSEL_PLLVCO  ((uint32_t)0x00000200) /*!< PLL VCO selected as UCDR 300M Clock source */
+#define RCC_CFG3_UCDR300MSEL_OSC300M ((uint32_t)0x00000000) /*!< OSC300M selected as UCDR 300M Clock source */
+
+/*!< TRNG1MPRE configuration */
+#define RCC_CFG3_TRNG1MPRES   ((uint32_t)0x0000F800) /*!< TRNG1MPRE[4:0] bits */
+#define RCC_CFG3_TRNG1MPRES_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFG3_TRNG1MPRES_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFG3_TRNG1MPRES_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+#define RCC_CFG3_TRNG1MPRES_3 ((uint32_t)0x00004000) /*!< Bit 3 */
+#define RCC_CFG3_TRNG1MPRES_4 ((uint32_t)0x00008000) /*!< Bit 4 */
+
+#define RCC_CFG3_TRNG1MPRES_VAL2  ((uint32_t)0x00000800) /*!< TRNG 1M source clock is divided by 2 */
+#define RCC_CFG3_TRNG1MPRES_VAL3  ((uint32_t)0x00001000) /*!< TRNG 1M source clock is divided by 4 */
+#define RCC_CFG3_TRNG1MPRES_VAL4  ((uint32_t)0x00001800) /*!< TRNG 1M source clock is divided by 6 */
+#define RCC_CFG3_TRNG1MPRES_VAL5  ((uint32_t)0x00002000) /*!< TRNG 1M source clock is divided by 8 */
+#define RCC_CFG3_TRNG1MPRES_VAL6  ((uint32_t)0x00002800) /*!< TRNG 1M source clock is divided by 10 */
+#define RCC_CFG3_TRNG1MPRES_VAL7  ((uint32_t)0x00003000) /*!< TRNG 1M source clock is divided by 12 */
+#define RCC_CFG3_TRNG1MPRES_VAL8  ((uint32_t)0x00003800) /*!< TRNG 1M source clock is divided by 14 */
+#define RCC_CFG3_TRNG1MPRES_VAL9  ((uint32_t)0x00004000) /*!< TRNG 1M source clock is divided by 16 */
+#define RCC_CFG3_TRNG1MPRES_VAL10 ((uint32_t)0x00004800) /*!< TRNG 1M source clock is divided by 18 */
+#define RCC_CFG3_TRNG1MPRES_VAL11 ((uint32_t)0x00005000) /*!< TRNG 1M source clock is divided by 20 */
+#define RCC_CFG3_TRNG1MPRES_VAL12 ((uint32_t)0x00005800) /*!< TRNG 1M source clock is divided by 22 */
+#define RCC_CFG3_TRNG1MPRES_VAL13 ((uint32_t)0x00006000) /*!< TRNG 1M source clock is divided by 24 */
+#define RCC_CFG3_TRNG1MPRES_VAL14 ((uint32_t)0x00006800) /*!< TRNG 1M source clock is divided by 26 */
+#define RCC_CFG3_TRNG1MPRES_VAL15 ((uint32_t)0x00007000) /*!< TRNG 1M source clock is divided by 28 */
+#define RCC_CFG3_TRNG1MPRES_VAL16 ((uint32_t)0x00007800) /*!< TRNG 1M source clock is divided by 30 */
+#define RCC_CFG3_TRNG1MPRES_VAL17 ((uint32_t)0x00008000) /*!< TRNG 1M source clock is divided by 32 */
+#define RCC_CFG3_TRNG1MPRES_VAL18 ((uint32_t)0x00008800) /*!< TRNG 1M source clock is divided by 34 */
+#define RCC_CFG3_TRNG1MPRES_VAL19 ((uint32_t)0x00009000) /*!< TRNG 1M source clock is divided by 36 */
+#define RCC_CFG3_TRNG1MPRES_VAL20 ((uint32_t)0x00009800) /*!< TRNG 1M source clock is divided by 38 */
+#define RCC_CFG3_TRNG1MPRES_VAL21 ((uint32_t)0x0000A000) /*!< TRNG 1M source clock is divided by 40 */
+#define RCC_CFG3_TRNG1MPRES_VAL22 ((uint32_t)0x0000A800) /*!< TRNG 1M source clock is divided by 42 */
+#define RCC_CFG3_TRNG1MPRES_VAL23 ((uint32_t)0x0000B000) /*!< TRNG 1M source clock is divided by 44 */
+#define RCC_CFG3_TRNG1MPRES_VAL24 ((uint32_t)0x0000B800) /*!< TRNG 1M source clock is divided by 46 */
+#define RCC_CFG3_TRNG1MPRES_VAL25 ((uint32_t)0x0000C000) /*!< TRNG 1M source clock is divided by 48 */
+#define RCC_CFG3_TRNG1MPRES_VAL26 ((uint32_t)0x0000C800) /*!< TRNG 1M source clock is divided by 50 */
+#define RCC_CFG3_TRNG1MPRES_VAL27 ((uint32_t)0x0000D000) /*!< TRNG 1M source clock is divided by 52 */
+#define RCC_CFG3_TRNG1MPRES_VAL28 ((uint32_t)0x0000D800) /*!< TRNG 1M source clock is divided by 54 */
+#define RCC_CFG3_TRNG1MPRES_VAL29 ((uint32_t)0x0000E000) /*!< TRNG 1M source clock is divided by 56 */
+#define RCC_CFG3_TRNG1MPRES_VAL30 ((uint32_t)0x0000E800) /*!< TRNG 1M source clock is divided by 58 */
+#define RCC_CFG3_TRNG1MPRES_VAL31 ((uint32_t)0x0000F000) /*!< TRNG 1M source clock is divided by 60 */
+#define RCC_CFG3_TRNG1MPRES_VAL32 ((uint32_t)0x0000F800) /*!< TRNG 1M source clock is divided by 62 */
+
+/*!< TRNG1MSEL configuration */
+#define RCC_CFG3_TRNG1MSEL ((uint32_t)0x00020000) /*!< TRNG_1M clock source select */
+
+#define RCC_CFG3_TRNG1MSEL_HSI ((uint32_t)0x00000000) /*!< HSI clock selected as TRNG_1M input clock */
+#define RCC_CFG3_TRNG1MSEL_HSE ((uint32_t)0x00020000) /*!< HSE clock selected as TRNG_1M input clock */
+
+/*!< TRNG1MEN configuration */
+#define RCC_CFG3_TRNG1MEN ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */
+
+#define RCC_CFG3_TRNG1MEN_DISABLE ((uint32_t)0x00000000) /*!< TRNG_1M clock disable */
+#define RCC_CFG3_TRNG1MEN_ENABLE  ((uint32_t)0x00040000) /*!< TRNG_1M clock enable */
+
+/*******************  Bit definition for RCC_RDCTRL register  ******************/
+/*!< LPTIMSEL congiguration */
+#define RCC_RDCTRL_LPTIMSEL   ((uint32_t)0x00000007) /*!< LPTIMSEL[2:0] bits (LPTIM clock source selection) */
+#define RCC_RDCTRL_LPTIMSEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_RDCTRL_LPTIMSEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_RDCTRL_LPTIMSEL_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define RCC_RDCTRL_LPTIMSEL_APB1  ((uint32_t)0x00000000) /*!< APB1 clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_LSI   ((uint32_t)0x00000001) /*!< LSI oscillator clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_HSI   ((uint32_t)0x00000002) /*!< HSI oscillator clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_LSE   ((uint32_t)0x00000003) /*!< LSE oscillator clock used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_COMP1 ((uint32_t)0x00000004) /*!< COMP1 output used as LPTIM clock */
+#define RCC_RDCTRL_LPTIMSEL_COMP2 ((uint32_t)0x00000005) /*!< COMP1 output used as LPTIM clock */
+
+/*!< LPUARTSEL congiguration */
+#define RCC_RDCTRL_LPUARTSEL   ((uint32_t)0x00000018) /*!< LPUARTSEL[1:0] bits (LPUART clock source selection) */
+#define RCC_RDCTRL_LPUARTSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_RDCTRL_LPUARTSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_RDCTRL_LPUARTSEL_APB1   ((uint32_t)0x00000000) /*!< APB1 clock used as LPUART clock */
+#define RCC_RDCTRL_LPUARTSEL_SYSCLK ((uint32_t)0x00000008) /*!< SYSCLK used as LPUART clock */
+#define RCC_RDCTRL_LPUARTSEL_HSI    ((uint32_t)0x00000010) /*!< HSI oscillator clock used as LPUART clock */
+#define RCC_RDCTRL_LPUARTSEL_LSE    ((uint32_t)0x00000018) /*!< LSE oscillator clock used as LPUART clock */
+
+#define RCC_RDCTRL_LPTIMEN   ((uint32_t)0x00000040) /*!< LPTIM clock enable */
+#define RCC_RDCTRL_LPUARTEN  ((uint32_t)0x00000080) /*!< LPUART clock enable */
+#define RCC_RDCTRL_LPTIMRST  ((uint32_t)0x00000400) /*!< LPTIM reset */
+#define RCC_RDCTRL_LPUARTRST ((uint32_t)0x00000800) /*!< LPUART reset */
+
+/*******************  Bit definition for RCC_PLLHSIPRE register  ******************/
+/*!< PLLHSIPRE configuration */
+#define RCC_PLLHSIPRE_PLLHSIPRE ((uint32_t)0x00000001) /*!< HSI divider for PLL entry */
+
+#define RCC_PLLHSIPRE_PLLHSIPRE_HSI      ((uint32_t)0x00000000) /*!< HSI clock not divided for PLL entry */
+#define RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2 ((uint32_t)0x00000001) /*!< HSI clock divided by 2 for PLL entry */
+
+/*!< PLLSRCDIV configuration */
+#define RCC_PLLHSIPRE_PLLSRCDIV ((uint32_t)0x00000002) /*!< PLL source clock for PLL entry */
+
+#define RCC_PLLHSIPRE_PLLSRCDIV_DISABLE ((uint32_t)0x00000000) /*!< PLL source clock not divided for PLL entry */
+#define RCC_PLLHSIPRE_PLLSRCDIV_ENABLE  ((uint32_t)0x00000002) /*!< PLL source clock divided by 2 for PLL entry */
+
+/*******************  Bit definition for RCC_SRAM_CTRLSTS register  ******************/
+#define RCC_SRAM_CTRLSTS_ERR1EN    ((uint32_t)0x00000001) /*!< SRAM1 Parity Error Interrupt Enable */
+#define RCC_SRAM_CTRLSTS_ERR1RSTEN ((uint32_t)0x00000002) /*!< SRAM1 Parity Error Reset Enable */
+#define RCC_SRAM_CTRLSTS_ERR1STS   ((uint32_t)0x00000004) /*!< SRAM1 Parity Error Status */
+#define RCC_SRAM_CTRLSTS_ERR2EN    ((uint32_t)0x00000008) /*!< SRAM2 Parity Error Interrupt Enable */
+#define RCC_SRAM_CTRLSTS_ERR2RSTEN ((uint32_t)0x00000010) /*!< SRAM2 Parity Error Reset Enable */
+#define RCC_SRAM_CTRLSTS_ERR2STS   ((uint32_t)0x00000020) /*!< SRAM2 Parity Error Status */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               SystemTick                                   */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for SysTick_CTRL register  *****************/
+#define SysTick_CTRL_ENABLE    ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT   ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/*****************  Bit definition for SysTick_LOAD register  *****************/
+#define SysTick_LOAD_RELOAD                                                                                            \
+    ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/*****************  Bit definition for SysTick_VAL register  ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/*****************  Bit definition for SysTick_CALIB register  ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW  ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/*                                                                            */
+/*                  Nested Vectored Interrupt Controller                      */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for NVIC_ISER register  *******************/
+#define NVIC_ISER_SETENA    ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0  ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1  ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2  ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3  ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4  ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5  ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6  ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7  ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8  ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9  ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICER register  *******************/
+#define NVIC_ICER_CLRENA    ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0  ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1  ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2  ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3  ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4  ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5  ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6  ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7  ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8  ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9  ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ISPR register  *******************/
+#define NVIC_ISPR_SETPEND    ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0  ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1  ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2  ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3  ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4  ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5  ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6  ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7  ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8  ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9  ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICPR register  *******************/
+#define NVIC_ICPR_CLRPEND    ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0  ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1  ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2  ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3  ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4  ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5  ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6  ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7  ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8  ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9  ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/******************  Bit definition for NVIC_IABR register  *******************/
+#define NVIC_IABR_ACTIVE    ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0  ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1  ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2  ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3  ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4  ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5  ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6  ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7  ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8  ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9  ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/******************  Bit definition for NVIC_PRI0 register  *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/******************  Bit definition for NVIC_PRI1 register  *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/******************  Bit definition for NVIC_PRI2 register  *******************/
+#define NVIC_IPR2_PRI_8  ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9  ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/******************  Bit definition for NVIC_PRI3 register  *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/******************  Bit definition for NVIC_PRI4 register  *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/******************  Bit definition for NVIC_PRI5 register  *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/******************  Bit definition for NVIC_PRI6 register  *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/******************  Bit definition for NVIC_PRI7 register  *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/******************  Bit definition for SCB_CPUID register  *******************/
+#define SCB_CPUID_REVISION    ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO      ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant    ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT     ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/*******************  Bit definition for SCB_ICSR register  *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active INTSTS number field */
+#define SCB_ICSR_RETTOBASE                                                                                             \
+    ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending INTSTS number field */
+#define SCB_ICSR_ISRPENDING  ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT                                                                                            \
+    ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR  ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET  ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR  ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET  ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/*******************  Bit definition for SCB_VTOR register  *******************/
+#define SCB_VTOR_TBLOFF  ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
+#define SCB_AIRCR_VECTRESET     ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ   ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP   ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2  */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0                                                                                            \
+    ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1                                                                                            \
+    ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2                                                                                            \
+    ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3                                                                                            \
+    ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4                                                                                            \
+    ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5                                                                                            \
+    ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6                                                                                            \
+    ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7                                                                                            \
+    ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY   ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/*******************  Bit definition for SCB_SCR register  ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP   ((uint8_t)0x04) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND   ((uint8_t)0x10) /*!< Wake up from WFE */
+
+/********************  Bit definition for SCB_CCR register  *******************/
+#define SCB_CCR_NONBASETHRDENA                                                                                         \
+    ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND                                                                                           \
+    ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a     \
+                          Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP   ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN   ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN                                                                                               \
+    ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/*******************  Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N                                                                                                 \
+    ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1                                                                                                \
+    ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2                                                                                                \
+    ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3                                                                                                \
+    ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/******************  Bit definition for SCB_SHCSR register  *******************/
+#define SCB_SHCSR_MEMFAULTACT    ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT    ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT    ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT      ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT     ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT      ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT     ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED   ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA    ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA    ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA    ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/*******************  Bit definition for SCB_CFSR register  *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL  ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL  ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR   ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR     ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR   ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR    ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR      ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID   ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE   ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC      ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP       ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED                                                                                             \
+    ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO                                                                                             \
+    ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/*******************  Bit definition for SCB_HFSR register  *******************/
+#define SCB_HFSR_VECTTBL                                                                                               \
+    ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED                                                                                                \
+    ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/*******************  Bit definition for SCB_DFSR register  *******************/
+#define SCB_DFSR_HALTED   ((uint8_t)0x01) /*!< Halt request flag */
+#define SCB_DFSR_BKPT     ((uint8_t)0x02) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP  ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH   ((uint8_t)0x08) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
+
+/*******************  Bit definition for SCB_MMFAR register  ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/*******************  Bit definition for SCB_BFAR register  *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/*******************  Bit definition for SCB_afsr register  *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_INTSTS register  ********************/
+#define DMA_INTSTS_GLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_INTSTS_TXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_INTSTS_HTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_INTSTS_ERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_INTSTS_GLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_INTSTS_TXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_INTSTS_HTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_INTSTS_ERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_INTSTS_GLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_INTSTS_TXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_INTSTS_HTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_INTSTS_ERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_INTSTS_GLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_INTSTS_TXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_INTSTS_HTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_INTSTS_ERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_INTSTS_GLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_INTSTS_TXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_INTSTS_HTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_INTSTS_ERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_INTSTS_GLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_INTSTS_TXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_INTSTS_HTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_INTSTS_ERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_INTSTS_GLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_INTSTS_TXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_INTSTS_HTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_INTSTS_ERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+#define DMA_INTSTS_GLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_INTSTS_TXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_INTSTS_HTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_INTSTS_ERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_INTCLR register  *******************/
+#define DMA_INTCLR_CGLBF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_INTCLR_CTXCF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_INTCLR_CERRF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_INTCLR_CGLBF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_INTCLR_CTXCF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_INTCLR_CERRF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_INTCLR_CGLBF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_INTCLR_CTXCF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_INTCLR_CERRF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_INTCLR_CGLBF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_INTCLR_CTXCF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_INTCLR_CERRF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_INTCLR_CGLBF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_INTCLR_CTXCF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_INTCLR_CERRF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_INTCLR_CGLBF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_INTCLR_CTXCF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_INTCLR_CERRF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_INTCLR_CGLBF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_INTCLR_CTXCF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_INTCLR_CERRF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+#define DMA_INTCLR_CGLBF8 ((uint32_t)0x10000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_INTCLR_CTXCF8 ((uint32_t)0x20000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_INTCLR_CHTXF8 ((uint32_t)0x40000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_INTCLR_CERRF8 ((uint32_t)0x80000000) /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CHCFG1 register  *******************/
+#define DMA_CHCFG1_CHEN  ((uint16_t)0x0001) /*!< Channel enable*/
+#define DMA_CHCFG1_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG1_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG1_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG1_DIR   ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG1_CIRC  ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG1_PINC  ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG1_MINC  ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG1_PSIZE   ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG1_MSIZE   ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG1_PRIOLVL   ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CHCFG1_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG1_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CHCFG2 register  *******************/
+#define DMA_CHCFG2_CHEN  ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG2_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG2_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG2_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG2_DIR   ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG2_CIRC  ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG2_PINC  ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG2_MINC  ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG2_PSIZE   ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG2_MSIZE   ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG2_PRIOLVL   ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG2_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG2_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CHCFG3 register  *******************/
+#define DMA_CHCFG3_CHEN  ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG3_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG3_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG3_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG3_DIR   ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG3_CIRC  ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG3_PINC  ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG3_MINC  ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG3_PSIZE   ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG3_MSIZE   ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG3_PRIOLVL   ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG3_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG3_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*!<******************  Bit definition for DMA_CHCFG4 register  *******************/
+#define DMA_CHCFG4_CHEN  ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG4_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG4_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG4_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG4_DIR   ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG4_CIRC  ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG4_PINC  ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG4_MINC  ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG4_PSIZE   ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG4_MSIZE   ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG4_PRIOLVL   ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG4_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG4_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************  Bit definition for DMA_CHCFG5 register  *******************/
+#define DMA_CHCFG5_CHEN  ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG5_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG5_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG5_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG5_DIR   ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG5_CIRC  ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG5_PINC  ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG5_MINC  ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG5_PSIZE   ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG5_MSIZE   ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG5_PRIOLVL   ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG5_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG5_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CHCFG6 register  *******************/
+#define DMA_CHCFG6_CHEN  ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG6_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG6_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG6_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG6_DIR   ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG6_CIRC  ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG6_PINC  ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG6_MINC  ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG6_PSIZE   ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CHCFG6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CHCFG6_MSIZE   ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG6_PRIOLVL   ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG6_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG6_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CHCFG7 register  *******************/
+#define DMA_CHCFG7_CHEN  ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG7_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG7_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG7_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG7_DIR   ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG7_CIRC  ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG7_PINC  ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG7_MINC  ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG7_PSIZE   , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG7_PSIZE_0 ((uint16_t)0x0100)   /*!< Bit 0 */
+#define DMA_CHCFG7_PSIZE_1 ((uint16_t)0x0200)   /*!< Bit 1 */
+
+#define DMA_CHCFG7_MSIZE   ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG7_PRIOLVL   ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG7_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG7_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CHCFG8 register  *******************/
+#define DMA_CHCFG8_CHEN  ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CHCFG8_TXCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CHCFG8_HTXIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CHCFG8_ERRIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CHCFG8_DIR   ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CHCFG8_CIRC  ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CHCFG8_PINC  ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CHCFG8_MINC  ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CHCFG8_PSIZE   , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CHCFG8_PSIZE_0 ((uint16_t)0x0100)   /*!< Bit 0 */
+#define DMA_CHCFG8_PSIZE_1 ((uint16_t)0x0200)   /*!< Bit 1 */
+
+#define DMA_CHCFG8_MSIZE   ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CHCFG8_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CHCFG8_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CHCFG8_PRIOLVL   ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CHCFG8_PRIOLVL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CHCFG8_PRIOLVL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CHCFG8_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/******************  Bit definition for DMA_TXNUM1 register  ******************/
+#define DMA_TXNUM1_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TXNUM2 register  ******************/
+#define DMA_TXNUM2_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TXNUM3 register  ******************/
+#define DMA_TXNUM3_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TXNUM4 register  ******************/
+#define DMA_TXNUM4_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TXNUM5 register  ******************/
+#define DMA_TXNUM5_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TXNUM6 register  ******************/
+#define DMA_TXNUM6_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TXNUM7 register  ******************/
+#define DMA_TXNUM7_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_TXNUM8 register  ******************/
+#define DMA_TXNUM8_NDTX ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_PADDR1 register  *******************/
+#define DMA_PADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR2 register  *******************/
+#define DMA_PADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR3 register  *******************/
+#define DMA_PADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR4 register  *******************/
+#define DMA_PADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR5 register  *******************/
+#define DMA_PADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR6 register  *******************/
+#define DMA_PADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR7 register  *******************/
+#define DMA_PADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR8 register  *******************/
+#define DMA_PADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_MADDR1 register  *******************/
+#define DMA_MADDR1_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************  Bit definition for DMA_MADDR2 register  *******************/
+#define DMA_MADDR2_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************  Bit definition for DMA_MADDR3 register  *******************/
+#define DMA_MADDR3_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************  Bit definition for DMA_MADDR4 register  *******************/
+#define DMA_MADDR4_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************  Bit definition for DMA_MADDR5 register  *******************/
+#define DMA_MADDR5_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************  Bit definition for DMA_MADDR6 register  *******************/
+#define DMA_MADDR6_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************  Bit definition for DMA_MADDR7 register  *******************/
+#define DMA_MADDR7_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************  Bit definition for DMA_MADDR8 register  *******************/
+#define DMA_MADDR8_ADDR ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_STS register  ********************/
+#define ADC_STS_AWDG  ((uint8_t)0x01) /*!< Analog watchdog flag */
+#define ADC_STS_ENDC  ((uint8_t)0x02) /*!< End of conversion */
+#define ADC_STS_JENDC ((uint8_t)0x04) /*!< Injected channel end of conversion */
+#define ADC_STS_JSTR  ((uint8_t)0x08) /*!< Injected channel Start flag */
+#define ADC_STS_STR   ((uint8_t)0x10) /*!< Regular channel Start flag */
+#define ADC_STS_ENDCA  ((uint8_t)0x20) /*!< Regular channel any end flag */
+#define ADC_STS_JENDCA   ((uint8_t)0x40) /*!< Injected channel any end flag */
+
+
+/*******************  Bit definition for ADC_CTRL1 register  ********************/
+#define ADC_CTRL1_AWDGCH  ((uint32_t)0x0000001F) /*!< AWDG_CH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CTRL1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_CTRL1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_CTRL1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_CTRL1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_CTRL1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_CTRL1_ENDCIEN   ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
+#define ADC_CTRL1_AWDGIEN   ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
+#define ADC_CTRL1_JENDCIEN  ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
+#define ADC_CTRL1_SCANMD    ((uint32_t)0x00000100) /*!< Scan mode */
+#define ADC_CTRL1_AWDGSGLEN ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
+#define ADC_CTRL1_AUTOJC    ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
+#define ADC_CTRL1_DREGCH    ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
+#define ADC_CTRL1_DJCH      ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
+
+#define ADC_CTRL1_DCTU   ((uint32_t)0x0000E000) /*!< DISC_NUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CTRL1_DCTU_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define ADC_CTRL1_DCTU_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define ADC_CTRL1_DCTU_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define ADC_CTRL1_AWDGEJCH ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
+#define ADC_CTRL1_AWDGERCH ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+
+/*******************  Bit definition for ADC_CTRL2 register  ********************/
+#define ADC_CTRL2_ON    ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
+#define ADC_CTRL2_CTU   ((uint32_t)0x00000002) /*!< Continuous Conversion */
+#define ADC_CTRL2_ENCAL ((uint32_t)0x00000004) /*!< A/D Calibration */
+#define ADC_CTRL2_ENDMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
+#define ADC_CTRL2_ALIG  ((uint32_t)0x00000800) /*!< Data Alignment */
+
+#define ADC_CTRL2_EXTJSEL                                                                                              \
+    ((uint32_t)0x00007000) /*!< INJ_EXT_SEL[2:0] bits (External event select for injected group) */
+#define ADC_CTRL2_EXTJSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_CTRL2_EXTJSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_CTRL2_EXTJSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_CTRL2_EXTJTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
+
+#define ADC_CTRL2_EXTRSEL   ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CTRL2_EXTRSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define ADC_CTRL2_EXTRSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define ADC_CTRL2_EXTRSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+#define ADC_CTRL2_EXTRTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
+#define ADC_CTRL2_SWSTRJCH ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
+#define ADC_CTRL2_SWSTRRCH ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
+#define ADC_CTRL2_TEMPEN   ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
+
+/******************  Bit definition for ADC_SAMPT1 register  *******************/
+#define ADC_SAMPT1_SAMP10   ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SAMPT1_SAMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP11   ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SAMPT1_SAMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP12   ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SAMPT1_SAMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP13   ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SAMPT1_SAMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP14   ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SAMPT1_SAMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP15   ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SAMPT1_SAMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP16   ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SAMPT1_SAMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SAMPT1_SAMP17   ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SAMPT1_SAMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SAMPT1_SAMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SAMPT1_SAMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+/******************  Bit definition for ADC_SAMPT2 register  *******************/
+#define ADC_SAMPT2_SAMP0   ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SAMPT2_SAMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP1   ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SAMPT2_SAMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP2   ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SAMPT2_SAMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP3   ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SAMPT2_SAMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP4   ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SAMPT2_SAMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP5   ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SAMPT2_SAMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP6   ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SAMPT2_SAMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP7   ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SAMPT2_SAMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP8   ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SAMPT2_SAMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SAMPT2_SAMP9   ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SAMPT2_SAMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SAMPT2_SAMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SAMPT2_SAMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/******************  Bit definition for ADC_JOFFSET1 register  *******************/
+#define ADC_JOFFSET1_OFFSETJCH1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFFSET2 register  *******************/
+#define ADC_JOFFSET2_OFFSETJCH2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFFSET3 register  *******************/
+#define ADC_JOFFSET3_OFFSETJCH3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFFSET4 register  *******************/
+#define ADC_JOFFSET4_OFFSETJCH4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_WDGHIGH register  ********************/
+#define ADC_WDGHIGH_HTH ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_WDGLOW register  ********************/
+#define ADC_WDGLOW_LTH ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_RSEQ1 register  *******************/
+#define ADC_RSEQ1_SEQ13   ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_RSEQ1_SEQ14   ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_RSEQ1_SEQ15   ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_RSEQ1_SEQ16   ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_RSEQ1_SEQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_RSEQ1_SEQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_RSEQ1_SEQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_RSEQ1_SEQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_RSEQ1_SEQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_RSEQ1_LEN   ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
+#define ADC_RSEQ1_LEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_RSEQ1_LEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_RSEQ1_LEN_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_RSEQ1_LEN_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+/*******************  Bit definition for ADC_RSEQ2 register  *******************/
+#define ADC_RSEQ2_SEQ7   ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ8   ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ9   ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ10   ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ11   ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_RSEQ2_SEQ12   ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_RSEQ2_SEQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_RSEQ2_SEQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_RSEQ2_SEQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_RSEQ2_SEQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_RSEQ2_SEQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_RSEQ3 register  *******************/
+#define ADC_RSEQ3_SEQ1   ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ2   ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ3   ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ4   ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ5   ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_RSEQ3_SEQ6   ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_RSEQ3_SEQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_RSEQ3_SEQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_RSEQ3_SEQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_RSEQ3_SEQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_RSEQ3_SEQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_JSEQ register  *******************/
+#define ADC_JSEQ_JSEQ1   ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_JSEQ_JSEQ2   ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_JSEQ_JSEQ3   ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_JSEQ_JSEQ4   ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSEQ_JSEQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_JSEQ_JSEQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_JSEQ_JSEQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_JSEQ_JSEQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_JSEQ_JSEQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_JSEQ_JLEN   ((uint32_t)0x00300000) /*!< INJ_LEN[1:0] bits (Injected Sequence length) */
+#define ADC_JSEQ_JLEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_JSEQ_JLEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+/*******************  Bit definition for ADC_JDAT1 register  *******************/
+#define ADC_JDAT1_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDAT2 register  *******************/
+#define ADC_JDAT2_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDAT3 register  *******************/
+#define ADC_JDAT3_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDAT4 register  *******************/
+#define ADC_JDAT4_JDAT ((uint16_t)0xFFFF) /*!< Injected data */
+
+/********************  Bit definition for ADC_DAT register  ********************/
+#define ADC_DAT_DAT     ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+///********************  Bit definition for ADC_DIFSEL register  ********************/
+//#define ADC_DIFSEL_DIFSEL       ((uint32_t)0x000FFFFE) /*!< Differential data */
+//#define ADC_DIFSEL_DIFSEL_0     ((uint32_t)0x00000002) /*!< Differential_1 data */
+//#define ADC_DIFSEL_DIFSEL_1     ((uint32_t)0x00000004) /*!< Differential_2 data */
+//#define ADC_DIFSEL_DIFSEL_2     ((uint32_t)0x00000008) /*!< Differential_3 data */
+//#define ADC_DIFSEL_DIFSEL_3     ((uint32_t)0x00000010) /*!< Differential_4 data */
+//#define ADC_DIFSEL_DIFSEL_4     ((uint32_t)0x00000020) /*!< Differential_5 data */
+//#define ADC_DIFSEL_DIFSEL_5     ((uint32_t)0x00000040) /*!< Differential_6 data */
+//#define ADC_DIFSEL_DIFSEL_6     ((uint32_t)0x00000080) /*!< Differential_7 data */
+//#define ADC_DIFSEL_DIFSEL_7     ((uint32_t)0x00000100) /*!< Differential_8 data */
+//#define ADC_DIFSEL_DIFSEL_8     ((uint32_t)0x00000200) /*!< Differential_9 data */
+//#define ADC_DIFSEL_DIFSEL_9     ((uint32_t)0x00000400) /*!< Differential_10 data */
+//#define ADC_DIFSEL_DIFSEL_10     ((uint32_t)0x00000800) /*!< Differential_11 data */
+//#define ADC_DIFSEL_DIFSEL_11     ((uint32_t)0x00001000) /*!< Differential_12 data */
+//#define ADC_DIFSEL_DIFSEL_12     ((uint32_t)0x00002000) /*!< Differential_13 data */
+//#define ADC_DIFSEL_DIFSEL_13     ((uint32_t)0x00004000) /*!< Differential_14 data */
+//#define ADC_DIFSEL_DIFSEL_14     ((uint32_t)0x00008000) /*!< Differential_15 data */
+//#define ADC_DIFSEL_DIFSEL_15     ((uint32_t)0x00010000) /*!< Differential_16 data */
+//#define ADC_DIFSEL_DIFSEL_16     ((uint32_t)0x00020000) /*!< Differential_17 data */
+//#define ADC_DIFSEL_DIFSEL_17     ((uint32_t)0x00040000) /*!< Differential_18 data */
+//#define ADC_DIFSEL_DIFSEL_18     ((uint32_t)0x00080000) /*!< Differential_19 data */
+
+///********************  Bit definition for ADC_CALFACT register  ********************/
+//#define ADC_CALFACT_CALFACTS     ((uint32_t)0x0000007F) /*!< Calibration factors in single data */
+//#define ADC_CALFACT_CALFACTS_0   ((uint32_t)0x00000001) /*!< Calibration factors_0 in single data */
+//#define ADC_CALFACT_CALFACTS_1   ((uint32_t)0x00000002) /*!< Calibration factors_1 in single data */
+//#define ADC_CALFACT_CALFACTS_2   ((uint32_t)0x00000004) /*!< Calibration factors_2 in single data */
+//#define ADC_CALFACT_CALFACTS_3   ((uint32_t)0x00000008) /*!< Calibration factors_3 in single data */
+//#define ADC_CALFACT_CALFACTS_4   ((uint32_t)0x00000010) /*!< Calibration factors_4 in single data */
+//#define ADC_CALFACT_CALFACTS_5   ((uint32_t)0x00000020) /*!< Calibration factors_5 in single data */
+//#define ADC_CALFACT_CALFACTS_6   ((uint32_t)0x00000040) /*!< Calibration factors_6 in single data */
+
+//#define ADC_CALFACT_CALFACTD     ((uint32_t)0x007F0000) /*!< Calibration factors in differential data */
+//#define ADC_CALFACT_CALFACTD_0   ((uint32_t)0x00010000) /*!< Calibration factors_0 in differential data */
+//#define ADC_CALFACT_CALFACTD_1   ((uint32_t)0x00020000) /*!< Calibration factors_1 in differential data */
+//#define ADC_CALFACT_CALFACTD_2   ((uint32_t)0x00040000) /*!< Calibration factors_2 in differential data */
+//#define ADC_CALFACT_CALFACTD_3   ((uint32_t)0x00080000) /*!< Calibration factors_3 in differential data */
+//#define ADC_CALFACT_CALFACTD_4   ((uint32_t)0x00100000) /*!< Calibration factors_4 in differential data */
+//#define ADC_CALFACT_CALFACTD_5   ((uint32_t)0x00200000) /*!< Calibration factors_5 in differential data */
+//#define ADC_CALFACT_CALFACTD_6   ((uint32_t)0x00400000) /*!< Calibration factors_6 in differential data */
+
+///********************  Bit definition for ADC_CTRL3 register  ********************/
+//#define ADC_CTRL3_RES       ((uint32_t)0x00000003) /*!< Resolution data */
+//#define ADC_CTRL3_RES_0     ((uint32_t)0x00000001) /*!< Resolution_0 data */
+//#define ADC_CTRL3_RES_1     ((uint32_t)0x00000002) /*!< Resolution_1 data */
+
+//#define ADC_CTRL3_CALDIF     ((uint32_t)0x00000004) /*!< Differential mode for calibration enable */
+//#define ADC_CTRL3_CALALD     ((uint32_t)0x00000008) /*!< Differential mode for calibration auto reload enable */
+//#define ADC_CTRL3_CKMOD      ((uint32_t)0x00000010) /*!< Clock mode selection */
+//#define ADC_CTRL3_RDY        ((uint32_t)0x00000020) /*!< Ready flag */
+//#define ADC_CTRL3_PDRDY      ((uint32_t)0x00000040) /*!< Powerdown ready flag */
+//#define ADC_CTRL3_BPCAL      ((uint32_t)0x00000080) /*!< Bypass calibration */
+//#define ADC_CTRL3_ENDCAIEN      ((uint32_t)0x00000100) /*!< Interrupt enable for any regular channels */
+//#define ADC_CTRL3_JENDCAIEN      ((uint32_t)0x00000200) /*!< Interrupt enable for any injected channels */
+//#define ADC_CTRL3_DPWMOD         ((uint32_t)0x00000400) /*!< Deep Power Mode */
+//#define ADC_CTRL3_VBATMEN        ((uint32_t)0x00000800) /*!< Vbat monitor enable */
+
+///********************  Bit definition for ADC_SAMPT3 register  ********************/
+//#define ADC_SAMPT3_SAMP18   ((uint32_t)0x00000007) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+//#define ADC_SAMPT3_SAMP18_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+//#define ADC_SAMPT3_SAMP18_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+//#define ADC_SAMPT3_SAMP18_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+//#define ADC_SAMPT3_SAMPSEL  ((uint32_t)0x00000008) /*!< Sample time selection */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CTRL register  ********************/
+#define DAC_CTRL_CHEN ((uint32_t)0x00000001) /*!< DAC channel enable */
+#define DAC_CTRL_BEN  ((uint32_t)0x00000002) /*!< DAC channel output buffer enable */
+#define DAC_CTRL_TEN  ((uint32_t)0x00000004) /*!< DAC channel Trigger enable */
+
+#define DAC_CTRL_TSEL   ((uint32_t)0x00000038) /*!< TSEL[2:0] (DAC channel Trigger selection) */
+#define DAC_CTRL_TSEL_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CTRL_TSEL_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CTRL_TSEL_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CTRL_WEN   ((uint32_t)0x000000C0) /*!< WEN[1:0] (DAC channel noise/triangle wave generation enable) */
+#define DAC_CTRL_WEN_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CTRL_WEN_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CTRL_MASEL   ((uint32_t)0x00000F00) /*!< MASEL [3:0] (DAC channel Mask/Amplitude selector) */
+#define DAC_CTRL_MASEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CTRL_MASEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CTRL_MASEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CTRL_MASEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CTRL_DMAEN ((uint32_t)0x00001000) /*!< DAC channel DMA enable */
+
+
+
+/*****************  Bit definition for DAC_SOTTR register  ******************/
+#define DAC_SOTTR_TREN ((uint8_t)0x01) /*!< DAC channel software trigger */
+
+
+/*****************  Bit definition for DAC_DR12CH register  ******************/
+#define DAC_DR12CH_DACCHD ((uint16_t)0x0FFF) /*!< DAC channel 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DL12CH register  ******************/
+#define DAC_DL12CH_DACCHD ((uint16_t)0xFFF0) /*!< DAC channel 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DR8CH register  ******************/
+#define DAC_DR8CH_DACCHD ((uint8_t)0xFF) /*!< DAC channel 8-bit Right aligned data */
+
+
+
+
+/*******************  Bit definition for DAC_DATO register  *******************/
+#define DAC_DATO_DACCHDO ((uint16_t)0x0FFF) /*!< DAC channel data output */
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CTRL1 register  ********************/
+#define TIM_CTRL1_CNTEN ((uint32_t)0x00000001) /*!< Counter enable */
+#define TIM_CTRL1_UPDIS ((uint32_t)0x00000002) /*!< Update disable */
+#define TIM_CTRL1_UPRS  ((uint32_t)0x00000004) /*!< Update request source */
+#define TIM_CTRL1_ONEPM ((uint32_t)0x00000008) /*!< One pulse mode */
+#define TIM_CTRL1_DIR   ((uint32_t)0x00000010) /*!< Direction */
+
+#define TIM_CTRL1_CAMSEL   ((uint32_t)0x00000060) /*!< CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CTRL1_CAMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define TIM_CTRL1_CAMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+
+#define TIM_CTRL1_ARPEN ((uint32_t)0x00000080) /*!< Auto-reload preload enable */
+
+#define TIM_CTRL1_CLKD   ((uint32_t)0x00000300) /*!< CKD[1:0] bits (clock division) */
+#define TIM_CTRL1_CLKD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define TIM_CTRL1_CLKD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define TIM_CTRL1_IOMBKPEN ((uint32_t)0x00000400) /*!< Break_in selection from IOM/COMP */
+#define TIM_CTRL1_C1SEL    ((uint32_t)0x00000800) /*!< Channel 1 selection from IOM/COMP */
+#define TIM_CTRL1_C2SEL    ((uint32_t)0x00001000) /*!< Channel 2 selection from IOM/COMP */
+#define TIM_CTRL1_C3SEL    ((uint32_t)0x00002000) /*!< Channel 3 selection from IOM/COMP */
+#define TIM_CTRL1_C4SEL    ((uint32_t)0x00004000) /*!< Channel 4 selection from IOM/COMP */
+#define TIM_CTRL1_CLRSEL   ((uint32_t)0x00008000) /*!< OCxRef selection from ETR/COMP */
+
+#define TIM_CTRL1_LBKPEN ((uint32_t)0x00010000) /*!< LOCKUP as bkp Enable*/
+#define TIM_CTRL1_PBKPEN ((uint32_t)0x00020000) /*!< PVD as bkp Enable */
+
+/*******************  Bit definition for TIM_CTRL2 register  ********************/
+#define TIM_CTRL2_CCPCTL ((uint32_t)0x00000001) /*!< Capture/Compare Preloaded Control */
+#define TIM_CTRL2_CCUSEL ((uint32_t)0x00000004) /*!< Capture/Compare Control Update Selection */
+#define TIM_CTRL2_CCDSEL ((uint32_t)0x00000008) /*!< Capture/Compare DMA Selection */
+
+#define TIM_CTRL2_MMSEL   ((uint32_t)0x00000070) /*!< MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CTRL2_MMSEL_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define TIM_CTRL2_MMSEL_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define TIM_CTRL2_MMSEL_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define TIM_CTRL2_TI1SEL ((uint32_t)0x00000080) /*!< TI1 Selection */
+#define TIM_CTRL2_OI1    ((uint32_t)0x00000100) /*!< Output Idle state 1 (OC1 output) */
+#define TIM_CTRL2_OI1N   ((uint32_t)0x00000200) /*!< Output Idle state 1 (OC1N output) */
+#define TIM_CTRL2_OI2    ((uint32_t)0x00000400) /*!< Output Idle state 2 (OC2 output) */
+#define TIM_CTRL2_OI2N   ((uint32_t)0x00000800) /*!< Output Idle state 2 (OC2N output) */
+#define TIM_CTRL2_OI3    ((uint32_t)0x00001000) /*!< Output Idle state 3 (OC3 output) */
+#define TIM_CTRL2_OI3N   ((uint32_t)0x00002000) /*!< Output Idle state 3 (OC3N output) */
+#define TIM_CTRL2_OI4    ((uint32_t)0x00004000) /*!< Output Idle state 4 (OC4 output) */
+
+#define TIM_CTRL2_OI5 ((uint32_t)0x00010000) /*!< Output Idle state 5 (OC5 output) */
+#define TIM_CTRL2_OI6 ((uint32_t)0x00040000) /*!< Output Idle state 6 (OC6 output) */
+
+/*******************  Bit definition for TIM_SMCTRL register  *******************/
+#define TIM_SMCTRL_SMSEL   ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCTRL_SMSEL_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_SMCTRL_SMSEL_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_SMCTRL_SMSEL_2 ((uint16_t)0x0004) /*!< Bit 2 */
+
+#define TIM_SMCTRL_TSEL   ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */
+#define TIM_SMCTRL_TSEL_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_SMCTRL_TSEL_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_SMCTRL_TSEL_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_SMCTRL_MSMD ((uint16_t)0x0080) /*!< Master/slave mode */
+
+#define TIM_SMCTRL_EXTF   ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCTRL_EXTF_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_SMCTRL_EXTF_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_SMCTRL_EXTF_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_SMCTRL_EXTF_3 ((uint16_t)0x0800) /*!< Bit 3 */
+
+#define TIM_SMCTRL_EXTPS   ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCTRL_EXTPS_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_SMCTRL_EXTPS_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define TIM_SMCTRL_EXCEN ((uint16_t)0x4000) /*!< External clock enable */
+#define TIM_SMCTRL_EXTP  ((uint16_t)0x8000) /*!< External trigger polarity */
+
+/*******************  Bit definition for TIM_DINTEN register  *******************/
+#define TIM_DINTEN_UIEN   ((uint16_t)0x0001) /*!< Update interrupt enable */
+#define TIM_DINTEN_CC1IEN ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */
+#define TIM_DINTEN_CC2IEN ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */
+#define TIM_DINTEN_CC3IEN ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */
+#define TIM_DINTEN_CC4IEN ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */
+#define TIM_DINTEN_COMIEN ((uint16_t)0x0020) /*!< COM interrupt enable */
+#define TIM_DINTEN_TIEN   ((uint16_t)0x0040) /*!< Trigger interrupt enable */
+#define TIM_DINTEN_BIEN   ((uint16_t)0x0080) /*!< Break interrupt enable */
+#define TIM_DINTEN_UDEN   ((uint16_t)0x0100) /*!< Update DMA request enable */
+#define TIM_DINTEN_CC1DEN ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */
+#define TIM_DINTEN_CC2DEN ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */
+#define TIM_DINTEN_CC3DEN ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */
+#define TIM_DINTEN_CC4DEN ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */
+#define TIM_DINTEN_COMDEN ((uint16_t)0x2000) /*!< COM DMA request enable */
+#define TIM_DINTEN_TDEN   ((uint16_t)0x4000) /*!< Trigger DMA request enable */
+
+/********************  Bit definition for TIM_STS register  ********************/
+#define TIM_STS_UDITF  ((uint32_t)0x00000001) /*!< Update interrupt Flag */
+#define TIM_STS_CC1ITF ((uint32_t)0x00000002) /*!< Capture/Compare 1 interrupt Flag */
+#define TIM_STS_CC2ITF ((uint32_t)0x00000004) /*!< Capture/Compare 2 interrupt Flag */
+#define TIM_STS_CC3ITF ((uint32_t)0x00000008) /*!< Capture/Compare 3 interrupt Flag */
+#define TIM_STS_CC4ITF ((uint32_t)0x00000010) /*!< Capture/Compare 4 interrupt Flag */
+#define TIM_STS_COMITF ((uint32_t)0x00000020) /*!< COM interrupt Flag */
+#define TIM_STS_TITF   ((uint32_t)0x00000040) /*!< Trigger interrupt Flag */
+#define TIM_STS_BITF   ((uint32_t)0x00000080) /*!< Break interrupt Flag */
+#define TIM_STS_CC1OCF ((uint32_t)0x00000200) /*!< Capture/Compare 1 Overcapture Flag */
+#define TIM_STS_CC2OCF ((uint32_t)0x00000400) /*!< Capture/Compare 2 Overcapture Flag */
+#define TIM_STS_CC3OCF ((uint32_t)0x00000800) /*!< Capture/Compare 3 Overcapture Flag */
+#define TIM_STS_CC4OCF ((uint32_t)0x00001000) /*!< Capture/Compare 4 Overcapture Flag */
+
+#define TIM_STS_CC5ITF ((uint32_t)0x00010000) /*!< Capture/Compare 5 interrupt Flag */
+#define TIM_STS_CC6ITF ((uint32_t)0x00020000) /*!< Capture/Compare 6 interrupt Flag */
+
+/*******************  Bit definition for TIM_EVTGEN register  ********************/
+#define TIM_EVTGEN_UDGN   ((uint8_t)0x01) /*!< Update Generation */
+#define TIM_EVTGEN_CC1GN  ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */
+#define TIM_EVTGEN_CC2GN  ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */
+#define TIM_EVTGEN_CC3GN  ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */
+#define TIM_EVTGEN_CC4GN  ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */
+#define TIM_EVTGEN_CCUDGN ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */
+#define TIM_EVTGEN_TGN    ((uint8_t)0x40) /*!< Trigger Generation */
+#define TIM_EVTGEN_BGN    ((uint8_t)0x80) /*!< Break Generation */
+
+/******************  Bit definition for TIM_CCMOD1 register  *******************/
+#define TIM_CCMOD1_CC1SEL   ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMOD1_CC1SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMOD1_CC1SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */
+
+#define TIM_CCMOD1_OC1FEN ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */
+#define TIM_CCMOD1_OC1PEN ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */
+
+#define TIM_CCMOD1_OC1M   ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMOD1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMOD1_OC1CEN ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */
+
+#define TIM_CCMOD1_CC2SEL   ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMOD1_CC2SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMOD1_CC2SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_CCMOD1_OC2FEN ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */
+#define TIM_CCMOD1_OC2PEN ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */
+
+#define TIM_CCMOD1_OC2M   ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMOD1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMOD1_OC2CEN ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMOD1_IC1PSC   ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMOD1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMOD1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
+
+#define TIM_CCMOD1_IC1F   ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMOD1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMOD1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define TIM_CCMOD1_IC2PSC   ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMOD1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMOD1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define TIM_CCMOD1_IC2F   ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMOD1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMOD1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */
+
+/******************  Bit definition for TIM_CCMOD2 register  *******************/
+#define TIM_CCMOD2_CC3SEL   ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMOD2_CC3SEL_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMOD2_CC3SEL_1 ((uint16_t)0x0002) /*!< Bit 1 */
+
+#define TIM_CCMOD2_OC3FEN ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */
+#define TIM_CCMOD2_OC3PEN ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */
+
+#define TIM_CCMOD2_OC3MD   ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMOD2_OC3MD_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD2_OC3MD_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD2_OC3MD_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMOD2_OC3CEN ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */
+
+#define TIM_CCMOD2_CC4SEL   ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMOD2_CC4SEL_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMOD2_CC4SEL_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_CCMOD2_OC4FEN ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */
+#define TIM_CCMOD2_OC4PEN ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */
+
+#define TIM_CCMOD2_OC4MD   ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMOD2_OC4MD_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD2_OC4MD_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD2_OC4MD_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMOD2_OC4CEN ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMOD2_IC3PSC   ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMOD2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMOD2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
+
+#define TIM_CCMOD2_IC3F   ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMOD2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMOD2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define TIM_CCMOD2_IC4PSC   ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMOD2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMOD2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define TIM_CCMOD2_IC4F   ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMOD2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMOD2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */
+
+/******************  Bit definition for TIM_CCMOD3 register  *******************/
+#define TIM_CCMOD3_OC5FEN ((uint16_t)0x0004) /*!< Output Compare 5 Fast enable */
+#define TIM_CCMOD3_OC5PEN ((uint16_t)0x0008) /*!< Output Compare 5 Preload enable */
+
+#define TIM_CCMOD3_OC5MD   ((uint16_t)0x0070) /*!< OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMOD3_OC5MD_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMOD3_OC5MD_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMOD3_OC5MD_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMOD3_OC5CEN ((uint16_t)0x0080) /*!< Output Compare 5Clear Enable */
+
+#define TIM_CCMOD3_OC6FEN ((uint16_t)0x0400) /*!< Output Compare 6 Fast enable */
+#define TIM_CCMOD3_OC6PEN ((uint16_t)0x0800) /*!< Output Compare 6 Preload enable */
+
+#define TIM_CCMOD3_OC6MD   ((uint16_t)0x7000) /*!< OC6M[2:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMOD3_OC6MD_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMOD3_OC6MD_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMOD3_OC6MD_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMOD3_OC6CEN ((uint16_t)0x8000) /*!< Output Compare 6 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+/*******************  Bit definition for TIM_CCEN register  *******************/
+#define TIM_CCEN_CC1EN  ((uint32_t)0x00000001) /*!< Capture/Compare 1 output enable */
+#define TIM_CCEN_CC1P   ((uint32_t)0x00000002) /*!< Capture/Compare 1 output Polarity */
+#define TIM_CCEN_CC1NEN ((uint32_t)0x00000004) /*!< Capture/Compare 1 Complementary output enable */
+#define TIM_CCEN_CC1NP  ((uint32_t)0x00000008) /*!< Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCEN_CC2EN  ((uint32_t)0x00000010) /*!< Capture/Compare 2 output enable */
+#define TIM_CCEN_CC2P   ((uint32_t)0x00000020) /*!< Capture/Compare 2 output Polarity */
+#define TIM_CCEN_CC2NEN ((uint32_t)0x00000040) /*!< Capture/Compare 2 Complementary output enable */
+#define TIM_CCEN_CC2NP  ((uint32_t)0x00000080) /*!< Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCEN_CC3EN  ((uint32_t)0x00000100) /*!< Capture/Compare 3 output enable */
+#define TIM_CCEN_CC3P   ((uint32_t)0x00000200) /*!< Capture/Compare 3 output Polarity */
+#define TIM_CCEN_CC3NEN ((uint32_t)0x00000400) /*!< Capture/Compare 3 Complementary output enable */
+#define TIM_CCEN_CC3NP  ((uint32_t)0x00000800) /*!< Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCEN_CC4EN  ((uint32_t)0x00001000) /*!< Capture/Compare 4 output enable */
+#define TIM_CCEN_CC4P   ((uint32_t)0x00002000) /*!< Capture/Compare 4 output Polarity */
+
+#define TIM_CCEN_CC5EN ((uint32_t)0x00010000) /*!< Capture/Compare 5 output enable */
+#define TIM_CCEN_CC5P  ((uint32_t)0x00020000) /*!< Capture/Compare 5 output Polarity */
+#define TIM_CCEN_CC6EN ((uint32_t)0x00100000) /*!< Capture/Compare 6 output enable */
+#define TIM_CCEN_CC6P  ((uint32_t)0x00200000) /*!< Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */
+
+/*******************  Bit definition for TIM_AR register  ********************/
+#define TIM_AR_AR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */
+
+/*******************  Bit definition for TIM_REPCNT register  ********************/
+#define TIM_REPCNT_REPCNT ((uint8_t)0xFF) /*!< Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCDAT1 register  *******************/
+#define TIM_CCDAT1_CCDAT1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCDAT2 register  *******************/
+#define TIM_CCDAT2_CCDAT2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCDAT3 register  *******************/
+#define TIM_CCDAT3_CCDAT3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCDAT4 register  *******************/
+#define TIM_CCDAT4_CCDAT4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCDAT5 register  *******************/
+#define TIM_CCDAT5_CCDAT5 ((uint16_t)0xFFFF) /*!< Capture/Compare 5 Value */
+
+/*******************  Bit definition for TIM_CCDAT6 register  *******************/
+#define TIM_CCDAT6_CCDAT6 ((uint16_t)0xFFFF) /*!< Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BKDT register  *******************/
+#define TIM_BKDT_DTGN   ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BKDT_DTGN_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_BKDT_DTGN_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_BKDT_DTGN_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_BKDT_DTGN_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_BKDT_DTGN_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define TIM_BKDT_DTGN_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define TIM_BKDT_DTGN_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define TIM_BKDT_DTGN_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define TIM_BKDT_LCKCFG   ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BKDT_LCKCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_BKDT_LCKCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_BKDT_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */
+#define TIM_BKDT_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */
+#define TIM_BKDT_BKEN ((uint16_t)0x1000) /*!< Break enable */
+#define TIM_BKDT_BKP  ((uint16_t)0x2000) /*!< Break Polarity */
+#define TIM_BKDT_AOEN ((uint16_t)0x4000) /*!< Automatic Output enable */
+#define TIM_BKDT_MOEN ((uint16_t)0x8000) /*!< Main Output enable */
+
+/*******************  Bit definition for TIM_DCTRL register  ********************/
+#define TIM_DCTRL_DBADDR   ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCTRL_DBADDR_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_DCTRL_DBADDR_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_DCTRL_DBADDR_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_DCTRL_DBADDR_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_DCTRL_DBADDR_4 ((uint16_t)0x0010) /*!< Bit 4 */
+
+#define TIM_DCTRL_DBLEN   ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCTRL_DBLEN_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_DCTRL_DBLEN_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_DCTRL_DBLEN_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_DCTRL_DBLEN_3 ((uint16_t)0x0800) /*!< Bit 3 */
+#define TIM_DCTRL_DBLEN_4 ((uint16_t)0x1000) /*!< Bit 4 */
+
+/*******************  Bit definition for TIM_DADDR register  *******************/
+#define TIM_DADDR_BURST ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_INTSTS register  *******************/
+#define LPTIM_INTSTS_CMPM                       ((uint32_t)0x00000001)       /*!< Compare match */
+#define LPTIM_INTSTS_ARRM                      ((uint32_t)0x00000002)       /*!< Autoreload match */
+#define LPTIM_INTSTS_EXTRIG                   ((uint32_t)0x00000004)       /*!< External trigger edge event */
+#define LPTIM_INTSTS_CMPUPD                      ((uint32_t)0x00000008)       /*!< Compare register update OK */
+#define LPTIM_INTSTS_ARRUPD                      ((uint32_t)0x00000010)       /*!< Autoreload register update OK */
+#define LPTIM_INTSTS_UP                         ((uint32_t)0x00000020)       /*!< Counter direction change down to up */
+#define LPTIM_INTSTS_DOWN                       ((uint32_t)0x00000040)       /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_INTCLR register  *******************/
+#define LPTIM_INTCLR_CMPMCF                     ((uint32_t)0x00000001)       /*!< Compare match Clear Flag */
+#define LPTIM_INTCLR_ARRMCF                     ((uint32_t)0x00000002)       /*!< Autoreload match Clear Flag */
+#define LPTIM_INTCLR_EXTRIGCF                  ((uint32_t)0x00000004)       /*!< External trigger edge event Clear Flag */
+#define LPTIM_INTCLR_CMPUPDCF                    ((uint32_t)0x00000008)       /*!< Compare register update OK Clear Flag */
+#define LPTIM_INTCLR_ARRUPDCF                    ((uint32_t)0x00000010)       /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_INTCLR_UPCF                       ((uint32_t)0x00000020)       /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_INTCLR_DOWNCF                     ((uint32_t)0x00000040)       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_INTEN register ********************/
+#define LPTIM_INTEN_CMPMIE                     ((uint32_t)0x00000001)       /*!< Compare match Interrupt Enable */
+#define LPTIM_INTEN_ARRMIE                    ((uint32_t)0x00000002)       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_INTEN_EXTRIGIE                  ((uint32_t)0x00000004)       /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_INTEN_CMPUPDIE                   ((uint32_t)0x00000008)       /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_INTEN_ARRUPDIE                   ((uint32_t)0x00000010)       /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_INTEN_UPIE                       ((uint32_t)0x00000020)       /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_INTEN_DOWNIE                    ((uint32_t)0x00000040)       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFG register *******************/
+#define LPTIM_CFG_CLKSEL                     ((uint32_t)0x00000001)       /*!< Clock selector */
+
+#define LPTIM_CFG_CLKPOL                     ((uint32_t)0x00000006)       /*!< CLKP[1:0] bits (Clock polarity) */
+#define LPTIM_CFG_CLKPOL_0                   ((uint32_t)0x00000002)       /*!< 0x00000002 */
+#define LPTIM_CFG_CLKPOL_1                   ((uint32_t)0x00000004)       /*!< 0x00000004 */
+
+#define LPTIM_CFG_CLKFLT                     ((uint32_t)0x00000018)       /*!< CFGDFFEXT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFG_CLKFLT_0                   ((uint32_t)0x00000008)       /*!< 0x00000008 */
+#define LPTIM_CFG_CLKFLT_1                   ((uint32_t)0x00000010)       /*!< 0x00000010 */
+
+#define LPTIM_CFG_TRIGFLT                    ((uint32_t)0x000000C0)       /*!< CFGDFFTRG[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFG_TRIGFLT_0                  ((uint32_t)0x00000040)       /*!< 0x00000040 */
+#define LPTIM_CFG_TRIGFLT_1                  ((uint32_t)0x00000080)       /*!< 0x00000080 */
+
+#define LPTIM_CFG_CLKPRE                     ((uint32_t)0x00000E00)       /*!< CLKPRE[2:0] bits (Clock prescaler) */
+#define LPTIM_CFG_CLKPRE_0                   ((uint32_t)0x00000200)       /*!< 0x00000200 */
+#define LPTIM_CFG_CLKPRE_1                   ((uint32_t)0x00000400)       /*!< 0x00000400 */
+#define LPTIM_CFG_CLKPRE_2                   ((uint32_t)0x00000800)       /*!< 0x00000800 */
+
+#define LPTIM_CFG_TRGSEL                   ((uint32_t)0x0000E000)       /*!< TRGS[2:0]] bits (Trigger selector) */
+#define LPTIM_CFG_TRGSEL_0                 ((uint32_t)0x00002000)       /*!< 0x00002000 */
+#define LPTIM_CFG_TRGSEL_1                 ((uint32_t)0x00004000)       /*!< 0x00004000 */
+#define LPTIM_CFG_TRGSEL_2                 ((uint32_t)0x00008000)       /*!< 0x00008000 */
+
+#define LPTIM_CFG_TRGEN                    ((uint32_t)0x00060000)       /*!< TRGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFG_TRGEN_0                  ((uint32_t)0x00020000)       /*!< 0x00020000 */
+#define LPTIM_CFG_TRGEN_1                  ((uint32_t)0x00040000)       /*!< 0x00040000 */
+
+#define LPTIM_CFG_TIMOUTEN                  ((uint32_t)0x00080000)       /*!< Timout enable */
+#define LPTIM_CFG_WAVE                      ((uint32_t)0x00100000)       /*!< Waveform shape */
+#define LPTIM_CFG_WAVEPOL                   ((uint32_t)0x00200000)       /*!< Waveform shape polarity */
+#define LPTIM_CFG_RELOAD                    ((uint32_t)0x00400000)       /*!< Reg update mode */
+#define LPTIM_CFG_CNTMEN                    ((uint32_t)0x00800000)       /*!< Counter mode enable */
+#define LPTIM_CFG_ENC                       ((uint32_t)0x01000000)       /*!< Encoder mode enable */
+#define LPTIM_CFG_NENC                      ((uint32_t)0x02000000)       /*!< NONEncoder mode enable */
+/******************  Bit definition for LPTIM_CTRL register  ********************/
+#define LPTIM_CTRL_LPTIMEN                      ((uint32_t)0x000000001)      /*!< LPTIMer enable */
+#define LPTIM_CTRL_SNGMST                       ((uint32_t)0x000000002)      /*!< Timer start in single mode */
+#define LPTIM_CTRL_TSTCM                        ((uint32_t)0x000000004)      /*!< Timer start in continuous mode */
+
+/******************  Bit definition for LPTIM_CMPT register  *******************/
+#define LPTIM_COMP_CMPVAL                          ((uint16_t)0xFFFF)           /*!< Compare register */
+
+/******************  Bit definition for LPTIM_AUTRLD register  *******************/
+#define LPTIM_ARR_ARRVAL                     ((uint16_t)0xFFFF)           /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNTVAL                        ((uint16_t)0xFFFF)           /*!< Counter register */
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TSH register  *******************/
+#define RTC_TSH_APM   ((uint32_t)0x00400000)
+#define RTC_TSH_HOT   ((uint32_t)0x00300000)
+#define RTC_TSH_HOT_0 ((uint32_t)0x00100000)
+#define RTC_TSH_HOT_1 ((uint32_t)0x00200000)
+#define RTC_TSH_HOU   ((uint32_t)0x000F0000)
+#define RTC_TSH_HOU_0 ((uint32_t)0x00010000)
+#define RTC_TSH_HOU_1 ((uint32_t)0x00020000)
+#define RTC_TSH_HOU_2 ((uint32_t)0x00040000)
+#define RTC_TSH_HOU_3 ((uint32_t)0x00080000)
+#define RTC_TSH_MIT   ((uint32_t)0x00007000)
+#define RTC_TSH_MIT_0 ((uint32_t)0x00001000)
+#define RTC_TSH_MIT_1 ((uint32_t)0x00002000)
+#define RTC_TSH_MIT_2 ((uint32_t)0x00004000)
+#define RTC_TSH_MIU   ((uint32_t)0x00000F00)
+#define RTC_TSH_MIU_0 ((uint32_t)0x00000100)
+#define RTC_TSH_MIU_1 ((uint32_t)0x00000200)
+#define RTC_TSH_MIU_2 ((uint32_t)0x00000400)
+#define RTC_TSH_MIU_3 ((uint32_t)0x00000800)
+#define RTC_TSH_SCT   ((uint32_t)0x00000070)
+#define RTC_TSH_SCT_0 ((uint32_t)0x00000010)
+#define RTC_TSH_SCT_1 ((uint32_t)0x00000020)
+#define RTC_TSH_SCT_2 ((uint32_t)0x00000040)
+#define RTC_TSH_SCU   ((uint32_t)0x0000000F)
+#define RTC_TSH_SCU_0 ((uint32_t)0x00000001)
+#define RTC_TSH_SCU_1 ((uint32_t)0x00000002)
+#define RTC_TSH_SCU_2 ((uint32_t)0x00000004)
+#define RTC_TSH_SCU_3 ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_DATE register  *******************/
+#define RTC_DATE_YRT   ((uint32_t)0x00F00000)
+#define RTC_DATE_YRT_0 ((uint32_t)0x00100000)
+#define RTC_DATE_YRT_1 ((uint32_t)0x00200000)
+#define RTC_DATE_YRT_2 ((uint32_t)0x00400000)
+#define RTC_DATE_YRT_3 ((uint32_t)0x00800000)
+#define RTC_DATE_YRU   ((uint32_t)0x000F0000)
+#define RTC_DATE_YRU_0 ((uint32_t)0x00010000)
+#define RTC_DATE_YRU_1 ((uint32_t)0x00020000)
+#define RTC_DATE_YRU_2 ((uint32_t)0x00040000)
+#define RTC_DATE_YRU_3 ((uint32_t)0x00080000)
+#define RTC_DATE_WDU   ((uint32_t)0x0000E000)
+#define RTC_DATE_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DATE_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DATE_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DATE_MOT   ((uint32_t)0x00001000)
+#define RTC_DATE_MOU   ((uint32_t)0x00000F00)
+#define RTC_DATE_MOU_0 ((uint32_t)0x00000100)
+#define RTC_DATE_MOU_1 ((uint32_t)0x00000200)
+#define RTC_DATE_MOU_2 ((uint32_t)0x00000400)
+#define RTC_DATE_MOU_3 ((uint32_t)0x00000800)
+#define RTC_DATE_DAT   ((uint32_t)0x00000030)
+#define RTC_DATE_DAT_0 ((uint32_t)0x00000010)
+#define RTC_DATE_DAT_1 ((uint32_t)0x00000020)
+#define RTC_DATE_DAU   ((uint32_t)0x0000000F)
+#define RTC_DATE_DAU_0 ((uint32_t)0x00000001)
+#define RTC_DATE_DAU_1 ((uint32_t)0x00000002)
+#define RTC_DATE_DAU_2 ((uint32_t)0x00000004)
+#define RTC_DATE_DAU_3 ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_CTRL register  *******************/
+#define RTC_CTRL_COEN     ((uint32_t)0x00800000)
+#define RTC_CTRL_OUTSEL   ((uint32_t)0x00600000)
+#define RTC_CTRL_OUTSEL_0 ((uint32_t)0x00200000)
+#define RTC_CTRL_OUTSEL_1 ((uint32_t)0x00400000)
+#define RTC_CTRL_OPOL     ((uint32_t)0x00100000)
+#define RTC_CTRL_CALOSEL  ((uint32_t)0x00080000)
+#define RTC_CTRL_BAKP     ((uint32_t)0x00040000)
+#define RTC_CTRL_SU1H     ((uint32_t)0x00020000)
+#define RTC_CTRL_AD1H     ((uint32_t)0x00010000)
+#define RTC_CTRL_TSIEN    ((uint32_t)0x00008000)
+#define RTC_CTRL_WTIEN    ((uint32_t)0x00004000)
+#define RTC_CTRL_ALBIEN   ((uint32_t)0x00002000)
+#define RTC_CTRL_ALAIEN   ((uint32_t)0x00001000)
+#define RTC_CTRL_TSEN     ((uint32_t)0x00000800)
+#define RTC_CTRL_WTEN     ((uint32_t)0x00000400)
+#define RTC_CTRL_ALBEN    ((uint32_t)0x00000200)
+#define RTC_CTRL_ALAEN    ((uint32_t)0x00000100)
+
+#define RTC_CTRL_HFMT      ((uint32_t)0x00000040)
+#define RTC_CTRL_BYPS      ((uint32_t)0x00000020)
+#define RTC_CTRL_REFCLKEN  ((uint32_t)0x00000010)
+#define RTC_CTRL_TEDGE     ((uint32_t)0x00000008)
+#define RTC_CTRL_WKUPSEL   ((uint32_t)0x00000007)
+#define RTC_CTRL_WKUPSEL_0 ((uint32_t)0x00000001)
+#define RTC_CTRL_WKUPSEL_1 ((uint32_t)0x00000002)
+#define RTC_CTRL_WKUPSEL_2 ((uint32_t)0x00000004)
+
+/********************  Bits definition for RTC_INITSTS register  ******************/
+#define RTC_INITSTS_RECPF  ((uint32_t)0x00010000)
+#define RTC_INITSTS_TAM3F  ((uint32_t)0x00008000)
+#define RTC_INITSTS_TAM2F  ((uint32_t)0x00004000)
+#define RTC_INITSTS_TAM1F  ((uint32_t)0x00002000)
+#define RTC_INITSTS_TISOVF ((uint32_t)0x00001000)
+#define RTC_INITSTS_TISF   ((uint32_t)0x00000800)
+#define RTC_INITSTS_WTF    ((uint32_t)0x00000400)
+#define RTC_INITSTS_ALBF   ((uint32_t)0x00000200)
+#define RTC_INITSTS_ALAF   ((uint32_t)0x00000100)
+#define RTC_INITSTS_INITM  ((uint32_t)0x00000080)
+#define RTC_INITSTS_INITF  ((uint32_t)0x00000040)
+#define RTC_INITSTS_RSYF   ((uint32_t)0x00000020)
+#define RTC_INITSTS_INITSF ((uint32_t)0x00000010)
+#define RTC_INITSTS_SHOPF  ((uint32_t)0x00000008)
+#define RTC_INITSTS_WTWF   ((uint32_t)0x00000004)
+#define RTC_INITSTS_ALBWF  ((uint32_t)0x00000002)
+#define RTC_INITSTS_ALAWF  ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRE register  *****************/
+#define RTC_PRE_DIVA ((uint32_t)0x007F0000)
+#define RTC_PRE_DIVS ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WKUPT register  *****************/
+#define RTC_WKUPT_WKUPT ((uint32_t)0x0000FFFF)
+
+
+/********************  Bits definition for RTC_ALARMA register  ***************/
+#define RTC_ALARMA_MASK4  ((uint32_t)0x80000000)
+#define RTC_ALARMA_WKDSEL ((uint32_t)0x40000000)
+#define RTC_ALARMA_DTT    ((uint32_t)0x30000000)
+#define RTC_ALARMA_DTT_0  ((uint32_t)0x10000000)
+#define RTC_ALARMA_DTT_1  ((uint32_t)0x20000000)
+#define RTC_ALARMA_DTU    ((uint32_t)0x0F000000)
+#define RTC_ALARMA_DTU_0  ((uint32_t)0x01000000)
+#define RTC_ALARMA_DTU_1  ((uint32_t)0x02000000)
+#define RTC_ALARMA_DTU_2  ((uint32_t)0x04000000)
+#define RTC_ALARMA_DTU_3  ((uint32_t)0x08000000)
+#define RTC_ALARMA_MASK3  ((uint32_t)0x00800000)
+#define RTC_ALARMA_APM    ((uint32_t)0x00400000)
+#define RTC_ALARMA_HOT    ((uint32_t)0x00300000)
+#define RTC_ALARMA_HOT_0  ((uint32_t)0x00100000)
+#define RTC_ALARMA_HOT_1  ((uint32_t)0x00200000)
+#define RTC_ALARMA_HOU    ((uint32_t)0x000F0000)
+#define RTC_ALARMA_HOU_0  ((uint32_t)0x00010000)
+#define RTC_ALARMA_HOU_1  ((uint32_t)0x00020000)
+#define RTC_ALARMA_HOU_2  ((uint32_t)0x00040000)
+#define RTC_ALARMA_HOU_3  ((uint32_t)0x00080000)
+#define RTC_ALARMA_MASK2  ((uint32_t)0x00008000)
+#define RTC_ALARMA_MIT    ((uint32_t)0x00007000)
+#define RTC_ALARMA_MIT_0  ((uint32_t)0x00001000)
+#define RTC_ALARMA_MIT_1  ((uint32_t)0x00002000)
+#define RTC_ALARMA_MIT_2  ((uint32_t)0x00004000)
+#define RTC_ALARMA_MIU    ((uint32_t)0x00000F00)
+#define RTC_ALARMA_MIU_0  ((uint32_t)0x00000100)
+#define RTC_ALARMA_MIU_1  ((uint32_t)0x00000200)
+#define RTC_ALARMA_MIU_2  ((uint32_t)0x00000400)
+#define RTC_ALARMA_MIU_3  ((uint32_t)0x00000800)
+#define RTC_ALARMA_MASK1  ((uint32_t)0x00000080)
+#define RTC_ALARMA_SET    ((uint32_t)0x00000070)
+#define RTC_ALARMA_SET_0  ((uint32_t)0x00000010)
+#define RTC_ALARMA_SET_1  ((uint32_t)0x00000020)
+#define RTC_ALARMA_SET_2  ((uint32_t)0x00000040)
+#define RTC_ALARMA_SEU    ((uint32_t)0x0000000F)
+#define RTC_ALARMA_SEU_0  ((uint32_t)0x00000001)
+#define RTC_ALARMA_SEU_1  ((uint32_t)0x00000002)
+#define RTC_ALARMA_SEU_2  ((uint32_t)0x00000004)
+#define RTC_ALARMA_SEU_3  ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_ALARMB register  ***************/
+#define RTC_ALARMB_MASK4  ((uint32_t)0x80000000)
+#define RTC_ALARMB_WKDSEL ((uint32_t)0x40000000)
+#define RTC_ALARMB_DTT    ((uint32_t)0x30000000)
+#define RTC_ALARMB_DTT_0  ((uint32_t)0x10000000)
+#define RTC_ALARMB_DTT_1  ((uint32_t)0x20000000)
+#define RTC_ALARMB_DTU    ((uint32_t)0x0F000000)
+#define RTC_ALARMB_DTU_0  ((uint32_t)0x01000000)
+#define RTC_ALARMB_DTU_1  ((uint32_t)0x02000000)
+#define RTC_ALARMB_DTU_2  ((uint32_t)0x04000000)
+#define RTC_ALARMB_DTU_3  ((uint32_t)0x08000000)
+#define RTC_ALARMB_MASK3  ((uint32_t)0x00800000)
+#define RTC_ALARMB_APM    ((uint32_t)0x00400000)
+#define RTC_ALARMB_HOT    ((uint32_t)0x00300000)
+#define RTC_ALARMB_HOT_0  ((uint32_t)0x00100000)
+#define RTC_ALARMB_HOT_1  ((uint32_t)0x00200000)
+#define RTC_ALARMB_HOU    ((uint32_t)0x000F0000)
+#define RTC_ALARMB_HOU_0  ((uint32_t)0x00010000)
+#define RTC_ALARMB_HOU_1  ((uint32_t)0x00020000)
+#define RTC_ALARMB_HOU_2  ((uint32_t)0x00040000)
+#define RTC_ALARMB_HOU_3  ((uint32_t)0x00080000)
+#define RTC_ALARMB_MASK2  ((uint32_t)0x00008000)
+#define RTC_ALARMB_MIT    ((uint32_t)0x00007000)
+#define RTC_ALARMB_MIT_0  ((uint32_t)0x00001000)
+#define RTC_ALARMB_MIT_1  ((uint32_t)0x00002000)
+#define RTC_ALARMB_MIT_2  ((uint32_t)0x00004000)
+#define RTC_ALARMB_MIU    ((uint32_t)0x00000F00)
+#define RTC_ALARMB_MIU_0  ((uint32_t)0x00000100)
+#define RTC_ALARMB_MIU_1  ((uint32_t)0x00000200)
+#define RTC_ALARMB_MIU_2  ((uint32_t)0x00000400)
+#define RTC_ALARMB_MIU_3  ((uint32_t)0x00000800)
+#define RTC_ALARMB_MASK1  ((uint32_t)0x00000080)
+#define RTC_ALARMB_SET    ((uint32_t)0x00000070)
+#define RTC_ALARMB_SET_0  ((uint32_t)0x00000010)
+#define RTC_ALARMB_SET_1  ((uint32_t)0x00000020)
+#define RTC_ALARMB_SET_2  ((uint32_t)0x00000040)
+#define RTC_ALARMB_SEU    ((uint32_t)0x0000000F)
+#define RTC_ALARMB_SEU_0  ((uint32_t)0x00000001)
+#define RTC_ALARMB_SEU_1  ((uint32_t)0x00000002)
+#define RTC_ALARMB_SEU_2  ((uint32_t)0x00000004)
+#define RTC_ALARMB_SEU_3  ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WRP register  ******************/
+#define RTC_WRP_PKEY ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SUBS register  ******************/
+#define RTC_SUBS_SS ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SCTRL register  ***************/
+#define RTC_SCTRL_SUBF ((uint32_t)0x00007FFF)
+#define RTC_SCTRL_AD1S  ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TST register  *****************/
+#define RTC_TST_APM   ((uint32_t)0x00400000)
+#define RTC_TST_HOT   ((uint32_t)0x00300000)
+#define RTC_TST_HOT_0 ((uint32_t)0x00100000)
+#define RTC_TST_HOT_1 ((uint32_t)0x00200000)
+#define RTC_TST_HOU   ((uint32_t)0x000F0000)
+#define RTC_TST_HOU_0 ((uint32_t)0x00010000)
+#define RTC_TST_HOU_1 ((uint32_t)0x00020000)
+#define RTC_TST_HOU_2 ((uint32_t)0x00040000)
+#define RTC_TST_HOU_3 ((uint32_t)0x00080000)
+#define RTC_TST_MIT   ((uint32_t)0x00007000)
+#define RTC_TST_MIT_0 ((uint32_t)0x00001000)
+#define RTC_TST_MIT_1 ((uint32_t)0x00002000)
+#define RTC_TST_MIT_2 ((uint32_t)0x00004000)
+#define RTC_TST_MIU   ((uint32_t)0x00000F00)
+#define RTC_TST_MIU_0 ((uint32_t)0x00000100)
+#define RTC_TST_MIU_1 ((uint32_t)0x00000200)
+#define RTC_TST_MIU_2 ((uint32_t)0x00000400)
+#define RTC_TST_MIU_3 ((uint32_t)0x00000800)
+#define RTC_TST_SET   ((uint32_t)0x00000070)
+#define RTC_TST_SET_0 ((uint32_t)0x00000010)
+#define RTC_TST_SET_1 ((uint32_t)0x00000020)
+#define RTC_TST_SET_2 ((uint32_t)0x00000040)
+#define RTC_TST_SEU   ((uint32_t)0x0000000F)
+#define RTC_TST_SEU_0 ((uint32_t)0x00000001)
+#define RTC_TST_SEU_1 ((uint32_t)0x00000002)
+#define RTC_TST_SEU_2 ((uint32_t)0x00000004)
+#define RTC_TST_SEU_3 ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSD register  *****************/
+#define RTC_TSD_YRT   ((uint32_t)0x00F00000)
+#define RTC_TSD_YRT_0 ((uint32_t)0x00100000)
+#define RTC_TSD_YRT_1 ((uint32_t)0x00200000)
+#define RTC_TSD_YRT_2 ((uint32_t)0x00400000)
+#define RTC_TSD_YRT_3 ((uint32_t)0x00800000)
+#define RTC_TSD_YRU   ((uint32_t)0x000F0000)
+#define RTC_TSD_YRU_0 ((uint32_t)0x00010000)
+#define RTC_TSD_YRU_1 ((uint32_t)0x00020000)
+#define RTC_TSD_YRU_2 ((uint32_t)0x00040000)
+#define RTC_TSD_YRU_3 ((uint32_t)0x00080000)
+
+#define RTC_TSD_WDU   ((uint32_t)0x0000E000)
+#define RTC_TSD_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSD_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSD_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSD_MOT   ((uint32_t)0x00001000)
+#define RTC_TSD_MOU   ((uint32_t)0x00000F00)
+#define RTC_TSD_MOU_0 ((uint32_t)0x00000100)
+#define RTC_TSD_MOU_1 ((uint32_t)0x00000200)
+#define RTC_TSD_MOU_2 ((uint32_t)0x00000400)
+#define RTC_TSD_MOU_3 ((uint32_t)0x00000800)
+#define RTC_TSD_DAT   ((uint32_t)0x00000030)
+#define RTC_TSD_DAT_0 ((uint32_t)0x00000010)
+#define RTC_TSD_DAT_1 ((uint32_t)0x00000020)
+#define RTC_TSD_DAU   ((uint32_t)0x0000000F)
+#define RTC_TSD_DAU_0 ((uint32_t)0x00000001)
+#define RTC_TSD_DAU_1 ((uint32_t)0x00000002)
+#define RTC_TSD_DAU_2 ((uint32_t)0x00000004)
+#define RTC_TSD_DAU_3 ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSS register  ****************/
+#define RTC_TSSS_SSE ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CALIB register  *****************/
+#define RTC_CALIB_CP   ((uint32_t)0x00008000)
+#define RTC_CALIB_CW8  ((uint32_t)0x00004000)
+#define RTC_CALIB_CW16 ((uint32_t)0x00002000)
+#define RTC_CALIB_CM   ((uint32_t)0x000001FF)
+#define RTC_CALIB_CM_0 ((uint32_t)0x00000001)
+#define RTC_CALIB_CM_1 ((uint32_t)0x00000002)
+#define RTC_CALIB_CM_2 ((uint32_t)0x00000004)
+#define RTC_CALIB_CM_3 ((uint32_t)0x00000008)
+#define RTC_CALIB_CM_4 ((uint32_t)0x00000010)
+#define RTC_CALIB_CM_5 ((uint32_t)0x00000020)
+#define RTC_CALIB_CM_6 ((uint32_t)0x00000040)
+#define RTC_CALIB_CM_7 ((uint32_t)0x00000080)
+#define RTC_CALIB_CM_8 ((uint32_t)0x00000100)
+
+/********************  Bits definition for RTC_TMPCFG register  ****************/
+
+#define RTC_TMPCFG_TP3MF                    ((uint32_t)0x01000000)
+#define RTC_TMPCFG_TP3NOE                   ((uint32_t)0x00800000)
+#define RTC_TMPCFG_TP3INTEN                 ((uint32_t)0x00400000)
+#define RTC_TMPCFG_TP2MF                    ((uint32_t)0x00200000)
+#define RTC_TMPCFG_TP2NOE                   ((uint32_t)0x00100000)
+#define RTC_TMPCFG_TP2INTEN                 ((uint32_t)0x00080000)
+#define RTC_TMPCFG_TP1MF                    ((uint32_t)0x00040000)
+#define RTC_TMPCFG_TP1NOE                   ((uint32_t)0x00020000)
+#define RTC_TMPCFG_TP1INTEN                 ((uint32_t)0x00010000)
+#define RTC_TMPCFG_TPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TMPCFG_TPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TMPCFG_TPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TMPCFG_TPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TMPCFG_TPFLT                    ((uint32_t)0x00001800)
+#define RTC_TMPCFG_TPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TMPCFG_TPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TMPCFG_TPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TMPCFG_TPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TMPCFG_TPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TMPCFG_TPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TMPCFG_TPTS                     ((uint32_t)0x00000080)
+#define RTC_TMPCFG_TP3TRG                   ((uint32_t)0x00000040)
+#define RTC_TMPCFG_TP3EN                    ((uint32_t)0x00000020)
+#define RTC_TMPCFG_TP2TRG                   ((uint32_t)0x00000010)
+#define RTC_TMPCFG_TP2EN                    ((uint32_t)0x00000008)
+#define RTC_TMPCFG_TPINTEN                  ((uint32_t)0x00000004)
+#define RTC_TMPCFG_TP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TMPCFG_TP1EN                    ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_ALRMASS register  *************/
+#define RTC_ALRMASS_MASKSSB   ((uint32_t)0x0F000000)
+#define RTC_ALRMASS_MASKSSB_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASS_MASKSSB_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASS_MASKSSB_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASS_MASKSSB_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASS_SSV       ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_ALRMBSS register  *************/
+#define RTC_ALRMBSS_MASKSSB   ((uint32_t)0x0F000000)
+#define RTC_ALRMBSS_MASKSSB_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSS_MASKSSB_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSS_MASKSSB_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSS_MASKSSB_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSS_SSV       ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_OPT register  *******************/
+#define RTC_OPT_TYPE ((uint32_t)0x00000001)
+/********************  Bits definition for  RTC_TSCWKUPCTRL register  *******************/
+#define RTC_TSCWKUPCTRL_WKUPOFF ((uint32_t)0x00000008)
+#define RTC_TSCWKUPCTRL_WKUPCNF ((uint32_t)0x00000004)
+#define RTC_TSCWKUPCTRL_WKUPEN  ((uint32_t)0x00000001)
+/********************  Bits definition for  RTC_TSCWKUPCNT register  *******************/
+#define RTC_TSCWKUPCNT_CNT ((uint32_t)0x00003FFF)
+/********************  Bits definition for RTC_BKP1 register  ****************/
+#define RTC_BKP1                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2 register  ****************/
+#define RTC_BKP2                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3 register  ****************/
+#define RTC_BKP3                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4 register  ****************/
+#define RTC_BKP4                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP5 register  ****************/
+#define RTC_BKP5                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP6 register  ****************/
+#define RTC_BKP6                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP7 register  ****************/
+#define RTC_BKP7                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP8 register  ****************/
+#define RTC_BKP8                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP9 register  ****************/
+#define RTC_BKP9                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP10 register  ****************/
+#define RTC_BKP10                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP11 register  ***************/
+#define RTC_BKP11                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP12register  ***************/
+#define RTC_BKP12                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP13 register  ***************/
+#define RTC_BKP13                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP14 register  ***************/
+#define RTC_BKP14                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP15 register  ***************/
+#define RTC_BKP15                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP16 register  ***************/
+#define RTC_BKP16                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP17register  ***************/
+#define RTC_BKP17                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP18 register  ***************/
+#define RTC_BKP18                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP19 register  ***************/
+#define RTC_BKP19                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP20 register  ***************/
+#define RTC_BKP20                           ((uint32_t)0xFFFFFFFF)
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_KEY register  ********************/
+#define IWDG_KEY_KEYV ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PREDIV register  ********************/
+#define IWDG_PREDIV_PD ((uint8_t)0x07) /*!< PD[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0   ((uint8_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1   ((uint8_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2   ((uint8_t)0x04) /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RELV register  *******************/
+#define IWDG_RELV_REL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_STS register  ********************/
+#define IWDG_STS_PVU  ((uint8_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_STS_CRVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CTRL register  ********************/
+#define WWDG_CTRL_T  ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CTRL_T0 ((uint8_t)0x01) /*!< Bit 0 */
+#define WWDG_CTRL_T1 ((uint8_t)0x02) /*!< Bit 1 */
+#define WWDG_CTRL_T2 ((uint8_t)0x04) /*!< Bit 2 */
+#define WWDG_CTRL_T3 ((uint8_t)0x08) /*!< Bit 3 */
+#define WWDG_CTRL_T4 ((uint8_t)0x10) /*!< Bit 4 */
+#define WWDG_CTRL_T5 ((uint8_t)0x20) /*!< Bit 5 */
+#define WWDG_CTRL_T6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define WWDG_CTRL_ACTB ((uint8_t)0x80) /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFG register  *******************/
+#define WWDG_CFG_W  ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFG_W0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define WWDG_CFG_W1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define WWDG_CFG_W2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define WWDG_CFG_W3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define WWDG_CFG_W4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define WWDG_CFG_W5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define WWDG_CFG_W6 ((uint16_t)0x0040) /*!< Bit 6 */
+
+#define WWDG_CFG_TIMERB  ((uint16_t)0x0180) /*!< TIMERB[1:0] bits (Timer Base) */
+#define WWDG_CFG_TIMERB0 ((uint16_t)0x0080) /*!< Bit 0 */
+#define WWDG_CFG_TIMERB1 ((uint16_t)0x0100) /*!< Bit 1 */
+
+#define WWDG_CFG_EWINT ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_STS register  ********************/
+#define WWDG_STS_EWINTF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Flexible Static Memory Controller                    */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for XFMC_BCR1 register  *******************/
+#define XFMC_BK1CSCTRL1_MBEN  ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define XFMC_BK1CSCTRL1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define XFMC_BK1CSCTRL1_MTYPE   ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define XFMC_BK1CSCTRL1_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL1_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL1_MDBW   ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define XFMC_BK1CSCTRL1_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL1_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL1_ACCEN     ((uint32_t)0x00000040) /*!< Flash access enable */
+#define XFMC_BK1CSCTRL1_BURSTEN   ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define XFMC_BK1CSCTRL1_WAITDIR   ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define XFMC_BK1CSCTRL1_WRAPEN    ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define XFMC_BK1CSCTRL1_WCFG      ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define XFMC_BK1CSCTRL1_WREN      ((uint32_t)0x00001000) /*!< Write enable bit */
+#define XFMC_BK1CSCTRL1_WAITEN    ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define XFMC_BK1CSCTRL1_EXTEN     ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define XFMC_BK1CSCTRL1_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define XFMC_BK1CSCTRL1_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/******************  Bit definition for XFMC_BCR2 register  *******************/
+#define XFMC_BK1CSCTRL2_MBEN  ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define XFMC_BK1CSCTRL2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define XFMC_BK1CSCTRL2_MTYPE   ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define XFMC_BK1CSCTRL2_MTYPE_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL2_MTYPE_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL2_MDBW   ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define XFMC_BK1CSCTRL2_MDBW_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1CSCTRL2_MDBW_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK1CSCTRL2_ACCEN     ((uint32_t)0x00000040) /*!< Flash access enable */
+#define XFMC_BK1CSCTRL2_BURSTEN   ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define XFMC_BK1CSCTRL2_WAITDIR   ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define XFMC_BK1CSCTRL2_WRAPEN    ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define XFMC_BK1CSCTRL2_WCFG      ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define XFMC_BK1CSCTRL2_WREN      ((uint32_t)0x00001000) /*!< Write enable bit */
+#define XFMC_BK1CSCTRL2_WAITEN    ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define XFMC_BK1CSCTRL2_EXTEN     ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define XFMC_BK1CSCTRL2_WAITASYNC ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define XFMC_BK1CSCTRL2_BURSTWREN ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/******************  Bit definition for XFMC_BTR1 register  ******************/
+#define XFMC_BK1TM1_ADDBLD   ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1TM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1TM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1TM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1TM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_ADDHLD   ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1TM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1TM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1TM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1TM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_DATABLD   ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1TM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1TM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1TM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1TM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_BUSRECOVERY   ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define XFMC_BK1TM1_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_BK1TM1_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_BK1TM1_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_BK1TM1_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_CLKDIV   ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1TM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1TM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define XFMC_BK1TM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1TM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_DATAHLD   ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1TM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1TM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1TM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1TM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1TM1_ACCMODE   ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1TM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1TM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/******************  Bit definition for XFMC_BTR2 register  *******************/
+#define XFMC_BK1TM2_ADDBLD   ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1TM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1TM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1TM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1TM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_ADDHLD   ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1TM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1TM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1TM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1TM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_DATABLD   ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1TM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1TM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1TM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1TM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_BUSRECOVERY   ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define XFMC_BK1TM2_BUSRECOVERY_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_BK1TM2_BUSRECOVERY_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_BK1TM2_BUSRECOVERY_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_BK1TM2_BUSRECOVERY_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_CLKDIV   ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1TM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1TM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define XFMC_BK1TM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1TM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_DATAHLD   ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1TM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1TM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1TM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1TM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1TM2_ACCMODE   ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1TM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1TM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/******************  Bit definition for XFMC_BWTR1 register  ******************/
+#define XFMC_BK1WTM1_ADDBLD   ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1WTM1_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1WTM1_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1WTM1_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1WTM1_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_ADDHLD   ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1WTM1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1WTM1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1WTM1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1WTM1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_DATABLD   ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1WTM1_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1WTM1_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1WTM1_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1WTM1_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_CLKDIV   ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1WTM1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1WTM1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define XFMC_BK1WTM1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1WTM1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_DATAHLD   ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1WTM1_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1WTM1_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1WTM1_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1WTM1_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM1_ACCMODE   ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1WTM1_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1WTM1_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/******************  Bit definition for XFMC_BWTR2 register  ******************/
+#define XFMC_BK1WTM2_ADDBLD   ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define XFMC_BK1WTM2_ADDBLD_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_BK1WTM2_ADDBLD_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_BK1WTM2_ADDBLD_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_BK1WTM2_ADDBLD_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_ADDHLD   ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define XFMC_BK1WTM2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK1WTM2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define XFMC_BK1WTM2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define XFMC_BK1WTM2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_DATABLD   ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define XFMC_BK1WTM2_DATABLD_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_BK1WTM2_DATABLD_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_BK1WTM2_DATABLD_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_BK1WTM2_DATABLD_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_CLKDIV   ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define XFMC_BK1WTM2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define XFMC_BK1WTM2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/
+#define XFMC_BK1WTM2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define XFMC_BK1WTM2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_DATAHLD   ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define XFMC_BK1WTM2_DATAHLD_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_BK1WTM2_DATAHLD_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_BK1WTM2_DATAHLD_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_BK1WTM2_DATAHLD_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define XFMC_BK1WTM2_ACCMODE   ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define XFMC_BK1WTM2_ACCMODE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define XFMC_BK1WTM2_ACCMODE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/******************  Bit definition for XFMC_PCR2 register  *******************/
+#define XFMC_BK2CTRL_WAITEN  ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define XFMC_BK2CTRL_BANKEN  ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define XFMC_BK2CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */
+
+#define XFMC_BK2CTRL_BUSWID   ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define XFMC_BK2CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK2CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK2CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define XFMC_BK2CTRL_CRDLY   ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define XFMC_BK2CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define XFMC_BK2CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define XFMC_BK2CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define XFMC_BK2CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define XFMC_BK2CTRL_ARDLY   ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define XFMC_BK2CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define XFMC_BK2CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define XFMC_BK2CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define XFMC_BK2CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define XFMC_BK2CTRL_ECCPGS   ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */
+#define XFMC_BK2CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define XFMC_BK2CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define XFMC_BK2CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/******************  Bit definition for XFMC_PCR3 register  *******************/
+#define XFMC_BK3CTRL_WAITEN  ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define XFMC_BK3CTRL_BANKEN  ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define XFMC_BK3CTRL_MEMTYPE ((uint32_t)0x00000008) /*!< Memory type */
+
+#define XFMC_BK3CTRL_BUSWID   ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define XFMC_BK3CTRL_BUSWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define XFMC_BK3CTRL_BUSWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define XFMC_BK3CTRL_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define XFMC_BK3CTRL_CRDLY   ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define XFMC_BK3CTRL_CRDLY_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define XFMC_BK3CTRL_CRDLY_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define XFMC_BK3CTRL_CRDLY_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define XFMC_BK3CTRL_CRDLY_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define XFMC_BK3CTRL_ARDLY   ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define XFMC_BK3CTRL_ARDLY_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define XFMC_BK3CTRL_ARDLY_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define XFMC_BK3CTRL_ARDLY_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define XFMC_BK3CTRL_ARDLY_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define XFMC_BK3CTRL_ECCPGS   ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
+#define XFMC_BK3CTRL_ECCPGS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define XFMC_BK3CTRL_ECCPGS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define XFMC_BK3CTRL_ECCPGS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/*******************  Bit definition for XFMC_SR2 register  *******************/
+//#define  XFMC_SR2_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+//#define  XFMC_SR2_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+//#define  XFMC_SR2_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+//#define  XFMC_SR2_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable
+// bit */ #define  XFMC_SR2_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection
+// Enable bit */ #define  XFMC_SR2_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge
+// detection Enable bit */
+#define XFMC_STS2_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */
+
+/*******************  Bit definition for XFMC_SR3 register  *******************/
+//#define  XFMC_SR3_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+//#define  XFMC_SR3_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+//#define  XFMC_SR3_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+//#define  XFMC_SR3_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable
+// bit */ #define  XFMC_SR3_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection
+// Enable bit */ #define  XFMC_SR3_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge
+// detection Enable bit */
+#define XFMC_STS3_FIFOEMPT ((uint8_t)0x40) /*!< DATFIFO empty */
+
+/******************  Bit definition for XFMC_PMEM2 register  ******************/
+#define XFMC_CMEMTM2_SET   ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define XFMC_CMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_CMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_CMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_CMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_CMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_CMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_CMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_CMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_CMEMTM2_WAIT   ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define XFMC_CMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_CMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_CMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_CMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_CMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_CMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_CMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_CMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM2_HLD   ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define XFMC_CMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_CMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_CMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_CMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_CMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_CMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_CMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_CMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM2_HIZ   ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define XFMC_CMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_CMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_CMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_CMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_CMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_CMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_CMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_CMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/******************  Bit definition for XFMC_PMEM3 register  ******************/
+#define XFMC_CMEMTM3_SET   ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define XFMC_CMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_CMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_CMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_CMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_CMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_CMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_CMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_CMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_CMEMTM3_WAIT   ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define XFMC_CMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_CMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_CMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_CMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_CMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_CMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_CMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_CMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM3_HLD   ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define XFMC_CMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_CMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_CMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_CMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_CMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_CMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_CMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_CMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_CMEMTM3_HIZ   ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define XFMC_CMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_CMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_CMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_CMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_CMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_CMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_CMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_CMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/******************  Bit definition for XFMC_PATT2 register  ******************/
+#define XFMC_ATTMEMTM2_SET   ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define XFMC_ATTMEMTM2_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM2_WAIT   ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define XFMC_ATTMEMTM2_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM2_HLD   ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define XFMC_ATTMEMTM2_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM2_HIZ   ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define XFMC_ATTMEMTM2_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM2_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM2_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM2_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM2_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM2_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM2_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM2_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/******************  Bit definition for XFMC_PATT3 register  ******************/
+#define XFMC_ATTMEMTM3_SET   ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define XFMC_ATTMEMTM3_SET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_SET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_SET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_SET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_SET_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_SET_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_SET_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_SET_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM3_WAIT   ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define XFMC_ATTMEMTM3_WAIT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_WAIT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_WAIT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_WAIT_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_WAIT_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_WAIT_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_WAIT_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_WAIT_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM3_HLD   ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define XFMC_ATTMEMTM3_HLD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_HLD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_HLD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_HLD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_HLD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_HLD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_HLD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_HLD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define XFMC_ATTMEMTM3_HIZ   ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define XFMC_ATTMEMTM3_HIZ_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define XFMC_ATTMEMTM3_HIZ_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define XFMC_ATTMEMTM3_HIZ_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define XFMC_ATTMEMTM3_HIZ_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define XFMC_ATTMEMTM3_HIZ_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define XFMC_ATTMEMTM3_HIZ_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define XFMC_ATTMEMTM3_HIZ_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define XFMC_ATTMEMTM3_HIZ_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/******************  Bit definition for XFMC_ECCR2 register  ******************/
+#define XFMC_ECCR2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
+
+/******************  Bit definition for XFMC_ECCR3 register  ******************/
+#define XFMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   USB Device FS                            */
+/*                                                                            */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+/*******************  Bit definition for USB_EP0R register  *******************/
+#define USB_EP0_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP0_STS_TX   ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP0_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP0_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP0_CTRS_TX   ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP0_EP_KIND   ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP0_EP_TYPE   ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP0_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP0_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP0_STS_RX   ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP0_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP0_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP0_CTRS_RX   ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP1R register  *******************/
+#define USB_EP1_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP1_STS_TX   ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP1_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP1_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP1_CTRS_TX   ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP1_EP_KIND   ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP1_EP_TYPE   ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP1_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP1_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP1_STS_RX   ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP1_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP1_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP1_CTRS_RX   ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP2R register  *******************/
+#define USB_EP2_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP2_STS_TX   ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP2_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP2_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP2_CTRS_TX   ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP2_EP_KIND   ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP2_EP_TYPE   ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP2_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP2_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP2_STS_RX   ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP2_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP2_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP2_CTRS_RX   ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP3R register  *******************/
+#define USB_EP3_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP3_STS_TX   ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP3_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP3_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP3_CTRS_TX   ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP3_EP_KIND   ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP3_EP_TYPE   ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP3_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP3_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP3_STS_RX   ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP3_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP3_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP3_CTRS_RX   ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP4R register  *******************/
+#define USB_EP4_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP4_STS_TX   ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP4_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP4_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP4_CTRS_TX   ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP4_EP_KIND   ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP4_EP_TYPE   ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP4_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP4_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP4_STS_RX   ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP4_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP4_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP4_CTRS_RX   ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP5R register  *******************/
+#define USB_EP5_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP5_STS_TX   ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP5_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP5_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP5_CTRS_TX   ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP5_EP_KIND   ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP5_EP_TYPE   ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP5_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP5_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP5_STS_RX   ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP5_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP5_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP5_CTRS_RX   ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP6R register  *******************/
+#define USB_EP6_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP6_STS_TX   ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP6_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP6_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP6_CTRS_TX   ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP6_EP_KIND   ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP6_EP_TYPE   ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP6_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP6_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP6_STS_RX   ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP6_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP6_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP6_CTRS_RX   ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP7R register  *******************/
+#define USB_EP7_EPADDR ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP7_STS_TX   ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7_STS_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP7_STS_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP7_DATTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP7_CTRS_TX   ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP7_EP_KIND   ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP7_EP_TYPE   ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP7_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP7_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP7_STS_RX   ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7_STS_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP7_STS_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP7_DATTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP7_CTRS_RX   ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/*******************  Bit definition for USB_CNTR register  *******************/
+#define USB_CTRL_FRST    ((uint16_t)0x0001) /*!< Force USB Reset */
+#define USB_CTRL_PD      ((uint16_t)0x0002) /*!< Power down */
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */
+#define USB_CTRL_FSUSPD  ((uint16_t)0x0008) /*!< Force suspend */
+#define USB_CTRL_RESUM   ((uint16_t)0x0010) /*!< Resume request */
+#define USB_CNTR_ESOFM   ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM    ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */
+#define USB_CTRL_RSTM    ((uint16_t)0x0400) /*!< RESET Interrupt Mask */
+#define USB_CTRL_SUSPDM  ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */
+#define USB_CTRL_WKUPM   ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */
+#define USB_CTRL_ERRORM  ((uint16_t)0x2000) /*!< Error Interrupt Mask */
+#define USB_CTRL_PMAOM   ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CTRL_CTRSM   ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */
+
+/*******************  Bit definition for USB_ISTR register  *******************/
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */
+#define USB_ISTR_DIR   ((uint16_t)0x0010) /*!< Direction of transaction */
+#define USB_ISTR_ESOF  ((uint16_t)0x0100) /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF   ((uint16_t)0x0200) /*!< Start Of Frame */
+#define USB_STS_RST    ((uint16_t)0x0400) /*!< USB RESET request */
+#define USB_STS_SUSPD  ((uint16_t)0x0800) /*!< Suspend mode request */
+#define USB_ISTR_WKUP  ((uint16_t)0x1000) /*!< Wake up */
+#define USB_STS_ERROR  ((uint16_t)0x2000) /*!< Error */
+#define USB_STS_PMAO   ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */
+#define USB_STS_CTRS   ((uint16_t)0x8000) /*!< Correct Transfer */
+
+/*******************  Bit definition for USB_FNR register  ********************/
+#define USB_FN_FNUM     ((uint16_t)0x07FF) /*!< Frame Number */
+#define USB_FN_LSTSOF   ((uint16_t)0x1800) /*!< Lost SOF */
+#define USB_FNR_LCK     ((uint16_t)0x2000) /*!< Locked */
+#define USB_FN_RXDM_STS ((uint16_t)0x4000) /*!< Receive Data - Line Status */
+#define USB_FN_RXDP_STS ((uint16_t)0x8000) /*!< Receive Data + Line Status */
+
+/******************  Bit definition for USB_DADDR register  *******************/
+#define USB_ADDR_ADDR  ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */
+#define USB_ADDR_ADDR0 ((uint8_t)0x01) /*!< Bit 0 */
+#define USB_ADDR_ADDR1 ((uint8_t)0x02) /*!< Bit 1 */
+#define USB_ADDR_ADDR2 ((uint8_t)0x04) /*!< Bit 2 */
+#define USB_ADDR_ADDR3 ((uint8_t)0x08) /*!< Bit 3 */
+#define USB_ADDR_ADDR4 ((uint8_t)0x10) /*!< Bit 4 */
+#define USB_ADDR_ADDR5 ((uint8_t)0x20) /*!< Bit 5 */
+#define USB_ADDR_ADDR6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define USB_ADDR_EFUC ((uint8_t)0x80) /*!< Enable Function */
+
+/******************  Bit definition for USB_BTABLE register  ******************/
+#define USB_BUFTAB_BUFTAB ((uint16_t)0xFFF8) /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/*****************  Bit definition for USB_ADDR0_TX register  *****************/
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_TX register  *****************/
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_TX register  *****************/
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_TX register  *****************/
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_TX register  *****************/
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_TX register  *****************/
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_TX register  *****************/
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_TX register  *****************/
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_TX register  ****************/
+#define USB_CNT0_TX_CNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
+
+/*****************  Bit definition for USB_COUNT1_TX register  ****************/
+#define USB_CNT1_TX_CNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
+
+/*****************  Bit definition for USB_COUNT2_TX register  ****************/
+#define USB_CNT2_TX_CNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
+
+/*****************  Bit definition for USB_COUNT3_TX register  ****************/
+#define USB_CNT3_TX_CNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
+
+/*****************  Bit definition for USB_COUNT4_TX register  ****************/
+#define USB_CNT4_TX_CNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
+
+/*****************  Bit definition for USB_COUNT5_TX register  ****************/
+#define USB_CNT5_TX_CNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
+
+/*****************  Bit definition for USB_COUNT6_TX register  ****************/
+#define USB_CNT6_TX_CNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
+
+/*****************  Bit definition for USB_COUNT7_TX register  ****************/
+#define USB_CNT7_TX_CNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
+#define USB_CNT0_TX_0_CNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
+#define USB_CNT0_TX_1_CNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
+#define USB_CNT1_TX_0_CNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
+#define USB_CNT1_TX_1_CNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
+#define USB_CNT2_TX_0_CNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
+#define USB_CNT2_TX_1_CNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
+#define USB_CNT3_TX_0_CNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
+#define USB_CNT3_TX_1_CNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
+#define USB_CNT4_TX_0_CNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
+#define USB_CNT4_TX_1_CNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
+#define USB_CNT5_TX_0_CNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
+#define USB_CNT5_TX_1_CNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
+#define USB_CNT6_TX_0_CNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
+#define USB_CNT6_TX_1_CNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
+#define USB_CNT7_TX_0_CNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
+#define USB_CNT7_TX_1_CNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_ADDR0_RX register  *****************/
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_RX register  *****************/
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_RX register  *****************/
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_RX register  *****************/
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_RX register  *****************/
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_RX register  *****************/
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_RX register  *****************/
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_RX register  *****************/
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_RX register  ****************/
+#define USB_CNT0_RX_CNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT0_RX_NUM_BLK   ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT0_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT0_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT0_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT0_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT0_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT1_RX register  ****************/
+#define USB_CNT1_RX_CNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT1_RX_NUM_BLK   ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT1_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT1_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT1_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT1_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT1_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT2_RX register  ****************/
+#define USB_CNT2_RX_CNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT2_RX_NUM_BLK   ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT2_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT2_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT2_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT2_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT2_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT3_RX register  ****************/
+#define USB_CNT3_RX_CNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT3_RX_NUM_BLK   ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT3_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT3_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT3_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT3_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT3_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT4_RX register  ****************/
+#define USB_CNT4_RX_CNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT4_RX_NUM_BLK   ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT4_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT4_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT4_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT4_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT4_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT5_RX register  ****************/
+#define USB_CNT5_RX_CNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT5_RX_NUM_BLK   ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT5_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT5_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT5_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT5_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT5_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT6_RX register  ****************/
+#define USB_CNT6_RX_CNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT6_RX_NUM_BLK   ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT6_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT6_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT6_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT6_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT6_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT7_RX register  ****************/
+#define USB_CNT7_RX_CNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_CNT7_RX_NUM_BLK   ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_CNT7_RX_NUM_BLK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_CNT7_RX_NUM_BLK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_CNT7_RX_NUM_BLK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_CNT7_RX_NUM_BLK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_CNT7_RX_NUM_BLK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_CNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
+#define USB_CNT0_RX_0_CNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT0_RX_0_NUM_BLK_0   ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT0_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT0_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT0_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT0_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT0_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
+#define USB_CNT0_RX_1_CNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT0_RX_1_NUM_BLK_1   ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT0_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_CNT0_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT0_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT0_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT0_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
+#define USB_CNT1_RX_0_CNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT1_RX_0_NUM_BLK_0   ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT1_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT1_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT1_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT1_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT1_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
+#define USB_CNT1_RX_1_CNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT1_RX_1_NUM_BLK_1   ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT1_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT1_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT1_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT1_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT1_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
+#define USB_CNT2_RX_0_CNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT2_RX_0_NUM_BLK_0   ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT2_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT2_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT2_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT2_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT2_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
+#define USB_CNT2_RX_1_CNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT2_RX_1_NUM_BLK_1   ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT2_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT2_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT2_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT2_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT2_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
+#define USB_CNT3_RX_0_CNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT3_RX_0_NUM_BLK_0   ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT3_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT3_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT3_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT3_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT3_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
+#define USB_CNT3_RX_1_CNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT3_RX_1_NUM_BLK_1   ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT3_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT3_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT3_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT3_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT3_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
+#define USB_CNT4_RX_0_CNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT4_RX_0_NUM_BLK_0   ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT4_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT4_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT4_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT4_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT4_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
+#define USB_CNT4_RX_1_CNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT4_RX_1_NUM_BLK_1   ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT4_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT4_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT4_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT4_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT4_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
+#define USB_CNT5_RX_0_CNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT5_RX_0_NUM_BLK_0   ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT5_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT5_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT5_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT5_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT5_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
+#define USB_CNT5_RX_1_CNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT5_RX_1_NUM_BLK_1   ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT5_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT5_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT5_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT5_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT5_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
+#define USB_CNT6_RX_0_CNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT6_RX_0_NUM_BLK_0   ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT6_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT6_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT6_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT6_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT6_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
+#define USB_CNT6_RX_1_CNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT6_RX_1_NUM_BLK_1   ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT6_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT6_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT6_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT6_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT6_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
+#define USB_CNT7_RX_0_CNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_CNT7_RX_0_NUM_BLK_0   ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_CNT7_RX_0_NUM_BLK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_CNT7_RX_0_NUM_BLK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_CNT7_RX_0_NUM_BLK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_CNT7_RX_0_NUM_BLK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_CNT7_RX_0_NUM_BLK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_CNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
+#define USB_CNT7_RX_1_CNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_CNT7_RX_1_NUM_BLK_1   ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_CNT7_RX_1_NUM_BLK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_CNT7_RX_1_NUM_BLK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_CNT7_RX_1_NUM_BLK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_CNT7_RX_1_NUM_BLK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_CNT7_RX_1_NUM_BLK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_CNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/*******************  Bit definition for CAN_MCTRL register  ********************/
+#define CAN_MCTRL_INIRQ ((uint16_t)0x0001) /*!< Initialization Request */
+#define CAN_MCTRL_SLPRQ ((uint16_t)0x0002) /*!< Sleep Mode Request */
+#define CAN_MCTRL_TXFP  ((uint16_t)0x0004) /*!< Transmit DATFIFO Priority */
+#define CAN_MCTRL_RFLM  ((uint16_t)0x0008) /*!< Receive DATFIFO Locked Mode */
+#define CAN_MCTRL_NART  ((uint16_t)0x0010) /*!< No Automatic Retransmission */
+#define CAN_MCTRL_AWKUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */
+#define CAN_MCTRL_ABOM  ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */
+#define CAN_MCTRL_TTCM  ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */
+#define CAN_MCTRL_MRST  ((uint16_t)0x8000) /*!< CAN software master reset */
+#define CAN_MCTRL_DBGF  ((uint32_t)0x00010000) /*!< CAN Debug freeze */
+
+/*******************  Bit definition for CAN_MSTS register  ********************/
+#define CAN_MSTS_INIAK   ((uint16_t)0x0001) /*!< Initialization Acknowledge */
+#define CAN_MSTS_SLPAK   ((uint16_t)0x0002) /*!< Sleep Acknowledge */
+#define CAN_MSTS_ERRINT  ((uint16_t)0x0004) /*!< Error Interrupt */
+#define CAN_MSTS_WKUINT  ((uint16_t)0x0008) /*!< Wakeup Interrupt */
+#define CAN_MSTS_SLAKINT ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSTS_TXMD    ((uint16_t)0x0100) /*!< Transmit Mode */
+#define CAN_MSTS_RXMD    ((uint16_t)0x0200) /*!< Receive Mode */
+#define CAN_MSTS_LSMP    ((uint16_t)0x0400) /*!< Last Sample Point */
+#define CAN_MSTS_RXS     ((uint16_t)0x0800) /*!< CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSTS register  ********************/
+#define CAN_TSTS_RQCPM0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */
+#define CAN_TSTS_TXOKM0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */
+#define CAN_TSTS_ALSTM0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSTS_TERRM0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */
+#define CAN_TSTS_ABRQM0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */
+#define CAN_TSTS_RQCPM1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */
+#define CAN_TSTS_TXOKM1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */
+#define CAN_TSTS_ALSTM1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSTS_TERRM1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */
+#define CAN_TSTS_ABRQM1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */
+#define CAN_TSTS_RQCPM2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */
+#define CAN_TSTS_TXOKM2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSTS_ALSTM2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSTS_TERRM2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSTS_ABRQM2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */
+#define CAN_TSTS_CODE   ((uint32_t)0x03000000) /*!< Mailbox Code */
+
+#define CAN_TSTS_TMEM  ((uint32_t)0x1C000000) /*!< TME[2:0] bits */
+#define CAN_TSTS_TMEM0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSTS_TMEM1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSTS_TMEM2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSTS_LOWM  ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */
+#define CAN_TSTS_LOWM0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSTS_LOWM1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSTS_LOWM2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RFF0 register  *******************/
+#define CAN_RFF0_FFMP0  ((uint8_t)0x03) /*!< DATFIFO 0 Message Pending */
+#define CAN_RFF0_FFULL0 ((uint8_t)0x08) /*!< DATFIFO 0 Full */
+#define CAN_RFF0_FFOVR0 ((uint8_t)0x10) /*!< DATFIFO 0 Overrun */
+#define CAN_RFF0_RFFOM0 ((uint8_t)0x20) /*!< Release DATFIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RFF1 register  *******************/
+#define CAN_RFF1_FFMP1  ((uint8_t)0x03) /*!< DATFIFO 1 Message Pending */
+#define CAN_RFF1_FFULL1 ((uint8_t)0x08) /*!< DATFIFO 1 Full */
+#define CAN_RFF1_FFOVR1 ((uint8_t)0x10) /*!< DATFIFO 1 Overrun */
+#define CAN_RFF1_RFFOM1 ((uint8_t)0x20) /*!< Release DATFIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_INTE register  *******************/
+#define CAN_INTE_TMEITE  ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_INTE_FMPITE0 ((uint32_t)0x00000002) /*!< DATFIFO Message Pending Interrupt Enable */
+#define CAN_INTE_FFITE0  ((uint32_t)0x00000004) /*!< DATFIFO Full Interrupt Enable */
+#define CAN_INTE_FOVITE0 ((uint32_t)0x00000008) /*!< DATFIFO Overrun Interrupt Enable */
+#define CAN_INTE_FMPITE1 ((uint32_t)0x00000010) /*!< DATFIFO Message Pending Interrupt Enable */
+#define CAN_INTE_FFITE1  ((uint32_t)0x00000020) /*!< DATFIFO Full Interrupt Enable */
+#define CAN_INTE_FOVITE1 ((uint32_t)0x00000040) /*!< DATFIFO Overrun Interrupt Enable */
+#define CAN_INTE_EWGITE  ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */
+#define CAN_INTE_EPVITE  ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */
+#define CAN_INTE_BOFITE  ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */
+#define CAN_INTE_LECITE  ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */
+#define CAN_INTE_ERRITE  ((uint32_t)0x00008000) /*!< Error Interrupt Enable */
+#define CAN_INTE_WKUITE  ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */
+#define CAN_INTE_SLKITE  ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESTS register  *******************/
+#define CAN_ESTS_EWGFL ((uint32_t)0x00000001) /*!< Error Warning Flag */
+#define CAN_ESTS_EPVFL ((uint32_t)0x00000002) /*!< Error Passive Flag */
+#define CAN_ESTS_BOFFL ((uint32_t)0x00000004) /*!< Bus-Off Flag */
+
+#define CAN_ESTS_LEC   ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESTS_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define CAN_ESTS_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define CAN_ESTS_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define CAN_ESTS_TXEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESTS_RXEC ((uint32_t)0xFF000000) /*!< Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTIM register  ********************/
+#define CAN_BTIM_BRTP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */
+#define CAN_BTIM_TBS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */
+#define CAN_BTIM_TBS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */
+#define CAN_BTIM_RSJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */
+#define CAN_BTIM_LBM  ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */
+#define CAN_BTIM_SLM  ((uint32_t)0x80000000) /*!< Silent Mode */
+
+/*!< Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define CAN_TMI0_TXRQ  ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TMI0_RTRQ  ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TMI0_IDE   ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define CAN_TMDT0_DLC  ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TMDT0_TGT  ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define CAN_TMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define CAN_TMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define CAN_TMI1_TXRQ  ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TMI1_RTRQ  ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TMI1_IDE   ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define CAN_TMDT1_DLC  ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TMDT1_TGT  ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define CAN_TMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define CAN_TMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define CAN_TMI2_TXRQ  ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TMI2_RTRQ  ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TMI2_IDE   ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TMI2_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_TMI2_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/
+#define CAN_TMDT2_DLC  ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TMDT2_TGT  ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TMDT2_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define CAN_TMDL2_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TMDL2_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TMDL2_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TMDL2_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define CAN_TMDH2_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TMDH2_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TMDH2_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TMDH2_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define CAN_RMI0_RTRQ  ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RMI0_IDE   ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RMI0_EXTID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_RMI0_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define CAN_RMDT0_DLC  ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RMDT0_FMI  ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RMDT0_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define CAN_RMDL0_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RMDL0_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RMDL0_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RMDL0_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define CAN_RMDH0_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RMDH0_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RMDH0_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RMDH0_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define CAN_RMI1_RTRQ  ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RMI1_IDE   ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RMI1_EXTID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_RMI1_STDID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define CAN_RMDT1_DLC  ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RMDT1_FMI  ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RMDT1_MTIM ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define CAN_RMDL1_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RMDL1_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RMDL1_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RMDL1_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define CAN_RMDH1_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RMDH1_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RMDH1_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RMDH1_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/*******************  Bit definition for CAN_FMC register  ********************/
+#define CAN_FMC_FINITM ((uint8_t)0x01) /*!< Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1 register  *******************/
+#define CAN_FM1_FB   ((uint16_t)0x3FFF) /*!< Filter Mode */
+#define CAN_FM1_FB0  ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */
+#define CAN_FM1_FB1  ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */
+#define CAN_FM1_FB2  ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */
+#define CAN_FM1_FB3  ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */
+#define CAN_FM1_FB4  ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */
+#define CAN_FM1_FB5  ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */
+#define CAN_FM1_FB6  ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */
+#define CAN_FM1_FB7  ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */
+#define CAN_FM1_FB8  ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */
+#define CAN_FM1_FB9  ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */
+#define CAN_FM1_FB10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */
+#define CAN_FM1_FB11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */
+#define CAN_FM1_FB12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */
+#define CAN_FM1_FB13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1 register  *******************/
+#define CAN_FS1_FSC   ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */
+#define CAN_FS1_FSC0  ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */
+#define CAN_FS1_FSC1  ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */
+#define CAN_FS1_FSC2  ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */
+#define CAN_FS1_FSC3  ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */
+#define CAN_FS1_FSC4  ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */
+#define CAN_FS1_FSC5  ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */
+#define CAN_FS1_FSC6  ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */
+#define CAN_FS1_FSC7  ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */
+#define CAN_FS1_FSC8  ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */
+#define CAN_FS1_FSC9  ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */
+#define CAN_FS1_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */
+#define CAN_FS1_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */
+#define CAN_FS1_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */
+#define CAN_FS1_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1 register  *******************/
+#define CAN_FFA1_FAF   ((uint16_t)0x3FFF) /*!< Filter DATFIFO Assignment */
+#define CAN_FFA1_FAF0  ((uint16_t)0x0001) /*!< Filter DATFIFO Assignment for Filter 0 */
+#define CAN_FFA1_FAF1  ((uint16_t)0x0002) /*!< Filter DATFIFO Assignment for Filter 1 */
+#define CAN_FFA1_FAF2  ((uint16_t)0x0004) /*!< Filter DATFIFO Assignment for Filter 2 */
+#define CAN_FFA1_FAF3  ((uint16_t)0x0008) /*!< Filter DATFIFO Assignment for Filter 3 */
+#define CAN_FFA1_FAF4  ((uint16_t)0x0010) /*!< Filter DATFIFO Assignment for Filter 4 */
+#define CAN_FFA1_FAF5  ((uint16_t)0x0020) /*!< Filter DATFIFO Assignment for Filter 5 */
+#define CAN_FFA1_FAF6  ((uint16_t)0x0040) /*!< Filter DATFIFO Assignment for Filter 6 */
+#define CAN_FFA1_FAF7  ((uint16_t)0x0080) /*!< Filter DATFIFO Assignment for Filter 7 */
+#define CAN_FFA1_FAF8  ((uint16_t)0x0100) /*!< Filter DATFIFO Assignment for Filter 8 */
+#define CAN_FFA1_FAF9  ((uint16_t)0x0200) /*!< Filter DATFIFO Assignment for Filter 9 */
+#define CAN_FFA1_FAF10 ((uint16_t)0x0400) /*!< Filter DATFIFO Assignment for Filter 10 */
+#define CAN_FFA1_FAF11 ((uint16_t)0x0800) /*!< Filter DATFIFO Assignment for Filter 11 */
+#define CAN_FFA1_FAF12 ((uint16_t)0x1000) /*!< Filter DATFIFO Assignment for Filter 12 */
+#define CAN_FFA1_FAF13 ((uint16_t)0x2000) /*!< Filter DATFIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1 register  *******************/
+#define CAN_FA1_FAC   ((uint16_t)0x3FFF) /*!< Filter Active */
+#define CAN_FA1_FAC0  ((uint16_t)0x0001) /*!< Filter 0 Active */
+#define CAN_FA1_FAC1  ((uint16_t)0x0002) /*!< Filter 1 Active */
+#define CAN_FA1_FAC2  ((uint16_t)0x0004) /*!< Filter 2 Active */
+#define CAN_FA1_FAC3  ((uint16_t)0x0008) /*!< Filter 3 Active */
+#define CAN_FA1_FAC4  ((uint16_t)0x0010) /*!< Filter 4 Active */
+#define CAN_FA1_FAC5  ((uint16_t)0x0020) /*!< Filter 5 Active */
+#define CAN_FA1_FAC6  ((uint16_t)0x0040) /*!< Filter 6 Active */
+#define CAN_FA1_FAC7  ((uint16_t)0x0080) /*!< Filter 7 Active */
+#define CAN_FA1_FAC8  ((uint16_t)0x0100) /*!< Filter 8 Active */
+#define CAN_FA1_FAC9  ((uint16_t)0x0200) /*!< Filter 9 Active */
+#define CAN_FA1_FAC10 ((uint16_t)0x0400) /*!< Filter 10 Active */
+#define CAN_FA1_FAC11 ((uint16_t)0x0800) /*!< Filter 11 Active */
+#define CAN_FA1_FAC12 ((uint16_t)0x1000) /*!< Filter 12 Active */
+#define CAN_FA1_FAC13 ((uint16_t)0x2000) /*!< Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13B1_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13B1_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13B1_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13B1_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13B1_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13B1_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13B1_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13B1_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13B1_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13B1_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13B1_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13B1_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13B1_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13B1_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13B1_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13B1_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13B1_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13B1_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13B1_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13B1_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13B1_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13B1_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13B1_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13B1_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13B1_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13B1_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13B1_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13B1_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13B1_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13B1_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13B1_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13B1_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13B2_FBC0  ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13B2_FBC1  ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13B2_FBC2  ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13B2_FBC3  ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13B2_FBC4  ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13B2_FBC5  ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13B2_FBC6  ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13B2_FBC7  ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13B2_FBC8  ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13B2_FBC9  ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13B2_FBC10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13B2_FBC11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13B2_FBC12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13B2_FBC13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13B2_FBC14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13B2_FBC15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13B2_FBC16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13B2_FBC17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13B2_FBC18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13B2_FBC19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13B2_FBC20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13B2_FBC21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13B2_FBC22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13B2_FBC23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13B2_FBC24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13B2_FBC25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13B2_FBC26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13B2_FBC27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13B2_FBC28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13B2_FBC29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13B2_FBC30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13B2_FBC31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SPI_CTRL1 register  ********************/
+#define SPI_CTRL1_CLKPHA ((uint16_t)0x0001) /*!< Clock Phase */
+#define SPI_CTRL1_CLKPOL ((uint16_t)0x0002) /*!< Clock Polarity */
+#define SPI_CTRL1_MSEL   ((uint16_t)0x0004) /*!< Master Selection */
+
+#define SPI_CTRL1_BR  ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CTRL1_BR0 ((uint16_t)0x0008) /*!< Bit 0 */
+#define SPI_CTRL1_BR1 ((uint16_t)0x0010) /*!< Bit 1 */
+#define SPI_CTRL1_BR2 ((uint16_t)0x0020) /*!< Bit 2 */
+
+#define SPI_CTRL1_SPIEN     ((uint16_t)0x0040) /*!< SPI Enable */
+#define SPI_CTRL1_LSBFF     ((uint16_t)0x0080) /*!< Frame Format */
+#define SPI_CTRL1_SSEL      ((uint16_t)0x0100) /*!< Internal slave select */
+#define SPI_CTRL1_SSMEN     ((uint16_t)0x0200) /*!< Software slave management */
+#define SPI_CTRL1_RONLY     ((uint16_t)0x0400) /*!< Receive only */
+#define SPI_CTRL1_DATFF     ((uint16_t)0x0800) /*!< Data Frame Format */
+#define SPI_CTRL1_CRCNEXT   ((uint16_t)0x1000) /*!< Transmit CRC next */
+#define SPI_CTRL1_CRCEN     ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
+#define SPI_CTRL1_BIDIROEN  ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
+#define SPI_CTRL1_BIDIRMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CTRL2 register  ********************/
+#define SPI_CTRL2_RDMAEN   ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
+#define SPI_CTRL2_TDMAEN   ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
+#define SPI_CTRL2_SSOEN    ((uint8_t)0x04) /*!< SS Output Enable */
+#define SPI_CTRL2_ERRINTEN ((uint8_t)0x20) /*!< Error Interrupt Enable */
+#define SPI_CTRL2_RNEINTEN ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CTRL2_TEINTEN  ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_STS register  ********************/
+#define SPI_STS_RNE    ((uint8_t)0x01) /*!< Receive buffer Not Empty */
+#define SPI_STS_TE     ((uint8_t)0x02) /*!< Transmit buffer Empty */
+#define SPI_STS_CHSIDE ((uint8_t)0x04) /*!< Channel side */
+#define SPI_STS_UNDER  ((uint8_t)0x08) /*!< Underrun flag */
+#define SPI_STS_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
+#define SPI_STS_MODERR ((uint8_t)0x20) /*!< Mode fault */
+#define SPI_STS_OVER   ((uint8_t)0x40) /*!< Overrun flag */
+#define SPI_STS_BUSY   ((uint8_t)0x80) /*!< Busy flag */
+
+/********************  Bit definition for SPI_DAT register  ********************/
+#define SPI_DAT_DAT ((uint16_t)0xFFFF) /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPOLY register  ******************/
+#define SPI_CRCPOLY_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_CRCRDAT register  ******************/
+#define SPI_CRCRDAT_CRCRDAT ((uint16_t)0xFFFF) /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_CRCTDAT register  ******************/
+#define SPI_CRCTDAT_CRCTDAT ((uint16_t)0xFFFF) /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFG register  *****************/
+#define SPI_I2SCFG_CHBITS ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFG_TDATLEN  ((uint16_t)0x0006) /*!< TDATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFG_TDATLEN0 ((uint16_t)0x0002) /*!< Bit 0 */
+#define SPI_I2SCFG_TDATLEN1 ((uint16_t)0x0004) /*!< Bit 1 */
+
+#define SPI_I2SCFG_CLKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */
+
+#define SPI_I2SCFG_STDSEL  ((uint16_t)0x0030) /*!< STDSEL[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFG_STDSEL0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define SPI_I2SCFG_STDSEL1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define SPI_I2SCFG_PCMFSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */
+
+#define SPI_I2SCFG_MODCFG  ((uint16_t)0x0300) /*!< MODCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFG_MODCFG0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define SPI_I2SCFG_MODCFG1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define SPI_I2SCFG_I2SEN  ((uint16_t)0x0400) /*!< I2S Enable */
+#define SPI_I2SCFG_MODSEL ((uint16_t)0x0800) /*!< I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPREDIV register  *******************/
+#define SPI_I2SPREDIV_LDIV     ((uint16_t)0x00FF) /*!< I2S Linear prescaler */
+#define SPI_I2SPREDIV_ODD_EVEN ((uint16_t)0x0100) /*!< Odd factor for the prescaler */
+#define SPI_I2SPREDIV_MCLKOEN  ((uint16_t)0x0200) /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CTRL1 register  ********************/
+#define I2C_CTRL1_EN       ((uint16_t)0x0001) /*!< Peripheral Enable */
+#define I2C_CTRL1_SMBMODE  ((uint16_t)0x0002) /*!< SMBus Mode */
+#define I2C_CTRL1_SMBTYPE  ((uint16_t)0x0008) /*!< SMBus Type */
+#define I2C_CTRL1_ARPEN    ((uint16_t)0x0010) /*!< ARP Enable */
+#define I2C_CTRL1_PECEN    ((uint16_t)0x0020) /*!< PEC Enable */
+#define I2C_CTRL1_GCEN     ((uint16_t)0x0040) /*!< General Call Enable */
+#define I2C_CTRL1_NOEXTEND ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CTRL1_STARTGEN ((uint16_t)0x0100) /*!< Start Generation */
+#define I2C_CTRL1_STOPGEN  ((uint16_t)0x0200) /*!< Stop Generation */
+#define I2C_CTRL1_ACKEN    ((uint16_t)0x0400) /*!< Acknowledge Enable */
+#define I2C_CTRL1_ACKPOS   ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CTRL1_PEC      ((uint16_t)0x1000) /*!< Packet Error Checking */
+#define I2C_CTRL1_SMBALERT ((uint16_t)0x2000) /*!< SMBus Alert */
+#define I2C_CTRL1_SWRESET  ((uint16_t)0x8000) /*!< Software Reset */
+
+/*******************  Bit definition for I2C_CTRL2 register  ********************/
+#define I2C_CTRL2_CLKFREQ   ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CTRL2_CLKFREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_CTRL2_CLKFREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_CTRL2_CLKFREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_CTRL2_CLKFREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_CTRL2_CLKFREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_CTRL2_CLKFREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
+
+#define I2C_CTRL2_ERRINTEN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
+#define I2C_CTRL2_EVTINTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
+#define I2C_CTRL2_BUFINTEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
+#define I2C_CTRL2_DMAEN    ((uint16_t)0x0800) /*!< DMA Requests Enable */
+#define I2C_CTRL2_DMALAST  ((uint16_t)0x1000) /*!< DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OADDR1 register  *******************/
+#define I2C_OADDR1_ADDR1_7 ((uint16_t)0x00FE) /*!< Interface Address */
+#define I2C_OADDR1_ADDR8_9 ((uint16_t)0x0300) /*!< Interface Address */
+
+#define I2C_OADDR1_ADDR0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_OADDR1_ADDR1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_OADDR1_ADDR2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_OADDR1_ADDR3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_OADDR1_ADDR4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_OADDR1_ADDR5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define I2C_OADDR1_ADDR6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define I2C_OADDR1_ADDR7 ((uint16_t)0x0080) /*!< Bit 7 */
+#define I2C_OADDR1_ADDR8 ((uint16_t)0x0100) /*!< Bit 8 */
+#define I2C_OADDR1_ADDR9 ((uint16_t)0x0200) /*!< Bit 9 */
+
+#define I2C_OADDR1_ADDRMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OADDR2 register  *******************/
+#define I2C_OADDR2_DUALEN ((uint8_t)0x01) /*!< Dual addressing mode enable */
+#define I2C_OADDR2_ADDR2  ((uint8_t)0xFE) /*!< Interface address */
+
+/********************  Bit definition for I2C_DAT register  ********************/
+#define I2C_DAT_DATA ((uint8_t)0xFF) /*!< 8-bit Data Register */
+
+/*******************  Bit definition for I2C_STS1 register  ********************/
+#define I2C_STS1_STARTBF  ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
+#define I2C_STS1_ADDRF    ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_STS1_BSF      ((uint16_t)0x0004) /*!< Byte Transfer Finished */
+#define I2C_STS1_ADDR10F  ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
+#define I2C_STS1_STOPF    ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
+#define I2C_STS1_RXDATNE  ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
+#define I2C_STS1_TXDATE   ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
+#define I2C_STS1_BUSERR   ((uint16_t)0x0100) /*!< Bus Error */
+#define I2C_STS1_ARLOST   ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
+#define I2C_STS1_ACKFAIL  ((uint16_t)0x0400) /*!< Acknowledge Failure */
+#define I2C_STS1_OVERRUN  ((uint16_t)0x0800) /*!< Overrun/Underrun */
+#define I2C_STS1_PECERR   ((uint16_t)0x1000) /*!< PEC Error in reception */
+#define I2C_STS1_TIMOUT   ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
+#define I2C_STS1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
+
+/*******************  Bit definition for I2C_STS2 register  ********************/
+#define I2C_STS2_MSMODE    ((uint16_t)0x0001) /*!< Master/Slave */
+#define I2C_STS2_BUSY      ((uint16_t)0x0002) /*!< Bus Busy */
+#define I2C_STS2_TRF       ((uint16_t)0x0004) /*!< Transmitter/Receiver */
+#define I2C_STS2_GCALLADDR ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
+#define I2C_STS2_SMBDADDR  ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_STS2_SMBHADDR  ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
+#define I2C_STS2_DUALFLAG  ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
+#define I2C_STS2_PECVAL    ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CLKCTRL register  ********************/
+#define I2C_CLKCTRL_CLKCTRL ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CLKCTRL_DUTY    ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
+#define I2C_CLKCTRL_FSMODE  ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define I2C_TMRISE_TMRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_STS register  *******************/
+#define USART_STS_PEF    ((uint16_t)0x0001) /*!< Parity Error */
+#define USART_STS_FEF    ((uint16_t)0x0002) /*!< Framing Error */
+#define USART_STS_NEF    ((uint16_t)0x0004) /*!< Noise Error Flag */
+#define USART_STS_OREF   ((uint16_t)0x0008) /*!< OverRun Error */
+#define USART_STS_IDLEF  ((uint16_t)0x0010) /*!< IDLE line detected */
+#define USART_STS_RXDNE  ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
+#define USART_STS_TXC    ((uint16_t)0x0040) /*!< Transmission Complete */
+#define USART_STS_TXDE   ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
+#define USART_STS_LINBDF ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
+#define USART_STS_CTSF   ((uint16_t)0x0200) /*!< CTS Flag */
+
+/*******************  Bit definition for USART_DAT register  *******************/
+#define USART_DAT_DATV ((uint16_t)0x01FF) /*!< Data value */
+
+/******************  Bit definition for USART_BRCF register  *******************/
+#define USART_BRCF_DIV_Decimal ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
+#define USART_BRCF_DIV_Integer ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CTRL1 register  *******************/
+#define USART_CTRL1_SDBRK    ((uint16_t)0x0001) /*!< Send Break */
+#define USART_CTRL1_RCVWU    ((uint16_t)0x0002) /*!< Receiver wakeup */
+#define USART_CTRL1_RXEN     ((uint16_t)0x0004) /*!< Receiver Enable */
+#define USART_CTRL1_TXEN     ((uint16_t)0x0008) /*!< Transmitter Enable */
+#define USART_CTRL1_IDLEIEN  ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
+#define USART_CTRL1_RXDNEIEN ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
+#define USART_CTRL1_TXCIEN   ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CTRL1_TXDEIEN  ((uint16_t)0x0080) /*!< PE Interrupt Enable */
+#define USART_CTRL1_PEIEN    ((uint16_t)0x0100) /*!< PE Interrupt Enable */
+#define USART_CTRL1_PSEL     ((uint16_t)0x0200) /*!< Parity Selection */
+#define USART_CTRL1_PCEN     ((uint16_t)0x0400) /*!< Parity Control Enable */
+#define USART_CTRL1_WUM      ((uint16_t)0x0800) /*!< Wakeup method */
+#define USART_CTRL1_WL       ((uint16_t)0x1000) /*!< Word length */
+#define USART_CTRL1_UEN      ((uint16_t)0x2000) /*!< USART Enable */
+
+/******************  Bit definition for USART_CTRL2 register  *******************/
+#define USART_CTRL2_ADDR        ((uint16_t)0x000F) /*!< Address of the USART node */
+#define USART_CTRL2_LINBDL      ((uint16_t)0x0020) /*!< LIN Break Detection Length */
+#define USART_CTRL2_LINBDIEN    ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CTRL2_LBCLK       ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
+#define USART_CTRL2_CLKPHA      ((uint16_t)0x0200) /*!< Clock Phase */
+#define USART_CTRL2_CLKPOL      ((uint16_t)0x0400) /*!< Clock Polarity */
+#define USART_CTRL2_CLKEN       ((uint16_t)0x0800) /*!< Clock Enable */
+
+#define USART_CTRL2_STPB   ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CTRL2_STPB_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USART_CTRL2_STPB_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USART_CTRL2_LINMEN ((uint16_t)0x4000) /*!< LIN mode enable */
+
+/******************  Bit definition for USART_CTRL3 register  *******************/
+#define USART_CTRL3_ERRIEN  ((uint16_t)0x0001) /*!< Error Interrupt Enable */
+#define USART_CTRL3_IRDAMEN ((uint16_t)0x0002) /*!< IrDA mode Enable */
+#define USART_CTRL3_IRDALP  ((uint16_t)0x0004) /*!< IrDA Low-Power */
+#define USART_CTRL3_HDMEN   ((uint16_t)0x0008) /*!< Half-Duplex Selection */
+#define USART_CTRL3_SCNACK  ((uint16_t)0x0010) /*!< Smartcard NACK enable */
+#define USART_CTRL3_SCMEN   ((uint16_t)0x0020) /*!< Smartcard mode enable */
+#define USART_CTRL3_DMARXEN ((uint16_t)0x0040) /*!< DMA Enable Receiver */
+#define USART_CTRL3_DMATXEN ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
+#define USART_CTRL3_RTSEN   ((uint16_t)0x0100) /*!< RTS Enable */
+#define USART_CTRL3_CTSEN   ((uint16_t)0x0200) /*!< CTS Enable */
+#define USART_CTRL3_CTSIEN  ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
+
+/******************  Bit definition for USART_GTP register  ******************/
+#define USART_GTP_PSCV   ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTP_PSCV_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define USART_GTP_PSCV_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define USART_GTP_PSCV_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define USART_GTP_PSCV_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define USART_GTP_PSCV_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define USART_GTP_PSCV_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define USART_GTP_PSCV_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define USART_GTP_PSCV_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define USART_GTP_GTV ((uint16_t)0xFF00) /*!< Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*          Low-power Universal Asynchronous Receiver Transmitter             */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for LPUART_STS register  ******************/
+#define LPUART_STS_PEF      ((uint16_t)0x0001) /*!< Parity Check Error Flag */
+#define LPUART_STS_TXC      ((uint16_t)0x0002) /*!< TX Complete Flag */
+#define LPUART_STS_FIFO_OV  ((uint16_t)0x0004) /*!< FIFO Overflow Flag */
+#define LPUART_STS_FIFO_FU  ((uint16_t)0x0008) /*!< FIFO Full Flag */
+#define LPUART_STS_FIFO_HF  ((uint16_t)0x0010) /*!< FIFO Half Full Flag */
+#define LPUART_STS_FIFO_NE  ((uint16_t)0x0020) /*!< FIFO Non-Empty Flag */
+#define LPUART_STS_CTS      ((uint16_t)0x0040) /*!< Clear to Send (Hardware Flow Control) Flag */
+#define LPUART_STS_WUF      ((uint16_t)0x0080) /*!< Wakeup from Stop mode Flag */
+#define LPUART_STS_NF       ((uint16_t)0x0100) /*!< Noise Detected Flag */
+
+/******************  Bit definition for LPUART_INTEN register  ******************/
+#define LPUART_INTEN_PEIE       ((uint8_t)0x01) /*!< Parity Check Error Interrupt Enable */
+#define LPUART_INTEN_TXCIE      ((uint8_t)0x02) /*!< TX Complete Interrupt Enable */
+#define LPUART_INTEN_FIFO_OVIE  ((uint8_t)0x04) /*!< FIFO Overflow Interrupt Enable */
+#define LPUART_INTEN_FIFO_FUIE  ((uint8_t)0x08) /*!< FIFO Full Interrupt Enable*/
+#define LPUART_INTEN_FIFO_HFIE  ((uint8_t)0x10) /*!< FIFO Half Full Interrupt Enable */
+#define LPUART_INTEN_FIFO_NEIE  ((uint8_t)0x20) /*!< FIFO Non-Empty Interrupt Enable */
+#define LPUART_INTEN_WUFIE      ((uint8_t)0x40) /*!< Wakeup Interrupt Enable */
+
+/******************  Bit definition for LPUART_CTRL register  ******************/
+#define LPUART_CTRL_PSEL      ((uint16_t)0x0001) /*!< Odd Parity Bit Enable */
+#define LPUART_CTRL_TXEN      ((uint16_t)0x0002) /*!< TX Enable */
+#define LPUART_CTRL_FLUSH     ((uint16_t)0x0004) /*!< Flush Receiver FIFO Enable */
+#define LPUART_CTRL_PCDIS     ((uint16_t)0x0008) /*!< Parity Control Disable */
+#define LPUART_CTRL_LOOPBACK  ((uint16_t)0x0010) /*!< Loop Back Self-Test */
+#define LPUART_CTRL_DMA_TXEN  ((uint16_t)0x0020) /*!< DMA TX Request Enable */
+#define LPUART_CTRL_DMA_RXEN  ((uint16_t)0x0040) /*!< DMA RX Request Enable */
+#define LPUART_CTRL_WUSTP     ((uint16_t)0x0080) /*!< LPUART Wakeup Enable in Stop mode */
+#define LPUART_CTRL_RTS_THSEL ((uint16_t)0x0300) /*!< RTS Threshold Selection */
+#define LPUART_CTRL_CTSEN     ((uint16_t)0x0400) /*!< Hardware Flow Control TX Enable */
+#define LPUART_CTRL_RTSEN     ((uint16_t)0x0800) /*!< Hardware Flow Control RX Enable */
+#define LPUART_CTRL_WUSEL     ((uint16_t)0x3000) /*!< Wakeup Event Selection */
+#define LPUART_CTRL_SMPCNT    ((uint16_t)0x4000) /*!< Specify the Sampling Method */
+
+/******************  Bit definition for LPUART_BRCFG1 register  ******************/
+#define LPUART_BRCFG1_INTEGER  ((uint16_t)0xFFFF) /*!< Baud Rate Parameter Configeration Register1: Fraction */
+
+/******************  Bit definition for LPUART_DAT register  ******************/
+#define LPUART_DAT_DAT  ((uint8_t)0xFF) /*!< Data Register */
+
+/******************  Bit definition for LPUART_BRCFG2 register  ******************/
+#define LPUART_BRCFG2_DECIMAL  ((uint8_t)0xFF) /*!< Baud Rate Parameter Configeration Register2: Mantissa */
+
+/******************  Bit definition for LPUART_WUDAT register  ******************/
+#define LPUART_WUDAT_WUDAT  ((uint32_t)0xFFFFFFFF) /*!< Data Register */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBG_ID register  *****************/
+#define DBG_ID_DEV ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBG_ID_REV    ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBG_ID_REV_0  ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBG_ID_REV_1  ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBG_ID_REV_2  ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBG_ID_REV_3  ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBG_ID_REV_4  ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBG_ID_REV_5  ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBG_ID_REV_6  ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBG_ID_REV_7  ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBG_ID_REV_8  ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBG_ID_REV_9  ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBG_ID_REV_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBG_ID_REV_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBG_ID_REV_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBG_ID_REV_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBG_ID_REV_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBG_ID_REV_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/******************  Bit definition for DBG_CTRL register  *******************/
+#define DBG_CTRL_SLEEP  ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
+#define DBG_CTRL_STOP   ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBG_CTRL_STDBY  ((uint32_t)0x00000004) /*!< Debug Standby mode */
+
+#define DBG_CTRL_IWDG_STOP    ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBG_CTRL_WWDG_STOP    ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBG_CTRL_TIM1_STOP    ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
+#define DBG_CTRL_TIM2_STOP    ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
+#define DBG_CTRL_TIM3_STOP    ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
+#define DBG_CTRL_TIM4_STOP    ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
+#define DBG_CTRL_CAN_STOP     ((uint32_t)0x00004000) /*!< Debug CAN stopped when Core is halted */
+#define DBG_CTRL_I2C1SMBUS_TO ((uint32_t)0x00008000) /*!< SMBUS I2C1 timeout mode stopped when Core is halted */
+#define DBG_CTRL_I2C2SMBUS_TO ((uint32_t)0x00010000) /*!< SMBUS I2C2 timeout mode stopped when Core is halted */
+#define DBG_CTRL_TIM8_STOP    ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */
+#define DBG_CTRL_TIM5_STOP    ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */
+#define DBG_CTRL_TIM6_STOP    ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */
+#define DBG_CTRL_TIM7_STOP    ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */
+#define DBG_CTRL_TIM9_STOP    ((uint32_t)0x00200000) /*!< TIM9 counter stopped when core is halted*/
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_AC register  ******************/
+#define FLASH_AC_LATENCY   ((uint32_t)0x00000003) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_AC_LATENCY_0 ((uint32_t)0x00000000) /*!< Bit 0 = 0 */
+#define FLASH_AC_LATENCY_1 ((uint32_t)0x00000001) /*!< Bit 0 = 1 */
+#define FLASH_AC_LATENCY_2 ((uint32_t)0x00000002) /*!< Bit 0 = 0; Bit 1 = 1 */
+#define FLASH_AC_LATENCY_3 ((uint32_t)0x00000003) /*!< Bit 0 = 1; Bit 1 = 1 */
+
+#define FLASH_AC_PRFTBFEN  ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_AC_PRFTBFSTS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+#define FLASH_AC_ICAHRST   ((uint32_t)0x00000040) /*!< Icache Reset */
+#define FLASH_AC_ICAHEN    ((uint32_t)0x00000080) /*!< Icache Enable */
+#define FLASH_AC_LVMF      ((uint32_t)0x00000100) /*!< Flash low power work mode status */
+#define FLASH_AC_LVMEN     ((uint32_t)0x00000200) /*!< Flash low power work mode Enable */
+#define FLASH_AC_SLMF      ((uint32_t)0x00000400) /*!< Flash sleep mode status */
+#define FLASH_AC_SLMEN     ((uint32_t)0x00000800) /*!< Flash sleep mode Enable */
+
+/******************  Bit definition for FLASH_KEY register  ******************/
+#define FLASH_KEY_FKEY ((uint32_t)0xFFFFFFFF) /*!< FLASH Key */
+
+/*****************  Bit definition for FLASH_OPTKEY register  ****************/
+#define FLASH_OPTKEY_OPTKEY ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/******************  Bit definition for FLASH_STS register  *******************/
+#define FLASH_STS_BUSY     ((uint8_t)0x01) /*!< Busy */
+#define FLASH_STS_PGERR    ((uint8_t)0x04) /*!< Programming Error */
+#define FLASH_STS_PVERR    ((uint8_t)0x08) /*!< Programming Verify ERROR after program */
+#define FLASH_STS_WRPERR   ((uint8_t)0x10) /*!< Write Protection Error */
+#define FLASH_STS_EOP      ((uint8_t)0x20) /*!< End of operation */
+#define FLASH_STS_EVERR    ((uint8_t)0x40) /*!< Erase Verify ERROR after page erase */
+
+/*******************  Bit definition for FLASH_CTRL register  *******************/
+#define FLASH_CTRL_PG        ((uint16_t)0x0001) /*!< Programming */
+#define FLASH_CTRL_PER       ((uint16_t)0x0002) /*!< Page Erase */
+#define FLASH_CTRL_MER       ((uint16_t)0x0004) /*!< Mass Erase */
+#define FLASH_CTRL_OPTPG     ((uint16_t)0x0010) /*!< Option Byte Programming */
+#define FLASH_CTRL_OPTER     ((uint16_t)0x0020) /*!< Option Byte Erase */
+#define FLASH_CTRL_START     ((uint16_t)0x0040) /*!< Start */
+#define FLASH_CTRL_LOCK      ((uint16_t)0x0080) /*!< Lock */
+#define FLASH_CTRL_SMPSEL    ((uint16_t)0x0100) /*!< Flash Program Option Select */
+#define FLASH_CTRL_OPTWE     ((uint16_t)0x0200) /*!< Option Bytes Write Enable */
+#define FLASH_CTRL_ERRITE    ((uint16_t)0x0400) /*!< Error Interrupt Enable */
+#define FLASH_CTRL_FERRITE   ((uint16_t)0x0800) /*!< EVERR PVERR Error Interrupt Enable */
+#define FLASH_CTRL_EOPITE    ((uint16_t)0x1000) /*!< End of operation Interrupt Enable */
+
+/*******************  Bit definition for FLASH_ADD register  *******************/
+#define FLASH_ADD_FADD ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OB2 register  *******************/
+#define FLASH_OB2_BOR_LEV  ((uint32_t)0x00000700) /*!< BOR_LEV[2:0] */
+#define FLASH_OB2_nBOOT1   ((uint32_t)0x00800000) /*!< nBOOT1 */
+#define FLASH_OB2_nSWBOOT0 ((uint32_t)0x04000000) /*!< nSWBOOT0 */
+#define FLASH_OB2_nBOOT0   ((uint32_t)0x08000000) /*!< nBOOT1 */
+
+/******************  Bit definition for FLASH_OB register  *******************/
+#define FLASH_OB_OBERR   ((uint16_t)0x0001) /*!< Option Byte Error */
+#define FLASH_OB_RDPRT1 ((uint16_t)0x0002) /*!< Read Protection */
+
+#define FLASH_OB_USER       ((uint16_t)0x03FC) /*!< User Option Bytes */
+#define FLASH_OB_WDG_SW     ((uint16_t)0x0004) /*!< WDG_SW */
+#define FLASH_OB_NRST_STOP2 ((uint16_t)0x0008) /*!< nRST_STOP2 */
+#define FLASH_OB_NRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */
+#define FLASH_OB_NRST_PD    ((uint16_t)0x0020) /*!< nRST_PD */
+
+#define FLASH_OB_DATA0_MSK ((uint32_t)0x0003FC00) /*!< Data0 Mask */
+#define FLASH_OB_DATA1_MSK ((uint32_t)0x03FC0000) /*!< Data1 Mask */
+#define FLASH_OB_RDPRT2    ((uint32_t)0x80000000) /*!< Read Protection Level 2 */
+
+/******************  Bit definition for FLASH_WRP register  ******************/
+#define FLASH_WRP_WRPT ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/******************  Bit definition for FLASH_CAHR register  ******************/
+#define FLASH_CAHR_LOCKSTRT_MSK ((uint32_t)0x000F) /*!< LOCKSTRT Mask */
+#define FLASH_CAHR_LOCKSTOP_MSK ((uint32_t)0x00F0) /*!< LOCKSTOP Mask */
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OptionByte USER  ******************/
+#define FLASH_RDP_RDP1  ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define FLASH_RDP_NRDP1 ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OptionByte USER  ******************/
+#define FLASH_USER_USER  ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_NUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/******************  Bit definition for OptionByte Data0  *****************/
+#define FLASH_Data0_Data0  ((uint32_t)0x000000FF) /*!< User data storage option byte */
+#define FLASH_Data0_NData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
+
+/******************  Bit definition for OptionByte Data1  *****************/
+#define FLASH_Data1_Data1  ((uint32_t)0x00FF0000) /*!< User data storage option byte */
+#define FLASH_Data1_NData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
+
+/******************  Bit definition for OptionByte WRP0  ******************/
+#define FLASH_WRP0_WRP0  ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_NWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OptionByte WRP1  ******************/
+#define FLASH_WRP1_WRP1  ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_NWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OptionByte WRP2  ******************/
+#define FLASH_WRP2_WRP2  ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_NWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OptionByte WRP3  ******************/
+#define FLASH_WRP3_WRP3  ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_NWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OptionByte RDP2  *******************/
+#define FLASH_RDP_RDP2  ((uint32_t)0x000000FF) /*!< Read protection level 2 option byte */
+#define FLASH_RDP_NRDP2 ((uint32_t)0x0000FF00) /*!< Read protection level 2 complemented option byte */
+
+/******************  Bit definition for OptionByte USER2  ******************/
+#define FLASH_USER_USER2  ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_NUSER2 ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/******************************************************************************/
+/*                                                                            */
+/*                General Purpose and Alternate Function I/O                  */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for GPIO_PMODE register  *******************/
+
+
+#define GPIO_PMODE0_Pos            (0)
+#define GPIO_PMODE0_Msk            (0x3 << GPIO_PMODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE0                GPIO_PMODE0_Msk
+#define GPIO_PMODE0_0              (0x0 << GPIO_PMODE0_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE0_1              (0x1 << GPIO_PMODE0_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE0_2              (0x2 << GPIO_PMODE0_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE0_3              (0x3 << GPIO_PMODE0_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE1_Pos            (2)
+#define GPIO_PMODE1_Msk            (0x3 << GPIO_PMODE1_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE1                GPIO_PMODE1_Msk
+#define GPIO_PMODE1_0              (0x0 << GPIO_PMODE1_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE1_1              (0x1 << GPIO_PMODE1_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE1_2              (0x2 << GPIO_PMODE1_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE1_3              (0x3 << GPIO_PMODE1_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE2_Pos            (4)
+#define GPIO_PMODE2_Msk            (0x3 << GPIO_PMODE2_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE2                GPIO_PMODE2_Msk
+#define GPIO_PMODE2_0              (0x0 << GPIO_PMODE2_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE2_1              (0x1 << GPIO_PMODE2_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE2_2              (0x2 << GPIO_PMODE2_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE2_3              (0x3 << GPIO_PMODE2_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE3_Pos            (6)
+#define GPIO_PMODE3_Msk            (0x3 << GPIO_PMODE3_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE3                GPIO_PMODE3_Msk
+#define GPIO_PMODE3_0              (0x0 << GPIO_PMODE3_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE3_1              (0x1 << GPIO_PMODE3_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE3_2              (0x2 << GPIO_PMODE3_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE3_3              (0x3 << GPIO_PMODE3_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE4_Pos            (8)
+#define GPIO_PMODE4_Msk            (0x3 << GPIO_PMODE4_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE4                GPIO_PMODE4_Msk
+#define GPIO_PMODE4_0              (0x0 << GPIO_PMODE4_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE4_1              (0x1 << GPIO_PMODE4_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE4_2              (0x2 << GPIO_PMODE4_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE4_3              (0x3 << GPIO_PMODE4_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE5_Pos            (10)
+#define GPIO_PMODE5_Msk            (0x3 << GPIO_PMODE5_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE5                GPIO_PMODE5_Msk
+#define GPIO_PMODE5_0              (0x0 << GPIO_PMODE5_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE5_1              (0x1 << GPIO_PMODE5_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE5_2              (0x2 << GPIO_PMODE5_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE5_3              (0x3 << GPIO_PMODE5_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE6_Pos            (12)
+#define GPIO_PMODE6_Msk            (0x3 << GPIO_PMODE6_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE6                GPIO_PMODE6_Msk
+#define GPIO_PMODE6_0              (0x0 << GPIO_PMODE6_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE6_1              (0x1 << GPIO_PMODE6_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE6_2              (0x2 << GPIO_PMODE6_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE6_3              (0x3 << GPIO_PMODE6_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE7_Pos            (14)
+#define GPIO_PMODE7_Msk            (0x3 << GPIO_PMODE7_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE7                GPIO_PMODE7_Msk
+#define GPIO_PMODE7_0              (0x0 << GPIO_PMODE7_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE7_1              (0x1 << GPIO_PMODE7_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE7_2              (0x2 << GPIO_PMODE7_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE7_3              (0x3 << GPIO_PMODE7_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE8_Pos            (16)
+#define GPIO_PMODE8_Msk            (0x3 << GPIO_PMODE8_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE8                GPIO_PMODE8_Msk
+#define GPIO_PMODE8_0              (0x0 << GPIO_PMODE8_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE8_1              (0x1 << GPIO_PMODE8_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE8_2              (0x2 << GPIO_PMODE8_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE8_3              (0x3 << GPIO_PMODE8_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE9_Pos            (18)
+#define GPIO_PMODE9_Msk            (0x3 << GPIO_PMODE9_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE9                GPIO_PMODE9_Msk
+#define GPIO_PMODE9_0              (0x0 << GPIO_PMODE9_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE9_1              (0x1 << GPIO_PMODE9_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE9_2              (0x2 << GPIO_PMODE9_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE9_3              (0x3 << GPIO_PMODE9_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE10_Pos            (20)
+#define GPIO_PMODE10_Msk            (0x3 << GPIO_PMODE10_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE10                GPIO_PMODE10_Msk
+#define GPIO_PMODE10_0              (0x0 << GPIO_PMODE10_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE10_1              (0x1 << GPIO_PMODE10_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE10_2              (0x2 << GPIO_PMODE10_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE10_3              (0x3 << GPIO_PMODE10_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE11_Pos            (22)
+#define GPIO_PMODE11_Msk            (0x3 << GPIO_PMODE11_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE11                GPIO_PMODE11_Msk
+#define GPIO_PMODE11_0              (0x0 << GPIO_PMODE11_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE11_1              (0x1 << GPIO_PMODE11_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE11_2              (0x2 << GPIO_PMODE11_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE11_3              (0x3 << GPIO_PMODE11_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE12_Pos            (24)
+#define GPIO_PMODE12_Msk            (0x3 << GPIO_PMODE12_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE12                GPIO_PMODE12_Msk
+#define GPIO_PMODE12_0              (0x0 << GPIO_PMODE12_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE12_1              (0x1 << GPIO_PMODE12_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE12_2              (0x2 << GPIO_PMODE12_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE12_3              (0x3 << GPIO_PMODE12_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE13_Pos            (26)
+#define GPIO_PMODE13_Msk            (0x3 << GPIO_PMODE13_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE13                GPIO_PMODE13_Msk
+#define GPIO_PMODE13_0              (0x0 << GPIO_PMODE13_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE13_1              (0x1 << GPIO_PMODE13_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE13_2              (0x2 << GPIO_PMODE13_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE13_3              (0x3 << GPIO_PMODE13_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE14_Pos            (28)
+#define GPIO_PMODE14_Msk            (0x3 << GPIO_PMODE14_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE14                GPIO_PMODE14_Msk
+#define GPIO_PMODE14_0              (0x0 << GPIO_PMODE14_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE14_1              (0x1 << GPIO_PMODE14_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE14_2              (0x2 << GPIO_PMODE14_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE14_3              (0x3 << GPIO_PMODE14_Pos)         /*!< 0x00000003 */
+
+#define GPIO_PMODE15_Pos            (30)
+#define GPIO_PMODE15_Msk            (0x3 << GPIO_PMODE15_Pos)         /*!< 0x00000003 */
+#define GPIO_PMODE15                GPIO_PMODE15_Msk
+#define GPIO_PMODE15_0              (0x0 << GPIO_PMODE15_Pos)         /*!< 0x00000000 */
+#define GPIO_PMODE15_1              (0x1 << GPIO_PMODE15_Pos)         /*!< 0x00000001 */
+#define GPIO_PMODE15_2              (0x2 << GPIO_PMODE15_Pos)         /*!< 0x00000002 */
+#define GPIO_PMODE15_3              (0x3 << GPIO_PMODE15_Pos)         /*!< 0x00000003 */
+
+
+
+
+/******************  Bit definition for GPIO_POTYPER register  *****************/
+#define GPIO_POTYPE_POT_0                (0x00000001)
+#define GPIO_POTYPE_POT_1                (0x00000002)
+#define GPIO_POTYPE_POT_2                (0x00000004)
+#define GPIO_POTYPE_POT_3                (0x00000008)
+#define GPIO_POTYPE_POT_4                (0x00000010)
+#define GPIO_POTYPE_POT_5                (0x00000020)
+#define GPIO_POTYPE_POT_6                (0x00000040)
+#define GPIO_POTYPE_POT_7                (0x00000080)
+#define GPIO_POTYPE_POT_8                (0x00000100)
+#define GPIO_POTYPE_POT_9                (0x00000200)
+#define GPIO_POTYPE_POT_10               (0x00000400)
+#define GPIO_POTYPE_POT_11               (0x00000800)
+#define GPIO_POTYPE_POT_12               (0x00001000)
+#define GPIO_POTYPE_POT_13               (0x00002000)
+#define GPIO_POTYPE_POT_14               (0x00004000)
+#define GPIO_POTYPE_POT_15               (0x00008000)
+
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPD0_Pos            (0)
+#define GPIO_PUPD0_Msk            (0x3 << GPIO_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD0                GPIO_PUPD0_Msk
+#define GPIO_PUPD0_0              (0x0 << GPIO_PUPD0_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD0_1              (0x1 << GPIO_PUPD0_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD0_2              (0x2 << GPIO_PUPD0_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD1_Pos            (2)
+#define GPIO_PUPD1_Msk            (0x3 << GPIO_PUPD1_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD1                GPIO_PUPD1_Msk
+#define GPIO_PUPD1_0              (0x0 << GPIO_PUPD1_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD1_1              (0x1 << GPIO_PUPD1_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD1_2              (0x2 << GPIO_PUPD1_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD2_Pos            (4)
+#define GPIO_PUPD2_Msk            (0x3 << GPIO_PUPD2_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD2                GPIO_PUPD2_Msk
+#define GPIO_PUPD2_0              (0x0 << GPIO_PUPD2_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD2_1              (0x1 << GPIO_PUPD2_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD2_2              (0x2 << GPIO_PUPD2_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD3_Pos            (6)
+#define GPIO_PUPD3_Msk            (0x3 << GPIO_PUPD3_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD3                GPIO_PUPD3_Msk
+#define GPIO_PUPD3_0              (0x0 << GPIO_PUPD3_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD3_1              (0x1 << GPIO_PUPD3_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD3_2              (0x2 << GPIO_PUPD3_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD4_Pos            (8)
+#define GPIO_PUPD4_Msk            (0x3 << GPIO_PUPD4_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD4                GPIO_PUPD4_Msk
+#define GPIO_PUPD4_0              (0x0 << GPIO_PUPD4_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD4_1              (0x1 << GPIO_PUPD4_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD4_2              (0x2 << GPIO_PUPD4_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD5_Pos            (10)
+#define GPIO_PUPD5_Msk            (0x3 << GPIO_PUPD5_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD5                GPIO_PUPD5_Msk
+#define GPIO_PUPD5_0              (0x0 << GPIO_PUPD5_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD5_1              (0x1 << GPIO_PUPD5_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD5_2              (0x2 << GPIO_PUPD5_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD6_Pos            (12)
+#define GPIO_PUPD6_Msk            (0x3 << GPIO_PUPD6_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD6                GPIO_PUPD6_Msk
+#define GPIO_PUPD6_0              (0x0 << GPIO_PUPD6_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD6_1              (0x1 << GPIO_PUPD6_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD6_2              (0x2 << GPIO_PUPD6_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD7_Pos            (14)
+#define GPIO_PUPD7_Msk            (0x3 << GPIO_PUPD7_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD7                GPIO_PUPD7_Msk
+#define GPIO_PUPD7_0              (0x0 << GPIO_PUPD7_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD7_1              (0x1 << GPIO_PUPD7_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD7_2              (0x2 << GPIO_PUPD7_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD8_Pos            (16)
+#define GPIO_PUPD8_Msk            (0x3 << GPIO_PUPD8_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD8                GPIO_PUPD8_Msk
+#define GPIO_PUPD8_0              (0x0 << GPIO_PUPD8_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD8_1              (0x1 << GPIO_PUPD8_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD8_2              (0x2 << GPIO_PUPD8_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD9_Pos            (18)
+#define GPIO_PUPD9_Msk            (0x3 << GPIO_PUPD9_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD9                GPIO_PUPD9_Msk
+#define GPIO_PUPD9_0              (0x0 << GPIO_PUPD9_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD9_1              (0x1 << GPIO_PUPD9_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD9_2              (0x2 << GPIO_PUPD9_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD10_Pos             (20)
+#define GPIO_PUPD10_Msk            (0x3 << GPIO_PUPD10_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD10                GPIO_PUPD10_Msk
+#define GPIO_PUPD10_0              (0x0 << GPIO_PUPD10_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD10_1              (0x1 << GPIO_PUPD10_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD10_2              (0x2 << GPIO_PUPD10_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD11_Pos            (22)
+#define GPIO_PUPD11_Msk            (0x3 << GPIO_PUPD11_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD11                GPIO_PUPD11_Msk
+#define GPIO_PUPD11_0              (0x0 << GPIO_PUPD11_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD11_1              (0x1 << GPIO_PUPD11_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD11_2              (0x2 << GPIO_PUPD11_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD12_Pos            (24)
+#define GPIO_PUPD12_Msk            (0x3 << GPIO_PUPD12_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD12                GPIO_PUPD12_Msk
+#define GPIO_PUPD12_0              (0x0 << GPIO_PUPD12_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD12_1              (0x1 << GPIO_PUPD12_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD12_2              (0x2 << GPIO_PUPD12_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD13_Pos            (26)
+#define GPIO_PUPD13_Msk            (0x3 << GPIO_PUPD13_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD13                GPIO_PUPD13_Msk
+#define GPIO_PUPD13_0              (0x0 << GPIO_PUPD13_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD13_1              (0x1 << GPIO_PUPD13_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD13_2              (0x2 << GPIO_PUPD13_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD14_Pos            (28)
+#define GPIO_PUPD14_Msk            (0x3 << GPIO_PUPD14_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD14                GPIO_PUPD14_Msk
+#define GPIO_PUPD14_0              (0x0 << GPIO_PUPD14_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD14_1              (0x1 << GPIO_PUPD14_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD14_2              (0x2 << GPIO_PUPD14_Pos)         /*!< 0x00000002 */
+
+#define GPIO_PUPD15_Pos            (30)
+#define GPIO_PUPD15_Msk            (0x3 << GPIO_PUPD15_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPD15                GPIO_PUPD15_Msk
+#define GPIO_PUPD15_0              (0x0 << GPIO_PUPD15_Pos)         /*!< 0x00000000 */
+#define GPIO_PUPD15_1              (0x1 << GPIO_PUPD15_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPD15_2              (0x2 << GPIO_PUPD15_Pos)         /*!< 0x00000002 */
+
+
+/*!<******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_PID_PID0  ((uint16_t)0x0001) /*!< Port input data, bit 0 */
+#define GPIO_PID_PID1  ((uint16_t)0x0002) /*!< Port input data, bit 1 */
+#define GPIO_PID_PID2  ((uint16_t)0x0004) /*!< Port input data, bit 2 */
+#define GPIO_PID_PID3  ((uint16_t)0x0008) /*!< Port input data, bit 3 */
+#define GPIO_PID_PID4  ((uint16_t)0x0010) /*!< Port input data, bit 4 */
+#define GPIO_PID_PID5  ((uint16_t)0x0020) /*!< Port input data, bit 5 */
+#define GPIO_PID_PID6  ((uint16_t)0x0040) /*!< Port input data, bit 6 */
+#define GPIO_PID_PID7  ((uint16_t)0x0080) /*!< Port input data, bit 7 */
+#define GPIO_PID_PID8  ((uint16_t)0x0100) /*!< Port input data, bit 8 */
+#define GPIO_PID_PID9  ((uint16_t)0x0200) /*!< Port input data, bit 9 */
+#define GPIO_PID_PID10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
+#define GPIO_PID_PID11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
+#define GPIO_PID_PID12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
+#define GPIO_PID_PID13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
+#define GPIO_PID_PID14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
+#define GPIO_PID_PID15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
+
+/*******************  Bit definition for GPIO_POD register  *******************/
+#define GPIO_POD_POD0  ((uint16_t)0x0001) /*!< Port output data, bit 0 */
+#define GPIO_POD_POD1  ((uint16_t)0x0002) /*!< Port output data, bit 1 */
+#define GPIO_POD_POD2  ((uint16_t)0x0004) /*!< Port output data, bit 2 */
+#define GPIO_POD_POD3  ((uint16_t)0x0008) /*!< Port output data, bit 3 */
+#define GPIO_POD_POD4  ((uint16_t)0x0010) /*!< Port output data, bit 4 */
+#define GPIO_POD_POD5  ((uint16_t)0x0020) /*!< Port output data, bit 5 */
+#define GPIO_POD_POD6  ((uint16_t)0x0040) /*!< Port output data, bit 6 */
+#define GPIO_POD_POD7  ((uint16_t)0x0080) /*!< Port output data, bit 7 */
+#define GPIO_POD_POD8  ((uint16_t)0x0100) /*!< Port output data, bit 8 */
+#define GPIO_POD_POD9  ((uint16_t)0x0200) /*!< Port output data, bit 9 */
+#define GPIO_POD_POD10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
+#define GPIO_POD_POD11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
+#define GPIO_POD_POD12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
+#define GPIO_POD_POD13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
+#define GPIO_POD_POD14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
+#define GPIO_POD_POD15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
+
+/******************  Bit definition for GPIO_BSRR register  *******************/
+#define GPIO_PBSC_PBS0  ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
+#define GPIO_PBSC_PBS1  ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
+#define GPIO_PBSC_PBS2  ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
+#define GPIO_PBSC_PBS3  ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
+#define GPIO_PBSC_PBS4  ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
+#define GPIO_PBSC_PBS5  ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
+#define GPIO_PBSC_PBS6  ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
+#define GPIO_PBSC_PBS7  ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
+#define GPIO_PBSC_PBS8  ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
+#define GPIO_PBSC_PBS9  ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
+#define GPIO_PBSC_PBS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
+#define GPIO_PBSC_PBS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
+#define GPIO_PBSC_PBS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
+#define GPIO_PBSC_PBS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
+#define GPIO_PBSC_PBS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
+#define GPIO_PBSC_PBS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
+
+#define GPIO_PBSC_PBC0  ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
+#define GPIO_PBSC_PBC1  ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
+#define GPIO_PBSC_PBC2  ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
+#define GPIO_PBSC_PBC3  ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
+#define GPIO_PBSC_PBC4  ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
+#define GPIO_PBSC_PBC5  ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
+#define GPIO_PBSC_PBC6  ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
+#define GPIO_PBSC_PBC7  ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
+#define GPIO_PBSC_PBC8  ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
+#define GPIO_PBSC_PBC9  ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
+#define GPIO_PBSC_PBC10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
+#define GPIO_PBSC_PBC11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
+#define GPIO_PBSC_PBC12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
+#define GPIO_PBSC_PBC13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
+#define GPIO_PBSC_PBC14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
+#define GPIO_PBSC_PBC15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
+
+/*******************  Bit definition for GPIO_BRR register  *******************/
+#define GPIO_PBC_PBC0  ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
+#define GPIO_PBC_PBC1  ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
+#define GPIO_PBC_PBC2  ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
+#define GPIO_PBC_PBC3  ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
+#define GPIO_PBC_PBC4  ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
+#define GPIO_PBC_PBC5  ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
+#define GPIO_PBC_PBC6  ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
+#define GPIO_PBC_PBC7  ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
+#define GPIO_PBC_PBC8  ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
+#define GPIO_PBC_PBC9  ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
+#define GPIO_PBC_PBC10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
+#define GPIO_PBC_PBC11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
+#define GPIO_PBC_PBC12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
+#define GPIO_PBC_PBC13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
+#define GPIO_PBC_PBC14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
+#define GPIO_PBC_PBC15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
+
+/******************  Bit definition for GPIO_LCKR register  *******************/
+#define GPIO_PLOCK_PLOCK0  ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
+#define GPIO_PLOCK_PLOCK1  ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
+#define GPIO_PLOCK_PLOCK2  ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
+#define GPIO_PLOCK_PLOCK3  ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
+#define GPIO_PLOCK_PLOCK4  ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
+#define GPIO_PLOCK_PLOCK5  ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
+#define GPIO_PLOCK_PLOCK6  ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
+#define GPIO_PLOCK_PLOCK7  ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
+#define GPIO_PLOCK_PLOCK8  ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
+#define GPIO_PLOCK_PLOCK9  ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
+#define GPIO_PLOCK_PLOCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
+#define GPIO_PLOCK_PLOCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
+#define GPIO_PLOCK_PLOCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
+#define GPIO_PLOCK_PLOCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
+#define GPIO_PLOCK_PLOCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
+#define GPIO_PLOCK_PLOCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
+#define GPIO_PLOCK_PLOCKK  ((uint32_t)0x00010000) /*!< Lock key */
+
+/******************  Bit definition for GPIO_AFL register  *******************/
+#define GPIO_AFL_AFSEL0  ((uint32_t)0x0000000F) /*!< Port x AFL bit (0..3) */
+#define GPIO_AFL_AFSEL1  ((uint32_t)0x000000F0) /*!< Port x AFL bit (4..7) */
+#define GPIO_AFL_AFSEL2  ((uint32_t)0x00000F00) /*!< Port x AFL bit (8..11) */
+#define GPIO_AFL_AFSEL3  ((uint32_t)0x0000F000) /*!< Port x AFL bit (12..15) */
+#define GPIO_AFL_AFSEL4  ((uint32_t)0x000F0000) /*!< Port x AFL bit (16..19) */
+#define GPIO_AFL_AFSEL5  ((uint32_t)0x00F00000) /*!< Port x AFL bit (20..23) */
+#define GPIO_AFL_AFSEL6  ((uint32_t)0x0F000000) /*!< Port x AFL bit (24..27) */
+#define GPIO_AFL_AFSEL7  ((uint32_t)0xF0000000) /*!< Port x AFL bit (27..31) */
+
+/******************  Bit definition for GPIO_AFH register  *******************/
+#define GPIO_AFH_AFSEL8  ((uint32_t)0x0000000F) /*!< Port x AFH bit (0..3) */
+#define GPIO_AFH_AFSEL9  ((uint32_t)0x000000F0) /*!< Port x AFH bit (4..7) */
+#define GPIO_AFH_AFSEL10 ((uint32_t)0x00000F00) /*!< Port x AFH bit (8..11) */
+#define GPIO_AFH_AFSEL11 ((uint32_t)0x0000F000) /*!< Port x AFH bit (12..15) */
+#define GPIO_AFH_AFSEL12 ((uint32_t)0x000F0000) /*!< Port x AFH bit (16..19) */
+#define GPIO_AFH_AFSEL13 ((uint32_t)0x00F00000) /*!< Port x AFH bit (20..23) */
+#define GPIO_AFH_AFSEL14 ((uint32_t)0x0F000000) /*!< Port x AFH bit (24..27) */
+#define GPIO_AFH_AFSEL15 ((uint32_t)0xF0000000) /*!< Port x AFH bit (27..31) */
+
+
+/*******************  Bit definition for GPIO_DS register ******************/
+#define GPIO_DS0_Pos            (0)
+#define GPIO_DS0_Msk            (0x3 << GPIO_DS0_Pos)         /*!< 0x00000003 */
+#define GPIO_DS0                        GPIO_DS0_Msk
+#define GPIO_DS0_0              (0x0 << GPIO_DS0_Pos)         /*!< 0x00000000 */
+#define GPIO_DS0_1              (0x1 << GPIO_DS0_Pos)         /*!< 0x00000001 */
+#define GPIO_DS0_2              (0x2 << GPIO_DS0_Pos)         /*!< 0x00000002 */
+#define GPIO_DS0_3              (0x3 << GPIO_DS0_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS1_Pos            (2)
+#define GPIO_DS1_Msk            (0x3 << GPIO_DS1_Pos)         /*!< 0x00000003 */
+#define GPIO_DS1                        GPIO_DS1_Msk
+#define GPIO_DS1_0              (0x0 << GPIO_DS1_Pos)         /*!< 0x00000000 */
+#define GPIO_DS1_1              (0x1 << GPIO_DS1_Pos)         /*!< 0x00000001 */
+#define GPIO_DS1_2              (0x2 << GPIO_DS1_Pos)         /*!< 0x00000002 */
+#define GPIO_DS1_3              (0x3 << GPIO_DS1_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS2_Pos            (4)
+#define GPIO_DS2_Msk            (0x3 << GPIO_DS2_Pos)         /*!< 0x00000003 */
+#define GPIO_DS2                        GPIO_DS2_Msk
+#define GPIO_DS2_0              (0x0 << GPIO_DS2_Pos)         /*!< 0x00000000 */
+#define GPIO_DS2_1              (0x1 << GPIO_DS2_Pos)         /*!< 0x00000001 */
+#define GPIO_DS2_2              (0x2 << GPIO_DS2_Pos)         /*!< 0x00000002 */
+#define GPIO_DS2_3              (0x3 << GPIO_DS2_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS3_Pos            (6)
+#define GPIO_DS3_Msk            (0x3 << GPIO_DS3_Pos)         /*!< 0x00000003 */
+#define GPIO_DS3                        GPIO_DS3_Msk
+#define GPIO_DS3_0              (0x0 << GPIO_DS3_Pos)         /*!< 0x00000000 */
+#define GPIO_DS3_1              (0x1 << GPIO_DS3_Pos)         /*!< 0x00000001 */
+#define GPIO_DS3_2              (0x2 << GPIO_DS3_Pos)         /*!< 0x00000002 */
+#define GPIO_DS3_3              (0x3 << GPIO_DS3_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS4_Pos            (8)
+#define GPIO_DS4_Msk            (0x3 << GPIO_DS4_Pos)         /*!< 0x00000003 */
+#define GPIO_DS4                        GPIO_DS4_Msk
+#define GPIO_DS4_0              (0x0 << GPIO_DS4_Pos)         /*!< 0x00000000 */
+#define GPIO_DS4_1              (0x1 << GPIO_DS4_Pos)         /*!< 0x00000001 */
+#define GPIO_DS4_2              (0x2 << GPIO_DS4_Pos)         /*!< 0x00000002 */
+#define GPIO_DS4_3              (0x3 << GPIO_DS4_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS5_Pos            (10)
+#define GPIO_DS5_Msk            (0x3 << GPIO_DS5_Pos)         /*!< 0x00000003 */
+#define GPIO_DS5                        GPIO_DS5_Msk
+#define GPIO_DS5_0              (0x0 << GPIO_DS5_Pos)         /*!< 0x00000000 */
+#define GPIO_DS5_1              (0x1 << GPIO_DS5_Pos)         /*!< 0x00000001 */
+#define GPIO_DS5_2              (0x2 << GPIO_DS5_Pos)         /*!< 0x00000002 */
+#define GPIO_DS5_3              (0x3 << GPIO_DS5_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS6_Pos            (12)
+#define GPIO_DS6_Msk            (0x3 << GPIO_DS6_Pos)         /*!< 0x00000003 */
+#define GPIO_DS6                        GPIO_DS6_Msk
+#define GPIO_DS6_0              (0x0 << GPIO_DS6_Pos)         /*!< 0x00000000 */
+#define GPIO_DS6_1              (0x1 << GPIO_DS6_Pos)         /*!< 0x00000001 */
+#define GPIO_DS6_2              (0x2 << GPIO_DS6_Pos)         /*!< 0x00000002 */
+#define GPIO_DS6_3              (0x3 << GPIO_DS6_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS7_Pos            (14)
+#define GPIO_DS7_Msk            (0x3 << GPIO_DS7_Pos)         /*!< 0x00000003 */
+#define GPIO_DS7                        GPIO_DS7_Msk
+#define GPIO_DS7_0              (0x0 << GPIO_DS7_Pos)         /*!< 0x00000000 */
+#define GPIO_DS7_1              (0x1 << GPIO_DS7_Pos)         /*!< 0x00000001 */
+#define GPIO_DS7_2              (0x2 << GPIO_DS7_Pos)         /*!< 0x00000002 */
+#define GPIO_DS7_3              (0x3 << GPIO_DS7_Pos)         /*!< 0x00000003 */
+
+
+#define GPIO_DS8_Pos            (16)
+#define GPIO_DS8_Msk            (0x3 << GPIO_DS8_Pos)         /*!< 0x00000003 */
+#define GPIO_DS8                        GPIO_DS8_Msk
+#define GPIO_DS8_0              (0x0 << GPIO_DS8_Pos)         /*!< 0x00000000 */
+#define GPIO_DS8_1              (0x1 << GPIO_DS8_Pos)         /*!< 0x00000001 */
+#define GPIO_DS8_2              (0x2 << GPIO_DS8_Pos)         /*!< 0x00000002 */
+#define GPIO_DS8_3              (0x3 << GPIO_DS8_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS9_Pos            (18)
+#define GPIO_DS9_Msk            (0x3 << GPIO_DS9_Pos)         /*!< 0x00000003 */
+#define GPIO_DS9                        GPIO_DS9_Msk
+#define GPIO_DS9_0              (0x0 << GPIO_DS9_Pos)         /*!< 0x00000000 */
+#define GPIO_DS9_1              (0x1 << GPIO_DS9_Pos)         /*!< 0x00000001 */
+#define GPIO_DS9_2              (0x2 << GPIO_DS9_Pos)         /*!< 0x00000002 */
+#define GPIO_DS9_3              (0x3 << GPIO_DS9_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS10_Pos            (20)
+#define GPIO_DS10_Msk            (0x3 << GPIO_DS10_Pos)         /*!< 0x00000003 */
+#define GPIO_DS10                        GPIO_DS10_Msk
+#define GPIO_DS10_0              (0x0 << GPIO_DS10_Pos)         /*!< 0x00000000 */
+#define GPIO_DS10_1              (0x1 << GPIO_DS10_Pos)         /*!< 0x00000001 */
+#define GPIO_DS10_2              (0x2 << GPIO_DS10_Pos)         /*!< 0x00000002 */
+#define GPIO_DS10_3              (0x3 << GPIO_DS10_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS11_Pos            (22)
+#define GPIO_DS11_Msk            (0x3 << GPIO_DS11_Pos)         /*!< 0x00000003 */
+#define GPIO_DS11                        GPIO_DS11_Msk
+#define GPIO_DS11_0              (0x0 << GPIO_DS11_Pos)         /*!< 0x00000000 */
+#define GPIO_DS11_1              (0x1 << GPIO_DS11_Pos)         /*!< 0x00000001 */
+#define GPIO_DS11_2              (0x2 << GPIO_DS11_Pos)         /*!< 0x00000002 */
+#define GPIO_DS11_3              (0x3 << GPIO_DS11_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS12_Pos            (24)
+#define GPIO_DS12_Msk            (0x3 << GPIO_DS12_Pos)         /*!< 0x00000003 */
+#define GPIO_DS12                        GPIO_DS12_Msk
+#define GPIO_DS12_0              (0x0 << GPIO_DS12_Pos)         /*!< 0x00000000 */
+#define GPIO_DS12_1              (0x1 << GPIO_DS12_Pos)         /*!< 0x00000001 */
+#define GPIO_DS12_2              (0x2 << GPIO_DS12_Pos)         /*!< 0x00000002 */
+#define GPIO_DS12_3              (0x3 << GPIO_DS12_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS13_Pos            (26)
+#define GPIO_DS13_Msk            (0x3 << GPIO_DS13_Pos)         /*!< 0x00000003 */
+#define GPIO_DS13                        GPIO_DS13_Msk
+#define GPIO_DS13_0              (0x0 << GPIO_DS13_Pos)         /*!< 0x00000000 */
+#define GPIO_DS13_1              (0x1 << GPIO_DS13_Pos)         /*!< 0x00000001 */
+#define GPIO_DS13_2              (0x2 << GPIO_DS13_Pos)         /*!< 0x00000002 */
+#define GPIO_DS13_3              (0x3 << GPIO_DS13_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS14_Pos            (28)
+#define GPIO_DS14_Msk            (0x3 << GPIO_DS14_Pos)         /*!< 0x00000003 */
+#define GPIO_DS14                        GPIO_DS14_Msk
+#define GPIO_DS14_0              (0x0 << GPIO_DS14_Pos)         /*!< 0x00000000 */
+#define GPIO_DS14_1              (0x1 << GPIO_DS14_Pos)         /*!< 0x00000001 */
+#define GPIO_DS14_2              (0x2 << GPIO_DS14_Pos)         /*!< 0x00000002 */
+#define GPIO_DS14_3              (0x3 << GPIO_DS14_Pos)         /*!< 0x00000003 */
+
+#define GPIO_DS15_Pos            (30)
+#define GPIO_DS15_Msk            (0x3 << GPIO_DS15_Pos)         /*!< 0x00000003 */
+#define GPIO_DS15                        GPIO_DS15_Msk
+#define GPIO_DS15_0              (0x0 << GPIO_DS15_Pos)         /*!< 0x00000000 */
+#define GPIO_DS15_1              (0x1 << GPIO_DS15_Pos)         /*!< 0x00000001 */
+#define GPIO_DS15_2              (0x2 << GPIO_DS15_Pos)         /*!< 0x00000002 */
+#define GPIO_DS15_3              (0x3 << GPIO_DS15_Pos)         /*!< 0x00000003 */
+
+/*******************  Bit definition for GPIO_SR register  *******************/
+#define GPIO_SR_SR0  ((uint16_t)0x0001) /*!<  Slew rate bit 0 */
+#define GPIO_SR_SR1  ((uint16_t)0x0002) /*!<  Slew rate bit 1 */
+#define GPIO_SR_SR2  ((uint16_t)0x0004) /*!<  Slew rate bit 2 */
+#define GPIO_SR_SR3  ((uint16_t)0x0008) /*!<  Slew rate bit 3 */
+#define GPIO_SR_SR4  ((uint16_t)0x0010) /*!<  Slew rate bit 4 */
+#define GPIO_SR_SR5  ((uint16_t)0x0020) /*!<  Slew rate bit 5 */
+#define GPIO_SR_SR6  ((uint16_t)0x0040) /*!<  Slew rate bit 6 */
+#define GPIO_SR_SR7  ((uint16_t)0x0080) /*!<  Slew rate bit 7 */
+#define GPIO_SR_SR8  ((uint16_t)0x0100) /*!<  Slew rate bit 8 */
+#define GPIO_SR_SR9  ((uint16_t)0x0200) /*!<  Slew rate bit 9 */
+#define GPIO_SR_SR10 ((uint16_t)0x0400) /*!<  Slew rate bit 10 */
+#define GPIO_SR_SR11 ((uint16_t)0x0800) /*!<  Slew rate bit 11 */
+#define GPIO_SR_SR12 ((uint16_t)0x1000) /*!<  Slew rate bit 12 */
+#define GPIO_SR_SR13 ((uint16_t)0x2000) /*!<  Slew rate bit 13 */
+#define GPIO_SR_SR14 ((uint16_t)0x4000) /*!<  Slew rate bit 14 */
+#define GPIO_SR_SR15 ((uint16_t)0x8000) /*!<  Slew rate bit 15 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for AFIO_RMP_CFG register  *****************/
+#define AFIO_RMP_CFG_SPI1_NSS ((uint16_t)0x0800) /*!< AFIO_RMP_CFG bit 11 */
+#define AFIO_RMP_CFG_SPI2_NSS ((uint16_t)0x0400) /*!< AFIO_RMP_CFG bit 10 */
+#define AFIO_RMP_CFG_ADC_ETRI ((uint16_t)0x0200) /*!< AFIO_RMP_CFG bit 9 */
+#define AFIO_RMP_CFG_ADC_ETRR ((uint16_t)0x0100) /*!< AFIO_RMP_CFG bit 8 */
+#define AFIO_RMP_CFG_EXTI_ETRI ((uint16_t)0x00F0) /*!< AFIO_RMP_CFG bit (4..7) */
+#define AFIO_RMP_CFG_EXTI_ETRR ((uint16_t)0x000F) /*!< AFIO_RMP_CFG bit (0..3) */
+
+/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
+#define AFIO_EXTI_CFG1_EXTI0 ((uint16_t)0x0003) /*!< EXTI 0 configuration */
+#define AFIO_EXTI_CFG1_EXTI1 ((uint16_t)0x0030) /*!< EXTI 1 configuration */
+#define AFIO_EXTI_CFG1_EXTI2 ((uint16_t)0x0300) /*!< EXTI 2 configuration */
+#define AFIO_EXTI_CFG1_EXTI3 ((uint16_t)0x3000) /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTI_CFG1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define AFIO_EXTI_CFG1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTI_CFG1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define AFIO_EXTI_CFG1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTI_CFG1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define AFIO_EXTI_CFG1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTI_CFG1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define AFIO_EXTI_CFG1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+
+/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
+#define AFIO_EXTI_CFG2_EXTI4 ((uint16_t)0x0003) /*!< EXTI 4 configuration */
+#define AFIO_EXTI_CFG2_EXTI5 ((uint16_t)0x0030) /*!< EXTI 5 configuration */
+#define AFIO_EXTI_CFG2_EXTI6 ((uint16_t)0x0300) /*!< EXTI 6 configuration */
+#define AFIO_EXTI_CFG2_EXTI7 ((uint16_t)0x3000) /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTI_CFG2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define AFIO_EXTI_CFG2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+
+/*!< EXTI5 configuration */
+#define AFIO_EXTI_CFG2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define AFIO_EXTI_CFG2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTI_CFG2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define AFIO_EXTI_CFG2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTI_CFG2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define AFIO_EXTI_CFG2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+
+/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
+#define AFIO_EXTI_CFG3_EXTI8  ((uint16_t)0x0003) /*!< EXTI 8 configuration */
+#define AFIO_EXTI_CFG3_EXTI9  ((uint16_t)0x0030) /*!< EXTI 9 configuration */
+#define AFIO_EXTI_CFG3_EXTI10 ((uint16_t)0x0300) /*!< EXTI 10 configuration */
+#define AFIO_EXTI_CFG3_EXTI11 ((uint16_t)0x3000) /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTI_CFG3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define AFIO_EXTI_CFG3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTI_CFG3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define AFIO_EXTI_CFG3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTI_CFG3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define AFIO_EXTI_CFG3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTI_CFG3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define AFIO_EXTI_CFG3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+
+/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
+#define AFIO_EXTI_CFG4_EXTI12 ((uint16_t)0x0003) /*!< EXTI 12 configuration */
+#define AFIO_EXTI_CFG4_EXTI13 ((uint16_t)0x0030) /*!< EXTI 13 configuration */
+#define AFIO_EXTI_CFG4_EXTI14 ((uint16_t)0x0300) /*!< EXTI 14 configuration */
+#define AFIO_EXTI_CFG4_EXTI15 ((uint16_t)0x3000) /*!< EXTI 15 configuration */
+
+/*!< EXTI12 configuration */
+#define AFIO_EXTI_CFG4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define AFIO_EXTI_CFG4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+
+/*!< EXTI13 configuration */
+#define AFIO_EXTI_CFG4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define AFIO_EXTI_CFG4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTI_CFG4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define AFIO_EXTI_CFG4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTI_CFG4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define AFIO_EXTI_CFG4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define EXTI_IMASK_IMASK0  ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMASK_IMASK1  ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMASK_IMASK2  ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMASK_IMASK3  ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMASK_IMASK4  ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMASK_IMASK5  ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMASK_IMASK6  ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMASK_IMASK7  ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMASK_IMASK8  ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMASK_IMASK9  ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMASK_IMASK10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMASK_IMASK11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMASK_IMASK12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMASK_IMASK13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMASK_IMASK14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMASK_IMASK15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMASK_IMASK16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMASK_IMASK17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMASK_IMASK18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMASK_IMASK19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMASK_IMASK20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMASK_IMASK21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMASK_IMASK22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMASK_IMASK23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMASK_IMASK24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
+#define EXTI_IMASK_IMASK25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMASK_IMASK26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMASK_IMASK27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define EXTI_EMASK_EMASK0  ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMASK_EMASK1  ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMASK_EMASK2  ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMASK_EMASK3  ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMASK_EMASK4  ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMASK_EMASK5  ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMASK_EMASK6  ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMASK_EMASK7  ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMASK_EMASK8  ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMASK_EMASK9  ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMASK_EMASK10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMASK_EMASK11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMASK_EMASK12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMASK_EMASK13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMASK_EMASK14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMASK_EMASK15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMASK_EMASK16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMASK_EMASK17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMASK_EMASK18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMASK_EMASK19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMASK_EMASK20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMASK_EMASK21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMASK_EMASK22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMASK_EMASK23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMASK_EMASK24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
+#define EXTI_EMASK_EMASK25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMASK_EMASK26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
+#define EXTI_EMASK_EMASK27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+
+
+/******************  Bit definition for EXTI_RT_CFG register  *******************/
+#define EXTI_EMASK_RT_CFG_RT_CFG0  ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_EMASK_RT_CFG_RT_CFG1  ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_EMASK_RT_CFG_RT_CFG2  ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_EMASK_RT_CFG_RT_CFG3  ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_EMASK_RT_CFG_RT_CFG4  ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_EMASK_RT_CFG_RT_CFG5  ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_EMASK_RT_CFG_RT_CFG6  ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_EMASK_RT_CFG_RT_CFG7  ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_EMASK_RT_CFG_RT_CFG8  ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_EMASK_RT_CFG_RT_CFG9  ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_EMASK_RT_CFG_RT_CFG10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_EMASK_RT_CFG_RT_CFG11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_EMASK_RT_CFG_RT_CFG12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_EMASK_RT_CFG_RT_CFG13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_EMASK_RT_CFG_RT_CFG14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_EMASK_RT_CFG_RT_CFG15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_EMASK_RT_CFG_RT_CFG16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_EMASK_RT_CFG_RT_CFG17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_EMASK_RT_CFG_RT_CFG18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_EMASK_RT_CFG_RT_CFG19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_EMASK_RT_CFG_RT_CFG20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_EMASK_RT_CFG_RT_CFG21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_EMASK_RT_CFG_RT_CFG22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_EMASK_RT_CFG_RT_CFG23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
+#define EXTI_EMASK_RT_CFG_RT_CFG24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
+#define EXTI_EMASK_RT_CFG_RT_CFG25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
+#define EXTI_EMASK_RT_CFG_RT_CFG26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
+#define EXTI_EMASK_RT_CFG_RT_CFG27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
+
+
+
+/******************  Bit definition for EXTI_FT_CFG register  *******************/
+#define EXTI_EMASK_FT_CFG_FT_CFG0  ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_EMASK_FT_CFG_FT_CFG1  ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_EMASK_FT_CFG_FT_CFG2  ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_EMASK_FT_CFG_FT_CFG3  ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_EMASK_FT_CFG_FT_CFG4  ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_EMASK_FT_CFG_FT_CFG5  ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_EMASK_FT_CFG_FT_CFG6  ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_EMASK_FT_CFG_FT_CFG7  ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_EMASK_FT_CFG_FT_CFG8  ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_EMASK_FT_CFG_FT_CFG9  ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_EMASK_FT_CFG_FT_CFG10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_EMASK_FT_CFG_FT_CFG11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_EMASK_FT_CFG_FT_CFG12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_EMASK_FT_CFG_FT_CFG13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_EMASK_FT_CFG_FT_CFG14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_EMASK_FT_CFG_FT_CFG15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_EMASK_FT_CFG_FT_CFG16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_EMASK_FT_CFG_FT_CFG17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_EMASK_FT_CFG_FT_CFG18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_EMASK_FT_CFG_FT_CFG19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_EMASK_FT_CFG_FT_CFG20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_EMASK_FT_CFG_FT_CFG21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_EMASK_FT_CFG_FT_CFG22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_EMASK_FT_CFG_FT_CFG23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
+#define EXTI_EMASK_FT_CFG_FT_CFG24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
+#define EXTI_EMASK_FT_CFG_FT_CFG25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
+#define EXTI_EMASK_FT_CFG_FT_CFG26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
+#define EXTI_EMASK_FT_CFG_FT_CFG27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
+
+/******************  Bit definition for EXTI_SWIE register  ******************/
+#define EXTI_SWIE_SWIE0  ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIE_SWIE1  ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIE_SWIE2  ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIE_SWIE3  ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIE_SWIE4  ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIE_SWIE5  ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIE_SWIE6  ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIE_SWIE7  ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIE_SWIE8  ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIE_SWIE9  ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIE_SWIE10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIE_SWIE11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIE_SWIE12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIE_SWIE13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIE_SWIE14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIE_SWIE15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIE_SWIE16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIE_SWIE17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIE_SWIE18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIE_SWIE19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIE_SWIE20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIE_SWIE21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIE_SWIE22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIE_SWIE23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
+#define EXTI_SWIE_SWIE24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
+#define EXTI_SWIE_SWIE25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
+#define EXTI_SWIE_SWIE26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
+#define EXTI_SWIE_SWIE27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
+
+/*******************  Bit definition for EXTI_PEND register  ********************/
+#define EXTI_PEND_PEND0  ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PEND_PEND1  ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PEND_PEND2  ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PEND_PEND3  ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PEND_PEND4  ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PEND_PEND5  ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PEND_PEND6  ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PEND_PEND7  ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PEND_PEND8  ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PEND_PEND9  ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PEND_PEND10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PEND_PEND11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PEND_PEND12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PEND_PEND13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PEND_PEND14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PEND_PEND15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PEND_PEND16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PEND_PEND17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PEND_PEND18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PEND_PEND19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PEND_PEND20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PEND_PEND21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PEND_PEND22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+#define EXTI_PEND_PEND23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
+#define EXTI_PEND_PEND24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
+#define EXTI_PEND_PEND25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
+#define EXTI_PEND_PEND26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
+#define EXTI_PEND_PEND27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 TSC Registers                              */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for TSC_CTRL register         ****************/
+#define TSC_CTRL_TM2_ETR_CH1_Msk    ((uint32_t)0x2000)
+#define TSC_CTRL_TM2_ETR_CH1_Pos    (13U)
+#define TSC_CTRL_TM2_ETR_CH1        (TSC_CTRL_TM2_ETR_CH1_Msk)      /*!<TSC_out connected to TIM2_ETR and TIM2_CH1*/
+
+#define TSC_CTRL_TM4_ETR_Msk        ((uint32_t)0x1000)
+#define TSC_CTRL_TM4_ETR_Pos        (12U)
+#define TSC_CTRL_TM4_ETR            (TSC_CTRL_TM4_ETR_Msk)          /*!<TSC_out connected to TIM4_ETR*/
+
+#define TSC_CTRL_DET_INTEN_Msk      ((uint32_t)0x0400)
+#define TSC_CTRL_DET_INTEN_Pos      (10U)
+#define TSC_CTRL_DET_INTEN          (TSC_CTRL_DET_INTEN_Msk)        /*!<TSC interrupt control bit*/
+
+#define TSC_CTRL_GREAT_DET_SEL_Msk  ((uint32_t)0x0200)
+#define TSC_CTRL_GREAT_DET_SEL_Pos  (9U)
+#define TSC_CTRL_GREAT_DET_SEL      (TSC_CTRL_GREAT_DET_SEL_Msk)    /*!<TSC great detect control*/
+
+#define TSC_CTRL_LESS_DET_SEL_Msk   ((uint32_t)0x0100)
+#define TSC_CTRL_LESS_DET_SEL_Pos   (8U)
+#define TSC_CTRL_LESS_DET_SEL       (TSC_CTRL_LESS_DET_SEL_Msk)     /*!<TSC less detect control*/
+
+#define TSC_CTRL_HW_DET_ST_Msk      ((uint32_t)0x0080)
+#define TSC_CTRL_HW_DET_ST_Pos      (7U)
+#define TSC_CTRL_HW_DET_ST          (TSC_CTRL_HW_DET_ST_Msk)        /*!<Status of TSC hardware detect mode*/
+
+#define TSC_CTRL_HW_DET_MODE_Msk    ((uint32_t)0x0040)
+#define TSC_CTRL_HW_DET_MODE_Pos    (6U)
+#define TSC_CTRL_HW_DET_MODE        (TSC_CTRL_HW_DET_MODE_Msk)      /*!<TSC hardware detect mode control*/
+
+#define TSC_CTRL_DET_FILTER_Msk     ((uint32_t)0x0030)
+#define TSC_CTRL_DET_FILTER_Pos     (4U)
+#define TSC_CTRL_DET_FILTER         (TSC_CTRL_DET_FILTER_Msk)       /*!<TSC filter for continuously detect */
+#define TSC_CTRL_DET_FILTER_0       (0x1UL << TSC_CTRL_DET_FILTER_Pos)
+#define TSC_CTRL_DET_FILTER_1       (0x2UL << TSC_CTRL_DET_FILTER_Pos)
+
+#define TSC_CTRL_DET_PERIOD_Msk     ((uint32_t)0x000F)
+#define TSC_CTRL_DET_PERIOD_Pos     (0U)
+#define TSC_CTRL_DET_PERIOD         (TSC_CTRL_DET_PERIOD_Msk)       /*!<TSC detect time of one sample */
+#define TSC_CTRL_DET_PERIOD_0       (0x1UL << TSC_CTRL_DET_PERIOD_Pos)
+#define TSC_CTRL_DET_PERIOD_1       (0x2UL << TSC_CTRL_DET_PERIOD_Pos)
+#define TSC_CTRL_DET_PERIOD_2       (0x4UL << TSC_CTRL_DET_PERIOD_Pos)
+#define TSC_CTRL_DET_PERIOD_3       (0x8UL << TSC_CTRL_DET_PERIOD_Pos)
+
+/****************  Bit definition for TSC TSC_CHNEN register    ****************/
+#define TSC_CHNEN_CHN_SELx_Msk      ((uint32_t)0x00FBFFF2)
+#define TSC_CHNEN_CHN_SELx_Pos      (0U)
+#define TSC_CHNEN_CHN_SEL1          ((uint32_t)0x00000002) /*!< Channel 1 enable bit */
+#define TSC_CHNEN_CHN_SEL4          ((uint32_t)0x00000010) /*!< Channel 4 enable bit */
+#define TSC_CHNEN_CHN_SEL5          ((uint32_t)0x00000020) /*!< Channel 5 enable bit */
+#define TSC_CHNEN_CHN_SEL6          ((uint32_t)0x00000040) /*!< Channel 6 enable bit */
+#define TSC_CHNEN_CHN_SEL7          ((uint32_t)0x00000080) /*!< Channel 7 enable bit */
+#define TSC_CHNEN_CHN_SEL8          ((uint32_t)0x00000100) /*!< Channel 8 enable bit */
+#define TSC_CHNEN_CHN_SEL9          ((uint32_t)0x00000200) /*!< Channel 9 enable bit */
+#define TSC_CHNEN_CHN_SEL10         ((uint32_t)0x00000400) /*!< Channel 10 enable bit */
+#define TSC_CHNEN_CHN_SEL11         ((uint32_t)0x00000800) /*!< Channel 11 enable bit */
+#define TSC_CHNEN_CHN_SEL12         ((uint32_t)0x00001000) /*!< Channel 12 enable bit */
+#define TSC_CHNEN_CHN_SEL13         ((uint32_t)0x00002000) /*!< Channel 13 enable bit */
+#define TSC_CHNEN_CHN_SEL14         ((uint32_t)0x00004000) /*!< Channel 14 enable bit */
+#define TSC_CHNEN_CHN_SEL15         ((uint32_t)0x00008000) /*!< Channel 15 enable bit */
+#define TSC_CHNEN_CHN_SEL16         ((uint32_t)0x00010000) /*!< Channel 16 enable bit */
+#define TSC_CHNEN_CHN_SEL17         ((uint32_t)0x00020000) /*!< Channel 17 enable bit */
+#define TSC_CHNEN_CHN_SEL19         ((uint32_t)0x00080000) /*!< Channel 19 enable bit */
+#define TSC_CHNEN_CHN_SEL20         ((uint32_t)0x00100000) /*!< Channel 20 enable bit */
+#define TSC_CHNEN_CHN_SEL21         ((uint32_t)0x00200000) /*!< Channel 21 enable bit */
+#define TSC_CHNEN_CHN_SEL22         ((uint32_t)0x00400000) /*!< Channel 22 enable bit */
+#define TSC_CHNEN_CHN_SEL23         ((uint32_t)0x00800000) /*!< Channel 23 enable bit */
+
+/****************  Bit definition for TSC TSC_STS register      ****************/
+#define TSC_STS_CHN_NUM_Msk         ((uint32_t)0x001F0000)
+#define TSC_STS_CHN_NUM_Pos         (16U)
+#define TSC_STS_CHN_NUM             TSC_STS_CHN_NUM_Msk     /*!<Current detect channel number */
+
+#define TSC_STS_GREAT_DET_Msk        ((uint32_t)0x00002000)
+#define TSC_STS_GREAT_DET_Pos       (13U)
+#define TSC_STS_GREAT_DET           TSC_STS_GREAT_DET_Msk   /*!<Status of TSC great detect*/
+
+#define TSC_STS_LESS_DET_Msk        ((uint32_t)0x00001000)
+#define TSC_STS_LESS_DET_Pos        (12U)
+#define TSC_STS_LESS_DET            TSC_STS_LESS_DET_Msk    /*!<Status of TSC less detect*/
+
+#define TSC_STS_CNT_VAL_Msk         ((uint32_t)0x000007FF)
+#define TSC_STS_CNT_VAL_Pos         (0U)
+#define TSC_STS_CNT_VAL             TSC_STS_CNT_VAL_Msk     /*!<The pulse count value for current channel*/
+
+/****************  Bit definition for TSC_ANA_CTRL register      ****************/
+#define TSC_ANA_CTRL_SW_TSC_EN_Msk  ((uint32_t)0x0020)
+#define TSC_ANA_CTRL_SW_TSC_EN_Pos  (5U)
+#define TSC_ANA_CTRL_SW_TSC_EN      TSC_ANA_CTRL_SW_TSC_EN_Msk  /*!<TSC software detect mode control bit*/
+
+#define TSC_ANA_CTRL_SW_PAD_MUX_Msk ((uint32_t)0x001F)
+#define TSC_ANA_CTRL_SW_PAD_MUX_Pos (0U)
+#define TSC_ANA_CTRL_SW_PAD_MUX     TSC_ANA_CTRL_SW_PAD_MUX_Msk /*!<Current channel number of TSC software detect mode*/
+
+/****************  Bit definition for TSC_ANA_SEL register      ****************/
+#define TSC_ANA_SEL_PAD_OPT_Msk     ((uint32_t)0x0040)
+#define TSC_ANA_SEL_PAD_OPT_Pos     (6U)
+#define TSC_ANA_SEL_PAD_OPT         TSC_ANA_SEL_PAD_OPT_Msk     /*!<TSC charge pad control bit,internal or external resistor*/
+
+#define TSC_ANA_SEL_SP_OPT_Msk      ((uint32_t)0x0030)
+#define TSC_ANA_SEL_SP_OPT_Pos      (4U)
+#define TSC_ANA_SEL_SP_OPT          TSC_ANA_SEL_SP_OPT_Msk          /*!<TSC speed control bits*/
+#define TSC_ANA_SEL_SP_OPT_0        (0x1UL << TSC_ANA_SEL_SP_OPT_Pos)
+#define TSC_ANA_SEL_SP_OPT_1        (0x2UL << TSC_ANA_SEL_SP_OPT_Pos)
+
+/*****************  Resistor value of  TSC_RESRx register  *****************/
+#define TSC_RESRx_CHN_RESIST_Msk    ((uint32_t)0x00000007) /*!< TSC_RESRx CHx MASK */
+#define TSC_RESRx_CHN_RESIST_0      ((uint32_t)0x00000000) /*!< 812.5K ohm */
+#define TSC_RESRx_CHN_RESIST_1      ((uint32_t)0x00000001) /*!< 437.5K 0hm */
+#define TSC_RESRx_CHN_RESIST_2      ((uint32_t)0x00000002) /*!< 281.25K ohm */
+#define TSC_RESRx_CHN_RESIST_3      ((uint32_t)0x00000003) /*!< 218.75K ohm */
+#define TSC_RESRx_CHN_RESIST_4      ((uint32_t)0x00000004) /*!< 187.5K ohm */
+#define TSC_RESRx_CHN_RESIST_5      ((uint32_t)0x00000005) /*!< 156.25K ohm */
+#define TSC_RESRx_CHN_RESIST_6      ((uint32_t)0x00000006) /*!< 125K ohm */
+#define TSC_RESRx_CHN_RESIST_7      ((uint32_t)0x00000007) /*!< 93.75K ohm */
+
+/*****************  Bit definition for TSC_RESR0 register  *****************/
+#define TSC_RESR0_CHN_RESIST1_Pos   (4U)  /*!< TSC_RESR 0 channel 1 */
+#define TSC_RESR0_CHN_RESIST4_Pos   (16U) /*!< TSC_RESR 0 channel 4 */
+#define TSC_RESR0_CHN_RESIST5_Pos   (20U) /*!< TSC_RESR 0 channel 5 */
+#define TSC_RESR0_CHN_RESIST6_Pos   (24U) /*!< TSC_RESR 0 channel 6 */
+#define TSC_RESR0_CHN_RESIST7_Pos   (28U) /*!< TSC_RESR 0 channel 7 */
+
+/*****************  Bit definition for TSC_RESR1 register  *****************/
+#define TSC_RESR1_CHN_RESIST8_Pos   (0U)  /*!< TSC_RESR 1 channel 8  */
+#define TSC_RESR1_CHN_RESIST9_Pos   (4U)  /*!< TSC_RESR 1 channel 9  */
+#define TSC_RESR1_CHN_RESIST10_Pos  (8U)  /*!< TSC_RESR 1 channel 10 */
+#define TSC_RESR1_CHN_RESIST11_Pos  (12U) /*!< TSC_RESR 1 channel 11 */
+#define TSC_RESR1_CHN_RESIST12_Pos  (16U) /*!< TSC_RESR 1 channel 12 */
+#define TSC_RESR1_CHN_RESIST13_Pos  (20U) /*!< TSC_RESR 1 channel 13 */
+#define TSC_RESR1_CHN_RESIST14_Pos  (24U) /*!< TSC_RESR 1 channel 14 */
+#define TSC_RESR1_CHN_RESIST15_Pos  (28U) /*!< TSC_RESR 1 channel 15 */
+
+/*****************  Bit definition for TSC_RESR2 register  *****************/
+#define TSC_RESR2_CHN_RESIST16_Pos  (0U)  /*!< TSC_RESR 2 channel 16 */
+#define TSC_RESR2_CHN_RESIST17_Pos  (4U)  /*!< TSC_RESR 2 channel 17 */
+#define TSC_RESR2_CHN_RESIST19_Pos  (12U) /*!< TSC_RESR 2 channel 19 */
+#define TSC_RESR2_CHN_RESIST20_Pos  (16U) /*!< TSC_RESR 2 channel 20 */
+#define TSC_RESR2_CHN_RESIST21_Pos  (20U) /*!< TSC_RESR 2 channel 21 */
+#define TSC_RESR2_CHN_RESIST22_Pos  (24U) /*!< TSC_RESR 2 channel 22 */
+#define TSC_RESR2_CHN_RESIST23_Pos  (28U) /*!< TSC_RESR 2 channel 23 */
+
+/****************  Bit definition for TSC_THRHDx register       ****************/
+#define TSC_THRHDx_DELTA_Msk        ((uint32_t)0x00FF0000)
+#define TSC_THRHDx_DELTA_Pos        (16U)
+#define TSC_THRHDx_DELTA            TSC_THRHDx_DELTA_Msk    /*!<TSC_THRHD register delta bit */
+
+#define TSC_THRHDx_BASE_Msk         ((uint32_t)0x000007FF)
+#define TSC_THRHDx_BASE_Pos         (0U)
+#define TSC_THRHDx_BASE             TSC_THRHDx_BASE_Msk     /*!<TSC_THRHD register base bit */
+
+
+
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+ * @}
+ */
+
+#ifdef USE_STDPERIPH_DRIVER
+#include "n32g43x_conf.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_H__ */

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_conf.h

@@ -0,0 +1,84 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_conf.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_CONF_H__
+#define __N32G43X_CONF_H__
+
+/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+
+#include "n32g43x_adc.h"
+#include "n32g43x_can.h"
+#include "n32g43x_comp.h"
+#include "n32g43x_crc.h"
+#include "n32g43x_dac.h"
+#include "n32g43x_dbg.h"
+#include "n32g43x_dma.h"
+#include "n32g43x_exti.h"
+#include "n32g43x_flash.h"
+#include "n32g43x_gpio.h"
+#include "n32g43x_i2c.h"
+#include "n32g43x_iwdg.h"
+#include "n32g43x_opamp.h"
+#include "n32g43x_pwr.h"
+#include "n32g43x_rcc.h"
+#include "n32g43x_rtc.h"
+#include "n32g43x_spi.h"
+#include "n32g43x_tim.h"
+#include "n32g43x_usart.h"
+#include "n32g43x_lpuart.h"
+#include "n32g43x_wwdg.h"
+#include "n32g43x_tsc.h"
+
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Uncomment the line below to expanse the "assert_param" macro in the
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1  */
+
+#ifdef USE_FULL_ASSERT
+
+/**
+ * @brief  The assert_param macro is used for function's parameters check.
+ * @param expr If expr is false, it calls assert_failed function which reports
+ *         the name of the source file and the source line number of the call
+ *         that failed. If expr is true, it returns no value.
+ */
+#define assert_param(expr) ((expr) ? (void)0 : assert_failed((const uint8_t*)#expr, (const uint8_t*)__FILE__, __LINE__))
+
+void assert_failed(const uint8_t* expr, const uint8_t* file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __N32G43X_CONF_H__ */

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_flash.ld

@@ -0,0 +1,182 @@
+/**
+  ****************************************************************************
+  Copyright (c) 2019, Nations Technologies Inc.
+
+  All rights reserved.
+  ****************************************************************************
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions are met:
+
+  - Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the disclaimer below.
+
+  Nations' name may not be used to endorse or promote products derived from
+  this software without specific prior written permission.
+
+  DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+  DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  ****************************************************************************
+ **/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 128K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+	
+	/* section information for finsh shell */
+	. = ALIGN(4);
+	__fsymtab_start = .;
+	KEEP(*(FSymTab))
+	__fsymtab_end = .;
+
+	. = ALIGN(4);
+	__vsymtab_start = .;
+	KEEP(*(VSymTab))
+	__vsymtab_end = .;
+
+	/* section information for initial. */
+	. = ALIGN(4);
+	__rt_init_start = .;
+	KEEP(*(SORT(.rti_fn*)))
+	__rt_init_end = .;
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x.s

@@ -0,0 +1,371 @@
+; ****************************************************************************
+; Copyright (c) 2019, Nations Technologies Inc.
+;
+; All rights reserved.
+; ****************************************************************************
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; - Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the disclaimer below.
+;
+; Nations' name may not be used to endorse or promote products derived from
+; this software without specific prior written permission.
+;
+; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; ****************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00001500
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+                                                  
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000300
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt
+                DCD     RTC_WKUP_IRQHandler        ; RTC_WKUP
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA_Channel1_IRQHandler    ; DMA Channel 1
+                DCD     DMA_Channel2_IRQHandler    ; DMA Channel 2
+                DCD     DMA_Channel3_IRQHandler    ; DMA Channel 3
+                DCD     DMA_Channel4_IRQHandler    ; DMA Channel 4
+                DCD     DMA_Channel5_IRQHandler    ; DMA Channel 5
+                DCD     DMA_Channel6_IRQHandler    ; DMA Channel 6
+                DCD     DMA_Channel7_IRQHandler    ; DMA Channel 7
+                DCD     DMA_Channel8_IRQHandler    ; DMA Channel 8
+                DCD     ADC_IRQHandler             ; ADC
+                DCD     USB_HP_IRQHandler          ; USB High Priority
+                DCD     USB_LP_IRQHandler          ; USB Low  Priority
+                DCD     COMP_1_2_IRQHandler        ; COMP1 & COMP2 through EXTI line 21/22
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     TIM4_IRQHandler            ; TIM4
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     SPI2_IRQHandler            ; SPI2
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     USART3_IRQHandler          ; USART3
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
+                DCD     TIM8_BRK_IRQHandler        ; TIM8 Break
+                DCD     TIM8_UP_IRQHandler         ; TIM8 Update
+                DCD     TIM8_TRG_COM_IRQHandler    ; TIM8 Trigger and Commutation
+                DCD     TIM8_CC_IRQHandler         ; TIM8 Capture Compare
+                DCD     UART4_IRQHandler           ; UART4
+                DCD     UART5_IRQHandler           ; UART5
+                DCD     LPUART_IRQHandler          ; LPUART
+                DCD     TIM5_IRQHandler            ; TIM5
+                DCD     TIM6_IRQHandler            ; TIM6
+                DCD     TIM7_IRQHandler            ; TIM7
+                DCD     CAN_TX_IRQHandler          ; CAN TX
+                DCD     CAN_RX0_IRQHandler         ; CAN RX0
+                DCD     CAN_RX1_IRQHandler         ; CAN RX1
+                DCD     CAN_SCE_IRQHandler         ; CAN SCE
+                DCD     LPUART_WKUP_IRQHandler     ; LPUART_WKUP
+                DCD     LPTIM_WKUP_IRQHandler      ; LPTIM_WKUP
+                DCD     0                          ; Reserved
+                DCD     SAC_IRQHandler             ; SAC
+                DCD     MMU_IRQHandler             ; MMU
+                DCD     TSC_IRQHandler             ; TSC
+                DCD     RAMC_PERR_IRQHandler       ; RAMC ERR
+                DCD     TIM9_IRQHandler            ; TIM9
+                DCD     UCDR_IRQHandler            ; UCDR ERR
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+                
+; Reset handler
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  __main
+                IMPORT  SystemInit
+                LDR     R0, =SystemInit
+                BLX     R0               
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+                
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA_Channel1_IRQHandler    [WEAK]
+                EXPORT  DMA_Channel2_IRQHandler    [WEAK]
+                EXPORT  DMA_Channel3_IRQHandler    [WEAK]
+                EXPORT  DMA_Channel4_IRQHandler    [WEAK]
+                EXPORT  DMA_Channel5_IRQHandler    [WEAK]
+                EXPORT  DMA_Channel6_IRQHandler    [WEAK]
+                EXPORT  DMA_Channel7_IRQHandler    [WEAK]
+                EXPORT  DMA_Channel8_IRQHandler    [WEAK]
+                EXPORT  ADC_IRQHandler             [WEAK]
+                EXPORT  USB_HP_IRQHandler          [WEAK]
+                EXPORT  USB_LP_IRQHandler          [WEAK]
+                EXPORT  COMP_1_2_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  USBWakeUp_IRQHandler       [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM8_UP_IRQHandler         [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM8_CC_IRQHandler         [WEAK]
+                EXPORT  UART4_IRQHandler           [WEAK]
+                EXPORT  UART5_IRQHandler           [WEAK]
+                EXPORT  LPUART_IRQHandler          [WEAK]
+                EXPORT  TIM5_IRQHandler            [WEAK]
+                EXPORT  TIM6_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler            [WEAK]
+                EXPORT  CAN_TX_IRQHandler          [WEAK]
+                EXPORT  CAN_RX0_IRQHandler         [WEAK]
+                EXPORT  CAN_RX1_IRQHandler         [WEAK]
+                EXPORT  CAN_SCE_IRQHandler         [WEAK]
+                EXPORT  LPUART_WKUP_IRQHandler     [WEAK]
+                EXPORT  LPTIM_WKUP_IRQHandler      [WEAK]
+                EXPORT  SAC_IRQHandler             [WEAK]
+                EXPORT  MMU_IRQHandler             [WEAK]
+                EXPORT  TSC_IRQHandler             [WEAK]
+                EXPORT  RAMC_PERR_IRQHandler       [WEAK]
+                EXPORT  TIM9_IRQHandler            [WEAK]
+                EXPORT  UCDR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA_Channel1_IRQHandler
+DMA_Channel2_IRQHandler
+DMA_Channel3_IRQHandler
+DMA_Channel4_IRQHandler
+DMA_Channel5_IRQHandler
+DMA_Channel6_IRQHandler
+DMA_Channel7_IRQHandler
+DMA_Channel8_IRQHandler
+ADC_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+COMP_1_2_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+CAN_TX_IRQHandler
+CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+LPUART_WKUP_IRQHandler
+LPTIM_WKUP_IRQHandler
+SAC_IRQHandler
+MMU_IRQHandler
+TSC_IRQHandler
+RAMC_PERR_IRQHandler
+TIM9_IRQHandler
+UCDR_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_EWARM.s

@@ -0,0 +1,523 @@
+; ****************************************************************************
+; Copyright (c) 2019, Nations Technologies Inc.
+;
+; All rights reserved.
+; ****************************************************************************
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; - Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the disclaimer below.
+;
+; Nations name may not be used to endorse or promote products derived from
+; this software without specific prior written permission.
+;
+; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; ****************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+  
+    MODULE  ?cstartup
+        
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit        
+        PUBLIC  __vector_table
+
+        DATA
+       
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler           ; Window Watchdog
+        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+        DCD     TAMPER_IRQHandler         ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt
+        DCD     RTC_WKUP_IRQHandler       ; RTC_WKUP
+        DCD     FLASH_IRQHandler          ; Flash
+        DCD     RCC_IRQHandler            ; RCC
+        DCD     EXTI0_IRQHandler          ; EXTI Line 0
+        DCD     EXTI1_IRQHandler          ; EXTI Line 1
+        DCD     EXTI2_IRQHandler          ; EXTI Line 2
+        DCD     EXTI3_IRQHandler          ; EXTI Line 3
+        DCD     EXTI4_IRQHandler          ; EXTI Line 4
+        DCD     DMA_Channel1_IRQHandler   ; DMA1 Channel 1
+        DCD     DMA_Channel2_IRQHandler   ; DMA1 Channel 2
+        DCD     DMA_Channel3_IRQHandler   ; DMA1 Channel 3
+        DCD     DMA_Channel4_IRQHandler   ; DMA1 Channel 4
+        DCD     DMA_Channel5_IRQHandler   ; DMA1 Channel 5
+        DCD     DMA_Channel6_IRQHandler   ; DMA1 Channel 6
+        DCD     DMA_Channel7_IRQHandler   ; DMA1 Channel 7
+        DCD     DMA_Channel8_IRQHandler   ; DMA Channel 8
+        DCD     ADC_IRQHandler            ; ADC
+        DCD     USB_HP_IRQHandler         ; USB High Priority
+        DCD     USB_LP_IRQHandler         ; USB Low  Priority
+        DCD     COMP_1_2_IRQHandler       ; COMP1 & COMP2 through EXTI line 21/22
+        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+        DCD     TIM1_BRK_IRQHandler       ; TIM1 Break
+        DCD     TIM1_UP_IRQHandler        ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler   ; TIM1 Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler        ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler           ; TIM2
+        DCD     TIM3_IRQHandler           ; TIM3
+        DCD     TIM4_IRQHandler           ; TIM4
+        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+        DCD     SPI1_IRQHandler           ; SPI1
+        DCD     SPI2_IRQHandler           ; SPI2
+        DCD     USART1_IRQHandler         ; USART1
+        DCD     USART2_IRQHandler         ; USART2
+        DCD     USART3_IRQHandler         ; USART3
+        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+        DCD     RTCAlarm_IRQHandler       ; RTC Alarm through EXTI Line
+        DCD     USBWakeUp_IRQHandler      ; USB Wakeup from suspend
+        DCD     TIM8_BRK_IRQHandler       ; TIM8 Break
+        DCD     TIM8_UP_IRQHandler        ; TIM8 Update
+        DCD     TIM8_TRG_COM_IRQHandler   ; TIM8 Trigger and Commutation
+        DCD     TIM8_CC_IRQHandler        ; TIM8 Capture Compare
+        DCD     UART4_IRQHandler          ; UART4
+        DCD     UART5_IRQHandler          ; UART5
+        DCD     LPUART_IRQHandler         ; LPUART
+        DCD     TIM5_IRQHandler           ; TIM5
+        DCD     TIM6_IRQHandler           ; TIM6
+        DCD     TIM7_IRQHandler           ; TIM7
+        DCD     CAN_TX_IRQHandler         ; CAN TX
+        DCD     CAN_RX0_IRQHandler        ; CAN RX0
+        DCD     CAN_RX1_IRQHandler        ; CAN RX1
+        DCD     CAN_SCE_IRQHandler        ; CAN SCE
+        DCD     LPUART_WKUP_IRQHandler    ; LPUART_WKUP
+        DCD     LPTIM_WKUP_IRQHandler     ; LPTIM_WKUP
+        DCD     LCD_IRQHandler            ; LCD
+        DCD     SAC_IRQHandler            ; SAC
+        DCD     MMU_IRQHandler            ; MMU
+        DCD     TSC_IRQHandler            ; TSC
+        DCD     RAMC_PERR_IRQHandler      ; RAMC ERR
+        DCD     TIM9_IRQHandler           ; TIM9
+        DCD     UCDR_IRQHandler           ; UCDR ERR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+               
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+
+        PUBWEAK TAMPER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TAMPER_IRQHandler
+        B TAMPER_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel1_IRQHandler
+        B DMA_Channel1_IRQHandler
+
+        PUBWEAK DMA_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel2_IRQHandler
+        B DMA_Channel2_IRQHandler
+
+        PUBWEAK DMA_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel3_IRQHandler
+        B DMA_Channel3_IRQHandler
+
+        PUBWEAK DMA_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel4_IRQHandler
+        B DMA_Channel4_IRQHandler
+
+        PUBWEAK DMA_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel5_IRQHandler
+        B DMA_Channel5_IRQHandler
+
+        PUBWEAK DMA_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel6_IRQHandler
+        B DMA_Channel6_IRQHandler
+
+        PUBWEAK DMA_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel7_IRQHandler
+        B DMA_Channel7_IRQHandler
+
+        PUBWEAK DMA_Channel8_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA_Channel8_IRQHandler
+        B DMA_Channel8_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+
+        PUBWEAK COMP_1_2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+COMP_1_2_IRQHandler
+        B COMP_1_2_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTCAlarm_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTCAlarm_IRQHandler
+        B RTCAlarm_IRQHandler
+
+        PUBWEAK USBWakeUp_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USBWakeUp_IRQHandler
+        B USBWakeUp_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK LPUART_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LPUART_IRQHandler
+        B LPUART_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK CAN_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_TX_IRQHandler
+        B CAN_TX_IRQHandler
+
+        PUBWEAK CAN_RX0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_RX0_IRQHandler
+        B CAN_RX0_IRQHandler
+
+        PUBWEAK CAN_RX1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_RX1_IRQHandler
+        B CAN_RX1_IRQHandler
+
+        PUBWEAK CAN_SCE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN_SCE_IRQHandler
+        B CAN_SCE_IRQHandler
+
+        PUBWEAK LPUART_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LPUART_WKUP_IRQHandler
+        B LPUART_WKUP_IRQHandler
+
+        PUBWEAK LPTIM_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LPTIM_WKUP_IRQHandler
+        B LPTIM_WKUP_IRQHandler
+
+        PUBWEAK LCD_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LCD_IRQHandler
+        B LCD_IRQHandler
+
+        PUBWEAK SAC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SAC_IRQHandler
+        B SAC_IRQHandler
+
+        PUBWEAK MMU_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MMU_IRQHandler
+        B MMU_IRQHandler
+
+        PUBWEAK TSC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TSC_IRQHandler
+        B TSC_IRQHandler
+
+        PUBWEAK RAMC_PERR_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RAMC_PERR_IRQHandler
+        B RAMC_PERR_IRQHandler
+
+        PUBWEAK TIM9_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM9_IRQHandler
+        B TIM9_IRQHandler
+
+        PUBWEAK UCDR_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UCDR_IRQHandler
+        B UCDR_IRQHandler
+        
+		
+        END
+

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_gcc.s

@@ -0,0 +1,450 @@
+/**
+  ****************************************************************************
+  Copyright (c) 2019, Nations Technologies Inc.
+
+  All rights reserved.
+  ****************************************************************************
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions are met:
+
+  - Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the disclaimer below.
+
+  Nations' name may not be used to endorse or promote products derived from
+  this software without specific prior written permission.
+
+  DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+  DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  ****************************************************************************
+ **/
+
+/**
+******************************************************************************
+* @file      startup_n32g43x_gcc.s
+******************************************************************************
+*/
+    
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+  .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+  Reset_Handler:  
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit   
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                     /* Window WatchDog                      */                                        
+  .word     PVD_IRQHandler                      /* PVD through EXTI Line detection      */                        
+  .word     TAMPER_IRQHandler                   /* Tamper                               */            
+  .word     RTC_WKUP_IRQHandler                 /* RTC Wakeup                           */                      
+  .word     FLASH_IRQHandler                    /* FLASH                                */                                          
+  .word     RCC_IRQHandler                      /* RCC                                  */                                            
+  .word     EXTI0_IRQHandler                    /* EXTI Line0                           */                        
+  .word     EXTI1_IRQHandler                    /* EXTI Line1                           */                          
+  .word     EXTI2_IRQHandler                    /* EXTI Line2                           */                          
+  .word     EXTI3_IRQHandler                    /* EXTI Line3                           */                          
+  .word     EXTI4_IRQHandler                    /* EXTI Line4                           */                          
+  .word     DMA_Channel1_IRQHandler            /* DMA1 Channel 1                       */                  
+  .word     DMA_Channel2_IRQHandler            /* DMA1 Channel 2                       */                   
+  .word     DMA_Channel3_IRQHandler            /* DMA1 Channel 3                       */                   
+  .word     DMA_Channel4_IRQHandler            /* DMA1 Channel 4                       */                   
+  .word     DMA_Channel5_IRQHandler            /* DMA1 Channel 5                       */                   
+  .word     DMA_Channel6_IRQHandler            /* DMA1 Channel 6                       */                   
+  .word     DMA_Channel7_IRQHandler            /* DMA1 Channel 7                       */       
+  .word     DMA_Channel8_IRQHandler             /* DMA1 Channel 8                       */ 
+  .word     ADC_IRQHandler                      /* ADC                                  */                   
+  .word     USB_HP_IRQHandler                   /* USB High Priority                    */                         
+  .word     USB_LP_IRQHandler                   /* USB Low  Priority                    */                          
+  .word     COMP_1_2_IRQHandler                 /* COMP1 & COMP2 through EXTI line 21/22    */                          
+  .word     EXTI9_5_IRQHandler                  /* EXTI Line 9..5                       */                          
+  .word     TIM1_BRK_IRQHandler                 /* TIM1 Break                           */
+  .word     TIM1_UP_IRQHandler                  /* TIM1 Update                          */         
+  .word     TIM1_TRG_COM_IRQHandler             /* TIM1 Trigger and Commutation         */
+  .word     TIM1_CC_IRQHandler                  /* TIM1 Capture Compare                 */                          
+  .word     TIM2_IRQHandler                     /* TIM2                                 */                   
+  .word     TIM3_IRQHandler                     /* TIM3                                 */                   
+  .word     TIM4_IRQHandler                     /* TIM4                                 */                   
+  .word     I2C1_EV_IRQHandler                  /* I2C1 Event                           */                          
+  .word     I2C1_ER_IRQHandler                  /* I2C1 Error                           */                          
+  .word     I2C2_EV_IRQHandler                  /* I2C2 Event                           */                          
+  .word     I2C2_ER_IRQHandler                  /* I2C2 Error                           */                            
+  .word     SPI1_IRQHandler                     /* SPI1                                 */                   
+  .word     SPI2_IRQHandler                     /* SPI2                                 */                   
+  .word     USART1_IRQHandler                   /* USART1                               */                   
+  .word     USART2_IRQHandler                   /* USART2                               */                   
+  .word     USART3_IRQHandler                   /* USART3                               */                   
+  .word     EXTI15_10_IRQHandler                /* EXTI Line 15..10                     */                          
+  .word     RTCAlarm_IRQHandler                 /* RTC Alarm through EXTI Line          */                 
+  .word     USBWakeUp_IRQHandler                /* USB Wakeup from suspend              */                       
+  .word     TIM8_BRK_IRQHandler                 /* TIM8 Break                           */         
+  .word     TIM8_UP_IRQHandler                  /* TIM8 Update                          */         
+  .word     TIM8_TRG_COM_IRQHandler             /* TIM8 Trigger and Commutation         */
+  .word     TIM8_CC_IRQHandler                  /* TIM8 Capture Compare                 */                          
+  .word     UART4_IRQHandler                    /* UART4                                */                   
+  .word     UART5_IRQHandler                    /* UART5                                */       
+  .word     LPUART_IRQHandler                   /* LPUART                               */
+  .word     TIM5_IRQHandler                     /* TIM5                                 */   
+  .word     TIM6_IRQHandler                     /* TIM6                                 */                   
+  .word     TIM7_IRQHandler                     /* TIM7                                 */
+  .word     CAN_TX_IRQHandler                   /* CAN TX                               */                          
+  .word     CAN_RX0_IRQHandler                  /* CAN RX0                              */                          
+  .word     CAN_RX1_IRQHandler                  /* CAN RX1                              */                          
+  .word     CAN_SCE_IRQHandler                  /* CAN SCE                              */                          
+  .word     LPUART_WKUP_IRQHandler              /* LPUART_WKUP                          */                   
+  .word     LPTIM_WKUP_IRQHandler               /* LPTIM_WKUP                           */                   
+  .word     LCD_IRQHandler                      /* LCD                                  */                   
+  .word     SAC_IRQHandler                      /* SAC                                  */                   
+  .word     MMU_IRQHandler                      /* MMU                                  */
+  .word     TSC_IRQHandler                      /* TSC                                  */
+  .word     RAMC_PERR_IRQHandler                /* RAMC ERR                             */
+  .word     TIM9_IRQHandler                     /* TIM9                                 */
+  .word     UCDR_IRQHandler                     /* UCDR ERR                             */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler                   
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+                  
+   .weak      PVD_IRQHandler      
+   .thumb_set PVD_IRQHandler,Default_Handler
+               
+   .weak      TAMPER_IRQHandler            
+   .thumb_set TAMPER_IRQHandler,Default_Handler
+            
+   .weak      RTC_WKUP_IRQHandler                  
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+            
+   .weak      FLASH_IRQHandler         
+   .thumb_set FLASH_IRQHandler,Default_Handler
+                  
+   .weak      RCC_IRQHandler      
+   .thumb_set RCC_IRQHandler,Default_Handler
+                  
+   .weak      EXTI0_IRQHandler         
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+                  
+   .weak      EXTI1_IRQHandler         
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+                     
+   .weak      EXTI2_IRQHandler         
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+                 
+   .weak      EXTI3_IRQHandler         
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+                        
+   .weak      EXTI4_IRQHandler         
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+                  
+   .weak      DMA_Channel1_IRQHandler               
+   .thumb_set DMA_Channel1_IRQHandler,Default_Handler
+         
+   .weak      DMA_Channel2_IRQHandler               
+   .thumb_set DMA_Channel2_IRQHandler,Default_Handler
+                  
+   .weak      DMA_Channel3_IRQHandler               
+   .thumb_set DMA_Channel3_IRQHandler,Default_Handler
+                  
+   .weak      DMA_Channel4_IRQHandler               
+   .thumb_set DMA_Channel4_IRQHandler,Default_Handler 
+                 
+   .weak      DMA_Channel5_IRQHandler              
+   .thumb_set DMA_Channel5_IRQHandler,Default_Handler
+                  
+   .weak      DMA_Channel6_IRQHandler               
+   .thumb_set DMA_Channel6_IRQHandler,Default_Handler
+                  
+   .weak      DMA_Channel7_IRQHandler               
+   .thumb_set DMA_Channel7_IRQHandler,Default_Handler
+
+   .weak      DMA_Channel8_IRQHandler               
+   .thumb_set DMA_Channel8_IRQHandler,Default_Handler
+   
+   .weak      ADC_IRQHandler      
+   .thumb_set ADC_IRQHandler,Default_Handler
+               
+   .weak      USB_HP_IRQHandler   
+   .thumb_set USB_HP_IRQHandler,Default_Handler
+            
+   .weak      USB_LP_IRQHandler                  
+   .thumb_set USB_LP_IRQHandler,Default_Handler
+
+   .weak      COMP_1_2_IRQHandler                  
+   .thumb_set COMP_1_2_IRQHandler,Default_Handler
+ 
+   .weak      EXTI9_5_IRQHandler   
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+            
+   .weak      TIM1_BRK_IRQHandler            
+   .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+            
+   .weak      TIM1_UP_IRQHandler            
+   .thumb_set TIM1_UP_IRQHandler,Default_Handler
+      
+   .weak      TIM1_TRG_COM_IRQHandler      
+   .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+      
+   .weak      TIM1_CC_IRQHandler   
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                  
+   .weak      TIM2_IRQHandler            
+   .thumb_set TIM2_IRQHandler,Default_Handler
+                  
+   .weak      TIM3_IRQHandler            
+   .thumb_set TIM3_IRQHandler,Default_Handler
+                  
+   .weak      TIM4_IRQHandler            
+   .thumb_set TIM4_IRQHandler,Default_Handler
+                  
+   .weak      I2C1_EV_IRQHandler   
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                     
+   .weak      I2C1_ER_IRQHandler   
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                     
+   .weak      I2C2_EV_IRQHandler   
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                  
+   .weak      I2C2_ER_IRQHandler   
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+                           
+   .weak      SPI1_IRQHandler            
+   .thumb_set SPI1_IRQHandler,Default_Handler
+                        
+   .weak      SPI2_IRQHandler            
+   .thumb_set SPI2_IRQHandler,Default_Handler
+                  
+   .weak      USART1_IRQHandler      
+   .thumb_set USART1_IRQHandler,Default_Handler
+                     
+   .weak      USART2_IRQHandler      
+   .thumb_set USART2_IRQHandler,Default_Handler
+                     
+   .weak      USART3_IRQHandler      
+   .thumb_set USART3_IRQHandler,Default_Handler
+                  
+   .weak      EXTI15_10_IRQHandler               
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+               
+   .weak      RTCAlarm_IRQHandler               
+   .thumb_set RTCAlarm_IRQHandler,Default_Handler
+            
+   .weak      USBWakeUp_IRQHandler         
+   .thumb_set USBWakeUp_IRQHandler,Default_Handler
+            
+   .weak      TIM8_BRK_IRQHandler         
+   .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+         
+   .weak      TIM8_UP_IRQHandler            
+   .thumb_set TIM8_UP_IRQHandler,Default_Handler
+         
+   .weak      TIM8_TRG_COM_IRQHandler      
+   .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+      
+   .weak      TIM8_CC_IRQHandler   
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                  
+   .weak      UART4_IRQHandler         
+   .thumb_set UART4_IRQHandler,Default_Handler
+                  
+   .weak      UART5_IRQHandler         
+   .thumb_set UART5_IRQHandler,Default_Handler
+   
+   .weak      LPUART_IRQHandler         
+   .thumb_set LPUART_IRQHandler,Default_Handler
+                  
+   .weak      TIM5_IRQHandler            
+   .thumb_set TIM5_IRQHandler,Default_Handler
+                  
+   .weak      TIM6_IRQHandler                  
+   .thumb_set TIM6_IRQHandler,Default_Handler
+               
+   .weak      TIM7_IRQHandler            
+   .thumb_set TIM7_IRQHandler,Default_Handler
+            
+   .weak      CAN_TX_IRQHandler   
+   .thumb_set CAN_TX_IRQHandler,Default_Handler
+                           
+   .weak      CAN_RX0_IRQHandler                  
+   .thumb_set CAN_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN_RX1_IRQHandler                  
+   .thumb_set CAN_RX1_IRQHandler,Default_Handler
+                           
+   .weak      CAN_SCE_IRQHandler                  
+   .thumb_set CAN_SCE_IRQHandler,Default_Handler
+                           
+   .weak      LPUART_WKUP_IRQHandler      
+   .thumb_set LPUART_WKUP_IRQHandler,Default_Handler
+                     
+   .weak      LPTIM_WKUP_IRQHandler               
+   .thumb_set LPTIM_WKUP_IRQHandler,Default_Handler
+
+   .weak      LCD_IRQHandler            
+   .thumb_set LCD_IRQHandler,Default_Handler
+   
+   .weak      SAC_IRQHandler            
+   .thumb_set SAC_IRQHandler,Default_Handler
+               
+   .weak      MMU_IRQHandler                  
+   .thumb_set MMU_IRQHandler,Default_Handler   
+
+   .weak      TSC_IRQHandler                  
+   .thumb_set TSC_IRQHandler,Default_Handler  
+    
+   .weak      RAMC_PERR_IRQHandler                  
+   .thumb_set RAMC_PERR_IRQHandler,Default_Handler  
+    
+   .weak      TIM9_IRQHandler                  
+   .thumb_set TIM9_IRQHandler,Default_Handler  
+   
+   .weak      UCDR_IRQHandler                  
+   .thumb_set UCDR_IRQHandler,Default_Handler  
+   
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.c

@@ -0,0 +1,615 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file system_n32g43x.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x.h"
+
+/* Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+
+   IMPORTANT NOTE:
+   ==============
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your
+   device's maximum frequency.
+
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume
+   that:
+        - For Low, Medium and High density Value line devices an external 8MHz
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to
+   drive the System clock. If you are using different crystal you have to adapt
+   those functions accordingly.
+    */
+
+#define SYSCLK_USE_MSI     0
+#define SYSCLK_USE_HSI     1
+#define SYSCLK_USE_HSE     2
+#define SYSCLK_USE_HSI_PLL 3
+#define SYSCLK_USE_HSE_PLL 4
+
+#ifndef SYSCLK_FREQ
+#define SYSCLK_FREQ 108000000
+#endif
+
+/*
+* SYSCLK_SRC *
+** SYSCLK_USE_MSI      **
+** SYSCLK_USE_HSI      **
+** SYSCLK_USE_HSE      **
+** SYSCLK_USE_HSI_PLL  **
+** SYSCLK_USE_HSE_PLL  **
+*/
+#ifndef SYSCLK_SRC
+#define SYSCLK_SRC SYSCLK_USE_HSE_PLL
+#endif
+
+#define PLL_DIV2_DISABLE 0x00000000
+#define PLL_DIV2_ENABLE 0x00000002
+
+#if SYSCLK_SRC == SYSCLK_USE_MSI
+
+    #if (SYSCLK_FREQ == MSI_VALUE_L0)
+        #define MSI_CLK 0
+    #elif (SYSCLK_FREQ == MSI_VALUE_L1)
+        #define MSI_CLK 1
+    #elif (SYSCLK_FREQ == MSI_VALUE_L2)
+        #define MSI_CLK 2
+    #elif (SYSCLK_FREQ == MSI_VALUE_L3)
+        #define MSI_CLK 3
+    #elif (SYSCLK_FREQ == MSI_VALUE_L4)
+        #define MSI_CLK 4
+    #elif (SYSCLK_FREQ == MSI_VALUE_L5)
+        #define MSI_CLK 5
+    #elif (SYSCLK_FREQ == MSI_VALUE_L6)
+        #define MSI_CLK 6
+    #else
+        #error SYSCL_FREQ must be set to MSI_VALUE_Lx(x=0~6)
+    #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSI
+
+    #if SYSCLK_FREQ != HSI_VALUE
+        #error SYSCL_FREQ must be set to HSI_VALUE
+    #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSE
+
+    #ifndef HSE_VALUE
+        #error HSE_VALUE must be defined!
+    #endif
+
+    #if SYSCLK_FREQ != HSE_VALUE
+        #error SYSCL_FREQ must be set to HSE_VALUE
+    #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL
+
+    #ifndef HSI_VALUE
+        #error HSI_VALUE must be defined!
+    #endif
+
+    #if ((SYSCLK_FREQ % (HSI_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2)                                     \
+        && (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32)
+
+        #define PLLSRC_DIV 2
+        #define PLL_DIV    PLL_DIV2_DISABLE
+        #define PLL_MUL    (SYSCLK_FREQ / (HSI_VALUE / 2))
+
+    #elif (SYSCLK_FREQ % HSI_VALUE == 0) && (SYSCLK_FREQ / HSI_VALUE >= 2) && (SYSCLK_FREQ / HSI_VALUE <= 32)
+
+        #define PLLSRC_DIV 1
+        #define PLL_DIV    PLL_DIV2_DISABLE
+        #define PLL_MUL    (SYSCLK_FREQ / HSI_VALUE)
+
+    #elif ((SYSCLK_FREQ % (HSI_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 4) >= 2)                                     \
+          && (SYSCLK_FREQ / (HSI_VALUE / 4) <= 32)
+
+        #define PLLSRC_DIV 2
+        #define PLL_DIV    PLL_DIV2_ENABLE
+        #define PLL_MUL    (SYSCLK_FREQ / (HSI_VALUE / 4))
+
+    #else
+        #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
+    #endif
+
+#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+
+    #ifndef HSE_VALUE
+        #error HSE_VALUE must be defined!
+    #endif
+
+    #if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2)                                     \
+        && (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32)
+
+        #define PLLSRC_DIV 2
+        #define PLL_DIV    PLL_DIV2_DISABLE
+        #define PLL_MUL    (SYSCLK_FREQ / (HSE_VALUE / 2))
+
+    #elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2) && (SYSCLK_FREQ / HSE_VALUE <= 32)
+
+        #define PLLSRC_DIV 1
+        #define PLL_DIV    PLL_DIV2_DISABLE
+        #define PLL_MUL    (SYSCLK_FREQ / HSE_VALUE)
+
+    #elif ((SYSCLK_FREQ % (HSE_VALUE / 4)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 4) >= 2)                                     \
+          && (SYSCLK_FREQ / (HSE_VALUE / 4) <= 32)
+
+        #define PLLSRC_DIV 2
+        #define PLL_DIV    PLL_DIV2_ENABLE
+        #define PLL_MUL    (SYSCLK_FREQ / (HSE_VALUE / 4))
+
+    #else
+        #error Cannot make a PLL multiply factor to SYSCLK_FREQ.
+    #endif
+
+#else
+#error wrong value for SYSCLK_SRC
+#endif
+
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */
+
+/*******************************************************************************
+ *  Clock Definitions
+ *******************************************************************************/
+uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint32_t MSIClockTable[7] = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3,
+                                   MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6};
+
+static void SetSysClock(void);
+
+#ifdef DATA_IN_ExtSRAM
+static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @brief  Setup the microcontroller system
+ *         Initialize the Embedded Flash Interface, the PLL and update the
+ *         SystemCoreClock variable.
+ * @note   This function should be used only after reset.
+ */
+void SystemInit(void)
+{
+    /* FPU settings
+     * ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+
+    /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+    /* Set MSIEN bit */
+    RCC->CTRLSTS |= (uint32_t)0x00000004;
+
+    /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */
+    RCC->CFG &= (uint32_t)0xF8FFC000;
+
+    /* Reset HSEON, CLKSSEN and PLLEN bits */
+    RCC->CTRL &= (uint32_t)0xFEF6FFFF;
+
+    /* Reset HSEBYP bit */
+    RCC->CTRL &= (uint32_t)0xFFFBFFFF;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL, MCOPRES and USBPRES bits */
+    RCC->CFG &= (uint32_t)0x0700FFFF;
+
+    /* Reset CFG2 register */
+    RCC->CFG2 = 0x00007000;
+
+    /* Reset CFG3 register */
+    RCC->CFG3 = 0x00003800;
+
+    /* Reset RDCTRL register */
+    RCC->RDCTRL = 0x00000000;
+
+    /* Reset PLLHSIPRE register */
+    RCC->PLLHSIPRE = 0x00000000;
+
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CLKINT = 0x04BF8000;
+
+    /* Enable ex mode */
+    RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN;
+    RCC->APB1PCLKEN &= (uint32_t)(~RCC_APB1PCLKEN_PWREN);
+
+    /* Enable ICACHE and Prefetch Buffer */
+    FLASH->AC |= (uint32_t)(FLASH_AC_ICAHEN | FLASH_AC_PRFTBFEN);
+
+    /* Checks whether the Low Voltage Mode status is SET or RESET */
+    if ((FLASH->AC & FLASH_AC_LVMF) != RESET)
+    {
+        /* FLASH Low Voltage Mode Disable */
+        FLASH->AC &= (uint32_t)(~FLASH_AC_LVMEN);
+    }
+
+#ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+    /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+    /* Configure the Flash Latency cycles and enable prefetch buffer */
+    SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief  Update SystemCoreClock variable according to Clock Register Values.
+ *         The SystemCoreClock variable contains the core clock (HCLK), it can
+ *         be used by the user application to setup the SysTick timer or
+ * configure other parameters.
+ *
+ * @note   Each time the core clock (HCLK) changes, this function must be called
+ *         to update SystemCoreClock variable value. Otherwise, any
+ * configuration based on this variable will be incorrect.
+ *
+ * @note   - The system frequency computed by this function is not the real
+ *           frequency in the chip. It is calculated based on the predefined
+ *           constant and the selected clock source:
+ *
+ *           - If SYSCLK source is MSI, SystemCoreClock will contain the
+ * MSI_VALUE(*)
+ *
+ *           - If SYSCLK source is HSI, SystemCoreClock will contain the
+ * HSI_VALUE(**)
+ *
+ *           - If SYSCLK source is HSE, SystemCoreClock will contain the
+ * HSE_VALUE(***)
+ *
+ *           - If SYSCLK source is PLL, SystemCoreClock will contain the
+ * HSE_VALUE(***) or HSI_VALUE(**) multiplied by the PLL factors.
+ *
+ *         (*) MSI_VALUE is a constant defined in n32g43x.h file (default value
+ *             4 MHz, 100KHz/200KHz/400KHz/800KHz/1MHz/2MHz/4MHz ) but the real
+ *             value may vary depending on the variations in voltage and temperature.
+ *
+ *         (**) HSI_VALUE is a constant defined in n32g43x.h file (default value
+ *             8 MHz) but the real value may vary depending on the variations
+ *             in voltage and temperature.
+ *
+ *         (***) HSE_VALUE is a constant defined in n32g43x.h file (default value
+ *              8 MHz or 25 MHz, depedning on the product used), user has to
+ *              ensure that HSE_VALUE is same as the real frequency of the crystal used.
+ *              Otherwise, this function may have wrong result.
+ *
+ *         - The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ */
+void SystemCoreClockUpdate(void)
+{
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0, plldiv2 = 0;
+    uint8_t msi_clk = 0;
+
+    /* Get SYSCLK source
+     * -------------------------------------------------------*/
+    tmp = RCC->CFG & RCC_CFG_SCLKSTS;
+
+    /* Get MSI clock
+     * -------------------------------------------------------*/
+    msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4);
+
+    switch (tmp)
+    {
+    case 0x00: /* MSI used as system clock */
+        SystemCoreClock = MSIClockTable[msi_clk];
+        break;
+    case 0x04: /* HSI used as system clock */
+        SystemCoreClock = HSI_VALUE;
+        break;
+    case 0x08: /* HSE used as system clock */
+        SystemCoreClock = HSE_VALUE;
+        break;
+    case 0x0C: /* PLL used as system clock */
+
+        /* Get PLL clock source and multiplication factor
+         * ----------------------*/
+        pllmull   = RCC->CFG & RCC_CFG_PLLMULFCT;
+        pllsource = RCC->CFG & RCC_CFG_PLLSRC;
+        plldiv2   = RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV;
+
+        if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
+        {
+            pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
+        }
+        else
+        {
+            pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
+        }
+
+        if (pllsource == 0x00)
+        {
+            /* HSI selected as PLL clock entry */
+            if ((RCC->PLLHSIPRE & RCC_PLLHSIPRE_PLLSRCDIV) != (uint32_t)RESET)
+            { /* HSI oscillator clock divided by 2 */
+                SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+            }
+            else
+            {
+                SystemCoreClock = HSI_VALUE * pllmull;
+            }
+        }
+        else
+        {
+            /* HSE selected as PLL clock entry */
+            if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET)
+            { /* HSE oscillator clock divided by 2 */
+                SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+            }
+            else
+            {
+                SystemCoreClock = HSE_VALUE * pllmull;
+            }
+        }
+
+        if (plldiv2 == 0x02)
+        {
+            /* PLL source clock divided by 2 selected as PLL clock entry */
+            SystemCoreClock >>= 1;
+        }
+
+        break;
+
+    default:
+        SystemCoreClock = MSIClockTable[msi_clk];
+        break;
+    }
+
+    /* Compute HCLK clock frequency ----------------*/
+    /* Get HCLK prescaler */
+    tmp = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)];
+    /* HCLK clock frequency */
+    SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1
+ * prescalers.
+ */
+static void SetSysClock(void)
+{
+    uint32_t rcc_cfg        = 0;
+    uint32_t rcc_pllhsipre  = 0;
+    uint32_t StartUpCounter = 0;
+
+#if (SYSCLK_SRC == SYSCLK_USE_MSI)
+    uint8_t i=0;
+    bool MSIStatus = 0;
+    /* Config MSI */
+    RCC->CTRLSTS &= 0xFFFFFF8F;
+    /*Delay for while*/
+    for(i=0;i<0x30;i++);
+    RCC->CTRLSTS |= (((uint32_t)MSI_CLK) << 4);
+    /*Delay for while*/
+    for(i=0;i<0x30;i++);
+    /* Enable MSI */
+    RCC->CTRLSTS |= ((uint32_t)RCC_CTRLSTS_MSIEN);
+
+    /* Wait till MSI is ready and if Time out is reached exit */
+    do
+    {
+        MSIStatus = RCC->CTRLSTS & RCC_CTRLSTS_MSIRD;
+        StartUpCounter++;
+    } while ((MSIStatus == 0) && (StartUpCounter != MSI_STARTUP_TIMEOUT));
+
+    MSIStatus = ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRD) != RESET);
+    if (!MSIStatus)
+    {
+        /* If MSI fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error */
+        SystemCoreClock = MSI_VALUE_L6;
+        return;
+    }
+
+#elif ((SYSCLK_SRC == SYSCLK_USE_HSI) || (SYSCLK_SRC == SYSCLK_USE_HSI_PLL))
+
+    bool HSIStatus = 0;
+    /* Enable HSI */
+    RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
+
+    /* Wait till HSI is ready and if Time out is reached exit */
+    do
+    {
+        HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF;
+        StartUpCounter++;
+    } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+    HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET);
+    if (!HSIStatus)
+    {
+        /* If HSI fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error */
+        SystemCoreClock = MSI_VALUE_L6;
+        return;
+    }
+
+#elif ((SYSCLK_SRC == SYSCLK_USE_HSE) || (SYSCLK_SRC == SYSCLK_USE_HSE_PLL))
+
+    bool HSEStatus = 0;
+    /* Enable HSE */
+    RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF;
+        StartUpCounter++;
+    } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    HSEStatus = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET);
+    if (!HSEStatus)
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error */
+        SystemCoreClock = MSI_VALUE_L6;
+        return;
+    }
+#endif
+
+    /* If the system clock is greater than 64MHz, the voltage range of the main voltage regulator
+       must be configured as 1.1V */
+    if (SYSCLK_FREQ >= 64000000)
+    {
+        /* Enables PWR peripheral clock */
+        RCC->APB1PCLKEN |= RCC_APB1_PERIPH_PWR;
+        /* Check PWR->CTRL1.MRSEL configuration */
+        if ((PWR->CTRL1 & ((uint32_t)PWR_CTRL1_MRSEL)) == ((uint32_t)PWR_CTRL1_MRSEL2))
+        {
+            /* Config 1.1V */
+            PWR->CTRL1 |= PWR_CTRL1_MRSEL1;
+        }
+    }
+
+    /* Flash wait state
+        0: HCLK <= 32M
+        1: HCLK <= 64M
+        2: HCLK <= 96M
+        3: HCLK <= 128M
+     */
+    FLASH->AC &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY);
+    FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / 32000000);
+
+    /* HCLK = SYSCLK */
+    RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1;
+
+    /* PCLK2 max 54M */
+    if (SYSCLK_FREQ > 54000000)
+    {
+        RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2;
+    }
+    else
+    {
+        RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1;
+    }
+
+    /* PCLK1 max 27M */
+    if (SYSCLK_FREQ > 54000000)
+    {
+        RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4;
+    }
+    else if (SYSCLK_FREQ > 27000000)
+    {
+        RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2;
+    }
+    else
+    {
+        RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1;
+    }
+
+#if SYSCLK_SRC == SYSCLK_USE_MSI
+    /* Select MSI as system clock source */
+    RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+    RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_MSI;
+
+    /* Wait till MSI is used as system clock source */
+    while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x00)
+    {
+    }
+#elif SYSCLK_SRC == SYSCLK_USE_HSI
+    /* Select HSI as system clock source */
+    RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+    RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSI;
+
+    /* Wait till HSI is used as system clock source */
+    while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x04)
+    {
+    }
+#elif SYSCLK_SRC == SYSCLK_USE_HSE
+    /* Select HSE as system clock source */
+    RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+    RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE;
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08)
+    {
+    }
+#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+
+    /* clear bits */
+    RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT));
+    RCC->PLLHSIPRE &= (uint32_t)((uint32_t) ~(RCC_PLLHSIPRE_PLLHSIPRE | RCC_PLLHSIPRE_PLLSRCDIV));
+
+    /* set PLL source */
+    rcc_cfg = RCC->CFG;
+    rcc_cfg |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI : RCC_CFG_PLLSRC_HSE);
+    /* PLL DIV */
+    rcc_pllhsipre = RCC->PLLHSIPRE;
+
+    #if SYSCLK_SRC == SYSCLK_USE_HSI_PLL
+        rcc_pllhsipre |= (PLLSRC_DIV == 1 ? RCC_PLLHSIPRE_PLLHSIPRE_HSI : RCC_PLLHSIPRE_PLLHSIPRE_HSI_DIV2);
+    #elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
+        rcc_cfg |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2);
+    #endif
+
+    /* set PLL DIV */
+    rcc_pllhsipre |= (PLL_DIV == PLL_DIV2_DISABLE ? RCC_PLLHSIPRE_PLLSRCDIV_DISABLE : RCC_PLLHSIPRE_PLLSRCDIV_ENABLE);
+
+    /* set PLL multiply factor */
+    #if PLL_MUL <= 16
+        rcc_cfg |= (PLL_MUL - 2) << 18;
+    #else
+        rcc_cfg |= ((PLL_MUL - 17) << 18) | (1 << 27);
+    #endif
+
+    RCC->CFG       = rcc_cfg;
+    RCC->PLLHSIPRE = rcc_pllhsipre;
+
+    /* Enable PLL */
+    RCC->CTRL |= RCC_CTRL_PLLEN;
+
+    /* Wait till PLL is ready */
+    while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
+    RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x0C)
+    {
+    }
+#endif
+}

bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.h

@@ -0,0 +1,59 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file system_n32g43x.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __SYSTEM_N32G43X_H__
+#define __SYSTEM_N32G43X_H__
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup N32G43X_System
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_N32G43X_H__ */

bsp/n32/libraries/N32G43x_Firmware_Library/SConscript

@@ -0,0 +1,63 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Split('''
+CMSIS/device/system_n32g43x.c
+n32g43x_std_periph_driver/src/n32g43x_gpio.c
+n32g43x_std_periph_driver/src/n32g43x_rcc.c
+n32g43x_std_periph_driver/src/n32g43x_exti.c
+n32g43x_std_periph_driver/src/misc.c
+''')
+    
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['n32g43x_std_periph_driver/src/n32g43x_usart.c']
+    
+if GetDepend(['RT_USING_I2C']):
+    src += ['n32g43x_std_periph_driver/src/n32g43x_i2c.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['n32g43x_std_periph_driver/src/n32g43x_spi.c']
+
+if GetDepend(['RT_USING_CAN']):
+    src += ['n32g43x_std_periph_driver/src/n32g43x_can.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += ['n32g43x_std_periph_driver/src/n32g43x_adc.c']
+
+if GetDepend(['RT_USING_DAC']):
+    src += ['n32g43x_std_periph_driver/src/n32g43x_dac.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+    src += ['n32g43x_std_periph_driver/src/n32g43x_tim.c']
+
+if GetDepend(['RT_USING_RTC']):
+    src += ['n32g43x_std_periph_driver/src/n32g43x_rtc.c']
+    src += ['n32g43x_std_periph_driver/src/n32g43x_pwr.c']
+    src += ['n32g43x_std_periph_driver/src/n32g43x_flash.c']
+
+if GetDepend(['RT_USING_WDT']):
+    src += ['n32g43x_std_periph_driver/src/n32g43x_iwdg.c']
+    src += ['n32g43x_std_periph_driver/src/n32g43x_wwdg.c']
+    
+if GetDepend(['RT_USING_BSP_USB']):
+    path += [cwd + '/n32g43x_usbfs_driver/inc']
+    src  += [cwd + '/n32g43x_usbfs_driver/src']
+
+path = [
+    cwd + '/CMSIS/device',
+    cwd + '/CMSIS/core',
+    cwd + '/n32g43x_std_periph_driver/inc',]
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER']
+
+
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_aes.h

@@ -0,0 +1,119 @@
+/*****************************************************************************
+*         NationS Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, NationS Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* NationS's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: n32g43x_aes.h
+* Function: Declaring AES algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+#ifndef __N32G43X_AES_H__
+#define __N32G43X_AES_H__
+
+#include <stdint.h>
+
+#define AES_ECB (0x11111111)
+#define AES_CBC (0x22222222)
+#define AES_CTR (0x33333333)
+
+#define AES_ENC  (0x44444444)
+#define AES_DEC  (0x55555555)
+
+enum
+{
+    AES_Crypto_OK = 0x0,   //AES opreation success
+    AES_Init_OK = 0x0,   //AES Init opreation success
+    AES_Crypto_ModeError = 0x5a5a5a5a,   //Working mode error(Neither ECB nor CBC nor CTR)
+    AES_Crypto_EnOrDeError,    //En&De error(Neither encryption nor decryption)
+    AES_Crypto_ParaNull,    // the part of input(output/iv) Null
+    AES_Crypto_LengthError,     // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
+                                //if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
+
+    AES_Crypto_KeyLengthError, //the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError
+  AES_Crypto_UnInitError, //AES uninitialized
+};
+
+typedef struct
+{
+    uint32_t *in;       // the part of input to be encrypted or decrypted
+    uint32_t *iv;       // the part of initial vector
+    uint32_t *out;      // the part of out
+    uint32_t *key;      // the part of key
+    uint32_t keyWordLen;   // the length(by word) of key
+    uint32_t inWordLen; // the length(by word) of plaintext or cipher
+    uint32_t En_De; // 0x44444444- encrypt, 0x55555555 - decrypt
+    uint32_t Mode;  // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR
+}AES_PARM;
+
+ /**
+ * @brief AES_Init
+ * @return AES_Init_OK, AES Init success; othets: AES Init fail
+ * @note
+ */
+
+uint32_t  AES_Init(AES_PARM *parm);
+
+/**
+ * @brief AES crypto
+ * @param[in] parm pointer to AES context and the detail please refer to struct AES_PARM in AES.h
+ * @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation)
+ * @note  1.Please refer to the demo in user guidance before using this function
+ *        2.Input and output can be the same buffer
+ *        3. IV can be NULL when ECB mode
+ *        4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
+ *           if Working mode is CTR,the length of input message cannot be zero;
+ *        5. If the input is in byte, make sure align by word.
+ */
+uint32_t AES_Crypto(AES_PARM *parm);
+
+/**
+ * @brief AES close
+ * @return none
+ * @note if you want to close AES algorithm, this function can be recalled.
+ */
+void AES_Close(void);
+
+/**
+ * @brief Get AES lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get AES lib information
+ */
+void AES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+
+
+
+#endif
+
+

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_algo_common.h

@@ -0,0 +1,154 @@
+/*****************************************************************************
+*         NationS Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, NationS Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* NationS's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: Common.h
+* Function: Defining the public functions used by other algorithm lib
+* version: V1.2.0
+* Author: huang.jinshang
+* date: 2020-01-06
+* ****************************************************************************/
+
+#ifndef _N32G43X_ALGO_COMMON_H_
+#define _N32G43X_ALGO_COMMON_H_
+
+#include <stdint.h>
+
+
+enum{
+  Cpy_OK=0,//copy success
+    SetZero_OK = 0,//set zero success
+    XOR_OK = 0,   //XOR success
+    Reverse_OK = 0, //Reverse success
+    Cmp_EQUAL = 0, //Two big number are equal
+    Cmp_UNEQUAL = 1, //Two big number are not equal
+
+};
+
+/**
+ * @brief disturb the sequence order
+ * @param[in] order pointer to the sequence to be disturbed
+ * @param[in] rand pointer to random number
+ * @param[in] the length of order
+ * @return RandomSort_OK:  disturb order success;  Others: disturb order fail;
+ * @note
+ */
+uint32_t RandomSort(uint8_t *order, const  uint8_t *rand, uint32_t len);
+
+/**
+ * @brief Copy data by byte
+ * @param[in]  dst pointer to destination data
+ * @param[in]  src pointer to source data
+ * @param[in]  byte length
+ * @return Cpy_OK: success; others: fail.
+ * @note 1. dst and  src cannot be same
+ */
+uint32_t Cpy_U8( uint8_t *dst,  uint8_t *src,  uint32_t byteLen);
+
+/**
+ * @brief Copy data by word
+ * @param[in]  dst pointer to destination data
+ * @param[in]  src pointer to source data
+ * @param[in]  word length
+ * @return Cpy_OK: success; others: fail.
+ * @note 1. dst and  src must be aligned by word
+ */
+uint32_t Cpy_U32( uint32_t *dst, const uint32_t *src,  uint32_t wordLen);
+
+ /**
+ * @brief XOR
+ * @param[in] a pointer to one data to be XORed
+ * @param[in] b pointer to another data to be XORed
+ * @param[in] the length of order
+ * @return XOR_OK:  operation success;  Others: operation fail;
+ * @note
+ */
+uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
+
+ /**
+ * @brief XORed two u32 arrays
+ * @param[in] a pointer to one data to be XORed
+ * @param[in] b pointer to another data to be XORed
+ * @param[in] the length of order
+ * @return XOR_OK:  operation success;  Others: operation fail;
+ * @note
+ */
+uint32_t XOR_U32(uint32_t *a,uint32_t *b,uint32_t *c,uint32_t wordLen);
+
+/**
+ * @brief set zero by byte
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in]  byte length
+ * @return SetZero_OK: success; others: fail.
+ * @note
+ */
+uint32_t SetZero_U8(uint8_t *dst, uint32_t byteLen);
+
+/**
+ * @brief set zero by word
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in]  word length
+ * @return SetZero_OK: success; others: fail.
+ * @note
+ */
+uint32_t SetZero_U32(uint32_t *dst, uint32_t wordLen);
+
+/**
+ * @brief reverse byte order of every word, the words stay the same
+ * @param[in]  dst pointer to the destination address
+ * @param[in]  src pointer to the source address
+ * @param[in]  word length
+ * @return Reverse_OK: success; others: fail.
+ * @note 1.dst and src can be same
+ */
+uint32_t ReverseBytesInWord_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);
+
+/**
+ * @brief compare two big number
+ * @param[in] a pointer to one big number
+ * @param[in] word length of a
+ * @param[in] b pointer to another big number
+ * @param[in]  word length of b
+ * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
+ *
+ */
+int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_t bWordLen);
+
+/**
+ * @brief compare two big number
+ * @param[in] a pointer to one big number
+ * @param[in] word length of a
+ * @param[in] b pointer to another big number
+ * @param[in]  word length of b
+ * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
+ *
+ */
+int32_t Cmp_U8(const  uint8_t *a, uint32_t aByteLen, const uint8_t *b, uint32_t bByteLen);
+
+
+#endif
+

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_des.h

@@ -0,0 +1,115 @@
+/*****************************************************************************
+*         Nations Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, Nations Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nations's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY Nations "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL Nations BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: Dn32g43x_des.h
+* Function: Declaring DES algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+
+#ifndef _N32G43X_DES_H_
+#define _N32G43X_DES_H_
+
+#include <stdint.h>
+
+#define DES_ECB (0x11111111)
+#define DES_CBC (0x22222222)
+
+
+#define DES_ENC  (0x33333333)
+#define DES_DEC  (0x44444444)
+
+#define DES_KEY  (0x55555555)
+#define TDES_2KEY  (0x66666666)
+#define TDES_3KEY  (0x77777777)
+
+enum DES
+{
+  DES_Crypto_OK = 0x0,      //DES/TDES opreation success
+    DES_Init_OK   = 0x0,    //DES/TDES Init opreation success
+    DES_Crypto_ModeError = 0x5a5a5a5a,      //Working mode error(Neither ECB nor CBC)
+    DES_Crypto_EnOrDeError,     //En&De error(Neither encryption nor decryption)
+    DES_Crypto_ParaNull,        // the part of input(output/iv) Null
+    DES_Crypto_LengthError,     //the length of input message must be 2 times and cannot be zero
+    DES_Crypto_KeyError,  //keyMode error(Neither DES_KEY nor TDES_2KEY nor TDES_3KEY)
+    DES_Crypto_UnInitError,   //DES/TDES uninitialized
+};
+
+typedef struct
+{
+        uint32_t *in;   // the  part of input to be encrypted or decrypted
+        uint32_t *iv;   // the  part of initial vector
+        uint32_t *out;  // the  part of out
+        uint32_t *key;  // the  part of key
+        uint32_t inWordLen;  // the length(by word) of plaintext or cipher
+        uint32_t En_De; // 0x33333333- encrypt, 0x44444444 - decrypt
+        uint32_t Mode;  // 0x11111111 - ECB, 0x22222222 - CBC
+        uint32_t keyMode; //TDES key mode: 0x55555555-key,0x66666666-2key, 0x77777777-3key
+}DES_PARM;
+
+ /**
+ * @brief DES_Init
+ * @return DES_Init_OK, DES/TDES Init success; othets: DES/TDES Init fail
+ * @note
+ */
+uint32_t DES_Init(DES_PARM *parm);
+
+/**
+ * @brief DES crypto
+ * @param[in] parm pointer to DES/TDES context and the detail please refer to struct DES_PARM in DES.h
+ * @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation)
+ * @note  1.Please refer to the demo in user guidance before using this function
+ *        2.Input and output can be the same buffer
+ *        3. IV can be NULL when ECB mode
+ *        4. The word lengrh of message must be as times as 2.
+ *        5. If the input is in byte, make sure align by word.
+ */
+uint32_t DES_Crypto(DES_PARM *parm);
+
+/**
+ * @brief DES close
+ * @return none
+ * @note  if you want to close DES algorithm, this function can be recalled.
+ */
+void DES_Close(void);
+
+/**
+ * @brief Get DES/TDES lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get DES/TDES lib information
+ */
+void DES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+#endif

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_hash.h

@@ -0,0 +1,213 @@
+/*****************************************************************************
+*         Nationz Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, Nationz Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* Nationz's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: HASH.h
+* Function: Declaring HASH algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+#ifndef _N32G43X_HASH_H_
+#define _N32G43X_HASH_H_
+
+#include <stdint.h>
+
+#define  ALG_SHA1           (uint16_t)(0x0004)
+#define  ALG_SHA224         (uint16_t)(0x000A)
+#define  ALG_SHA256         (uint16_t)(0x000B)
+//#define  ALG_MD5            (u16)(0x000C)
+#define  ALG_SM3        (uint16_t)(0x0012)
+
+enum
+{
+    HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
+    HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV
+    HASH_Init_OK = 0,//hash init success
+    HASH_Start_OK = 0,//hash update success
+    HASH_Update_OK = 0,//hash update success
+    HASH_Complete_OK = 0,//hash complete success
+    HASH_Close_OK = 0,//hash close success
+    HASH_ByteLenPlus_OK = 0,//byte length plus success
+    HASH_PadMsg_OK = 0,//message padding success
+    HASH_ProcMsgBuf_OK = 0, //message processing success
+    SHA1_Hash_OK = 0,//sha1 operation success
+    SM3_Hash_OK = 0,//sm3 operation success
+    SHA224_Hash_OK = 0,//sha224 operation success
+    SHA256_Hash_OK = 0,//sha256 operation success
+    //MD5_Hash_OK = 0,//MD5 operation success
+
+    HASH_Init_ERROR = 0x01044400,//hash init error
+    HASH_Start_ERROR, //hash start error
+    HASH_Update_ERROR, //hash update error
+    HASH_ByteLenPlus_ERROR,//hash byte plus error
+};
+
+struct _HASH_CTX_;
+
+typedef struct
+{
+    const uint16_t HashAlgID;//choice hash algorithm
+    const uint32_t * const K, KLen;//K and word length of K
+    const uint32_t * const IV, IVLen;//IV and word length of IV
+    const uint32_t HASH_SACCR, HASH_HASHCTRL;//relate registers
+    const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block
+    const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest
+    const uint32_t Cycle; //interation times
+    uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer
+    uint32_t (* const PadMsg)(struct _HASH_CTX_ *); //function pointer
+}HASH_ALG;
+
+
+typedef struct _HASH_CTX_
+{
+    const HASH_ALG  *hashAlg;//pointer to HASH_ALG
+    uint32_t        sequence;   // TRUE if the IV should be saved
+    uint32_t    IV[16];
+    uint32_t        msgByteLen[4];
+  uint8_t       msgBuf[128+4];
+  uint32_t      msgIdx;
+}HASH_CTX;
+
+extern const HASH_ALG HASH_ALG_SHA1[1];
+extern const HASH_ALG HASH_ALG_SHA224[1];
+extern const HASH_ALG HASH_ALG_SHA256[1];
+//extern const HASH_ALG HASH_ALG_MD5[1];
+extern const HASH_ALG HASH_ALG_SM3[1];
+
+/**
+ * @brief  Hash init
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @return HASH_Init_OK,  Hash init success; othets:  Hash init fail
+ * @note   1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t HASH_Init(HASH_CTX *ctx);
+
+/**
+ * @brief  Hash start
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @return HASH_Start_OK,  Hash start success; othets:  Hash start fail
+ * @note   1.Please refer to the demo in user guidance before using this function
+ *         2.HASH_Init() should be recalled before use this function
+ */
+uint32_t HASH_Start(HASH_CTX *ctx);
+
+/**
+ * @brief  Hash update
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @param[in] in pointer to message
+ * @param[out] out pointer tohash result,digest
+ * @return HASH_Update_OK,  Hash update success; othets:  Hash update fail
+ * @note   1.Please refer to the demo in user guidance before using this function
+ *         2.HASH_Init() and HASH_Start() should be recalled before use this function
+ */
+uint32_t HASH_Update(HASH_CTX *ctx,  uint8_t *in,  uint32_t byteLen);
+
+/**
+ * @brief  Hash complete
+ * @param[in] ctx pointer to HASH_CTX struct
+ * @param[out] out pointer tohash result,digest
+ * @return HASH_Complete_OK,  Hash complete success; othets:  Hash complete fail
+ * @note   1.Please refer to the demo in user guidance before using this function
+ *         2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function
+ */
+uint32_t HASH_Complete(HASH_CTX *ctx,  uint8_t *out);
+
+/**
+ * @brief  Hash close
+ * @return HASH_Close_OK, Hash close success; othets: Hash close fail
+ * @note   1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t HASH_Close(void);
+
+/**
+ * @brief  SM3 Hash for 256bits digest
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SM3_Hash_OK, SM3 hash success; othets: SM3 hash fail
+ * @note   1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SM3_Hash(uint8_t *in,uint32_t byteLen, uint8_t* out);
+
+
+/**
+ * @brief  SHA1 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail
+ * @note   1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA1_Hash(uint8_t*in, uint32_t byteLen, uint8_t*out);
+
+/**
+ * @brief  SHA224 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail
+ * @note   1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+
+/**
+ * @brief  SHA256 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[out] out pointer tohash result,digest
+ * @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail
+ * @note   1.Please refer to the demo in user guidance before using this function
+ */
+uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
+
+/**
+ * @brief  MD5 Hash
+ * @param[in] in pointer to message
+ * @param[in] byte length of in
+ * @param[in] out pointer tohash result,digest
+ * @return MD5_Hash_OK, MD5 hash success; othets: MD5 hash fail
+ * @note   1.Please refer to the demo in user guidance before using this function
+ */
+//u32 MD5_Hash(u8* in,u32 byteLen, u8* out);
+
+/**
+ * @brief Get HASH lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get RSA lib information
+ */
+void HASH_Version(uint8_t*type, uint8_t*customer, uint8_t date[3], uint8_t *version);
+
+
+#endif

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_rng.h

@@ -0,0 +1,83 @@
+/*****************************************************************************
+*         NationS Microcontroller Software Support
+* ----------------------------------------------------------------------------
+* Copyright (c) 2020, NationS Corporation
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* - Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the disclaimer below.
+*
+* NationS's name may not be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ****************************************************************************/
+/*****************************************************************************
+* File Name: n32g43x_rng.h
+* Function: Declaring RNG algorithm library API
+* version: V1.2.0
+* Author: zhang.zhenshan
+* date: 2020-4-8
+* ****************************************************************************/
+
+#ifndef  _N32G43X_RNG_H_
+#define  _N32G43X_RNG_H_
+
+#include <stdint.h>
+
+enum{
+    RNG_OK = 0x5a5a5a5a,
+    LENError = 0x311ECF50,   //RNG generation of key length error
+    ADDRNULL = 0x7A9DB86C,   // This address is empty
+};
+
+
+//u32 RNG_init(void);
+/**
+ * @brief Get pseudo random number
+ * @param[out] rand pointer to random number
+ * @param[in] the wordlen of random number
+ * @param[in] the seed, can be NULL
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
+ */
+uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen,uint32_t seed[2]);
+
+
+/**
+ * @brief Get true random number
+ * @param[out] rand pointer to random number
+ * @param[in] the wordlen of random number
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
+ */
+uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen);
+
+/**
+ * @brief Get RNG lib version
+ * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
+ * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
+ * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
+ * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
+ * @return none
+ * @1.You can recall this function to get RSA lib information
+ */
+void RNG_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
+
+#endif
+
+

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/misc.h

@@ -0,0 +1,228 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file misc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __MISC_H__
+#define __MISC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @addtogroup MISC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief  NVIC Init Structure definition
+ */
+
+typedef struct
+{
+    uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+                                  This parameter can be a value of @ref IRQn_Type
+                                  (For the complete N32G43x Devices IRQ Channels list, please
+                                   refer to n32g43x.h file) */
+
+    uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+                                                specified in NVIC_IRQChannel. This parameter can be a value
+                                                between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+    uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+                                             in NVIC_IRQChannel. This parameter can be a value
+                                             between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+    FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                             will be enabled or disabled.
+                                             This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup NVIC_Priority_Table
+ * @{
+ */
+
+/**
+@code
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  ============================================================================================================================
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+  ============================================================================================================================
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption
+priority |                                   |                             |   4 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption
+priority |                                   |                             |   3 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption
+priority |                                   |                             |   2 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption
+priority |                                   |                             |   1 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption
+priority |                                   |                             |   0 bits for subpriority
+  ============================================================================================================================
+@endcode
+*/
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM         ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH       ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @addtogroup System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND   ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP   ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP)      (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @addtogroup Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0                                                                                           \
+    ((uint32_t)0x700) /*!< 0 bits for pre-emption priority                                                             \
+                           4 bits for subpriority */
+#define NVIC_PriorityGroup_1                                                                                           \
+    ((uint32_t)0x600) /*!< 1 bits for pre-emption priority                                                             \
+                           3 bits for subpriority */
+#define NVIC_PriorityGroup_2                                                                                           \
+    ((uint32_t)0x500) /*!< 2 bits for pre-emption priority                                                             \
+                           2 bits for subpriority */
+#define NVIC_PriorityGroup_3                                                                                           \
+    ((uint32_t)0x400) /*!< 3 bits for pre-emption priority                                                             \
+                           1 bits for subpriority */
+#define NVIC_PriorityGroup_4                                                                                           \
+    ((uint32_t)0x300) /*!< 4 bits for pre-emption priority                                                             \
+                           0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP)                                                                                  \
+    (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2)       \
+     || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup SysTick_clock_source
+ * @{
+ */
+
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK      ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE)                                                                                  \
+    (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Exported_Functions
+ * @{
+ */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_adc.h

@@ -0,0 +1,545 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_adc.h
+ * @author Nations
+ * @version V1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43x_ADC_H__
+#define __N32G43x_ADC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+#include <stdbool.h>
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+#define VREF1P2_CTRL  (*(uint32_t*)(0x40001800+0x24))
+#define _EnVref1p2()  do{VREF1P2_CTRL|=(0x1<<13);}while (0);
+#define _DisVref1p2() do{VREF1P2_CTRL&=~(0x1<<13);}while (0);
+
+#define VREF2P0_CTRL  (*(uint32_t*)(0x40001800+0x24))
+#define _EnVref2p0()  do{VREF2P0_CTRL|=(0x1<<20);}while (0);
+#define _DisVref2p0() do{VREF2P0_CTRL&=~(0x1<<20);}while (0);
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief  ADC Init structure definition
+ */
+typedef struct
+{
+
+    FunctionalState MultiChEn; /*!< Specifies whether the conversion is performed in
+                                           Scan (multichannels) or Single (one channel) mode.
+                                           This parameter can be set to ENABLE or DISABLE */
+
+    FunctionalState ContinueConvEn; /*!< Specifies whether the conversion is performed in
+                                                 Continuous or Single mode.
+                                                 This parameter can be set to ENABLE or DISABLE. */
+
+    uint32_t ExtTrigSelect; /*!< Defines the external trigger used to start the analog
+                                        to digital conversion of regular channels. This parameter
+                                        can be a value of @ref
+                               ADC_external_trigger_sources_for_regular_channels_conversion */
+
+    uint32_t DatAlign; /*!< Specifies whether the ADC data alignment is left or right.
+                                 This parameter can be a value of @ref ADC_data_align */
+
+    uint8_t ChsNumber; /*!< Specifies the number of ADC channels that will be converted
+                                   using the sequencer for regular channel group.
+                                   This parameter must range from 1 to 16. */
+} ADC_InitType;
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Constants
+ * @{
+ */
+
+#define IsAdcModule(PERIPH) (((PERIPH) == ADC))
+
+#define IsAdcDmaModule(PERIPH) (((PERIPH) == ADC))
+
+
+
+/** @addtogroup ADC_external_trigger_sources_for_regular_channels_conversion
+ * @{
+ */
+
+#define ADC_EXT_TRIGCONV_T1_CC1              ((uint32_t)0x00000000)
+#define ADC_EXT_TRIGCONV_T1_CC2              ((uint32_t)0x00020000)
+#define ADC_EXT_TRIGCONV_T1_CC3              ((uint32_t)0x00040000)
+#define ADC_EXT_TRIGCONV_T2_CC2              ((uint32_t)0x00060000)
+#define ADC_EXT_TRIGCONV_T3_TRGO             ((uint32_t)0x00080000)
+#define ADC_EXT_TRIGCONV_T4_CC4              ((uint32_t)0x000A0000)
+#define ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO ((uint32_t)0x000C0000)
+#define ADC_EXT_TRIGCONV_NONE                ((uint32_t)0x000E0000)
+
+
+#define IsAdcExtTrig(REGTRIG)                                                                                          \
+    (((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC2)                                  \
+     || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC3) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC2)                               \
+     || ((REGTRIG) == ADC_EXT_TRIGCONV_T3_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_T4_CC4)                              \
+     || ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_data_align
+ * @{
+ */
+
+#define ADC_DAT_ALIGN_R      ((uint32_t)0x00000000)
+#define ADC_DAT_ALIGN_L      ((uint32_t)0x00000800)
+#define IsAdcDatAlign(ALIGN) (((ALIGN) == ADC_DAT_ALIGN_R) || ((ALIGN) == ADC_DAT_ALIGN_L))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_channels
+ * @{
+ */
+
+#define ADC_CH_0  ((uint8_t)0x00)
+#define ADC_CH_1  ((uint8_t)0x01)
+#define ADC_CH_2  ((uint8_t)0x02)
+#define ADC_CH_3  ((uint8_t)0x03)
+#define ADC_CH_4  ((uint8_t)0x04)
+#define ADC_CH_5  ((uint8_t)0x05)
+#define ADC_CH_6  ((uint8_t)0x06)
+#define ADC_CH_7  ((uint8_t)0x07)
+#define ADC_CH_8  ((uint8_t)0x08)
+#define ADC_CH_9  ((uint8_t)0x09)
+#define ADC_CH_10 ((uint8_t)0x0A)
+#define ADC_CH_11 ((uint8_t)0x0B)
+#define ADC_CH_12 ((uint8_t)0x0C)
+#define ADC_CH_13 ((uint8_t)0x0D)
+#define ADC_CH_14 ((uint8_t)0x0E)
+#define ADC_CH_15 ((uint8_t)0x0F)
+#define ADC_CH_16 ((uint8_t)0x10)
+#define ADC_CH_17 ((uint8_t)0x11)
+#define ADC_CH_18 ((uint8_t)0x12)
+
+#define ADC_CH_VREFINT        ((uint8_t)ADC_CH_0)
+#define ADC_CH_TEMP_SENSOR    ((uint8_t)ADC_CH_17)
+#define ADC_CH_VREFBUF        ((uint8_t)ADC_CH_18)
+
+#define IsAdcChannel(CHANNEL)                                                                                          \
+    (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3)          \
+     || ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7)       \
+     || ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11)     \
+     || ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15)   \
+     || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_sampling_time
+ * @{
+ */
+
+#define ADC_SAMP_TIME_1CYCLES5   ((uint8_t)0x00)
+#define ADC_SAMP_TIME_7CYCLES5   ((uint8_t)0x01)
+#define ADC_SAMP_TIME_13CYCLES5  ((uint8_t)0x02)
+#define ADC_SAMP_TIME_28CYCLES5  ((uint8_t)0x03)
+#define ADC_SAMP_TIME_41CYCLES5  ((uint8_t)0x04)
+#define ADC_SAMP_TIME_55CYCLES5  ((uint8_t)0x05)
+#define ADC_SAMP_TIME_71CYCLES5  ((uint8_t)0x06)
+#define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07)
+#define IsAdcSampleTime(TIME)                                                                                          \
+    (((TIME) == ADC_SAMP_TIME_1CYCLES5) || ((TIME) == ADC_SAMP_TIME_7CYCLES5) || ((TIME) == ADC_SAMP_TIME_13CYCLES5)   \
+     || ((TIME) == ADC_SAMP_TIME_28CYCLES5) || ((TIME) == ADC_SAMP_TIME_41CYCLES5)                                     \
+     || ((TIME) == ADC_SAMP_TIME_55CYCLES5) || ((TIME) == ADC_SAMP_TIME_71CYCLES5)                                     \
+     || ((TIME) == ADC_SAMP_TIME_239CYCLES5))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_external_trigger_sources_for_injected_channels_conversion
+ * @{
+ */
+
+#define ADC_EXT_TRIG_INJ_CONV_T1_TRGO            ((uint32_t)0x00000000)
+#define ADC_EXT_TRIG_INJ_CONV_T1_CC4             ((uint32_t)0x00001000)
+#define ADC_EXT_TRIG_INJ_CONV_T2_TRGO            ((uint32_t)0x00002000)
+#define ADC_EXT_TRIG_INJ_CONV_T2_CC1             ((uint32_t)0x00003000)
+#define ADC_EXT_TRIG_INJ_CONV_T3_CC4             ((uint32_t)0x00004000)
+#define ADC_EXT_TRIG_INJ_CONV_T4_TRGO            ((uint32_t)0x00005000)
+#define ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 ((uint32_t)0x00006000)
+#define ADC_EXT_TRIG_INJ_CONV_NONE               ((uint32_t)0x00007000)
+
+
+#define IsAdcExtInjTrig(INJTRIG)                                                                                       \
+    (((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_CC4)                       \
+     || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_CC1)                    \
+     || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T3_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_TRGO)                    \
+     || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_channel_selection
+ * @{
+ */
+
+#define ADC_INJ_CH_1 ((uint8_t)0x14)
+#define ADC_INJ_CH_2 ((uint8_t)0x18)
+#define ADC_INJ_CH_3 ((uint8_t)0x1C)
+#define ADC_INJ_CH_4 ((uint8_t)0x20)
+#define IsAdcInjCh(CHANNEL)                                                                                            \
+    (((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3)                         \
+     || ((CHANNEL) == ADC_INJ_CH_4))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_analog_watchdog_selection
+ * @{
+ */
+
+#define ADC_ANALOG_WTDG_SINGLEREG_ENABLE          ((uint32_t)0x00800200)
+#define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE        ((uint32_t)0x00400200)
+#define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE ((uint32_t)0x00C00200)
+#define ADC_ANALOG_WTDG_ALLREG_ENABLE             ((uint32_t)0x00800000)
+#define ADC_ANALOG_WTDG_ALLINJEC_ENABLE           ((uint32_t)0x00400000)
+#define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE    ((uint32_t)0x00C00000)
+#define ADC_ANALOG_WTDG_NONE                      ((uint32_t)0x00000000)
+
+#define IsAdcAnalogWatchdog(WATCHDOG)                                                                                  \
+    (((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE)            \
+     || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ENABLE)     \
+     || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLINJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE)      \
+     || ((WATCHDOG) == ADC_ANALOG_WTDG_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_interrupts_definition
+ * @{
+ */
+
+#define ADC_INT_ENDC  ((uint16_t)0x0220)
+#define ADC_INT_AWD   ((uint16_t)0x0140)
+#define ADC_INT_JENDC ((uint16_t)0x0480)
+
+#define IsAdcInt(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IsAdcGetInt(IT) (((IT) == ADC_INT_ENDC) || ((IT) == ADC_INT_AWD) || ((IT) == ADC_INT_JENDC))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_flags_definition
+ * @{
+ */
+
+#define ADC_FLAG_AWDG      ((uint8_t)0x01)
+#define ADC_FLAG_ENDC      ((uint8_t)0x02)
+#define ADC_FLAG_JENDC     ((uint8_t)0x04)
+#define ADC_FLAG_JSTR      ((uint8_t)0x08)
+#define ADC_FLAG_STR       ((uint8_t)0x10)
+#define ADC_FLAG_EOC_ANY   ((uint8_t)0x20)
+#define ADC_FLAG_JEOC_ANY  ((uint8_t)0x40)
+#define IsAdcClrFlag(FLAG) ((((FLAG) & (uint8_t)0x80) == 0x00) && ((FLAG) != 0x00))
+#define IsAdcGetFlag(FLAG)                                                                                             \
+    (((FLAG) == ADC_FLAG_AWDG) || ((FLAG) == ADC_FLAG_ENDC) || ((FLAG) == ADC_FLAG_JENDC) || ((FLAG) == ADC_FLAG_JSTR) \
+     || ((FLAG) == ADC_FLAG_STR) || ((FLAG) == ADC_FLAG_EOC_ANY) || ((FLAG) == ADC_FLAG_JEOC_ANY))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_thresholds
+ * @{
+ */
+#define IsAdcValid(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_offset
+ * @{
+ */
+
+#define IsAdcOffsetValid(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_length
+ * @{
+ */
+
+#define IsAdcInjLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_injected_rank
+ * @{
+ */
+
+#define IsAdcInjRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_length
+ * @{
+ */
+
+#define IsAdcSeqLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_rank
+ * @{
+ */
+
+#define IsAdcReqRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+
+#define IsAdcSeqDiscNumberValid(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+ * @}
+ */
+
+/************************** fllowing bit seg in ex register  **********************/
+/**@addtogroup ADC_channels_ex_style
+ * @{
+ */
+
+
+#define ADC_CH_0       ((uint8_t)0x00)
+#define ADC_CH_1_PA0   ((uint8_t)0x01)
+#define ADC_CH_2_PA1   ((uint8_t)0x02)
+#define ADC_CH_3_PA2   ((uint8_t)0x03)
+#define ADC_CH_4_PA3   ((uint8_t)0x04)
+#define ADC_CH_5_PA4   ((uint8_t)0x05)
+#define ADC_CH_6_PA5   ((uint8_t)0x06)
+#define ADC_CH_7_PA6   ((uint8_t)0x07)
+#define ADC_CH_8_PA7   ((uint8_t)0x08)
+#define ADC_CH_9_PB0   ((uint8_t)0x09)
+#define ADC_CH_10_PB1  ((uint8_t)0x0A)
+#define ADC_CH_11_PC0  ((uint8_t)0x0B)
+#define ADC_CH_12_PC1  ((uint8_t)0x0C)
+#define ADC_CH_13_PC2  ((uint8_t)0x0D)
+#define ADC_CH_14_PC3  ((uint8_t)0x0E)
+#define ADC_CH_15_PC4  ((uint8_t)0x0F)
+#define ADC_CH_16_PC5  ((uint8_t)0x10)
+#define ADC_CH_17      ((uint8_t)0x11)
+#define ADC_CH_18      ((uint8_t)0x12)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_dif_sel_ch_definition
+ * @{
+ */
+#define aDC_DIFSEL_CHS_MASK ((uint32_t)0x0007FFFF)
+#define ADC_DIFSEL_CHS_0    ((uint32_t)0x00000001)
+#define ADC_DIFSEL_CHS_1    ((uint32_t)0x00000002)
+#define ADC_DIFSEL_CHS_2    ((uint32_t)0x00000004)
+#define ADC_DIFSEL_CHS_3    ((uint32_t)0x00000008)
+#define ADC_DIFSEL_CHS_4    ((uint32_t)0x00000010)
+#define ADC_DIFSEL_CHS_5    ((uint32_t)0x00000020)
+#define ADC_DIFSEL_CHS_6    ((uint32_t)0x00000040)
+#define ADC_DIFSEL_CHS_7    ((uint32_t)0x00000080)
+#define ADC_DIFSEL_CHS_8    ((uint32_t)0x00000100)
+#define ADC_DIFSEL_CHS_9    ((uint32_t)0x00000200)
+#define ADC_DIFSEL_CHS_10   ((uint32_t)0x00000400)
+#define ADC_DIFSEL_CHS_11   ((uint32_t)0x00000800)
+#define ADC_DIFSEL_CHS_12   ((uint32_t)0x00001000)
+#define ADC_DIFSEL_CHS_13   ((uint32_t)0x00002000)
+#define ADC_DIFSEL_CHS_14   ((uint32_t)0x00004000)
+#define ADC_DIFSEL_CHS_15   ((uint32_t)0x00008000)
+#define ADC_DIFSEL_CHS_16   ((uint32_t)0x00010000)
+#define ADC_DIFSEL_CHS_17   ((uint32_t)0x00020000)
+#define ADC_DIFSEL_CHS_18   ((uint32_t)0x00040000)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_calfact_definition
+ * @{
+ */
+#define ADC_CALFACT_CALFACTD_MSK ((uint32_t)0x3FL << 16)
+#define ADC_CALFACT_CALFACTS_MSK ((uint32_t)0x3FL << 0)
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_ctrl3_definition
+ * @{
+ */
+#define ADC_CTRL3_DPWMOD_MSK    ((uint32_t)0x01L << 10)
+#define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9)
+#define ADC_CTRL3_ENDCAIEN_MSK  ((uint32_t)0x01L << 8)
+#define ADC_CTRL3_BPCAL_MSK     ((uint32_t)0x01L << 7)
+#define ADC_CTRL3_CKMOD_MSK     ((uint32_t)0x01L << 4)
+#define ADC_CTRL3_CALALD_MSK    ((uint32_t)0x01L << 3)
+#define ADC_CTRL3_CALDIF_MSK    ((uint32_t)0x01L << 2)
+#define ADC_CTRL3_RES_MSK       ((uint32_t)0x03L << 0)
+#define ADC_SAMPT3_SAMPSEL_MSK  ((uint32_t)0x01L << 3)
+typedef enum
+{
+    ADC_CTRL3_CKMOD_AHB = 0,
+    ADC_CTRL3_CKMOD_PLL = 1,
+} ADC_CTRL3_CKMOD;
+typedef enum
+{
+    ADC_CTRL3_RES_12BIT  = 3,
+    ADC_CTRL3_RES_10BIT  = 2,
+    ADC_CTRL3_RES_8BIT   = 1,
+    ADC_CTRL3_RES_6BIT   = 0,
+} ADC_CTRL3_RES;
+typedef struct
+{
+    FunctionalState DeepPowerModEn;
+    FunctionalState JendcIntEn;
+    FunctionalState EndcIntEn;
+    ADC_CTRL3_CKMOD ClkMode;
+    FunctionalState CalAtuoLoadEn;
+    bool DifModCal;
+    ADC_CTRL3_RES ResBit;
+    bool Samp303Style;
+} ADC_InitTypeEx;
+/**
+ * @}
+ */
+
+/**@addtogroup ADC_bit_num_definition
+ * @{
+ */
+#define ADC_RST_BIT_12   ((uint32_t)0x03)
+#define ADC_RST_BIT_10   ((uint32_t)0x02)
+#define ADC_RST_BIT_8    ((uint32_t)0x01)
+#define ADC_RESULT_BIT_6 ((uint32_t)0x00)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_flags_ex_definition
+ * @{
+ */
+#define ADC_FLAG_RDY    ((uint8_t)0x20)
+#define ADC_FLAG_PD_RDY ((uint8_t)0x40)
+#define IS_ADC_GET_READY(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_PD_RDY))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+void ADC_DeInit(ADC_Module* ADCx);
+void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct);
+void ADC_InitStruct(ADC_InitType* ADC_InitStruct);
+void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd);
+void ADC_StartCalibration(ADC_Module* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx);
+void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx);
+void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number);
+void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd);
+uint16_t ADC_GetDat(ADC_Module* ADCx);
+void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx);
+void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length);
+void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel);
+void ADC_EnableTempSensorVrefint(FunctionalState Cmd);
+FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG);
+INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT);
+void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT);
+
+void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx);
+FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW);
+void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en);
+void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum);
+
+void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_ADC_H__ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_can.h

@@ -0,0 +1,670 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_can.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_CAN_H__
+#define __N32G43X_CAN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Types
+ * @{
+ */
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN))
+
+/**
+ * @brief  CAN init structure definition
+ */
+
+typedef struct
+{
+    uint16_t BaudRatePrescaler; /*!< Specifies the length of a time quantum.
+                                 It ranges from 1 to 1024. */
+
+    uint8_t OperatingMode; /*!< Specifies the CAN operating mode.
+                           This parameter can be a value of
+                          @ref CAN_operating_mode */
+
+    uint8_t RSJW; /*!< Specifies the maximum number of time quanta
+                          the CAN hardware is allowed to lengthen or
+                          shorten a bit to perform resynchronization.
+                          This parameter can be a value of
+                          @ref CAN_synchronisation_jump_width */
+
+    uint8_t TBS1; /*!< Specifies the number of time quanta in Bit
+                          Segment 1. This parameter can be a value of
+                          @ref CAN_time_quantum_in_bit_segment_1 */
+
+    uint8_t TBS2; /*!< Specifies the number of time quanta in Bit
+                          Segment 2.
+                          This parameter can be a value of
+                          @ref CAN_time_quantum_in_bit_segment_2 */
+
+    FunctionalState TTCM; /*!< Enable or disable the time triggered
+                                   communication mode. This parameter can be set
+                                   either to ENABLE or DISABLE. */
+
+    FunctionalState ABOM; /*!< Enable or disable the automatic bus-off
+                                   management. This parameter can be set either
+                                   to ENABLE or DISABLE. */
+
+    FunctionalState AWKUM; /*!< Enable or disable the automatic wake-up mode.
+                                   This parameter can be set either to ENABLE or
+                                   DISABLE. */
+
+    FunctionalState NART; /*!< Enable or disable the no-automatic
+                                   retransmission mode. This parameter can be
+                                   set either to ENABLE or DISABLE. */
+
+    FunctionalState RFLM; /*!< Enable or disable the Receive DATFIFO Locked mode.
+                                   This parameter can be set either to ENABLE
+                                   or DISABLE. */
+
+    FunctionalState TXFP; /*!< Enable or disable the transmit DATFIFO priority.
+                                   This parameter can be set either to ENABLE
+                                   or DISABLE. */
+} CAN_InitType;
+
+/**
+ * @brief  CAN filter init structure definition
+ */
+
+typedef struct
+{
+    uint16_t Filter_HighId; /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                        configuration, first one for a 16-bit configuration).
+                                        This parameter can be a value between 0x0000 and 0xFFFF */
+
+    uint16_t Filter_LowId; /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                       configuration, second one for a 16-bit configuration).
+                                       This parameter can be a value between 0x0000 and 0xFFFF */
+
+    uint16_t FilterMask_HighId; /*!< Specifies the filter mask number or identification number,
+                                            according to the mode (MSBs for a 32-bit configuration,
+                                            first one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+    uint16_t FilterMask_LowId; /*!< Specifies the filter mask number or identification number,
+                                           according to the mode (LSBs for a 32-bit configuration,
+                                           second one for a 16-bit configuration).
+                                           This parameter can be a value between 0x0000 and 0xFFFF */
+
+    uint16_t Filter_FIFOAssignment; /*!< Specifies the DATFIFO (0 or 1) which will be assigned to the filter.
+                                                This parameter can be a value of @ref CAN_filter_FIFO */
+
+    uint8_t Filter_Num; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+    uint8_t Filter_Mode; /*!< Specifies the filter mode to be initialized.
+                                     This parameter can be a value of @ref CAN_filter_mode */
+
+    uint8_t Filter_Scale; /*!< Specifies the filter scale.
+                                      This parameter can be a value of @ref CAN_filter_scale */
+
+    FunctionalState Filter_Act; /*!< Enable or disable the filter.
+                                                This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitType;
+
+/**
+ * @brief  CAN Tx message structure definition
+ */
+
+typedef struct
+{
+    uint32_t StdId; /*!< Specifies the standard identifier.
+                         This parameter can be a value between 0 to 0x7FF. */
+
+    uint32_t ExtId; /*!< Specifies the extended identifier.
+                         This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+    uint8_t IDE; /*!< Specifies the type of identifier for the message that
+                      will be transmitted. This parameter can be a value
+                      of @ref CAN_identifier_type */
+
+    uint8_t RTR; /*!< Specifies the type of frame for the message that will
+                      be transmitted. This parameter can be a value of
+                      @ref CAN_remote_transmission_request */
+
+    uint8_t DLC; /*!< Specifies the length of the frame that will be
+                      transmitted. This parameter can be a value between
+                      0 to 8 */
+
+    uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
+                          to 0xFF. */
+} CanTxMessage;
+
+/**
+ * @brief  CAN Rx message structure definition
+ */
+
+typedef struct
+{
+    uint32_t StdId; /*!< Specifies the standard identifier.
+                         This parameter can be a value between 0 to 0x7FF. */
+
+    uint32_t ExtId; /*!< Specifies the extended identifier.
+                         This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+    uint8_t IDE; /*!< Specifies the type of identifier for the message that
+                      will be received. This parameter can be a value of
+                      @ref CAN_identifier_type */
+
+    uint8_t RTR; /*!< Specifies the type of frame for the received message.
+                      This parameter can be a value of
+                      @ref CAN_remote_transmission_request */
+
+    uint8_t DLC; /*!< Specifies the length of the frame that will be received.
+                      This parameter can be a value between 0 to 8 */
+
+    uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
+                          0xFF. */
+
+    uint8_t FMI; /*!< Specifies the index of the filter the message stored in
+                      the mailbox passes through. This parameter can be a
+                      value between 0 to 0xFF */
+} CanRxMessage;
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_InitSTS_Failed  ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitSTS_Success ((uint8_t)0x01) /*!< CAN initialization OK */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OperatingMode
+ * @{
+ */
+
+#define CAN_Normal_Mode          ((uint8_t)0x00) /*!< normal mode */
+#define CAN_LoopBack_Mode        ((uint8_t)0x01) /*!< loopback mode */
+#define CAN_Silent_Mode          ((uint8_t)0x02) /*!< silent mode */
+#define CAN_Silent_LoopBack_Mode ((uint8_t)0x03) /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE)                                                                                              \
+    (((MODE) == CAN_Normal_Mode) || ((MODE) == CAN_LoopBack_Mode) || ((MODE) == CAN_Silent_Mode)                       \
+     || ((MODE) == CAN_Silent_LoopBack_Mode))
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_operating_mode
+ * @{
+ */
+#define CAN_Operating_InitMode   ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_Operating_NormalMode ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_Operating_SleepMode  ((uint8_t)0x02) /*!< sleep mode */
+
+#define IS_CAN_OPERATING_MODE(MODE)                                                                                    \
+    (((MODE) == CAN_Operating_InitMode) || ((MODE) == CAN_Operating_NormalMode) || ((MODE) == CAN_Operating_SleepMode))
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup CAN_Mode_Status
+ * @{
+ */
+
+#define CAN_ModeSTS_Failed  ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
+#define CAN_ModeSTS_Success ((uint8_t)!CAN_ModeSTS_Failed) /*!< CAN entering the specific mode Succeed */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_synchronisation_jump_width
+ * @{
+ */
+
+#define CAN_RSJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_RSJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_RSJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_RSJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+
+#define IS_CAN_RSJW(SJW)                                                                                               \
+    (((SJW) == CAN_RSJW_1tq) || ((SJW) == CAN_RSJW_2tq) || ((SJW) == CAN_RSJW_3tq) || ((SJW) == CAN_RSJW_4tq))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+
+#define CAN_TBS1_1tq  ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_TBS1_2tq  ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_TBS1_3tq  ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_TBS1_4tq  ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_TBS1_5tq  ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_TBS1_6tq  ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_TBS1_7tq  ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_TBS1_8tq  ((uint8_t)0x07) /*!< 8 time quantum */
+#define CAN_TBS1_9tq  ((uint8_t)0x08) /*!< 9 time quantum */
+#define CAN_TBS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
+#define CAN_TBS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
+#define CAN_TBS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
+#define CAN_TBS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
+#define CAN_TBS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
+#define CAN_TBS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
+#define CAN_TBS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
+
+#define IS_CAN_TBS1(BS1) ((BS1) <= CAN_TBS1_16tq)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+
+#define CAN_TBS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_TBS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_TBS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_TBS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_TBS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_TBS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_TBS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_TBS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+
+#define IS_CAN_TBS2(BS2) ((BS2) <= CAN_TBS2_8tq)
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_clock_prescaler
+ * @{
+ */
+
+#define IS_CAN_BAUDRATEPRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_number
+ * @{
+ */
+#define IS_CAN_FILTER_NUM(NUMBER) ((NUMBER) <= 13)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_mode
+ * @{
+ */
+
+#define CAN_Filter_IdMaskMode ((uint8_t)0x00) /*!< identifier/mask mode */
+#define CAN_Filter_IdListMode ((uint8_t)0x01) /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_Filter_IdMaskMode) || ((MODE) == CAN_Filter_IdListMode))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_scale
+ * @{
+ */
+
+#define CAN_Filter_16bitScale ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_Filter_32bitScale ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_Filter_16bitScale) || ((SCALE) == CAN_Filter_32bitScale))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_filter_FIFO
+ * @{
+ */
+
+#define CAN_Filter_FIFO0            ((uint8_t)0x00) /*!< Filter DATFIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1            ((uint8_t)0x01) /*!< Filter DATFIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(DATFIFO) (((DATFIFO) == CAN_FilterFIFO0) || ((DATFIFO) == CAN_FilterFIFO1))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Tx
+ * @{
+ */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID)                     ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)                     ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)                         ((DLC) <= ((uint8_t)0x08))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_identifier_type
+ * @{
+ */
+
+#define CAN_Standard_Id   ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_Extended_Id   ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_ID(IDTYPE) (((IDTYPE) == CAN_Standard_Id) || ((IDTYPE) == CAN_Extended_Id))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_remote_transmission_request
+ * @{
+ */
+
+#define CAN_RTRQ_Data    ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTRQ_Remote  ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTRQ(RTR) (((RTR) == CAN_RTRQ_Data) || ((RTR) == CAN_RTRQ_Remote))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_transmit_constants
+ * @{
+ */
+
+#define CAN_TxSTS_Failed    ((uint8_t)0x00) /*!< CAN transmission failed */
+#define CAN_TxSTS_Ok        ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxSTS_Pending   ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxSTS_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN DATFIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN DATFIFO 1 used to receive */
+
+#define IS_CAN_FIFO(DATFIFO) (((DATFIFO) == CAN_FIFO0) || ((DATFIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_SLEEP_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_SLEEP_Ok     ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_wake_up_constants
+ * @{
+ */
+
+#define CAN_WKU_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WKU_Ok     ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup   CAN_Error_Code_constants
+ * @{
+ */
+
+#define CAN_ERRCode_NoErr           ((uint8_t)0x00) /*!< No Error */
+#define CAN_ERRCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */
+#define CAN_ERRCode_FormErr         ((uint8_t)0x20) /*!< Form Error */
+#define CAN_ERRCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */
+#define CAN_ERRCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
+#define CAN_ERRCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */
+#define CAN_ERRCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */
+#define CAN_ERRCode_SWSetErr        ((uint8_t)0x70) /*!< Software Set Error */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagSTS()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagSTS() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCPM0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCPM1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCPM2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FFMP0  ((uint32_t)0x12000003) /*!< DATFIFO 0 Message Pending Flag */
+#define CAN_FLAG_FFULL0 ((uint32_t)0x32000008) /*!< DATFIFO 0 Full Flag            */
+#define CAN_FLAG_FFOVR0 ((uint32_t)0x32000010) /*!< DATFIFO 0 Overrun Flag         */
+#define CAN_FLAG_FFMP1  ((uint32_t)0x14000003) /*!< DATFIFO 1 Message Pending Flag */
+#define CAN_FLAG_FFULL1 ((uint32_t)0x34000008) /*!< DATFIFO 1 Full Flag            */
+#define CAN_FLAG_FFOVR1 ((uint32_t)0x34000010) /*!< DATFIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU  ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWGFL ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
+#define CAN_FLAG_EPVFL ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
+#define CAN_FLAG_BOFFL ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
+#define CAN_FLAG_LEC   ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG)                                                                                          \
+    (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOFFL) || ((FLAG) == CAN_FLAG_EPVFL)                              \
+     || ((FLAG) == CAN_FLAG_EWGFL) || ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FFOVR0)                          \
+     || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFMP0) || ((FLAG) == CAN_FLAG_FFOVR1)                       \
+     || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFMP1) || ((FLAG) == CAN_FLAG_RQCPM2)                       \
+     || ((FLAG) == CAN_FLAG_RQCPM1) || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_SLAK))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)                                                                                        \
+    (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCPM2) || ((FLAG) == CAN_FLAG_RQCPM1)                            \
+     || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFOVR0)                      \
+     || ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFOVR1) || ((FLAG) == CAN_FLAG_WKU)                         \
+     || ((FLAG) == CAN_FLAG_SLAK))
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_interrupts
+ * @{
+ */
+
+#define CAN_INT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_INT_FMP0 ((uint32_t)0x00000002) /*!< DATFIFO 0 message pending Interrupt*/
+#define CAN_INT_FF0  ((uint32_t)0x00000004) /*!< DATFIFO 0 full Interrupt*/
+#define CAN_INT_FOV0 ((uint32_t)0x00000008) /*!< DATFIFO 0 overrun Interrupt*/
+#define CAN_INT_FMP1 ((uint32_t)0x00000010) /*!< DATFIFO 1 message pending Interrupt*/
+#define CAN_INT_FF1  ((uint32_t)0x00000020) /*!< DATFIFO 1 full Interrupt*/
+#define CAN_INT_FOV1 ((uint32_t)0x00000040) /*!< DATFIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_INT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_INT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_INT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_INT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_INT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_INT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_INT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_INT_RQCPM0 CAN_INT_TME
+#define CAN_INT_RQCPM1 CAN_INT_TME
+#define CAN_INT_RQCPM2 CAN_INT_TME
+
+#define IS_CAN_INT(IT)                                                                                                 \
+    (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FMP0) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0)                \
+     || ((IT) == CAN_INT_FMP1) || ((IT) == CAN_INT_FF1) || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG)             \
+     || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR)               \
+     || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK))
+
+#define IS_CAN_CLEAR_INT(IT)                                                                                           \
+    (((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) || ((IT) == CAN_INT_FF1)                 \
+     || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF)              \
+     || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK))
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Legacy
+ * @{
+ */
+#define CANINITSTSFAILED CAN_InitSTS_Failed
+#define CANINITSTSOK     CAN_InitSTS_Success
+#define CAN_FilterFIFO0  CAN_Filter_FIFO0
+#define CAN_FilterFIFO1  CAN_Filter_FIFO1
+#define CAN_ID_STD       CAN_Standard_Id
+#define CAN_ID_EXT       CAN_Extended_Id
+#define CAN_RTRQ_DATA    CAN_RTRQ_Data
+#define CAN_RTRQ_REMOTE  CAN_RTRQ_Remote
+#define CANTXSTSFAILE    CAN_TxSTS_Failed
+#define CANTXSTSOK       CAN_TxSTS_Ok
+#define CANTXSTSPENDING  CAN_TxSTS_Pending
+#define CAN_STS_NO_MB    CAN_TxSTS_NoMailBox
+#define CANSLEEPFAILED   CAN_SLEEP_Failed
+#define CANSLEEPOK       CAN_SLEEP_Ok
+#define CANWKUFAILED     CAN_WKU_Failed
+#define CANWKUOK         CAN_WKU_Ok
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions
+ * @{
+ */
+/*  Function used to set the CAN configuration to the default reset state *****/
+void CAN_DeInit(CAN_Module* CANx);
+
+/* Initialization and Configuration functions *********************************/
+uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam);
+void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct);
+void CAN_InitStruct(CAN_InitType* CAN_InitParam);
+void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd);
+void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd);
+
+/* Transmit functions *********************************************************/
+uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage);
+uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox);
+
+/* Receive functions **********************************************************/
+void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage);
+void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum);
+uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_EnterSleep(CAN_Module* CANx);
+uint8_t CAN_WakeUp(CAN_Module* CANx);
+
+/* Error management functions *************************************************/
+uint8_t CAN_GetLastErrCode(CAN_Module* CANx);
+uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx);
+uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd);
+FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG);
+INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT);
+void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_CAN_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_comp.h

@@ -0,0 +1,282 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_comp.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_COMP_H__
+#define __N32G43X_COMP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+#include <stdbool.h>
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @{
+ */
+
+/** @addtogroup COMP_Exported_Constants
+ * @{
+ */
+typedef enum
+{
+    COMP1 = 0,
+    COMP2 = 1,
+} COMPX;
+
+// COMPx_CTRL
+#define COMP1_CTRL_PWRMODE_MASK (0x01L << 21)
+#define COMP1_CTRL_INPDAC_MASK  (0x01L << 20)
+#define COMP_CTRL_OUT_MASK      (0x01L << 19)
+#define COMP_CTRL_BLKING_MASK   (0x03L << 16)
+typedef enum
+{
+    COMP_CTRL_BLKING_NO       = (0x0L << 16),
+    COMP_CTRL_BLKING_TIM1_OC5 = (0x1L << 16),
+    COMP_CTRL_BLKING_TIM8_OC5 = (0x2L << 16),
+} COMP_CTRL_BLKING;
+#define COMPx_CTRL_HYST_MASK (0x03L << 14)
+typedef enum
+{
+    COMP_CTRL_HYST_NO   = (0x0L << 14),
+    COMP_CTRL_HYST_LOW  = (0x1L << 14),
+    COMP_CTRL_HYST_MID  = (0x2L << 14),
+    COMP_CTRL_HYST_HIGH = (0x3L << 14),
+} COMP_CTRL_HYST;
+
+#define COMP_POL_MASK         (0x01L << 13)
+#define COMP_CTRL_OUTSEL_MASK (0x0FL << 9)
+typedef enum
+{
+    // comp1 out trig
+    COMP1_CTRL_OUTSEL_NC                  = (0x0L << 9),
+    COMP1_CTRL_OUTSEL_TIM1_BKIN           = (0x1L << 9),
+    COMP1_CTRL_OUTSEL_TIM1_OCrefclear     = (0x2L << 9),
+    COMP1_CTRL_OUTSEL_TIM1_IC1            = (0x3L << 9),
+    COMP1_CTRL_OUTSEL_TIM2_IC1            = (0x4L << 9),
+    COMP1_CTRL_OUTSEL_TIM2_OCrefclear     = (0x5L << 9),
+    COMP1_CTRL_OUTSEL_TIM3_IC1            = (0x6L << 9),
+    COMP1_CTRL_OUTSEL_TIM3_OCrefclear     = (0x7L << 9),
+    COMP1_CTRL_OUTSEL_TIM4_OCrefclear     = (0x8L << 9),
+    COMP1_CTRL_OUTSEL_TIM5_IC1            = (0x9L << 9),
+    COMP1_CTRL_OUTSEL_TIM8_IC1            = (0xAL << 9),
+    COMP1_CTRL_OUTSEL_TIM8_OCrefclear     = (0xBL << 9),
+    COMP1_CTRL_OUTSEL_TIM9_OCrefclear     = (0xCL << 9),
+    COMP1_CTRL_OUTSEL_TIM8_BKIN           = (0xDL << 9),
+    COMP1_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9),
+    COMP1_CTRL_OUTSEL_LPTIM_ETR           = (0xFL << 9),
+    // comp2 out trig
+    COMP2_CTRL_OUTSEL_NC                  = (0x0L << 9),
+    COMP2_CTRL_OUTSEL_TIM1_BKIN           = (0x1L << 9),
+    COMP2_CTRL_OUTSEL_TIM1_OCrefclear     = (0x2L << 9),
+    COMP2_CTRL_OUTSEL_TIM1_IC1            = (0x3L << 9),
+    COMP2_CTRL_OUTSEL_TIM2_OCrefclear     = (0x4L << 9),
+    COMP2_CTRL_OUTSEL_TIM3_OCrefclear     = (0x5L << 9),
+    COMP2_CTRL_OUTSEL_TIM4_IC1            = (0x6L << 9),
+    COMP2_CTRL_OUTSEL_TIM4_OCrefclear     = (0x7L << 9),
+    COMP2_CTRL_OUTSEL_TIM5_IC1            = (0x8L << 9),
+    COMP2_CTRL_OUTSEL_TIM8_IC1            = (0x9L << 9),
+    COMP2_CTRL_OUTSEL_TIM8_OCrefclear     = (0xAL << 9),
+    COMP2_CTRL_OUTSEL_TIM9_IC1            = (0xBL << 9),
+    COMP2_CTRL_OUTSEL_TIM9_OCrefclear     = (0xCL << 9),
+    COMP2_CTRL_OUTSEL_TIM8_BKIN           = (0xDL << 9),
+    COMP2_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9),
+    COMP2_CTRL_OUTSEL_LPTIM_ETR           = (0xFL << 9),
+} COMP_CTRL_OUTTRIG;
+
+#define COMP_CTRL_INPSEL_MASK                       (0x0FL<<5)
+typedef enum {
+  //comp1 inp sel
+  COMP1_CTRL_INPSEL_FLOAT       = ((uint32_t)0x00000000),
+  COMP1_CTRL_INPSEL_PA0         = ((uint32_t)0x00000100),
+  COMP1_CTRL_INPSEL_PA2         = ((uint32_t)0x00000140),
+  COMP1_CTRL_INPSEL_PA12        = ((uint32_t)0x00000160),
+  COMP1_CTRL_INPSEL_PB3         = ((uint32_t)0x00000180),
+  COMP1_CTRL_INPSEL_PB4         = ((uint32_t)0x000001A0),
+  COMP1_CTRL_INPSEL_PB10        = ((uint32_t)0x000001C0),
+  COMP1_CTRL_INPSEL_PD5         = ((uint32_t)0x000001E0),
+  COMP1_CTRL_INPSEL_PA1_DAC1    = ((uint32_t)0x00000120),
+  //comp2 inp sel
+  COMP2_CTRL_INPSEL_FLOAT       = ((uint32_t)0x00000000),
+  COMP2_CTRL_INPSEL_PA1_DAC1_PA4= ((uint32_t)0x00000100),
+  COMP2_CTRL_INPSEL_PA3         = ((uint32_t)0x00000120),
+  COMP2_CTRL_INPSEL_PA6         = ((uint32_t)0x00000140),
+  COMP2_CTRL_INPSEL_PA7         = ((uint32_t)0x00000160),
+  COMP2_CTRL_INPSEL_PA11        = ((uint32_t)0x00000180),
+  COMP2_CTRL_INPSEL_PA15        = ((uint32_t)0x000001A0),
+  COMP2_CTRL_INPSEL_PB7         = ((uint32_t)0x000001C0),
+  COMP2_CTRL_INPSEL_PD7         = ((uint32_t)0x000001E0),
+}COMP_CTRL_INPSEL;
+
+
+#define COMP_CTRL_INMSEL_MASK                       (0x07L<<1)
+typedef enum {
+  //comp1 inm sel
+  COMP1_CTRL_INMSEL_DAC1_PA4    = ((uint32_t)0x00000002),
+  COMP1_CTRL_INMSEL_PA0         = ((uint32_t)0x00000004),
+  COMP1_CTRL_INMSEL_PA5         = ((uint32_t)0x00000006),
+  COMP1_CTRL_INMSEL_PB5         = ((uint32_t)0x00000008),
+  COMP1_CTRL_INMSEL_PD4         = ((uint32_t)0x0000000A),
+  COMP1_CTRL_INMSEL_VREF_VC1    = ((uint32_t)0x0000000C),
+  COMP1_CTRL_INMSEL_VREF_VC2    = ((uint32_t)0x0000000E),
+  COMP1_CTRL_INMSEL_NC          = ((uint32_t)0x00000000),
+  //comp2 inm sel
+  COMP2_CTRL_INMSEL_PA2         = ((uint32_t)0x00000002),
+  COMP2_CTRL_INMSEL_PA5         = ((uint32_t)0x00000004),
+  COMP2_CTRL_INMSEL_PA6         = ((uint32_t)0x00000006),
+  COMP2_CTRL_INMSEL_PB3         = ((uint32_t)0x00000008),
+  COMP2_CTRL_INMSEL_PD6         = ((uint32_t)0x0000000A),
+  COMP2_CTRL_INMSEL_DAC1_PA4    = ((uint32_t)0x0000000C),
+  COMP2_CTRL_INMSEL_VREF_VC2    = ((uint32_t)0x0000000E),
+  COMP2_CTRL_INMSEL_NC          = ((uint32_t)0x00000000),
+}COMP_CTRL_INMSEL;
+
+#define COMP_CTRL_EN_MASK (0x01L << 0)
+
+//COMPx_FILC
+#define COMP_FILC_SAMPW_MASK                        (0x1FL<<6)//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
+#define COMP_FILC_THRESH_MASK                       (0x1FL<<1)//For proper operation, the value of THRESH must be greater than SAMPWIN / 2.
+#define COMP_FILC_FILEN_MASK                        (0x01L<<0)//Filter enable.
+
+//COMPx_FILP
+#define COMP_FILP_CLKPSC_MASK                        (0xFFFFL)//Prescale number .
+
+//COMP_WINMODE @addtogroup COMP_WINMODE_CMPMD
+#define COMP_WINMODE_CMP12MD                        (0x01L <<0)//1: Comparators 1 and 2 can be used in window mode.
+
+//COMP_INTEN @addtogroup COMP_INTEN_CMPIEN
+#define COMP_INTEN_CMPIEN_MSK   (0x3L << 0) // This bit control Interrput enable of COMP.
+#define COMP_INTEN_CMP2IEN      (0x01L << 1)
+#define COMP_INTEN_CMP1IEN      (0x01L << 0)
+
+//COMP_INTSTS @addtogroup COMP_INTSTS_CMPIS
+#define COMP_INTSTS_INTSTS_MSK  (0x3L << 0) // This bit control Interrput enable of COMP.
+#define COMP_INTSTS_CMP2IS      (0x01L << 1)
+#define COMP_INTSTS_CMP1IS      (0x01L << 0)
+
+//COMP_VREFSCL @addtogroup COMP_VREFSCL
+#define COMP_VREFSCL_VV2TRM_MSK (0x3FL << 8) // Vref2 Voltage scaler triming value.
+#define COMP_VREFSCL_VV2EN_MSK  (0x01L << 7)
+#define COMP_VREFSCL_VV1TRM_MSK (0x3FL << 1) // Vref1 Voltage scaler triming value.
+#define COMP_VREFSCL_VV1EN_MSK  (0x01L << 0)
+
+//COMP_LOCK @addtogroup COMP_LOCK
+#define COMP_LOCK_CMP2LK        (0x1L << 1) // Vref1 Voltage scaler triming value.
+#define COMP_LOCK_CMP1LK        (0x1L << 0)
+
+//COMP_LPCKSEL @addtogroup COMP_LPCKSEL
+#define COMP_LKCKSEL_LPCLKSEL    (0x1L << 0)
+
+//COMP_OSEL @addtogroup COMP_OSEL
+#define COMP_OSEL_CMP2XO         (0x1L << 0)
+
+/**
+ * @}
+ */
+
+/**
+ * @brief  COMP Init structure definition
+ */
+
+typedef struct
+{
+    // ctrl
+    bool LowPoweMode; // only COMP1 have this bit
+    bool InpDacConnect; // only COMP1 have this bit
+
+    COMP_CTRL_BLKING Blking; /*see @ref COMP_CTRL_BLKING */
+
+    COMP_CTRL_HYST Hyst;
+
+    bool PolRev; // out polarity reverse
+
+    COMP_CTRL_OUTTRIG OutTrig;
+    COMP_CTRL_INPSEL InpSel;
+    COMP_CTRL_INMSEL InmSel;
+
+    bool En;
+
+    // filter
+    uint8_t SampWindow; // 5bit
+    uint8_t Thresh;     // 5bit ,need > SampWindow/2
+    bool FilterEn;
+
+    // filter psc
+    uint16_t ClkPsc;
+} COMP_InitType;
+
+/** @addtogroup COMP_Exported_Functions
+ * @{
+ */
+
+void COMP_DeInit(void);
+void COMP_StructInit(COMP_InitType* COMP_InitStruct);
+void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct);
+void COMP_Enable(COMPX COMPx, FunctionalState en);
+void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel);
+void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel);
+void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig);
+uint32_t COMP_GetIntSts(void);                                                 // return see @COMP_INTSTS_CMPIS
+void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En); // parma range see @COMP_VREFSCL
+FlagStatus COMP_GetOutStatus(COMPX COMPx);
+FlagStatus COMP_GetIntStsOneComp(COMPX COMPx);
+void COMP_SetLock(uint32_t Lock);                                              // see @COMP_LOCK_CMPLK
+void COMP_SetIntEn(uint32_t IntEn);                                            // see @COMP_INTEN_CMPIEN
+void COMP_CMP2XorOut(bool En);
+void COMP_StopOrLowpower32KClkSel(bool En);
+void COMP_WindowModeEn(bool En);
+void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal);
+void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW);
+void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST);
+void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_ADC_H */
+/**
+ * @}
+ */
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_crc.h

@@ -0,0 +1,105 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_crc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_CRC_H__
+#define __N32G43X_CRC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/** @addtogroup CRC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions
+ * @{
+ */
+
+void CRC32_ResetCrc(void);
+uint32_t CRC32_CalcCrc(uint32_t Data);
+uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC32_GetCrc(void);
+void CRC32_SetIDat(uint8_t IDValue);
+uint8_t CRC32_GetIDat(void);
+
+uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength);
+uint16_t CRC16_CalcCRC(uint8_t Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_CRC_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dac.h

@@ -0,0 +1,293 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_dac.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_DAC_H__
+#define __N32G43X_DAC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief  DAC Init structure definition
+ */
+
+typedef struct
+{
+    uint32_t Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+                               This parameter can be a value of @ref DAC_trigger_selection */
+
+    uint32_t WaveGen; /*!< Specifies whether DAC channel noise waves or triangle waves
+                                      are generated, or whether no wave is generated.
+                                      This parameter can be a value of @ref DAC_wave_generation */
+
+    uint32_t
+        LfsrUnMaskTriAmp; /*!< Specifies the LFSR mask for noise wave generation or
+                                               the maximum amplitude triangle generation for the DAC channel.
+                                               This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+    uint32_t BufferOutput; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                    This parameter can be a value of @ref DAC_output_buffer */
+} DAC_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_TRG_NONE                                                                                                   \
+    ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register                                 \
+                                    has been loaded, and not by external trigger */
+#define DAC_TRG_T6_TRGO                                                                                                \
+    ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel                      \
+                            */
+#define DAC_TRG_T8_TRGO                                                                                                \
+    ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel                      \
+                                    only in High-density devices*/
+#define DAC_TRG_T7_TRGO                                                                                                \
+    ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel                      \
+                            */
+#define DAC_TRG_T5_TRGO                                                                                                \
+    ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel                      \
+                            */
+#define DAC_TRG_T2_TRGO                                                                                                \
+    ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel                      \
+                            */
+#define DAC_TRG_T4_TRGO                                                                                                \
+    ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel                      \
+                            */
+#define DAC_TRG_EXT_IT9                                                                                                \
+    ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRG_SOFTWARE ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER)                                                                                        \
+    (((TRIGGER) == DAC_TRG_NONE) || ((TRIGGER) == DAC_TRG_T6_TRGO) || ((TRIGGER) == DAC_TRG_T8_TRGO)                   \
+     || ((TRIGGER) == DAC_TRG_T7_TRGO) || ((TRIGGER) == DAC_TRG_T5_TRGO) || ((TRIGGER) == DAC_TRG_T2_TRGO)             \
+     || ((TRIGGER) == DAC_TRG_T4_TRGO) || ((TRIGGER) == DAC_TRG_EXT_IT9) || ((TRIGGER) == DAC_TRG_SOFTWARE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WAVEGEN_NONE     ((uint32_t)0x00000000)
+#define DAC_WAVEGEN_NOISE    ((uint32_t)0x00000040)
+#define DAC_WAVEGEN_TRIANGLE ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE)                                                                                     \
+    (((WAVE) == DAC_WAVEGEN_NONE) || ((WAVE) == DAC_WAVEGEN_NOISE) || ((WAVE) == DAC_WAVEGEN_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_lfsrunmask_triangleamplitude
+ * @{
+ */
+
+#define DAC_UNMASK_LFSRBIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_UNMASK_LFSRBITS1_0                                                                                         \
+    ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation                             \
+                            */
+#define DAC_UNMASK_LFSRBITS2_0                                                                                         \
+    ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation                             \
+                            */
+#define DAC_UNMASK_LFSRBITS3_0                                                                                         \
+    ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation                             \
+                            */
+#define DAC_UNMASK_LFSRBITS4_0                                                                                         \
+    ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation                             \
+                            */
+#define DAC_UNMASK_LFSRBITS5_0                                                                                         \
+    ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation                             \
+                            */
+#define DAC_UNMASK_LFSRBITS6_0                                                                                         \
+    ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation                             \
+                            */
+#define DAC_UNMASK_LFSRBITS7_0                                                                                         \
+    ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation                             \
+                            */
+#define DAC_UNMASK_LFSRBITS8_0                                                                                         \
+    ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation                             \
+                            */
+#define DAC_UNMASK_LFSRBITS9_0                                                                                         \
+    ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation                             \
+                            */
+#define DAC_UNMASK_LFSRBITS10_0                                                                                        \
+    ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_UNMASK_LFSRBITS11_0                                                                                        \
+    ((uint32_t)0x00000B00)                     /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIAMP_1    ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIAMP_3    ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIAMP_7    ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIAMP_15   ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIAMP_31   ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIAMP_63   ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIAMP_127  ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIAMP_255  ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIAMP_511  ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIAMP_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIAMP_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIAMP_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)                                                                   \
+    (((VALUE) == DAC_UNMASK_LFSRBIT0) || ((VALUE) == DAC_UNMASK_LFSRBITS1_0) || ((VALUE) == DAC_UNMASK_LFSRBITS2_0)    \
+     || ((VALUE) == DAC_UNMASK_LFSRBITS3_0) || ((VALUE) == DAC_UNMASK_LFSRBITS4_0)                                     \
+     || ((VALUE) == DAC_UNMASK_LFSRBITS5_0) || ((VALUE) == DAC_UNMASK_LFSRBITS6_0)                                     \
+     || ((VALUE) == DAC_UNMASK_LFSRBITS7_0) || ((VALUE) == DAC_UNMASK_LFSRBITS8_0)                                     \
+     || ((VALUE) == DAC_UNMASK_LFSRBITS9_0) || ((VALUE) == DAC_UNMASK_LFSRBITS10_0)                                    \
+     || ((VALUE) == DAC_UNMASK_LFSRBITS11_0) || ((VALUE) == DAC_TRIAMP_1) || ((VALUE) == DAC_TRIAMP_3)                 \
+     || ((VALUE) == DAC_TRIAMP_7) || ((VALUE) == DAC_TRIAMP_15) || ((VALUE) == DAC_TRIAMP_31)                          \
+     || ((VALUE) == DAC_TRIAMP_63) || ((VALUE) == DAC_TRIAMP_127) || ((VALUE) == DAC_TRIAMP_255)                       \
+     || ((VALUE) == DAC_TRIAMP_511) || ((VALUE) == DAC_TRIAMP_1023) || ((VALUE) == DAC_TRIAMP_2047)                    \
+     || ((VALUE) == DAC_TRIAMP_4095))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_output_buffer
+ * @{
+ */
+
+#define DAC_BUFFOUTPUT_ENABLE             ((uint32_t)0x00000002)
+#define DAC_BUFFOUTPUT_DISABLE            ((uint32_t)0x00000000)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_BUFFOUTPUT_ENABLE) || ((STATE) == DAC_BUFFOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_data_alignment
+ * @{
+ */
+
+#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000000)
+#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004)
+#define DAC_ALIGN_R_8BIT  ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN)                                                                                            \
+    (((ALIGN) == DAC_ALIGN_R_12BIT) || ((ALIGN) == DAC_ALIGN_L_12BIT) || ((ALIGN) == DAC_ALIGN_R_8BIT))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WAVE_NOISE    ((uint32_t)0x00000040)
+#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_data
+ * @{
+ */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+void DAC_DeInit(void);
+void DAC_Init(DAC_InitType* DAC_InitStruct);
+void DAC_ClearStruct(DAC_InitType* DAC_InitStruct);
+void DAC_Enable(FunctionalState Cmd);
+
+void DAC_DmaEnable(FunctionalState Cmd);
+void DAC_SoftTrgEnable(FunctionalState Cmd);
+void DAC_SoftwareTrgEnable(FunctionalState Cmd);
+void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd);
+void DAC_SetChData(uint32_t DAC_Align, uint16_t Data);
+uint16_t DAC_GetOutputDataVal(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_DAC_H__ */
+       /**
+        * @}
+        */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dbg.h

@@ -0,0 +1,124 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_dbg.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43x_DBG_H__
+#define __N32G43x_DBG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBG
+ * @{
+ */
+
+/** @addtogroup DBGMCU_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Constants
+ * @{
+ */
+
+#define DBG_SLEEP             ((uint32_t)0x00000001)
+#define DBG_STOP              ((uint32_t)0x00000002)
+#define DBG_STDBY             ((uint32_t)0x00000004)
+#define DBG_IWDG_STOP         ((uint32_t)0x00000100)
+#define DBG_WWDG_STOP         ((uint32_t)0x00000200)
+#define DBG_TIM1_STOP         ((uint32_t)0x00000400)
+#define DBG_TIM2_STOP         ((uint32_t)0x00000800)
+#define DBG_TIM3_STOP         ((uint32_t)0x00001000)
+#define DBG_TIM4_STOP         ((uint32_t)0x00002000)
+#define DBG_CAN_STOP          ((uint32_t)0x00004000)
+#define DBG_I2C1SMBUS_TIMEOUT ((uint32_t)0x00008000)
+#define DBG_I2C2SMBUS_TIMEOUT ((uint32_t)0x00010000)
+#define DBG_TIM8_STOP         ((uint32_t)0x00020000)
+#define DBG_TIM5_STOP         ((uint32_t)0x00040000)
+#define DBG_TIM6_STOP         ((uint32_t)0x00080000)
+#define DBG_TIM7_STOP         ((uint32_t)0x00100000)
+#define DBG_TIM9_STOP         ((uint32_t)0x00200000)
+
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH)&0xFFC000F8) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Exported_Functions
+ * @{
+ */
+
+void GetUCID(uint8_t *UCIDbuf);
+void GetUID(uint8_t *UIDbuf);
+void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf);
+uint32_t DBG_GetRevNum(void);
+uint32_t DBG_GetDevNum(void);
+void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd);
+
+uint32_t DBG_GetFlashSize(void);
+uint32_t DBG_GetSramSize(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43x_DBG_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dma.h

@@ -0,0 +1,469 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_dma.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_DMA_H__
+#define __N32G43X_DMA_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief  DMA Init structure definition
+ */
+
+typedef struct
+{
+    uint32_t PeriphAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+    uint32_t MemAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+    uint32_t Direction; /*!< Specifies if the peripheral is the source or destination.
+                           This parameter can be a value of @ref DMA_data_transfer_direction */
+
+    uint32_t BufSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+                                  The data unit is equal to the configuration set in PeriphDataSize
+                                  or MemDataSize members depending in the transfer direction. */
+
+    uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+                                     This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+    uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+                                 This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+    uint32_t PeriphDataSize; /*!< Specifies the Peripheral data width.
+                                          This parameter can be a value of @ref DMA_peripheral_data_size */
+
+    uint32_t MemDataSize; /*!< Specifies the Memory data width.
+                                      This parameter can be a value of @ref DMA_memory_data_size */
+
+    uint32_t CircularMode; /*!< Specifies the operation mode of the DMAy Channelx.
+                            This parameter can be a value of @ref DMA_circular_normal_mode.
+                            @note: The circular buffer mode cannot be used if the memory-to-memory
+                                   data transfer is configured on the selected Channel */
+
+    uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+                                This parameter can be a value of @ref DMA_priority_level */
+
+    uint32_t Mem2Mem; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                           This parameter can be a value of @ref DMA_memory_to_memory */
+} DMA_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH)                                                                                      \
+    (((PERIPH) == DMA_CH1) || ((PERIPH) == DMA_CH2) || ((PERIPH) == DMA_CH3) || ((PERIPH) == DMA_CH4)              \
+     || ((PERIPH) == DMA_CH5) || ((PERIPH) == DMA_CH6) || ((PERIPH) == DMA_CH7) || ((PERIPH) == DMA_CH8))
+
+/** @addtogroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PERIPH_DST ((uint32_t)0x00000010)
+#define DMA_DIR_PERIPH_SRC ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR)    (((DIR) == DMA_DIR_PERIPH_DST) || ((DIR) == DMA_DIR_PERIPH_SRC))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PERIPH_INC_ENABLE          ((uint32_t)0x00000040)
+#define DMA_PERIPH_INC_DISABLE         ((uint32_t)0x00000000)
+#define IS_DMA_PERIPH_INC_STATE(STATE) (((STATE) == DMA_PERIPH_INC_ENABLE) || ((STATE) == DMA_PERIPH_INC_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MEM_INC_ENABLE          ((uint32_t)0x00000080)
+#define DMA_MEM_INC_DISABLE         ((uint32_t)0x00000000)
+#define IS_DMA_MEM_INC_STATE(STATE) (((STATE) == DMA_MEM_INC_ENABLE) || ((STATE) == DMA_MEM_INC_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PERIPH_DATA_SIZE_BYTE     ((uint32_t)0x00000000)
+#define DMA_PERIPH_DATA_SIZE_HALFWORD ((uint32_t)0x00000100)
+#define DMA_PERIPH_DATA_SIZE_WORD     ((uint32_t)0x00000200)
+#define IS_DMA_PERIPH_DATA_SIZE(SIZE)                                                                                  \
+    (((SIZE) == DMA_PERIPH_DATA_SIZE_BYTE) || ((SIZE) == DMA_PERIPH_DATA_SIZE_HALFWORD)                                \
+     || ((SIZE) == DMA_PERIPH_DATA_SIZE_WORD))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte     ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word     ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE)                                                                                  \
+    (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord)                                    \
+     || ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_MODE_CIRCULAR ((uint32_t)0x00000020)
+#define DMA_MODE_NORMAL   ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)0x00003000)
+#define DMA_PRIORITY_HIGH      ((uint32_t)0x00002000)
+#define DMA_PRIORITY_MEDIUM    ((uint32_t)0x00001000)
+#define DMA_PRIORITY_LOW       ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY)                                                                                      \
+    (((PRIORITY) == DMA_PRIORITY_VERY_HIGH) || ((PRIORITY) == DMA_PRIORITY_HIGH)                                       \
+     || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_ENABLE          ((uint32_t)0x00004000)
+#define DMA_M2M_DISABLE         ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_ENABLE) || ((STATE) == DMA_M2M_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_INT_TXC           ((uint32_t)0x00000002)
+#define DMA_INT_HTX           ((uint32_t)0x00000004)
+#define DMA_INT_ERR           ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_INT(IT) ((((IT)&0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA_INT_GLB1 ((uint32_t)0x00000001)
+#define DMA_INT_TXC1 ((uint32_t)0x00000002)
+#define DMA_INT_HTX1 ((uint32_t)0x00000004)
+#define DMA_INT_ERR1 ((uint32_t)0x00000008)
+#define DMA_INT_GLB2 ((uint32_t)0x00000010)
+#define DMA_INT_TXC2 ((uint32_t)0x00000020)
+#define DMA_INT_HTX2 ((uint32_t)0x00000040)
+#define DMA_INT_ERR2 ((uint32_t)0x00000080)
+#define DMA_INT_GLB3 ((uint32_t)0x00000100)
+#define DMA_INT_TXC3 ((uint32_t)0x00000200)
+#define DMA_INT_HTX3 ((uint32_t)0x00000400)
+#define DMA_INT_ERR3 ((uint32_t)0x00000800)
+#define DMA_INT_GLB4 ((uint32_t)0x00001000)
+#define DMA_INT_TXC4 ((uint32_t)0x00002000)
+#define DMA_INT_HTX4 ((uint32_t)0x00004000)
+#define DMA_INT_ERR4 ((uint32_t)0x00008000)
+#define DMA_INT_GLB5 ((uint32_t)0x00010000)
+#define DMA_INT_TXC5 ((uint32_t)0x00020000)
+#define DMA_INT_HTX5 ((uint32_t)0x00040000)
+#define DMA_INT_ERR5 ((uint32_t)0x00080000)
+#define DMA_INT_GLB6 ((uint32_t)0x00100000)
+#define DMA_INT_TXC6 ((uint32_t)0x00200000)
+#define DMA_INT_HTX6 ((uint32_t)0x00400000)
+#define DMA_INT_ERR6 ((uint32_t)0x00800000)
+#define DMA_INT_GLB7 ((uint32_t)0x01000000)
+#define DMA_INT_TXC7 ((uint32_t)0x02000000)
+#define DMA_INT_HTX7 ((uint32_t)0x04000000)
+#define DMA_INT_ERR7 ((uint32_t)0x08000000)
+#define DMA_INT_GLB8 ((uint32_t)0x10000000)
+#define DMA_INT_TXC8 ((uint32_t)0x20000000)
+#define DMA_INT_HTX8 ((uint32_t)0x40000000)
+#define DMA_INT_ERR8 ((uint32_t)0x80000000)
+
+
+#define IS_DMA_CLR_INT(IT) ((IT) != 0x00)
+
+#define IS_DMA_GET_IT(IT)                                                                                              \
+    (((IT) == DMA_INT_GLB1) || ((IT) == DMA_INT_TXC1) || ((IT) == DMA_INT_HTX1) || ((IT) == DMA_INT_ERR1)          \
+     || ((IT) == DMA_INT_GLB2) || ((IT) == DMA_INT_TXC2) || ((IT) == DMA_INT_HTX2) || ((IT) == DMA_INT_ERR2)       \
+     || ((IT) == DMA_INT_GLB3) || ((IT) == DMA_INT_TXC3) || ((IT) == DMA_INT_HTX3) || ((IT) == DMA_INT_ERR3)       \
+     || ((IT) == DMA_INT_GLB4) || ((IT) == DMA_INT_TXC4) || ((IT) == DMA_INT_HTX4) || ((IT) == DMA_INT_ERR4)       \
+     || ((IT) == DMA_INT_GLB5) || ((IT) == DMA_INT_TXC5) || ((IT) == DMA_INT_HTX5) || ((IT) == DMA_INT_ERR5)       \
+     || ((IT) == DMA_INT_GLB6) || ((IT) == DMA_INT_TXC6) || ((IT) == DMA_INT_HTX6) || ((IT) == DMA_INT_ERR6)       \
+     || ((IT) == DMA_INT_GLB7) || ((IT) == DMA_INT_TXC7) || ((IT) == DMA_INT_HTX7) || ((IT) == DMA_INT_ERR7)       \
+     || ((IT) == DMA_INT_GLB8) || ((IT) == DMA_INT_TXC8) || ((IT) == DMA_INT_HTX8) || ((IT) == DMA_INT_ERR8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_flags_definition
+ * @{
+ */
+#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
+#define DMA_FLAG_GL8 ((uint32_t)0x10000000)
+#define DMA_FLAG_TC8 ((uint32_t)0x20000000)
+#define DMA_FLAG_HT8 ((uint32_t)0x40000000)
+#define DMA_FLAG_TE8 ((uint32_t)0x80000000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) ((FLAG) != 0x00)
+
+#define IS_DMA_GET_FLAG(FLAG)                                                                                          \
+    (((FLAG) == DMA_FLAG_GL1) || ((FLAG) == DMA_FLAG_TC1) || ((FLAG) == DMA_FLAG_HT1) || ((FLAG) == DMA_FLAG_TE1)  \
+     || ((FLAG) == DMA_FLAG_GL2) || ((FLAG) == DMA_FLAG_TC2) || ((FLAG) == DMA_FLAG_HT2)                            \
+     || ((FLAG) == DMA_FLAG_TE2) || ((FLAG) == DMA_FLAG_GL3) || ((FLAG) == DMA_FLAG_TC3)                            \
+     || ((FLAG) == DMA_FLAG_HT3) || ((FLAG) == DMA_FLAG_TE3) || ((FLAG) == DMA_FLAG_GL4)                            \
+     || ((FLAG) == DMA_FLAG_TC4) || ((FLAG) == DMA_FLAG_HT4) || ((FLAG) == DMA_FLAG_TE4)                            \
+     || ((FLAG) == DMA_FLAG_GL5) || ((FLAG) == DMA_FLAG_TC5) || ((FLAG) == DMA_FLAG_HT5)                            \
+     || ((FLAG) == DMA_FLAG_TE5) || ((FLAG) == DMA_FLAG_GL6) || ((FLAG) == DMA_FLAG_TC6)                            \
+     || ((FLAG) == DMA_FLAG_HT6) || ((FLAG) == DMA_FLAG_TE6) || ((FLAG) == DMA_FLAG_GL7)                            \
+     || ((FLAG) == DMA_FLAG_TC7) || ((FLAG) == DMA_FLAG_HT7) || ((FLAG) == DMA_FLAG_TE7)                            \
+     || ((FLAG) == DMA_FLAG_GL8) || ((FLAG) == DMA_FLAG_TC8) || ((FLAG) == DMA_FLAG_HT8)                            \
+     || ((FLAG) == DMA_FLAG_TE8))
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Buffer_Size
+ * @{
+ */
+
+#define IS_DMA_BUF_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_remap_request_definition
+ * @{
+ */
+#define DMA_REMAP_ADC1                    ((uint32_t)0x00000000)
+#define DMA_REMAP_USART1_TX               ((uint32_t)0x00000001)
+#define DMA_REMAP_USART1_RX               ((uint32_t)0x00000002)
+#define DMA_REMAP_USART2_TX               ((uint32_t)0x00000003)
+#define DMA_REMAP_USART2_RX               ((uint32_t)0x00000004)
+#define DMA_REMAP_USART3_TX               ((uint32_t)0x00000005)
+#define DMA_REMAP_USART3_RX               ((uint32_t)0x00000006)
+#define DMA_REMAP_UART4_TX                ((uint32_t)0x00000007)
+#define DMA_REMAP_UART4_RX                ((uint32_t)0x00000008)
+#define DMA_REMAP_UART5_TX                ((uint32_t)0x00000009)
+#define DMA_REMAP_UART5_RX                ((uint32_t)0x0000000A)
+#define DMA_REMAP_LPUART_TX               ((uint32_t)0x0000000B)
+#define DMA_REMAP_LPUART_RX               ((uint32_t)0x0000000C)
+#define DMA_REMAP_SPI1_TX                 ((uint32_t)0x0000000D)
+#define DMA_REMAP_SPI1_RX                 ((uint32_t)0x0000000E)
+#define DMA_REMAP_SPI2_TX                 ((uint32_t)0x0000000F)
+#define DMA_REMAP_SPI2_RX                 ((uint32_t)0x00000010)
+#define DMA_REMAP_I2C1_TX                 ((uint32_t)0x00000011)
+#define DMA_REMAP_I2C1_RX                 ((uint32_t)0x00000012)
+#define DMA_REMAP_I2C2_TX                 ((uint32_t)0x00000013)
+#define DMA_REMAP_I2C2_RX                 ((uint32_t)0x00000014)
+#define DMA_REMAP_DAC1                    ((uint32_t)0x00000015)
+#define DMA_REMAP_TIM1_CH1                ((uint32_t)0x00000016)
+#define DMA_REMAP_TIM1_CH2                ((uint32_t)0x00000017)
+#define DMA_REMAP_TIM1_CH3                ((uint32_t)0x00000018)
+#define DMA_REMAP_TIM1_CH4                ((uint32_t)0x00000019)
+#define DMA_REMAP_TIM1_COM                ((uint32_t)0x0000001A)
+#define DMA_REMAP_TIM1_UP                 ((uint32_t)0x0000001B)
+#define DMA_REMAP_TIM1_TRIG               ((uint32_t)0x0000001C)
+#define DMA_REMAP_TIM2_CH1                ((uint32_t)0x0000001D)
+#define DMA_REMAP_TIM2_CH2                ((uint32_t)0x0000001E)
+#define DMA_REMAP_TIM2_CH3                ((uint32_t)0x0000001F)
+#define DMA_REMAP_TIM2_CH4                ((uint32_t)0x00000020)
+#define DMA_REMAP_TIM2_UP                 ((uint32_t)0x00000021)
+#define DMA_REMAP_TIM3_CH1                ((uint32_t)0x00000022)
+#define DMA_REMAP_TIM3_CH3                ((uint32_t)0x00000023)
+#define DMA_REMAP_TIM3_CH4                ((uint32_t)0x00000024)
+#define DMA_REMAP_TIM3_UP                 ((uint32_t)0x00000025)
+#define DMA_REMAP_TIM3_TRIG               ((uint32_t)0x00000026)
+#define DMA_REMAP_TIM4_CH1                ((uint32_t)0x00000027)
+#define DMA_REMAP_TIM4_CH2                ((uint32_t)0x00000028)
+#define DMA_REMAP_TIM4_CH3                ((uint32_t)0x00000029)
+#define DMA_REMAP_TIM4_UP                 ((uint32_t)0x0000002A)
+#define DMA_REMAP_TIM5_CH1                ((uint32_t)0x0000002B)
+#define DMA_REMAP_TIM5_CH2                ((uint32_t)0x0000002C)
+#define DMA_REMAP_TIM5_CH3                ((uint32_t)0x0000002D)
+#define DMA_REMAP_TIM5_CH4                ((uint32_t)0x0000002E)
+#define DMA_REMAP_TIM5_UP                 ((uint32_t)0x0000002F)
+#define DMA_REMAP_TIM5_TRIG               ((uint32_t)0x00000030)
+#define DMA_REMAP_TIM6_UP                 ((uint32_t)0x00000031)
+#define DMA_REMAP_TIM7_UP                 ((uint32_t)0x00000032)
+#define DMA_REMAP_TIM8_CH1                ((uint32_t)0x00000033)
+#define DMA_REMAP_TIM8_CH2                ((uint32_t)0x00000034)
+#define DMA_REMAP_TIM8_CH3                ((uint32_t)0x00000035)
+#define DMA_REMAP_TIM8_CH4                ((uint32_t)0x00000036)
+#define DMA_REMAP_TIM8_COM                ((uint32_t)0x00000037)
+#define DMA_REMAP_TIM8_UP                 ((uint32_t)0x00000038)
+#define DMA_REMAP_TIM8_TRIG               ((uint32_t)0x00000039)
+#define DMA_REMAP_TIM9_CH1                ((uint32_t)0x0000003A)
+#define DMA_REMAP_TIM9_TRIG               ((uint32_t)0x0000003B)
+#define DMA_REMAP_TIM9_CH3                ((uint32_t)0x0000003C)
+#define DMA_REMAP_TIM9_CH4                ((uint32_t)0x0000003D)
+#define DMA_REMAP_TIM9_UP                 ((uint32_t)0x0000003E)
+
+
+#define IS_DMA_REMAP(FLAG)                                                                                             \
+    (((FLAG) == DMA_REMAP_ADC1) || ((FLAG) == DMA_REMAP_USART1_TX) || ((FLAG) == DMA_REMAP_USART1_RX)               \
+        || ((FLAG) == DMA_REMAP_USART2_TX) || ((FLAG) == DMA_REMAP_USART2_RX) || ((FLAG) == DMA_REMAP_USART3_TX)        \
+        || ((FLAG) == DMA_REMAP_USART3_RX) || ((FLAG) == DMA_REMAP_UART4_TX)  || ((FLAG) == DMA_REMAP_UART4_RX)         \
+        || ((FLAG) == DMA_REMAP_UART5_TX)  || ((FLAG) == DMA_REMAP_UART5_RX)  || ((FLAG) == DMA_REMAP_LPUART_TX)        \
+        || ((FLAG) == DMA_REMAP_LPUART_RX) || ((FLAG) == DMA_REMAP_SPI1_TX)   || ((FLAG) == DMA_REMAP_SPI1_RX)          \
+        || ((FLAG) == DMA_REMAP_SPI2_TX)  || ((FLAG) == DMA_REMAP_SPI2_RX) || ((FLAG) == DMA_REMAP_I2C1_TX)      \
+        || ((FLAG) == DMA_REMAP_I2C1_RX)  || ((FLAG) == DMA_REMAP_I2C2_TX)  || ((FLAG) == DMA_REMAP_I2C2_RX)              \
+        || ((FLAG) == DMA_REMAP_DAC1)     || ((FLAG) == DMA_REMAP_TIM1_CH1) || ((FLAG) == DMA_REMAP_TIM1_CH2)               \
+        || ((FLAG) == DMA_REMAP_TIM1_CH3) || ((FLAG) == DMA_REMAP_TIM1_CH4) || ((FLAG) == DMA_REMAP_TIM1_COM)           \
+        || ((FLAG) == DMA_REMAP_TIM1_UP)  || ((FLAG) == DMA_REMAP_TIM1_TRIG)|| ((FLAG) == DMA_REMAP_TIM2_CH1)           \
+        || ((FLAG) == DMA_REMAP_TIM2_CH2) || ((FLAG) == DMA_REMAP_TIM2_CH3) || ((FLAG) == DMA_REMAP_TIM2_CH4)           \
+        || ((FLAG) == DMA_REMAP_TIM2_UP)  || ((FLAG) == DMA_REMAP_TIM3_CH1) || ((FLAG) == DMA_REMAP_TIM3_CH3)           \
+        || ((FLAG) == DMA_REMAP_TIM3_CH4) || ((FLAG) == DMA_REMAP_TIM3_UP)  || ((FLAG) == DMA_REMAP_TIM3_TRIG)          \
+        || ((FLAG) == DMA_REMAP_TIM4_CH1) || ((FLAG) == DMA_REMAP_TIM4_CH2) || ((FLAG) == DMA_REMAP_TIM4_CH3)           \
+        || ((FLAG) == DMA_REMAP_TIM4_UP)  || ((FLAG) == DMA_REMAP_TIM5_CH1) || ((FLAG) == DMA_REMAP_TIM5_CH2)           \
+        || ((FLAG) == DMA_REMAP_TIM5_CH3) || ((FLAG) == DMA_REMAP_TIM5_CH4) || ((FLAG) == DMA_REMAP_TIM5_UP)            \
+        || ((FLAG) == DMA_REMAP_TIM5_TRIG)|| ((FLAG) == DMA_REMAP_TIM6_UP)  || ((FLAG) == DMA_REMAP_TIM7_UP)            \
+        || ((FLAG) == DMA_REMAP_TIM8_CH1) || ((FLAG) == DMA_REMAP_TIM8_CH2) || ((FLAG) == DMA_REMAP_TIM8_CH3)           \
+        || ((FLAG) == DMA_REMAP_TIM8_CH4) || ((FLAG) == DMA_REMAP_TIM8_COM) || ((FLAG) == DMA_REMAP_TIM8_UP)            \
+        || ((FLAG) == DMA_REMAP_TIM8_TRIG)|| ((FLAG) == DMA_REMAP_TIM9_CH1) || ((FLAG) == DMA_REMAP_TIM9_TRIG)          \
+        || ((FLAG) == DMA_REMAP_TIM9_CH3) || ((FLAG) == DMA_REMAP_TIM9_CH4) || ((FLAG) == DMA_REMAP_TIM9_UP))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions
+ * @{
+ */
+
+void DMA_DeInit(DMA_ChannelType* DMAChx);
+void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam);
+void DMA_StructInit(DMA_InitType* DMA_InitParam);
+void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd);
+void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd);
+void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy);
+void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy);
+INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy);
+void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy);
+void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_DMA_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_exti.h

@@ -0,0 +1,232 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_exti.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_EXTI_H__
+#define __N32G43X_EXTI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief  EXTI mode enumeration
+ */
+
+typedef enum
+{
+    EXTI_Mode_Interrupt = 0x00,
+    EXTI_Mode_Event     = 0x04
+} EXTI_ModeType;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief  EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+    EXTI_Trigger_Rising         = 0x08,
+    EXTI_Trigger_Falling        = 0x0C,
+    EXTI_Trigger_Rising_Falling = 0x10
+} EXTI_TriggerType;
+
+#define IS_EXTI_TRIGGER(TRIGGER)                                                                                       \
+    (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling)                                         \
+     || ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief  EXTI Init Structure definition
+ */
+
+typedef struct
+{
+    uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+                             This parameter can be any combination of @ref EXTI_Lines */
+
+    EXTI_ModeType EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_ModeType */
+
+    EXTI_TriggerType EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                           This parameter can be a value of @ref EXTI_ModeType */
+
+    FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+                                       This parameter can be set either to ENABLE or DISABLE */
+} EXTI_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_LINE0  ((uint32_t)0x00001) /*!< External interrupt line 0 */
+#define EXTI_LINE1  ((uint32_t)0x00002) /*!< External interrupt line 1 */
+#define EXTI_LINE2  ((uint32_t)0x00004) /*!< External interrupt line 2 */
+#define EXTI_LINE3  ((uint32_t)0x00008) /*!< External interrupt line 3 */
+#define EXTI_LINE4  ((uint32_t)0x00010) /*!< External interrupt line 4 */
+#define EXTI_LINE5  ((uint32_t)0x00020) /*!< External interrupt line 5 */
+#define EXTI_LINE6  ((uint32_t)0x00040) /*!< External interrupt line 6 */
+#define EXTI_LINE7  ((uint32_t)0x00080) /*!< External interrupt line 7 */
+#define EXTI_LINE8  ((uint32_t)0x00100) /*!< External interrupt line 8 */
+#define EXTI_LINE9  ((uint32_t)0x00200) /*!< External interrupt line 9 */
+#define EXTI_LINE10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
+#define EXTI_LINE11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
+#define EXTI_LINE12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
+#define EXTI_LINE13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
+#define EXTI_LINE14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
+#define EXTI_LINE15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
+#define EXTI_LINE16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the USB Device/USB OTG FS Wakeup from suspend event */
+#define EXTI_LINE18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the RTC Alarm event */
+#define EXTI_LINE19 ((uint32_t)0x80000)  /*!< External interrupt line 19 Connected to the RTC Time stamp event */
+#define EXTI_LINE20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+#define EXTI_LINE21 ((uint32_t)0x200000) /*!< External interrupt line 21 Connected to the COMP1 Global interrupt */
+#define EXTI_LINE22 ((uint32_t)0x400000) /*!< External interrupt line 22 Connected to the COMP2 Global interrupt */
+#define EXTI_LINE23 ((uint32_t)0x800000) /*!< External interrupt line 23 Connected to the LPUART Global interrupt */
+#define EXTI_LINE24 ((uint32_t)0x1000000) /*!< External interrupt line 24 Connected to the LPTIM Global interrupt */
+#define EXTI_LINE25 ((uint32_t)0x2000000) /*!< External interrupt line 25 Connected to the TSC Global interrupt */
+
+
+
+
+
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xF0000000) == 0x00) && ((LINE) != (uint16_t)0x00))
+#define IS_GET_EXTI_LINE(LINE)                                                                                         \
+    (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)              \
+     || ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)           \
+     || ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11)         \
+     || ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15)       \
+     || ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19)       \
+     || ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23)         \
+     || ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25))
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_TSSEL_Line
+ * @{
+ */
+#define EXTI_TSSEL_LINE_MASK ((uint32_t)0x00000)
+#define EXTI_TSSEL_LINE0     ((uint32_t)0x00000) /*!< External interrupt line 0 */
+#define EXTI_TSSEL_LINE1     ((uint32_t)0x00001) /*!< External interrupt line 1 */
+#define EXTI_TSSEL_LINE2     ((uint32_t)0x00002) /*!< External interrupt line 2 */
+#define EXTI_TSSEL_LINE3     ((uint32_t)0x00003) /*!< External interrupt line 3 */
+#define EXTI_TSSEL_LINE4     ((uint32_t)0x00004) /*!< External interrupt line 4 */
+#define EXTI_TSSEL_LINE5     ((uint32_t)0x00005) /*!< External interrupt line 5 */
+#define EXTI_TSSEL_LINE6     ((uint32_t)0x00006) /*!< External interrupt line 6 */
+#define EXTI_TSSEL_LINE7     ((uint32_t)0x00007) /*!< External interrupt line 7 */
+#define EXTI_TSSEL_LINE8     ((uint32_t)0x00008) /*!< External interrupt line 8 */
+#define EXTI_TSSEL_LINE9     ((uint32_t)0x00009) /*!< External interrupt line 9 */
+#define EXTI_TSSEL_LINE10    ((uint32_t)0x0000A) /*!< External interrupt line 10 */
+#define EXTI_TSSEL_LINE11    ((uint32_t)0x0000B) /*!< External interrupt line 11 */
+#define EXTI_TSSEL_LINE12    ((uint32_t)0x0000C) /*!< External interrupt line 12 */
+#define EXTI_TSSEL_LINE13    ((uint32_t)0x0000D) /*!< External interrupt line 13 */
+#define EXTI_TSSEL_LINE14    ((uint32_t)0x0000E) /*!< External interrupt line 14 */
+#define EXTI_TSSEL_LINE15    ((uint32_t)0x0000F) /*!< External interrupt line 15 */
+
+#define IS_EXTI_TSSEL_LINE(LINE)                                                                                       \
+    (((LINE) == EXTI_TSSEL_LINE0) || ((LINE) == EXTI_TSSEL_LINE1) || ((LINE) == EXTI_TSSEL_LINE2)                      \
+     || ((LINE) == EXTI_TSSEL_LINE3) || ((LINE) == EXTI_TSSEL_LINE4) || ((LINE) == EXTI_TSSEL_LINE5)                   \
+     || ((LINE) == EXTI_TSSEL_LINE6) || ((LINE) == EXTI_TSSEL_LINE7) || ((LINE) == EXTI_TSSEL_LINE8)                   \
+     || ((LINE) == EXTI_TSSEL_LINE9) || ((LINE) == EXTI_TSSEL_LINE10) || ((LINE) == EXTI_TSSEL_LINE11)                 \
+     || ((LINE) == EXTI_TSSEL_LINE12) || ((LINE) == EXTI_TSSEL_LINE13) || ((LINE) == EXTI_TSSEL_LINE14)                \
+     || ((LINE) == EXTI_TSSEL_LINE15))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+void EXTI_DeInit(void);
+void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct);
+void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct);
+void EXTI_TriggerSWInt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line);
+void EXTI_ClrStatusFlag(uint32_t EXTI_Line);
+INTStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClrITPendBit(uint32_t EXTI_Line);
+void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_EXTI_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_flash.h

@@ -0,0 +1,513 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_flash.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_FLASH_H__
+#define __N32G43X_FLASH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief  FLASH Status
+ */
+
+typedef enum
+{
+    FLASH_BUSY = 1,
+    FLASH_RESERVED,
+    FLASH_ERR_PG,
+    FLASH_ERR_PV,
+    FLASH_ERR_WRP,
+    FLASH_COMPL,
+    FLASH_ERR_EV,
+    FLASH_ERR_RDP2,
+    FLASH_ERR_ADD,
+    FLASH_TIMEOUT
+} FLASH_STS;
+
+/**
+ * @brief  FLASH_SMPSEL
+ */
+
+typedef enum
+{
+    FLASH_SMP1 = 0,
+    FLASH_SMP2
+} FLASH_SMPSEL;
+
+/**
+ * @brief  FLASH_HSICLOCK
+ */
+
+typedef enum
+{
+    FLASH_HSICLOCK_ENABLE = 0,
+    FLASH_HSICLOCK_DISABLE
+} FLASH_HSICLOCK;
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Flash_Latency
+ * @{
+ */
+
+#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
+#define FLASH_LATENCY_3 ((uint32_t)0x00000003) /*!< FLASH Three Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY)                                                                                      \
+    (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2)                \
+     || ((LATENCY) == FLASH_LATENCY_3))
+/**
+ * @}
+ */
+
+/** @addtogroup Prefetch_Buffer_Enable_Disable
+ * @{
+ */
+
+#define FLASH_PrefetchBuf_EN              ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuf_DIS             ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUF_STATE(STATE) (((STATE) == FLASH_PrefetchBuf_EN) || ((STATE) == FLASH_PrefetchBuf_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup iCache_Enable_Disable
+ * @{
+ */
+
+#define FLASH_iCache_EN              ((uint32_t)0x00000080) /*!< FLASH iCache Enable */
+#define FLASH_iCache_DIS             ((uint32_t)0x00000000) /*!< FLASH iCache Disable */
+#define IS_FLASH_ICACHE_STATE(STATE) (((STATE) == FLASH_iCache_EN) || ((STATE) == FLASH_iCache_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup Low Voltage Mode
+ * @{
+ */
+
+#define FLASH_LVM_EN              ((uint32_t)0x00000200) /*!< FLASH Low Voltage Mode Enable */
+#define FLASH_LVM_DIS             ((uint32_t)0x00000000) /*!< FLASH Low Voltage Mode Disable */
+#define IS_FLASH_LVM(STATE)       (((STATE) == FLASH_LVM_EN) || ((STATE) == FLASH_LVM_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH Sleep Mode
+ * @{
+ */
+
+#define FLASH_SLM_EN              ((uint32_t)0x00000800) /*!< FLASH Sleep Mode Enable */
+#define FLASH_SLM_DIS             ((uint32_t)0x00000000) /*!< FLASH Sleep Mode Disable */
+#define IS_FLASH_SLM(STATE)       (((STATE) == FLASH_SLM_EN) || ((STATE) == FLASH_SLM_DIS))
+/**
+ * @}
+ */
+
+/** @addtogroup SMPSEL_SMP1_SMP2
+ * @{
+ */
+
+#define FLASH_SMPSEL_SMP1            ((uint32_t)0x00000000) /*!< FLASH SMPSEL SMP1 */
+#define FLASH_SMPSEL_SMP2            ((uint32_t)0x00000100) /*!< FLASH SMPSEL SMP2 */
+#define IS_FLASH_SMPSEL_STATE(STATE) (((STATE) == FLASH_SMPSEL_SMP1) || ((STATE) == FLASH_SMPSEL_SMP2))
+/**
+ * @}
+ */
+
+/* Values to be used with N32G43x devices */
+#define FLASH_WRP_Pages0to1                                                                                           \
+    ((uint32_t)0x00000001) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 0 to 1 */
+#define FLASH_WRP_Pages2to3                                                                                           \
+    ((uint32_t)0x00000002) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 2 to 3 */
+#define FLASH_WRP_Pages4to5                                                                                           \
+    ((uint32_t)0x00000004) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 4 to 5 */
+#define FLASH_WRP_Pages6to7                                                                                           \
+    ((uint32_t)0x00000008) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 6 to 7 */
+#define FLASH_WRP_Pages8to9                                                                                           \
+    ((uint32_t)0x00000010) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 8 to 9 */
+#define FLASH_WRP_Pages10to11                                                                                         \
+    ((uint32_t)0x00000020) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 10 to 11 */
+#define FLASH_WRP_Pages12to13                                                                                         \
+    ((uint32_t)0x00000040) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 12 to 13 */
+#define FLASH_WRP_Pages14to15                                                                                         \
+    ((uint32_t)0x00000080) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 14 to 15 */
+#define FLASH_WRP_Pages16to17                                                                                         \
+    ((uint32_t)0x00000100) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 16 to 17 */
+#define FLASH_WRP_Pages18to19                                                                                         \
+    ((uint32_t)0x00000200) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 18 to 19 */
+#define FLASH_WRP_Pages20to21                                                                                         \
+    ((uint32_t)0x00000400) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 20 to 21 */
+#define FLASH_WRP_Pages22to23                                                                                         \
+    ((uint32_t)0x00000800) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 22 to 23 */
+#define FLASH_WRP_Pages24to25                                                                                         \
+    ((uint32_t)0x00001000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 24 to 25 */
+#define FLASH_WRP_Pages26to27                                                                                         \
+    ((uint32_t)0x00002000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 26 to 27 */
+#define FLASH_WRP_Pages28to29                                                                                         \
+    ((uint32_t)0x00004000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 28 to 29 */
+#define FLASH_WRP_Pages30to31                                                                                         \
+    ((uint32_t)0x00008000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 30 to 31 */
+#define FLASH_WRP_Pages32to33                                                                                         \
+    ((uint32_t)0x00010000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 32 to 33 */
+#define FLASH_WRP_Pages34to35                                                                                         \
+    ((uint32_t)0x00020000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 34 to 35 */
+#define FLASH_WRP_Pages36to37                                                                                         \
+    ((uint32_t)0x00040000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 36 to 37 */
+#define FLASH_WRP_Pages38to39                                                                                         \
+    ((uint32_t)0x00080000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 38 to 39 */
+#define FLASH_WRP_Pages40to41                                                                                         \
+    ((uint32_t)0x00100000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 40 to 41 */
+#define FLASH_WRP_Pages42to43                                                                                         \
+    ((uint32_t)0x00200000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 42 to 43 */
+#define FLASH_WRP_Pages44to45                                                                                         \
+    ((uint32_t)0x00400000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 44 to 45 */
+#define FLASH_WRP_Pages46to47                                                                                         \
+    ((uint32_t)0x00800000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 46 to 47 */
+#define FLASH_WRP_Pages48to49                                                                                         \
+    ((uint32_t)0x01000000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 48 to 49 */
+#define FLASH_WRP_Pages50to51                                                                                         \
+    ((uint32_t)0x02000000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 50 to 51 */
+#define FLASH_WRP_Pages52to53                                                                                         \
+    ((uint32_t)0x04000000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 52 to 53 */
+#define FLASH_WRP_Pages54to55                                                                                         \
+    ((uint32_t)0x08000000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 54 to 55 */
+#define FLASH_WRP_Pages56to57                                                                                         \
+    ((uint32_t)0x10000000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 56 to 57 */
+#define FLASH_WRP_Pages58to59                                                                                         \
+    ((uint32_t)0x20000000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 58 to 59 */
+#define FLASH_WRP_Pages60to61                                                                                         \
+    ((uint32_t)0x40000000) /*!< N32G43x devices:                                                                       \
+                                  Write protection of page 60 to 61 */
+#define FLASH_WRP_Pages62to63                                                                                        \
+    ((uint32_t)0x80000000) /*!< N32G43x devices:
+                                  Write protection of page 62 to 63 */
+
+#define FLASH_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+#define IS_FLASH_WRP_PAGE(PAGE) (1) //(((PAGE) <= FLASH_WRP_AllPages))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0801FFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) ((ADDRESS) == 0x1FFFF804)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_RDP1
+ * @{
+ */
+
+#define OB_RDP1_ENABLE            ((uint8_t)0x00) /*!< Enable RDP1 */
+#define OB_RDP1_DISABLE           ((uint8_t)0xA5) /*!< DISABLE RDP1 */
+#define IS_OB_RDP1_SOURCE(SOURCE) (((SOURCE) == OB_RDP1_ENABLE) || ((SOURCE) == OB_RDP1_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW                ((uint8_t)0x01) /*!< Software IWDG selected */
+#define OB_IWDG_HW                ((uint8_t)0x00) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP2_NORST             ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
+#define OB_STOP2_RST               ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP2_SOURCE(SOURCE) (((SOURCE) == OB_STOP2_NORST) || ((SOURCE) == OB_STOP2_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NORST             ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST               ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nRST_PD
+ * @{
+ */
+
+#define OB_PD_NORST                ((uint8_t)0x08) /*!< No reset generated when entering in PowerDown */
+#define OB_PD_RST                  ((uint8_t)0x00) /*!< Reset generated when entering in PowerDown */
+#define IS_OB_PD_SOURCE(SOURCE)    (((SOURCE) == OB_PD_NORST) || ((SOURCE) == OB_PD_RST))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_RDP2
+ * @{
+ */
+
+#define OB_RDP2_ENABLE            ((uint8_t)0x33) /*!< Enable RDP2 */
+#define OB_RDP2_DISABLE           ((uint8_t)0x00) /*!< Disable RDP2 */
+#define IS_OB_RDP2_SOURCE(SOURCE) (((SOURCE) == OB_RDP2_ENABLE) || ((SOURCE) == OB_RDP2_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nBOOT0
+ * @{
+ */
+
+#define OB2_NBOOT0_SET                ((uint8_t)0x01) /*!< Set nBOOT0 */
+#define OB2_NBOOT0_CLR                ((uint8_t)0x00) /*!< Clear nBOOT0 */
+#define IS_OB2_NBOOT0_SOURCE(SOURCE)  (((SOURCE) == OB2_NBOOT0_SET) || ((SOURCE) == OB2_NBOOT0_CLR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nBOOT1
+ * @{
+ */
+
+#define OB2_NBOOT1_SET                ((uint8_t)0x02) /*!< Set nBOOT1 */
+#define OB2_NBOOT1_CLR                ((uint8_t)0x00) /*!< Clear nBOOT1 */
+#define IS_OB2_NBOOT1_SOURCE(SOURCE)  (((SOURCE) == OB2_NBOOT1_SET) || ((SOURCE) == OB2_NBOOT1_CLR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_nSWBOOT0
+ * @{
+ */
+
+#define OB2_NSWBOOT0_SET                ((uint8_t)0x04) /*!< Set nSWBOOT0 */
+#define OB2_NSWBOOT0_CLR                ((uint8_t)0x00) /*!< Clear nSWBOOT0 */
+#define IS_OB2_NSWBOOT0_SOURCE(SOURCE)  (((SOURCE) == OB2_NSWBOOT0_SET) || ((SOURCE) == OB2_NSWBOOT0_CLR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Option_Bytes_BOR_LEV
+ * @{
+ */
+
+#define OB2_BOR_LEV0                    ((uint8_t)0x00) /*!< BOR_LEV[2:0] L0 */
+#define OB2_BOR_LEV1                    ((uint8_t)0x10) /*!< BOR_LEV[2:0] L1 */
+#define OB2_BOR_LEV2                    ((uint8_t)0x20) /*!< BOR_LEV[2:0] L2 */
+#define OB2_BOR_LEV3                    ((uint8_t)0x30) /*!< BOR_LEV[2:0] L3 */
+#define OB2_BOR_LEV4                    ((uint8_t)0x40) /*!< BOR_LEV[2:0] L4 */
+#define OB2_BOR_LEV5                    ((uint8_t)0x50) /*!< BOR_LEV[2:0] L5 */
+#define OB2_BOR_LEV6                    ((uint8_t)0x60) /*!< BOR_LEV[2:0] L6 */
+#define OB2_BOR_LEV7                    ((uint8_t)0x70) /*!< BOR_LEV[2:0] L7 */
+#define IS_OB2_BOR_LEV_SOURCE(SOURCE)   (((SOURCE) == OB2_BOR_LEV0) || ((SOURCE) == OB2_BOR_LEV1)  \
+                                     || ((SOURCE) == OB2_BOR_LEV2) || ((SOURCE) == OB2_BOR_LEV3)  \
+                                     || ((SOURCE) == OB2_BOR_LEV4) || ((SOURCE) == OB2_BOR_LEV5)  \
+                                     || ((SOURCE) == OB2_BOR_LEV6) || ((SOURCE) == OB2_BOR_LEV7))
+
+
+/**
+ * @}
+ */
+/** @addtogroup FLASH_Interrupts
+ * @{
+ */
+#define FLASH_INT_ERRIE    ((uint32_t)0x00000400) /*!< PGERR WRPERR ERROR error interrupt source */
+#define FLASH_INT_FERR     ((uint32_t)0x00000800) /*!< EVERR PVERR interrupt source */
+#define FLASH_INT_EOP      ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
+
+#define IS_FLASH_INT(IT) ((((IT) & (uint32_t)0xFFFFE3FF) == 0x00000000) && (((IT) != 0x00000000)))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Flags
+ * @{
+ */
+#define FLASH_FLAG_BUSY     ((uint32_t)0x00000001) /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR    ((uint32_t)0x00000004) /*!< FLASH Program error flag */
+#define FLASH_FLAG_PVERR    ((uint32_t)0x00000008) /*!< FLASH Program Verify ERROR flag after program */
+#define FLASH_FLAG_WRPERR   ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP      ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_EVERR    ((uint32_t)0x00000040) /*!< FLASH Erase Verify ERROR flag after page erase */
+#define FLASH_FLAG_OBERR    ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF83) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)                                                                                       \
+       (((FLAG) == FLASH_FLAG_BUSY)   || ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_PVERR)                 \
+     || ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP)   || ((FLAG) == FLASH_FLAG_EVERR)                 \
+     || ((FLAG) == FLASH_FLAG_OBERR))
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_STS_CLRFLAG
+ * @{
+ */
+#define FLASH_STS_CLRFLAG   (FLASH_FLAG_PGERR | FLASH_FLAG_PVERR | FLASH_FLAG_WRPERR | FLASH_FLAG_EOP |FLASH_FLAG_EVERR)
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/*------------ Functions used for N32G43x devices -----*/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf);
+void FLASH_iCacheRST(void);
+void FLASH_iCacheCmd(uint32_t FLASH_iCache);
+void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM);
+FlagStatus FLASH_GetLowVoltageModeSTS(void);
+void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM);
+FlagStatus FLASH_GetFLASHSleepModeSTS(void);
+FLASH_HSICLOCK FLASH_ClockInit(void);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address);
+FLASH_STS FLASH_MassErase(void);
+FLASH_STS FLASH_EraseOB(void);
+FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data);
+FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages);
+FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd);
+FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void);
+FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1,    uint8_t OB_IWDG,    uint8_t OB_STOP2,
+                                    uint8_t OB_STDBY,   uint8_t OB_PD,      uint8_t OB_Data0,
+                                    uint8_t OB_Data1,   uint32_t WRP_Pages, uint8_t OB_RDP2,
+                                    uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0,
+                                    uint8_t OB2_BOR_LEV);
+FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY, uint8_t OB_PD);
+FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV);
+uint32_t FLASH_GetUserOB(void);
+uint32_t FLASH_GetWriteProtectionOB(void);
+FlagStatus FLASH_GetReadOutProtectionSTS(void);
+FlagStatus FLASH_GetReadOutProtectionL2STS(void);
+FlagStatus FLASH_GetPrefetchBufSTS(void);
+void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel);
+FLASH_SMPSEL FLASH_GetSMPSELStatus(void);
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd);
+FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_STS FLASH_GetSTS(void);
+FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_FLASH_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_gpio.h

@@ -0,0 +1,660 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_gpio.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_GPIO_H__
+#define __N32G43X_GPIO_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Types
+ * @{
+ */
+
+#define IS_GPIO_ALL_PERIPH(PERIPH)                                                                                     \
+    (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD))
+
+
+#define GPIO_GET_INDEX(PERIPH)    (((PERIPH) == (GPIOA))? 0 :\
+                                      ((PERIPH) == (GPIOB))? 1 :\
+                                      ((PERIPH) == (GPIOC))? 2 :3)
+#define GPIO_GET_PERIPH(INDEX) (((INDEX)==((uint8_t)0x00))? GPIOA :\
+                                ((INDEX)==((uint8_t)0x01))? GPIOB :\
+                                ((INDEX)==((uint8_t)0x02))? GPIOC : GPIOD )
+
+
+/**
+ * @brief  Output Maximum frequency selection
+ */
+
+typedef enum
+{
+    GPIO_Slew_Rate_High = 0,
+    GPIO_Slew_Rate_Low
+} GPIO_SpeedType;
+#define IS_GPIO_SLEW_RATE(_RATE_)                           \
+    (((_RATE_) == GPIO_Slew_Rate_High) || ((_RATE_) == GPIO_Slew_Rate_Low))
+
+/**
+ * @brief   driver strength config
+ */
+
+typedef enum
+{
+    GPIO_DC_2mA = 0x00,
+    GPIO_DC_4mA = 0x10,
+    GPIO_DC_8mA = 0x01,
+    GPIO_DC_12mA= 0x11
+}GPIO_CurrentType;
+
+#define IS_GPIO_CURRENT(CURRENT)  \
+        (((CURRENT) == GPIO_DC_2mA) ||((CURRENT) == GPIO_DC_4mA)   \
+        || ((CURRENT) == GPIO_DC_8mA)||((CURRENT) == GPIO_DC_12mA))
+/**
+ * @brief  Configuration Mode enumeration
+ */
+
+
+/** @brief GPIO_mode_define Mode definition
+  * @brief GPIO Configuration Mode
+  *    Values convention: 0xW0yz00YZ
+  *           - W  : GPIO mode or EXTI Mode
+  *           - y  : External IT or Event trigger detection
+  *           - z  : IO configuration on External IT or Event
+  *           - Y  : Output type (Push Pull or Open Drain)
+  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+  * @{
+  */
+
+typedef enum
+{
+    GPIO_Mode_Input =  0x00000000,   /*!< Input Floating Mode                   */
+    GPIO_Mode_Out_PP = 0x00000001,   /*!< Output Push Pull Mode                 */
+    GPIO_Mode_Out_OD = 0x00000011,   /*!< Output Open Drain Mode                */
+    GPIO_Mode_AF_PP =  0x00000002,   /*!< Alternate Function Push Pull Mode     */
+    GPIO_Mode_AF_OD =  0x00000012,   /*!< Alternate Function Open Drain Mode    */
+
+    GPIO_Mode_Analog = 0x00000003,   /*!< Analog Mode  */
+
+    GPIO_Mode_IT_Rising = 0x10110000,   /*!< External Interrupt Mode with Rising edge trigger detection          */
+    GPIO_Mode_IT_Falling = 0x10210000,   /*!< External Interrupt Mode with Falling edge trigger detection         */
+    GPIO_Mode_IT_Rising_Falling = 0x10310000,   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+
+    GPIO_Mode_EVT_Rising = 0x10120000,   /*!< External Event Mode with Rising edge trigger detection               */
+    GPIO_Mode_EVT_Falling = 0x10220000,   /*!< External Event Mode with Falling edge trigger detection              */
+    GPIO_Mode_EVT_Rising_Falling = 0x10320000
+}GPIO_ModeType;
+
+
+
+/**
+  * @}
+  */
+#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_Mode_Input)              ||\
+                                ((__MODE__) == GPIO_Mode_Out_PP)             ||\
+                                ((__MODE__) == GPIO_Mode_Out_OD)             ||\
+                                ((__MODE__) == GPIO_Mode_AF_PP)              ||\
+                                ((__MODE__) == GPIO_Mode_AF_OD)              ||\
+                                ((__MODE__) == GPIO_Mode_IT_Rising)          ||\
+                                ((__MODE__) == GPIO_Mode_IT_Falling)         ||\
+                                ((__MODE__) == GPIO_Mode_IT_Rising_Falling)  ||\
+                                ((__MODE__) == GPIO_Mode_EVT_Rising)         ||\
+                                ((__MODE__) == GPIO_Mode_EVT_Falling)        ||\
+                                ((__MODE__) == GPIO_Mode_EVT_Rising_Falling) ||\
+                                ((__MODE__) == GPIO_Mode_Analog))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @brief GPIO_pull_define Pull definition
+   * @brief GPIO Pull-Up or Pull-Down Activation
+   * @{
+   */
+
+typedef enum
+{
+    GPIO_No_Pull = 0x00000000,   /*!< No Pull-up or Pull-down activation  */
+    GPIO_Pull_Up = 0x00000001,  /*!< Pull-up activation                  */
+    GPIO_Pull_Down = 0x00000002   /*!< Pull-down activation                */
+}GPIO_PuPdType;
+/**
+  * @}
+  */
+
+#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_No_Pull) || ((__PULL__) == GPIO_Pull_Up) || \
+                                ((__PULL__) == GPIO_Pull_Down))
+/**
+  * @}
+  */
+
+/**
+ * @brief  GPIO Init structure definition
+ */
+
+typedef struct
+{
+    uint16_t Pin; /*!< Specifies the GPIO pins to be configured.
+                            This parameter can be any value of @ref GPIO_pins_define */
+
+    GPIO_CurrentType GPIO_Current; /*!<Driving current of the select pins>.
+                                        This paramter can be a value of @ref GPIO_CurrentType*/
+
+    GPIO_SpeedType GPIO_Slew_Rate; /*!< Specifies the speed for the selected pins.
+                                       This parameter can be a value of @ref GPIO_SpeedType */
+
+    GPIO_PuPdType GPIO_Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull_define */
+
+    GPIO_ModeType GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+                                     This parameter can be a value of @ref GPIO_ModeType */
+
+    uint32_t GPIO_Alternate;  /*!< Peripheral to be connected to the selected pins
+                            This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+} GPIO_InitType;
+
+/**
+ * @brief  Bit_SET and Bit_RESET enumeration
+ */
+
+typedef enum
+{
+    Bit_RESET = 0,
+    Bit_SET
+} Bit_OperateType;
+
+#define IS_GPIO_BIT_OPERATE(OPERATE) (((OPERATE) == Bit_RESET) || ((OPERATE) == Bit_SET))
+
+/**
+ * @}
+ */
+
+
+
+
+/** @addtogroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup GPIO_pins_define
+ * @{
+ */
+
+#define GPIO_PIN_0   ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_PIN_1   ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_PIN_2   ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_PIN_3   ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_PIN_4   ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_PIN_5   ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_PIN_6   ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_PIN_7   ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_PIN_8   ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_PIN_9   ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_PIN_10  ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_PIN_11  ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_PIN_12  ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_PIN_13  ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_PIN_14  ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_PIN_15  ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define GPIOA_PIN_AVAILABLE  ((uint16_t)0xFFFF)
+#define GPIOB_PIN_AVAILABLE  ((uint16_t)0xFFFF)
+#define GPIOC_PIN_AVAILABLE  ((uint16_t)0xFFFF)
+#define GPIOD_PIN_AVAILABLE  ((uint16_t)0xFFFF)
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PIN(PIN)                                                                                           \
+    (((PIN) == GPIO_PIN_0) || ((PIN) == GPIO_PIN_1) || ((PIN) == GPIO_PIN_2) || ((PIN) == GPIO_PIN_3)                  \
+     || ((PIN) == GPIO_PIN_4) || ((PIN) == GPIO_PIN_5) || ((PIN) == GPIO_PIN_6) || ((PIN) == GPIO_PIN_7)               \
+     || ((PIN) == GPIO_PIN_8) || ((PIN) == GPIO_PIN_9) || ((PIN) == GPIO_PIN_10) || ((PIN) == GPIO_PIN_11)             \
+     || ((PIN) == GPIO_PIN_12) || ((PIN) == GPIO_PIN_13) || ((PIN) == GPIO_PIN_14) || ((PIN) == GPIO_PIN_15))
+
+
+#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__)  \
+           ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
+            (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
+            (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
+            (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))))
+
+
+
+
+
+/**
+ * @}
+ */
+
+
+
+
+/** @addtogroup GPIO_Port_Sources
+ * @{
+ */
+
+#define GPIOA_PORT_SOURCE ((uint8_t)0x00)
+#define GPIOB_PORT_SOURCE ((uint8_t)0x01)
+#define GPIOC_PORT_SOURCE ((uint8_t)0x02)
+#define GPIOD_PORT_SOURCE ((uint8_t)0x03)
+
+#define IS_GPIO_REMAP_PORT_SOURCE(PORTSOURCE)                                                                       \
+    (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+     || ((PORTSOURCE) == GPIOD_PORT_SOURCE))
+
+
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE)                                                                       \
+    (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+     || ((PORTSOURCE) == GPIOD_PORT_SOURCE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE)                                                                           \
+    (((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
+     || ((PORTSOURCE) == GPIOD_PORT_SOURCE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Pin_sources
+ * @{
+ */
+
+#define GPIO_PIN_SOURCE0  ((uint8_t)0x00)
+#define GPIO_PIN_SOURCE1  ((uint8_t)0x01)
+#define GPIO_PIN_SOURCE2  ((uint8_t)0x02)
+#define GPIO_PIN_SOURCE3  ((uint8_t)0x03)
+#define GPIO_PIN_SOURCE4  ((uint8_t)0x04)
+#define GPIO_PIN_SOURCE5  ((uint8_t)0x05)
+#define GPIO_PIN_SOURCE6  ((uint8_t)0x06)
+#define GPIO_PIN_SOURCE7  ((uint8_t)0x07)
+#define GPIO_PIN_SOURCE8  ((uint8_t)0x08)
+#define GPIO_PIN_SOURCE9  ((uint8_t)0x09)
+#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A)
+#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B)
+#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C)
+#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D)
+#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E)
+#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE)                                                                                  \
+    (((PINSOURCE) == GPIO_PIN_SOURCE0) || ((PINSOURCE) == GPIO_PIN_SOURCE1) || ((PINSOURCE) == GPIO_PIN_SOURCE2)       \
+     || ((PINSOURCE) == GPIO_PIN_SOURCE3) || ((PINSOURCE) == GPIO_PIN_SOURCE4) || ((PINSOURCE) == GPIO_PIN_SOURCE5)    \
+     || ((PINSOURCE) == GPIO_PIN_SOURCE6) || ((PINSOURCE) == GPIO_PIN_SOURCE7) || ((PINSOURCE) == GPIO_PIN_SOURCE8)    \
+     || ((PINSOURCE) == GPIO_PIN_SOURCE9) || ((PINSOURCE) == GPIO_PIN_SOURCE10) || ((PINSOURCE) == GPIO_PIN_SOURCE11)  \
+     || ((PINSOURCE) == GPIO_PIN_SOURCE12) || ((PINSOURCE) == GPIO_PIN_SOURCE13) || ((PINSOURCE) == GPIO_PIN_SOURCE14) \
+     || ((PINSOURCE) == GPIO_PIN_SOURCE15))
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup GPIOx_Alternate_function_selection Alternate function selection
+ * @{
+ */
+
+/*
+ * Alternate function AF0
+ */
+#define GPIO_AF0_SW_JTAG        ((uint8_t)0x00)  /* SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI1           ((uint8_t)0x00)  /* SPI1 Alternate Function mapping */
+#define GPIO_AF0_LPTIM          ((uint8_t)0x00)  /* LPTIM Alternate Function mapping    */
+#define GPIO_AF0_SPI2           ((uint8_t)0x00)  /* SPI2 Alternate Function mapping     */
+#define GPIO_AF0_TIM8           ((uint8_t)0x00)  /* TIM8 Alternate Function mapping      */
+#define GPIO_AF0_USART1         ((uint8_t)0x00)  /* USART1 Alternate Function mapping    */
+#define GPIO_AF0_USART3         ((uint8_t)0x00)  /* USART3 Alternate Function mapping    */
+#define GPIO_AF0_LPUART         ((uint8_t)0x00)  /* LPUART Alternate Function mapping   */
+#define GPIO_AF0_USART2         ((uint8_t)0x00)  /* USART2 Alternate Function mapping     */
+
+/**
+ *
+ */
+
+/*
+ * Alternate function AF1
+ */
+#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping     */
+#define GPIO_AF1_USART1        ((uint8_t)0x01)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF1_I2C2          ((uint8_t)0x01)  /* I2C2 Alternate Function mapping    */
+#define GPIO_AF1_CAN           ((uint8_t)0x01)  /* CAN Alternate Function mapping      */
+#define GPIO_AF1_SPI2          ((uint8_t)0x01)  /* SPI2 Alternate Function mapping     */
+#define GPIO_AF1_TIM9          ((uint8_t)0x01)  /* TIM9 Alternate Function mapping     */
+#define GPIO_AF1_SPI1          ((uint8_t)0x01)  /* SPI1 Alternate Function mapping    */
+#define GPIO_AF1_I2C1          ((uint8_t)0x01)  /* I2C1 Alternate Function mapping      */
+#define GPIO_AF1               ((uint8_t)0x01)  /* test Alternate Function mapping      */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF2
+ */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping     */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping     */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_LPTIM         ((uint8_t)0x02)  /* LPTIM Alternate Function mapping   */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping  */
+#define GPIO_AF2_LPUART        ((uint8_t)0x02)  /* LPUART Alternate Function mapping      */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF3
+ */
+#define GPIO_AF3_EVENTOUT      ((uint8_t)0x03)  /* EVENTOUT Alternate Function mapping */
+
+/**
+ *
+ */
+
+/*
+ * Alternate function AF4
+ */
+#define GPIO_AF4_USART2          ((uint8_t)0x04)  /* USART2 Alternate Function mapping  */
+#define GPIO_AF4_LPUART          ((uint8_t)0x04)  /* LPUART Alternate Function mapping */
+#define GPIO_AF4_USART1          ((uint8_t)0x04)  /* USART1 Alternate Function mapping  */
+#define GPIO_AF4_TIM3            ((uint8_t)0x04)  /* TIM3 Alternate Function mapping*/
+#define GPIO_AF4_SPI1            ((uint8_t)0x04)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF4_I2C1            ((uint8_t)0x04)  /* I2C1 Alternate Function mapping    */
+#define GPIO_AF4_USART3          ((uint8_t)0x04)  /* USART3 Alternate Function mapping    */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF5
+ */
+#define GPIO_AF5_TIM2          ((uint8_t)0x05)  /* TIM2 Alternate Function mapping     */
+#define GPIO_AF5_TIM1          ((uint8_t)0x05)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping    */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF5_I2C2          ((uint8_t)0x05)  /* I2C2 Alternate Function mapping     */
+#define GPIO_AF5_LPTIM         ((uint8_t)0x05)  /* LPTIM Alternate Function mapping     */
+#define GPIO_AF5_CAN           ((uint8_t)0x05)  /* CAN Alternate Function mapping    */
+#define GPIO_AF5_USART3        ((uint8_t)0x05)  /* USART3 Alternate Function mapping    */
+
+/**
+ *
+ */
+
+/*
+ * Alternate function AF6
+ */
+
+#define GPIO_AF6_USART2        ((uint8_t)0x06)  /* USART2 Alternate Function mapping   */
+#define GPIO_AF6_LPUART        ((uint8_t)0x06)  /* LPUART Alternate Function mapping  */
+#define GPIO_AF6_TIM5          ((uint8_t)0x06)  /* TIM5 Alternate Function mapping */
+#define GPIO_AF6_TIM8          ((uint8_t)0x06)  /* TIM8 Alternate Function mapping     */
+#define GPIO_AF6_I2C2          ((uint8_t)0x06)  /* I2C2 Alternate Function mapping     */
+#define GPIO_AF6_UART4         ((uint8_t)0x06)  /* UART4 Alternate Function mapping   */
+#define GPIO_AF6_UART5         ((uint8_t)0x06)  /* UART5 Alternate Function mapping    */
+#define GPIO_AF6_SPI1          ((uint8_t)0x06)  /* SPI1 Alternate Function mapping    */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF7
+ */
+#define GPIO_AF7_COMP1        ((uint8_t)0x07)  /* COMP1 Alternate Function mapping     */
+#define GPIO_AF7_COMP2        ((uint8_t)0x07)  /* COMP2 Alternate Function mapping     */
+#define GPIO_AF7_I2C1         ((uint8_t)0x07)  /* I2C1 Alternate Function mapping      */
+#define GPIO_AF7_TIM8         ((uint8_t)0x07)  /* TIM8 Alternate Function mapping   */
+#define GPIO_AF7_TIM5         ((uint8_t)0x07)  /* TIM5 Alternate Function mapping     */
+#define GPIO_AF7_LPUART       ((uint8_t)0x07)  /* LPUART Alternate Function mapping     */
+#define GPIO_AF7_UART5        ((uint8_t)0x07)  /* UART5 Alternate Function mapping      */
+#define GPIO_AF7_TIM1         ((uint8_t)0x07)  /* TIM1 Alternate Function mapping   */
+#define GPIO_AF7_USART3       ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+
+/**
+  *
+  */
+
+ /*
+ * Alternate function AF8
+ */
+#define GPIO_AF8_COMP1        ((uint8_t)0x08)  /* COMP1 Alternate Function mapping     */
+#define GPIO_AF8_COMP2        ((uint8_t)0x08)  /* COMP2 Alternate Function mapping     */
+#define GPIO_AF8_LPTIM        ((uint8_t)0x08)  /* LPTIM Alternate Function mapping      */
+#define GPIO_AF8_MCO          ((uint8_t)0x08)  /* MCO   Alternate Function mapping      */
+
+/**
+  *
+  */
+
+ /*
+ * Alternate function AF9
+ */
+#define GPIO_AF9_RTC          ((uint8_t)0x09)  /* RTC Alternate Function mapping     */
+#define GPIO_AF9_COMP1        ((uint8_t)0x09)  /* COMP1 Alternate Function mapping     */
+#define GPIO_AF9_TSC          ((uint8_t)0x09)  /* COMP1 Alternate Function mapping     */
+
+/**
+  *
+  */
+
+ /*
+ * Alternate function AF15
+ */
+#define GPIO_AF15         ((uint8_t)0x0F)  /* NON Alternate Function mapping   */
+
+#define GPIO_NO_AF        (GPIO_AF15)
+/**
+  * @}
+  */
+
+
+/**
+ *  IS_GPIO_AF macro definition
+ */
+
+#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF1_TIM5)      || \
+                            ((__AF__) == GPIO_AF0_LPTIM)     || ((__AF__) == GPIO_AF1_USART1)     || \
+                            ((__AF__) == GPIO_AF0_SPI2)    || ((__AF__) == GPIO_AF1_I2C2)     || \
+                            ((__AF__) == GPIO_AF0_TIM8)      || ((__AF__) == GPIO_AF1_CAN)    || \
+                            ((__AF__) == GPIO_AF0_USART1)    || ((__AF__) == GPIO_AF1_SPI2)     || \
+                            ((__AF__) == GPIO_AF0_USART3)    || ((__AF__) == GPIO_AF1_TIM9)     || \
+                            ((__AF__) == GPIO_AF0_LPUART)   || ((__AF__) == GPIO_AF1_SPI1)      || \
+                            ((__AF__) == GPIO_AF0_USART2)     || ((__AF__) == GPIO_AF1_I2C1) || \
+                            ((__AF__) == GPIO_AF3_EVENTOUT)   || ((__AF__) == GPIO_AF2_TIM2)   || \
+                            ((__AF__) == GPIO_AF5_TIM2)     || ((__AF__) == GPIO_AF2_TIM3)  || \
+                            ((__AF__) == GPIO_AF5_TIM1)  || ((__AF__) == GPIO_AF2_TIM1)      || \
+                            ((__AF__) == GPIO_AF5_SPI1)   || ((__AF__) == GPIO_AF2_LPTIM)      || \
+                            ((__AF__) == GPIO_AF5_SPI2)      || ((__AF__) == GPIO_AF2_TIM4)     || \
+                            ((__AF__) == GPIO_AF5_I2C2)     || ((__AF__) == GPIO_AF2_LPUART)   || \
+                            ((__AF__) == GPIO_AF5_LPTIM)      || ((__AF__) == GPIO_AF4_USART2)     || \
+                            ((__AF__) == GPIO_AF5_CAN) || ((__AF__) == GPIO_AF4_LPUART)   || \
+                            ((__AF__) == GPIO_AF5_USART3)     || ((__AF__) == GPIO_AF4_USART1)  || \
+                            ((__AF__) == GPIO_AF6_USART2)    || ((__AF__) == GPIO_AF4_TIM3) || \
+                            ((__AF__) == GPIO_AF6_LPUART)     || ((__AF__) == GPIO_AF4_SPI1)   || \
+                            ((__AF__) == GPIO_AF6_TIM5)   || ((__AF__) == GPIO_AF4_I2C1)    || \
+                            ((__AF__) == GPIO_AF6_TIM8)    || ((__AF__) == GPIO_AF4_USART3)     || \
+                            ((__AF__) == GPIO_AF6_I2C2)     || ((__AF__) == GPIO_AF7_COMP1)     || \
+                            ((__AF__) == GPIO_AF6_UART4)     || ((__AF__) == GPIO_AF7_COMP2)   || \
+                            ((__AF__) == GPIO_AF6_UART5)    || ((__AF__) == GPIO_AF7_I2C1)  || \
+                            ((__AF__) == GPIO_AF6_SPI1)    || ((__AF__) == GPIO_AF7_TIM8)     || \
+                            ((__AF__) == GPIO_AF8_COMP1)     || ((__AF__) == GPIO_AF7_TIM5) || \
+                            ((__AF__) == GPIO_AF8_COMP2)  || ((__AF__) == GPIO_AF7_LPUART)     || \
+                            ((__AF__) == GPIO_AF8_LPTIM)   || ((__AF__) == GPIO_AF7_UART5)       || \
+                            ((__AF__) == GPIO_AF9_RTC)   || ((__AF__) == GPIO_AF7_TIM1)   || \
+                            ((__AF__) == GPIO_AF9_COMP1)     || ((__AF__) == GPIO_AF7_USART3)  || \
+                            ((__AF__) == GPIO_AF15)  || ((__AF__) == GPIO_NO_AF))
+
+
+
+
+
+/**
+ * @}
+ */
+/** @defgroup GPIO Alternate function remaping
+ * @{
+ */
+#define AFIO_SPI1_NSS   (11U)
+#define AFIO_SPI2_NSS   (10U)
+
+#define IS_AFIO_SPIX(_PARAMETER_) \
+            (((_PARAMETER_) == AFIO_SPI1_NSS) ||((_PARAMETER_) == AFIO_SPI2_NSS))
+typedef enum
+{
+    AFIO_SPI_NSS_High_IMPEDANCE = 0U,
+    AFIO_SPI_NSS_High_LEVEL = 1U
+}AFIO_SPI_NSSType;
+
+#define IS_AFIO_SPI_NSS(_PARAMETER_) \
+            (((_PARAMETER_) == AFIO_SPI_NSS_High_IMPEDANCE) ||((_PARAMETER_) == AFIO_SPI_NSS_High_LEVEL))
+
+
+typedef enum
+{
+    AFIO_ADC_ETRI= 9U,
+    AFIO_ADC_ETRR = 8U
+}AFIO_ADC_ETRType;
+
+typedef enum
+{
+    AFIO_ADC_TRIG_EXTI_0 = 0x0U,
+    AFIO_ADC_TRIG_EXTI_1 = 0x01U,
+    AFIO_ADC_TRIG_EXTI_2,
+    AFIO_ADC_TRIG_EXTI_3,
+    AFIO_ADC_TRIG_EXTI_4,
+    AFIO_ADC_TRIG_EXTI_5,
+    AFIO_ADC_TRIG_EXTI_6,
+    AFIO_ADC_TRIG_EXTI_7,
+    AFIO_ADC_TRIG_EXTI_8,
+    AFIO_ADC_TRIG_EXTI_9,
+    AFIO_ADC_TRIG_EXTI_10,
+    AFIO_ADC_TRIG_EXTI_11,
+    AFIO_ADC_TRIG_EXTI_12,
+    AFIO_ADC_TRIG_EXTI_13,
+    AFIO_ADC_TRIG_EXTI_14,
+    AFIO_ADC_TRIG_EXTI_15,
+    AFIO_ADC_TRIG_TIM8_CH3,
+    AFIO_ADC_TRIG_TIM8_CH4
+}AFIO_ADC_Trig_RemapType;
+
+#define IS_AFIO_ADC_ETR(_PARAMETER_) \
+            (((_PARAMETER_) == AFIO_ADC_ETRI) ||((_PARAMETER_) == AFIO_ADC_ETRR))
+#define IS_AFIO_ADC_ETRI(_PARAMETER_) \
+            (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH4))
+
+#define IS_AFIO_ADC_ETRR(_PARAMETER_) \
+            (((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_0) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_1)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_2) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_3)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_4) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_5)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_6) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_7)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_8) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_9)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_10) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_11)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_12) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_13) ||\
+            ((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_14) ||((_PARAMETER_) == AFIO_ADC_TRIG_EXTI_15)|| \
+            ((_PARAMETER_) == AFIO_ADC_TRIG_TIM8_CH3))
+
+ /**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+void GPIO_DeInit(GPIO_Module* GPIOx);
+void GPIO_AFIOInitDefault(void);
+void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct);
+void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
+uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
+uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx);
+void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd);
+void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal);
+void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin);
+void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource);
+void GPIO_CtrlEventOutput(FunctionalState Cmd);
+void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction);
+void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource);
+
+void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType);
+void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_GPIO_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_i2c.h

@@ -0,0 +1,672 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_i2c.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_I2C_H__
+#define __N32G43X_I2C_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief  I2C Init structure definition
+ */
+
+typedef struct
+{
+    uint32_t ClkSpeed; /*!< Specifies the clock frequency.
+                                  This parameter must be set to a value lower than 400kHz */
+
+    uint16_t BusMode; /*!< Specifies the I2C mode.
+                            This parameter can be a value of @ref I2C_BusMode */
+
+    uint16_t FmDutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+                                 This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+    uint16_t OwnAddr1; /*!< Specifies the first device own address.
+                                   This parameter can be a 7-bit or 10-bit address. */
+
+    uint16_t AckEnable; /*!< Enables or disables the acknowledgement.
+                           This parameter can be a value of @ref I2C_acknowledgement */
+
+    uint16_t AddrMode; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                           This parameter can be a value of @ref I2C_acknowledged_address */
+} I2C_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2))
+/** @addtogroup I2C_BusMode
+ * @{
+ */
+
+#define I2C_BUSMODE_I2C       ((uint16_t)0x0000)
+#define I2C_BUSMODE_SMBDEVICE ((uint16_t)0x0002)
+#define I2C_BUSMODE_SMBHOST   ((uint16_t)0x000A)
+#define IS_I2C_BUS_MODE(MODE)                                                                                          \
+    (((MODE) == I2C_BUSMODE_I2C) || ((MODE) == I2C_BUSMODE_SMBDEVICE) || ((MODE) == I2C_BUSMODE_SMBHOST))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_duty_cycle_in_fast_mode
+ * @{
+ */
+
+#define I2C_FMDUTYCYCLE_16_9        ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_FMDUTYCYCLE_2           ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_FM_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_FMDUTYCYCLE_16_9) || ((CYCLE) == I2C_FMDUTYCYCLE_2))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_acknowledgement
+ * @{
+ */
+
+#define I2C_ACKEN               ((uint16_t)0x0400)
+#define I2C_ACKDIS              ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_ACKEN) || ((STATE) == I2C_ACKDIS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_transfer_direction
+ * @{
+ */
+
+#define I2C_DIRECTION_SEND          ((uint8_t)0x00)
+#define I2C_DIRECTION_RECV          ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_DIRECTION_SEND) || ((DIRECTION) == I2C_DIRECTION_RECV))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_acknowledged_address
+ * @{
+ */
+
+#define I2C_ADDR_MODE_7BIT        ((uint16_t)0x4000)
+#define I2C_ADDR_MODE_10BIT       ((uint16_t)0xC000)
+#define IS_I2C_ADDR_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_MODE_7BIT) || ((ADDRESS) == I2C_ADDR_MODE_10BIT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_registers
+ * @{
+ */
+
+#define I2C_REG_CTRL1   ((uint8_t)0x00)
+#define I2C_REG_CTRL2   ((uint8_t)0x04)
+#define I2C_REG_OADDR1  ((uint8_t)0x08)
+#define I2C_REG_OADDR2  ((uint8_t)0x0C)
+#define I2C_REG_DAT     ((uint8_t)0x10)
+#define I2C_REG_STS1    ((uint8_t)0x14)
+#define I2C_REG_STS2    ((uint8_t)0x18)
+#define I2C_REG_CLKCTRL ((uint8_t)0x1C)
+#define I2C_REG_TMRISE  ((uint8_t)0x20)
+#define IS_I2C_REG(REGISTER)                                                                                           \
+    (((REGISTER) == I2C_REG_CTRL1) || ((REGISTER) == I2C_REG_CTRL2) || ((REGISTER) == I2C_REG_OADDR1)                  \
+     || ((REGISTER) == I2C_REG_OADDR2) || ((REGISTER) == I2C_REG_DAT) || ((REGISTER) == I2C_REG_STS1)                  \
+     || ((REGISTER) == I2C_REG_STS2) || ((REGISTER) == I2C_REG_CLKCTRL) || ((REGISTER) == I2C_REG_TMRISE))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_SMBus_alert_pin_level
+ * @{
+ */
+
+#define I2C_SMBALERT_LOW        ((uint16_t)0x2000)
+#define I2C_SMBALERT_HIGH       ((uint16_t)0xDFFF)
+#define IS_I2C_SMB_ALERT(ALERT) (((ALERT) == I2C_SMBALERT_LOW) || ((ALERT) == I2C_SMBALERT_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_PEC_position
+ * @{
+ */
+
+#define I2C_PEC_POS_NEXT         ((uint16_t)0x0800)
+#define I2C_PEC_POS_CURRENT      ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POS(POSITION) (((POSITION) == I2C_PEC_POS_NEXT) || ((POSITION) == I2C_PEC_POS_CURRENT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_NCAK_position
+ * @{
+ */
+
+#define I2C_NACK_POS_NEXT         ((uint16_t)0x0800)
+#define I2C_NACK_POS_CURRENT      ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POS(POSITION) (((POSITION) == I2C_NACK_POS_NEXT) || ((POSITION) == I2C_NACK_POS_CURRENT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_INT_BUF        ((uint16_t)0x0400)
+#define I2C_INT_EVENT      ((uint16_t)0x0200)
+#define I2C_INT_ERR        ((uint16_t)0x0100)
+#define IS_I2C_CFG_INT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_INT_SMBALERT ((uint32_t)0x01008000)
+#define I2C_INT_TIMOUT   ((uint32_t)0x01004000)
+#define I2C_INT_PECERR   ((uint32_t)0x01001000)
+#define I2C_INT_OVERRUN  ((uint32_t)0x01000800)
+#define I2C_INT_ACKFAIL  ((uint32_t)0x01000400)
+#define I2C_INT_ARLOST   ((uint32_t)0x01000200)
+#define I2C_INT_BUSERR   ((uint32_t)0x01000100)
+#define I2C_INT_TXDATE   ((uint32_t)0x06000080)
+#define I2C_INT_RXDATNE  ((uint32_t)0x06000040)
+#define I2C_INT_STOPF    ((uint32_t)0x02000010)
+#define I2C_INT_ADDR10F  ((uint32_t)0x02000008)
+#define I2C_INT_BYTEF    ((uint32_t)0x02000004)
+#define I2C_INT_ADDRF    ((uint32_t)0x02000002)
+#define I2C_INT_STARTBF  ((uint32_t)0x02000001)
+
+#define IS_I2C_CLR_INT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_INT(IT)                                                                                             \
+    (((IT) == I2C_INT_SMBALERT) || ((IT) == I2C_INT_TIMOUT) || ((IT) == I2C_INT_PECERR) || ((IT) == I2C_INT_OVERRUN)   \
+     || ((IT) == I2C_INT_ACKFAIL) || ((IT) == I2C_INT_ARLOST) || ((IT) == I2C_INT_BUSERR) || ((IT) == I2C_INT_TXDATE)  \
+     || ((IT) == I2C_INT_RXDATNE) || ((IT) == I2C_INT_STOPF) || ((IT) == I2C_INT_ADDR10F) || ((IT) == I2C_INT_BYTEF)   \
+     || ((IT) == I2C_INT_ADDRF) || ((IT) == I2C_INT_STARTBF))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_flags_definition
+ * @{
+ */
+
+/**
+ * @brief  STS2 register flags
+ */
+
+#define I2C_FLAG_DUALFLAG  ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHADDR  ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDADDR  ((uint32_t)0x00200000)
+#define I2C_FLAG_GCALLADDR ((uint32_t)0x00100000)
+#define I2C_FLAG_TRF       ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY      ((uint32_t)0x00020000)
+#define I2C_FLAG_MSMODE    ((uint32_t)0x00010000)
+
+/**
+ * @brief  STS1 register flags
+ */
+
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMOUT   ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR   ((uint32_t)0x10001000)
+#define I2C_FLAG_OVERRUN  ((uint32_t)0x10000800)
+#define I2C_FLAG_ACKFAIL  ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLOST   ((uint32_t)0x10000200)
+#define I2C_FLAG_BUSERR   ((uint32_t)0x10000100)
+#define I2C_FLAG_TXDATE   ((uint32_t)0x10000080)
+#define I2C_FLAG_RXDATNE  ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF    ((uint32_t)0x10000010)
+#define I2C_FLAG_ADDR10F  ((uint32_t)0x10000008)
+#define I2C_FLAG_BYTEF    ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDRF    ((uint32_t)0x10000002)
+#define I2C_FLAG_STARTBF  ((uint32_t)0x10000001)
+
+#define IS_I2C_CLR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG)                                                                                          \
+    (((FLAG) == I2C_FLAG_DUALFLAG) || ((FLAG) == I2C_FLAG_SMBHADDR) || ((FLAG) == I2C_FLAG_SMBDADDR)                   \
+     || ((FLAG) == I2C_FLAG_GCALLADDR) || ((FLAG) == I2C_FLAG_TRF) || ((FLAG) == I2C_FLAG_BUSY)                        \
+     || ((FLAG) == I2C_FLAG_MSMODE) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMOUT)                    \
+     || ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVERRUN) || ((FLAG) == I2C_FLAG_ACKFAIL)                    \
+     || ((FLAG) == I2C_FLAG_ARLOST) || ((FLAG) == I2C_FLAG_BUSERR) || ((FLAG) == I2C_FLAG_TXDATE)                      \
+     || ((FLAG) == I2C_FLAG_RXDATNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADDR10F)                     \
+     || ((FLAG) == I2C_FLAG_BYTEF) || ((FLAG) == I2C_FLAG_ADDRF) || ((FLAG) == I2C_FLAG_STARTBF))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Events
+ * @{
+ */
+
+/*========================================
+
+                     I2C Master Events (Events grouped in order of communication)
+                                                        ==========================================*/
+/**
+ * @brief  Communication start
+ *
+ * After sending the START condition (I2C_GenerateStart() function) the master
+ * has to wait for this event. It means that the Start condition has been correctly
+ * released on the I2C bus (the bus is free, no other devices is communicating).
+ *
+ */
+/* Master mode */
+#define I2C_ROLE_MASTER ((uint32_t)0x00010000) /* MSMODE */
+/* --EV5 */
+#define I2C_EVT_MASTER_MODE_FLAG ((uint32_t)0x00030001) /* BUSY, MSMODE and SB flag */
+
+/**
+ * @brief  Address Acknowledge
+ *
+ * After checking on EV5 (start condition correctly released on the bus), the
+ * master sends the address of the slave(s) with which it will communicate
+ * (I2C_SendAddr7bit() function, it also determines the direction of the communication:
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
+ * his address. If an acknowledge is sent on the bus, one of the following events will
+ * be set:
+ *
+ *  1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG
+ *     event is set.
+ *
+ *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG
+ *     is set
+ *
+ *  3) In case of 10-Bit addressing mode, the master (just after generating the START
+ *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
+ *  function). Then master should wait on EV9. It means that the 10-bit addressing
+ *  header has been correctly sent on the bus. Then master should send the second part of
+ *  the 10-bit address (LSB) using the function I2C_SendAddr7bit(). Then master
+ *  should wait for event EV6.
+ *
+ */
+
+/* --EV6 */
+#define I2C_EVT_MASTER_TXMODE_FLAG ((uint32_t)0x00070082) /* BUSY, MSMODE, ADDRF, TXDATE and TRF flags */
+#define I2C_EVT_MASTER_RXMODE_FLAG ((uint32_t)0x00030002) /* BUSY, MSMODE and ADDRF flags */
+/* --EV9 */
+#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG ((uint32_t)0x00030008) /* BUSY, MSMODE and ADDR10F flags */
+
+/**
+ * @brief Communication events
+ *
+ * If a communication is established (START condition generated and slave address
+ * acknowledged) then the master has to check on one of the following events for
+ * communication procedures:
+ *
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
+ *    the data received from the slave (I2C_RecvData() function).
+ *
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
+ *    function) then to wait on event EV8 or EV8_2.
+ *    These two events are similar:
+ *     - EV8 means that the data has been written in the data register and is
+ *       being shifted out.
+ *     - EV8_2 means that the data has been physically shifted out and output
+ *       on the bus.
+ *     In most cases, using EV8 is sufficient for the application.
+ *     Using EV8_2 leads to a slower communication but ensure more reliable test.
+ *     EV8_2 is also more suitable than EV8 for testing on the last data transmission
+ *     (before Stop condition generation).
+ *
+ *  @note In case the  user software does not guarantee that this event EV7 is
+ *  managed before the current byte end of transfer, then user may check on EV7
+ *  and BSF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)).
+ *  In this case the communication may be slower.
+ *
+ */
+
+/* Master RECEIVER mode -----------------------------*/
+/* --EV7 */
+#define I2C_EVT_MASTER_DATA_RECVD_FLAG ((uint32_t)0x00030040) /* BUSY, MSMODE and RXDATNE flags */
+/* EV7x shifter register full */
+#define I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG ((uint32_t)0x00030044) /* BUSY, MSMODE, BSF and RXDATNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVT_MASTER_DATA_SENDING ((uint32_t)0x00070080) /* TRF, BUSY, MSMODE, TXDATE flags */
+/* --EV8_2 */
+#define I2C_EVT_MASTER_DATA_SENDED ((uint32_t)0x00070084) /* TRF, BUSY, MSMODE, TXDATE and BSF flags */
+
+/*========================================
+
+                     I2C Slave Events (Events grouped in order of communication)
+                                                        ==========================================*/
+
+/**
+ * @brief  Communication start events
+ *
+ * Wait on one of these events at the start of the communication. It means that
+ * the I2C peripheral detected a Start condition on the bus (generated by master
+ * device) followed by the peripheral address. The peripheral generates an ACK
+ * condition on the bus (if the acknowledge feature is enabled through function
+ * I2C_ConfigAck()) and the events listed above are set :
+ *
+ * 1) In normal case (only one address managed by the slave), when the address
+ *   sent by the master matches the own address of the peripheral (configured by
+ *   OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
+ *   (where XXX could be TRANSMITTER or RECEIVER).
+ *
+ * 2) In case the address sent by the master matches the second address of the
+ *   peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled
+ *   by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
+ *   (where XXX could be TRANSMITTER or RECEIVER) are set.
+ *
+ * 3) In case the address sent by the master is General Call (address 0x00) and
+ *   if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall())
+ *   the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED.
+ *
+ */
+
+/* --EV1  (all the events below are variants of EV1) */
+/* 1) Case of One Single Address managed by the slave */
+#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDRF flags */
+#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED ((uint32_t)0x00060082) /* TRF, BUSY, TXDATE and ADDRF flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED ((uint32_t)0x00860080) /* DUALF, TRF, BUSY and TXDATE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+
+/**
+ * @brief  Communication events
+ *
+ * Wait on one of these events when EV1 has already been checked and:
+ *
+ * - Slave RECEIVER mode:
+ *     - EV2: When the application is expecting a data byte to be received.
+ *     - EV4: When the application is expecting the end of the communication: master
+ *       sends a stop condition and data transmission is stopped.
+ *
+ * - Slave Transmitter mode:
+ *    - EV3: When a byte has been transmitted by the slave and the application is expecting
+ *      the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and
+ *      I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be
+ *      used when the user software doesn't guarantee the EV3 is managed before the
+ *      current byte end of transfer.
+ *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission
+ *      shall end (before sending the STOP condition). In this case slave has to stop sending
+ *      data bytes and expect a Stop condition on the bus.
+ *
+ *  @note In case the  user software does not guarantee that the event EV2 is
+ *  managed before the current byte end of transfer, then user may check on EV2
+ *  and BSF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Slave RECEIVER mode --------------------------*/
+/* --EV2 */
+#define I2C_EVT_SLAVE_DATA_RECVD ((uint32_t)0x00020040) /* BUSY and RXDATNE flags */
+/* --EV2x */
+#define I2C_EVT_SLAVE_DATA_RECVD_NOBUSY ((uint32_t)0x00000040) /* no BUSY and RXDATNE flags */
+/* --EV4  */
+#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)0x00000010) /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define I2C_EVT_SLAVE_DATA_SENDED  ((uint32_t)0x00060084) /* TRF, BUSY, TXDATE and BSF flags */
+#define I2C_EVT_SLAVE_DATA_SENDING ((uint32_t)0x00060080) /* TRF, BUSY and TXDATE flags */
+/* --EV3_2 */
+#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)0x00000400) /* AF flag */
+
+/*===========================      End of Events Description           ==========================================*/
+
+#define IS_I2C_EVT(EVENT)                                                                                              \
+    (((EVENT) == I2C_EVT_SLAVE_SEND_ADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR_MATCHED)                      \
+     || ((EVENT) == I2C_EVT_SLAVE_SEND_ADDR2_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR2_MATCHED)                 \
+     || ((EVENT) == I2C_EVT_SLAVE_GCALLADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD)                          \
+     || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG))                                                    \
+     || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_DATA_SENDED)         \
+     || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG))                                                   \
+     || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_STOP_RECVD)         \
+     || ((EVENT) == I2C_EVT_MASTER_MODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_TXMODE_FLAG)                               \
+     || ((EVENT) == I2C_EVT_MASTER_RXMODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_DATA_RECVD_FLAG)                         \
+     || ((EVENT) == I2C_EVT_MASTER_DATA_SENDED) || ((EVENT) == I2C_EVT_MASTER_DATA_SENDING)                            \
+     || ((EVENT) == I2C_EVT_MASTER_MODE_ADDRESS10_FLAG) || ((EVENT) == I2C_EVT_SLAVE_ACK_MISS)                         \
+     || ((EVENT) == I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD_NOBUSY))
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_own_address1
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDR1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_clock_speed
+ * @{
+ */
+
+//#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 1000000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+void I2C_DeInit(I2C_Module* I2Cx);
+void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct);
+void I2C_InitStruct(I2C_InitType* I2C_InitStruct);
+void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address);
+void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd);
+void I2C_SendData(I2C_Module* I2Cx, uint8_t Data);
+uint8_t I2C_RecvData(I2C_Module* I2Cx);
+void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register);
+void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition);
+void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd);
+uint8_t I2C_GetPec(I2C_Module* I2Cx);
+void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd);
+void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle);
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ *                         I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ *  depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ *    Using I2C_CheckEvent() function:
+ *    It compares the status registers (STS1 and STS2) content to a given event
+ *    (can be the combination of one or more flags).
+ *    It returns SUCCESS if the current status includes the given flags
+ *    and returns ERROR if one or more flags are missing in the current status.
+ *    - When to use:
+ *      - This function is suitable for most applications as well as for startup
+ *      activity since the events are fully described in the product reference manual
+ *      (RM0008).
+ *      - It is also suitable for users who need to define their own events.
+ *    - Limitations:
+ *      - If an error occurs (ie. error flags are set besides to the monitored flags),
+ *        the I2C_CheckEvent() function may return SUCCESS despite the communication
+ *        hold or corrupted real state.
+ *        In this case, it is advised to use error interrupts to monitor the error
+ *        events and handle them in the interrupt IRQ handler.
+ *
+ *        @note
+ *        For error management, it is advised to use the following functions:
+ *          - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR).
+ *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ *            Where x is the peripheral instance (I2C1, I2C2 ...)
+ *          - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler()
+ *            in order to determine which error occurred.
+ *          - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset()
+ *            and/or I2C_GenerateStop() in order to clear the error flag and source,
+ *            and return to correct communication status.
+ *
+ *
+ *  2) Advanced state monitoring:
+ *     Using the function I2C_GetLastEvent() which returns the image of both status
+ *     registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ *     by 16 bits and concatenated to Status Register 1).
+ *     - When to use:
+ *       - This function is suitable for the same applications above but it allows to
+ *         overcome the limitations of I2C_GetFlag() function (see below).
+ *         The returned value could be compared to events already defined in the
+ *         library (n32g43x_i2c.h) or to custom values defined by user.
+ *       - This function is suitable when multiple flags are monitored at the same time.
+ *       - At the opposite of I2C_CheckEvent() function, this function allows user to
+ *         choose when an event is accepted (when all events flags are set and no
+ *         other flags are set or just when the needed flags are set like
+ *         I2C_CheckEvent() function).
+ *     - Limitations:
+ *       - User may need to define his own events.
+ *       - Same remark concerning the error management is applicable for this
+ *         function if user decides to check only regular communication flags (and
+ *         ignores error flags).
+ *
+ *
+ *  3) Flag-based state monitoring:
+ *     Using the function I2C_GetFlag() which simply returns the status of
+ *     one single flag (ie. I2C_FLAG_RXDATNE ...).
+ *     - When to use:
+ *        - This function could be used for specific applications or in debug phase.
+ *        - It is suitable when only one flag checking is needed (most I2C events
+ *          are monitored through multiple flags).
+ *     - Limitations:
+ *        - When calling this function, the Status register is accessed. Some flags are
+ *          cleared when the status register is accessed. So checking the status
+ *          of one Flag, may clear other ones.
+ *        - Function may need to be called twice or more in order to monitor one
+ *          single event.
+ *
+ */
+
+/**
+ *
+ *  1) Basic state monitoring
+ *******************************************************************************
+ */
+ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT);
+/**
+ *
+ *  2) Advanced state monitoring
+ *******************************************************************************
+ */
+uint32_t I2C_GetLastEvent(I2C_Module* I2Cx);
+/**
+ *
+ *  3) Flag-based state monitoring
+ *******************************************************************************
+ */
+FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG);
+/**
+ *
+ *******************************************************************************
+ */
+
+void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG);
+INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT);
+void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_I2C_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h

@@ -0,0 +1,145 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_iwdg.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_IWDG_H__
+#define __N32G43X_IWDG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WRITE_ENABLE     ((uint16_t)0x5555)
+#define IWDG_WRITE_DISABLE    ((uint16_t)0x0000)
+#define IS_IWDG_WRITE(ACCESS) (((ACCESS) == IWDG_WRITE_ENABLE) || ((ACCESS) == IWDG_WRITE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_prescaler
+ * @{
+ */
+
+#define IWDG_PRESCALER_DIV4   ((uint8_t)0x00)
+#define IWDG_PRESCALER_DIV8   ((uint8_t)0x01)
+#define IWDG_PRESCALER_DIV16  ((uint8_t)0x02)
+#define IWDG_PRESCALER_DIV32  ((uint8_t)0x03)
+#define IWDG_PRESCALER_DIV64  ((uint8_t)0x04)
+#define IWDG_PRESCALER_DIV128 ((uint8_t)0x05)
+#define IWDG_PRESCALER_DIV256 ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER_DIV(PRESCALER)                                                                               \
+    (((PRESCALER) == IWDG_PRESCALER_DIV4) || ((PRESCALER) == IWDG_PRESCALER_DIV8)                                      \
+     || ((PRESCALER) == IWDG_PRESCALER_DIV16) || ((PRESCALER) == IWDG_PRESCALER_DIV32)                                 \
+     || ((PRESCALER) == IWDG_PRESCALER_DIV64) || ((PRESCALER) == IWDG_PRESCALER_DIV128)                                \
+     || ((PRESCALER) == IWDG_PRESCALER_DIV256))
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Flag
+ * @{
+ */
+
+#define IWDG_PVU_FLAG          ((uint16_t)0x0001)
+#define IWDG_CRVU_FLAG         ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG)     (((FLAG) == IWDG_PVU_FLAG) || ((FLAG) == IWDG_CRVU_FLAG))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+void IWDG_WriteConfig(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler);
+void IWDG_CntReload(uint16_t Reload);
+void IWDG_ReloadKey(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_IWDG_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lptim.h

@@ -0,0 +1,427 @@
+/** ----------------------------------------------------------------------------
+ *         Nationz Technology Software Support  -  NATIONZ  -
+ * -----------------------------------------------------------------------------
+ * Copyright (c) 2022, Nationz Corporation  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Nationz's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * -----------------------------------------------------------------------------
+ */
+/** ****************************************************************************
+ * @copyright      Nationz Co.,Ltd
+ *                 Copyright (c) 2019 All Rights Reserved
+ *******************************************************************************
+ * @file     n32g43x_lptim.h
+ * @author
+ * @date
+ * @version  v1.2.0
+ * @brief
+ ******************************************************************************/
+#ifndef __n32g43x_LPTIM_H
+#define __n32g43x_LPTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "n32g43x.h"
+
+/** @addtogroup n32g43x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup LPTIM
+  * @{
+  */
+
+//#if defined (LPTIM)
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LPTIM_ES_INIT LPTIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  LPTIM Init structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;    /*!< Specifies the source of the clock used by the LPTIM instance.
+                                This parameter can be a value of @ref LPTIM_EC_CLK_SOURCE.
+
+                                This feature can be modified afterwards using unitary function @ref LPTIM_SetClockSource().*/
+
+  uint32_t Prescaler;      /*!< Specifies the prescaler division ratio.
+                                This parameter can be a value of @ref LPTIM_EC_PRESCALER.
+
+                                This feature can be modified afterwards using using unitary function @ref LPTIM_SetPrescaler().*/
+
+  uint32_t Waveform;       /*!< Specifies the waveform shape.
+                                This parameter can be a value of @ref LPTIM_EC_OUTPUT_WAVEFORM.
+
+                                This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/
+
+  uint32_t Polarity;       /*!< Specifies waveform polarity.
+                                This parameter can be a value of @ref LPTIM_EC_OUTPUT_POLARITY.
+
+                                This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/
+} LPTIM_InitType;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
+  * @{
+  */
+
+/** @defgroup LPTIM_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LPTIM_ReadReg function
+  * @{
+  */
+#define LPTIM_INTSTS_CMPM_FLAG                    LPTIM_INTSTS_CMPM      /*!< Compare match */
+#define LPTIM_INTSTS_ARRM_FLAG                    LPTIM_INTSTS_ARRM     /*!< Autoreload match */
+#define LPTIM_INTSTS_EXTRIG_FLAG                  LPTIM_INTSTS_EXTRIG    /*!< External trigger edge event */
+#define LPTIM_INTSTS_CMPUPD_FLAG                  LPTIM_INTSTS_CMPUPD     /*!< Compare register update OK */
+#define LPTIM_INTSTS_ARRUPD_FLAG                  LPTIM_INTSTS_ARRUPD    /*!< Autoreload register update OK */
+#define LPTIM_INTSTS_UP_FLAG                      LPTIM_INTSTS_UP         /*!< Counter direction change down to up */
+#define LPTIM_INTSTS_DOWN_FLAG                    LPTIM_INTSTS_DOWN       /*!< Counter direction change up to down */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_IT IT Defines
+  * @brief    IT defines which can be used with LPTIM_ReadReg and  LPTIM_WriteReg functions
+  * @{
+  */
+#define LPTIM_INTEN_CMPMIE_ENABLE                   LPTIM_INTEN_CMPMIE       /*!< Compare match Interrupt Enable */
+#define LPTIM_INTEN_ARRMIE_ENABLE                   LPTIM_INTEN_ARRMIE      /*!< Autoreload match Interrupt Enable */
+#define LPTIM_INTEN_EXTRIGIE_ENABLE                 LPTIM_INTEN_EXTRIGIE     /*!< External trigger valid edge Interrupt Enable */
+#define LPTIM_INTEN_CMPUPDIE_ENABLE                 LPTIM_INTEN_CMPUPDIE      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_INTEN_ARRUPDIE_ENABLE                 LPTIM_INTEN_ARRUPDIE     /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_INTEN_UPIE_ENABLE                     LPTIM_INTEN_UPIE          /*!< Direction change to UP Interrupt Enable */
+#define LPTIM_INTEN_DOWNIE_ENABLE                   LPTIM_INTEN_DOWNIE        /*!< Direction change to down Interrupt Enable */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_OPERATING_MODE Operating Mode
+  * @{
+  */
+#define LPTIM_OPERATING_MODE_CONTINUOUS    LPTIM_CTRL_TSTCM  /*!<LP Timer starts in continuous mode*/
+#define LPTIM_OPERATING_MODE_ONESHOT       LPTIM_CTRL_SNGMST /*!<LP Tilmer starts in single mode*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_UPDATE_MODE Update Mode
+  * @{
+  */
+#define LPTIM_UPDATE_MODE_IMMEDIATE        0x00000000U        /*!<Preload is disabled: registers are updated after each APB bus write access*/
+#define LPTIM_UPDATE_MODE_ENDOFPERIOD      LPTIM_CFG_RELOAD    /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_COUNTER_MODE Counter Mode
+  * @{
+  */
+#define LPTIM_COUNTER_MODE_INTERNAL        0x00000000U          /*!<The counter is incremented following each internal clock pulse*/
+#define LPTIM_COUNTER_MODE_EXTERNAL        LPTIM_CFG_CNTMEN     /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_OUTPUT_WAVEFORM Output Waveform Type
+  * @{
+  */
+#define LPTIM_OUTPUT_WAVEFORM_PWM          0x00000000U     /*!<LPTIM  generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
+#define LPTIM_OUTPUT_WAVEFORM_SETONCE      LPTIM_CFG_WAVE  /*!<LPTIM  generates a Set Once waveform*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_OUTPUT_POLARITY Output Polarity
+  * @{
+  */
+#define LPTIM_OUTPUT_POLARITY_REGULAR      0x00000000U             /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
+#define LPTIM_OUTPUT_POLARITY_INVERSE      LPTIM_CFG_WAVEPOL         /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_PRESCALER Prescaler Value
+  * @{
+  */
+#define LPTIM_PRESCALER_DIV1               0x00000000U                               /*!<Prescaler division factor is set to 1*/
+#define LPTIM_PRESCALER_DIV2               LPTIM_CFG_CLKPRE_0                        /*!<Prescaler division factor is set to 2*/
+#define LPTIM_PRESCALER_DIV4               LPTIM_CFG_CLKPRE_1                        /*!<Prescaler division factor is set to 4*/
+#define LPTIM_PRESCALER_DIV8               (LPTIM_CFG_CLKPRE_1 | LPTIM_CFG_CLKPRE_0) /*!<Prescaler division factor is set to 8*/
+#define LPTIM_PRESCALER_DIV16              LPTIM_CFG_CLKPRE_2                        /*!<Prescaler division factor is set to 16*/
+#define LPTIM_PRESCALER_DIV32              (LPTIM_CFG_CLKPRE_2 | LPTIM_CFG_CLKPRE_0) /*!<Prescaler division factor is set to 32*/
+#define LPTIM_PRESCALER_DIV64              (LPTIM_CFG_CLKPRE_2 | LPTIM_CFG_CLKPRE_1) /*!<Prescaler division factor is set to 64*/
+#define LPTIM_PRESCALER_DIV128             LPTIM_CFG_CLKPRE                          /*!<Prescaler division factor is set to 128*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_TRIG_SOURCE Trigger Source
+  * @{
+  */
+#define LPTIM_TRIG_SOURCE_GPIO             0x00000000U                               /*!<External input trigger is connected to TIMx_ETR input*/
+#define LPTIM_TRIG_SOURCE_RTCALARMA        LPTIM_CFG_TRGSEL_0                          /*!<External input trigger is connected to RTC Alarm A*/
+#define LPTIM_TRIG_SOURCE_RTCALARMB        LPTIM_CFG_TRGSEL_1                          /*!<External input trigger is connected to RTC Alarm B*/
+#define LPTIM_TRIG_SOURCE_RTCTAMP1         (LPTIM_CFG_TRGSEL_1 | LPTIM_CFG_TRGSEL_0)     /*!<External input trigger is connected to RTC Tamper 1*/
+#define LPTIM_TRIG_SOURCE_RTCTAMP2         LPTIM_CFG_TRGSEL_2                          /*!<External input trigger is connected to RTC Tamper 2*/
+#define LPTIM_TRIG_SOURCE_RTCTAMP3         (LPTIM_CFG_TRGSEL_2 | LPTIM_CFG_TRGSEL_0)     /*!<External input trigger is connected to RTC Tamper 3*/
+#define LPTIM_TRIG_SOURCE_COMP1            (LPTIM_CFG_TRGSEL_2 | LPTIM_CFG_TRGSEL_1)     /*!<External input trigger is connected to COMP1 output*/
+#define LPTIM_TRIG_SOURCE_COMP2            LPTIM_CFG_TRGSEL                            /*!<External input trigger is connected to COMP2 output*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_TRIG_FILTER Trigger Filter
+  * @{
+  */
+#define LPTIM_TRIG_FILTER_NONE             0x00000000U           /*!<Any trigger active level change is considered as a valid trigger*/
+#define LPTIM_TRIG_FILTER_2                LPTIM_CFG_TRIGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
+#define LPTIM_TRIG_FILTER_4                LPTIM_CFG_TRIGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
+#define LPTIM_TRIG_FILTER_8                LPTIM_CFG_TRIGFLT   /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_TRIG_POLARITY Trigger Polarity
+  * @{
+  */
+#define LPTIM_TRIG_POLARITY_RISING         LPTIM_CFG_TRGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
+#define LPTIM_TRIG_POLARITY_FALLING        LPTIM_CFG_TRGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
+#define LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFG_TRGEN   /*!<LPTIM counter starts when a rising or a falling edge is detected*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_CLK_SOURCE Clock Source
+  * @{
+  */
+#define LPTIM_CLK_SOURCE_INTERNAL          0x00000000U    /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
+#define LPTIM_CLK_SOURCE_EXTERNAL          LPTIM_CFG_CLKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_CLK_FILTER Clock Filter
+  * @{
+  */
+#define LPTIM_CLK_FILTER_NONE              0x00000000U           /*!<Any external clock signal level change is considered as a valid transition*/
+#define LPTIM_CLK_FILTER_2                 LPTIM_CFG_CLKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
+#define LPTIM_CLK_FILTER_4                 LPTIM_CFG_CLKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
+#define LPTIM_CLK_FILTER_8                 LPTIM_CFG_CLKFLT   /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_CLK_POLARITY Clock Polarity
+  * @{
+  */
+#define LPTIM_CLK_POLARITY_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
+#define LPTIM_CLK_POLARITY_FALLING         LPTIM_CFG_CLKPOL_0   /*!< The falling edge is the active edge used for counting*/
+#define LPTIM_CLK_POLARITY_RISING_FALLING  LPTIM_CFG_CLKPOL_1   /*!< Both edges are active edges*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_ENCODER_MODE Encoder Mode
+  * @{
+  */
+#define LPTIM_ENCODER_MODE_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
+#define LPTIM_ENCODER_MODE_FALLING         LPTIM_CFG_CLKPOL_0   /*!< The falling edge is the active edge used for counting*/
+#define LPTIM_ENCODER_MODE_RISING_FALLING  LPTIM_CFG_CLKPOL_1   /*!< Both edges are active edges*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
+  * @{
+  */
+
+/** @defgroup LPTIM_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in LPTIM register
+  * @param  __INSTANCE__ LPTIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->(__REG__), (__VALUE__))
+
+/**
+  * @brief  Read a value in LPTIM register
+  * @param  __INSTANCE__ LPTIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+  * @{
+  */
+
+/** @defgroup LPTIM_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+void LPTIM_DeInit(LPTIM_Module *LPTIMx);
+void LPTIM_StructInit(LPTIM_InitType *LPTIM_InitStruct);
+ErrorStatus LPTIM_Init(LPTIM_Module *LPTIMx, LPTIM_InitType *LPTIM_InitStruct);
+void LPTIM_Disable(LPTIM_Module *LPTIMx);
+
+
+
+void LPTIM_Enable(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx);
+void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode);
+void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode);
+uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx);
+void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload);
+uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx);
+void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue);
+uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx);
+void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode);
+uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx);
+void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity);
+void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform);
+uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx);
+void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity);
+uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx);
+void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler);
+uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx);
+void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx);
+void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx);
+void LPTIM_TrigSw(LPTIM_Module *LPTIMx);
+void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity);
+uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx);
+void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource);
+uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx);
+void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity);
+uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx);
+void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode);
+uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx);
+void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx);
+void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx);
+void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx);
+void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx);
+void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx);
+uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx);
+void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+//#endif /* LPTIM */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __n32g43x_LPTIM_H */
+
+/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h

@@ -0,0 +1,280 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_lpuart.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43x_LPUART_H__
+#define __N32G43x_LPUART_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LPUART
+ * @{
+ */
+
+/** @addtogroup LPUART_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief  LPUART Init Structure definition
+ */
+
+typedef struct
+{
+    uint32_t BaudRate; /*!< This member configures the LPUART communication baud rate.
+                                  The baud rate is computed using the following formula:
+                                   - IntegerDivider = ((CLK) / (LPUART_InitStruct->BaudRate)))
+                                   - FractionalDivider */
+
+    uint16_t Parity; /*!< Specifies the parity mode.
+                                This parameter can be a value of @ref Parity
+                                @note When parity is enabled, the computed parity is inserted
+                                      at the MSB position of the transmitted data (only support
+                                      8 data bits). */
+
+    uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                              This parameter can be a value of @ref Mode */
+
+    uint16_t RtsThreshold; /* Specifies RTS Threshold.
+                                    This parameter can be a value of @ref RtsThreshold */
+
+    uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+                                             or disabled.
+                                             This parameter can be a value of @ref LPUART_Hardware_Flow_Control */
+} LPUART_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup Parity
+ * @{
+ */
+
+#define LPUART_PE_NO             ((uint16_t)0x0008)
+#define LPUART_PE_EVEN           ((uint16_t)0x0000)
+#define LPUART_PE_ODD            ((uint16_t)0x0001)
+#define IS_LPUART_PARITY(PARITY) (((PARITY) == LPUART_PE_NO) || ((PARITY) == LPUART_PE_EVEN) || ((PARITY) == LPUART_PE_ODD))
+/**
+ * @}
+ */
+
+/** @addtogroup Mode
+ * @{
+ */
+
+#define LPUART_MODE_RX       ((uint16_t)0x0000)
+#define LPUART_MODE_TX       ((uint16_t)0x0002)
+#define IS_LPUART_MODE(MODE) (((MODE) == LPUART_MODE_RX) || ((MODE) == LPUART_MODE_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup RtsThreshold
+ * @{
+ */
+
+#define LPUART_RTSTH_FIFOHF       ((uint16_t)0x0000)
+#define LPUART_RTSTH_FIFO3QF      ((uint16_t)0x0100)
+#define LPUART_RTSTH_FIFOFU       ((uint16_t)0x0200)
+#define IS_LPUART_RTSTHRESHOLD(RTSTHRESHOLD)                                                                                \
+    (((RTSTHRESHOLD) == LPUART_RTSTH_FIFOHF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFO3QF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFOFU))
+/**
+ * @}
+ */
+
+/** @addtogroup Hardware_Flow_Control
+ * @{
+ */
+#define LPUART_HFCTRL_NONE    ((uint16_t)0x0000)
+#define LPUART_HFCTRL_CTS     ((uint16_t)0x0400)
+#define LPUART_HFCTRL_RTS     ((uint16_t)0x0800)
+#define LPUART_HFCTRL_RTS_CTS ((uint16_t)0x0C00)
+#define IS_LPUART_HARDWARE_FLOW_CONTROL(CONTROL)                                                                        \
+    (((CONTROL) == LPUART_HFCTRL_NONE) || ((CONTROL) == LPUART_HFCTRL_RTS) || ((CONTROL) == LPUART_HFCTRL_CTS)          \
+     || ((CONTROL) == LPUART_HFCTRL_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Interrupt_definition
+ * @{
+ */
+
+#define LPUART_INT_PE      ((uint16_t)0x0001)
+#define LPUART_INT_TXC     ((uint16_t)0x0102)
+#define LPUART_INT_FIFO_OV ((uint16_t)0x0204)
+#define LPUART_INT_FIFO_FU ((uint16_t)0x0308)
+#define LPUART_INT_FIFO_HF ((uint16_t)0x0410)
+#define LPUART_INT_FIFO_NE ((uint16_t)0x0520)
+#define LPUART_INT_WUF     ((uint16_t)0x0640)
+#define IS_LPUART_CFG_INT(IT)                                                                                           \
+    (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU)       \
+     || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
+#define IS_LPUART_GET_INT(IT)                                                                                           \
+    (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU)       \
+     || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
+#define IS_LPUART_CLR_INT(IT)                                                                                           \
+    (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU)      \
+     || ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_DMA_Requests
+ * @{
+ */
+
+#define LPUART_DMAREQ_TX         ((uint16_t)0x0020)
+#define LPUART_DMAREQ_RX         ((uint16_t)0x0040)
+#define IS_LPUART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF9F) == (uint16_t)0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_WakeUp_methods
+ * @{
+ */
+
+#define LPUART_WUSTP_STARTBIT    ((uint16_t)0x0000)
+#define LPUART_WUSTP_RXNE        ((uint16_t)0x1000)
+#define LPUART_WUSTP_BYTE        ((uint16_t)0x2000)
+#define LPUART_WUSTP_FRAME       ((uint16_t)0x3000)
+#define IS_LPUART_WAKEUP(WAKEUP)  \
+    (((WAKEUP) == LPUART_WUSTP_STARTBIT) || ((WAKEUP) == LPUART_WUSTP_RXNE) || ((WAKEUP) == LPUART_WUSTP_BYTE) || ((WAKEUP) == LPUART_WUSTP_FRAME))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Sampling_methods
+ * @{
+ */
+
+#define LPUART_SMPCNT_3B    ((uint16_t)0x0000)
+#define LPUART_SMPCNT_1B    ((uint16_t)0x4000)
+#define IS_LPUART_SAMPLING(SAMPLING) (((SAMPLING) == LPUART_SMPCNT_1B) || ((SAMPLING) == LPUART_SMPCNT_3B))
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Flags
+ * @{
+ */
+
+#define LPUART_FLAG_PEF      ((uint16_t)0x0001)
+#define LPUART_FLAG_TXC      ((uint16_t)0x0002)
+#define LPUART_FLAG_FIFO_OV  ((uint16_t)0x0004)
+#define LPUART_FLAG_FIFO_FU  ((uint16_t)0x0008)
+#define LPUART_FLAG_FIFO_HF  ((uint16_t)0x0010)
+#define LPUART_FLAG_FIFO_NE  ((uint16_t)0x0020)
+#define LPUART_FLAG_CTS      ((uint16_t)0x0040)
+#define LPUART_FLAG_WUF      ((uint16_t)0x0080)
+#define LPUART_FLAG_NF       ((uint16_t)0x0100)
+#define IS_LPUART_FLAG(FLAG)                                                                                            \
+    (((FLAG) == LPUART_FLAG_PEF) || ((FLAG) == LPUART_FLAG_TXC) || ((FLAG) == LPUART_FLAG_FIFO_OV)                           \
+     || ((FLAG) == LPUART_FLAG_FIFO_FU) || ((FLAG) == LPUART_FLAG_FIFO_HF) || ((FLAG) == LPUART_FLAG_FIFO_NE)                   \
+     || ((FLAG) == LPUART_FLAG_CTS) || ((FLAG) == LPUART_FLAG_WUF) || ((FLAG) == LPUART_FLAG_NF))
+
+#define IS_LPUART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFE40) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_LPUART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x010000))
+
+#define IS_LPUART_DATA(DATA)         ((DATA) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Exported_Functions
+ * @{
+ */
+
+void LPUART_DeInit(void);
+void LPUART_Init(LPUART_InitType* LPUART_InitStruct);
+void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct);
+void LPUART_FlushRxFifo(void);
+void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd);
+void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd);
+void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod);
+void LPUART_EnableWakeUpStop(FunctionalState Cmd);
+void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod);
+void LPUART_EnableLoopBack(FunctionalState Cmd);
+void LPUART_SendData(uint8_t Data);
+uint8_t LPUART_ReceiveData(void);
+void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData);
+FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG);
+void LPUART_ClrFlag(uint16_t LPUART_FLAG);
+INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT);
+void LPUART_ClrIntPendingBit(uint16_t LPART_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43x_LPUART_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_opamp.h

@@ -0,0 +1,209 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_opamp.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_OPAMPMP_H__
+#define __N32G43X_OPAMPMP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+#include <stdbool.h>
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @{
+ */
+
+/** @addtogroup OPAMP_Exported_Constants
+ * @{
+ */
+typedef enum
+{
+    OPAMP1 = 0,
+    OPAMP2 = 4,
+} OPAMPX;
+
+// OPAMP_CS
+typedef enum
+{
+    OPAMP2_CS_TIMSRCSEL_TIM1CC6  = (0x0L << 24),
+    OPAMP2_CS_TIMSRCSEL_TIM8CC6  = (0x1L << 24),
+}OPAMP2_CS_TIMSRCSEL;
+typedef enum
+{
+    OPAMP1_CS_VPSSEL_PA1        = (0x00L << 19),
+    OPAMP1_CS_VPSSEL_PA5        = (0x01L << 19),
+    OPAMP1_CS_VPSSEL_PA4        = (0x02L << 19),
+    OPAMP1_CS_VPSSEL_PA7        = (0x03L << 19),
+    OPAMP1_CS_VPSSEL_NC         = (0x04L << 19),
+
+    OPAMP2_CS_VPSSEL_PA7        = (0x00L << 19),
+    OPAMP2_CS_VPSSEL_PA4        = (0x01L << 19),
+    OPAMP2_CS_VPSSEL_PB14       = (0x02L << 19),
+    OPAMP2_CS_VPSSEL_PD13       = (0x03L << 19),
+    OPAMP2_CS_VPSSEL_NC         = (0x04L << 19),
+} OPAMP_CS_VPSSEL;
+typedef enum
+{
+    OPAMP1_CS_VMSSEL_PA3    = (0x00L << 17),
+    OPAMP1_CS_VMSSEL_PC5    = (0x01L << 17),
+    OPAMP1_CS_VMSSEL_NC     = (0x02L << 17),
+    OPAMP1_CS_VMSSEL_FLOAT  = (0x03L << 17),
+
+    OPAMP2_CS_VMSSEL_PC5    = (0x00L << 17),
+    OPAMP2_CS_VMSSEL_PB0    = (0x01L << 17),
+    OPAMP2_CS_VMSSEL_PA5    = (0x02L << 17),
+    OPAMP2_CS_VMSSEL_FLOAT  = (0x03L << 17),
+} OPAMP_CS_VMSSEL;
+
+typedef enum
+{
+    OPAMP1_CS_VPSEL_PA1     = (0x00L << 8),
+    OPAMP1_CS_VPSEL_PA5     = (0x01L << 8),
+    OPAMP1_CS_VPSEL_PA4     = (0x02L << 8),
+    OPAMP1_CS_VPSEL_PA7     = (0x03L << 8),
+    OPAMP1_CS_VPSEL_NC      = (0x04L << 8),
+
+    OPAMP2_CS_VPSEL_PA7     = (0x00L << 8),
+    OPAMP2_CS_VPSEL_PA4     = (0x01L << 8),
+    OPAMP2_CS_VPSEL_PB14    = (0x02L << 8),
+    OPAMP2_CS_VPSEL_PD13    = (0x03L << 8),
+    OPAMP2_CS_VPSEL_NC      = (0x04L << 8),
+} OPAMP_CS_VPSEL;
+typedef enum
+{
+    OPAMP1_CS_VMSEL_PA3     = (0x00L << 6),
+    OPAMP1_CS_VMSEL_PC5     = (0x01L << 6),
+    OPAMPx_CS_VMSEL_NC      = (0x02L << 6),
+    OPAMPx_CS_VMSEL_FLOAT   = (0x03L << 6),
+
+    OPAMP2_CS_VMSEL_PC5     = (0x00L << 6),
+    OPAMP2_CS_VMSEL_PB0     = (0x01L << 6),
+    OPAMP2_CS_VMSEL_PA5     = (0x02L << 6),
+    OPAMP2_CS_VMSEL_FLOAT   = (0x03L << 6),
+} OPAMP_CS_VMSEL;
+typedef enum
+{
+    OPAMP_CS_PGA_GAIN_2  = (0x00 << 3),
+    OPAMP_CS_PGA_GAIN_4  = (0x01 << 3),
+    OPAMP_CS_PGA_GAIN_8  = (0x02 << 3),
+    OPAMP_CS_PGA_GAIN_16 = (0x03 << 3),
+    OPAMP_CS_PGA_GAIN_32 = (0x04 << 3),
+} OPAMP_CS_PGA_GAIN;
+typedef enum
+{
+    OPAMP_CS_EXT_OPAMP = (0x00 << 1),
+    OPAMP_CS_PGA_EN    = (0x02 << 1),
+    OPAMP_CS_FOLLOW    = (0x03 << 1),
+} OPAMP_CS_MOD;
+
+// bit mask
+#define OPAMP_CS_EN_MASK           (0x01L << 0)
+#define OPAMP_CS_MOD_MASK          (0x03L << 1)
+#define OPAMP_CS_PGA_GAIN_MASK     (0x07L << 3)
+#define OPAMP_CS_VMSEL_MASK        (0x03L << 6)
+#define OPAMP_CS_VPSEL_MASK        (0x07L << 8)
+#define OPAMP_CS_CALON_MASK        (0x01L << 11)
+#define OPAMP_CS_TSTREF_MASK       (0x01L << 13)
+#define OPAMP_CS_CALOUT_MASK       (0x01L << 14)
+#define OPAMP_CS_RANGE_MASK        (0x01L << 15)
+#define OPAMP_CS_TCMEN_MASK        (0x01L << 16)
+#define OPAMP_CS_VMSEL_SECOND_MASK (0x03L << 17)
+#define OPAMP_CS_VPSEL_SECOND_MASK (0x07L << 19)
+#define OPAMP_CS_OPAMP2_TIMSRCSEL  (0x01L << 24)
+/** @addtogroup OPAMP_LOCK
+ * @{
+ */
+#define OPAMP_LOCK_1 0x01L
+#define OPAMP_LOCK_2 0x02L
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @brief  OPAMP Init structure definition
+ */
+
+typedef struct
+{
+    OPAMP2_CS_TIMSRCSEL Opa2SrcSel; /*only for opa2 can sel,opa1 always TIM1_CC6*/
+
+    FunctionalState TimeAutoMuxEn; /*call ENABLE or DISABLE */
+
+    FunctionalState HighVolRangeEn; /*call ENABLE or DISABLE ,low range VDDA < 2.4V,high range VDDA >= 2.4V*/
+
+    OPAMP_CS_PGA_GAIN Gain; /*see @EM_PGA_GAIN */
+
+    OPAMP_CS_MOD Mod; /*see @EM_OPAMP_MOD*/
+} OPAMP_InitType;
+
+/** @addtogroup OPAMP_Exported_Functions
+ * @{
+ */
+
+void OPAMP_DeInit(void);
+void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct);
+void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct);
+void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en);
+void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain);
+void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel);
+void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel);
+void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel);
+void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel);
+bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx);
+void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en);
+void OPAMP_SetLock(uint32_t Lock); // see @OPAMP_LOCK
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_ADC_H */
+       /**
+        * @}
+        */
+       /**
+        * @}
+        */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_pwr.h

@@ -0,0 +1,222 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_pwr.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43x_PWR_H__
+#define __N32G43x_PWR_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup PVD_detection_level
+ * @{
+ */
+
+#define PWR_PVDLEVEL_2V1  ((uint32_t)0x00000000)
+#define PWR_PVDLEVEL_2V25 ((uint32_t)0x0000002)
+#define PWR_PVDLEVEL_2V4  ((uint32_t)0x0000004)
+#define PWR_PVDLEVEL_2V55 ((uint32_t)0x0000006)
+#define PWR_PVDLEVEL_2V7  ((uint32_t)0x0000008)
+#define PWR_PVDLEVEL_2V85 ((uint32_t)0x000000A)
+#define PWR_PVDLEVEL_2V95 ((uint32_t)0x000000C)
+#define PWR_PVDLEVEL_IN   ((uint32_t)0x000000E)
+
+
+#define IS_PWR_PVD_LEVEL(LEVEL)                                                                                        \
+    (((LEVEL) == PWR_PVDLEVEL_2V1) || ((LEVEL) == PWR_PVDLEVEL_2V25) || ((LEVEL) == PWR_PVDLEVEL_2V4)               \
+     || ((LEVEL) == PWR_PVDLEVEL_2V55) || ((LEVEL) == PWR_PVDLEVEL_2V7) || ((LEVEL) == PWR_PVDLEVEL_2V85)           \
+     || ((LEVEL) == PWR_PVDLEVEL_2V95) || ((LEVEL) == PWR_PVDLEVEL_IN) )
+
+/**
+ * @}
+ */
+
+/** @addtogroup Regulator_state_is_STOP_mode
+ * @{
+ */
+
+#define PWR_REGULATOR_ON            ((uint32_t)0x00000000)
+#define PWR_REGULATOR_LOWPOWER      ((uint32_t)0x00000001)
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER))
+/**
+ * @}
+ */
+
+/** @defgroup SLEEP_mode_entry
+  * @{
+  */
+#define SLEEP_ON_EXIT              (1)
+#define SLEEP_OFF_EXIT             (0)
+#define PWR_SLEEPENTRY_WFI         ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE         ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup STOP_mode_entry
+  * @{
+  */
+
+#define PWR_STOPENTRY_WFI        ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE        ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Flag
+ * @{
+ */
+//STS1
+#define PWR_WKUP0_FLAG    ((uint32_t)0x00000001)
+#define PWR_WKUP1_FLAG    ((uint32_t)0x00000002)
+#define PWR_WKUP2_FLAG    ((uint32_t)0x00000004)
+#define PWR_STBY_FLAG     ((uint32_t)0x00000100)
+//STS2
+#define PWR_LPRUN_FLAG    ((uint32_t)0x00000001)
+#define PWR_MR_FLAG       ((uint32_t)0x00000002)
+#define PWR_PVDO_FLAG     ((uint32_t)0x00000004)
+
+#define IS_PWR_GET_FLAG(FLAG)                                                                                          \
+    (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\
+      || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) \
+    (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\
+    || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG))
+
+
+
+/** @addtogroup SRAM1 SRAM2 retention set
+ * @{
+ */
+//#define SRAM1DIS_SRAM2DIS      0
+//#define SRAM1EN_SRAM2DIS       1
+
+//#define SRAM1DIS_SRAM2EN       2
+//#define SRAM1EN_SRAM2EN        3
+/** @addtogroup MR VOLTAGE
+ * @{
+ */
+#define MR_1V0  2
+#define MR_1V1  3
+
+
+/**
+ * @}
+ */
+typedef enum
+{
+    WAKEUP_PIN0 = 0x0001,
+    WAKEUP_PIN1 = 0x0002,
+    WAKEUP_PIN2 = 0x0004,
+} WAKEUP_PINX;
+/** @addtogroup PWR_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#define LPRUN_SRAM_ADDR   (__IO unsigned*)(0x40001800 + 0x20)
+#define CLERR_BIT25  0xfdffffff //bit25
+#define _SetLprunSramVoltage(vale) do{(*LPRUN_SRAM_ADDR) &= CLERR_BIT25;(*LPRUN_SRAM_ADDR) |= (uint32_t)(vale <<25);}while (0) //0:0.9V 1:1.1V
+#define _SetBandGapMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_BGDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<8);}while (0) //0:always on 1:duty on
+#define _SetPvdBorMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_PBDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<16);}while (0) //0:normal mode 1:standby mode
+/** @addtogroup PWR_Exported_Functions
+ * @{
+ */
+
+void PWR_DeInit(void);
+void PWR_BackupAccessEnable(FunctionalState Cmd);
+void PWR_PvdEnable(FunctionalState Cmd);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd);
+void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry);
+void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode);
+void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret);
+void PWR_EnterLowPowerRunMode(void);
+void PWR_ExitLowPowerRunMode(void);
+void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry);
+
+FlagStatus PWR_GetFlagStatus(uint8_t STS, uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+void PWR_WakeUpPinConfig(void);
+void SetSysClock_MSI(void);
+uint8_t GetMrVoltage(void);
+void PWR_MRconfig(uint8_t voltage);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43x_PWR_H__ */
+       /**
+        * @}
+        */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rcc.h

@@ -0,0 +1,911 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_rcc.h
+ * @author Nations
+ * @version V1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_RCC_H__
+#define __N32G43X_RCC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Types
+ * @{
+ */
+
+typedef struct
+{
+    uint32_t SysclkFreq;    /*!< returns SYSCLK clock frequency expressed in Hz */
+    uint32_t HclkFreq;      /*!< returns HCLK clock frequency expressed in Hz */
+    uint32_t Pclk1Freq;     /*!< returns PCLK1 clock frequency expressed in Hz */
+    uint32_t Pclk2Freq;     /*!< returns PCLK2 clock frequency expressed in Hz */
+    uint32_t AdcPllClkFreq; /*!< returns ADCPLLCLK clock frequency expressed in Hz */
+    uint32_t AdcHclkFreq;   /*!< returns ADCHCLK clock frequency expressed in Hz */
+} RCC_ClocksType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_DISABLE ((uint32_t)0x00000000)
+#define RCC_HSE_ENABLE  ((uint32_t)0x00010000)
+#define RCC_HSE_BYPASS  ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_DISABLE) || ((HSE) == RCC_HSE_ENABLE) || ((HSE) == RCC_HSE_BYPASS))
+
+/**
+ * @}
+ */
+
+/** @addtogroup HSI_configuration
+ * @{
+ */
+
+#define RCC_HSI_DISABLE ((uint32_t)0x00000000)
+#define RCC_HSI_ENABLE  ((uint32_t)0x00000001)
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_DISABLE) || ((HSI) == RCC_HSI_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup MSI_configuration
+ * @{
+ */
+
+#define RCC_MSI_DISABLE ((uint32_t)0x00000000)
+#define RCC_MSI_ENABLE  ((uint32_t)0x00000004)
+#define IS_RCC_MSI(MSI) (((MSI) == RCC_MSI_DISABLE) || ((MSI) == RCC_MSI_ENABLE))
+
+#define RCC_MSI_RANGE_100K ((uint32_t)0x00000000)
+#define RCC_MSI_RANGE_200K ((uint32_t)0x00000010)
+#define RCC_MSI_RANGE_400K ((uint32_t)0x00000020)
+#define RCC_MSI_RANGE_800K ((uint32_t)0x00000030)
+#define RCC_MSI_RANGE_1M   ((uint32_t)0x00000040)
+#define RCC_MSI_RANGE_2M   ((uint32_t)0x00000050)
+#define RCC_MSI_RANGE_4M   ((uint32_t)0x00000060)
+#define IS_RCC_MSI_RANGE(MSI_RANGE) (((MSI_RANGE) == RCC_MSI_RANGE_100K) || ((MSI_RANGE) == RCC_MSI_RANGE_200K)  \
+                                   || ((MSI_RANGE) == RCC_MSI_RANGE_400K) || ((MSI_RANGE) == RCC_MSI_RANGE_800K) \
+                                   || ((MSI_RANGE) == RCC_MSI_RANGE_1M) || ((MSI_RANGE) == RCC_MSI_RANGE_2M)     \
+                                   || ((MSI_RANGE) == RCC_MSI_RANGE_4M)                                          \
+                                    )
+
+/**
+ * @}
+ */
+
+/** @addtogroup PLL_entry_clock_source
+ * @{
+ */
+#define RCC_PLL_HSI_PRE_DIV1 ((uint32_t)0x00000000)
+#define RCC_PLL_HSI_PRE_DIV2 ((uint32_t)0x00000001)
+
+#define RCC_PLL_SRC_HSE_DIV1 ((uint32_t)0x00010000)
+#define RCC_PLL_SRC_HSE_DIV2 ((uint32_t)0x00030000)
+#define IS_RCC_PLL_SRC(SOURCE)                                                                                         \
+    (((SOURCE) == RCC_PLL_HSI_PRE_DIV1) || ((SOURCE) == RCC_PLL_HSI_PRE_DIV2)                                          \
+  || ((SOURCE) == RCC_PLL_SRC_HSE_DIV1) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV2))
+
+#define RCC_PLLDIVCLK_DISABLE ((uint32_t)0x00000000)
+#define RCC_PLLDIVCLK_ENABLE  ((uint32_t)0x00000002)
+#define IS_RCC_PLL_DIVCLK(DIVCLK)                                                                                         \
+    (((DIVCLK) == RCC_PLLDIVCLK_DISABLE) || ((DIVCLK) == RCC_PLLDIVCLK_ENABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup PLL_multiplication_factor
+ * @{
+ */
+#define RCC_PLL_MUL_2  ((uint32_t)0x00000000)
+#define RCC_PLL_MUL_3  ((uint32_t)0x00040000)
+#define RCC_PLL_MUL_4  ((uint32_t)0x00080000)
+#define RCC_PLL_MUL_5  ((uint32_t)0x000C0000)
+#define RCC_PLL_MUL_6  ((uint32_t)0x00100000)
+#define RCC_PLL_MUL_7  ((uint32_t)0x00140000)
+#define RCC_PLL_MUL_8  ((uint32_t)0x00180000)
+#define RCC_PLL_MUL_9  ((uint32_t)0x001C0000)
+#define RCC_PLL_MUL_10 ((uint32_t)0x00200000)
+#define RCC_PLL_MUL_11 ((uint32_t)0x00240000)
+#define RCC_PLL_MUL_12 ((uint32_t)0x00280000)
+#define RCC_PLL_MUL_13 ((uint32_t)0x002C0000)
+#define RCC_PLL_MUL_14 ((uint32_t)0x00300000)
+#define RCC_PLL_MUL_15 ((uint32_t)0x00340000)
+#define RCC_PLL_MUL_16 ((uint32_t)0x00380000)
+#define RCC_PLL_MUL_17 ((uint32_t)0x08000000)
+#define RCC_PLL_MUL_18 ((uint32_t)0x08040000)
+#define RCC_PLL_MUL_19 ((uint32_t)0x08080000)
+#define RCC_PLL_MUL_20 ((uint32_t)0x080C0000)
+#define RCC_PLL_MUL_21 ((uint32_t)0x08100000)
+#define RCC_PLL_MUL_22 ((uint32_t)0x08140000)
+#define RCC_PLL_MUL_23 ((uint32_t)0x08180000)
+#define RCC_PLL_MUL_24 ((uint32_t)0x081C0000)
+#define RCC_PLL_MUL_25 ((uint32_t)0x08200000)
+#define RCC_PLL_MUL_26 ((uint32_t)0x08240000)
+#define RCC_PLL_MUL_27 ((uint32_t)0x08280000)
+#define RCC_PLL_MUL_28 ((uint32_t)0x082C0000)
+#define RCC_PLL_MUL_29 ((uint32_t)0x08300000)
+#define RCC_PLL_MUL_30 ((uint32_t)0x08340000)
+#define RCC_PLL_MUL_31 ((uint32_t)0x08380000)
+#define RCC_PLL_MUL_32 ((uint32_t)0x083C0000)
+#define IS_RCC_PLL_MUL(MUL)                                                                                            \
+    (((MUL) == RCC_PLL_MUL_2) || ((MUL) == RCC_PLL_MUL_3) || ((MUL) == RCC_PLL_MUL_4) || ((MUL) == RCC_PLL_MUL_5)      \
+     || ((MUL) == RCC_PLL_MUL_6) || ((MUL) == RCC_PLL_MUL_7) || ((MUL) == RCC_PLL_MUL_8) || ((MUL) == RCC_PLL_MUL_9)   \
+     || ((MUL) == RCC_PLL_MUL_10) || ((MUL) == RCC_PLL_MUL_11) || ((MUL) == RCC_PLL_MUL_12)                            \
+     || ((MUL) == RCC_PLL_MUL_13) || ((MUL) == RCC_PLL_MUL_14) || ((MUL) == RCC_PLL_MUL_15)                            \
+     || ((MUL) == RCC_PLL_MUL_16) || ((MUL) == RCC_PLL_MUL_17) || ((MUL) == RCC_PLL_MUL_18)                            \
+     || ((MUL) == RCC_PLL_MUL_19) || ((MUL) == RCC_PLL_MUL_20) || ((MUL) == RCC_PLL_MUL_21)                            \
+     || ((MUL) == RCC_PLL_MUL_22) || ((MUL) == RCC_PLL_MUL_23) || ((MUL) == RCC_PLL_MUL_24)                            \
+     || ((MUL) == RCC_PLL_MUL_25) || ((MUL) == RCC_PLL_MUL_26) || ((MUL) == RCC_PLL_MUL_27)                            \
+     || ((MUL) == RCC_PLL_MUL_28) || ((MUL) == RCC_PLL_MUL_29) || ((MUL) == RCC_PLL_MUL_30)                            \
+     || ((MUL) == RCC_PLL_MUL_31) || ((MUL) == RCC_PLL_MUL_32))
+
+/**
+ * @}
+ */
+
+/** @addtogroup System_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_SRC_MSI    ((uint32_t)0x00000000)
+#define RCC_SYSCLK_SRC_HSI    ((uint32_t)0x00000001)
+#define RCC_SYSCLK_SRC_HSE    ((uint32_t)0x00000002)
+#define RCC_SYSCLK_SRC_PLLCLK ((uint32_t)0x00000003)
+#define IS_RCC_SYSCLK_SRC(SOURCE)                                                                                      \
+    (((SOURCE) == RCC_SYSCLK_SRC_MSI) || ((SOURCE) == RCC_SYSCLK_SRC_HSI)                                              \
+  || ((SOURCE) == RCC_SYSCLK_SRC_HSE) || ((SOURCE) == RCC_SYSCLK_SRC_PLLCLK))
+/**
+ * @}
+ */
+
+/** @addtogroup AHB_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_DIV1   ((uint32_t)0x00000000)
+#define RCC_SYSCLK_DIV2   ((uint32_t)0x00000080)
+#define RCC_SYSCLK_DIV4   ((uint32_t)0x00000090)
+#define RCC_SYSCLK_DIV8   ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_DIV16  ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_DIV64  ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_DIV128 ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_DIV256 ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_DIV512 ((uint32_t)0x000000F0)
+#define IS_RCC_SYSCLK_DIV(HCLK)                                                                                        \
+    (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4)                         \
+     || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64)                    \
+     || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512))
+/**
+ * @}
+ */
+
+/** @addtogroup APB1_APB2_clock_source
+ * @{
+ */
+
+#define RCC_HCLK_DIV1  ((uint32_t)0x00000000)
+#define RCC_HCLK_DIV2  ((uint32_t)0x00000400)
+#define RCC_HCLK_DIV4  ((uint32_t)0x00000500)
+#define RCC_HCLK_DIV8  ((uint32_t)0x00000600)
+#define RCC_HCLK_DIV16 ((uint32_t)0x00000700)
+#define IS_RCC_HCLK_DIV(PCLK)                                                                                          \
+    (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8)  \
+     || ((PCLK) == RCC_HCLK_DIV16))
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Interrupt_source
+ * @{
+ */
+
+#define RCC_INT_LSIRDIF ((uint8_t)0x01)
+#define RCC_INT_LSERDIF ((uint8_t)0x02)
+#define RCC_INT_HSIRDIF ((uint8_t)0x04)
+#define RCC_INT_HSERDIF ((uint8_t)0x08)
+#define RCC_INT_PLLRDIF ((uint8_t)0x10)
+#define RCC_INT_BORIF   ((uint8_t)0x20)
+#define RCC_INT_MSIRDIF ((uint8_t)0x40)
+#define RCC_INT_CLKSSIF ((uint8_t)0x80)
+
+#define IS_RCC_INT(IT)                                                                                                 \
+    (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF)  \
+  || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF)   || ((IT) == RCC_INT_MSIRDIF))
+
+#define IS_RCC_GET_INT(IT)                                                                                             \
+    (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF)  \
+  || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_BORIF)   || ((IT) == RCC_INT_MSIRDIF) || ((IT) == RCC_INT_CLKSSIF))
+
+#define RCC_CLR_MSIRDIF ((uint32_t)0x00008000)
+#define RCC_CLR_LSIRDIF ((uint32_t)0x00010000)
+#define RCC_CLR_LSERDIF ((uint32_t)0x00020000)
+#define RCC_CLR_HSIRDIF ((uint32_t)0x00040000)
+#define RCC_CLR_HSERDIF ((uint32_t)0x00080000)
+#define RCC_CLR_PLLRDIF ((uint32_t)0x00100000)
+#define RCC_CLR_BORIF   ((uint32_t)0x00200000)
+#define RCC_CLR_CLKSSIF ((uint32_t)0x00800000)
+
+#define IS_RCC_CLR_INTF(IT)                                                                                             \
+    (((IT) == RCC_CLR_LSIRDIF) || ((IT) == RCC_CLR_LSERDIF) || ((IT) == RCC_CLR_HSIRDIF) || ((IT) == RCC_CLR_HSERDIF)  \
+  || ((IT) == RCC_CLR_PLLRDIF) || ((IT) == RCC_CLR_BORIF)   || ((IT) == RCC_CLR_MSIRDIF) || ((IT) == RCC_CLR_CLKSSIF))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USB_Device_clock_source
+ * @{
+ */
+
+#define RCC_USBCLK_SRC_PLLCLK_DIV1_5 ((uint8_t)0x00)
+#define RCC_USBCLK_SRC_PLLCLK_DIV1   ((uint8_t)0x01)
+#define RCC_USBCLK_SRC_PLLCLK_DIV2   ((uint8_t)0x02)
+#define RCC_USBCLK_SRC_PLLCLK_DIV3   ((uint8_t)0x03)
+
+#define IS_RCC_USBCLK_SRC(SOURCE)                                                                                      \
+    (((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1_5) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1)                            \
+     || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV2) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV3))
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_clock_source
+ * @{
+ */
+
+#define RCC_PCLK2_DIV2 ((uint32_t)0x00000000)
+#define RCC_PCLK2_DIV4 ((uint32_t)0x00004000)
+#define RCC_PCLK2_DIV6 ((uint32_t)0x00008000)
+#define RCC_PCLK2_DIV8 ((uint32_t)0x0000C000)
+#define IS_RCC_PCLK2_DIV(ADCCLK)                                                                                       \
+    (((ADCCLK) == RCC_PCLK2_DIV2) || ((ADCCLK) == RCC_PCLK2_DIV4) || ((ADCCLK) == RCC_PCLK2_DIV6)                      \
+     || ((ADCCLK) == RCC_PCLK2_DIV8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_CFGR2_Config
+ * @{
+ */
+#define RCC_TIM18CLK_SRC_TIM18CLK ((uint32_t)0x00000000)
+#define RCC_TIM18CLK_SRC_SYSCLK   ((uint32_t)0x20000000)
+#define IS_RCC_TIM18CLKSRC(TIM18CLK)                                                                                   \
+    (((TIM18CLK) == RCC_TIM18CLK_SRC_TIM18CLK) || ((TIM18CLK) == RCC_TIM18CLK_SRC_SYSCLK))
+
+#define RCC_RNGCCLK_SYSCLK_DIV1  ((uint32_t)0x00000000)
+#define RCC_RNGCCLK_SYSCLK_DIV2  ((uint32_t)0x01000000)
+#define RCC_RNGCCLK_SYSCLK_DIV3  ((uint32_t)0x02000000)
+#define RCC_RNGCCLK_SYSCLK_DIV4  ((uint32_t)0x03000000)
+#define RCC_RNGCCLK_SYSCLK_DIV5  ((uint32_t)0x04000000)
+#define RCC_RNGCCLK_SYSCLK_DIV6  ((uint32_t)0x05000000)
+#define RCC_RNGCCLK_SYSCLK_DIV7  ((uint32_t)0x06000000)
+#define RCC_RNGCCLK_SYSCLK_DIV8  ((uint32_t)0x07000000)
+#define RCC_RNGCCLK_SYSCLK_DIV9  ((uint32_t)0x08000000)
+#define RCC_RNGCCLK_SYSCLK_DIV10 ((uint32_t)0x09000000)
+#define RCC_RNGCCLK_SYSCLK_DIV11 ((uint32_t)0x0A000000)
+#define RCC_RNGCCLK_SYSCLK_DIV12 ((uint32_t)0x0B000000)
+#define RCC_RNGCCLK_SYSCLK_DIV13 ((uint32_t)0x0C000000)
+#define RCC_RNGCCLK_SYSCLK_DIV14 ((uint32_t)0x0D000000)
+#define RCC_RNGCCLK_SYSCLK_DIV15 ((uint32_t)0x0E000000)
+#define RCC_RNGCCLK_SYSCLK_DIV16 ((uint32_t)0x0F000000)
+#define RCC_RNGCCLK_SYSCLK_DIV17 ((uint32_t)0x10000000)
+#define RCC_RNGCCLK_SYSCLK_DIV18 ((uint32_t)0x11000000)
+#define RCC_RNGCCLK_SYSCLK_DIV19 ((uint32_t)0x12000000)
+#define RCC_RNGCCLK_SYSCLK_DIV20 ((uint32_t)0x13000000)
+#define RCC_RNGCCLK_SYSCLK_DIV21 ((uint32_t)0x14000000)
+#define RCC_RNGCCLK_SYSCLK_DIV22 ((uint32_t)0x15000000)
+#define RCC_RNGCCLK_SYSCLK_DIV23 ((uint32_t)0x16000000)
+#define RCC_RNGCCLK_SYSCLK_DIV24 ((uint32_t)0x17000000)
+#define RCC_RNGCCLK_SYSCLK_DIV25 ((uint32_t)0x18000000)
+#define RCC_RNGCCLK_SYSCLK_DIV26 ((uint32_t)0x19000000)
+#define RCC_RNGCCLK_SYSCLK_DIV27 ((uint32_t)0x1A000000)
+#define RCC_RNGCCLK_SYSCLK_DIV28 ((uint32_t)0x1B000000)
+#define RCC_RNGCCLK_SYSCLK_DIV29 ((uint32_t)0x1C000000)
+#define RCC_RNGCCLK_SYSCLK_DIV30 ((uint32_t)0x1D000000)
+#define RCC_RNGCCLK_SYSCLK_DIV31 ((uint32_t)0x1E000000)
+#define RCC_RNGCCLK_SYSCLK_DIV32 ((uint32_t)0x1F000000)
+#define IS_RCC_RNGCCLKPRE(DIV)                                                                                         \
+    (((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV3)    \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV6) \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV9) \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV10) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV11)                                     \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV12) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV13)                                     \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV14) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV15)                                     \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV16) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV17)                                     \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV18) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV19)                                     \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV20) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV21)                                     \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV22) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV23)                                     \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV24) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV25)                                     \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV26) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV27)                                     \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV28) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV29)                                     \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV30) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV31)                                     \
+     || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV32))
+
+#define RCC_ADC1MCLK_SRC_HSI         ((uint32_t)0x00000000)
+#define RCC_ADC1MCLK_SRC_HSE         ((uint32_t)0x00020000)
+#define IS_RCC_ADC1MCLKSRC(ADC1MCLK) (((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSI) || ((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSE))
+
+#define RCC_ADC1MCLK_DIV1  ((uint32_t)0x00000000)
+#define RCC_ADC1MCLK_DIV2  ((uint32_t)0x00001000)
+#define RCC_ADC1MCLK_DIV3  ((uint32_t)0x00002000)
+#define RCC_ADC1MCLK_DIV4  ((uint32_t)0x00003000)
+#define RCC_ADC1MCLK_DIV5  ((uint32_t)0x00004000)
+#define RCC_ADC1MCLK_DIV6  ((uint32_t)0x00005000)
+#define RCC_ADC1MCLK_DIV7  ((uint32_t)0x00006000)
+#define RCC_ADC1MCLK_DIV8  ((uint32_t)0x00007000)
+#define RCC_ADC1MCLK_DIV9  ((uint32_t)0x00008000)
+#define RCC_ADC1MCLK_DIV10 ((uint32_t)0x00009000)
+#define RCC_ADC1MCLK_DIV11 ((uint32_t)0x0000A000)
+#define RCC_ADC1MCLK_DIV12 ((uint32_t)0x0000B000)
+#define RCC_ADC1MCLK_DIV13 ((uint32_t)0x0000C000)
+#define RCC_ADC1MCLK_DIV14 ((uint32_t)0x0000D000)
+#define RCC_ADC1MCLK_DIV15 ((uint32_t)0x0000E000)
+#define RCC_ADC1MCLK_DIV16 ((uint32_t)0x0000F000)
+#define RCC_ADC1MCLK_DIV17 ((uint32_t)0x00010000)
+#define RCC_ADC1MCLK_DIV18 ((uint32_t)0x00011000)
+#define RCC_ADC1MCLK_DIV19 ((uint32_t)0x00012000)
+#define RCC_ADC1MCLK_DIV20 ((uint32_t)0x00013000)
+#define RCC_ADC1MCLK_DIV21 ((uint32_t)0x00014000)
+#define RCC_ADC1MCLK_DIV22 ((uint32_t)0x00015000)
+#define RCC_ADC1MCLK_DIV23 ((uint32_t)0x00016000)
+#define RCC_ADC1MCLK_DIV24 ((uint32_t)0x00017000)
+#define RCC_ADC1MCLK_DIV25 ((uint32_t)0x00018000)
+#define RCC_ADC1MCLK_DIV26 ((uint32_t)0x00019000)
+#define RCC_ADC1MCLK_DIV27 ((uint32_t)0x0001A000)
+#define RCC_ADC1MCLK_DIV28 ((uint32_t)0x0001B000)
+#define RCC_ADC1MCLK_DIV29 ((uint32_t)0x0001C000)
+#define RCC_ADC1MCLK_DIV30 ((uint32_t)0x0001D000)
+#define RCC_ADC1MCLK_DIV31 ((uint32_t)0x0001E000)
+#define RCC_ADC1MCLK_DIV32 ((uint32_t)0x0001F000)
+#define IS_RCC_ADC1MCLKPRE(DIV)                                                                                        \
+    (((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3)                      \
+     || ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6)                   \
+     || ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9)                   \
+     || ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12)                \
+     || ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15)                \
+     || ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18)                \
+     || ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21)                \
+     || ((DIV) == RCC_ADC1MCLK_DIV22) || ((DIV) == RCC_ADC1MCLK_DIV23) || ((DIV) == RCC_ADC1MCLK_DIV24)                \
+     || ((DIV) == RCC_ADC1MCLK_DIV25) || ((DIV) == RCC_ADC1MCLK_DIV26) || ((DIV) == RCC_ADC1MCLK_DIV27)                \
+     || ((DIV) == RCC_ADC1MCLK_DIV28) || ((DIV) == RCC_ADC1MCLK_DIV29) || ((DIV) == RCC_ADC1MCLK_DIV30)                \
+     || ((DIV) == RCC_ADC1MCLK_DIV31) || ((DIV) == RCC_ADC1MCLK_DIV32))
+
+#define RCC_ADCPLLCLK_DISABLE    ((uint32_t)0xFFFFFEFF)
+#define RCC_ADCPLLCLK_DIV1       ((uint32_t)0x00000100)
+#define RCC_ADCPLLCLK_DIV2       ((uint32_t)0x00000110)
+#define RCC_ADCPLLCLK_DIV4       ((uint32_t)0x00000120)
+#define RCC_ADCPLLCLK_DIV6       ((uint32_t)0x00000130)
+#define RCC_ADCPLLCLK_DIV8       ((uint32_t)0x00000140)
+#define RCC_ADCPLLCLK_DIV10      ((uint32_t)0x00000150)
+#define RCC_ADCPLLCLK_DIV12      ((uint32_t)0x00000160)
+#define RCC_ADCPLLCLK_DIV16      ((uint32_t)0x00000170)
+#define RCC_ADCPLLCLK_DIV32      ((uint32_t)0x00000180)
+#define RCC_ADCPLLCLK_DIV64      ((uint32_t)0x00000190)
+#define RCC_ADCPLLCLK_DIV128     ((uint32_t)0x000001A0)
+#define RCC_ADCPLLCLK_DIV256     ((uint32_t)0x000001B0)
+#define RCC_ADCPLLCLK_DIV_OTHERS ((uint32_t)0x000001C0)
+#define IS_RCC_ADCPLLCLKPRE(DIV)                                                                                       \
+    (((DIV) == RCC_ADCPLLCLK_DIV1) || ((DIV) == RCC_ADCPLLCLK_DIV2) || ((DIV) == RCC_ADCPLLCLK_DIV4)                   \
+     || ((DIV) == RCC_ADCPLLCLK_DIV6) || ((DIV) == RCC_ADCPLLCLK_DIV8) || ((DIV) == RCC_ADCPLLCLK_DIV10)               \
+     || ((DIV) == RCC_ADCPLLCLK_DIV12) || ((DIV) == RCC_ADCPLLCLK_DIV16) || ((DIV) == RCC_ADCPLLCLK_DIV32)             \
+     || ((DIV) == RCC_ADCPLLCLK_DIV64) || ((DIV) == RCC_ADCPLLCLK_DIV128) || ((DIV) == RCC_ADCPLLCLK_DIV256)           \
+     || (((DIV)&RCC_ADCPLLCLK_DIV_OTHERS) == 0x000001C0))
+
+#define RCC_ADCHCLK_DIV1       ((uint32_t)0x00000000)
+#define RCC_ADCHCLK_DIV2       ((uint32_t)0x00000001)
+#define RCC_ADCHCLK_DIV4       ((uint32_t)0x00000002)
+#define RCC_ADCHCLK_DIV6       ((uint32_t)0x00000003)
+#define RCC_ADCHCLK_DIV8       ((uint32_t)0x00000004)
+#define RCC_ADCHCLK_DIV10      ((uint32_t)0x00000005)
+#define RCC_ADCHCLK_DIV12      ((uint32_t)0x00000006)
+#define RCC_ADCHCLK_DIV16      ((uint32_t)0x00000007)
+#define RCC_ADCHCLK_DIV32      ((uint32_t)0x00000008)
+#define RCC_ADCHCLK_DIV_OTHERS ((uint32_t)0x00000008)
+#define IS_RCC_ADCHCLKPRE(DIV)                                                                                         \
+    (((DIV) == RCC_ADCHCLK_DIV1) || ((DIV) == RCC_ADCHCLK_DIV2) || ((DIV) == RCC_ADCHCLK_DIV4)                         \
+     || ((DIV) == RCC_ADCHCLK_DIV6) || ((DIV) == RCC_ADCHCLK_DIV8) || ((DIV) == RCC_ADCHCLK_DIV10)                     \
+     || ((DIV) == RCC_ADCHCLK_DIV12) || ((DIV) == RCC_ADCHCLK_DIV16) || ((DIV) == RCC_ADCHCLK_DIV32)                   \
+     || (((DIV)&RCC_ADCHCLK_DIV_OTHERS) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_CFGR3_Config
+ * @{
+ */
+
+#define RCC_TRNG1MCLK_ENABLE  ((uint32_t)0x00040000)
+#define RCC_TRNG1MCLK_DISABLE ((uint32_t)0xFFFBFFFF)
+
+#define RCC_TRNG1MCLK_SRC_HSI ((uint32_t)0x00000000)
+#define RCC_TRNG1MCLK_SRC_HSE ((uint32_t)0x00020000)
+#define IS_RCC_TRNG1MCLK_SRC(TRNG1MCLK)                                                                                \
+    (((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSI) || ((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSE))
+
+#define RCC_TRNG1MCLK_DIV2  ((uint32_t)0x00000800)
+#define RCC_TRNG1MCLK_DIV4  ((uint32_t)0x00001000)
+#define RCC_TRNG1MCLK_DIV6  ((uint32_t)0x00001800)
+#define RCC_TRNG1MCLK_DIV8  ((uint32_t)0x00002000)
+#define RCC_TRNG1MCLK_DIV10 ((uint32_t)0x00002800)
+#define RCC_TRNG1MCLK_DIV12 ((uint32_t)0x00003000)
+#define RCC_TRNG1MCLK_DIV14 ((uint32_t)0x00003800)
+#define RCC_TRNG1MCLK_DIV16 ((uint32_t)0x00004000)
+#define RCC_TRNG1MCLK_DIV18 ((uint32_t)0x00004800)
+#define RCC_TRNG1MCLK_DIV20 ((uint32_t)0x00005000)
+#define RCC_TRNG1MCLK_DIV22 ((uint32_t)0x00005800)
+#define RCC_TRNG1MCLK_DIV24 ((uint32_t)0x00006000)
+#define RCC_TRNG1MCLK_DIV26 ((uint32_t)0x00006800)
+#define RCC_TRNG1MCLK_DIV28 ((uint32_t)0x00007000)
+#define RCC_TRNG1MCLK_DIV30 ((uint32_t)0x00007800)
+#define RCC_TRNG1MCLK_DIV32 ((uint32_t)0x00008000)
+#define RCC_TRNG1MCLK_DIV34 ((uint32_t)0x00008800)
+#define RCC_TRNG1MCLK_DIV36 ((uint32_t)0x00009000)
+#define RCC_TRNG1MCLK_DIV38 ((uint32_t)0x00009800)
+#define RCC_TRNG1MCLK_DIV40 ((uint32_t)0x0000A000)
+#define RCC_TRNG1MCLK_DIV42 ((uint32_t)0x0000A800)
+#define RCC_TRNG1MCLK_DIV44 ((uint32_t)0x0000B000)
+#define RCC_TRNG1MCLK_DIV46 ((uint32_t)0x0000B800)
+#define RCC_TRNG1MCLK_DIV48 ((uint32_t)0x0000C000)
+#define RCC_TRNG1MCLK_DIV50 ((uint32_t)0x0000C800)
+#define RCC_TRNG1MCLK_DIV52 ((uint32_t)0x0000D000)
+#define RCC_TRNG1MCLK_DIV54 ((uint32_t)0x0000D800)
+#define RCC_TRNG1MCLK_DIV56 ((uint32_t)0x0000E000)
+#define RCC_TRNG1MCLK_DIV58 ((uint32_t)0x0000E800)
+#define RCC_TRNG1MCLK_DIV60 ((uint32_t)0x0000F000)
+#define RCC_TRNG1MCLK_DIV62 ((uint32_t)0x0000F800)
+#define IS_RCC_TRNG1MCLKPRE(VAL)                                                                                       \
+    (((VAL) == RCC_TRNG1MCLK_DIV2) || ((VAL) == RCC_TRNG1MCLK_DIV4) || ((VAL) == RCC_TRNG1MCLK_DIV6)                \
+     || ((VAL) == RCC_TRNG1MCLK_DIV8) || ((VAL) == RCC_TRNG1MCLK_DIV10) || ((VAL) == RCC_TRNG1MCLK_DIV12)              \
+     || ((VAL) == RCC_TRNG1MCLK_DIV14) || ((VAL) == RCC_TRNG1MCLK_DIV16) || ((VAL) == RCC_TRNG1MCLK_DIV18)             \
+     || ((VAL) == RCC_TRNG1MCLK_DIV20) || ((VAL) == RCC_TRNG1MCLK_DIV22) || ((VAL) == RCC_TRNG1MCLK_DIV24)             \
+     || ((VAL) == RCC_TRNG1MCLK_DIV26) || ((VAL) == RCC_TRNG1MCLK_DIV28) || ((VAL) == RCC_TRNG1MCLK_DIV30)             \
+     || ((VAL) == RCC_TRNG1MCLK_DIV32) || ((VAL) == RCC_TRNG1MCLK_DIV34) || ((VAL) == RCC_TRNG1MCLK_DIV36)             \
+     || ((VAL) == RCC_TRNG1MCLK_DIV38) || ((VAL) == RCC_TRNG1MCLK_DIV40) || ((VAL) == RCC_TRNG1MCLK_DIV42)             \
+     || ((VAL) == RCC_TRNG1MCLK_DIV44) || ((VAL) == RCC_TRNG1MCLK_DIV46) || ((VAL) == RCC_TRNG1MCLK_DIV48)             \
+     || ((VAL) == RCC_TRNG1MCLK_DIV50) || ((VAL) == RCC_TRNG1MCLK_DIV52) || ((VAL) == RCC_TRNG1MCLK_DIV54)             \
+     || ((VAL) == RCC_TRNG1MCLK_DIV56) || ((VAL) == RCC_TRNG1MCLK_DIV58) || ((VAL) == RCC_TRNG1MCLK_DIV60)             \
+     || ((VAL) == RCC_TRNG1MCLK_DIV62))
+
+#define RCC_UCDR_ENABLE  ((uint32_t)0x00000080)
+#define RCC_UCDR_DISABLE ((uint32_t)0xFFFFFF7F)
+
+#define RCC_UCDR300MSource_MASK  ((uint32_t)0xFFFFFDFF)
+#define RCC_UCDR300M_SRC_OSC300M ((uint32_t)0x00000000)
+#define RCC_UCDR300M_SRC_PLLVCO  ((uint32_t)0x00000200)
+#define IS_RCC_UCDR300M_SRC(UCDR300MCLK)                                                                                \
+    (((UCDR300MCLK) == RCC_UCDR300M_SRC_OSC300M) || ((UCDR300MCLK) == RCC_UCDR300M_SRC_PLLVCO))
+
+#define RCC_USBXTALESSMode_MASK ((uint32_t)0xFFFFFEFF)
+#define RCC_USBXTALESS_MODE     ((uint32_t)0x00000000)
+#define RCC_USBXTALESS_LESSMODE ((uint32_t)0x00000100)
+#define IS_RCC_USBXTALESS_MODE(USBXTALESS)                                                                                \
+    (((USBXTALESS) == RCC_USBXTALESS_MODE) || ((USBXTALESS) == RCC_USBXTALESS_LESSMODE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LSE_configuration
+ * @{
+ */
+
+#define RCC_LSE_DISABLE ((uint32_t)0x00000000)
+#define RCC_LSE_ENABLE  ((uint32_t)0x00000001)
+#define RCC_LSE_BYPASS  ((uint32_t)0x00000004)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || ((LSE) == RCC_LSE_BYPASS))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_clock_source
+ * @{
+ */
+
+#define RCC_RTCCLK_SRC_NONE       ((uint32_t)0x00000000)
+#define RCC_RTCCLK_SRC_LSE        ((uint32_t)0x00000100)
+#define RCC_RTCCLK_SRC_LSI        ((uint32_t)0x00000200)
+#define RCC_RTCCLK_SRC_HSE_DIV32  ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SRC(SOURCE)                                                                                      \
+    (((SOURCE) == RCC_RTCCLK_SRC_NONE) || ((SOURCE) == RCC_RTCCLK_SRC_LSE) || ((SOURCE) == RCC_RTCCLK_SRC_LSI)         \
+     || ((SOURCE) == RCC_RTCCLK_SRC_HSE_DIV32))
+/**
+ * @}
+ */
+
+/** @addtogroup LSX_clock_source
+ * @{
+ */
+
+#define RCC_LSXCLK_SRC_LSI        ((uint32_t)0x00000000)
+#define RCC_LSXCLK_SRC_LSE        ((uint32_t)0x00000020)
+#define IS_RCC_LSXCLK_SRC(SOURCE)                                                                                      \
+    (((SOURCE) == RCC_LSXCLK_SRC_LSI) || ((SOURCE) == RCC_LSXCLK_SRC_LSE))
+/**
+ * @}
+ */
+
+/** @addtogroup AHB_peripheral
+ * @{
+ */
+
+#define RCC_AHB_PERIPH_DMA    ((uint32_t)0x00000001)
+#define RCC_AHB_PERIPH_SRAM   ((uint32_t)0x00000004)
+#define RCC_AHB_PERIPH_FLITF  ((uint32_t)0x00000010)
+#define RCC_AHB_PERIPH_CRC    ((uint32_t)0x00000040)
+#define RCC_AHB_PERIPH_RNGC   ((uint32_t)0x00000200)
+#define RCC_AHB_PERIPH_SAC    ((uint32_t)0x00000800)
+#define RCC_AHB_PERIPH_ADC    ((uint32_t)0x00001000)
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH)&0xFFFFE5AA) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup APB2_peripheral
+ * @{
+ */
+
+#define RCC_APB2_PERIPH_AFIO   ((uint32_t)0x00000001)
+#define RCC_APB2_PERIPH_GPIOA  ((uint32_t)0x00000004)
+#define RCC_APB2_PERIPH_GPIOB  ((uint32_t)0x00000008)
+#define RCC_APB2_PERIPH_GPIOC  ((uint32_t)0x00000010)
+#define RCC_APB2_PERIPH_GPIOD  ((uint32_t)0x00000020)
+#define RCC_APB2_PERIPH_TIM1   ((uint32_t)0x00000800)
+#define RCC_APB2_PERIPH_SPI1   ((uint32_t)0x00001000)
+#define RCC_APB2_PERIPH_TIM8   ((uint32_t)0x00002000)
+#define RCC_APB2_PERIPH_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2_PERIPH_UART4  ((uint32_t)0x00020000)
+#define RCC_APB2_PERIPH_UART5  ((uint32_t)0x00040000)
+#define RCC_APB2_PERIPH_SPI2   ((uint32_t)0x00080000)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH)&0xFFF187C2) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup APB1_peripheral
+ * @{
+ */
+
+#define RCC_APB1_PERIPH_TIM2      ((uint32_t)0x00000001)
+#define RCC_APB1_PERIPH_TIM3      ((uint32_t)0x00000002)
+#define RCC_APB1_PERIPH_TIM4      ((uint32_t)0x00000004)
+#define RCC_APB1_PERIPH_TIM5      ((uint32_t)0x00000008)
+#define RCC_APB1_PERIPH_TIM6      ((uint32_t)0x00000010)
+#define RCC_APB1_PERIPH_TIM7      ((uint32_t)0x00000020)
+#define RCC_APB1_PERIPH_COMP      ((uint32_t)0x00000040)
+#define RCC_APB1_PERIPH_COMP_FILT ((uint32_t)0x00000080)
+#define RCC_APB1_PERIPH_AFEC      ((uint32_t)0x00000100)
+#define RCC_APB1_PERIPH_TIM9      ((uint32_t)0x00000200)
+#define RCC_APB1_PERIPH_TSC       ((uint32_t)0x00000400)
+#define RCC_APB1_PERIPH_WWDG      ((uint32_t)0x00000800)
+#define RCC_APB1_PERIPH_USART2    ((uint32_t)0x00020000)
+#define RCC_APB1_PERIPH_USART3    ((uint32_t)0x00040000)
+#define RCC_APB1_PERIPH_I2C1      ((uint32_t)0x00200000)
+#define RCC_APB1_PERIPH_I2C2      ((uint32_t)0x00400000)
+#define RCC_APB1_PERIPH_USB       ((uint32_t)0x00800000)
+#define RCC_APB1_PERIPH_CAN       ((uint32_t)0x02000000)
+#define RCC_APB1_PERIPH_PWR       ((uint32_t)0x10000000)
+#define RCC_APB1_PERIPH_DAC       ((uint32_t)0x20000000)
+#define RCC_APB1_PERIPH_OPAMP     ((uint32_t)0x80000000)
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH)&0x4D19F000) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RET_peripheral
+ * @{
+ */
+
+#define RCC_RET_PERIPH_LPTIM  ((uint32_t)0x00000040)
+#define RCC_RET_PERIPH_LPUART ((uint32_t)0x00000080)
+
+#define IS_RCC_RET_PERIPH(PERIPH) ((((PERIPH)&0xFFFFFF3F) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPTIM
+ * @{
+ */
+#define RCC_LPTIMCLK_SRC_MASK  ((uint32_t)0xFFFFFFF8)
+
+#define RCC_LPTIMCLK_SRC_APB1  ((uint32_t)0x00000000)
+#define RCC_LPTIMCLK_SRC_LSI   ((uint32_t)0x00000001)
+#define RCC_LPTIMCLK_SRC_HSI   ((uint32_t)0x00000002)
+#define RCC_LPTIMCLK_SRC_LSE   ((uint32_t)0x00000003)
+#define RCC_LPTIMCLK_SRC_COMP1 ((uint32_t)0x00000004)
+#define RCC_LPTIMCLK_SRC_COMP2 ((uint32_t)0x00000005)
+
+#define IS_RCC_LPTIM_CLK(LPTIMCLK) (((LPTIMCLK) == RCC_LPTIMCLK_SRC_APB1)   \
+                                 || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSI)    \
+                                 || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_HSI)    \
+                                 || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_LSE)    \
+                                 || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP1)  \
+                                 || ((LPTIMCLK) == RCC_LPTIMCLK_SRC_COMP2))
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART
+ * @{
+ */
+#define RCC_LPUARTCLK_SRC_MASK   ((uint32_t)0xFFFFFFE7)
+
+#define RCC_LPUARTCLK_SRC_APB1   ((uint32_t)0x00000000)
+#define RCC_LPUARTCLK_SRC_SYSCLK ((uint32_t)0x00000008)
+#define RCC_LPUARTCLK_SRC_HSI    ((uint32_t)0x00000010)
+#define RCC_LPUARTCLK_SRC_LSE    ((uint32_t)0x00000018)
+
+#define IS_RCC_LPUART_CLK(LPUARTCLK) (((LPUARTCLK)&0xFFFFFFE7) == 0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_CTRLSTS
+ * @{
+ */
+
+#define SRAM1_PARITYERROR_INT ((uint32_t)0x00000001)
+#define SRAM2_PARITYERROR_INT ((uint32_t)0x00000008)
+#define IS_RCC_SRAMERRORINT(PARITYERROR_INT) (((PARITYERROR_INT) == SRAM1_PARITYERROR_INT) \
+                                           || ((PARITYERROR_INT) == SRAM2_PARITYERROR_INT))
+
+#define SRAM1_PARITYERROR_RESET ((uint32_t)0x00000002)
+#define SRAM2_PARITYERROR_RESET ((uint32_t)0x00000010)
+#define IS_RCC_SRAMERRORRESET(PARITYERROR_RESET) (((PARITYERROR_RESET) == SRAM1_PARITYERROR_RESET) \
+                                               || ((PARITYERROR_RESET) == SRAM2_PARITYERROR_RESET))
+
+#define SRAM1_PARITYERROR_FLAG ((uint32_t)0x00000004)
+#define SRAM2_PARITYERROR_FLAG ((uint32_t)0x00000020)
+#define IS_RCC_SRAMERRORFLAG(PARITYERROR_FLAG) (((PARITYERROR_FLAG) == SRAM1_PARITYERROR_FLAG) \
+                                                 || ((PARITYERROR_FLAG) == SRAM2_PARITYERROR_FLAG))
+
+/**
+ * @}
+ */
+
+#define RCC_MCO_CLK_NUM0  ((uint32_t)0x00000000)
+#define RCC_MCO_CLK_NUM1  ((uint32_t)0x10000000)
+#define RCC_MCO_CLK_NUM2  ((uint32_t)0x20000000)
+#define RCC_MCO_CLK_NUM3  ((uint32_t)0x30000000)
+#define RCC_MCO_CLK_NUM4  ((uint32_t)0x40000000)
+#define RCC_MCO_CLK_NUM5  ((uint32_t)0x50000000)
+#define RCC_MCO_CLK_NUM6  ((uint32_t)0x60000000)
+#define RCC_MCO_CLK_NUM7  ((uint32_t)0x70000000)
+#define RCC_MCO_CLK_NUM8  ((uint32_t)0x80000000)
+#define RCC_MCO_CLK_NUM9  ((uint32_t)0x90000000)
+#define RCC_MCO_CLK_NUM10 ((uint32_t)0xA0000000)
+#define RCC_MCO_CLK_NUM11 ((uint32_t)0xB0000000)
+#define RCC_MCO_CLK_NUM12 ((uint32_t)0xC0000000)
+#define RCC_MCO_CLK_NUM13 ((uint32_t)0xD0000000)
+#define RCC_MCO_CLK_NUM14 ((uint32_t)0xE0000000)
+#define RCC_MCO_CLK_NUM15 ((uint32_t)0xF0000000)
+#define IS_RCC_MCOCLKPRE(NUM)                                                                              \
+       (((NUM) == RCC_MCO_CLK_NUM0)  || ((NUM) == RCC_MCO_CLK_NUM1)  || ((NUM) == RCC_MCO_CLK_NUM2)        \
+     || ((NUM) == RCC_MCO_CLK_NUM3)  || ((NUM) == RCC_MCO_CLK_NUM4)  || ((NUM) == RCC_MCO_CLK_NUM5)        \
+     || ((NUM) == RCC_MCO_CLK_NUM6)  || ((NUM) == RCC_MCO_CLK_NUM7)  || ((NUM) == RCC_MCO_CLK_NUM8)        \
+     || ((NUM) == RCC_MCO_CLK_NUM9)  || ((NUM) == RCC_MCO_CLK_NUM10) || ((NUM) == RCC_MCO_CLK_NUM11)       \
+     || ((NUM) == RCC_MCO_CLK_NUM12) || ((NUM) == RCC_MCO_CLK_NUM13) || ((NUM) == RCC_MCO_CLK_NUM14)       \
+     || ((NUM) == RCC_MCO_CLK_NUM15))
+
+/** @addtogroup Clock_source_to_output_on_MCO_pin
+ * @{
+ */
+
+#define RCC_MCO_NOCLK       ((uint8_t)0x00)
+#define RCC_MCO_LSI         ((uint8_t)0x01)
+#define RCC_MCO_LSE         ((uint8_t)0x02)
+#define RCC_MCO_MSI         ((uint8_t)0x03)
+#define RCC_MCO_SYSCLK      ((uint8_t)0x04)
+#define RCC_MCO_HSI         ((uint8_t)0x05)
+#define RCC_MCO_HSE         ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK      ((uint8_t)0x07)
+
+#define IS_RCC_MCO(MCO)                                                                                              \
+    (((MCO) == RCC_MCO_NOCLK)  || ((MCO) == RCC_MCO_LSI) || ((MCO) == RCC_MCO_LSE) || ((MCO) == RCC_MCO_MSI)         \
+  || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_HSE) || ((MCO) == RCC_MCO_PLLCLK))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Flag
+ * @{
+ */
+#define RCC_CTRL_FLAG_HSIRDF        ((uint8_t)0x21)
+#define RCC_CTRL_FLAG_HSERDF        ((uint8_t)0x31)
+#define RCC_CTRL_FLAG_PLLRDF        ((uint8_t)0x39)
+#define RCC_LDCTRL_FLAG_LSERD       ((uint8_t)0x41)
+#define RCC_LDCTRL_FLAG_LSECLKSSF   ((uint8_t)0x44)
+#define RCC_LDCTRL_FLAG_BORRSTF     ((uint8_t)0x5C)
+#define RCC_LDCTRL_FLAG_LDEMCRSTF   ((uint8_t)0x5E)
+#define RCC_CTRLSTS_FLAG_LSIRD      ((uint8_t)0x61)
+#define RCC_CTRLSTS_FLAG_MSIRD      ((uint8_t)0x63)
+#define RCC_CTRLSTS_FLAG_RAMRSTF    ((uint8_t)0x77)
+#define RCC_CTRLSTS_FLAG_MMURSTF    ((uint8_t)0x79)
+#define RCC_CTRLSTS_FLAG_PINRSTF    ((uint8_t)0x7A)
+#define RCC_CTRLSTS_FLAG_PORRSTF    ((uint8_t)0x7B)
+#define RCC_CTRLSTS_FLAG_SFTRSTF    ((uint8_t)0x7C)
+#define RCC_CTRLSTS_FLAG_IWDGRSTF   ((uint8_t)0x7D)
+#define RCC_CTRLSTS_FLAG_WWDGRSTF   ((uint8_t)0x7E)
+#define RCC_CTRLSTS_FLAG_LPWRRSTF   ((uint8_t)0x7F)
+
+#define IS_RCC_FLAG(FLAG)                                                                                                       \
+    (((FLAG) == RCC_CTRL_FLAG_HSIRDF)       || ((FLAG) == RCC_CTRL_FLAG_HSERDF)        || ((FLAG) == RCC_CTRL_FLAG_PLLRDF)      \
+  || ((FLAG) == RCC_LDCTRL_FLAG_LSERD)      || ((FLAG) == RCC_LDCTRL_FLAG_LSECLKSSF)  || ((FLAG) == RCC_LDCTRL_FLAG_BORRSTF)  \
+  || ((FLAG) == RCC_LDCTRL_FLAG_LDEMCRSTF)  || ((FLAG) == RCC_CTRLSTS_FLAG_LSIRD)      || ((FLAG) == RCC_CTRLSTS_FLAG_MSIRD)    \
+  || ((FLAG) == RCC_CTRLSTS_FLAG_RAMRSTF)   || ((FLAG) == RCC_CTRLSTS_FLAG_MMURSTF)    || ((FLAG) == RCC_CTRLSTS_FLAG_PINRSTF)  \
+  || ((FLAG) == RCC_CTRLSTS_FLAG_PORRSTF)   || ((FLAG) == RCC_CTRLSTS_FLAG_SFTRSTF)    || ((FLAG) == RCC_CTRLSTS_FLAG_IWDGRSTF) \
+  || ((FLAG) == RCC_CTRLSTS_FLAG_WWDGRSTF)  || ((FLAG) == RCC_CTRLSTS_FLAG_LPWRRSTF))
+
+#define IS_RCC_CALIB_VALUE(VALUE) ((VALUE) <= 0x1F)
+#define IS_RCC_MSICALIB_VALUE(VALUE) ((VALUE) <= 0xFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+void RCC_DeInit(void);
+void RCC_ConfigHse(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitHseStable(void);
+void RCC_ConfigHsi(uint32_t RCC_HSI);
+ErrorStatus RCC_WaitHsiStable(void);
+void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue);
+void RCC_EnableHsi(FunctionalState Cmd);
+void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range);
+ErrorStatus RCC_WaitMsiStable(void);
+void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue);
+void RCC_EnableMsi(FunctionalState Cmd);
+void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK);
+void RCC_EnablePll(FunctionalState Cmd);
+
+void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSysclkSrc(void);
+void RCC_ConfigHclk(uint32_t RCC_SYSCLK);
+void RCC_ConfigPclk1(uint32_t RCC_HCLK);
+void RCC_ConfigPclk2(uint32_t RCC_HCLK);
+void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd);
+
+void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource);
+
+void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource);
+void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler);
+
+void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler);
+void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd);
+void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler);
+
+void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler);
+void RCC_EnableTrng1mClk(FunctionalState Cmd);
+
+void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd);
+
+void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode);
+
+void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd);
+void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd);
+
+void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource);
+uint32_t RCC_GetLSXClkSrc(void);
+
+void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource);
+uint32_t RCC_GetLPTIMClkSrc(void);
+void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource);
+uint32_t RCC_GetLPUARTClkSrc(void);
+
+void RCC_ConfigSRAMParityErrorInt(uint32_t SramInt, FunctionalState Cmd);
+void RCC_ConfigSRAMParityErrorRESET(uint32_t SramReset, FunctionalState Cmd);
+void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag);
+
+void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim);
+void RCC_EnableLsi(FunctionalState Cmd);
+void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource);
+void RCC_EnableRtcClk(FunctionalState Cmd);
+uint32_t RCC_GetRTCClkSrc(void);
+void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks);
+void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd);
+void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd);
+void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd);
+
+void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd);
+void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd);
+void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd);
+void RCC_EnableLowPowerReset(FunctionalState Cmd);
+void RCC_EnableClockSecuritySystem(FunctionalState Cmd);
+void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd);
+FlagStatus RCC_GetLSEClockSecuritySystemStatus(void);
+void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler);
+void RCC_ConfigMco(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClrFlag(void);
+INTStatus RCC_GetIntStatus(uint8_t RccInt);
+void RCC_ClrIntPendingBit(uint32_t RccClrInt);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_RCC_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rtc.h

@@ -0,0 +1,789 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_rtc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_RTC_H__
+#define __N32G43X_RTC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/**
+ * @brief  RTC Init structures definition
+ */
+typedef struct
+{
+    uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
+                             This parameter can be a value of @ref RTC_Hour_Formats */
+
+    uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+                               This parameter must be set to a value lower than 0x7F */
+
+    uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+                              This parameter must be set to a value lower than 0x7FFF */
+} RTC_InitType;
+
+/**
+ * @brief  RTC Time structure definition
+ */
+typedef struct
+{
+    uint8_t Hours; /*!< Specifies the RTC Time Hour.
+                       This parameter must be set to a value in the 0-12 range
+                       if the RTC_12HOUR_FORMAT is selected or 0-23 range if
+                       the RTC_24HOUR_FORMAT is selected. */
+
+    uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+                         This parameter must be set to a value in the 0-59 range. */
+
+    uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+                         This parameter must be set to a value in the 0-59 range. */
+
+    uint8_t H12; /*!< Specifies the RTC AM/PM Time.
+                     This parameter can be a value of @ref RTC_AM_PM_Definitions */
+} RTC_TimeType;
+
+/**
+ * @brief  RTC Date structure definition
+ */
+typedef struct
+{
+    uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+    uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+    uint8_t Date; /*!< Specifies the RTC Date.
+                      This parameter must be set to a value in the 1-31 range. */
+
+    uint8_t Year; /*!< Specifies the RTC Date Year.
+                      This parameter must be set to a value in the 0-99 range. */
+} RTC_DateType;
+
+/**
+ * @brief  RTC Alarm structure definition
+ */
+typedef struct
+{
+    RTC_TimeType AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+    uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+                            This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+    uint32_t DateWeekMode; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+    uint8_t DateWeekValue; /*!< Specifies the RTC Alarm Date/WeekDay.
+                                  If the Alarm Date is selected, this parameter
+                                  must be set to a value in the 1-31 range.
+                                  If the Alarm WeekDay is selected, this
+                                  parameter can be a value of @ref RTC_WeekDay_Definitions */
+} RTC_AlarmType;
+
+/** @addtogroup RTC_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup RTC_Hour_Formats
+ * @{
+ */
+#define RTC_24HOUR_FORMAT          ((uint32_t)0x00000000)
+#define RTC_12HOUR_FORMAT          ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_12HOUR_FORMAT) || ((FORMAT) == RTC_24HOUR_FORMAT))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Asynchronous_Predivider
+ * @{
+ */
+#define IS_RTC_PREDIV_ASYNCH(PREDIV) ((PREDIV) <= 0x7F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Synchronous_Predivider
+ * @{
+ */
+#define IS_RTC_PREDIV_SYNCH(PREDIV) ((PREDIV) <= 0x7FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Time_Definitions
+ * @{
+ */
+#define IS_RTC_12HOUR(HOUR)     (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_24HOUR(HOUR)     ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AM_PM_Definitions
+ * @{
+ */
+#define RTC_AM_H12     ((uint8_t)0x00)
+#define RTC_PM_H12     ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_AM_H12) || ((PM) == RTC_PM_H12))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Year_Date_Definitions
+ * @{
+ */
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Month_Date_Definitions
+ * @{
+ */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY   ((uint8_t)0x01)
+#define RTC_MONTH_FEBRURY   ((uint8_t)0x02)
+#define RTC_MONTH_MARCH     ((uint8_t)0x03)
+#define RTC_MONTH_APRIL     ((uint8_t)0x04)
+#define RTC_MONTH_MAY       ((uint8_t)0x05)
+#define RTC_MONTH_JUNE      ((uint8_t)0x06)
+#define RTC_MONTH_JULY      ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST    ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER   ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER  ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER  ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE)   (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_WeekDay_Definitions
+ * @{
+ */
+
+#define RTC_WEEKDAY_MONDAY    ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY   ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY  ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY    ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY  ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY    ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY)                                                                                        \
+    (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY)   \
+     || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)                                       \
+     || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Definitions
+ * @{
+ */
+#define IS_RTC_ALARM_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_WEEKDAY_WEEKDAY(WEEKDAY)                                                                          \
+    (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY)   \
+     || ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)                                       \
+     || ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AlarmDateWeekDay_Definitions
+ * @{
+ */
+#define RTC_ALARM_SEL_WEEKDAY_DATE    ((uint32_t)0x00000000)
+#define RTC_ALARM_SEL_WEEKDAY_WEEKDAY ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_WEEKDAY_SEL(SEL)                                                                                  \
+    (((SEL) == RTC_ALARM_SEL_WEEKDAY_DATE) || ((SEL) == RTC_ALARM_SEL_WEEKDAY_WEEKDAY))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_AlarmMask_Definitions
+ * @{
+ */
+#define RTC_ALARMMASK_NONE    ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_WEEKDAY ((uint32_t)0x80000000)
+#define RTC_ALARMMASK_HOURS   ((uint32_t)0x00800000)
+#define RTC_ALARMMASK_MINUTES ((uint32_t)0x00008000)
+#define RTC_ALARMMASK_SECONDS ((uint32_t)0x00000080)
+#define RTC_ALARMMASK_ALL     ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(INTEN)  (((INTEN)&0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarms_Definitions
+ * @{
+ */
+#define RTC_A_ALARM                ((uint32_t)0x00000100)
+#define RTC_B_ALARM                ((uint32_t)0x00000200)
+#define IS_RTC_ALARM_SEL(ALARM)    (((ALARM) == RTC_A_ALARM) || ((ALARM) == RTC_B_ALARM))
+#define IS_RTC_ALARM_ENABLE(ALARM) (((ALARM) & (RTC_A_ALARM | RTC_B_ALARM)) != (uint32_t)RESET)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+ * @{
+ */
+#define RTC_SUBS_MASK_ALL                                                                                              \
+    ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.                                                        \
+                                         There is no comparison on sub seconds                                         \
+                                         for Alarm */
+#define RTC_SUBS_MASK_SS14_1                                                                                           \
+    ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm                                                       \
+                                         comparison. Only SS[0] is compared. */
+#define RTC_SUBS_MASK_SS14_2                                                                                           \
+    ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm                                                       \
+                                         comparison. Only SS[1:0] are compared */
+#define RTC_SUBS_MASK_SS14_3                                                                                           \
+    ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm                                                       \
+                                         comparison. Only SS[2:0] are compared */
+#define RTC_SUBS_MASK_SS14_4                                                                                           \
+    ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm                                                       \
+                                         comparison. Only SS[3:0] are compared */
+#define RTC_SUBS_MASK_SS14_5                                                                                           \
+    ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm                                                       \
+                                         comparison. Only SS[4:0] are compared */
+#define RTC_SUBS_MASK_SS14_6                                                                                           \
+    ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm                                                       \
+                                         comparison. Only SS[5:0] are compared */
+#define RTC_SUBS_MASK_SS14_7                                                                                           \
+    ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm                                                       \
+                                         comparison. Only SS[6:0] are compared */
+#define RTC_SUBS_MASK_SS14_8                                                                                           \
+    ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm                                                       \
+                                         comparison. Only SS[7:0] are compared */
+#define RTC_SUBS_MASK_SS14_9                                                                                           \
+    ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm                                                       \
+                                         comparison. Only SS[8:0] are compared */
+#define RTC_SUBS_MASK_SS14_10                                                                                          \
+    ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm                                                      \
+                                         comparison. Only SS[9:0] are compared */
+#define RTC_SUBS_MASK_SS14_11                                                                                          \
+    ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm                                                      \
+                                         comparison. Only SS[10:0] are compared */
+#define RTC_SUBS_MASK_SS14_12                                                                                          \
+    ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm                                                      \
+                                         comparison.Only SS[11:0] are compared */
+#define RTC_SUBS_MASK_SS14_13                                                                                          \
+    ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm                                                      \
+                                         comparison. Only SS[12:0] are compared */
+#define RTC_SUBS_MASK_SS14_14                                                                                          \
+    ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm                                                          \
+                                      comparison.Only SS[13:0] are compared */
+#define RTC_SUBS_MASK_NONE                                                                                             \
+    ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match                                                   \
+                                         to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK_MODE(INTEN)                                                                       \
+    (((INTEN) == RTC_SUBS_MASK_ALL) || ((INTEN) == RTC_SUBS_MASK_SS14_1) || ((INTEN) == RTC_SUBS_MASK_SS14_2)          \
+     || ((INTEN) == RTC_SUBS_MASK_SS14_3) || ((INTEN) == RTC_SUBS_MASK_SS14_4) || ((INTEN) == RTC_SUBS_MASK_SS14_5)    \
+     || ((INTEN) == RTC_SUBS_MASK_SS14_6) || ((INTEN) == RTC_SUBS_MASK_SS14_7) || ((INTEN) == RTC_SUBS_MASK_SS14_8)    \
+     || ((INTEN) == RTC_SUBS_MASK_SS14_9) || ((INTEN) == RTC_SUBS_MASK_SS14_10) || ((INTEN) == RTC_SUBS_MASK_SS14_11)  \
+     || ((INTEN) == RTC_SUBS_MASK_SS14_12) || ((INTEN) == RTC_SUBS_MASK_SS14_13) || ((INTEN) == RTC_SUBS_MASK_SS14_14) \
+     || ((INTEN) == RTC_SUBS_MASK_NONE))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Alarm_Sub_Seconds_Value
+ * @{
+ */
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Wakeup_Timer_Definitions
+ * @{
+ */
+#define RTC_WKUPCLK_RTCCLK_DIV16   ((uint32_t)0x00000000)
+#define RTC_WKUPCLK_RTCCLK_DIV8    ((uint32_t)0x00000001)
+#define RTC_WKUPCLK_RTCCLK_DIV4    ((uint32_t)0x00000002)
+#define RTC_WKUPCLK_RTCCLK_DIV2    ((uint32_t)0x00000003)
+#define RTC_WKUPCLK_CK_SPRE_16BITS ((uint32_t)0x00000004)
+#define RTC_WKUPCLK_CK_SPRE_17BITS ((uint32_t)0x00000006)
+#define IS_RTC_WKUP_CLOCK(CLOCK)                                                                                       \
+    (((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV16) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV8)                                     \
+     || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV4) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV2)                                   \
+     || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_16BITS) || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_17BITS))
+#define IS_RTC_WKUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Time_Stamp_Edges_definitions
+ * @{
+ */
+#define RTC_TIMESTAMP_EDGE_RISING  ((uint32_t)0x00000000)
+#define RTC_TIMESTAMP_EDGE_FALLING ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE_MODE(EDGE)                                                                               \
+    (((EDGE) == RTC_TIMESTAMP_EDGE_RISING) || ((EDGE) == RTC_TIMESTAMP_EDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_selection_Definitions
+ * @{
+ */
+#define RTC_OUTPUT_DIS  ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALA  ((uint32_t)0x00200000)
+#define RTC_OUTPUT_ALB  ((uint32_t)0x00400000)
+#define RTC_OUTPUT_WKUP ((uint32_t)0x00600000)
+
+#define IS_RTC_OUTPUT_MODE(OUTPUT)                                                                                     \
+    (((OUTPUT) == RTC_OUTPUT_DIS) || ((OUTPUT) == RTC_OUTPUT_ALA) || ((OUTPUT) == RTC_OUTPUT_ALB)                      \
+     || ((OUTPUT) == RTC_OUTPUT_WKUP))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_Polarity_Definitions
+ * @{
+ */
+#define RTC_OUTPOL_HIGH        ((uint32_t)0x00000000)
+#define RTC_OUTPOL_LOW         ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPOL_HIGH) || ((POL) == RTC_OUTPOL_LOW))
+/**
+ * @}
+ */
+
+
+/** @addtogroup RTC_Calib_Output_selection_Definitions
+ * @{
+ */
+#define RTC_CALIB_OUTPUT_256HZ      ((uint32_t)0x00000000)
+#define RTC_CALIB_OUTPUT_1HZ        ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIB_OUTPUT_256HZ) || ((OUTPUT) == RTC_CALIB_OUTPUT_1HZ))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_period_Definitions
+ * @{
+ */
+#define SMOOTH_CALIB_32SEC                                                                                             \
+    ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation                                               \
+                                    period is 32s,  else 2exp20 RTCCLK seconds */
+#define SMOOTH_CALIB_16SEC                                                                                             \
+    ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation                                               \
+                                    period is 16s, else 2exp19 RTCCLK seconds */
+#define SMOOTH_CALIB_8SEC                                                                                              \
+    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation                                               \
+                                    period is 8s, else 2exp18 RTCCLK seconds */
+#define IS_RTC_SMOOTH_CALIB_PERIOD_SEL(PERIOD)                                                                         \
+    (((PERIOD) == SMOOTH_CALIB_32SEC) || ((PERIOD) == SMOOTH_CALIB_16SEC) || ((PERIOD) == SMOOTH_CALIB_8SEC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_Plus_pulses_Definitions
+ * @{
+ */
+#define RTC_SMOOTH_CALIB_PLUS_PULSES_SET                                                                               \
+    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added                                                     \
+                        during a X -second window = Y - CALM[8:0].                                                     \
+                         with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTH_CALIB_PLUS_PULSES__RESET                                                                            \
+    ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited                                                \
+                        during a 32-second window =   CALM[8:0]. */
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS)                                                                                 \
+    (((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES_SET) || ((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES__RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Smooth_calib_Minus_pulses_Definitions
+ * @{
+ */
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_DayLightSaving_Definitions
+ * @{
+ */
+#define RTC_DAYLIGHT_SAVING_SUB1H    ((uint32_t)0x00020000)
+#define RTC_DAYLIGHT_SAVING_ADD1H    ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHT_SAVING_SUB1H) || ((SAVE) == RTC_DAYLIGHT_SAVING_ADD1H))
+
+#define RTC_STORE_OPERATION_RESET ((uint32_t)0x00000000)
+#define RTC_STORE_OPERATION_SET   ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION)                                                                              \
+    (((OPERATION) == RTC_STORE_OPERATION_RESET) || ((OPERATION) == RTC_STORE_OPERATION_SET))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Output_Type_ALARM_OUT
+ * @{
+ */
+#define RTC_OUTPUT_OPENDRAIN     ((uint32_t)0x00000000)
+#define RTC_OUTPUT_PUSHPULL      ((uint32_t)0x00000001)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPULL))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Add_1_Second_Parameter_Definitions
+ * @{
+ */
+#define RTC_SHIFT_ADD1S_DISABLE ((uint32_t)0x00000000)
+#define RTC_SHIFT_ADD1S_ENABLE  ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFT_ADD1S_DISABLE) || ((SEL) == RTC_SHIFT_ADD1S_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Substract_Fraction_Of_Second_Value
+ * @{
+ */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Input_parameter_format_definitions
+ * @{
+ */
+#define RTC_FORMAT_BIN        ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD        ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Flags_Definitions
+ * @{
+ */
+#define RTC_FLAG_RECPF  ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
+#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
+#define RTC_FLAG_TISOVF ((uint32_t)0x00001000)
+#define RTC_FLAG_TISF   ((uint32_t)0x00000800)
+#define RTC_FLAG_WTF    ((uint32_t)0x00000400)
+#define RTC_FLAG_ALBF   ((uint32_t)0x00000200)
+#define RTC_FLAG_ALAF   ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF  ((uint32_t)0x00000040)
+#define RTC_FLAG_RSYF   ((uint32_t)0x00000020)
+#define RTC_FLAG_INITSF ((uint32_t)0x00000010)
+#define RTC_FLAG_SHOPF  ((uint32_t)0x00000008)
+#define RTC_FLAG_WTWF   ((uint32_t)0x00000004)
+#define RTC_FLAG_ALBWF  ((uint32_t)0x00000002)
+#define RTC_FLAG_ALAWF  ((uint32_t)0x00000001)
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECPF) || ((FLAG) == RTC_FLAG_TAMP3F) || \
+                               ((FLAG) == RTC_FLAG_TAMP2F) || ((FLAG) == RTC_FLAG_TAMP1F) || \
+                               ((FLAG) == RTC_FLAG_TISOVF) || ((FLAG) == RTC_FLAG_TISF) || \
+                               ((FLAG) == RTC_FLAG_WTF) || ((FLAG) == RTC_FLAG_ALBF) || \
+                               ((FLAG) == RTC_FLAG_ALAF) || ((FLAG) == RTC_FLAG_INITF) || \
+                               ((FLAG) == RTC_FLAG_RSYF) || ((FLAG) == RTC_FLAG_INITSF) || \
+                               ((FLAG) == RTC_FLAG_SHOPF) || ((FLAG) == RTC_FLAG_WTWF) || \
+                               ((FLAG) == RTC_FLAG_ALBWF)|| ((FLAG) == RTC_FLAG_ALAWF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Interrupts_Definitions
+ * @{
+ */
+#define RTC_INT_TAMP3     ((uint32_t)0x00080000)
+#define RTC_INT_TAMP2     ((uint32_t)0x00040000)
+#define RTC_INT_TAMP1     ((uint32_t)0x00020000)
+#define RTC_INT_TS        ((uint32_t)0x00008000)
+#define RTC_INT_WUT  ((uint32_t)0x00004000)
+#define RTC_INT_ALRB ((uint32_t)0x00002000)
+#define RTC_INT_ALRA ((uint32_t)0x00001000)
+
+#define IS_RTC_CONFIG_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_INT(IT)                                                                                             \
+    (((IT) == RTC_INT_TAMP3) ||((IT) == RTC_INT_TAMP2) ||((IT) == RTC_INT_TAMP1) ||((IT) == RTC_INT_TS) || ((IT) == RTC_INT_WUT) || ((IT) == RTC_INT_ALRB) || ((IT) == RTC_INT_ALRA))
+#define IS_RTC_CLEAR_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFF10FFF) == (uint32_t)RESET))
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Legacy
+ * @{
+ */
+#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
+#define RTC_DigitalCalibCmd    RTC_CoarseCalibCmd
+/** @defgroup RTC_Tamper_Trigger_Definitions
+  * @{
+  */
+#define RTC_TamperTrigger_RisingEdge            ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge           ((uint32_t)0x00000002)
+#define RTC_TamperTrigger_LowLevel              ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel             ((uint32_t)0x00000002)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_HighLevel))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Filter_Definitions
+  * @{
+  */
+#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8
+                                                          consecutive samples at the active leve. */
+
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+                                      ((FILTER) == RTC_TamperFilter_2Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_4Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
+  * @{
+  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768  ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384  ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
+                                                                            with a frequency =  RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192   ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 8192  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096   ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 4096  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048   ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 2048  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024   ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 1024  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512    ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 512   */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256    ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 256   */
+#define RTC_TAMPCR_TAMPFREQ                      ((uint32_t)0x00000700) /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */
+
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
+/**
+  * @}
+  */
+
+  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
+  * @{
+  */
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before
+                                                                         sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before
+                                                                         sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before
+                                                                         sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before
+                                                                         sampling during 8 RTCCLK cycles */
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pins_Definitions
+  * @{
+  */
+#define RTC_TAMPER_1            RTC_TMPCFG_TP1EN /*!< Tamper detection enable for
+                                                      input tamper 1 */
+#define RTC_TAMPER_2            RTC_TMPCFG_TP2EN /*!< Tamper detection enable for
+                                                      input tamper 2 */
+#define RTC_TAMPER_3            RTC_TMPCFG_TP3EN /*!< Tamper detection enable for
+                                                      input tamper 3 */
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+
+#define RTC_TAMPER1_INT        RTC_TMPCFG_TP1INTEN  /*!< Tamper detection interruput enable */
+#define RTC_TAMPER2_INT        RTC_TMPCFG_TP2INTEN  /*!< Tamper detection interruput enable */
+#define RTC_TAMPER3_INT        RTC_TMPCFG_TP3INTEN  /*!< Tamper detection interruput enable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*  Function used to set the RTC configuration to the default reset state *****/
+ErrorStatus RTC_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct);
+void RTC_StructInit(RTC_InitType* RTC_InitStruct);
+void RTC_EnableWriteProtection(FunctionalState Cmd);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_EnableRefClock(FunctionalState Cmd);
+void RTC_EnableBypassShadow(FunctionalState Cmd);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateType* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct);
+
+/* Alarms (Alarm A and Alarm B) configuration functions  **********************/
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct);
+ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd);
+void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/
+void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock);
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
+uint32_t RTC_GetWakeUpCounter(void);
+ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd);
+
+/* Daylight Saving configuration functions ************************************/
+void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Coarse and Smooth Calibration configuration functions **********************/
+void RTC_EnableCalibOutput(FunctionalState Cmd);
+void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod,
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Output Type Config configuration functions *********************************/
+void RTC_ConfigOutputType(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/
+void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClrFlag(uint32_t RTC_FLAG);
+INTStatus RTC_GetITStatus(uint32_t RTC_INT);
+void RTC_ClrIntPendingBit(uint32_t RTC_INT);
+
+/* WakeUp TSC function **********************************/
+void RTC_EnableWakeUpTsc(uint32_t count);
+
+/* Tampers configuration functions ********************************************/
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState);
+void RTC_TamperTAMPTSCmd(FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_RTC_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_spi.h

@@ -0,0 +1,470 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_spi.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43x_SPI_H__
+#define __N32G43x_SPI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/** @addtogroup SPI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief  SPI Init structure definition
+ */
+
+typedef struct
+{
+    uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                 This parameter can be a value of @ref SPI_data_direction */
+
+    uint16_t SpiMode; /*!< Specifies the SPI operating mode.
+                            This parameter can be a value of @ref SPI_mode */
+
+    uint16_t DataLen; /*!< Specifies the SPI data size.
+                                This parameter can be a value of @ref SPI_data_size */
+
+    uint16_t CLKPOL; /*!< Specifies the serial clock steady state.
+                            This parameter can be a value of @ref SPI_Clock_Polarity */
+
+    uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture.
+                            This parameter can be a value of @ref SPI_Clock_Phase */
+
+    uint16_t NSS; /*!< Specifies whether the NSS signal is managed by
+                           hardware (NSS pin) or by software using the SSI bit.
+                           This parameter can be a value of @ref SPI_Slave_Select_management */
+
+    uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be
+                                         used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+                                         @note The communication clock is derived from the master
+                                               clock. The slave clock does not need to be set. */
+
+    uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+    uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */
+} SPI_InitType;
+
+/**
+ * @brief  I2S Init structure definition
+ */
+
+typedef struct
+{
+    uint16_t I2sMode; /*!< Specifies the I2S operating mode.
+                            This parameter can be a value of @ref I2sMode */
+
+    uint16_t Standard; /*!< Specifies the standard used for the I2S communication.
+                                This parameter can be a value of @ref Standard */
+
+    uint16_t DataFormat; /*!< Specifies the data format for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Data_Format */
+
+    uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                  This parameter can be a value of @ref I2S_MCLK_Output */
+
+    uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication.
+                                 This parameter can be a value of @ref I2S_Audio_Frequency */
+
+    uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock.
+                            This parameter can be a value of @ref I2S_Clock_Polarity */
+} I2S_InitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Constants
+ * @{
+ */
+
+#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2))
+
+
+/** @addtogroup SPI_data_direction
+ * @{
+ */
+
+#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000)
+#define SPI_DIR_DOUBLELINE_RONLY      ((uint16_t)0x0400)
+#define SPI_DIR_SINGLELINE_RX         ((uint16_t)0x8000)
+#define SPI_DIR_SINGLELINE_TX         ((uint16_t)0xC000)
+#define IS_SPI_DIR_MODE(MODE)                                                                                          \
+    (((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY)                                 \
+     || ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_mode
+ * @{
+ */
+
+#define SPI_MODE_MASTER   ((uint16_t)0x0104)
+#define SPI_MODE_SLAVE    ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_data_size
+ * @{
+ */
+
+#define SPI_DATA_SIZE_16BITS      ((uint16_t)0x0800)
+#define SPI_DATA_SIZE_8BITS       ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Clock_Polarity
+ * @{
+ */
+
+#define SPI_CLKPOL_LOW      ((uint16_t)0x0000)
+#define SPI_CLKPOL_HIGH     ((uint16_t)0x0002)
+#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Clock_Phase
+ * @{
+ */
+
+#define SPI_CLKPHA_FIRST_EDGE  ((uint16_t)0x0000)
+#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001)
+#define IS_SPI_CLKPHA(CPHA)    (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Slave_Select_management
+ * @{
+ */
+
+#define SPI_NSS_SOFT    ((uint16_t)0x0200)
+#define SPI_NSS_HARD    ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_BaudRate_Prescaler
+ * @{
+ */
+
+#define SPI_BR_PRESCALER_2   ((uint16_t)0x0000)
+#define SPI_BR_PRESCALER_4   ((uint16_t)0x0008)
+#define SPI_BR_PRESCALER_8   ((uint16_t)0x0010)
+#define SPI_BR_PRESCALER_16  ((uint16_t)0x0018)
+#define SPI_BR_PRESCALER_32  ((uint16_t)0x0020)
+#define SPI_BR_PRESCALER_64  ((uint16_t)0x0028)
+#define SPI_BR_PRESCALER_128 ((uint16_t)0x0030)
+#define SPI_BR_PRESCALER_256 ((uint16_t)0x0038)
+#define IS_SPI_BR_PRESCALER(PRESCALER)                                                                                 \
+    (((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \
+     || ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32)                                   \
+     || ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128)                                  \
+     || ((PRESCALER) == SPI_BR_PRESCALER_256))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_MSB_LSB_transmission
+ * @{
+ */
+
+#define SPI_FB_MSB            ((uint16_t)0x0000)
+#define SPI_FB_LSB            ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB))
+/**
+ * @}
+ */
+
+/** @addtogroup I2sMode
+ * @{
+ */
+
+#define I2S_MODE_SlAVE_TX  ((uint16_t)0x0000)
+#define I2S_MODE_SlAVE_RX  ((uint16_t)0x0100)
+#define I2S_MODE_MASTER_TX ((uint16_t)0x0200)
+#define I2S_MODE_MASTER_RX ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE)                                                                                              \
+    (((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX)                  \
+     || ((MODE) == I2S_MODE_MASTER_RX))
+/**
+ * @}
+ */
+
+/** @addtogroup Standard
+ * @{
+ */
+
+#define I2S_STD_PHILLIPS       ((uint16_t)0x0000)
+#define I2S_STD_MSB_ALIGN      ((uint16_t)0x0010)
+#define I2S_STD_LSB_ALIGN      ((uint16_t)0x0020)
+#define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030)
+#define I2S_STD_PCM_LONGFRAME  ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD)                                                                                      \
+    (((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN)        \
+     || ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Data_Format
+ * @{
+ */
+
+#define I2S_DATA_FMT_16BITS          ((uint16_t)0x0000)
+#define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001)
+#define I2S_DATA_FMT_24BITS          ((uint16_t)0x0003)
+#define I2S_DATA_FMT_32BITS          ((uint16_t)0x0005)
+#define IS_I2S_DATA_FMT(FORMAT)                                                                                        \
+    (((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED)                                   \
+     || ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_MCLK_Output
+ * @{
+ */
+
+#define I2S_MCLK_ENABLE            ((uint16_t)0x0200)
+#define I2S_MCLK_DISABLE           ((uint16_t)0x0000)
+#define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Audio_Frequency
+ * @{
+ */
+
+#define I2S_AUDIO_FREQ_192K    ((uint32_t)192000)
+#define I2S_AUDIO_FREQ_96K     ((uint32_t)96000)
+#define I2S_AUDIO_FREQ_48K     ((uint32_t)48000)
+#define I2S_AUDIO_FREQ_44K     ((uint32_t)44100)
+#define I2S_AUDIO_FREQ_32K     ((uint32_t)32000)
+#define I2S_AUDIO_FREQ_22K     ((uint32_t)22050)
+#define I2S_AUDIO_FREQ_16K     ((uint32_t)16000)
+#define I2S_AUDIO_FREQ_11K     ((uint32_t)11025)
+#define I2S_AUDIO_FREQ_8K      ((uint32_t)8000)
+#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ)                                                                                        \
+    ((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT))
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Clock_Polarity
+ * @{
+ */
+
+#define I2S_CLKPOL_LOW      ((uint16_t)0x0000)
+#define I2S_CLKPOL_HIGH     ((uint16_t)0x0008)
+#define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_DMA_transfer_requests
+ * @{
+ */
+
+#define SPI_I2S_DMA_TX         ((uint16_t)0x0002)
+#define SPI_I2S_DMA_RX         ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_NSS_internal_software_management
+ * @{
+ */
+
+#define SPI_NSS_HIGH               ((uint16_t)0x0100)
+#define SPI_NSS_LOW                ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_CRC_Transmit_Receive
+ * @{
+ */
+
+#define SPI_CRC_TX      ((uint8_t)0x00)
+#define SPI_CRC_RX      ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_direction_transmit_receive
+ * @{
+ */
+
+#define SPI_BIDIRECTION_RX            ((uint16_t)0xBFFF)
+#define SPI_BIDIRECTION_TX            ((uint16_t)0x4000)
+#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_interrupts_definition
+ * @{
+ */
+
+#define SPI_I2S_INT_TE            ((uint8_t)0x71)
+#define SPI_I2S_INT_RNE           ((uint8_t)0x60)
+#define SPI_I2S_INT_ERR           ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR))
+#define SPI_I2S_INT_OVER          ((uint8_t)0x56)
+#define SPI_INT_MODERR            ((uint8_t)0x55)
+#define SPI_INT_CRCERR            ((uint8_t)0x54)
+#define I2S_INT_UNDER             ((uint8_t)0x53)
+#define IS_SPI_I2S_CLR_INT(IT)    (((IT) == SPI_INT_CRCERR))
+#define IS_SPI_I2S_GET_INT(IT)                                                                                         \
+    (((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR)      \
+     || ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_I2S_flags_definition
+ * @{
+ */
+
+#define SPI_I2S_RNE_FLAG          ((uint16_t)0x0001)
+#define SPI_I2S_TE_FLAG           ((uint16_t)0x0002)
+#define I2S_CHSIDE_FLAG           ((uint16_t)0x0004)
+#define I2S_UNDER_FLAG            ((uint16_t)0x0008)
+#define SPI_CRCERR_FLAG           ((uint16_t)0x0010)
+#define SPI_MODERR_FLAG           ((uint16_t)0x0020)
+#define SPI_I2S_OVER_FLAG         ((uint16_t)0x0040)
+#define SPI_I2S_BUSY_FLAG         ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG))
+#define IS_SPI_I2S_GET_FLAG(FLAG)                                                                                      \
+    (((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG)                     \
+     || ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG)                       \
+     || ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG))
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_CRC_polynomial
+ * @{
+ */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+void SPI_I2S_DeInit(SPI_Module* SPIx);
+void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct);
+void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct);
+void SPI_InitStruct(SPI_InitType* SPI_InitStruct);
+void I2S_InitStruct(I2S_InitType* I2S_InitStruct);
+void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd);
+void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd);
+void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd);
+void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd);
+void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx);
+void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd);
+void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen);
+void SPI_TransmitCrcNext(SPI_Module* SPIx);
+void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd);
+uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPoly(SPI_Module* SPIx);
+void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection);
+FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
+INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43x_SPI_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tim.h

@@ -0,0 +1,1101 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_tim.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_TIM_H__
+#define __N32G43X_TIM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+#include "stdbool.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief  TIM Time Base Init structure definition
+ * @note   This structure is used with all TIMx except for TIM6 and TIM7.
+ */
+
+typedef struct
+{
+    uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+                                 This parameter can be a number between 0x0000 and 0xFFFF */
+
+    uint16_t CntMode; /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+    uint16_t Period; /*!< Specifies the period value to be loaded into the active
+                              Auto-Reload Register at the next update event.
+                              This parameter must be a number between 0x0000 and 0xFFFF.  */
+
+    uint16_t ClkDiv; /*!< Specifies the clock division.
+                                    This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+    uint8_t RepetCnt; /*!< Specifies the repetition counter value. Each time the REPCNT downcounter
+                                        reaches zero, an update event is generated and counting restarts
+                                        from the REPCNT value (N).
+                                        This means in PWM mode that (N+1) corresponds to:
+                                           - the number of PWM periods in edge-aligned mode
+                                           - the number of half PWM period in center-aligned mode
+                                        This parameter must be a number between 0x00 and 0xFF.
+                                        @note This parameter is valid only for TIM1 and TIM8. */
+
+    bool CapCh1FromCompEn;    /*!< channel 1 select capture in from comp if 1, from IOM if 0
+                                Tim1,Tim8,Tim2,Tim3,Tim4,Tim5 valid*/
+    bool CapCh2FromCompEn;    /*!< channel 2 select capture in from comp if 1, from IOM if 0
+                                Tim2,Tim3,Tim4,Tim5 valid*/
+    bool CapCh3FromCompEn;    /*!< channel 3 select capture in from comp if 1, from IOM if 0
+                                Tim2,Tim3,Tim4,Tim5 valid*/
+    bool CapCh4FromCompEn;    /*!< channel 4 select capture in from comp if 1, from IOM if 0
+                                Tim2,Tim3,Tim4 valid*/
+    bool CapEtrClrFromCompEn; /*!< etr clearref select from comp if 1, from ETR IOM if 0
+                                Tim2,Tim3,Tim4 valid*/
+    bool CapEtrSelFromTscEn;  /*!< etr select from TSC if 1, from IOM if 0
+                                 Tim2,Tim4 valid*/
+} TIM_TimeBaseInitType;
+
+/**
+ * @brief  TIM Output Compare Init structure definition
+ */
+
+typedef struct
+{
+    uint16_t OcMode; /*!< Specifies the TIM mode.
+                              This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+    uint16_t OutputState; /*!< Specifies the TIM Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_state */
+
+    uint16_t OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+                                    This parameter can be a value of @ref TIM_Output_Compare_N_state
+                                    @note This parameter is valid only for TIM1 and TIM8. */
+
+    uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                             This parameter can be a number between 0x0000 and 0xFFFF */
+
+    uint16_t OcPolarity; /*!< Specifies the output polarity.
+                                  This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+    uint16_t OcNPolarity; /*!< Specifies the complementary output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+
+    uint16_t OcIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+
+    uint16_t OcNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                    This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                                    @note This parameter is valid only for TIM1 and TIM8. */
+} OCInitType;
+
+/**
+ * @brief  TIM Input Capture Init structure definition
+ */
+
+typedef struct
+{
+    uint16_t Channel; /*!< Specifies the TIM channel.
+                               This parameter can be a value of @ref Channel */
+
+    uint16_t IcPolarity; /*!< Specifies the active edge of the input signal.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+    uint16_t IcSelection; /*!< Specifies the input.
+                                   This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+    uint16_t IcPrescaler; /*!< Specifies the Input Capture Prescaler.
+                                   This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+    uint16_t IcFilter; /*!< Specifies the input capture filter.
+                                This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitType;
+
+/**
+ * @brief  BKDT structure definition
+ * @note   This structure is used only with TIM1 and TIM8.
+ */
+
+typedef struct
+{
+    uint16_t OssrState; /*!< Specifies the Off-State selection used in Run mode.
+                                 This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+    uint16_t OssiState; /*!< Specifies the Off-State used in Idle state.
+                                 This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+    uint16_t LockLevel; /*!< Specifies the LOCK level parameters.
+                                 This parameter can be a value of @ref Lock_level */
+
+    uint16_t DeadTime; /*!< Specifies the delay time between the switching-off and the
+                                switching-on of the outputs.
+                                This parameter can be a number between 0x00 and 0xFF  */
+
+    uint16_t Break; /*!< Specifies whether the TIM Break input is enabled or not.
+                             This parameter can be a value of @ref Break_Input_enable_disable */
+
+    uint16_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+                                     This parameter can be a value of @ref Break_Polarity */
+
+    uint16_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+                                       This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+    bool IomBreakEn;          /*!< EXTENDMODE valid, open iom as break in*/
+    bool LockUpBreakEn;       /*!< EXTENDMODE valid, open lockup(haldfault) as break in*/
+    bool PvdBreakEn;          /*!< EXTENDMODE valid, open pvd(sys voltage too high or too low) as break in*/
+} TIM_BDTRInitType;
+
+/** @addtogroup TIM_Exported_constants
+ * @{
+ */
+
+#define IsTimAllModule(PERIPH)                                                                                         \
+    (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9)       \
+     || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/* LIST1: TIM 1 and 8 */
+#define IsTimList1Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8))
+
+/* LIST2: TIM 1, 8 */
+#define IsTimList2Module(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8))
+
+/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
+#define IsTimList3Module(PERIPH)                                                                                       \
+    (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5)  || ((PERIPH) == TIM9)       \
+     || ((PERIPH) == TIM8))
+
+/* LIST4: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList4Module(PERIPH)                                                                                       \
+    (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5)  || ((PERIPH) == TIM9)       \
+     || ((PERIPH) == TIM8))
+
+/* LIST5: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList5Module(PERIPH)                                                                                       \
+    (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5)  || ((PERIPH) == TIM9)       \
+     || ((PERIPH) == TIM8))
+
+/* LIST6: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList6Module(PERIPH)                                                                                       \
+    (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5)  || ((PERIPH) == TIM9)       \
+     || ((PERIPH) == TIM8))
+
+/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8 */
+#define IsTimList7Module(PERIPH)                                                                                       \
+    (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM9)        \
+     || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/* LIST8: TIM 1, 2, 3, 4, 5, 8 */
+#define IsTimList8Module(PERIPH)                                                                                       \
+    (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5)  || ((PERIPH) == TIM9)       \
+     || ((PERIPH) == TIM8))
+
+/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8 */
+#define IsTimList9Module(PERIPH)                                                                                       \
+    (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5)  || ((PERIPH) == TIM9)       \
+     || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMODE_TIMING   ((uint16_t)0x0000)
+#define TIM_OCMODE_ACTIVE   ((uint16_t)0x0010)
+#define TIM_OCMODE_INACTIVE ((uint16_t)0x0020)
+#define TIM_OCMODE_TOGGLE   ((uint16_t)0x0030)
+#define TIM_OCMODE_PWM1     ((uint16_t)0x0060)
+#define TIM_OCMODE_PWM2     ((uint16_t)0x0070)
+#define IsTimOcMode(MODE)                                                                                              \
+    (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE)                 \
+     || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2))
+#define IsTimOc(MODE)                                                                                                  \
+    (((MODE) == TIM_OCMODE_TIMING) || ((MODE) == TIM_OCMODE_ACTIVE) || ((MODE) == TIM_OCMODE_INACTIVE)                 \
+     || ((MODE) == TIM_OCMODE_TOGGLE) || ((MODE) == TIM_OCMODE_PWM1) || ((MODE) == TIM_OCMODE_PWM2)                    \
+     || ((MODE) == TIM_FORCED_ACTION_ACTIVE) || ((MODE) == TIM_FORCED_ACTION_INACTIVE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMODE_SINGLE ((uint16_t)0x0008)
+#define TIM_OPMODE_REPET  ((uint16_t)0x0000)
+#define IsTimOpMOde(MODE) (((MODE) == TIM_OPMODE_SINGLE) || ((MODE) == TIM_OPMODE_REPET))
+/**
+ * @}
+ */
+
+/** @addtogroup Channel
+ * @{
+ */
+
+#define TIM_CH_1 ((uint16_t)0x0000)
+#define TIM_CH_2 ((uint16_t)0x0004)
+#define TIM_CH_3 ((uint16_t)0x0008)
+#define TIM_CH_4 ((uint16_t)0x000C)
+#define IsTimCh(CHANNEL)                                                                                               \
+    (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3) || ((CHANNEL) == TIM_CH_4))
+#define IsTimPwmInCh(CHANNEL)         (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2))
+#define IsTimComplementaryCh(CHANNEL) (((CHANNEL) == TIM_CH_1) || ((CHANNEL) == TIM_CH_2) || ((CHANNEL) == TIM_CH_3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CLK_DIV1     ((uint16_t)0x0000)
+#define TIM_CLK_DIV2     ((uint16_t)0x0100)
+#define TIM_CLK_DIV4     ((uint16_t)0x0200)
+#define IsTimClkDiv(DIV) (((DIV) == TIM_CLK_DIV1) || ((DIV) == TIM_CLK_DIV2) || ((DIV) == TIM_CLK_DIV4))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_CNT_MODE_UP            ((uint16_t)0x0000)
+#define TIM_CNT_MODE_DOWN          ((uint16_t)0x0010)
+#define TIM_CNT_MODE_CENTER_ALIGN1 ((uint16_t)0x0020)
+#define TIM_CNT_MODE_CENTER_ALIGN2 ((uint16_t)0x0040)
+#define TIM_CNT_MODE_CENTER_ALIGN3 ((uint16_t)0x0060)
+#define IsTimCntMode(MODE)                                                                                             \
+    (((MODE) == TIM_CNT_MODE_UP) || ((MODE) == TIM_CNT_MODE_DOWN) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN1)            \
+     || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN2) || ((MODE) == TIM_CNT_MODE_CENTER_ALIGN3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OC_POLARITY_HIGH      ((uint16_t)0x0000)
+#define TIM_OC_POLARITY_LOW       ((uint16_t)0x0002)
+#define IsTimOcPolarity(POLARITY) (((POLARITY) == TIM_OC_POLARITY_HIGH) || ((POLARITY) == TIM_OC_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCN_POLARITY_HIGH      ((uint16_t)0x0000)
+#define TIM_OCN_POLARITY_LOW       ((uint16_t)0x0008)
+#define IsTimOcnPolarity(POLARITY) (((POLARITY) == TIM_OCN_POLARITY_HIGH) || ((POLARITY) == TIM_OCN_POLARITY_LOW))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_state
+ * @{
+ */
+
+#define TIM_OUTPUT_STATE_DISABLE ((uint16_t)0x0000)
+#define TIM_OUTPUT_STATE_ENABLE  ((uint16_t)0x0001)
+#define IsTimOutputState(STATE)  (((STATE) == TIM_OUTPUT_STATE_DISABLE) || ((STATE) == TIM_OUTPUT_STATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_state
+ * @{
+ */
+
+#define TIM_OUTPUT_NSTATE_DISABLE ((uint16_t)0x0000)
+#define TIM_OUTPUT_NSTATE_ENABLE  ((uint16_t)0x0004)
+#define IsTimOutputNState(STATE)  (((STATE) == TIM_OUTPUT_NSTATE_DISABLE) || ((STATE) == TIM_OUTPUT_NSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Capture_Compare_state
+ * @{
+ */
+
+#define TIM_CAP_CMP_ENABLE    ((uint16_t)0x0001)
+#define TIM_CAP_CMP_DISABLE   ((uint16_t)0x0000)
+#define IsTimCapCmpState(CCX) (((CCX) == TIM_CAP_CMP_ENABLE) || ((CCX) == TIM_CAP_CMP_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Capture_Compare_N_state
+ * @{
+ */
+
+#define TIM_CAP_CMP_N_ENABLE    ((uint16_t)0x0004)
+#define TIM_CAP_CMP_N_DISABLE   ((uint16_t)0x0000)
+#define IsTimCapCmpNState(CCXN) (((CCXN) == TIM_CAP_CMP_N_ENABLE) || ((CCXN) == TIM_CAP_CMP_N_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Break_Input_enable_disable
+ * @{
+ */
+
+#define TIM_BREAK_IN_ENABLE      ((uint16_t)0x1000)
+#define TIM_BREAK_IN_DISABLE     ((uint16_t)0x0000)
+#define IsTimBreakInState(STATE) (((STATE) == TIM_BREAK_IN_ENABLE) || ((STATE) == TIM_BREAK_IN_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Break_Polarity
+ * @{
+ */
+
+#define TIM_BREAK_POLARITY_LOW       ((uint16_t)0x0000)
+#define TIM_BREAK_POLARITY_HIGH      ((uint16_t)0x2000)
+#define IsTimBreakPalarity(POLARITY) (((POLARITY) == TIM_BREAK_POLARITY_LOW) || ((POLARITY) == TIM_BREAK_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+
+#define TIM_AUTO_OUTPUT_ENABLE      ((uint16_t)0x4000)
+#define TIM_AUTO_OUTPUT_DISABLE     ((uint16_t)0x0000)
+#define IsTimAutoOutputState(STATE) (((STATE) == TIM_AUTO_OUTPUT_ENABLE) || ((STATE) == TIM_AUTO_OUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup Lock_level
+ * @{
+ */
+
+#define TIM_LOCK_LEVEL_OFF ((uint16_t)0x0000)
+#define TIM_LOCK_LEVEL_1   ((uint16_t)0x0100)
+#define TIM_LOCK_LEVEL_2   ((uint16_t)0x0200)
+#define TIM_LOCK_LEVEL_3   ((uint16_t)0x0300)
+#define IsTimLockLevel(LEVEL)                                                                                          \
+    (((LEVEL) == TIM_LOCK_LEVEL_OFF) || ((LEVEL) == TIM_LOCK_LEVEL_1) || ((LEVEL) == TIM_LOCK_LEVEL_2)                 \
+     || ((LEVEL) == TIM_LOCK_LEVEL_3))
+/**
+ * @}
+ */
+
+/** @addtogroup OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+
+#define TIM_OSSI_STATE_ENABLE  ((uint16_t)0x0400)
+#define TIM_OSSI_STATE_DISABLE ((uint16_t)0x0000)
+#define IsTimOssiState(STATE)  (((STATE) == TIM_OSSI_STATE_ENABLE) || ((STATE) == TIM_OSSI_STATE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+
+#define TIM_OSSR_STATE_ENABLE  ((uint16_t)0x0800)
+#define TIM_OSSR_STATE_DISABLE ((uint16_t)0x0000)
+#define IsTimOssrState(STATE)  (((STATE) == TIM_OSSR_STATE_ENABLE) || ((STATE) == TIM_OSSR_STATE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+
+#define TIM_OC_IDLE_STATE_SET   ((uint16_t)0x0100)
+#define TIM_OC_IDLE_STATE_RESET ((uint16_t)0x0000)
+#define IsTimOcIdleState(STATE) (((STATE) == TIM_OC_IDLE_STATE_SET) || ((STATE) == TIM_OC_IDLE_STATE_RESET))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+
+#define TIM_OCN_IDLE_STATE_SET   ((uint16_t)0x0200)
+#define TIM_OCN_IDLE_STATE_RESET ((uint16_t)0x0000)
+#define IsTimOcnIdleState(STATE) (((STATE) == TIM_OCN_IDLE_STATE_SET) || ((STATE) == TIM_OCN_IDLE_STATE_RESET))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_IC_POLARITY_RISING   ((uint16_t)0x0000)
+#define TIM_IC_POLARITY_FALLING  ((uint16_t)0x0002)
+#define TIM_IC_POLARITY_BOTHEDGE ((uint16_t)0x000A)
+#define IsTimIcPalaritySingleEdge(POLARITY)                                                                            \
+    (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING))
+#define IsTimIcPolarityAnyEdge(POLARITY)                                                                               \
+    (((POLARITY) == TIM_IC_POLARITY_RISING) || ((POLARITY) == TIM_IC_POLARITY_FALLING)                                 \
+     || ((POLARITY) == TIM_IC_POLARITY_BOTHEDGE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_IC_SELECTION_DIRECTTI                                                                                      \
+    ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be                                                   \
+                           connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_IC_SELECTION_INDIRECTTI                                                                                    \
+    ((uint16_t)0x0002)                          /*!< TIM Input 1, 2, 3 or 4 is selected to be                          \
+                                                    connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_IC_SELECTION_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IsTimIcSelection(SELECTION)                                                                                    \
+    (((SELECTION) == TIM_IC_SELECTION_DIRECTTI) || ((SELECTION) == TIM_IC_SELECTION_INDIRECTTI)                        \
+     || ((SELECTION) == TIM_IC_SELECTION_TRC))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_IC_PSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input.  \
+                                            */
+#define TIM_IC_PSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_IC_PSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_IC_PSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IsTimIcPrescaler(PRESCALER)                                                                                    \
+    (((PRESCALER) == TIM_IC_PSC_DIV1) || ((PRESCALER) == TIM_IC_PSC_DIV2) || ((PRESCALER) == TIM_IC_PSC_DIV4)          \
+     || ((PRESCALER) == TIM_IC_PSC_DIV8))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_interrupt_sources
+ * @{
+ */
+
+#define TIM_INT_UPDATE ((uint16_t)0x0001)
+#define TIM_INT_CC1    ((uint16_t)0x0002)
+#define TIM_INT_CC2    ((uint16_t)0x0004)
+#define TIM_INT_CC3    ((uint16_t)0x0008)
+#define TIM_INT_CC4    ((uint16_t)0x0010)
+#define TIM_INT_COM    ((uint16_t)0x0020)
+#define TIM_INT_TRIG   ((uint16_t)0x0040)
+#define TIM_INT_BREAK  ((uint16_t)0x0080)
+#define IsTimInt(IT)   ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IsTimGetInt(IT)                                                                                                \
+    (((IT) == TIM_INT_UPDATE) || ((IT) == TIM_INT_CC1) || ((IT) == TIM_INT_CC2) || ((IT) == TIM_INT_CC3)               \
+     || ((IT) == TIM_INT_CC4) || ((IT) == TIM_INT_COM) || ((IT) == TIM_INT_TRIG) || ((IT) == TIM_INT_BREAK))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABASE_CTRL1      ((uint16_t)0x0000)
+#define TIM_DMABASE_CTRL2      ((uint16_t)0x0001)
+#define TIM_DMABASE_SMCTRL     ((uint16_t)0x0002)
+#define TIM_DMABASE_DMAINTEN   ((uint16_t)0x0003)
+#define TIM_DMABASE_STS        ((uint16_t)0x0004)
+#define TIM_DMABASE_EVTGEN     ((uint16_t)0x0005)
+#define TIM_DMABASE_CAPCMPMOD1 ((uint16_t)0x0006)
+#define TIM_DMABASE_CAPCMPMOD2 ((uint16_t)0x0007)
+#define TIM_DMABASE_CAPCMPEN   ((uint16_t)0x0008)
+#define TIM_DMABASE_CNT        ((uint16_t)0x0009)
+#define TIM_DMABASE_PSC        ((uint16_t)0x000A)
+#define TIM_DMABASE_AR         ((uint16_t)0x000B)
+#define TIM_DMABASE_REPCNT     ((uint16_t)0x000C)
+#define TIM_DMABASE_CAPCMPDAT1 ((uint16_t)0x000D)
+#define TIM_DMABASE_CAPCMPDAT2 ((uint16_t)0x000E)
+#define TIM_DMABASE_CAPCMPDAT3 ((uint16_t)0x000F)
+#define TIM_DMABASE_CAPCMPDAT4 ((uint16_t)0x0010)
+#define TIM_DMABASE_BKDT       ((uint16_t)0x0011)
+#define TIM_DMABASE_DMACTRL    ((uint16_t)0x0012)
+
+
+#define IsTimDmaBase(BASE)                                                                                             \
+    (((BASE) == TIM_DMABASE_CTRL1) || ((BASE) == TIM_DMABASE_CTRL2) || ((BASE) == TIM_DMABASE_SMCTRL)                  \
+     || ((BASE) == TIM_DMABASE_DMAINTEN) || ((BASE) == TIM_DMABASE_STS) || ((BASE) == TIM_DMABASE_EVTGEN)              \
+     || ((BASE) == TIM_DMABASE_CAPCMPMOD1) || ((BASE) == TIM_DMABASE_CAPCMPMOD2) || ((BASE) == TIM_DMABASE_CAPCMPMOD3) \
+     || ((BASE) == TIM_DMABASE_CAPCMPEN) || ((BASE) == TIM_DMABASE_CNT) || ((BASE) == TIM_DMABASE_PSC)                 \
+     || ((BASE) == TIM_DMABASE_AR) || ((BASE) == TIM_DMABASE_REPCNT) || ((BASE) == TIM_DMABASE_CAPCMPDAT1)             \
+     || ((BASE) == TIM_DMABASE_CAPCMPDAT2) || ((BASE) == TIM_DMABASE_CAPCMPDAT3) || ((BASE) == TIM_DMABASE_CAPCMPDAT4) \
+     || ((BASE) == TIM_DMABASE_BKDT)|| ((BASE) == TIM_DMABASE_DMACTRL))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABURST_LENGTH_1TRANSFER   ((uint16_t)0x0000)
+#define TIM_DMABURST_LENGTH_2TRANSFERS  ((uint16_t)0x0100)
+#define TIM_DMABURST_LENGTH_3TRANSFERS  ((uint16_t)0x0200)
+#define TIM_DMABURST_LENGTH_4TRANSFERS  ((uint16_t)0x0300)
+#define TIM_DMABURST_LENGTH_5TRANSFERS  ((uint16_t)0x0400)
+#define TIM_DMABURST_LENGTH_6TRANSFERS  ((uint16_t)0x0500)
+#define TIM_DMABURST_LENGTH_7TRANSFERS  ((uint16_t)0x0600)
+#define TIM_DMABURST_LENGTH_8TRANSFERS  ((uint16_t)0x0700)
+#define TIM_DMABURST_LENGTH_9TRANSFERS  ((uint16_t)0x0800)
+#define TIM_DMABURST_LENGTH_10TRANSFERS ((uint16_t)0x0900)
+#define TIM_DMABURST_LENGTH_11TRANSFERS ((uint16_t)0x0A00)
+#define TIM_DMABURST_LENGTH_12TRANSFERS ((uint16_t)0x0B00)
+#define TIM_DMABURST_LENGTH_13TRANSFERS ((uint16_t)0x0C00)
+#define TIM_DMABURST_LENGTH_14TRANSFERS ((uint16_t)0x0D00)
+#define TIM_DMABURST_LENGTH_15TRANSFERS ((uint16_t)0x0E00)
+#define TIM_DMABURST_LENGTH_16TRANSFERS ((uint16_t)0x0F00)
+#define TIM_DMABURST_LENGTH_17TRANSFERS ((uint16_t)0x1000)
+#define TIM_DMABURST_LENGTH_18TRANSFERS ((uint16_t)0x1100)
+#define TIM_DMABURST_LENGTH_19TRANSFERS ((uint16_t)0x1200)
+#define TIM_DMABURST_LENGTH_20TRANSFERS ((uint16_t)0x1300)
+#define TIM_DMABURST_LENGTH_21TRANSFERS ((uint16_t)0x1400)
+#define IsTimDmaLength(LENGTH)                                                                                         \
+    (((LENGTH) == TIM_DMABURST_LENGTH_1TRANSFER) || ((LENGTH) == TIM_DMABURST_LENGTH_2TRANSFERS)                       \
+     || ((LENGTH) == TIM_DMABURST_LENGTH_3TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_4TRANSFERS)                   \
+     || ((LENGTH) == TIM_DMABURST_LENGTH_5TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_6TRANSFERS)                   \
+     || ((LENGTH) == TIM_DMABURST_LENGTH_7TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_8TRANSFERS)                   \
+     || ((LENGTH) == TIM_DMABURST_LENGTH_9TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_10TRANSFERS)                  \
+     || ((LENGTH) == TIM_DMABURST_LENGTH_11TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_12TRANSFERS)                 \
+     || ((LENGTH) == TIM_DMABURST_LENGTH_13TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_14TRANSFERS)                 \
+     || ((LENGTH) == TIM_DMABURST_LENGTH_15TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_16TRANSFERS)                 \
+     || ((LENGTH) == TIM_DMABURST_LENGTH_17TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_18TRANSFERS)                 \
+     || ((LENGTH) == TIM_DMABURST_LENGTH_19TRANSFERS) || ((LENGTH) == TIM_DMABURST_LENGTH_20TRANSFERS)                 \
+     || ((LENGTH) == TIM_DMABURST_LENGTH_21TRANSFERS))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_UPDATE      ((uint16_t)0x0100)
+#define TIM_DMA_CC1         ((uint16_t)0x0200)
+#define TIM_DMA_CC2         ((uint16_t)0x0400)
+#define TIM_DMA_CC3         ((uint16_t)0x0800)
+#define TIM_DMA_CC4         ((uint16_t)0x1000)
+#define TIM_DMA_COM         ((uint16_t)0x2000)
+#define TIM_DMA_TRIG        ((uint16_t)0x4000)
+#define IsTimDmaSrc(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+
+#define TIM_EXT_TRG_PSC_OFF  ((uint16_t)0x0000)
+#define TIM_EXT_TRG_PSC_DIV2 ((uint16_t)0x1000)
+#define TIM_EXT_TRG_PSC_DIV4 ((uint16_t)0x2000)
+#define TIM_EXT_TRG_PSC_DIV8 ((uint16_t)0x3000)
+#define IsTimExtPreDiv(PRESCALER)                                                                                      \
+    (((PRESCALER) == TIM_EXT_TRG_PSC_OFF) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV2)                                     \
+     || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV4) || ((PRESCALER) == TIM_EXT_TRG_PSC_DIV8))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TRIG_SEL_IN_TR0  ((uint16_t)0x0000)
+#define TIM_TRIG_SEL_IN_TR1  ((uint16_t)0x0010)
+#define TIM_TRIG_SEL_IN_TR2  ((uint16_t)0x0020)
+#define TIM_TRIG_SEL_IN_TR3  ((uint16_t)0x0030)
+#define TIM_TRIG_SEL_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TRIG_SEL_TI1FP1  ((uint16_t)0x0050)
+#define TIM_TRIG_SEL_TI2FP2  ((uint16_t)0x0060)
+#define TIM_TRIG_SEL_ETRF    ((uint16_t)0x0070)
+#define IsTimTrigSel(SELECTION)                                                                                        \
+    (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1)                                      \
+     || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3)                                   \
+     || ((SELECTION) == TIM_TRIG_SEL_TI1F_ED) || ((SELECTION) == TIM_TRIG_SEL_TI1FP1)                                  \
+     || ((SELECTION) == TIM_TRIG_SEL_TI2FP2) || ((SELECTION) == TIM_TRIG_SEL_ETRF))
+#define IsTimInterTrigSel(SELECTION)                                                                                   \
+    (((SELECTION) == TIM_TRIG_SEL_IN_TR0) || ((SELECTION) == TIM_TRIG_SEL_IN_TR1)                                      \
+     || ((SELECTION) == TIM_TRIG_SEL_IN_TR2) || ((SELECTION) == TIM_TRIG_SEL_IN_TR3))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+
+#define TIM_EXT_CLK_SRC_TI1   ((uint16_t)0x0050)
+#define TIM_EXT_CLK_SRC_TI2   ((uint16_t)0x0060)
+#define TIM_EXT_CLK_SRC_TI1ED ((uint16_t)0x0040)
+#define IsTimExtClkSrc(SOURCE)                                                                                         \
+    (((SOURCE) == TIM_EXT_CLK_SRC_TI1) || ((SOURCE) == TIM_EXT_CLK_SRC_TI2) || ((SOURCE) == TIM_EXT_CLK_SRC_TI1ED))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_EXT_TRIG_POLARITY_INVERTED    ((uint16_t)0x8000)
+#define TIM_EXT_TRIG_POLARITY_NONINVERTED ((uint16_t)0x0000)
+#define IsTimExtTrigPolarity(POLARITY)                                                                                 \
+    (((POLARITY) == TIM_EXT_TRIG_POLARITY_INVERTED) || ((POLARITY) == TIM_EXT_TRIG_POLARITY_NONINVERTED))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+
+#define TIM_PSC_RELOAD_MODE_UPDATE    ((uint16_t)0x0000)
+#define TIM_PSC_RELOAD_MODE_IMMEDIATE ((uint16_t)0x0001)
+#define IsTimPscReloadMode(RELOAD)                                                                                     \
+    (((RELOAD) == TIM_PSC_RELOAD_MODE_UPDATE) || ((RELOAD) == TIM_PSC_RELOAD_MODE_IMMEDIATE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Forced_Action
+ * @{
+ */
+
+#define TIM_FORCED_ACTION_ACTIVE   ((uint16_t)0x0050)
+#define TIM_FORCED_ACTION_INACTIVE ((uint16_t)0x0040)
+#define IsTimForceActive(OPERATE)  (((OPERATE) == TIM_FORCED_ACTION_ACTIVE) || ((OPERATE) == TIM_FORCED_ACTION_INACTIVE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Encoder_Mode
+ * @{
+ */
+
+#define TIM_ENCODE_MODE_TI1  ((uint16_t)0x0001)
+#define TIM_ENCODE_MODE_TI2  ((uint16_t)0x0002)
+#define TIM_ENCODE_MODE_TI12 ((uint16_t)0x0003)
+#define IsTimEncodeMode(MODE)                                                                                          \
+    (((MODE) == TIM_ENCODE_MODE_TI1) || ((MODE) == TIM_ENCODE_MODE_TI2) || ((MODE) == TIM_ENCODE_MODE_TI12))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EVT_SRC_UPDATE  ((uint16_t)0x0001)
+#define TIM_EVT_SRC_CC1     ((uint16_t)0x0002)
+#define TIM_EVT_SRC_CC2     ((uint16_t)0x0004)
+#define TIM_EVT_SRC_CC3     ((uint16_t)0x0008)
+#define TIM_EVT_SRC_CC4     ((uint16_t)0x0010)
+#define TIM_EVT_SRC_COM     ((uint16_t)0x0020)
+#define TIM_EVT_SRC_TRIG    ((uint16_t)0x0040)
+#define TIM_EVT_SRC_BREAK   ((uint16_t)0x0080)
+#define IsTimEvtSrc(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UPDATE_SRC_GLOBAL                                                                                          \
+    ((uint16_t)0x0000)                            /*!< Source of update is the counter overflow/underflow              \
+                                                         or the setting of UG bit, or an update generation             \
+                                                         through the slave mode controller. */
+#define TIM_UPDATE_SRC_REGULAr ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IsTimUpdateSrc(SOURCE) (((SOURCE) == TIM_UPDATE_SRC_GLOBAL) || ((SOURCE) == TIM_UPDATE_SRC_REGULAr))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Preload_State
+ * @{
+ */
+
+#define TIM_OC_PRE_LOAD_ENABLE     ((uint16_t)0x0008)
+#define TIM_OC_PRE_LOAD_DISABLE    ((uint16_t)0x0000)
+#define IsTimOcPreLoadState(STATE) (((STATE) == TIM_OC_PRE_LOAD_ENABLE) || ((STATE) == TIM_OC_PRE_LOAD_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Fast_State
+ * @{
+ */
+
+#define TIM_OC_FAST_ENABLE      ((uint16_t)0x0004)
+#define TIM_OC_FAST_DISABLE     ((uint16_t)0x0000)
+#define IsTimOcFastState(STATE) (((STATE) == TIM_OC_FAST_ENABLE) || ((STATE) == TIM_OC_FAST_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Output_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OC_CLR_ENABLE      ((uint16_t)0x0080)
+#define TIM_OC_CLR_DISABLE     ((uint16_t)0x0000)
+#define IsTimOcClrState(STATE) (((STATE) == TIM_OC_CLR_ENABLE) || ((STATE) == TIM_OC_CLR_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Trigger_Output_Source
+ * @{
+ */
+
+#define TIM_TRGO_SRC_RESET  ((uint16_t)0x0000)
+#define TIM_TRGO_SRC_ENABLE ((uint16_t)0x0010)
+#define TIM_TRGO_SRC_UPDATE ((uint16_t)0x0020)
+#define TIM_TRGO_SRC_OC1    ((uint16_t)0x0030)
+#define TIM_TRGO_SRC_OC1REF ((uint16_t)0x0040)
+#define TIM_TRGO_SRC_OC2REF ((uint16_t)0x0050)
+#define TIM_TRGO_SRC_OC3REF ((uint16_t)0x0060)
+#define TIM_TRGO_SRC_OC4REF ((uint16_t)0x0070)
+#define IsTimTrgoSrc(SOURCE)                                                                                           \
+    (((SOURCE) == TIM_TRGO_SRC_RESET) || ((SOURCE) == TIM_TRGO_SRC_ENABLE) || ((SOURCE) == TIM_TRGO_SRC_UPDATE)        \
+     || ((SOURCE) == TIM_TRGO_SRC_OC1) || ((SOURCE) == TIM_TRGO_SRC_OC1REF) || ((SOURCE) == TIM_TRGO_SRC_OC2REF)       \
+     || ((SOURCE) == TIM_TRGO_SRC_OC3REF) || ((SOURCE) == TIM_TRGO_SRC_OC4REF))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Slave_Mode
+ * @{
+ */
+
+#define TIM_SLAVE_MODE_RESET ((uint16_t)0x0004)
+#define TIM_SLAVE_MODE_GATED ((uint16_t)0x0005)
+#define TIM_SLAVE_MODE_TRIG  ((uint16_t)0x0006)
+#define TIM_SLAVE_MODE_EXT1  ((uint16_t)0x0007)
+#define IsTimSlaveMode(MODE)                                                                                           \
+    (((MODE) == TIM_SLAVE_MODE_RESET) || ((MODE) == TIM_SLAVE_MODE_GATED) || ((MODE) == TIM_SLAVE_MODE_TRIG)           \
+     || ((MODE) == TIM_SLAVE_MODE_EXT1))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MASTER_SLAVE_MODE_ENABLE  ((uint16_t)0x0080)
+#define TIM_MASTER_SLAVE_MODE_DISABLE ((uint16_t)0x0000)
+#define IsTimMasterSlaveMode(STATE)                                                                                    \
+    (((STATE) == TIM_MASTER_SLAVE_MODE_ENABLE) || ((STATE) == TIM_MASTER_SLAVE_MODE_DISABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Flags
+ * @{
+ */
+
+#define TIM_FLAG_UPDATE ((uint32_t)0x0001)
+#define TIM_FLAG_CC1    ((uint32_t)0x0002)
+#define TIM_FLAG_CC2    ((uint32_t)0x0004)
+#define TIM_FLAG_CC3    ((uint32_t)0x0008)
+#define TIM_FLAG_CC4    ((uint32_t)0x0010)
+#define TIM_FLAG_COM    ((uint32_t)0x0020)
+#define TIM_FLAG_TRIG   ((uint32_t)0x0040)
+#define TIM_FLAG_BREAK  ((uint32_t)0x0080)
+#define TIM_FLAG_CC1OF  ((uint32_t)0x0200)
+#define TIM_FLAG_CC2OF  ((uint32_t)0x0400)
+#define TIM_FLAG_CC3OF  ((uint32_t)0x0800)
+#define TIM_FLAG_CC4OF  ((uint32_t)0x1000)
+#define TIM_FLAG_CC5    ((uint32_t)0x010000)
+#define TIM_FLAG_CC6    ((uint32_t)0x020000)
+
+#define IsTimGetFlag(FLAG)                                                                                             \
+    (((FLAG) == TIM_FLAG_UPDATE) || ((FLAG) == TIM_FLAG_CC1) || ((FLAG) == TIM_FLAG_CC2) || ((FLAG) == TIM_FLAG_CC3)   \
+     || ((FLAG) == TIM_FLAG_CC4) || ((FLAG) == TIM_FLAG_COM) || ((FLAG) == TIM_FLAG_TRIG)                              \
+     || ((FLAG) == TIM_FLAG_BREAK) || ((FLAG) == TIM_FLAG_CC1OF) || ((FLAG) == TIM_FLAG_CC2OF)                         \
+     || ((FLAG) == TIM_FLAG_CC3OF) || ((FLAG) == TIM_FLAG_CC4OF) || ((FLAG) == TIM_FLAG_CC5)                           \
+     || ((FLAG) == TIM_FLAG_CC6))
+
+#define IsTimClrFlag(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IsTimInCapFilter(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_External_Trigger_Filter
+ * @{
+ */
+
+#define IsTimExtTrigFilter(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+#define TIM_CC1EN        ((uint32_t)1<<0)
+#define TIM_CC1NEN       ((uint32_t)1<<2)
+#define TIM_CC2EN        ((uint32_t)1<<4)
+#define TIM_CC2NEN       ((uint32_t)1<<6)
+#define TIM_CC3EN        ((uint32_t)1<<8)
+#define TIM_CC3NEN       ((uint32_t)1<<10)
+#define TIM_CC4EN        ((uint32_t)1<<12)
+#define TIM_CC5EN        ((uint32_t)1<<16)
+#define TIM_CC6EN        ((uint32_t)1<<20)
+
+#define IsAdvancedTimCCENFlag(FLAG)                                                                                             \
+    (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC1NEN) || ((FLAG) == TIM_CC2EN) || ((FLAG) == TIM_CC2NEN)   \
+     || ((FLAG) == TIM_CC3EN) || ((FLAG) == TIM_CC3NEN)                              \
+     || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN)   )
+#define IsGeneralTimCCENFlag(FLAG)                                                                                             \
+    (((FLAG) == TIM_CC1EN) ||  ((FLAG) == TIM_CC2EN)    \
+     || ((FLAG) == TIM_CC3EN)                             \
+     || ((FLAG) == TIM_CC4EN)      )
+
+/** @addtogroup TIM_Legacy
+ * @{
+ */
+
+#define TIM_DMA_BURST_LEN_1BYTE   TIM_DMABURST_LENGTH_1TRANSFER
+#define TIM_DMA_BURST_LEN_2BYTES  TIM_DMABURST_LENGTH_2TRANSFERS
+#define TIM_DMA_BURST_LEN_3BYTES  TIM_DMABURST_LENGTH_3TRANSFERS
+#define TIM_DMA_BURST_LEN_4BYTES  TIM_DMABURST_LENGTH_4TRANSFERS
+#define TIM_DMA_BURST_LEN_5BYTES  TIM_DMABURST_LENGTH_5TRANSFERS
+#define TIM_DMA_BURST_LEN_6BYTES  TIM_DMABURST_LENGTH_6TRANSFERS
+#define TIM_DMA_BURST_LEN_7BYTES  TIM_DMABURST_LENGTH_7TRANSFERS
+#define TIM_DMA_BURST_LEN_8BYTES  TIM_DMABURST_LENGTH_8TRANSFERS
+#define TIM_DMA_BURST_LEN_9BYTES  TIM_DMABURST_LENGTH_9TRANSFERS
+#define TIM_DMA_BURST_LEN_10BYTES TIM_DMABURST_LENGTH_10TRANSFERS
+#define TIM_DMA_BURST_LEN_11BYTES TIM_DMABURST_LENGTH_11TRANSFERS
+#define TIM_DMA_BURST_LEN_12BYTES TIM_DMABURST_LENGTH_12TRANSFERS
+#define TIM_DMA_BURST_LEN_13BYTES TIM_DMABURST_LENGTH_13TRANSFERS
+#define TIM_DMA_BURST_LEN_14BYTES TIM_DMABURST_LENGTH_14TRANSFERS
+#define TIM_DMA_BURST_LEN_15BYTES TIM_DMABURST_LENGTH_15TRANSFERS
+#define TIM_DMA_BURST_LEN_16BYTES TIM_DMABURST_LENGTH_16TRANSFERS
+#define TIM_DMA_BURST_LEN_17BYTES TIM_DMABURST_LENGTH_17TRANSFERS
+#define TIM_DMA_BURST_LEN_18BYTES TIM_DMABURST_LENGTH_18TRANSFERS
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions
+ * @{
+ */
+
+void TIM_DeInit(TIM_Module* TIMx);
+void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
+void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
+void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
+void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
+void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct);
+void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
+void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct);
+void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct);
+void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct);
+void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd);
+void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource);
+void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd);
+void TIM_ConfigInternalClk(TIM_Module* TIMx);
+void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx,
+                            uint16_t TIM_TIxExternalCLKSource,
+                            uint16_t IcPolarity,
+                            uint16_t ICFilter);
+void TIM_ConfigExtClkMode1(TIM_Module* TIMx,
+                           uint16_t TIM_ExtTRGPrescaler,
+                           uint16_t TIM_ExtTRGPolarity,
+                           uint16_t ExtTRGFilter);
+void TIM_ConfigExtClkMode2(TIM_Module* TIMx,
+                           uint16_t TIM_ExtTRGPrescaler,
+                           uint16_t TIM_ExtTRGPolarity,
+                           uint16_t ExtTRGFilter);
+void TIM_ConfigExtTrig(TIM_Module* TIMx,
+                       uint16_t TIM_ExtTRGPrescaler,
+                       uint16_t TIM_ExtTRGPolarity,
+                       uint16_t ExtTRGFilter);
+void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode);
+void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_ConfigEncoderInterface(TIM_Module* TIMx,
+                                uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity,
+                                uint16_t TIM_IC2Polarity);
+void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload);
+void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast);
+void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear);
+void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity);
+void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity);
+void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx);
+void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN);
+void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode);
+void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd);
+void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter);
+void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload);
+void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1);
+void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2);
+void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3);
+void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4);
+void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5);
+void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6);
+void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCap1(TIM_Module* TIMx);
+uint16_t TIM_GetCap2(TIM_Module* TIMx);
+uint16_t TIM_GetCap3(TIM_Module* TIMx);
+uint16_t TIM_GetCap4(TIM_Module* TIMx);
+uint16_t TIM_GetCap5(TIM_Module* TIMx);
+uint16_t TIM_GetCap6(TIM_Module* TIMx);
+uint16_t TIM_GetCnt(TIM_Module* TIMx);
+uint16_t TIM_GetPrescaler(TIM_Module* TIMx);
+uint16_t TIM_GetAutoReload(TIM_Module* TIMx);
+FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN);
+FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG);
+void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG);
+INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT);
+void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__N32G43X_TIM_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tsc.h

@@ -0,0 +1,485 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_tsc.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_TSC_H__
+#define __N32G43X_TSC_H__
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43X_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TSC
+ * @{
+ */
+
+/**
+ * @brief   TSC error code
+ */
+ typedef enum {
+    TSC_ERROR_OK            = 0x00U,  /*!< No error   */
+    TSC_ERROR_CLOCK         = 0x01U,  /*!< clock config error */
+    TSC_ERROR_PARAMETER     = 0x02U,  /*!< parameter error */
+    TSC_ERROR_HW_MODE       = 0x03U,  /*!< Exit hw mode timeout */
+
+ }TSC_ErrorTypeDef;
+ /**
+  * @
+  */
+
+/**
+ * @brief   TSC clock source
+ */
+#define TSC_CLK_SRC_LSI                 (RCC_LSXCLK_SRC_LSI)                        /*!< LSI*/
+#define TSC_CLK_SRC_LSE                 (RCC_LSE_ENABLE|RCC_LSXCLK_SRC_LSE)         /*!< LSE */
+#define TSC_CLK_SRC_LSE_BYPASS          (RCC_LSE_BYPASS|RCC_LSXCLK_SRC_LSE)         /*!< LSE bypass */
+/**
+ * @
+ */
+
+
+/**
+ * @defgroup Detect_Period
+ */
+#define TSC_DET_PERIOD_8    (0x00000000U)                       /*!< DET_PERIOD[3:0] = 8/TSC_CLOCK   */
+#define TSC_DET_PERIOD_16   (0x01UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000001U DET_PERIOD[3:0] = 16/TSC_CLOCK  */
+#define TSC_DET_PERIOD_24   (0x02UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000002U DET_PERIOD[3:0] = 24/TSC_CLOCK  */
+#define TSC_DET_PERIOD_32   (0x03UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000003U DET_PERIOD[3:0] = 32/TSC_CLOCK(default)  */
+#define TSC_DET_PERIOD_40   (0x04UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000004U DET_PERIOD[3:0] = 40/TSC_CLOCK  */
+#define TSC_DET_PERIOD_48   (0x05UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000005U DET_PERIOD[3:0] = 48/TSC_CLOCK  */
+#define TSC_DET_PERIOD_56   (0x06UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000006U DET_PERIOD[3:0] = 56/TSC_CLOCK  */
+#define TSC_DET_PERIOD_64   (0x07UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000007U DET_PERIOD[3:0] = 64/TSC_CLOCK  */
+#define TSC_DET_PERIOD_72   (0x08UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000008U DET_PERIOD[3:0] = 72/TSC_CLOCK  */
+#define TSC_DET_PERIOD_80   (0x09UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000009U DET_PERIOD[3:0] = 80/TSC_CLOCK  */
+#define TSC_DET_PERIOD_88   (0x0AUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000AU DET_PERIOD[3:0] = 88/TSC_CLOCK  */
+#define TSC_DET_PERIOD_96   (0x0BUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000BU DET_PERIOD[3:0] = 96/TSC_CLOCK  */
+#define TSC_DET_PERIOD_104  (0x0CUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000CU DET_PERIOD[3:0] = 104/TSC_CLOCK   */
+/**
+ * @
+ */
+
+/**
+ * @defgroup Detect_Filter
+ */
+#define TSC_DET_FILTER_1    (0x00000000U)                       /*!< DET_FILTER[3:0] = 1 sample   */
+#define TSC_DET_FILTER_2    (0x01UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000010U DET_FILTER[3:0] = 2 samples */
+#define TSC_DET_FILTER_3    (0x02UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000020U DET_FILTER[3:0] = 3 samples  */
+#define TSC_DET_FILTER_4    (0x03UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000030U DET_FILTER[3:0] = 4 samples  */
+/**
+ * @
+ */
+
+/**
+ * @defgroup HW_Detect_Mode
+ */
+#define TSC_HW_DET_MODE_DISABLE (0x00000000U)                           /*!< Hardware detect mode disable   */
+#define TSC_HW_DET_MODE_ENABLE  (0x01UL << TSC_CTRL_HW_DET_MODE_Pos)    /*!< 0x00000040U Hardware detect mode enable */
+/**
+ * @
+ */
+
+/**
+ * @defgroup Detect_Type
+ */
+#define TSC_DET_TYPE_Msk    (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk)
+#define TSC_DET_TYPE_Pos    (TSC_CTRL_LESS_DET_SEL_Pos)
+
+#define TSC_DET_TYPE_NONE   (0UL)                           /*!< 0x00000000U Disable detect */
+#define TSC_DET_TYPE_LESS   (0x01UL << TSC_DET_TYPE_Pos)    /*!< 0x00000100U Less detect enable */
+#define TSC_DET_TYPE_GREAT  (0x02UL << TSC_DET_TYPE_Pos)    /*!< 0x00000200U Great detect enable */
+#define TSC_DET_TYPE_PERIOD (0x03UL << TSC_DET_TYPE_Pos)    /*!< 0x00000300U Both great and less detct enable */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Interrupt
+ */
+#define TSC_IT_DET_ENABLE       (TSC_CTRL_DET_INTEN)    /*!< Enable TSC detect interrupt */
+#define TSC_IT_DET_DISABLE      (0UL)                   /*!< Disable TSC detect interrupt */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Out
+ */
+#define TSC_OUT_PIN         (0x00000000U)                   /*!< TSC output to TSC_OUT pin */
+#define TSC_OUT_TIM4_ETR    (0x1UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM4 ETR */
+#define TSC_OUT_TIM2_ETR    (0x2UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM2 ETR and TIM2 CH1*/
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Flag
+ */
+#define TSC_FLAG_HW         (0x1UL << TSC_CTRL_HW_DET_ST_Pos)       /*!< Flag of hardware detect mode */
+
+#define TSC_FLAG_GREAT_DET  (0x1UL << TSC_STS_GREAT_DET_Pos)        /*!< Flag of great detect type */
+#define TSC_FLAG_LESS_DET   (0x1UL << TSC_STS_LESS_DET_Pos)         /*!< Flag of less detect type */
+#define TSC_FLAG_PERIOD_DET (TSC_FLAG_GREAT_DET|TSC_FLAG_LESS_DET)  /*!< Flag of period detect type */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_SW_Detect
+ */
+#define TSC_SW_MODE_DISABLE (0x00000000U)                           /*!< Disable software detect mode */
+#define TSC_SW_MODE_ENABLE  (0x1UL << TSC_ANA_CTRL_SW_TSC_EN_Pos)   /*!< Enable software detect mode */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_PadOption
+ */
+#define TSC_PAD_INTERNAL_RES    (0x00000000U)                       /*!< Use internal resistor */
+#define TSC_PAD_EXTERNAL_RES    (0x1UL << TSC_ANA_SEL_PAD_OPT_Pos)  /*!< Use external resistor */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_PadSpeed
+ */
+#define TSC_PAD_SPEED_0     (0x00000000U)                       /*!< Low speed,about 100K */
+#define TSC_PAD_SPEED_1     (0x1UL << TSC_ANA_SEL_SP_OPT_Pos)   /*!< Middle spped */
+#define TSC_PAD_SPEED_2     (0x2UL << TSC_ANA_SEL_SP_OPT_Pos)   /*!< Middle spped */
+#define TSC_PAD_SPEED_3     (0x3UL << TSC_ANA_SEL_SP_OPT_Pos)   /*!< Middle spped */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_Constant
+ */
+#define TSC_CHN_SEL_ALL             (TSC_CHNEN_CHN_SELx_Msk)
+#define MAX_TSC_HW_CHN              (24)        /*Maximum number of tsc pin*/
+#define MAX_TSC_THRESHOLD_BASE      (2047)      /*Maximum detect base value of threshold*/
+#define MAX_TSC_THRESHOLD_DELTA     (255)       /*Maximum detect delta value of threshold*/
+#define TSC_TIMEOUT                 (0x01000000)   /*TSC normal timeout */
+/**
+ * @
+ */
+
+/**
+ * @defgroup TSC_DetectMode
+ */
+#define TSC_HW_DETECT_MODE      (0x00000001U)   /*TSC hardware detect mode*/
+#define TSC_SW_DETECT_MODE      (0x00000000U)   /*TSC software detect mode*/
+/**
+ * @
+ */
+
+/* TSC Exported macros -----------------------------------------------------------*/
+/** @defgroup TSC_Exported_Macros
+ * @{
+ */
+
+/** @brief  Enable the TSC HW detect mode
+ * @param  None
+ * @retval None
+ */
+#define __TSC_HW_ENABLE()       SET_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE)
+
+/** @brief  Disable the TSC HW detect mode
+ * @param  None
+ * @retval None
+ */
+#define __TSC_HW_DISABLE()      CLEAR_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE)
+
+/** @brief  Config TSC detect period for HW detect mode
+ * @param  __PERIOD__  specifies the TSC detect period during HW detect mode
+ *     @arg TSC_DET_PERIOD_8:  Detect period = 8/TSC_CLK
+ *     @arg TSC_DET_PERIOD_16: Detect Period = 1/TSC_CLK
+ *     @arg TSC_DET_PERIOD_24: Detect Period = 2/TSC_CLK
+ *     @arg TSC_DET_PERIOD_32: Detect Period = 3/TSC_CLK
+ *     @arg TSC_DET_PERIOD_40: Detect Period = 4/TSC_CLK
+ *     @arg TSC_DET_PERIOD_48: Detect Period = 5/TSC_CLK
+ *     @arg TSC_DET_PERIOD_56: Detect Period = 6/TSC_CLK
+ *     @arg TSC_DET_PERIOD_64: Detect Period = 7/TSC_CLK
+ *     @arg TSC_DET_PERIOD_72: Detect Period = 7/TSC_CLK
+ *     @arg TSC_DET_PERIOD_80: Detect Period = 7/TSC_CLK
+ *     @arg TSC_DET_PERIOD_88: Detect Period = 7/TSC_CLK
+ *     @arg TSC_DET_PERIOD_96: Detect Period = 7/TSC_CLK
+ *     @arg TSC_DET_PERIOD_104:Detect Period = 7/TSC_CLK
+ * @retval None
+ */
+#define __TSC_PERIOD_CONFIG(__PERIOD__)     MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_PERIOD_Msk,__PERIOD__)
+
+/** @brief  Config TSC detect filter for HW detect mode
+ * @param  __FILTER__  specifies the least usefull continuous samples during HW detect mode
+ *     @arg TSC_DET_FILTER_1: Detect filter = 1 pulse
+ *     @arg TSC_DET_FILTER_2: Detect filter = 2 pulse
+ *     @arg TSC_DET_FILTER_3: Detect filter = 3 pulse
+ *     @arg TSC_DET_FILTER_4: Detect filter = 4 pulse
+ * @retval None
+ */
+#define __TSC_FILTER_CONFIG(__FILTER__)     MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_FILTER_Msk,__FILTER__)
+
+/** @brief  Config TSC detect type for HW detect mode,less great or both
+ * @param  __TYPE__  specifies the detect type of a sample during HW detect mode
+ *     @arg TSC_DET_TYPE_NONE:  Detect disable
+ *     @arg TSC_DET_TYPE_LESS:  Pulse number must be greater than the threshold(basee-delta) during a sample time
+ *     @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time
+ *     @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta)
+                                 and also be less than (basee+delta) during a sample time
+ * @retval None
+ */
+#define __TSC_LESS_GREAT_CONFIG(__TYPE__)   MODIFY_REG(TSC->CTRL,                                           \
+                                                       (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk),  \
+                                                       __TYPE__)
+
+/** @brief  Enable TSC interrupt
+ * @param  None
+ * @retval None
+ */
+#define __TSC_INT_ENABLE()                  SET_BIT(TSC->CTRL, TSC_IT_DET_ENABLE)
+
+/** @brief  Disable TSC interrupt
+ * @param  None
+ * @retval None
+ */
+#define __TSC_INT_DISABLE()                  CLEAR_BIT(TSC->CTRL, TSC_IT_DET_ENABLE)
+
+/** @brief  Config the TSC output
+ * @param  __OUT__  specifies where the TSC output should go
+ *     @arg TSC_OUT_PIN:      TSC output to the TSC_OUT pin
+ *     @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR
+ *     @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR
+ * @retval None
+ */
+#define __TSC_OUT_CONFIG(__OUT__)           MODIFY_REG( TSC->CTRL,  \
+                                                        (TSC_CTRL_TM4_ETR_Msk|TSC_CTRL_TM2_ETR_CH1_Msk),\
+                                                        __OUT__)
+
+/** @brief  Config the TSC channel
+ * @param  __CHN__  specifies the pin of channels used for detect
+ *              This parameter:bit[0:23] used,bit[24:31] must be 0
+ *                  bitx: TSC channel x
+ * @retval None
+ */
+#define __TSC_CHN_CONFIG(__CHN__)           WRITE_REG(TSC->CHNEN, __CHN__)
+
+/** @brief  Enable the TSC SW detect mode
+ * @param  None
+ * @retval None
+ */
+#define __TSC_SW_ENABLE()           SET_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN)
+
+/** @brief  Disable the TSC SW detect mode
+ * @param  None
+ * @retval None
+ */
+#define __TSC_SW_DISABLE()          CLEAR_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN)
+
+/** @brief  Config the detect channel number during SW detect mode
+ * @param  __NUM__  specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval None
+ */
+#define __TSC_SW_CHN_NUM_CONFIG(__NUM__)    MODIFY_REG(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_PAD_MUX_Msk,__NUM__)
+
+/** @brief  Config the pad charge type
+ * @param  __OPT__  specifies which resistor is used for charge
+ *     @arg TSC_PAD_INTERNAL_RES: Internal resistor is used
+ *     @arg TSC_PAD_EXTERNAL_RES: External resistor is used
+ * @retval None
+ */
+#define __TSC_PAD_OPT_CONFIG(__OPT__)       MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_PAD_OPT_Msk,__OPT__)
+
+/** @brief  Config TSC speed
+ * @param  __SPEED__  specifies the TSC speed range
+ *     @arg TSC_PAD_SPEED_0: Low speed
+ *     @arg TSC_PAD_SPEED_1: Middle speed
+ *     @arg TSC_PAD_SPEED_2: Middle speed
+ *     @arg TSC_PAD_SPEED_3: High speed
+ * @retval None
+ */
+#define __TSC_PAD_SPEED_CONFIG(__SPEED__)   MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_SP_OPT_Msk,__SPEED__)
+
+
+/** @brief  Check if the HW detect mode is enable
+ * @param  None
+ * @retval Current state of HW detect mode
+ */
+#define __TSC_GET_HW_MODE()                 (((TSC->CTRL) & TSC_FLAG_HW) == (TSC_FLAG_HW))
+
+/** @brief  Check the detect type during HW detect mode
+ * @param  __FLAG__  specifies the flag of detect type
+ *     @arg TSC_FLAG_LESS_DET:   Flag of less detect type
+ *     @arg TSC_FLAG_GREAT_DET:  Flag of great detect type
+ *     @arg TSC_FLAG_PERIOD_DET: Flag of priod detect type
+ * @retval Current state of flag
+ */
+#define __TSC_GET_HW_DET_TYPE(__FLAG__)     (((TSC->STS) & (__FLAG__))==(__FLAG__))
+
+/** @brief  Get the number of channel which is detected now
+ * @param  None
+ * @retval Current channel number
+ */
+#define __TSC_GET_CHN_NUMBER()              (((TSC->STS) & TSC_STS_CHN_NUM_Msk) >> TSC_STS_CHN_NUM_Pos )
+
+/** @brief  Get the count value of pulse
+ * @param  None
+ * @retval Pulse count of current channel
+ */
+#define __TSC_GET_CHN_CNT()                 (((TSC->STS) & TSC_STS_CNT_VAL_Msk ) >> TSC_STS_CNT_VAL_Pos )
+
+/** @brief  Get the base value of one channel
+ * @param  __NUM__  specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval base value of the channel
+ */
+#define __TSC_GET_CHN_BASE(__NUM__)   ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_BASE_Msk ) >> TSC_THRHDx_BASE_Pos)
+
+/** @brief  Get the delta value of one channel
+ * @param  __NUM__  specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval delta value of the channel
+ */
+#define __TSC_GET_CHN_DELTA(__NUM__)  ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_DELTA_Msk ) >> TSC_THRHDx_DELTA_Pos )
+
+/** @brief  Get the internal resist value of one channel
+ * @param  __NUM__  specifies channel number,must be less than MAX_TSC_HW_CHN
+ * @retval resist value of the channel
+ */
+#define __TSC_GET_CHN_RESIST(__NUM__)  ((TSC->RESR[(__NUM__)>>3] >>(((__NUM__) & 0x7UL)*4)) & TSC_RESRx_CHN_RESIST_Msk)
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TSC_Private_Macros
+ * @{
+ */
+#define IS_TSC_DET_PERIOD(_PERIOD_)   \
+        (((_PERIOD_)==TSC_DET_PERIOD_8)  ||((_PERIOD_)==TSC_DET_PERIOD_16)||((_PERIOD_)==TSC_DET_PERIOD_24)       \
+        ||((_PERIOD_)==TSC_DET_PERIOD_32)||((_PERIOD_)==TSC_DET_PERIOD_40)||((_PERIOD_)==TSC_DET_PERIOD_48)     \
+        ||((_PERIOD_)==TSC_DET_PERIOD_56)||((_PERIOD_)==TSC_DET_PERIOD_64)||((_PERIOD_)==TSC_DET_PERIOD_72)     \
+        ||((_PERIOD_)==TSC_DET_PERIOD_80)||((_PERIOD_)==TSC_DET_PERIOD_88)||((_PERIOD_)==TSC_DET_PERIOD_96)     \
+        ||((_PERIOD_)==TSC_DET_PERIOD_104)  )
+
+#define IS_TSC_FILTER(_FILTER_)   \
+        (   ((_FILTER_)==TSC_DET_FILTER_1) ||((_FILTER_)==TSC_DET_FILTER_2)\
+          ||((_FILTER_)==TSC_DET_FILTER_3) ||((_FILTER_)==TSC_DET_FILTER_4) )
+
+#define IS_TSC_DET_MODE(_MODE_)   \
+        ( ((_MODE_)==TSC_HW_DETECT_MODE) ||((_MODE_)==TSC_SW_DETECT_MODE)   )
+
+#define IS_TSC_DET_TYPE(_TYPE_)   \
+        ( ((_TYPE_)==TSC_DET_TYPE_GREAT) ||((_TYPE_)==TSC_DET_TYPE_LESS)    \
+        ||((_TYPE_)==TSC_DET_TYPE_PERIOD)|| ((_TYPE_)==TSC_DET_TYPE_NONE) )
+
+#define IS_TSC_INT(_INT_)           (((_INT_)==TSC_IT_DET_ENABLE)||((_INT_)==TSC_IT_DET_DISABLE))
+
+#define IS_TSC_OUT(_ETR_)           (((_ETR_)==TSC_OUT_PIN)||((_ETR_)==TSC_OUT_TIM2_ETR)||((_ETR_)==TSC_OUT_TIM4_ETR))
+
+#define IS_TSC_CHN(_CHN_)           (0==((_CHN_)&(~TSC_CHNEN_CHN_SELx_Msk)))
+
+#define IS_TSC_CHN_NUMBER(_NUM_)    ( ((_NUM_)==1)                      \
+                                    ||(((_NUM_)>=4) && ((_NUM_)<=17))    \
+                                    ||(((_NUM_)>=19) && ((_NUM_)<=23)) )
+
+#define IS_TSC_PAD_OPTION(_OPT_)    (((_OPT_)==TSC_PAD_INTERNAL_RES)||((_OPT_)==TSC_PAD_EXTERNAL_RES))
+
+#define IS_TSC_PAD_SPEED(_SPEED_)       \
+        ( ((_SPEED_)==TSC_PAD_SPEED_0)||((_SPEED_)==TSC_PAD_SPEED_1)        \
+        ||((_SPEED_)==TSC_PAD_SPEED_2)||((_SPEED_)==TSC_PAD_SPEED_3)  )
+
+#define IS_TSC_RESISTOR_VALUE(_RES_)     \
+        ( ((_RES_)==TSC_RESRx_CHN_RESIST_0)||((_RES_)==TSC_RESRx_CHN_RESIST_1)        \
+        ||((_RES_)==TSC_RESRx_CHN_RESIST_2)||((_RES_)==TSC_RESRx_CHN_RESIST_3)        \
+        ||((_RES_)==TSC_RESRx_CHN_RESIST_4)||((_RES_)==TSC_RESRx_CHN_RESIST_5)        \
+        ||((_RES_)==TSC_RESRx_CHN_RESIST_6)||((_RES_)==TSC_RESRx_CHN_RESIST_7)  )
+
+#define IS_TSC_THRESHOLD_BASE(_BASE_)       ( (_BASE_)<=MAX_TSC_THRESHOLD_BASE)
+
+
+#define IS_TSC_THRESHOLD_DELTA(_DELTA_)     ( (_DELTA_)<=MAX_TSC_THRESHOLD_DELTA)
+
+/**
+* @brief TSC Init structure definition
+*/
+
+typedef struct
+{
+    uint32_t Mode;      /*!< Configures the TSC work mode.
+                            This parameter can be one value of @ref TSC_DetectMode */
+    uint32_t Period;    /*!< Configures the TSC check period for a sample.
+                            This parameter can be one value of @ref Detect_Period */
+    uint32_t Filter;    /*!< Configures the TSC filter.
+                            This parameter can be one value of @ref Detect_Filter */
+    uint32_t Type;      /*!< Configures the TSC check type
+                            This parameter can be one value of @ref Detect_Type */
+    uint32_t Chn;       /*!< Selects the TSC chnnel used
+                            This parameter can be one value of @ref TSC_CHNEN_CHN_SELx_Msk */
+    uint32_t Out;       /*!< Configures the TSC_OUT etr
+                            This parameter can be one value of @ref TSC_Out */
+    uint32_t Int;       /*!< Configures the TSC interrupt
+                            This parameter can be one value of @ref TSC_Interrupt */
+    uint32_t PadOpt;    /*!< Configures the TSC charge resistor
+                            This parameter can be one value of @ref TSC_PadOption */
+    uint32_t Speed;     /*!< Configures the TSC detect speed
+                            This parameter can be one value of @ref TSC_PadSpeed */
+}TSC_InitType;
+
+typedef struct
+{
+    uint16_t    TSC_Base;       /*!< base value */
+    uint8_t     TSC_Delta;      /*!< offset value  */
+    uint8_t     TSC_Resistor;   /*!< resistance value configuration*/
+} TSC_ChnCfg;
+
+TSC_ErrorTypeDef TSC_Init(TSC_InitType* InitParam);
+TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource);
+TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res );
+TSC_ErrorTypeDef TSC_ConfigThreshold(  uint32_t Channels, uint32_t base, uint32_t delta);
+TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X_TSC_H__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_usart.h

@@ -0,0 +1,397 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_usart.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43x_USART_H__
+#define __N32G43x_USART_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/** @addtogroup USART_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief  USART Init Structure definition
+ */
+
+typedef struct
+{
+    uint32_t BaudRate; /*!< This member configures the USART communication baud rate.
+                                  The baud rate is computed using the following formula:
+                                   - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->BaudRate)))
+                                   - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+    uint16_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+                                    This parameter can be a value of @ref USART_Word_Length */
+
+    uint16_t StopBits; /*!< Specifies the number of stop bits transmitted.
+                                  This parameter can be a value of @ref USART_Stop_Bits */
+
+    uint16_t Parity; /*!< Specifies the parity mode.
+                                This parameter can be a value of @ref Parity
+                                @note When parity is enabled, the computed parity is inserted
+                                      at the MSB position of the transmitted data (9th bit when
+                                      the word length is set to 9 data bits; 8th bit when the
+                                      word length is set to 8 data bits). */
+
+    uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                              This parameter can be a value of @ref Mode */
+
+    uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+                                             or disabled.
+                                             This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitType;
+
+/**
+ * @brief  USART Clock Init Structure definition
+ */
+
+typedef struct
+{
+    uint16_t Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+                               This parameter can be a value of @ref Clock */
+
+    uint16_t Polarity; /*!< Specifies the steady state value of the serial clock.
+                              This parameter can be a value of @ref USART_Clock_Polarity */
+
+    uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made.
+                              This parameter can be a value of @ref USART_Clock_Phase */
+
+    uint16_t LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                 data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                 This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitType;
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Constants
+ * @{
+ */
+
+#define IS_USART_ALL_PERIPH(PERIPH)                                                                                    \
+    (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) || ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3))
+
+#define IS_USART_1234_PERIPH(PERIPH)                                                                                   \
+    (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4))
+/** @addtogroup USART_Word_Length
+ * @{
+ */
+
+#define USART_WL_8B ((uint16_t)0x0000)
+#define USART_WL_9B ((uint16_t)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WL_8B) || ((LENGTH) == USART_WL_9B))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Stop_Bits
+ * @{
+ */
+
+#define USART_STPB_1   ((uint16_t)0x0000)
+#define USART_STPB_0_5 ((uint16_t)0x1000)
+#define USART_STPB_2   ((uint16_t)0x2000)
+#define USART_STPB_1_5 ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS)                                                                                    \
+    (((STOPBITS) == USART_STPB_1) || ((STOPBITS) == USART_STPB_0_5) || ((STOPBITS) == USART_STPB_2)                    \
+     || ((STOPBITS) == USART_STPB_1_5))
+/**
+ * @}
+ */
+
+/** @addtogroup Parity
+ * @{
+ */
+
+#define USART_PE_NO             ((uint16_t)0x0000)
+#define USART_PE_EVEN           ((uint16_t)0x0400)
+#define USART_PE_ODD            ((uint16_t)0x0600)
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PE_NO) || ((PARITY) == USART_PE_EVEN) || ((PARITY) == USART_PE_ODD))
+/**
+ * @}
+ */
+
+/** @addtogroup Mode
+ * @{
+ */
+
+#define USART_MODE_RX       ((uint16_t)0x0004)
+#define USART_MODE_TX       ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Hardware_Flow_Control
+ * @{
+ */
+#define USART_HFCTRL_NONE    ((uint16_t)0x0000)
+#define USART_HFCTRL_RTS     ((uint16_t)0x0100)
+#define USART_HFCTRL_CTS     ((uint16_t)0x0200)
+#define USART_HFCTRL_RTS_CTS ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)                                                                        \
+    (((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL_CTS)            \
+     || ((CONTROL) == USART_HFCTRL_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @addtogroup Clock
+ * @{
+ */
+#define USART_CLK_DISABLE     ((uint16_t)0x0000)
+#define USART_CLK_ENABLE      ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLK_DISABLE) || ((CLOCK) == USART_CLK_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Clock_Polarity
+ * @{
+ */
+
+#define USART_CLKPOL_LOW    ((uint16_t)0x0000)
+#define USART_CLKPOL_HIGH   ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CLKPOL_LOW) || ((CPOL) == USART_CLKPOL_HIGH))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Clock_Phase
+ * @{
+ */
+
+#define USART_CLKPHA_1EDGE  ((uint16_t)0x0000)
+#define USART_CLKPHA_2EDGE  ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CLKPHA_1EDGE) || ((CPHA) == USART_CLKPHA_2EDGE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Last_Bit
+ * @{
+ */
+
+#define USART_CLKLB_DISABLE       ((uint16_t)0x0000)
+#define USART_CLKLB_ENABLE        ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_CLKLB_DISABLE) || ((LASTBIT) == USART_CLKLB_ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Interrupt_definition
+ * @{
+ */
+
+#define USART_INT_PEF   ((uint16_t)0x0028)
+#define USART_INT_TXDE  ((uint16_t)0x0727)
+#define USART_INT_TXC   ((uint16_t)0x0626)
+#define USART_INT_RXDNE ((uint16_t)0x0525)
+#define USART_INT_IDLEF ((uint16_t)0x0424)
+#define USART_INT_LINBD ((uint16_t)0x0846)
+#define USART_INT_CTSF  ((uint16_t)0x096A)
+#define USART_INT_ERRF  ((uint16_t)0x0060)
+#define USART_INT_OREF  ((uint16_t)0x0360)
+#define USART_INT_NEF   ((uint16_t)0x0260)
+#define USART_INT_FEF   ((uint16_t)0x0160)
+#define IS_USART_CFG_INT(IT)                                                                                           \
+    (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE)       \
+     || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF)                             \
+     || ((IT) == USART_INT_ERRF))
+#define IS_USART_GET_INT(IT)                                                                                           \
+    (((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE)       \
+     || ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) || ((IT) == USART_INT_OREF) \
+     || ((IT) == USART_INT_NEF) || ((IT) == USART_INT_FEF))
+#define IS_USART_CLR_INT(IT)                                                                                           \
+    (((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_DMA_Requests
+ * @{
+ */
+
+#define USART_DMAREQ_TX         ((uint16_t)0x0080)
+#define USART_DMAREQ_RX         ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_WakeUp_methods
+ * @{
+ */
+
+#define USART_WUM_IDLELINE      ((uint16_t)0x0000)
+#define USART_WUM_ADDRMASK      ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WUM_IDLELINE) || ((WAKEUP) == USART_WUM_ADDRMASK))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_LIN_Break_Detection_Length
+ * @{
+ */
+
+#define USART_LINBDL_10B                         ((uint16_t)0x0000)
+#define USART_LINBDL_11B                         ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBDL_10B) || ((LENGTH) == USART_LINBDL_11B))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_IrDA_Low_Power
+ * @{
+ */
+
+#define USART_IRDAMODE_LOWPPWER  ((uint16_t)0x0004)
+#define USART_IRDAMODE_NORMAL    ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IRDAMODE_LOWPPWER) || ((MODE) == USART_IRDAMODE_NORMAL))
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Flags
+ * @{
+ */
+
+#define USART_FLAG_CTSF  ((uint16_t)0x0200)
+#define USART_FLAG_LINBD ((uint16_t)0x0100)
+#define USART_FLAG_TXDE  ((uint16_t)0x0080)
+#define USART_FLAG_TXC   ((uint16_t)0x0040)
+#define USART_FLAG_RXDNE ((uint16_t)0x0020)
+#define USART_FLAG_IDLEF ((uint16_t)0x0010)
+#define USART_FLAG_OREF  ((uint16_t)0x0008)
+#define USART_FLAG_NEF   ((uint16_t)0x0004)
+#define USART_FLAG_FEF   ((uint16_t)0x0002)
+#define USART_FLAG_PEF   ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG)                                                                                            \
+    (((FLAG) == USART_FLAG_PEF) || ((FLAG) == USART_FLAG_TXDE) || ((FLAG) == USART_FLAG_TXC)                           \
+     || ((FLAG) == USART_FLAG_RXDNE) || ((FLAG) == USART_FLAG_IDLEF) || ((FLAG) == USART_FLAG_LINBD)                   \
+     || ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_OREF) || ((FLAG) == USART_FLAG_NEF)                       \
+     || ((FLAG) == USART_FLAG_FEF))
+
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG)                                                                       \
+    ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE))                              \
+     || ((USART_FLAG) != USART_FLAG_CTSF))
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x00337F99))
+#define IS_USART_ADDRESS(ADDRESS)   ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA)         ((DATA) <= 0x1FF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions
+ * @{
+ */
+
+void USART_DeInit(USART_Module* USARTx);
+void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct);
+void USART_StructInit(USART_InitType* USART_InitStruct);
+void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct);
+void USART_Enable(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd);
+void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd);
+void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr);
+void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode);
+void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd);
+void USART_SendData(USART_Module* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_Module* USARTx);
+void USART_SendBreak(USART_Module* USARTx);
+void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler);
+void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd);
+void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd);
+void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd);
+void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode);
+void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd);
+FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG);
+void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG);
+INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT);
+void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43x_USART_H__ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h

@@ -0,0 +1,122 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_wwdg.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __N32G43X_WWDG_H__
+#define __N32G43X_WWDG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "n32g43x.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/** @addtogroup WWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup WWDG_Prescaler
+ * @{
+ */
+
+#define WWDG_PRESCALER_DIV1 ((uint32_t)0x00000000)
+#define WWDG_PRESCALER_DIV2 ((uint32_t)0x00000080)
+#define WWDG_PRESCALER_DIV4 ((uint32_t)0x00000100)
+#define WWDG_PRESCALER_DIV8 ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER_DIV(PRESCALER)                                                                               \
+    (((PRESCALER) == WWDG_PRESCALER_DIV1) || ((PRESCALER) == WWDG_PRESCALER_DIV2)                                      \
+     || ((PRESCALER) == WWDG_PRESCALER_DIV4) || ((PRESCALER) == WWDG_PRESCALER_DIV8))
+#define IS_WWDG_WVALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_CNT(COUNTER)  (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Functions
+ * @{
+ */
+
+void WWDG_DeInit(void);
+void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler);
+void WWDG_SetWValue(uint8_t WindowValue);
+void WWDG_EnableInt(void);
+void WWDG_SetCnt(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetEWINTF(void);
+void WWDG_ClrEWINTF(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N32G43X__WWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/misc.c

@@ -0,0 +1,229 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file misc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "misc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/** @addtogroup MISC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Defines
+ * @{
+ */
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup specifies the priority grouping bits length.
+ *   This parameter can be one of the following values:
+ *     @arg NVIC_PriorityGroup_0 0 bits for pre-emption priority
+ *                                4 bits for subpriority
+ *     @arg NVIC_PriorityGroup_1 1 bits for pre-emption priority
+ *                                3 bits for subpriority
+ *     @arg NVIC_PriorityGroup_2 2 bits for pre-emption priority
+ *                                2 bits for subpriority
+ *     @arg NVIC_PriorityGroup_3 3 bits for pre-emption priority
+ *                                1 bits for subpriority
+ *     @arg NVIC_PriorityGroup_4 4 bits for pre-emption priority
+ *                                0 bits for subpriority
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+    /* Check the parameters */
+    assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+    /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+    SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @brief  Initializes the NVIC peripheral according to the specified
+ *         parameters in the NVIC_InitStruct.
+ * @param NVIC_InitStruct pointer to a NVIC_InitType structure that contains
+ *         the configuration information for the specified NVIC peripheral.
+ */
+void NVIC_Init(NVIC_InitType* NVIC_InitStruct)
+{
+    uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+    assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+    assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+    if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+    {
+        /* Compute the Corresponding IRQ Priority --------------------------------*/
+        tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08;
+        tmppre      = (0x4 - tmppriority);
+        tmpsub      = tmpsub >> tmppriority;
+
+        tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+        tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+        tmppriority = tmppriority << 0x04;
+
+        NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+        /* Enable the Selected IRQ Channels --------------------------------------*/
+        NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
+                                                               << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+    }
+    else
+    {
+        /* Disable the Selected IRQ Channels -------------------------------------*/
+        NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
+                                                               << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+    }
+}
+
+/**
+ * @brief  Sets the vector table location and Offset.
+ * @param NVIC_VectTab specifies if the vector table is in RAM or FLASH memory.
+ *   This parameter can be one of the following values:
+ *     @arg NVIC_VectTab_RAM
+ *     @arg NVIC_VectTab_FLASH
+ * @param Offset Vector Table base offset field. This value must be a multiple
+ *         of 0x200.
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+    /* Check the parameters */
+    assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+    assert_param(IS_NVIC_OFFSET(Offset));
+
+    SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief  Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode Specifies the new mode for the system to enter low power mode.
+ *   This parameter can be one of the following values:
+ *     @arg NVIC_LP_SEVONPEND
+ *     @arg NVIC_LP_SLEEPDEEP
+ *     @arg NVIC_LP_SLEEPONEXIT
+ * @param Cmd new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_NVIC_LP(LowPowerMode));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        SCB->SCR |= LowPowerMode;
+    }
+    else
+    {
+        SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+    }
+}
+
+/**
+ * @brief  Configures the SysTick clock source.
+ * @param SysTick_CLKSource specifies the SysTick clock source.
+ *   This parameter can be one of the following values:
+ *     @arg SysTick_CLKSource_HCLK_Div8 AHB clock divided by 8 selected as SysTick clock source.
+ *     @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source.
+ */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+    /* Check the parameters */
+    assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+    if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+    {
+        SysTick->CTRL |= SysTick_CLKSource_HCLK;
+    }
+    else
+    {
+        SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+    }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_adc.c

@@ -0,0 +1,1411 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_adc.c
+ * @author Nations
+ * @version V1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_adc.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+/** @addtogroup ADC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Defines
+ * @{
+ */
+
+/* ADC DISC_NUM mask */
+#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISC_EN mask */
+#define CTRL1_DISC_EN_SET   ((uint32_t)0x00000800)
+#define CTRL1_DISC_EN_RESET ((uint32_t)0xFFFFF7FF)
+
+/* ADC INJ_AUTO mask */
+#define CR1_JAUTO_Set   ((uint32_t)0x00000400)
+#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
+
+/* ADC INJ_DISC_EN mask */
+#define CTRL1_INJ_DISC_EN_SET   ((uint32_t)0x00001000)
+#define CTRL1_INJ_DISC_EN_RESET ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDG_CH mask */
+#define CTRL1_AWDG_CH_RESET ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CTRL1_AWDG_MODE_RESET ((uint32_t)0xFF3FFDFF)
+
+/* CTRL1 register Mask */
+#define CTRL1_CLR_MASK ((uint32_t)0xFFF0FEFF)
+
+/* ADC AD_ON mask */
+#define CTRL2_AD_ON_SET   ((uint32_t)0x00000001)
+#define CTRL2_AD_ON_RESET ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CTRL2_DMA_SET   ((uint32_t)0x00000100)
+#define CTRL2_DMA_RESET ((uint32_t)0xFFFFFEFF)
+
+/* ADC RST_CALI mask */
+#define CTRL2_RST_CALI_SET ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CTRL2_CAL_SET ((uint32_t)0x00000004)
+
+/* ADC SOFT_START mask */
+#define CTRL2_SOFT_START_SET ((uint32_t)0x00400000)
+
+/* ADC EXT_TRIG mask */
+#define CTRL2_EXT_TRIG_SET   ((uint32_t)0x00100000)
+#define CTRL2_EXT_TRIG_RESET ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CTRL2_EXT_TRIG_SWSTART_SET   ((uint32_t)0x00500000)
+#define CTRL2_EXT_TRIG_SWSTART_RESET ((uint32_t)0xFFAFFFFF)
+
+/* ADC INJ_EXT_SEL mask */
+#define CTRL2_INJ_EXT_SEL_RESET ((uint32_t)0xFFFF8FFF)
+
+/* ADC INJ_EXT_TRIG mask */
+#define CTRL2_INJ_EXT_TRIG_SET   ((uint32_t)0x00008000)
+#define CTRL2_INJ_EXT_TRIG_RESET ((uint32_t)0xFFFF7FFF)
+
+/* ADC INJ_SWSTART mask */
+#define CTRL2_INJ_SWSTART_SET ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CTRL2_INJ_EXT_TRIG_JSWSTART_SET   ((uint32_t)0x00208000)
+#define CTRL2_INJ_EXT_TRIG_JSWSTART_RESET ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CTRL2_TSVREFE_SET   ((uint32_t)0x00800000)
+#define CTRL2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF)
+
+/* CTRL2 register Mask */
+#define CTRL2_CLR_MASK ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define SQR4_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR3_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR2_SEQ_SET ((uint32_t)0x0000001F)
+#define SQR1_SEQ_SET ((uint32_t)0x0000001F)
+
+/* RSEQ1 register Mask */
+#define RSEQ1_CLR_MASK ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSEQ_JSQ_SET ((uint32_t)0x0000001F)
+
+/* ADC INJ_LEN mask */
+#define JSEQ_INJ_LEN_SET   ((uint32_t)0x00300000)
+#define JSEQ_INJ_LEN_RESET ((uint32_t)0xFFCFFFFF)
+
+/* ADC SAMPTx mask */
+#define SAMPT1_SMP_SET ((uint32_t)0x00000007)
+#define SAMPT2_SMP_SET ((uint32_t)0x00000007)
+
+/* ADC JDATx registers offset */
+#define JDAT_OFFSET ((uint8_t)0x28)
+
+/* ADC1 DAT register base address */
+#define DAT_ADDR ((uint32_t)0x4001244C)
+
+/* ADC STS register mask */
+#define ADC_STS_RESERVE_MASK    ((uint32_t)0x0000007F)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the ADCx peripheral registers to their default reset values.
+ * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral.
+ */
+void ADC_DeInit(ADC_Module* ADCx)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+
+    if (ADCx == ADC)
+    {
+        /* Enable ADC1 reset state */
+        RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, ENABLE);
+        /* Release ADC1 from reset state */
+        RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_ADC, DISABLE);
+    }
+}
+
+/**
+ * @brief  Initializes the ADCx peripheral according to the specified parameters
+ *         in the ADC_InitStruct.
+ * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral.
+ * @param ADC_InitStruct pointer to an ADC_InitType structure that contains
+ *         the configuration information for the specified ADC peripheral.
+ */
+void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct)
+{
+    uint32_t tmpreg1 = 0;
+    uint8_t tmpreg2  = 0;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->MultiChEn));
+    assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ContinueConvEn));
+    assert_param(IsAdcExtTrig(ADC_InitStruct->ExtTrigSelect));
+    assert_param(IsAdcDatAlign(ADC_InitStruct->DatAlign));
+    assert_param(IsAdcSeqLenValid(ADC_InitStruct->ChsNumber));
+
+    /*---------------------------- ADCx CTRL1 Configuration -----------------*/
+    /* Get the ADCx CTRL1 value */
+    tmpreg1 = ADCx->CTRL1;
+    /* Clear DUALMOD and SCAN bits */
+    tmpreg1 &= CTRL1_CLR_MASK;
+    /* Configure ADCx: Dual mode and scan conversion mode */
+    /* Set DUALMOD bits according to WorkMode value */
+    /* Set SCAN bit according to MultiChEn value */
+    tmpreg1 |= (uint32_t)( ((uint32_t)ADC_InitStruct->MultiChEn << 8));
+    /* Write to ADCx CTRL1 */
+    ADCx->CTRL1 = tmpreg1;
+
+    /*---------------------------- ADCx CTRL2 Configuration -----------------*/
+    /* Get the ADCx CTRL2 value */
+    tmpreg1 = ADCx->CTRL2;
+    /* Clear CONT, ALIGN and EXTSEL bits */
+    tmpreg1 &= CTRL2_CLR_MASK;
+    /* Configure ADCx: external trigger event and continuous conversion mode */
+    /* Set ALIGN bit according to DatAlign value */
+    /* Set EXTSEL bits according to ExtTrigSelect value */
+    /* Set CONT bit according to ContinueConvEn value */
+    tmpreg1 |= (uint32_t)(ADC_InitStruct->DatAlign | ADC_InitStruct->ExtTrigSelect
+                          | ((uint32_t)ADC_InitStruct->ContinueConvEn << 1));
+    /* Write to ADCx CTRL2 */
+    ADCx->CTRL2 = tmpreg1;
+
+    /*---------------------------- ADCx RSEQ1 Configuration -----------------*/
+    /* Get the ADCx RSEQ1 value */
+    tmpreg1 = ADCx->RSEQ1;
+    /* Clear L bits */
+    tmpreg1 &= RSEQ1_CLR_MASK;
+    /* Configure ADCx: regular channel sequence length */
+    /* Set L bits according to ChsNumber value */
+    tmpreg2 |= (uint8_t)(ADC_InitStruct->ChsNumber - (uint8_t)1);
+    tmpreg1 |= (uint32_t)tmpreg2 << 20;
+    /* Write to ADCx RSEQ1 */
+    ADCx->RSEQ1 = tmpreg1;
+}
+
+/**
+ * @brief  Fills each ADC_InitStruct member with its default value.
+ * @param ADC_InitStruct pointer to an ADC_InitType structure which will be initialized.
+ */
+void ADC_InitStruct(ADC_InitType* ADC_InitStruct)
+{
+    /* Reset ADC init structure parameters values */
+    /* initialize the MultiChEn member */
+    ADC_InitStruct->MultiChEn = DISABLE;
+    /* Initialize the ContinueConvEn member */
+    ADC_InitStruct->ContinueConvEn = DISABLE;
+    /* Initialize the ExtTrigSelect member */
+    ADC_InitStruct->ExtTrigSelect = ADC_EXT_TRIGCONV_T1_CC1;
+    /* Initialize the DatAlign member */
+    ADC_InitStruct->DatAlign = ADC_DAT_ALIGN_R;
+    /* Initialize the ChsNumber member */
+    ADC_InitStruct->ChsNumber = 1;
+}
+
+/**
+ * @brief  Enables or disables the specified ADC peripheral.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the ADCx peripheral.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Set the AD_ON bit to wake up the ADC from power down mode */
+        ADCx->CTRL2 |= CTRL2_AD_ON_SET;
+    }
+    else
+    {
+        /* Disable the selected ADC peripheral */
+        ADCx->CTRL2 &= CTRL2_AD_ON_RESET;
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified ADC DMA request.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC DMA transfer.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsAdcDmaModule(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected ADC DMA request */
+        ADCx->CTRL2 |= CTRL2_DMA_SET;
+    }
+    else
+    {
+        /* Disable the selected ADC DMA request */
+        ADCx->CTRL2 &= CTRL2_DMA_RESET;
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified ADC interrupts.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt sources to be enabled or disabled.
+ *   This parameter can be any combination of the following values:
+ *     @arg ADC_INT_ENDC End of conversion interrupt mask
+ *     @arg ADC_INT_AWD Analog watchdog interrupt mask
+ *     @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ * @param Cmd new state of the specified ADC interrupts.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd)
+{
+    uint8_t itmask = 0;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    assert_param(IsAdcInt(ADC_IT));
+    /* Get the ADC IT index */
+    itmask = (uint8_t)ADC_IT;
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected ADC interrupts */
+        ADCx->CTRL1 |= itmask;
+    }
+    else
+    {
+        /* Disable the selected ADC interrupts */
+        ADCx->CTRL1 &= (~(uint32_t)itmask);
+    }
+}
+
+
+/**
+ * @brief  Starts the selected ADC calibration process.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ */
+void ADC_StartCalibration(ADC_Module* ADCx)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    /* Enable the selected ADC calibration process */
+    if (ADCx->CALFACT==0)
+        ADCx->CTRL2 |= CTRL2_CAL_SET;
+}
+
+/**
+ * @brief  Gets the selected ADC calibration status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC calibration (SET or RESET).
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    /* Check the status of CAL bit */
+    if ((ADCx->CTRL2 & CTRL2_CAL_SET) != (uint32_t)RESET)
+    {
+        /* CAL bit is set: calibration on going */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* CAL bit is reset: end of calibration */
+        bitstatus = RESET;
+    }
+    if (ADCx->CALFACT!=0)
+        bitstatus = RESET;
+    /* Return the CAL bit status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Enables or disables the selected ADC software start conversion .
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC software start conversion.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected ADC conversion on external event and start the selected
+           ADC conversion */
+        ADCx->CTRL2 |= CTRL2_EXT_TRIG_SWSTART_SET;
+    }
+    else
+    {
+        /* Disable the selected ADC conversion on external event and stop the selected
+           ADC conversion */
+        ADCx->CTRL2 &= CTRL2_EXT_TRIG_SWSTART_RESET;
+    }
+}
+
+/**
+ * @brief  Gets the selected ADC Software start conversion Status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC software start conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    /* Check the status of SOFT_START bit */
+    if ((ADCx->CTRL2 & CTRL2_SOFT_START_SET) != (uint32_t)RESET)
+    {
+        /* SOFT_START bit is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* SOFT_START bit is reset */
+        bitstatus = RESET;
+    }
+    /* Return the SOFT_START bit status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Configures the discontinuous mode for the selected ADC regular
+ *         group channel.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Number specifies the discontinuous mode regular channel
+ *         count value. This number must be between 1 and 8.
+ */
+void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number)
+{
+    uint32_t tmpreg1 = 0;
+    uint32_t tmpreg2 = 0;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcSeqDiscNumberValid(Number));
+    /* Get the old register value */
+    tmpreg1 = ADCx->CTRL1;
+    /* Clear the old discontinuous mode channel count */
+    tmpreg1 &= CR1_DISCNUM_Reset;
+    /* Set the discontinuous mode channel count */
+    tmpreg2 = Number - 1;
+    tmpreg1 |= tmpreg2 << 13;
+    /* Store the new register value */
+    ADCx->CTRL1 = tmpreg1;
+}
+
+/**
+ * @brief  Enables or disables the discontinuous mode on regular group
+ *         channel for the specified ADC
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC discontinuous mode
+ *         on regular group channel.
+ *         This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected ADC regular discontinuous mode */
+        ADCx->CTRL1 |= CTRL1_DISC_EN_SET;
+    }
+    else
+    {
+        /* Disable the selected ADC regular discontinuous mode */
+        ADCx->CTRL1 &= CTRL1_DISC_EN_RESET;
+    }
+}
+
+/**
+ * @brief  Configures for the selected ADC regular channel its corresponding
+ *         rank in the sequencer and its sample time.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_CH_0 ADC Channel0 selected
+ *     @arg ADC_CH_1 ADC Channel1 selected
+ *     @arg ADC_CH_2 ADC Channel2 selected
+ *     @arg ADC_CH_3 ADC Channel3 selected
+ *     @arg ADC_CH_4 ADC Channel4 selected
+ *     @arg ADC_CH_5 ADC Channel5 selected
+ *     @arg ADC_CH_6 ADC Channel6 selected
+ *     @arg ADC_CH_7 ADC Channel7 selected
+ *     @arg ADC_CH_8 ADC Channel8 selected
+ *     @arg ADC_CH_9 ADC Channel9 selected
+ *     @arg ADC_CH_10 ADC Channel10 selected
+ *     @arg ADC_CH_11 ADC Channel11 selected
+ *     @arg ADC_CH_12 ADC Channel12 selected
+ *     @arg ADC_CH_13 ADC Channel13 selected
+ *     @arg ADC_CH_14 ADC Channel14 selected
+ *     @arg ADC_CH_15 ADC Channel15 selected
+ *     @arg ADC_CH_16 ADC Channel16 selected
+ *     @arg ADC_CH_17 ADC Channel17 selected
+ *     @arg ADC_CH_18 ADC Channel18 selected
+ * @param Rank The rank in the regular group sequencer. This parameter must be between 1 to 16.
+ * @param ADC_SampleTime The sample time value to be set for the selected channel.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles
+ *     @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles
+ *     @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles
+ *     @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles
+ *     @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles
+ *     @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles
+ *     @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles
+ *     @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles
+ */
+void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+    uint32_t tmpreg1 = 0, tmpreg2 = 0;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcChannel(ADC_Channel));
+    assert_param(IsAdcReqRankValid(Rank));
+    assert_param(IsAdcSampleTime(ADC_SampleTime));
+
+    if (ADC_Channel == ADC_CH_18)
+    {
+        tmpreg1 = ADCx->SAMPT3;
+        tmpreg1 &= (~0x00000007);
+        tmpreg1 |= ADC_SampleTime;
+        ADCx->SAMPT3 = tmpreg1;
+    }
+    if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */
+    {
+        /* Get the old register value */
+        tmpreg1 = ADCx->SAMPT1;
+        /* Calculate the mask to clear */
+        tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10));
+        /* Clear the old channel sample time */
+        tmpreg1 &= ~tmpreg2;
+        /* Calculate the mask to set */
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+        /* Set the new channel sample time */
+        tmpreg1 |= tmpreg2;
+        /* Store the new register value */
+        ADCx->SAMPT1 = tmpreg1;
+    }
+    else /* ADC_Channel include in ADC_Channel_[0..9] */
+    {
+        /* Get the old register value */
+        tmpreg1 = ADCx->SAMPT2;
+        /* Calculate the mask to clear */
+        tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel);
+        /* Clear the old channel sample time */
+        tmpreg1 &= ~tmpreg2;
+        /* Calculate the mask to set */
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+        /* Set the new channel sample time */
+        tmpreg1 |= tmpreg2;
+        /* Store the new register value */
+        ADCx->SAMPT2 = tmpreg1;
+    }
+    /* For Rank 1 to 6 */
+    if (Rank < 7)
+    {
+        /* Get the old register value */
+        tmpreg1 = ADCx->RSEQ3;
+        /* Calculate the mask to clear */
+        tmpreg2 = SQR3_SEQ_SET << (5 * (Rank - 1));
+        /* Clear the old SQx bits for the selected rank */
+        tmpreg1 &= ~tmpreg2;
+        /* Calculate the mask to set */
+        tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+        /* Set the SQx bits for the selected rank */
+        tmpreg1 |= tmpreg2;
+        /* Store the new register value */
+        ADCx->RSEQ3 = tmpreg1;
+    }
+    /* For Rank 7 to 12 */
+    else if (Rank < 13)
+    {
+        /* Get the old register value */
+        tmpreg1 = ADCx->RSEQ2;
+        /* Calculate the mask to clear */
+        tmpreg2 = SQR2_SEQ_SET << (5 * (Rank - 7));
+        /* Clear the old SQx bits for the selected rank */
+        tmpreg1 &= ~tmpreg2;
+        /* Calculate the mask to set */
+        tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+        /* Set the SQx bits for the selected rank */
+        tmpreg1 |= tmpreg2;
+        /* Store the new register value */
+        ADCx->RSEQ2 = tmpreg1;
+    }
+    /* For Rank 13 to 16 */
+    else
+    {
+        /* Get the old register value */
+        tmpreg1 = ADCx->RSEQ1;
+        /* Calculate the mask to clear */
+        tmpreg2 = SQR1_SEQ_SET << (5 * (Rank - 13));
+        /* Clear the old SQx bits for the selected rank */
+        tmpreg1 &= ~tmpreg2;
+        /* Calculate the mask to set */
+        tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+        /* Set the SQx bits for the selected rank */
+        tmpreg1 |= tmpreg2;
+        /* Store the new register value */
+        ADCx->RSEQ1 = tmpreg1;
+    }
+}
+
+/**
+ * @brief  Enables or disables the ADCx conversion through external trigger.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC external trigger start of conversion.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected ADC conversion on external event */
+        ADCx->CTRL2 |= CTRL2_EXT_TRIG_SET;
+    }
+    else
+    {
+        /* Disable the selected ADC conversion on external event */
+        ADCx->CTRL2 &= CTRL2_EXT_TRIG_RESET;
+    }
+}
+
+/**
+ * @brief  Returns the last ADCx conversion result data for regular channel.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The Data conversion value.
+ */
+uint16_t ADC_GetDat(ADC_Module* ADCx)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    /* Return the selected ADC conversion value */
+    return (uint16_t)ADCx->DAT;
+}
+
+/**
+ * @brief  Enables or disables the selected ADC automatic injected group
+ *         conversion after regular one.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC auto injected conversion
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected ADC automatic injected group conversion */
+        ADCx->CTRL1 |= CR1_JAUTO_Set;
+    }
+    else
+    {
+        /* Disable the selected ADC automatic injected group conversion */
+        ADCx->CTRL1 &= CR1_JAUTO_Reset;
+    }
+}
+
+/**
+ * @brief  Enables or disables the discontinuous mode for injected group
+ *         channel for the specified ADC
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC discontinuous mode
+ *         on injected group channel.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected ADC injected discontinuous mode */
+        ADCx->CTRL1 |= CTRL1_INJ_DISC_EN_SET;
+    }
+    else
+    {
+        /* Disable the selected ADC injected discontinuous mode */
+        ADCx->CTRL1 &= CTRL1_INJ_DISC_EN_RESET;
+    }
+}
+
+/**
+ * @brief  Configures the ADCx external trigger for injected channels conversion.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_ExternalTrigInjecConv specifies the ADC trigger to start injected conversion.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_EXT_TRIG_INJ_CONV_T1_TRGO Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+ *     @arg ADC_EXT_TRIG_INJ_CONV_T1_CC4 Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+ *     @arg ADC_EXT_TRIG_INJ_CONV_T2_TRGO Timer2 TRGO event selected (for ADC1 and ADC2)
+ *     @arg ADC_EXT_TRIG_INJ_CONV_T2_CC1 Timer2 capture compare1 selected (for ADC1 and ADC2)
+ *     @arg ADC_EXT_TRIG_INJ_CONV_T3_CC4 Timer3 capture compare4 selected (for ADC1 and ADC2)
+ *     @arg ADC_EXT_TRIG_INJ_CONV_T4_TRGO Timer4 TRGO event selected (for ADC1 and ADC2)
+ *     @arg ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 External interrupt line 15 or Timer8
+ *                                                       capture compare4 event selected (for ADC1 and ADC2)
+ *     @arg ADC_EXT_TRIG_INJ_CONV_T4_CC3 Timer4 capture compare3 selected (for ADC3 only)
+ *     @arg ADC_EXT_TRIG_INJ_CONV_T8_CC2 Timer8 capture compare2 selected (for ADC3 only)
+ *     @arg ADC_EXT_TRIG_INJ_CONV_T8_CC4 Timer8 capture compare4 selected (for ADC3 only)
+ *     @arg ADC_EXT_TRIG_INJ_CONV_T5_TRGO Timer5 TRGO event selected (for ADC3 only)
+ *     @arg ADC_EXT_TRIG_INJ_CONV_T5_CC4 Timer5 capture compare4 selected (for ADC3 only)
+ *     @arg ADC_EXT_TRIG_INJ_CONV_NONE Injected conversion started by software and not
+ *                                          by external trigger (for ADC1, ADC2 and ADC3)
+ */
+void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcExtInjTrig(ADC_ExternalTrigInjecConv));
+    /* Get the old register value */
+    tmpregister = ADCx->CTRL2;
+    /* Clear the old external event selection for injected group */
+    tmpregister &= CTRL2_INJ_EXT_SEL_RESET;
+    /* Set the external event selection for injected group */
+    tmpregister |= ADC_ExternalTrigInjecConv;
+    /* Store the new register value */
+    ADCx->CTRL2 = tmpregister;
+}
+
+/**
+ * @brief  Enables or disables the ADCx injected channels conversion through
+ *         external trigger
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC external trigger start of
+ *         injected conversion.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected ADC external event selection for injected group */
+        ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_SET;
+    }
+    else
+    {
+        /* Disable the selected ADC external event selection for injected group */
+        ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_RESET;
+    }
+}
+
+/**
+ * @brief  Enables or disables the selected ADC start of the injected
+ *         channels conversion.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Cmd new state of the selected ADC software start injected conversion.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected ADC conversion for injected group on external event and start the selected
+           ADC injected conversion */
+        ADCx->CTRL2 |= CTRL2_INJ_EXT_TRIG_JSWSTART_SET;
+    }
+    else
+    {
+        /* Disable the selected ADC conversion on external event for injected group and stop the selected
+           ADC injected conversion */
+        ADCx->CTRL2 &= CTRL2_INJ_EXT_TRIG_JSWSTART_RESET;
+    }
+}
+
+/**
+ * @brief  Gets the selected ADC Software start injected conversion Status.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @return The new state of ADC software start injected conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    /* Check the status of INJ_SWSTART bit */
+    if ((ADCx->CTRL2 & CTRL2_INJ_SWSTART_SET) != (uint32_t)RESET)
+    {
+        /* INJ_SWSTART bit is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* INJ_SWSTART bit is reset */
+        bitstatus = RESET;
+    }
+    /* Return the INJ_SWSTART bit status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Configures for the selected ADC injected channel its corresponding
+ *         rank in the sequencer and its sample time.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_CH_0 ADC Channel0 selected
+ *     @arg ADC_CH_1 ADC Channel1 selected
+ *     @arg ADC_CH_2 ADC Channel2 selected
+ *     @arg ADC_CH_3 ADC Channel3 selected
+ *     @arg ADC_CH_4 ADC Channel4 selected
+ *     @arg ADC_CH_5 ADC Channel5 selected
+ *     @arg ADC_CH_6 ADC Channel6 selected
+ *     @arg ADC_CH_7 ADC Channel7 selected
+ *     @arg ADC_CH_8 ADC Channel8 selected
+ *     @arg ADC_CH_9 ADC Channel9 selected
+ *     @arg ADC_CH_10 ADC Channel10 selected
+ *     @arg ADC_CH_11 ADC Channel11 selected
+ *     @arg ADC_CH_12 ADC Channel12 selected
+ *     @arg ADC_CH_13 ADC Channel13 selected
+ *     @arg ADC_CH_14 ADC Channel14 selected
+ *     @arg ADC_CH_15 ADC Channel15 selected
+ *     @arg ADC_CH_16 ADC Channel16 selected
+ *     @arg ADC_CH_17 ADC Channel17 selected
+ *     @arg ADC_CH_18 ADC Channel18 selected
+ * @param Rank The rank in the injected group sequencer. This parameter must be between 1 and 4.
+ * @param ADC_SampleTime The sample time value to be set for the selected channel.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_SAMP_TIME_1CYCLES5 Sample time equal to 1.5 cycles
+ *     @arg ADC_SAMP_TIME_7CYCLES5 Sample time equal to 7.5 cycles
+ *     @arg ADC_SAMP_TIME_13CYCLES5 Sample time equal to 13.5 cycles
+ *     @arg ADC_SAMP_TIME_28CYCLES5 Sample time equal to 28.5 cycles
+ *     @arg ADC_SAMP_TIME_41CYCLES5 Sample time equal to 41.5 cycles
+ *     @arg ADC_SAMP_TIME_55CYCLES5 Sample time equal to 55.5 cycles
+ *     @arg ADC_SAMP_TIME_71CYCLES5 Sample time equal to 71.5 cycles
+ *     @arg ADC_SAMP_TIME_239CYCLES5 Sample time equal to 239.5 cycles
+ */
+void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+    uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcChannel(ADC_Channel));
+    assert_param(IsAdcInjRankValid(Rank));
+    assert_param(IsAdcSampleTime(ADC_SampleTime));
+
+    if (ADC_Channel == ADC_CH_18)
+    {
+        tmpreg1 = ADCx->SAMPT3;
+        tmpreg1 &= (~0x00000007);
+        tmpreg1 |= ADC_SampleTime;
+        ADCx->SAMPT3 = tmpreg1;
+    }
+    else if (ADC_Channel > ADC_CH_9) /* if ADC_CH_10 ... ADC_CH_17 is selected */
+    {
+        /* Get the old register value */
+        tmpreg1 = ADCx->SAMPT1;
+        /* Calculate the mask to clear */
+        tmpreg2 = SAMPT1_SMP_SET << (3 * (ADC_Channel - 10));
+        /* Clear the old channel sample time */
+        tmpreg1 &= ~tmpreg2;
+        /* Calculate the mask to set */
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+        /* Set the new channel sample time */
+        tmpreg1 |= tmpreg2;
+        /* Store the new register value */
+        ADCx->SAMPT1 = tmpreg1;
+    }
+    else /* ADC_Channel include in ADC_Channel_[0..9] */
+    {
+        /* Get the old register value */
+        tmpreg1 = ADCx->SAMPT2;
+        /* Calculate the mask to clear */
+        tmpreg2 = SAMPT2_SMP_SET << (3 * ADC_Channel);
+        /* Clear the old channel sample time */
+        tmpreg1 &= ~tmpreg2;
+        /* Calculate the mask to set */
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+        /* Set the new channel sample time */
+        tmpreg1 |= tmpreg2;
+        /* Store the new register value */
+        ADCx->SAMPT2 = tmpreg1;
+    }
+    /* Rank configuration */
+    /* Get the old register value */
+    tmpreg1 = ADCx->JSEQ;
+    /* Get INJ_LEN value: Number = INJ_LEN+1 */
+    tmpreg3 = (tmpreg1 & JSEQ_INJ_LEN_SET) >> 20;
+    /* Calculate the mask to clear: ((Rank-1)+(4-INJ_LEN-1)) */
+    tmpreg2 = JSEQ_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+    /* Clear the old JSQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set: ((Rank-1)+(4-INJ_LEN-1)) */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+    /* Set the JSQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->JSEQ = tmpreg1;
+}
+
+/**
+ * @brief  Configures the sequencer length for injected channels
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param Length The sequencer length.
+ *   This parameter must be a number between 1 to 4.
+ */
+void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length)
+{
+    uint32_t tmpreg1 = 0;
+    uint32_t tmpreg2 = 0;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcInjLenValid(Length));
+
+    /* Get the old register value */
+    tmpreg1 = ADCx->JSEQ;
+    /* Clear the old injected sequnence lenght INJ_LEN bits */
+    tmpreg1 &= JSEQ_INJ_LEN_RESET;
+    /* Set the injected sequnence lenght INJ_LEN bits */
+    tmpreg2 = Length - 1;
+    tmpreg1 |= tmpreg2 << 20;
+    /* Store the new register value */
+    ADCx->JSEQ = tmpreg1;
+}
+
+/**
+ * @brief  Set the injected channels conversion value offset
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InjectedChannel the ADC injected channel to set its offset.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_INJ_CH_1 Injected Channel1 selected
+ *     @arg ADC_INJ_CH_2 Injected Channel2 selected
+ *     @arg ADC_INJ_CH_3 Injected Channel3 selected
+ *     @arg ADC_INJ_CH_4 Injected Channel4 selected
+ * @param Offset the offset value for the selected ADC injected channel
+ *   This parameter must be a 12bit value.
+ */
+void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+    __IO uint32_t tmp = 0;
+
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcInjCh(ADC_InjectedChannel));
+    assert_param(IsAdcOffsetValid(Offset));
+
+    tmp = (uint32_t)ADCx;
+    tmp += ADC_InjectedChannel;
+
+    /* Set the selected injected channel data offset */
+    *(__IO uint32_t*)tmp = (uint32_t)Offset;
+}
+
+/**
+ * @brief  Returns the ADC injected channel conversion result
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_InjectedChannel the converted ADC injected channel.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_INJ_CH_1 Injected Channel1 selected
+ *     @arg ADC_INJ_CH_2 Injected Channel2 selected
+ *     @arg ADC_INJ_CH_3 Injected Channel3 selected
+ *     @arg ADC_INJ_CH_4 Injected Channel4 selected
+ * @return The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel)
+{
+    __IO uint32_t tmp = 0;
+
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcInjCh(ADC_InjectedChannel));
+
+    tmp = (uint32_t)ADCx;
+    tmp += ADC_InjectedChannel + JDAT_OFFSET;
+
+    /* Returns the selected injected channel conversion data value */
+    return (uint16_t)(*(__IO uint32_t*)tmp);
+}
+
+/**
+ * @brief  Enables or disables the analog watchdog on single/all regular
+ *         or injected channels
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_AnalogWatchdog the ADC analog watchdog configuration.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_ANALOG_WTDG_SINGLEREG_ENABLE Analog watchdog on a single regular channel
+ *     @arg ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE Analog watchdog on a single injected channel
+ *     @arg ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE Analog watchdog on a single regular or injected channel
+ *     @arg ADC_ANALOG_WTDG_ALLREG_ENABLE Analog watchdog on  all regular channel
+ *     @arg ADC_ANALOG_WTDG_ALLINJEC_ENABLE Analog watchdog on  all injected channel
+ *     @arg ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE Analog watchdog on all regular and injected channels
+ *     @arg ADC_ANALOG_WTDG_NONE No channel guarded by the analog watchdog
+ */
+void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcAnalogWatchdog(ADC_AnalogWatchdog));
+    /* Get the old register value */
+    tmpregister = ADCx->CTRL1;
+    /* Clear AWDEN, AWDENJ and AWDSGL bits */
+    tmpregister &= CTRL1_AWDG_MODE_RESET;
+    /* Set the analog watchdog enable mode */
+    tmpregister |= ADC_AnalogWatchdog;
+    /* Store the new register value */
+    ADCx->CTRL1 = tmpregister;
+}
+
+/**
+ * @brief  Configures the high and low thresholds of the analog watchdog.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param HighThreshold the ADC analog watchdog High threshold value.
+ *   This parameter must be a 12bit value.
+ * @param LowThreshold the ADC analog watchdog Low threshold value.
+ *   This parameter must be a 12bit value.
+ */
+void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcValid(HighThreshold));
+    assert_param(IsAdcValid(LowThreshold));
+    /* Set the ADCx high threshold */
+    ADCx->WDGHIGH = HighThreshold;
+    /* Set the ADCx low threshold */
+    ADCx->WDGLOW = LowThreshold;
+}
+
+/**
+ * @brief  Configures the analog watchdog guarded single channel
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_Channel the ADC channel to configure for the analog watchdog.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_CH_0 ADC Channel0 selected
+ *     @arg ADC_CH_1 ADC Channel1 selected
+ *     @arg ADC_CH_2 ADC Channel2 selected
+ *     @arg ADC_CH_3 ADC Channel3 selected
+ *     @arg ADC_CH_4 ADC Channel4 selected
+ *     @arg ADC_CH_5 ADC Channel5 selected
+ *     @arg ADC_CH_6 ADC Channel6 selected
+ *     @arg ADC_CH_7 ADC Channel7 selected
+ *     @arg ADC_CH_8 ADC Channel8 selected
+ *     @arg ADC_CH_9 ADC Channel9 selected
+ *     @arg ADC_CH_10 ADC Channel10 selected
+ *     @arg ADC_CH_11 ADC Channel11 selected
+ *     @arg ADC_CH_12 ADC Channel12 selected
+ *     @arg ADC_CH_13 ADC Channel13 selected
+ *     @arg ADC_CH_14 ADC Channel14 selected
+ *     @arg ADC_CH_15 ADC Channel15 selected
+ *     @arg ADC_CH_16 ADC Channel16 selected
+ *     @arg ADC_CH_17 ADC Channel17 selected
+ *     @arg ADC_CH_18 ADC Channel18 selected
+ */
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcChannel(ADC_Channel));
+    /* Get the old register value */
+    tmpregister = ADCx->CTRL1;
+    /* Clear the Analog watchdog channel select bits */
+    tmpregister &= CTRL1_AWDG_CH_RESET;
+    /* Set the Analog watchdog channel */
+    tmpregister |= ADC_Channel;
+    /* Store the new register value */
+    ADCx->CTRL1 = tmpregister;
+}
+
+/**
+ * @brief  Enables or disables the temperature sensor and Vrefint channel.
+ * @param Cmd new state of the temperature sensor.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void ADC_EnableTempSensorVrefint(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the temperature sensor and Vrefint channel*/
+        ADC->CTRL2 |= CTRL2_TSVREFE_SET;
+        _EnVref1p2()
+        _EnVref2p0()
+    }
+    else
+    {
+        /* Disable the temperature sensor and Vrefint channel*/
+        ADC->CTRL2 &= CTRL2_TSVREFE_RESET;
+        _DisVref1p2()
+        _DisVref2p0()
+    }
+}
+
+/**
+ * @brief  Checks whether the specified ADC flag is set or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG specifies the flag to check.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_FLAG_AWDG Analog watchdog flag
+ *     @arg ADC_FLAG_ENDC End of conversion flag
+ *     @arg ADC_FLAG_JENDC End of injected group conversion flag
+ *     @arg ADC_FLAG_JSTR Start of injected group conversion flag
+ *     @arg ADC_FLAG_STR Start of regular group conversion flag
+ * @return The new state of ADC_FLAG (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcGetFlag(ADC_FLAG));
+    /* Check the status of the specified ADC flag */
+    if ((ADCx->STS & ADC_FLAG) != (uint8_t)RESET)
+    {
+        /* ADC_FLAG is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* ADC_FLAG is reset */
+        bitstatus = RESET;
+    }
+    /* Return the ADC_FLAG status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the ADCx's pending flags.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG specifies the flag to clear.
+ *   This parameter can be any combination of the following values:
+ *     @arg ADC_FLAG_AWDG Analog watchdog flag
+ *     @arg ADC_FLAG_ENDC End of conversion flag
+ *     @arg ADC_FLAG_JENDC End of injected group conversion flag
+ *     @arg ADC_FLAG_JSTR Start of injected group conversion flag
+ *     @arg ADC_FLAG_STR Start of regular group conversion flag
+ */
+void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcClrFlag(ADC_FLAG));
+    /* Clear the selected ADC flags */
+    ADCx->STS = (~(uint32_t)ADC_FLAG & ADC_STS_RESERVE_MASK);
+}
+
+/**
+ * @brief  Checks whether the specified ADC interrupt has occurred or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt source to check.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_INT_ENDC End of conversion interrupt mask
+ *     @arg ADC_INT_AWD Analog watchdog interrupt mask
+ *     @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ * @return The new state of ADC_IT (SET or RESET).
+ */
+INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT)
+{
+    INTStatus bitstatus = RESET;
+    uint32_t itmask = 0, enablestatus = 0;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcGetInt(ADC_IT));
+    /* Get the ADC IT index */
+    itmask = ADC_IT >> 8;
+    /* Get the ADC_IT enable bit status */
+    enablestatus = (ADCx->CTRL1 & (uint8_t)ADC_IT);
+    /* Check the status of the specified ADC interrupt */
+    if (((ADCx->STS & itmask) != (uint32_t)RESET) && enablestatus)
+    {
+        /* ADC_IT is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* ADC_IT is reset */
+        bitstatus = RESET;
+    }
+    /* Return the ADC_IT status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the ADCx's interrupt pending bits.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_IT specifies the ADC interrupt pending bit to clear.
+ *   This parameter can be any combination of the following values:
+ *     @arg ADC_INT_ENDC End of conversion interrupt mask
+ *     @arg ADC_INT_AWD Analog watchdog interrupt mask
+ *     @arg ADC_INT_JENDC End of injected conversion interrupt mask
+ */
+void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT)
+{
+    uint8_t itmask = 0;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcInt(ADC_IT));
+    /* Get the ADC IT index */
+    itmask = (uint8_t)(ADC_IT >> 8);
+    /* Clear the selected ADC interrupt pending bits */
+    ADCx->STS = (~(uint32_t)itmask & ADC_STS_RESERVE_MASK);
+}
+
+/**
+ * @brief  Initializes the ADCx peripheral according to the specified parameters
+ *         in the ADC_InitStructEx.
+ * @param ADCx where x can be 1, 2 ,3 or 4 to select the ADC peripheral.
+ * @param ADC_InitStructEx pointer to an ADC_InitTypeEx structure that contains
+ *         the configuration information for the specified ADC peripheral.
+ */
+void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx)
+{
+    uint32_t tmpregister = 0;
+    /*ADC_SAMPT3 samp time sele ,as sam 103 or 303 style*/
+    if (ADC_InitStructEx->Samp303Style)
+        ADCx->SAMPT3 |= ADC_SAMPT3_SAMPSEL_MSK;
+    else
+        ADCx->SAMPT3 &= (~ADC_SAMPT3_SAMPSEL_MSK);
+
+    /*intial ADC_CTRL3 once initiall config*/
+    tmpregister = ADCx->CTRL3;
+    if (ADC_InitStructEx->DeepPowerModEn)
+        tmpregister |= ADC_CTRL3_DPWMOD_MSK;
+    else
+        tmpregister &= (~ADC_CTRL3_DPWMOD_MSK);
+
+    if (ADC_InitStructEx->JendcIntEn)
+        tmpregister |= ADC_CTRL3_JENDCAIEN_MSK;
+    else
+        tmpregister &= (~ADC_CTRL3_JENDCAIEN_MSK);
+
+    if (ADC_InitStructEx->EndcIntEn)
+        tmpregister |= ADC_CTRL3_ENDCAIEN_MSK;
+    else
+        tmpregister &= (~ADC_CTRL3_ENDCAIEN_MSK);
+
+    if (ADC_InitStructEx->CalAtuoLoadEn)
+        tmpregister |= ADC_CTRL3_CALALD_MSK;
+    else
+        tmpregister &= (~ADC_CTRL3_CALALD_MSK);
+
+    if (ADC_InitStructEx->DifModCal)
+        tmpregister |= ADC_CTRL3_CALDIF_MSK;
+    else
+        tmpregister &= (~ADC_CTRL3_CALDIF_MSK);
+
+    tmpregister &= (~ADC_CTRL3_RES_MSK);
+    tmpregister |= ADC_InitStructEx->ResBit;
+
+    tmpregister &= (~ADC_CTRL3_CKMOD_MSK);
+    if (ADC_InitStructEx->ClkMode==ADC_CTRL3_CKMOD_PLL)
+    tmpregister |= ADC_CTRL3_CKMOD_MSK;
+
+    ADCx->CTRL3 = tmpregister;
+}
+/**
+ * @brief  Checks whether the specified ADC flag is set or not.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ADC_FLAG_NEW specifies the flag to check.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_FLAG_RDY ADC ready flag
+ *     @arg ADC_FLAG_PD_RDY ADC powerdown ready flag
+ * @return The new state of ADC_FLAG_NEW (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IsAdcModule(ADCx));
+    assert_param(IsAdcGetFlag(ADC_FLAG_NEW));
+    /* Check the status of the specified ADC flag */
+    if ((ADCx->CTRL3 & ADC_FLAG_NEW) != (uint8_t)RESET)
+    {
+        /* ADC_FLAG_NEW is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* ADC_FLAG_NEW is reset */
+        bitstatus = RESET;
+    }
+    /* Return the ADC_FLAG_NEW status */
+    return bitstatus;
+}
+/**
+ * @brief  Set Adc calibration bypass or enable.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param en enable bypass calibration.
+ *   This parameter can be one of the following values:
+ *     @arg true bypass calibration
+ *     @arg false not bypass calibration
+ */
+void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en)
+{
+    uint32_t tmpregister = 0;
+
+    tmpregister = ADCx->CTRL3;
+    if (en)
+        tmpregister |= ADC_CTRL3_BPCAL_MSK;
+    else
+        tmpregister &= (~ADC_CTRL3_BPCAL_MSK);
+        ADCx->CTRL3 = tmpregister;
+}
+/**
+ * @brief  Set Adc trans bits width.
+ * @param ADCx where x can be 1, 2, 3 or 4 to select the ADC peripheral.
+ * @param ResultBitNum specifies num with adc trans width.
+ *   This parameter can be one of the following values:
+ *     @arg ADC_RST_BIT_12 12 bit trans
+ *     @arg ADC_RST_BIT_10 10 bit trans
+ *     @arg ADC_RST_BIT_8 8 bit trans
+ *     @arg ADC_RESULT_BIT_6 6 bit trans
+ */
+void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum)
+{
+    uint32_t tmpregister = 0;
+
+    tmpregister = ADCx->CTRL3;
+    tmpregister &= 0xFFFFFFFC;
+    tmpregister |= ResultBitNum;
+    ADCx->CTRL3 = tmpregister;
+    return;
+}
+
+
+/**
+ * @brief  Configures the ADCHCLK prescaler.
+ * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler.
+ *   This parameter can be on of the following values:
+ *     @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1
+ *     @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2
+ *     @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4
+ *     @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6
+ *     @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8
+ *     @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10
+ *     @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12
+ *     @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16
+ *     @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32
+ *     @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32
+
+ *     @arg RCC_ADCPLLCLK_DISABLE ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable
+ *     @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1
+ *     @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2
+ *     @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4
+ *     @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6
+ *     @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8
+ *     @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10
+ *     @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12
+ *     @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16
+ *     @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32
+ *     @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64
+ *     @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128
+ *     @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256
+ *     @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256
+ */
+void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler)
+{
+    if (ADC_ClkMode==ADC_CTRL3_CKMOD_AHB){
+        RCC_ConfigAdcPllClk(RCC_ADCPLLCLK_DIV1, DISABLE);
+        RCC_ConfigAdcHclk(RCC_ADCHCLKPrescaler);
+    }else{
+        RCC_ConfigAdcPllClk(RCC_ADCHCLKPrescaler, ENABLE);
+        RCC_ConfigAdcHclk(RCC_ADCHCLK_DIV1);
+    }
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_can.c

@@ -0,0 +1,1372 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_can.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_can.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+/** @addtogroup CAN_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Defines
+ * @{
+ */
+
+/* CAN Master Control Register bits */
+#define MCTRL_DBGF ((uint32_t)0x00010000) /* Debug freeze */
+#define MCTRL_MRST ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMC_FINITM ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INIAK_TIMEOUT ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLPAK_TIMEOUT ((uint32_t)0x0000FFFF)
+
+/* Flags in TSTS register */
+#define CAN_FLAGS_TSTS ((uint32_t)0x08000000)
+/* Flags in RFF1 register */
+#define CAN_FLAGS_RFF1 ((uint32_t)0x04000000)
+/* Flags in RFF0 register */
+#define CAN_FLAGS_RFF0 ((uint32_t)0x02000000)
+/* Flags in MSTS register */
+#define CAN_FLAGS_MSTS ((uint32_t)0x01000000)
+/* Flags in ESTS register */
+#define CAN_FLAGS_ESTS ((uint32_t)0x00F00000)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+
+#define CAN_MODE_MASK ((uint32_t)0x00000003)
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_FunctionPrototypes
+ * @{
+ */
+
+static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the CAN peripheral registers to their default reset values.
+ * @param CANx.
+ */
+void CAN_DeInit(CAN_Module* CANx)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    /* Enable CAN reset state */
+    RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, ENABLE);
+    /* Release CAN from reset state */
+    RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_CAN, DISABLE);
+}
+
+/**
+ * @brief  Initializes the CAN peripheral according to the specified
+ *         parameters in the CAN_InitParam.
+ * @param  CAN to select the CAN peripheral.
+ * @param  CAN_InitParam pointer to a CAN_InitType structure that
+ *                         contains the configuration information for the
+ *                         CAN peripheral.
+ * @return Constant indicates initialization succeed which will be
+ *         CAN_InitSTS_Failed or CAN_InitSTS_Success.
+ */
+uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam)
+{
+    uint8_t InitStatus = CAN_InitSTS_Failed;
+    uint32_t wait_ack  = 0x00000000;
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TTCM));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->ABOM));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->AWKUM));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->NART));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->RFLM));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_InitParam->TXFP));
+    assert_param(IS_CAN_MODE(CAN_InitParam->OperatingMode));
+    assert_param(IS_CAN_RSJW(CAN_InitParam->RSJW));
+    assert_param(IS_CAN_TBS1(CAN_InitParam->TBS1));
+    assert_param(IS_CAN_TBS2(CAN_InitParam->TBS2));
+    assert_param(IS_CAN_BAUDRATEPRESCALER(CAN_InitParam->BaudRatePrescaler));
+
+    /* Exit from sleep mode */
+    CANx->MCTRL &= (~(uint32_t)CAN_MCTRL_SLPRQ);
+
+    /* Request initialisation */
+    CANx->MCTRL |= CAN_MCTRL_INIRQ;
+
+    /* Wait the acknowledge */
+    while (((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT))
+    {
+        wait_ack++;
+    }
+
+    /* Check acknowledge */
+    if ((CANx->MSTS & CAN_MSTS_INIAK) != CAN_MSTS_INIAK)
+    {
+        InitStatus = CAN_InitSTS_Failed;
+    }
+    else
+    {
+        /* Set the time triggered communication mode */
+        if (CAN_InitParam->TTCM == ENABLE)
+        {
+            CANx->MCTRL |= CAN_MCTRL_TTCM;
+        }
+        else
+        {
+            CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TTCM;
+        }
+
+        /* Set the automatic bus-off management */
+        if (CAN_InitParam->ABOM == ENABLE)
+        {
+            CANx->MCTRL |= CAN_MCTRL_ABOM;
+        }
+        else
+        {
+            CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_ABOM;
+        }
+
+        /* Set the automatic wake-up mode */
+        if (CAN_InitParam->AWKUM == ENABLE)
+        {
+            CANx->MCTRL |= CAN_MCTRL_AWKUM;
+        }
+        else
+        {
+            CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_AWKUM;
+        }
+
+        /* Set the no automatic retransmission */
+        if (CAN_InitParam->NART == ENABLE)
+        {
+            CANx->MCTRL |= CAN_MCTRL_NART;
+        }
+        else
+        {
+            CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_NART;
+        }
+
+        /* Set the receive DATFIFO locked mode */
+        if (CAN_InitParam->RFLM == ENABLE)
+        {
+            CANx->MCTRL |= CAN_MCTRL_RFLM;
+        }
+        else
+        {
+            CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_RFLM;
+        }
+
+        /* Set the transmit DATFIFO priority */
+        if (CAN_InitParam->TXFP == ENABLE)
+        {
+            CANx->MCTRL |= CAN_MCTRL_TXFP;
+        }
+        else
+        {
+            CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_TXFP;
+        }
+
+        /* Set the bit timing register */
+        CANx->BTIM = (uint32_t)((uint32_t)CAN_InitParam->OperatingMode << 30) | ((uint32_t)CAN_InitParam->RSJW << 24)
+                    | ((uint32_t)CAN_InitParam->TBS1 << 16) | ((uint32_t)CAN_InitParam->TBS2 << 20)
+                    | ((uint32_t)CAN_InitParam->BaudRatePrescaler - 1);
+
+        /* Request leave initialisation */
+        CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_INIRQ;
+
+        /* Wait the acknowledge */
+        wait_ack = 0;
+
+        while (((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK) && (wait_ack != INIAK_TIMEOUT))
+        {
+            wait_ack++;
+        }
+
+        /* ...and check acknowledged */
+        if ((CANx->MSTS & CAN_MSTS_INIAK) == CAN_MSTS_INIAK)
+        {
+            InitStatus = CAN_InitSTS_Failed;
+        }
+        else
+        {
+            InitStatus = CAN_InitSTS_Success;
+        }
+    }
+
+    /* At this step, return the status of initialization */
+    return InitStatus;
+}
+
+/**
+ * @brief  Initializes the CAN peripheral according to the specified
+ *         parameters in the CAN_InitFilterStruct.
+ * @param  CAN_InitFilterStruct pointer to a CAN_FilterInitType
+ *                               structure that contains the configuration
+ *                               information.
+ */
+void CAN_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct)
+{
+    uint32_t filter_number_bit_pos = 0;
+    /* Check the parameters */
+    assert_param(IS_CAN_FILTER_NUM(CAN_InitFilterStruct->Filter_Num));
+    assert_param(IS_CAN_FILTER_MODE(CAN_InitFilterStruct->Filter_Mode));
+    assert_param(IS_CAN_FILTER_SCALE(CAN_InitFilterStruct->Filter_Scale));
+    assert_param(IS_CAN_FILTER_FIFO(CAN_InitFilterStruct->Filter_FIFOAssignment));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_InitFilterStruct->Filter_Act));
+
+    filter_number_bit_pos = ((uint32_t)1) << CAN_InitFilterStruct->Filter_Num;
+
+    /* Initialisation mode for the filter */
+    CAN->FMC |= FMC_FINITM;
+
+    /* Filter Deactivation */
+    CAN->FA1 &= ~(uint32_t)filter_number_bit_pos;
+
+    /* Filter Scale */
+    if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_16bitScale)
+    {
+        /* 16-bit scale for the filter */
+        CAN->FS1 &= ~(uint32_t)filter_number_bit_pos;
+
+        /* First 16-bit identifier and First 16-bit mask */
+        /* Or First 16-bit identifier and Second 16-bit identifier */
+        CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 =
+            ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId) << 16)
+            | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId);
+
+        /* Second 16-bit identifier and Second 16-bit mask */
+        /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+        CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 =
+            ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16)
+            | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId);
+    }
+
+    if (CAN_InitFilterStruct->Filter_Scale == CAN_Filter_32bitScale)
+    {
+        /* 32-bit scale for the filter */
+        CAN->FS1 |= filter_number_bit_pos;
+        /* 32-bit identifier or First 32-bit identifier */
+        CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR1 =
+            ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_HighId) << 16)
+            | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->Filter_LowId);
+        /* 32-bit mask or Second 32-bit identifier */
+        CAN->sFilterRegister[CAN_InitFilterStruct->Filter_Num].FR2 =
+            ((0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_HighId) << 16)
+            | (0x0000FFFF & (uint32_t)CAN_InitFilterStruct->FilterMask_LowId);
+    }
+
+    /* Filter Mode */
+    if (CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdMaskMode)
+    {
+        /*Id/Mask mode for the filter*/
+        CAN->FM1 &= ~(uint32_t)filter_number_bit_pos;
+    }
+    else /* CAN_InitFilterStruct->Filter_Mode == CAN_Filter_IdListMode */
+    {
+        /*Identifier list mode for the filter*/
+        CAN->FM1 |= (uint32_t)filter_number_bit_pos;
+    }
+
+    /* Filter DATFIFO assignment */
+    if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO0)
+    {
+        /* DATFIFO 0 assignation for the filter */
+        CAN->FFA1 &= ~(uint32_t)filter_number_bit_pos;
+    }
+
+    if (CAN_InitFilterStruct->Filter_FIFOAssignment == CAN_Filter_FIFO1)
+    {
+        /* DATFIFO 1 assignation for the filter */
+        CAN->FFA1 |= (uint32_t)filter_number_bit_pos;
+    }
+
+    /* Filter activation */
+    if (CAN_InitFilterStruct->Filter_Act == ENABLE)
+    {
+        CAN->FA1 |= filter_number_bit_pos;
+    }
+
+    /* Leave the initialisation mode for the filter */
+    CAN->FMC &= ~FMC_FINITM;
+}
+/**
+ * @brief  Fills each CAN_InitParam member with its default value.
+ * @param CAN_InitParam pointer to a CAN_InitType structure which
+ *                         will be initialized.
+ */
+void CAN_InitStruct(CAN_InitType* CAN_InitParam)
+{
+    /* Reset CAN init structure parameters values */
+
+    /* Initialize the time triggered communication mode */
+    CAN_InitParam->TTCM = DISABLE;
+
+    /* Initialize the automatic bus-off management */
+    CAN_InitParam->ABOM = DISABLE;
+
+    /* Initialize the automatic wake-up mode */
+    CAN_InitParam->AWKUM = DISABLE;
+
+    /* Initialize the no automatic retransmission */
+    CAN_InitParam->NART = DISABLE;
+
+    /* Initialize the receive DATFIFO locked mode */
+    CAN_InitParam->RFLM = DISABLE;
+
+    /* Initialize the transmit DATFIFO priority */
+    CAN_InitParam->TXFP = DISABLE;
+
+    /* Initialize the OperatingMode member */
+    CAN_InitParam->OperatingMode = CAN_Normal_Mode;
+
+    /* Initialize the RSJW member */
+    CAN_InitParam->RSJW = CAN_RSJW_1tq;
+
+    /* Initialize the TBS1 member */
+    CAN_InitParam->TBS1 = CAN_TBS1_4tq;
+
+    /* Initialize the TBS2 member */
+    CAN_InitParam->TBS2 = CAN_TBS2_3tq;
+
+    /* Initialize the BaudRatePrescaler member */
+    CAN_InitParam->BaudRatePrescaler = 1;
+}
+
+/**
+ * @brief  Enables or disables the DBG Freeze for CAN.
+ * @param  CAN to select the CAN peripheral.
+ * @param  Cmd new state of the CAN peripheral. This parameter can
+ *                   be: ENABLE or DISABLE.
+ */
+void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable Debug Freeze  */
+        CANx->MCTRL |= MCTRL_DBGF;
+    }
+    else
+    {
+        /* Disable Debug Freeze */
+        CANx->MCTRL &= ~MCTRL_DBGF;
+    }
+}
+
+/**
+ * @brief  Enables or disabes the CAN Time TriggerOperation communication mode.
+ * @param  CAN to select the CAN peripheral.
+ * @param  Cmd Mode new state , can be one of @ref FunctionalState.
+ * @note   when enabled, Time stamp (TIME[15:0]) value is sent in the last
+ *         two data bytes of the 8-byte message: TIME[7:0] in data byte 6
+ *         and TIME[15:8] in data byte 7
+ * @note   DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
+ *         sent over the CAN bus.
+ */
+void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the TTCM mode */
+        CANx->MCTRL |= CAN_MCTRL_TTCM;
+
+        /* Set TGT bits */
+        CANx->sTxMailBox[0].TMDT |= ((uint32_t)CAN_TMDT0_TGT);
+        CANx->sTxMailBox[1].TMDT |= ((uint32_t)CAN_TMDT1_TGT);
+        CANx->sTxMailBox[2].TMDT |= ((uint32_t)CAN_TMDT2_TGT);
+    }
+    else
+    {
+        /* Disable the TTCM mode */
+        CANx->MCTRL &= (uint32_t)(~(uint32_t)CAN_MCTRL_TTCM);
+
+        /* Reset TGT bits */
+        CANx->sTxMailBox[0].TMDT &= ((uint32_t)~CAN_TMDT0_TGT);
+        CANx->sTxMailBox[1].TMDT &= ((uint32_t)~CAN_TMDT1_TGT);
+        CANx->sTxMailBox[2].TMDT &= ((uint32_t)~CAN_TMDT2_TGT);
+    }
+}
+/**
+ * @brief  Initiates the transmission of a message.
+ * @param CAN to select the CAN peripheral.
+ * @param TxMessage pointer to a structure which contains CAN Id, CAN
+ *                    DLC and CAN data.
+ * @return The number of the mailbox that is used for transmission
+ *                    or CAN_TxSTS_NoMailBox if there is no empty mailbox.
+ */
+uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage)
+{
+    uint8_t transmit_mailbox = 0;
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_ID(TxMessage->IDE));
+    assert_param(IS_CAN_RTRQ(TxMessage->RTR));
+    assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+    /* Select one empty transmit mailbox */
+    if ((CANx->TSTS & CAN_TSTS_TMEM0) == CAN_TSTS_TMEM0)
+    {
+        transmit_mailbox = 0;
+    }
+    else if ((CANx->TSTS & CAN_TSTS_TMEM1) == CAN_TSTS_TMEM1)
+    {
+        transmit_mailbox = 1;
+    }
+    else if ((CANx->TSTS & CAN_TSTS_TMEM2) == CAN_TSTS_TMEM2)
+    {
+        transmit_mailbox = 2;
+    }
+    else
+    {
+        transmit_mailbox = CAN_TxSTS_NoMailBox;
+    }
+
+    if (transmit_mailbox != CAN_TxSTS_NoMailBox)
+    {
+        /* Set up the Id */
+        CANx->sTxMailBox[transmit_mailbox].TMI &= TMIDxR_TXRQ;
+        if (TxMessage->IDE == CAN_Standard_Id)
+        {
+            assert_param(IS_CAN_STDID(TxMessage->StdId));
+            CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->StdId << 21) | TxMessage->RTR);
+        }
+        else
+        {
+            assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+            CANx->sTxMailBox[transmit_mailbox].TMI |= ((TxMessage->ExtId << 3) | TxMessage->IDE | TxMessage->RTR);
+        }
+
+        /* Set up the DLC */
+        TxMessage->DLC &= (uint8_t)0x0000000F;
+        CANx->sTxMailBox[transmit_mailbox].TMDT &= (uint32_t)0xFFFFFFF0;
+        CANx->sTxMailBox[transmit_mailbox].TMDT |= TxMessage->DLC;
+
+        /* Set up the data field */
+        CANx->sTxMailBox[transmit_mailbox].TMDL =
+            (((uint32_t)TxMessage->Data[3] << 24) | ((uint32_t)TxMessage->Data[2] << 16)
+             | ((uint32_t)TxMessage->Data[1] << 8) | ((uint32_t)TxMessage->Data[0]));
+        CANx->sTxMailBox[transmit_mailbox].TMDH =
+            (((uint32_t)TxMessage->Data[7] << 24) | ((uint32_t)TxMessage->Data[6] << 16)
+             | ((uint32_t)TxMessage->Data[5] << 8) | ((uint32_t)TxMessage->Data[4]));
+        /* Request transmission */
+        CANx->sTxMailBox[transmit_mailbox].TMI |= TMIDxR_TXRQ;
+    }
+    return transmit_mailbox;
+}
+
+/**
+ * @brief  Checks the transmission of a message.
+ * @param  CANx to select the CAN peripheral.
+ * @param  TransmitMailbox the number of the mailbox that is used for
+ *                          transmission.
+ * @return CAN_TxSTS_Ok if the CAN driver transmits the message, CAN_TxSTS_Failed
+ *         in an other case.
+ */
+uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox)
+{
+    uint32_t state = 0;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+
+    switch (TransmitMailbox)
+    {
+    case (CAN_TXMAILBOX_0):
+        state = CANx->TSTS & (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0);
+        break;
+    case (CAN_TXMAILBOX_1):
+        state = CANx->TSTS & (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1);
+        break;
+    case (CAN_TXMAILBOX_2):
+        state = CANx->TSTS & (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2);
+        break;
+    default:
+        state = CAN_TxSTS_Failed;
+        break;
+    }
+    switch (state)
+    {
+        /* transmit pending  */
+    case (0x0):
+        state = CAN_TxSTS_Pending;
+        break;
+        /* transmit failed  */
+    case (CAN_TSTS_RQCPM0 | CAN_TSTS_TMEM0):
+        state = CAN_TxSTS_Failed;
+        break;
+    case (CAN_TSTS_RQCPM1 | CAN_TSTS_TMEM1):
+        state = CAN_TxSTS_Failed;
+        break;
+    case (CAN_TSTS_RQCPM2 | CAN_TSTS_TMEM2):
+        state = CAN_TxSTS_Failed;
+        break;
+        /* transmit succeeded  */
+    case (CAN_TSTS_RQCPM0 | CAN_TSTS_TXOKM0 | CAN_TSTS_TMEM0):
+        state = CAN_TxSTS_Ok;
+        break;
+    case (CAN_TSTS_RQCPM1 | CAN_TSTS_TXOKM1 | CAN_TSTS_TMEM1):
+        state = CAN_TxSTS_Ok;
+        break;
+    case (CAN_TSTS_RQCPM2 | CAN_TSTS_TXOKM2 | CAN_TSTS_TMEM2):
+        state = CAN_TxSTS_Ok;
+        break;
+    default:
+        state = CAN_TxSTS_Failed;
+        break;
+    }
+    return (uint8_t)state;
+}
+
+/**
+ * @brief  Cancels a transmit request.
+ * @param CAN to select the CAN peripheral.
+ * @param Mailbox Mailbox number.
+ */
+void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+    /* abort transmission */
+    switch (Mailbox)
+    {
+    case (CAN_TXMAILBOX_0):
+        CANx->TSTS = CAN_TSTS_ABRQM0;
+        break;
+    case (CAN_TXMAILBOX_1):
+        CANx->TSTS = CAN_TSTS_ABRQM1;
+        break;
+    case (CAN_TXMAILBOX_2):
+        CANx->TSTS = CAN_TSTS_ABRQM2;
+        break;
+    default:
+        break;
+    }
+}
+
+/**
+ * @brief  Receives a message.
+ * @param  CAN to select the CAN peripheral.
+ * @param  FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @param  RxMessage pointer to a structure receive message which contains
+ *                     CAN Id, CAN DLC, CAN datas and FMI number.
+ */
+void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_FIFO(FIFONum));
+    /* Get the Id */
+    RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONum].RMI;
+    if (RxMessage->IDE == CAN_Standard_Id)
+    {
+        RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONum].RMI >> 21);
+    }
+    else
+    {
+        RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONum].RMI >> 3);
+    }
+
+    RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONum].RMI;
+    /* Get the DLC */
+    RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONum].RMDT;
+    /* Get the FMI */
+    RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDT >> 8);
+    /* Get the data field */
+    RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDL;
+    RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 8);
+    RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 16);
+    RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDL >> 24);
+    RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONum].RMDH;
+    RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 8);
+    RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 16);
+    RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONum].RMDH >> 24);
+    /* Release the DATFIFO */
+    /* Release FIFO0 */
+    if (FIFONum == CAN_FIFO0)
+    {
+        CANx->RFF0 |= CAN_RFF0_RFFOM0;
+    }
+    /* Release FIFO1 */
+    else /* FIFONum == CAN_FIFO1 */
+    {
+        CANx->RFF1 |= CAN_RFF1_RFFOM1;
+    }
+}
+
+/**
+ * @brief  Releases the specified DATFIFO.
+ * @param  CAN to select the CAN peripheral.
+ * @param  FIFONum DATFIFO to release, CAN_FIFO0 or CAN_FIFO1.
+ */
+void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_FIFO(FIFONum));
+    /* Release FIFO0 */
+    if (FIFONum == CAN_FIFO0)
+    {
+        CANx->RFF0 |= CAN_RFF0_RFFOM0;
+    }
+    /* Release FIFO1 */
+    else /* FIFONum == CAN_FIFO1 */
+    {
+        CANx->RFF1 |= CAN_RFF1_RFFOM1;
+    }
+}
+
+/**
+ * @brief  Returns the number of pending messages.
+ * @param  CAN to select the CAN peripheral.
+ * @param  FIFONum Receive DATFIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @return NbMessage : which is the number of pending message.
+ */
+uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum)
+{
+    uint8_t message_pending = 0;
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_FIFO(FIFONum));
+    if (FIFONum == CAN_FIFO0)
+    {
+        message_pending = (uint8_t)(CANx->RFF0 & (uint32_t)0x03);
+    }
+    else if (FIFONum == CAN_FIFO1)
+    {
+        message_pending = (uint8_t)(CANx->RFF1 & (uint32_t)0x03);
+    }
+    else
+    {
+        message_pending = 0;
+    }
+    return message_pending;
+}
+
+/**
+  * @brief  Select the CAN Operation mode.
+  * @param  CAN to select the CAN peripheral.
+  * @param  CAN_OperatingMode CAN Operating Mode. This parameter can be one
+  *                            of @ref CAN_operating_mode enumeration.
+  * @return status of the requested mode which can be
+  *         - CAN_ModeSTS_Failed    CAN failed entering the specific mode
+  *         - CAN_ModeSTS_Success   CAN Succeed entering the specific mode
+
+  */
+uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode)
+{
+    uint8_t status = CAN_ModeSTS_Failed;
+
+    /* Timeout for INAK or also for SLAK bits*/
+    uint32_t timeout = INIAK_TIMEOUT;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+    if (CAN_OperatingMode == CAN_Operating_InitMode)
+    {
+        /* Request initialisation */
+        CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_SLPRQ)) | CAN_MCTRL_INIRQ);
+
+        /* Wait the acknowledge */
+        while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK) && (timeout != 0))
+        {
+            timeout--;
+        }
+        if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_INIAK)
+        {
+            status = CAN_ModeSTS_Failed;
+        }
+        else
+        {
+            status = CAN_ModeSTS_Success;
+        }
+    }
+    else if (CAN_OperatingMode == CAN_Operating_NormalMode)
+    {
+        /* Request leave initialisation and sleep mode  and enter Normal mode */
+        CANx->MCTRL &= (uint32_t)(~(CAN_MCTRL_SLPRQ | CAN_MCTRL_INIRQ));
+
+        /* Wait the acknowledge */
+        while (((CANx->MSTS & CAN_MODE_MASK) != 0) && (timeout != 0))
+        {
+            timeout--;
+        }
+        if ((CANx->MSTS & CAN_MODE_MASK) != 0)
+        {
+            status = CAN_ModeSTS_Failed;
+        }
+        else
+        {
+            status = CAN_ModeSTS_Success;
+        }
+    }
+    else if (CAN_OperatingMode == CAN_Operating_SleepMode)
+    {
+        /* Request Sleep mode */
+        CANx->MCTRL = (uint32_t)((CANx->MCTRL & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ);
+
+        /* Wait the acknowledge */
+        while (((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK) && (timeout != 0))
+        {
+            timeout--;
+        }
+        if ((CANx->MSTS & CAN_MODE_MASK) != CAN_MSTS_SLPAK)
+        {
+            status = CAN_ModeSTS_Failed;
+        }
+        else
+        {
+            status = CAN_ModeSTS_Success;
+        }
+    }
+    else
+    {
+        status = CAN_ModeSTS_Failed;
+    }
+
+    return (uint8_t)status;
+}
+
+/**
+ * @brief  Enters the low power mode.
+ * @param  CAN to select the CAN peripheral.
+ * @return status: CAN_SLEEP_Ok if sleep entered, CAN_SLEEP_Failed in an
+ *                 other case.
+ */
+uint8_t CAN_EnterSleep(CAN_Module* CANx)
+{
+    uint8_t sleepstatus = CAN_SLEEP_Failed;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    /* Request Sleep mode */
+    CANx->MCTRL = (((CANx->MCTRL) & (uint32_t)(~(uint32_t)CAN_MCTRL_INIRQ)) | CAN_MCTRL_SLPRQ);
+
+    /* Sleep mode status */
+    if ((CANx->MSTS & (CAN_MSTS_SLPAK | CAN_MSTS_INIAK)) == CAN_MSTS_SLPAK)
+    {
+        /* Sleep mode not entered */
+        sleepstatus = CAN_SLEEP_Ok;
+    }
+    /* return sleep mode status */
+    return (uint8_t)sleepstatus;
+}
+
+/**
+ * @brief  Wakes the CAN up.
+ * @param  CAN to select the CAN peripheral.
+ * @return status:  CAN_WKU_Ok if sleep mode left, CAN_WKU_Failed in an
+ *                  other case.
+ */
+uint8_t CAN_WakeUp(CAN_Module* CANx)
+{
+    uint32_t wait_slak   = SLPAK_TIMEOUT;
+    uint8_t wakeupstatus = CAN_WKU_Failed;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    /* Wake up request */
+    CANx->MCTRL &= ~(uint32_t)CAN_MCTRL_SLPRQ;
+
+    /* Sleep mode status */
+    while (((CANx->MSTS & CAN_MSTS_SLPAK) == CAN_MSTS_SLPAK) && (wait_slak != 0x00))
+    {
+        wait_slak--;
+    }
+    if ((CANx->MSTS & CAN_MSTS_SLPAK) != CAN_MSTS_SLPAK)
+    {
+        /* wake up done : Sleep mode exited */
+        wakeupstatus = CAN_WKU_Ok;
+    }
+    /* return wakeup status */
+    return (uint8_t)wakeupstatus;
+}
+
+/**
+ * @brief  Returns the CANx's last error code (LEC).
+ * @param  CAN to select the CAN peripheral.
+ * @return CAN_ErrorCode: specifies the Error code :
+ *                        - CAN_ERRORCODE_NoErr            No Error
+ *                        - CAN_ERRORCODE_StuffErr         Stuff Error
+ *                        - CAN_ERRORCODE_FormErr          Form Error
+ *                        - CAN_ERRORCODE_ACKErr           Acknowledgment Error
+ *                        - CAN_ERRORCODE_BitRecessiveErr  Bit Recessive Error
+ *                        - CAN_ERRORCODE_BitDominantErr   Bit Dominant Error
+ *                        - CAN_ERRORCODE_CRCErr           CRC Error
+ *                        - CAN_ERRORCODE_SoftwareSetErr   Software Set Error
+ */
+
+uint8_t CAN_GetLastErrCode(CAN_Module* CANx)
+{
+    uint8_t errorcode = 0;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    /* Get the error code*/
+    errorcode = (((uint8_t)CANx->ESTS) & (uint8_t)CAN_ESTS_LEC);
+
+    /* Return the error code*/
+    return errorcode;
+}
+/**
+ * @brief  Returns the CANx Receive Error Counter (REC).
+ * @note   In case of an error during reception, this counter is incremented
+ *         by 1 or by 8 depending on the error condition as defined by the CAN
+ *         standard. After every successful reception, the counter is
+ *         decremented by 1 or reset to 120 if its value was higher than 128.
+ *         When the counter value exceeds 127, the CAN controller enters the
+ *         error passive state.
+ * @param  CANx to to select the CAN peripheral.
+ * @return CAN Receive Error Counter.
+ */
+uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx)
+{
+    uint8_t counter = 0;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    /* Get the Receive Error Counter*/
+    counter = (uint8_t)((CANx->ESTS & CAN_ESTS_RXEC) >> 24);
+
+    /* Return the Receive Error Counter*/
+    return counter;
+}
+
+/**
+ * @brief  Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+ * @param  CAN to to select the CAN peripheral.
+ * @return LSB of the 9-bit CAN Transmit Error Counter.
+ */
+uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx)
+{
+    uint8_t counter = 0;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+    counter = (uint8_t)((CANx->ESTS & CAN_ESTS_TXEC) >> 16);
+
+    /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+    return counter;
+}
+
+/**
+ * @brief  Enables or disables the specified CANx interrupts.
+ * @param  CAN to select the CAN peripheral.
+ * @param  CAN_INT specifies the CAN interrupt sources to be enabled or disabled.
+ *                 This parameter can be:
+ *                 - CAN_INT_TME,
+ *                 - CAN_INT_FMP0,
+ *                 - CAN_INT_FF0,
+ *                 - CAN_INT_FOV0,
+ *                 - CAN_INT_FMP1,
+ *                 - CAN_INT_FF1,
+ *                 - CAN_INT_FOV1,
+ *                 - CAN_INT_EWG,
+ *                 - CAN_INT_EPV,
+ *                 - CAN_INT_LEC,
+ *                 - CAN_INT_ERR,
+ *                 - CAN_INT_WKU or
+ *                 - CAN_INT_SLK.
+ * @param Cmd new state of the CAN interrupts.
+ *                   This parameter can be: ENABLE or DISABLE.
+ */
+void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_INT(CAN_INT));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected CANx interrupt */
+        CANx->INTE |= CAN_INT;
+    }
+    else
+    {
+        /* Disable the selected CANx interrupt */
+        CANx->INTE &= ~CAN_INT;
+    }
+}
+/**
+ * @brief  Checks whether the specified CAN flag is set or not.
+ * @param  CAN to select the CAN peripheral.
+ * @param  CAN_FLAG specifies the flag to check.
+ *                   This parameter can be one of the following flags:
+ *                  - CAN_FLAG_EWGFL
+ *                  - CAN_FLAG_EPVFL
+ *                  - CAN_FLAG_BOFFL
+ *                  - CAN_FLAG_RQCPM0
+ *                  - CAN_FLAG_RQCPM1
+ *                  - CAN_FLAG_RQCPM2
+ *                  - CAN_FLAG_FFMP1
+ *                  - CAN_FLAG_FFULL1
+ *                  - CAN_FLAG_FFOVR1
+ *                  - CAN_FLAG_FFMP0
+ *                  - CAN_FLAG_FFULL0
+ *                  - CAN_FLAG_FFOVR0
+ *                  - CAN_FLAG_WKU
+ *                  - CAN_FLAG_SLAK
+ *                  - CAN_FLAG_LEC
+ * @return The new state of CAN_FLAG (SET or RESET).
+ */
+FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+
+    if ((CAN_FLAG & CAN_FLAGS_ESTS) != (uint32_t)RESET)
+    {
+        /* Check the status of the specified CAN flag */
+        if ((CANx->ESTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+        {
+            /* CAN_FLAG is set */
+            bitstatus = SET;
+        }
+        else
+        {
+            /* CAN_FLAG is reset */
+            bitstatus = RESET;
+        }
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_MSTS) != (uint32_t)RESET)
+    {
+        /* Check the status of the specified CAN flag */
+        if ((CANx->MSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+        {
+            /* CAN_FLAG is set */
+            bitstatus = SET;
+        }
+        else
+        {
+            /* CAN_FLAG is reset */
+            bitstatus = RESET;
+        }
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET)
+    {
+        /* Check the status of the specified CAN flag */
+        if ((CANx->TSTS & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+        {
+            /* CAN_FLAG is set */
+            bitstatus = SET;
+        }
+        else
+        {
+            /* CAN_FLAG is reset */
+            bitstatus = RESET;
+        }
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET)
+    {
+        /* Check the status of the specified CAN flag */
+        if ((CANx->RFF0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+        {
+            /* CAN_FLAG is set */
+            bitstatus = SET;
+        }
+        else
+        {
+            /* CAN_FLAG is reset */
+            bitstatus = RESET;
+        }
+    }
+    else /* if (CAN_FLAG & CAN_FLAGS_RFF1 != (uint32_t)RESET) */
+    {
+        /* Check the status of the specified CAN flag */
+        if ((uint32_t)(CANx->RFF1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+        {
+            /* CAN_FLAG is set */
+            bitstatus = SET;
+        }
+        else
+        {
+            /* CAN_FLAG is reset */
+            bitstatus = RESET;
+        }
+    }
+    /* Return the CAN_FLAG status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the CAN's pending flags.
+ * @param  CAN to select the CAN peripheral.
+ * @param  CAN_FLAG specifies the flag to clear.
+ *                   This parameter can be one of the following flags:
+ *                    - CAN_FLAG_RQCPM0
+ *                    - CAN_FLAG_RQCPM1
+ *                    - CAN_FLAG_RQCPM2
+ *                    - CAN_FLAG_FFULL1
+ *                    - CAN_FLAG_FFOVR1
+ *                    - CAN_FLAG_FFULL0
+ *                    - CAN_FLAG_FFOVR0
+ *                    - CAN_FLAG_WKU
+ *                    - CAN_FLAG_SLAK
+ *                    - CAN_FLAG_LEC
+ */
+void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG)
+{
+    uint32_t flagtmp = 0;
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+
+    if (CAN_FLAG == CAN_FLAG_LEC) /* ESTS register */
+    {
+        /* Clear the selected CAN flags */
+        CANx->ESTS = (uint32_t)RESET;
+    }
+    else /* MSTS or TSTS or RFF0 or RFF1 */
+    {
+        flagtmp = CAN_FLAG & 0x000FFFFF;
+
+        if ((CAN_FLAG & CAN_FLAGS_RFF0) != (uint32_t)RESET)
+        {
+            /* Receive Flags */
+            CANx->RFF0 = (uint32_t)(flagtmp);
+        }
+        else if ((CAN_FLAG & CAN_FLAGS_RFF1) != (uint32_t)RESET)
+        {
+            /* Receive Flags */
+            CANx->RFF1 = (uint32_t)(flagtmp);
+        }
+        else if ((CAN_FLAG & CAN_FLAGS_TSTS) != (uint32_t)RESET)
+        {
+            /* Transmit Flags */
+            CANx->TSTS = (uint32_t)(flagtmp);
+        }
+        else /* if ((CAN_FLAG & CAN_FLAGS_MSTS)!=(uint32_t)RESET) */
+        {
+            /* Operating mode Flags */
+            CANx->MSTS = (uint32_t)(flagtmp);
+        }
+    }
+}
+
+/**
+ * @brief  Checks whether the specified CANx interrupt has occurred or not.
+ * @param  CAN to select the CAN peripheral.
+ * @param  CAN_INT specifies the CAN interrupt source to check.
+ *                  This parameter can be one of the following flags:
+ *                 -  CAN_INT_TME
+ *                 -  CAN_INT_FMP0
+ *                 -  CAN_INT_FF0
+ *                 -  CAN_INT_FOV0
+ *                 -  CAN_INT_FMP1
+ *                 -  CAN_INT_FF1
+ *                 -  CAN_INT_FOV1
+ *                 -  CAN_INT_WKU
+ *                 -  CAN_INT_SLK
+ *                 -  CAN_INT_EWG
+ *                 -  CAN_INT_EPV
+ *                 -  CAN_INT_BOF
+ *                 -  CAN_INT_LEC
+ *                 -  CAN_INT_ERR
+ * @return The current state of CAN_INT (SET or RESET).
+ */
+INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT)
+{
+    INTStatus itstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_INT(CAN_INT));
+
+    /* check the enable interrupt bit */
+    if ((CANx->INTE & CAN_INT) != RESET)
+    {
+        /* in case the Interrupt is enabled, .... */
+        switch (CAN_INT)
+        {
+        case CAN_INT_TME:
+            /* Check CAN_TSTS_RQCPx bits */
+            itstatus = CheckINTStatus(CANx->TSTS, CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2);
+            break;
+        case CAN_INT_FMP0:
+            /* Check CAN_RFF0_FFMP0 bit */
+            itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFMP0);
+            break;
+        case CAN_INT_FF0:
+            /* Check CAN_RFF0_FFULL0 bit */
+            itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFULL0);
+            break;
+        case CAN_INT_FOV0:
+            /* Check CAN_RFF0_FFOVR0 bit */
+            itstatus = CheckINTStatus(CANx->RFF0, CAN_RFF0_FFOVR0);
+            break;
+        case CAN_INT_FMP1:
+            /* Check CAN_RFF1_FFMP1 bit */
+            itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFMP1);
+            break;
+        case CAN_INT_FF1:
+            /* Check CAN_RFF1_FFULL1 bit */
+            itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFULL1);
+            break;
+        case CAN_INT_FOV1:
+            /* Check CAN_RFF1_FFOVR1 bit */
+            itstatus = CheckINTStatus(CANx->RFF1, CAN_RFF1_FFOVR1);
+            break;
+        case CAN_INT_WKU:
+            /* Check CAN_MSTS_WKUINT bit */
+            itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_WKUINT);
+            break;
+        case CAN_INT_SLK:
+            /* Check CAN_MSTS_SLAKINT bit */
+            itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_SLAKINT);
+            break;
+        case CAN_INT_EWG:
+            /* Check CAN_ESTS_EWGFL bit */
+            itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EWGFL);
+            break;
+        case CAN_INT_EPV:
+            /* Check CAN_ESTS_EPVFL bit */
+            itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_EPVFL);
+            break;
+        case CAN_INT_BOF:
+            /* Check CAN_ESTS_BOFFL bit */
+            itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_BOFFL);
+            break;
+        case CAN_INT_LEC:
+            /* Check CAN_ESTS_LEC bit */
+            itstatus = CheckINTStatus(CANx->ESTS, CAN_ESTS_LEC);
+            break;
+        case CAN_INT_ERR:
+            /* Check CAN_MSTS_ERRINT bit */
+            itstatus = CheckINTStatus(CANx->MSTS, CAN_MSTS_ERRINT);
+            break;
+        default:
+            /* in case of error, return RESET */
+            itstatus = RESET;
+            break;
+        }
+    }
+    else
+    {
+        /* in case the Interrupt is not enabled, return RESET */
+        itstatus = RESET;
+    }
+
+    /* Return the CAN_INT status */
+    return itstatus;
+}
+
+/**
+ * @brief  Clears the CANx's interrupt pending bits.
+ * @param  CAN to select the CAN peripheral.
+ * @param  CAN_INT specifies the interrupt pending bit to clear.
+ *                  -  CAN_INT_TME
+ *                  -  CAN_INT_FF0
+ *                  -  CAN_INT_FOV0
+ *                  -  CAN_INT_FF1
+ *                  -  CAN_INT_FOV1
+ *                  -  CAN_INT_WKU
+ *                  -  CAN_INT_SLK
+ *                  -  CAN_INT_EWG
+ *                  -  CAN_INT_EPV
+ *                  -  CAN_INT_BOF
+ *                  -  CAN_INT_LEC
+ *                  -  CAN_INT_ERR
+ */
+void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_CLEAR_INT(CAN_INT));
+
+    switch (CAN_INT)
+    {
+    case CAN_INT_TME:
+        /* Clear CAN_TSTS_RQCPx (rc_w1)*/
+        CANx->TSTS = CAN_TSTS_RQCPM0 | CAN_TSTS_RQCPM1 | CAN_TSTS_RQCPM2;
+        break;
+    case CAN_INT_FF0:
+        /* Clear CAN_RFF0_FFULL0 (rc_w1)*/
+        CANx->RFF0 = CAN_RFF0_FFULL0;
+        break;
+    case CAN_INT_FOV0:
+        /* Clear CAN_RFF0_FFOVR0 (rc_w1)*/
+        CANx->RFF0 = CAN_RFF0_FFOVR0;
+        break;
+    case CAN_INT_FF1:
+        /* Clear CAN_RFF1_FFULL1 (rc_w1)*/
+        CANx->RFF1 = CAN_RFF1_FFULL1;
+        break;
+    case CAN_INT_FOV1:
+        /* Clear CAN_RFF1_FFOVR1 (rc_w1)*/
+        CANx->RFF1 = CAN_RFF1_FFOVR1;
+        break;
+    case CAN_INT_WKU:
+        /* Clear CAN_MSTS_WKUINT (rc_w1)*/
+        CANx->MSTS = CAN_MSTS_WKUINT;
+        break;
+    case CAN_INT_SLK:
+        /* Clear CAN_MSTS_SLAKINT (rc_w1)*/
+        CANx->MSTS = CAN_MSTS_SLAKINT;
+        break;
+    case CAN_INT_EWG:
+        /* Clear CAN_MSTS_ERRINT (rc_w1) */
+        CANx->MSTS = CAN_MSTS_ERRINT;
+        /* Note : the corresponding Flag is cleared by hardware depending
+                  of the CAN Bus status*/
+        break;
+    case CAN_INT_EPV:
+        /* Clear CAN_MSTS_ERRINT (rc_w1) */
+        CANx->MSTS = CAN_MSTS_ERRINT;
+        /* Note : the corresponding Flag is cleared by hardware depending
+                  of the CAN Bus status*/
+        break;
+    case CAN_INT_BOF:
+        /* Clear CAN_MSTS_ERRINT (rc_w1) */
+        CANx->MSTS = CAN_MSTS_ERRINT;
+        /* Note : the corresponding Flag is cleared by hardware depending
+                  of the CAN Bus status*/
+        break;
+    case CAN_INT_LEC:
+        /*  Clear LEC bits */
+        CANx->ESTS = RESET;
+        /* Clear CAN_MSTS_ERRINT (rc_w1) */
+        CANx->MSTS = CAN_MSTS_ERRINT;
+        break;
+    case CAN_INT_ERR:
+        /*Clear LEC bits */
+        CANx->ESTS = RESET;
+        /* Clear CAN_MSTS_ERRINT (rc_w1) */
+        CANx->MSTS = CAN_MSTS_ERRINT;
+        /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending
+            of the CAN Bus status*/
+        break;
+    default:
+        break;
+    }
+}
+
+/**
+ * @brief  Checks whether the CAN interrupt has occurred or not.
+ * @param  CAN_Reg specifies the CAN interrupt register to check.
+ * @param  Int_Bit specifies the interrupt source bit to check.
+ * @return The new state of the CAN Interrupt (SET or RESET).
+ */
+static INTStatus CheckINTStatus(uint32_t CAN_Reg, uint32_t Int_Bit)
+{
+    INTStatus pendingbitstatus = RESET;
+
+    if ((CAN_Reg & Int_Bit) != (uint32_t)RESET)
+    {
+        /* CAN_INT is set */
+        pendingbitstatus = SET;
+    }
+    else
+    {
+        /* CAN_INT is reset */
+        pendingbitstatus = RESET;
+    }
+    return pendingbitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_comp.c

@@ -0,0 +1,385 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_comp.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_comp.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @brief COMP driver modules
+ * @{
+ */
+
+/** @addtogroup COMP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup COMP_Private_Functions
+ * @{
+ */
+#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit)))
+#define ClrBit(reg, bit)         ((reg) &= ~(bit))
+#define SetBit(reg, bit)         ((reg) |= (bit))
+#define GetBit(reg, bit)         ((reg) & (bit))
+/**
+ * @brief  Deinitializes the COMP peripheral registers to their default reset values.
+ */
+void COMP_DeInit(void)
+{
+   RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, ENABLE);
+   RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP, DISABLE);
+   RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, ENABLE);
+   RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_COMP_FILT, DISABLE);
+}
+void COMP_StructInit(COMP_InitType* COMP_InitStruct)
+{
+    COMP_InitStruct->LowPoweMode =false;    // only COMP1 have this bit
+    COMP_InitStruct->InpDacConnect = false; // only COMP1 have this bit
+
+    COMP_InitStruct->Blking = COMP_CTRL_BLKING_NO; /*see @ref COMP_CTRL_BLKING */
+
+    COMP_InitStruct->Hyst = COMP_CTRL_HYST_NO; // see @COMPx_CTRL_HYST_MASK
+
+    COMP_InitStruct->PolRev = false; // out polarity reverse
+
+    COMP_InitStruct->OutTrig = COMP1_CTRL_OUTSEL_NC;
+    COMP_InitStruct->InpSel = COMP1_CTRL_INPSEL_FLOAT; //Float as same with comp1 and comp2
+    COMP_InitStruct->InmSel = COMP2_CTRL_INMSEL_NC; //NC as same with comp1 and comp2s
+    COMP_InitStruct->FilterEn=false;
+    COMP_InitStruct->ClkPsc=0;
+    COMP_InitStruct->SampWindow=0;
+    COMP_InitStruct->Thresh=0;
+    COMP_InitStruct->En = false;
+}
+void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct)
+{
+    COMP_SingleType* pCS;
+    __IO uint32_t tmp;
+    if (COMPx == COMP1)
+        pCS = &COMP->Cmp1;
+    else
+        pCS = &COMP->Cmp2;
+
+    // filter
+    tmp = pCS->FILC;
+    SetBitMsk(tmp, COMP_InitStruct->SampWindow << 6, COMP_FILC_SAMPW_MASK);
+    SetBitMsk(tmp, COMP_InitStruct->Thresh << 1, COMP_FILC_THRESH_MASK);
+    SetBitMsk(tmp, COMP_InitStruct->FilterEn << 0, COMP_FILC_FILEN_MASK);
+    pCS->FILC = tmp;
+    // filter psc
+    pCS->FILP = COMP_InitStruct->ClkPsc;
+
+    // ctrl
+    tmp = pCS->CTRL;
+    if (COMPx == COMP1)
+    {
+        if (COMP_InitStruct->InpDacConnect)
+            SetBit(tmp, COMP1_CTRL_INPDAC_MASK);
+        else
+            ClrBit(tmp, COMP1_CTRL_INPDAC_MASK);
+        if (COMP_InitStruct->LowPoweMode)
+            SetBit(tmp, COMP1_CTRL_PWRMODE_MASK);
+        else
+            ClrBit(tmp, COMP1_CTRL_PWRMODE_MASK);
+    }
+    SetBitMsk(tmp, COMP_InitStruct->Blking, COMP_CTRL_BLKING_MASK);
+    SetBitMsk(tmp, COMP_InitStruct->Hyst, COMPx_CTRL_HYST_MASK);
+    if (COMP_InitStruct->PolRev)
+        SetBit(tmp, COMP_POL_MASK);
+    else
+        ClrBit(tmp, COMP_POL_MASK);
+    SetBitMsk(tmp, COMP_InitStruct->OutTrig, COMP_CTRL_OUTSEL_MASK);
+    SetBitMsk(tmp, COMP_InitStruct->InpSel, COMP_CTRL_INPSEL_MASK);
+    SetBitMsk(tmp, COMP_InitStruct->InmSel, COMP_CTRL_INMSEL_MASK);
+    if (COMP_InitStruct->En)
+        SetBit(tmp, COMP_CTRL_EN_MASK);
+    else
+        ClrBit(tmp, COMP_CTRL_EN_MASK);
+    pCS->CTRL = tmp;
+}
+void COMP_Enable(COMPX COMPx, FunctionalState en)
+{
+    if (COMPx == COMP1)
+    {
+        if (en)
+            SetBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK);
+        else
+            ClrBit(COMP->Cmp1.CTRL, COMP_CTRL_EN_MASK);
+    }
+    else
+    {
+        if (en)
+            SetBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK);
+        else
+            ClrBit(COMP->Cmp2.CTRL, COMP_CTRL_EN_MASK);
+    }
+}
+
+void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel)
+{
+    __IO uint32_t tmp;
+    if (COMPx == COMP1)
+        tmp = COMP->Cmp1.CTRL;
+    else
+        tmp = COMP->Cmp2.CTRL;
+
+    SetBitMsk(tmp, VpSel, COMP_CTRL_INPSEL_MASK);
+
+    if (COMPx == COMP1)
+        COMP->Cmp1.CTRL = tmp;
+    else
+        COMP->Cmp2.CTRL = tmp;
+}
+void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel)
+{
+    __IO uint32_t tmp;
+    if (COMPx == COMP1)
+        tmp = COMP->Cmp1.CTRL;
+    else
+        tmp = COMP->Cmp2.CTRL;
+
+    SetBitMsk(tmp, VmSel, COMP_CTRL_INMSEL_MASK);
+
+    if (COMPx == COMP1)
+        COMP->Cmp1.CTRL = tmp;
+    else
+        COMP->Cmp2.CTRL = tmp;
+
+}
+void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig)
+{
+    __IO uint32_t tmp;
+    if (COMPx == COMP1)
+        tmp = COMP->Cmp1.CTRL;
+    else
+        tmp = COMP->Cmp2.CTRL;
+
+    SetBitMsk(tmp, OutTrig, COMP_CTRL_OUTSEL_MASK);
+
+    if (COMPx == COMP1)
+        COMP->Cmp1.CTRL = tmp;
+    else
+        COMP->Cmp2.CTRL = tmp;
+}
+
+// return see @COMP_INTSTS_CMPIS
+uint32_t COMP_GetIntSts(void)
+{
+    return COMP->INTSTS;
+}
+// parma range see @COMP_VREFSCL
+// Vv2Trim,Vv1Trim max 63
+void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En)
+{
+    __IO uint32_t tmp = 0;
+
+    SetBitMsk(tmp, Vv2Trim << 8, COMP_VREFSCL_VV2TRM_MSK);
+    SetBitMsk(tmp, Vv2En << 7, COMP_VREFSCL_VV2EN_MSK);
+    SetBitMsk(tmp, Vv1Trim << 1, COMP_VREFSCL_VV1TRM_MSK);
+    SetBitMsk(tmp, Vv1En << 0, COMP_VREFSCL_VV1EN_MSK);
+
+    COMP->VREFSCL = tmp;
+}
+// SET when comp out 1
+// RESET when comp out 0
+FlagStatus COMP_GetOutStatus(COMPX COMPx)
+{
+    if (COMPx == COMP1)
+        return (COMP->Cmp1.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET;
+    else
+        return (COMP->Cmp2.CTRL & COMP_CTRL_OUT_MASK) ? SET : RESET;
+}
+// get one comp interrupt flags
+FlagStatus COMP_GetIntStsOneComp(COMPX COMPx)
+{
+    return (COMP_GetIntSts() & (0x01 << COMPx)) ? SET : RESET;
+}
+
+// Lock see @COMP_LOCK
+void COMP_SetLock(uint32_t Lock)
+{
+    COMP->LOCK = Lock;
+}
+// IntEn see @COMP_INTEN_CMPIEN
+void COMP_SetIntEn(uint32_t IntEn)
+{
+    COMP->INTEN = IntEn;
+}
+// set comp2 xor output with comp1
+void COMP_CMP2XorOut(bool En)
+{
+    COMP->CMP2OSEL = (En==true)?0x1L:0x0L;
+}
+// set stop or lowpower mode that sel 32k clk
+void COMP_StopOrLowpower32KClkSel(bool En)
+{
+    COMP->LPCKSEL = (En==true)?0x1L:0x0L;
+}
+// set comp1 and comp2 component window compare mode
+void COMP_WindowModeEn(bool En)
+{
+    COMP->WINMODE = (En==true)?0x1L:0x0L;
+}
+
+
+/**
+ * @brief  Set the COMP filter clock Prescaler value.
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param FilPreVal Prescaler Value,Div clock = FilPreVal+1.
+ * @return void
+ */
+void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal)
+{
+    if (COMPx == COMP1)
+        COMP->Cmp1.FILP=FilPreVal;
+    else
+        COMP->Cmp2.FILP=FilPreVal;
+}
+
+/**
+ * @brief  Set the COMP filter control value.
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param FilEn 1 for enable ,0 or disable
+ * @param TheresNum  num under this value is noise
+ * @param SampPW  total sample number in a window
+ * @return void
+ */
+void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW)
+{
+    if (COMPx == COMP1)
+        COMP->Cmp1.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK);
+    else
+        COMP->Cmp2.FILC=(FilEn&COMP_FILC_FILEN_MASK)+((TheresNum<<1)&COMP_FILC_THRESH_MASK)+((SampPW<<6)&COMP_FILC_SAMPW_MASK);
+}
+
+/**
+ * @brief  Set the COMP Hyst value.
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param HYST specifies the HYST level.
+ *   This parameter can be one of the following values:
+*     @arg COMP_CTRL_HYST_NO Hyst disable
+*     @arg COMP_CTRL_HYST_LOW Hyst level 5.1mV
+*     @arg COMP_CTRL_HYST_MID Hyst level 15mV
+*     @arg COMP_CTRL_HYST_HIGH Hyst level 25mV
+ * @return void
+ */
+void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST)
+{
+    uint32_t tmp;
+    if (COMPx == COMP1)
+        tmp=COMP->Cmp1.CTRL;
+    else
+        tmp=COMP->Cmp2.CTRL;
+
+    tmp&=~COMP_CTRL_HYST_HIGH;
+    tmp|=HYST;
+    if (COMPx == COMP1)
+        COMP->Cmp1.CTRL=tmp;
+    else
+        COMP->Cmp2.CTRL=tmp;
+}
+
+/**
+ * @brief  Set the COMP Blanking source .
+ * @param COMPx where x can be 1 to 2 to select the COMP peripheral.
+ * @param BLK specifies the blanking source .
+ *   This parameter can be one of the following values:
+*     @arg COMP_CTRL_BLKING_NO Blanking  disable
+*     @arg COMP_CTRL_BLKING_TIM1_OC5 Blanking source TIM1_OC5
+*     @arg COMP_CTRL_BLKING_TIM8_OC5 Blanking source TIM8_OC5
+ * @return void
+ */
+void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK)
+{
+    uint32_t tmp;
+    if (COMPx == COMP1)
+        tmp=COMP->Cmp1.CTRL;
+    else
+        tmp=COMP->Cmp2.CTRL;
+    tmp&=~(7<<16);
+    tmp|=BLK;
+    if (COMPx == COMP1)
+        COMP->Cmp1.CTRL=tmp;
+    else
+        COMP->Cmp2.CTRL=tmp;
+}
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_crc.c

@@ -0,0 +1,227 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_crc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_crc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @brief CRC driver modules
+ * @{
+ */
+
+/** @addtogroup CRC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Resets the CRC Data register (DAT).
+ */
+void CRC32_ResetCrc(void)
+{
+    /* Reset CRC generator */
+    CRC->CRC32CTRL = CRC32_CTRL_RESET;
+}
+
+/**
+ * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+ * @param Data data word(32-bit) to compute its CRC
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_CalcCrc(uint32_t Data)
+{
+    CRC->CRC32DAT = Data;
+
+    return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ * @param pBuffer pointer to the buffer containing the data to be computed
+ * @param BufferLength length of the buffer to be computed
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength)
+{
+    uint32_t index = 0;
+
+    for (index = 0; index < BufferLength; index++)
+    {
+        CRC->CRC32DAT = pBuffer[index];
+    }
+    return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief  Returns the current CRC value.
+ * @return 32-bit CRC
+ */
+uint32_t CRC32_GetCrc(void)
+{
+    return (CRC->CRC32DAT);
+}
+
+/**
+ * @brief  Stores a 8-bit data in the Independent Data(ID) register.
+ * @param IDValue 8-bit value to be stored in the ID register
+ */
+void CRC32_SetIDat(uint8_t IDValue)
+{
+    CRC->CRC32IDAT = IDValue;
+}
+
+/**
+ * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+ * @return 8-bit value of the ID register
+ */
+uint8_t CRC32_GetIDat(void)
+{
+    return (CRC->CRC32IDAT);
+}
+
+// CRC16 add
+void __CRC16_SetLittleEndianFmt(void)
+{
+    CRC->CRC16CTRL = CRC16_CTRL_LITTLE | CRC->CRC16CTRL;
+}
+void __CRC16_SetBigEndianFmt(void)
+{
+    CRC->CRC16CTRL = CRC16_CTRL_BIG & CRC->CRC16CTRL;
+}
+void __CRC16_SetCleanEnable(void)
+{
+    CRC->CRC16CTRL = CRC16_CTRL_RESET | CRC->CRC16CTRL;
+}
+void __CRC16_SetCleanDisable(void)
+{
+    CRC->CRC16CTRL = CRC16_CTRL_NO_RESET & CRC->CRC16CTRL;
+}
+
+uint16_t __CRC16_CalcCrc(uint8_t Data)
+{
+    CRC->CRC16DAT = Data;
+    return (CRC->CRC16D);
+}
+
+void __CRC16_SetCrc(uint8_t Data)
+{
+    CRC->CRC16DAT = Data;
+}
+
+uint16_t __CRC16_GetCrc(void)
+{
+    return (CRC->CRC16D);
+}
+
+void __CRC16_SetLRC(uint8_t Data)
+{
+    CRC->LRC = Data;
+}
+
+uint8_t __CRC16_GetLRC(void)
+{
+    return (CRC->LRC);
+}
+
+uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength)
+{
+    uint32_t index = 0;
+
+    CRC->CRC16D = 0x00;
+    for (index = 0; index < BufferLength; index++)
+    {
+        CRC->CRC16DAT = pBuffer[index];
+    }
+    return (CRC->CRC16D);
+}
+
+uint16_t CRC16_CalcCRC(uint8_t Data)
+{
+    CRC->CRC16DAT = Data;
+
+    return (CRC->CRC16D);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dac.c

@@ -0,0 +1,357 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_dac.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_dac.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+/** @addtogroup DAC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Defines
+ * @{
+ */
+
+/* CTRL register Mask */
+#define CTRL_CLEAR_MASK ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET   ((uint32_t)0x00000001)
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFE)
+
+/* DCH registers offsets */
+#define DR12CH_OFFSET ((uint32_t)0x00000008)
+
+/* DATO register offset */
+#define DATO_OFFSET ((uint32_t)0x0000002C)
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+ */
+void DAC_DeInit(void)
+{
+    /* Enable DAC reset state */
+    RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, ENABLE);
+    /* Release DAC from reset state */
+    RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, DISABLE);
+}
+
+/**
+ * @brief  Initializes the DAC peripheral according to the specified
+ *         parameters in the DAC_InitStruct.
+ * @param DAC_Channel the selected DAC channel.
+ *   This parameter can be one of the following values:
+ *     @arg DAC_CHANNEL_1 DAC Channel1 selected
+ *     @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param DAC_InitStruct pointer to a DAC_InitType structure that
+ *        contains the configuration information for the specified DAC channel.
+ */
+void DAC_Init(DAC_InitType* DAC_InitStruct)
+{
+    uint32_t tmpreg1 = 0, tmpreg2 = 0;
+    /* Check the DAC parameters */
+    assert_param(IS_DAC_TRIGGER(DAC_InitStruct->Trigger));
+    assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->WaveGen));
+    assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->LfsrUnMaskTriAmp));
+    assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->BufferOutput));
+    /*---------------------------- DAC CTRL Configuration --------------------------*/
+    /* Get the DAC CTRL value */
+    tmpreg1 = DAC->CTRL;
+    /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+    tmpreg1 &= ~(CTRL_CLEAR_MASK );
+    /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+       mask/amplitude for wave generation */
+    /* Set TSELx and TENx bits according to Trigger value */
+    /* Set WAVEx bits according to WaveGen value */
+    /* Set MAMPx bits according to LfsrUnMaskTriAmp value */
+    /* Set BOFFx bit according to BufferOutput value */
+    tmpreg2 = (DAC_InitStruct->Trigger | DAC_InitStruct->WaveGen | DAC_InitStruct->LfsrUnMaskTriAmp
+               | DAC_InitStruct->BufferOutput);
+    /* Calculate CTRL register value depending on DAC_Channel */
+    tmpreg1 |= tmpreg2 ;
+    /* Write to DAC CTRL */
+    DAC->CTRL = tmpreg1;
+}
+
+/**
+ * @brief  Fills each DAC_InitStruct member with its default value.
+ * @param DAC_InitStruct pointer to a DAC_InitType structure which will
+ *         be initialized.
+ */
+void DAC_ClearStruct(DAC_InitType* DAC_InitStruct)
+{
+    /*--------------- Reset DAC init structure parameters values -----------------*/
+    /* Initialize the Trigger member */
+    DAC_InitStruct->Trigger = DAC_TRG_NONE;
+    /* Initialize the WaveGen member */
+    DAC_InitStruct->WaveGen = DAC_WAVEGEN_NONE;
+    /* Initialize the LfsrUnMaskTriAmp member */
+    DAC_InitStruct->LfsrUnMaskTriAmp = DAC_UNMASK_LFSRBIT0;
+    /* Initialize the BufferOutput member */
+    DAC_InitStruct->BufferOutput = DAC_BUFFOUTPUT_ENABLE;
+}
+
+/**
+ * @brief  Enables or disables the specified DAC channel.
+ * @param DAC_Channel the selected DAC channel.
+ *   This parameter can be one of the following values:
+ *     @arg DAC_CHANNEL_1 DAC Channel1 selected
+ *     @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the DAC channel.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_Enable(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected DAC channel */
+        DAC->CTRL |= DAC_CTRL_CHEN ;
+    }
+    else
+    {
+        /* Disable the selected DAC channel */
+        DAC->CTRL &= ~DAC_CTRL_CHEN ;
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified DAC channel DMA request.
+ * @param DAC_Channel the selected DAC channel.
+ *   This parameter can be one of the following values:
+ *     @arg DAC_CHANNEL_1 DAC Channel1 selected
+ *     @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the selected DAC channel DMA request.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_DmaEnable(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected DAC channel DMA request */
+        DAC->CTRL |= DAC_CTRL_DMAEN;
+    }
+    else
+    {
+        /* Disable the selected DAC channel DMA request */
+        DAC->CTRL &= ~DAC_CTRL_DMAEN;
+    }
+}
+
+/**
+ * @brief  Enables or disables the selected DAC channel software trigger.
+ * @param DAC_Channel the selected DAC channel.
+ *   This parameter can be one of the following values:
+ *     @arg DAC_CHANNEL_1 DAC Channel1 selected
+ *     @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param Cmd new state of the selected DAC channel software trigger.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_SoftTrgEnable(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable software trigger for the selected DAC channel */
+        DAC->SOTTR |= DAC_SOTTR_TREN ;
+    }
+    else
+    {
+        /* Disable software trigger for the selected DAC channel */
+        DAC->SOTTR &= ~(DAC_SOTTR_TREN);
+    }
+}
+
+/**
+ * @brief  Enables or disables simultaneously the two DAC channels software
+ *   triggers.
+ * @param Cmd new state of the DAC channels software triggers.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_SoftwareTrgEnable(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable software trigger for both DAC channels */
+        DAC->SOTTR |= DUAL_SWTRIG_SET;
+    }
+    else
+    {
+        /* Disable software trigger for both DAC channels */
+        DAC->SOTTR &= DUAL_SWTRIG_RESET;
+    }
+}
+
+/**
+ * @brief  Enables or disables the selected DAC channel wave generation.
+ * @param DAC_Channel the selected DAC channel.
+ *   This parameter can be one of the following values:
+ *     @arg DAC_CHANNEL_1 DAC Channel1 selected
+ *     @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @param DAC_Wave Specifies the wave type to enable or disable.
+ *   This parameter can be one of the following values:
+ *     @arg DAC_WAVE_NOISE noise wave generation
+ *     @arg DAC_WAVE_TRIANGLE triangle wave generation
+ * @param Cmd new state of the selected DAC channel wave generation.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd)
+{
+      __IO uint32_t tmp = 0;
+    /* Check the parameters */
+    assert_param(IS_DAC_WAVE(DAC_Wave));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+      tmp=DAC->CTRL;
+      tmp&=~(3<<6);
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected wave generation for the selected DAC channel */
+        tmp |= DAC_Wave;
+    }
+    else
+    {
+        /* Disable the selected wave generation for the selected DAC channel */
+        tmp&=~(3<<6);
+    }
+        DAC->CTRL =tmp;
+}
+
+/**
+ * @brief  Set the specified data holding register value for DAC channel1.
+ * @param DAC_Align Specifies the data alignment for DAC channel1.
+ *   This parameter can be one of the following values:
+ *     @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected
+ *     @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected
+ *     @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected
+ * @param Data Data to be loaded in the selected data holding register.
+ */
+void DAC_SetChData(uint32_t DAC_Align, uint16_t Data)
+{
+    __IO uint32_t tmp = 0;
+
+    /* Check the parameters */
+    assert_param(IS_DAC_ALIGN(DAC_Align));
+    assert_param(IS_DAC_DATA(Data));
+
+    tmp = (uint32_t)DAC_BASE;
+    tmp += DR12CH_OFFSET + DAC_Align;
+
+    /* Set the DAC channel1 selected data holding register */
+    *(__IO uint32_t*)tmp = Data;
+}
+
+
+
+
+
+/**
+ * @brief  Returns the last data output value of the selected DAC channel.
+ * @param DAC_Channel the selected DAC channel.
+ *   This parameter can be one of the following values:
+ *     @arg DAC_CHANNEL_1 DAC Channel1 selected
+ *     @arg DAC_CHANNEL_2 DAC Channel2 selected
+ * @return The selected DAC channel data output value.
+ */
+uint16_t DAC_GetOutputDataVal(void)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)DAC_BASE;
+    tmp += DATO_OFFSET;
+
+    /* Returns the DAC channel data output register value */
+    return (uint16_t)(*(__IO uint32_t*)tmp);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dbg.c

@@ -0,0 +1,246 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_dbg.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_dbg.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBG
+ * @brief DBG driver modules
+ * @{
+ */
+
+/** @addtogroup DBGMCU_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Defines
+ * @{
+ */
+
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DBGMCU_Private_Functions
+ * @{
+ */
+
+
+void GetUCID(uint8_t *UCIDbuf)
+{
+    uint8_t num = 0;
+    uint32_t* ucid_addr = (void*)0;
+    uint32_t temp = 0;
+
+    ucid_addr = (uint32_t*)UCID_BASE;
+
+    for (num = 0; num < UCID_LENGTH;)
+    {
+        temp = *(__IO uint32_t*)(ucid_addr++);
+        UCIDbuf[num++] = (temp & 0xFF);
+        UCIDbuf[num++] = (temp & 0xFF00) >> 8;
+        UCIDbuf[num++] = (temp & 0xFF0000) >> 16;
+        UCIDbuf[num++] = (temp & 0xFF000000) >> 24;
+    }
+}
+
+/**
+ * @brief  Returns the UID.
+ * @return UID
+ */
+
+void GetUID(uint8_t *UIDbuf)
+{
+    uint8_t num = 0;
+    uint32_t* uid_addr = (void*)0;
+    uint32_t temp = 0;
+
+    uid_addr = (uint32_t*)UID_BASE;
+
+    for (num = 0; num < UID_LENGTH;)
+    {
+        temp = *(__IO uint32_t*)(uid_addr++);
+        UIDbuf[num++] = (temp & 0xFF);
+        UIDbuf[num++] = (temp & 0xFF00) >> 8;
+        UIDbuf[num++] = (temp & 0xFF0000) >> 16;
+        UIDbuf[num++] = (temp & 0xFF000000) >> 24;
+    }
+}
+
+/**
+ * @brief  Returns the DBGMCU_ID.
+ * @return DBGMCU_ID
+ */
+
+void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf)
+{
+    uint8_t num = 0;
+    uint32_t* dbgid_addr = (void*)0;
+    uint32_t temp = 0;
+
+    dbgid_addr = (uint32_t*)DBGMCU_ID_BASE;
+    for (num = 0; num < DBGMCU_ID_LENGTH;)
+    {
+        temp = *(__IO uint32_t*)(dbgid_addr++);
+        DBGMCU_IDbuf[num++] = (temp & 0xFF);
+        DBGMCU_IDbuf[num++] = (temp & 0xFF00) >> 8;
+        DBGMCU_IDbuf[num++] = (temp & 0xFF0000) >> 16;
+        DBGMCU_IDbuf[num++] = (temp & 0xFF000000) >> 24;
+    }
+}
+
+/**
+ * @brief  Returns the device revision number.
+ * @return Device revision identifier
+ */
+uint32_t DBG_GetRevNum(void)
+{
+    return (DBG->ID & 0x00FF);
+}
+
+/**
+ * @brief  Returns the device identifier.
+ * @return Device identifier
+ */
+uint32_t DBG_GetDevNum(void)
+{
+    uint32_t id = DBG->ID;
+    return ((id & 0x00F00000) >> 20) | ((id & 0xFF00) >> 4);
+}
+
+/**
+ * @brief  Configures the specified peripheral and low power mode behavior
+ *   when the MCU under Debug mode.
+ * @param DBG_Periph specifies the peripheral and low power mode.
+ *   This parameter can be any combination of the following values:
+ *     @arg DBG_SLEEP Keep debugger connection during SLEEP mode
+ *     @arg DBG_STOP Keep debugger connection during STOP mode
+ *     @arg DBG_STDBY Keep debugger connection during STANDBY mode
+ *     @arg DBG_IWDG_STOP Debug IWDG stopped when Core is halted
+ *     @arg DBG_WWDG_STOP Debug WWDG stopped when Core is halted
+ *     @arg DBG_TIM1_STOP TIM1 counter stopped when Core is halted
+ *     @arg DBG_TIM2_STOP TIM2 counter stopped when Core is halted
+ *     @arg DBG_TIM3_STOP TIM3 counter stopped when Core is halted
+ *     @arg DBG_TIM4_STOP TIM4 counter stopped when Core is halted
+ *     @arg DBG_CAN_STOP Debug CAN stopped when Core is halted
+ *     @arg DBG_I2C1SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when Core is halted
+ *     @arg DBG_I2C2SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when Core is halted
+ *     @arg DBG_TIM8_STOP TIM8 counter stopped when Core is halted
+ *     @arg DBG_TIM5_STOP TIM5 counter stopped when Core is halted
+ *     @arg DBG_TIM6_STOP TIM6 counter stopped when Core is halted
+ *     @arg DBG_TIM7_STOP TIM7 counter stopped when Core is halted
+ *     @arg DBG_TIM9_STOP TIM9 counter stopped when Core is halted
+
+ * @param Cmd new state of the specified peripheral in Debug mode.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_DBGMCU_PERIPH(DBG_Periph));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        DBG->CTRL |= DBG_Periph;
+    }
+    else
+    {
+        DBG->CTRL &= ~DBG_Periph;
+    }
+}
+
+/**
+ * @brief Get FLASH size of this chip.
+ *
+ * @return FLASH size in bytes.
+ */
+uint32_t DBG_GetFlashSize(void)
+{
+    return (DBG->ID & 0x000F0000);
+}
+
+/**
+ * @brief Get SRAM size of this chip.
+ *
+ * @return SRAM size in bytes.
+ */
+uint32_t DBG_GetSramSize(void)
+{
+    return (((DBG->ID & 0xF0000000) >> 28) + 1) << 14;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dma.c

@@ -0,0 +1,686 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_dma.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_dma.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+/** @addtogroup DMA_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Defines
+ * @{
+ */
+
+/* DMA Channelx interrupt pending bit masks */
+#define DMA_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1))
+#define DMA_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2))
+#define DMA_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3))
+#define DMA_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4))
+#define DMA_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5))
+#define DMA_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6))
+#define DMA_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7))
+#define DMA_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8))
+
+
+/* DMA CHCFGx registers Masks, MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the DMAy Channelx registers to their default reset
+ *         values.
+ * @param DMAyChx where y can be 1 or 2 to select the DMA and
+ *   x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
+ */
+void DMA_DeInit(DMA_ChannelType* DMAChx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+
+    /* Disable the selected DMAy Channelx */
+    DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN);
+
+    /* Reset DMAy Channelx control register */
+    DMAChx->CHCFG = 0;
+
+    /* Reset DMAy Channelx remaining bytes register */
+    DMAChx->TXNUM = 0;
+
+    /* Reset DMAy Channelx peripheral address register */
+    DMAChx->PADDR = 0;
+
+    /* Reset DMAy Channelx memory address register */
+    DMAChx->MADDR = 0;
+
+    if (DMAChx == DMA_CH1)
+    {
+        /* Reset interrupt pending bits for DMA1 Channel1 */
+        DMA->INTCLR |= DMA_CH1_INT_MASK;
+    }
+    else if (DMAChx == DMA_CH2)
+    {
+        /* Reset interrupt pending bits for DMA1 Channel2 */
+        DMA->INTCLR |= DMA_CH2_INT_MASK;
+    }
+    else if (DMAChx == DMA_CH3)
+    {
+        /* Reset interrupt pending bits for DMA1 Channel3 */
+        DMA->INTCLR |= DMA_CH3_INT_MASK;
+    }
+    else if (DMAChx == DMA_CH4)
+    {
+        /* Reset interrupt pending bits for DMA1 Channel4 */
+        DMA->INTCLR |= DMA_CH4_INT_MASK;
+    }
+    else if (DMAChx == DMA_CH5)
+    {
+        /* Reset interrupt pending bits for DMA1 Channel5 */
+        DMA->INTCLR |= DMA_CH5_INT_MASK;
+    }
+    else if (DMAChx == DMA_CH6)
+    {
+        /* Reset interrupt pending bits for DMA1 Channel6 */
+        DMA->INTCLR |= DMA_CH6_INT_MASK;
+    }
+    else if (DMAChx == DMA_CH7)
+    {
+        /* Reset interrupt pending bits for DMA1 Channel7 */
+        DMA->INTCLR |= DMA_CH7_INT_MASK;
+    }
+    else if (DMAChx == DMA_CH8)
+    {
+        /* Reset interrupt pending bits for DMA1 Channel8 */
+        DMA->INTCLR |= DMA_CH8_INT_MASK;
+    }
+}
+
+/**
+ * @brief  Initializes the DMAy Channelx according to the specified
+ *         parameters in the DMA_InitParam.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param DMA_InitParam pointer to a DMA_InitType structure that
+ *         contains the configuration information for the specified DMA Channel.
+ */
+void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam)
+{
+    uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+    assert_param(IS_DMA_DIR(DMA_InitParam->Direction));
+    assert_param(IS_DMA_BUF_SIZE(DMA_InitParam->BufSize));
+    assert_param(IS_DMA_PERIPH_INC_STATE(DMA_InitParam->PeriphInc));
+    assert_param(IS_DMA_MEM_INC_STATE(DMA_InitParam->DMA_MemoryInc));
+    assert_param(IS_DMA_PERIPH_DATA_SIZE(DMA_InitParam->PeriphDataSize));
+    assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitParam->MemDataSize));
+    assert_param(IS_DMA_MODE(DMA_InitParam->CircularMode));
+    assert_param(IS_DMA_PRIORITY(DMA_InitParam->Priority));
+    assert_param(IS_DMA_M2M_STATE(DMA_InitParam->Mem2Mem));
+
+    /*--------------------------- DMAy Channelx CHCFG Configuration -----------------*/
+    /* Get the DMAyChx CHCFG value */
+    tmpregister = DMAChx->CHCFG;
+    /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+    tmpregister &= CCR_CLEAR_Mask;
+    /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+    /* Set DIR bit according to Direction value */
+    /* Set CIRC bit according to CircularMode value */
+    /* Set PINC bit according to PeriphInc value */
+    /* Set MINC bit according to DMA_MemoryInc value */
+    /* Set PSIZE bits according to PeriphDataSize value */
+    /* Set MSIZE bits according to MemDataSize value */
+    /* Set PL bits according to Priority value */
+    /* Set the MEM2MEM bit according to Mem2Mem value */
+    tmpregister |= DMA_InitParam->Direction | DMA_InitParam->CircularMode | DMA_InitParam->PeriphInc
+                   | DMA_InitParam->DMA_MemoryInc | DMA_InitParam->PeriphDataSize | DMA_InitParam->MemDataSize
+                   | DMA_InitParam->Priority | DMA_InitParam->Mem2Mem;
+
+    /* Write to DMAy Channelx CHCFG */
+    DMAChx->CHCFG = tmpregister;
+
+    /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/
+    /* Write to DMAy Channelx TXNUM */
+    DMAChx->TXNUM = DMA_InitParam->BufSize;
+
+    /*--------------------------- DMAy Channelx PADDR Configuration ----------------*/
+    /* Write to DMAy Channelx PADDR */
+    DMAChx->PADDR = DMA_InitParam->PeriphAddr;
+
+    /*--------------------------- DMAy Channelx MADDR Configuration ----------------*/
+    /* Write to DMAy Channelx MADDR */
+    DMAChx->MADDR = DMA_InitParam->MemAddr;
+}
+
+/**
+ * @brief  Fills each DMA_InitParam member with its default value.
+ * @param DMA_InitParam pointer to a DMA_InitType structure which will
+ *         be initialized.
+ */
+void DMA_StructInit(DMA_InitType* DMA_InitParam)
+{
+    /*-------------- Reset DMA init structure parameters values ------------------*/
+    /* Initialize the PeriphAddr member */
+    DMA_InitParam->PeriphAddr = 0;
+    /* Initialize the MemAddr member */
+    DMA_InitParam->MemAddr = 0;
+    /* Initialize the Direction member */
+    DMA_InitParam->Direction = DMA_DIR_PERIPH_SRC;
+    /* Initialize the BufSize member */
+    DMA_InitParam->BufSize = 0;
+    /* Initialize the PeriphInc member */
+    DMA_InitParam->PeriphInc = DMA_PERIPH_INC_DISABLE;
+    /* Initialize the DMA_MemoryInc member */
+    DMA_InitParam->DMA_MemoryInc = DMA_MEM_INC_DISABLE;
+    /* Initialize the PeriphDataSize member */
+    DMA_InitParam->PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE;
+    /* Initialize the MemDataSize member */
+    DMA_InitParam->MemDataSize = DMA_MemoryDataSize_Byte;
+    /* Initialize the CircularMode member */
+    DMA_InitParam->CircularMode = DMA_MODE_NORMAL;
+    /* Initialize the Priority member */
+    DMA_InitParam->Priority = DMA_PRIORITY_LOW;
+    /* Initialize the Mem2Mem member */
+    DMA_InitParam->Mem2Mem = DMA_M2M_DISABLE;
+}
+
+/**
+ * @brief  Enables or disables the specified DMAy Channelx.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param Cmd new state of the DMA Channelx.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected DMAy Channelx */
+        DMAChx->CHCFG |= DMA_CHCFG1_CHEN;
+    }
+    else
+    {
+        /* Disable the selected DMAy Channelx */
+        DMAChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN);
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified DMAy Channelx interrupts.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param DMAInt specifies the DMA interrupts sources to be enabled
+ *   or disabled.
+ *   This parameter can be any combination of the following values:
+ *     @arg DMA_INT_TXC Transfer complete interrupt mask
+ *     @arg DMA_INT_HTX Half transfer interrupt mask
+ *     @arg DMA_INT_ERR Transfer error interrupt mask
+ * @param Cmd new state of the specified DMA interrupts.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+    assert_param(IS_DMA_CONFIG_INT(DMAInt));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected DMA interrupts */
+        DMAChx->CHCFG |= DMAInt;
+    }
+    else
+    {
+        /* Disable the selected DMA interrupts */
+        DMAChx->CHCFG &= ~DMAInt;
+    }
+}
+
+/**
+ * @brief  Sets the number of data units in the current DMAy Channelx transfer.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param DataNumber The number of data units in the current DMAy Channelx
+ *         transfer.
+ * @note   This function can only be used when the DMAyChx is disabled.
+ */
+void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+
+    /*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/
+    /* Write to DMA Channelx TXNUM */
+    DMAChx->TXNUM = DataNumber;
+}
+
+/**
+ * @brief  Returns the number of remaining data units in the current
+ *         DMA Channelx transfer.
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @return The number of remaining data units in the current DMA Channelx
+ *         transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMAChx));
+    /* Return the number of remaining data units for DMAy Channelx */
+    return ((uint16_t)(DMAChx->TXNUM));
+}
+
+/**
+ * @brief  Checks whether the specified DMA Channelx flag is set or not.
+ * @param DMAFlag specifies the flag to check.
+ *   This parameter can be one of the following values:
+ *     @arg DMA_FLAG_GL1 DMA Channel1 global flag.
+ *     @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag.
+ *     @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag.
+ *     @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag.
+ *     @arg DMA_FLAG_GL2 DMA Channel2 global flag.
+ *     @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag.
+ *     @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag.
+ *     @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag.
+ *     @arg DMA_FLAG_GL3 DMA Channel3 global flag.
+ *     @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag.
+ *     @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag.
+ *     @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag.
+ *     @arg DMA_FLAG_GL4 DMA Channel4 global flag.
+ *     @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag.
+ *     @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag.
+ *     @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag.
+ *     @arg DMA_FLAG_GL5 DMA Channel5 global flag.
+ *     @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag.
+ *     @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag.
+ *     @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag.
+ *     @arg DMA_FLAG_GL6 DMA Channel6 global flag.
+ *     @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag.
+ *     @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag.
+ *     @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag.
+ *     @arg DMA_FLAG_GL7 DMA Channel7 global flag.
+ *     @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag.
+ *     @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag.
+ *     @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag.
+ *     @arg DMA_FLAG_GL8 DMA Channel7 global flag.
+ *     @arg DMA_FLAG_TC8 DMA Channel7 transfer complete flag.
+ *     @arg DMA_FLAG_HT8 DMA Channel7 half transfer flag.
+ *     @arg DMA_FLAG_TE8 DMA Channel7 transfer error flag.
+ * @param DMAy DMA
+ *   This parameter can be one of the following values:
+ *     @arg DMA .
+ * @return The new state of DMAFlag (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy)
+{
+    FlagStatus bitstatus = RESET;
+    uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_DMA_GET_FLAG(DMAFlag));
+
+    /* Calculate the used DMAy */
+    /* Get DMAy INTSTS register value */
+    tmpregister = DMAy->INTSTS;
+
+    /* Check the status of the specified DMAy flag */
+    if ((tmpregister & DMAFlag) != (uint32_t)RESET)
+    {
+        /* DMAyFlag is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* DMAyFlag is reset */
+        bitstatus = RESET;
+    }
+
+    /* Return the DMAyFlag status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the DMA Channelx's pending flags.
+ * @param DMAFlag specifies the flag to clear.
+ *   This parameter can be any combination (for the same DMA) of the following values:
+ *     @arg DMA_FLAG_GL1 DMA Channel1 global flag.
+ *     @arg DMA_FLAG_TC1 DMA Channel1 transfer complete flag.
+ *     @arg DMA_FLAG_HT1 DMA Channel1 half transfer flag.
+ *     @arg DMA_FLAG_TE1 DMA Channel1 transfer error flag.
+ *     @arg DMA_FLAG_GL2 DMA Channel2 global flag.
+ *     @arg DMA_FLAG_TC2 DMA Channel2 transfer complete flag.
+ *     @arg DMA_FLAG_HT2 DMA Channel2 half transfer flag.
+ *     @arg DMA_FLAG_TE2 DMA Channel2 transfer error flag.
+ *     @arg DMA_FLAG_GL3 DMA Channel3 global flag.
+ *     @arg DMA_FLAG_TC3 DMA Channel3 transfer complete flag.
+ *     @arg DMA_FLAG_HT3 DMA Channel3 half transfer flag.
+ *     @arg DMA_FLAG_TE3 DMA Channel3 transfer error flag.
+ *     @arg DMA_FLAG_GL4 DMA Channel4 global flag.
+ *     @arg DMA_FLAG_TC4 DMA Channel4 transfer complete flag.
+ *     @arg DMA_FLAG_HT4 DMA Channel4 half transfer flag.
+ *     @arg DMA_FLAG_TE4 DMA Channel4 transfer error flag.
+ *     @arg DMA_FLAG_GL5 DMA Channel5 global flag.
+ *     @arg DMA_FLAG_TC5 DMA Channel5 transfer complete flag.
+ *     @arg DMA_FLAG_HT5 DMA Channel5 half transfer flag.
+ *     @arg DMA_FLAG_TE5 DMA Channel5 transfer error flag.
+ *     @arg DMA_FLAG_GL6 DMA Channel6 global flag.
+ *     @arg DMA_FLAG_TC6 DMA Channel6 transfer complete flag.
+ *     @arg DMA_FLAG_HT6 DMA Channel6 half transfer flag.
+ *     @arg DMA_FLAG_TE6 DMA Channel6 transfer error flag.
+ *     @arg DMA_FLAG_GL7 DMA Channel7 global flag.
+ *     @arg DMA_FLAG_TC7 DMA Channel7 transfer complete flag.
+ *     @arg DMA_FLAG_HT7 DMA Channel7 half transfer flag.
+ *     @arg DMA_FLAG_TE7 DMA Channel7 transfer error flag.
+ *     @arg DMA_FLAG_GL8 DMA Channel8 global flag.
+ *     @arg DMA_FLAG_TC8 DMA Channel8 transfer complete flag.
+ *     @arg DMA_FLAG_HT8 DMA Channel8 half transfer flag.
+ *     @arg DMA_FLAG_TE8 DMA Channel8 transfer error flag.
+ * @param DMA DMA
+ *   This parameter can be one of the following values:
+ *     @arg DMA .
+ */
+void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_CLEAR_FLAG(DMAFlag));
+
+    /* Calculate the used DMAy */
+    /* Clear the selected DMAy flags */
+    DMAy->INTCLR = DMAFlag;
+}
+
+/**
+ * @brief  Checks whether the specified DMA Channelx interrupt has occurred or not.
+ * @param DMA_IT specifies the DMAy interrupt source to check.
+ *   This parameter can be one of the following values:
+ *     @arg DMA_INT_GLB1 DMA Channel1 global interrupt.
+ *     @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt.
+ *     @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt.
+ *     @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt.
+ *     @arg DMA_INT_GLB2 DMA Channel2 global interrupt.
+ *     @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt.
+ *     @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt.
+ *     @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt.
+ *     @arg DMA_INT_GLB3 DMA Channel3 global interrupt.
+ *     @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt.
+ *     @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt.
+ *     @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt.
+ *     @arg DMA_INT_GLB4 DMA Channel4 global interrupt.
+ *     @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt.
+ *     @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt.
+ *     @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt.
+ *     @arg DMA_INT_GLB5 DMA Channel5 global interrupt.
+ *     @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt.
+ *     @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt.
+ *     @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt.
+ *     @arg DMA_INT_GLB6 DMA Channel6 global interrupt.
+ *     @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt.
+ *     @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt.
+ *     @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt.
+ *     @arg DMA_INT_GLB7 DMA Channel7 global interrupt.
+ *     @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt.
+ *     @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt.
+ *     @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt.
+ *     @arg DMA_INT_GLB8 DMA Channel8 global interrupt.
+ *     @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt.
+ *     @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt.
+ *     @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt.
+ * @param DMA DMA
+ *   This parameter can be one of the following values:
+ *     @arg DMA .
+ * @return The new state of DMA_IT (SET or RESET).
+ */
+INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy)
+{
+    INTStatus bitstatus  = RESET;
+    uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_DMA_GET_IT(DMA_IT));
+
+    /* Calculate the used DMA */
+    /* Get DMAy INTSTS register value */
+    tmpregister = DMAy->INTSTS;
+
+    /* Check the status of the specified DMAy interrupt */
+    if ((tmpregister & DMA_IT) != (uint32_t)RESET)
+    {
+        /* DMAy_IT is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* DMAy_IT is reset */
+        bitstatus = RESET;
+    }
+    /* Return the DMAInt status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the DMA Channelx's interrupt pending bits.
+ * @param DMA_IT specifies the DMA interrupt pending bit to clear.
+ *   This parameter can be any combination (for the same DMA) of the following values:
+ *     @arg DMA_INT_GLB1 DMA Channel1 global interrupt.
+ *     @arg DMA_INT_TXC1 DMA Channel1 transfer complete interrupt.
+ *     @arg DMA_INT_HTX1 DMA Channel1 half transfer interrupt.
+ *     @arg DMA_INT_ERR1 DMA Channel1 transfer error interrupt.
+ *     @arg DMA_INT_GLB2 DMA Channel2 global interrupt.
+ *     @arg DMA_INT_TXC2 DMA Channel2 transfer complete interrupt.
+ *     @arg DMA_INT_HTX2 DMA Channel2 half transfer interrupt.
+ *     @arg DMA_INT_ERR2 DMA Channel2 transfer error interrupt.
+ *     @arg DMA_INT_GLB3 DMA Channel3 global interrupt.
+ *     @arg DMA_INT_TXC3 DMA Channel3 transfer complete interrupt.
+ *     @arg DMA_INT_HTX3 DMA Channel3 half transfer interrupt.
+ *     @arg DMA_INT_ERR3 DMA Channel3 transfer error interrupt.
+ *     @arg DMA_INT_GLB4 DMA Channel4 global interrupt.
+ *     @arg DMA_INT_TXC4 DMA Channel4 transfer complete interrupt.
+ *     @arg DMA_INT_HTX4 DMA Channel4 half transfer interrupt.
+ *     @arg DMA_INT_ERR4 DMA Channel4 transfer error interrupt.
+ *     @arg DMA_INT_GLB5 DMA Channel5 global interrupt.
+ *     @arg DMA_INT_TXC5 DMA Channel5 transfer complete interrupt.
+ *     @arg DMA_INT_HTX5 DMA Channel5 half transfer interrupt.
+ *     @arg DMA_INT_ERR5 DMA Channel5 transfer error interrupt.
+ *     @arg DMA_INT_GLB6 DMA Channel6 global interrupt.
+ *     @arg DMA_INT_TXC6 DMA Channel6 transfer complete interrupt.
+ *     @arg DMA_INT_HTX6 DMA Channel6 half transfer interrupt.
+ *     @arg DMA_INT_ERR6 DMA Channel6 transfer error interrupt.
+ *     @arg DMA_INT_GLB7 DMA Channel7 global interrupt.
+ *     @arg DMA_INT_TXC7 DMA Channel7 transfer complete interrupt.
+ *     @arg DMA_INT_HTX7 DMA Channel7 half transfer interrupt.
+ *     @arg DMA_INT_ERR7 DMA Channel7 transfer error interrupt.
+ *     @arg DMA_INT_GLB8 DMA Channel8 global interrupt.
+ *     @arg DMA_INT_TXC8 DMA Channel8 transfer complete interrupt.
+ *     @arg DMA_INT_HTX8 DMA Channel8 half transfer interrupt.
+ *     @arg DMA_INT_ERR8 DMA Channel8 transfer error interrupt.
+ * @param DMAy DMA
+ *   This parameter can be one of the following values:
+ *     @arg DMA .
+ */
+void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_CLR_INT(DMA_IT));
+
+    /* Calculate the used DMA */
+    /* Clear the selected DMA interrupt pending bits */
+    DMAy->INTCLR = DMA_IT;
+}
+
+/**
+ * @brief  Set the DMA Channelx's remap request.
+ * @param DMA_REMAP specifies the DMA request.
+ *   This parameter can be set by the following values:
+ *     @arg DMA_REMAP_ADC1           DMA Request For ADC1.
+ *     @arg DMA_REMAP_USART1_TX      DMA Request For USART1_TX.
+ *     @arg DMA_REMAP_USART1_RX      DMA Request For USART1_RX.
+ *     @arg DMA_REMAP_USART2_TX      DMA Request For USART2_TX.
+ *     @arg DMA_REMAP_USART2_RX      DMA Request For USART2_RX.
+ *     @arg DMA_REMAP_USART3_TX      DMA Request For USART3_TX.
+ *     @arg DMA_REMAP_USART3_RX      DMA Request For USART3_RX.
+ *     @arg DMA_REMAP_UART4_TX       DMA Request For UART4_TX.
+ *     @arg DMA_REMAP_UART4_RX       DMA Request For UART4_RX.
+ *     @arg DMA_REMAP_UART5_TX       DMA Request For UART5_TX.
+ *     @arg DMA_REMAP_UART5_RX       DMA Request For UART5_RX.
+ *     @arg DMA_REMAP_LPUART_TX      DMA Request For LPUART_TX.
+ *     @arg DMA_REMAP_LPUART_RX      DMA Request For LPUART_RX.
+ *     @arg DMA_REMAP_SPI1_TX        DMA Request For SPI1_TX.
+ *     @arg DMA_REMAP_SPI1_RX        DMA Request For SPI1_RX.
+ *     @arg DMA_REMAP_SPI2_TX        DMA Request For SPI2_TX.
+ *     @arg DMA_REMAP_SPI2_RX        DMA Request For SPI2_RX.
+ *     @arg DMA_REMAP_I2C1_TX        DMA Request For I2C1_TX.
+ *     @arg DMA_REMAP_I2C1_RX        DMA Request For I2C1_RX.
+ *     @arg DMA_REMAP_I2C2_TX        DMA Request For I2C2_TX.
+ *     @arg DMA_REMAP_I2C2_RX        DMA Request For I2C2_RX.
+ *     @arg DMA_REMAP_DAC1           DMA Request For DAC1.
+ *     @arg DMA_REMAP_TIM1_CH1       DMA Request For TIM1_CH1.
+ *     @arg DMA_REMAP_TIM1_CH2       DMA Request For TIM1_CH2.
+ *     @arg DMA_REMAP_TIM1_CH3       DMA Request For TIM1_CH3.
+ *     @arg DMA_REMAP_TIM1_CH4       DMA Request For TIM1_CH4.
+ *     @arg DMA_REMAP_TIM1_COM       DMA Request For TIM1_COM.
+ *     @arg DMA_REMAP_TIM1_UP        DMA Request For TIM1_UP.
+ *     @arg DMA_REMAP_TIM1_TRIG      DMA Request For TIM1_TRIG.
+ *     @arg DMA_REMAP_TIM2_CH1       DMA Request For TIM2_CH1.
+ *     @arg DMA_REMAP_TIM2_CH2       DMA Request For TIM2_CH2.
+ *     @arg DMA_REMAP_TIM2_CH3       DMA Request For TIM2_CH3.
+ *     @arg DMA_REMAP_TIM2_CH4       DMA Request For TIM3_TRIG.
+ *     @arg DMA_REMAP_TIM2_UP        DMA Request For TIM2_UP.
+ *     @arg DMA_REMAP_TIM3_CH1       DMA Request For TIM3_CH1.
+ *     @arg DMA_REMAP_TIM3_CH3       DMA Request For TIM3_CH3.
+ *     @arg DMA_REMAP_TIM3_CH4       DMA Request For TIM3_CH4.
+ *     @arg DMA_REMAP_TIM3_UP        DMA Request For TIM3_UP.
+ *     @arg DMA_REMAP_TIM3_TRIG      DMA Request For TIM3_TRIG.
+ *     @arg DMA_REMAP_TIM4_CH1       DMA Request For TIM4_CH1.
+ *     @arg DMA_REMAP_TIM4_CH2       DMA Request For TIM4_CH2.
+ *     @arg DMA_REMAP_TIM4_CH3       DMA Request For TIM4_CH3.
+ *     @arg DMA_REMAP_TIM4_UP        DMA Request For TIM4_UP.
+ *     @arg DMA_REMAP_TIM5_CH1       DMA Request For TIM5_CH1.
+ *     @arg DMA_REMAP_TIM5_CH2       DMA Request For TIM5_CH2.
+ *     @arg DMA_REMAP_TIM5_CH3       DMA Request For TIM5_CH3.
+ *     @arg DMA_REMAP_TIM5_CH4       DMA Request For TIM5_CH4.
+ *     @arg DMA_REMAP_TIM5_UP        DMA Request For TIM5_UP.
+ *     @arg DMA_REMAP_TIM5_TRIG      DMA Request For TIM5_TRIG.
+ *     @arg DMA_REMAP_TIM6_UP        DMA Request For TIM6_UP.
+ *     @arg DMA_REMAP_TIM7_UP        DMA Request For TIM7_UP.
+ *     @arg DMA_REMAP_TIM8_CH1       DMA Request For TIM8_CH1.
+ *     @arg DMA_REMAP_TIM8_CH2       DMA Request For TIM8_CH2.
+ *     @arg DMA_REMAP_TIM8_CH3       DMA Request For TIM8_CH3.
+ *     @arg DMA_REMAP_TIM8_CH4       DMA Request For TIM8_CH4.
+ *     @arg DMA_REMAP_TIM8_COM       DMA Request For TIM8_COM.
+ *     @arg DMA_REMAP_TIM8_UP        DMA Request For TIM8_UP.
+ *     @arg DMA_REMAP_TIM8_TRIG      DMA Request For TIM8_TRIG.
+ *     @arg DMA_REMAP_TIM9_CH1       DMA Request For TIM9_CH1.
+ *     @arg DMA_REMAP_TIM9_TRIG      DMA Request For TIM9_TRIG.
+ *     @arg DMA_REMAP_TIM9_CH3       DMA Request For TIM9_CH3.
+ *     @arg DMA_REMAP_TIM9_CH4       DMA Request For TIM9_CH4.
+ *     @arg DMA_REMAP_TIM9_UP           DMA Request For TIM9_UP.
+ * @param DMAy DMA
+ *   This parameter can be one of the following values:
+ *     @arg DMA .
+ * @param DMAChx where x can be 1 to 8 for DMA to select the DMA Channel.
+ * @param Cmd new state of the DMA Channelx.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_REMAP(DMA_REMAP));
+
+    if (Cmd != DISABLE)
+    {
+        /* Calculate the used DMAy */
+        /* Set the selected DMAy remap request */
+        DMAChx->CHSEL = DMA_REMAP;
+    }
+    else
+    {
+        /* Clear DMAy remap */
+        DMAChx->CHSEL = 0;
+    }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_exti.c

@@ -0,0 +1,286 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_exti.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_exti.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @brief EXTI driver modules
+ * @{
+ */
+
+/** @addtogroup EXTI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Defines
+ * @{
+ */
+
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
+ */
+void EXTI_DeInit(void)
+{
+    EXTI->IMASK  = 0x00000000;
+    EXTI->EMASK  = 0x00000000;
+    EXTI->RT_CFG = 0x00000000;
+    EXTI->FT_CFG = 0x00000000;
+    EXTI->PEND   = 0x0FFFFFFF;
+}
+
+/**
+ * @brief  Initializes the EXTI peripheral according to the specified
+ *         parameters in the EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a EXTI_InitType structure
+ *         that contains the configuration information for the EXTI peripheral.
+ */
+void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct)
+{
+    uint32_t tmp = 0;
+
+    /* Check the parameters */
+    assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+    assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+    assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+    assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+    tmp = (uint32_t)EXTI_BASE;
+
+    if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+    {
+        /* Clear EXTI line configuration */
+        EXTI->IMASK &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->EMASK &= ~EXTI_InitStruct->EXTI_Line;
+
+        tmp += EXTI_InitStruct->EXTI_Mode;
+
+        *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line;
+
+        /* Clear Rising Falling edge configuration */
+        EXTI->RT_CFG &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->FT_CFG &= ~EXTI_InitStruct->EXTI_Line;
+
+        /* Select the trigger for the selected external interrupts */
+        if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+        {
+            /* Rising Falling edge */
+            EXTI->RT_CFG |= EXTI_InitStruct->EXTI_Line;
+            EXTI->FT_CFG |= EXTI_InitStruct->EXTI_Line;
+        }
+        else
+        {
+            tmp = (uint32_t)EXTI_BASE;
+            tmp += EXTI_InitStruct->EXTI_Trigger;
+
+            *(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line;
+        }
+    }
+    else
+    {
+        tmp += EXTI_InitStruct->EXTI_Mode;
+
+        /* Disable the selected external lines */
+        *(__IO uint32_t*)tmp &= ~EXTI_InitStruct->EXTI_Line;
+    }
+}
+
+/**
+ * @brief  Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct pointer to a EXTI_InitType structure which will
+ *         be initialized.
+ */
+void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct)
+{
+    EXTI_InitStruct->EXTI_Line    = EXTI_LINENONE;
+    EXTI_InitStruct->EXTI_Mode    = EXTI_Mode_Interrupt;
+    EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+    EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+ * @brief  Generates a Software interrupt.
+ * @param EXTI_Line specifies the EXTI lines to be enabled or disabled.
+ *   This parameter can be any combination of EXTI_Linex where x can be (0..27).
+ */
+void EXTI_TriggerSWInt(uint32_t EXTI_Line)
+{
+    /* Check the parameters */
+    assert_param(IS_EXTI_LINE(EXTI_Line));
+
+    EXTI->SWIE |= EXTI_Line;
+}
+
+/**
+ * @brief  Checks whether the specified EXTI line flag is set or not.
+ * @param EXTI_Line specifies the EXTI line flag to check.
+ *   This parameter can be:
+ *     @arg EXTI_Linex External interrupt line x where x(0..27)
+ * @return The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+    if ((EXTI->PEND & EXTI_Line) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the EXTI's line pending flags.
+ * @param EXTI_Line specifies the EXTI lines flags to clear.
+ *   This parameter can be any combination of EXTI_Linex where x can be (0..27).
+ */
+void EXTI_ClrStatusFlag(uint32_t EXTI_Line)
+{
+    /* Check the parameters */
+    assert_param(IS_EXTI_LINE(EXTI_Line));
+
+    EXTI->PEND = EXTI_Line;
+}
+
+/**
+ * @brief  Checks whether the specified EXTI line is asserted or not.
+ * @param EXTI_Line specifies the EXTI line to check.
+ *   This parameter can be:
+ *     @arg EXTI_Linex External interrupt line x where x(0..27)
+ * @return The new state of EXTI_Line (SET or RESET).
+ */
+INTStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+    INTStatus bitstatus   = RESET;
+    uint32_t enablestatus = 0;
+    /* Check the parameters */
+    assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+    enablestatus = EXTI->IMASK & EXTI_Line;
+    if (((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the EXTI's line pending bits.
+ * @param EXTI_Line specifies the EXTI lines to clear.
+ *   This parameter can be any combination of EXTI_Linex where x can be (0..27).
+ */
+void EXTI_ClrITPendBit(uint32_t EXTI_Line)
+{
+    /* Check the parameters */
+    assert_param(IS_EXTI_LINE(EXTI_Line));
+
+    EXTI->PEND = EXTI_Line;
+}
+
+/**
+ * @brief  Select one of EXTI inputs to the RTC TimeStamp event.
+ * @param EXTI_TSSEL_Line specifies the EXTI lines to select.
+ *   This parameter can be any combination of EXTI_TSSEL_Line where x can be (0..15).
+ */
+void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line)
+{
+    /* Check the parameters */
+    assert_param(IS_EXTI_TSSEL_LINE(EXTI_TSSEL_Line));
+
+    EXTI->TS_SEL &= EXTI_TSSEL_LINE_MASK;
+    EXTI->TS_SEL |= EXTI_TSSEL_Line;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_flash.c

@@ -0,0 +1,1565 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_flash.c
+ * @author Nations
+ * @version V1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_flash.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Defines
+ * @{
+ */
+
+/* Flash Access Control Register bits */
+#define AC_LATENCY_MSK ((uint32_t)0x000000F8)
+#define AC_PRFTBE_MSK  ((uint32_t)0xFFFFFFEF)
+#define AC_ICAHEN_MSK  ((uint32_t)0xFFFFFF7F)
+#define AC_LVMEN_MSK   ((uint32_t)0xFFFFFDFF)
+#define AC_SLMEN_MSK   ((uint32_t)0xFFFFF7FF)
+
+/* Flash Access Control Register bits */
+#define AC_PRFTBS_MSK  ((uint32_t)0x00000020)
+#define AC_ICAHRST_MSK ((uint32_t)0x00000040)
+#define AC_LVMF_MSK    ((uint32_t)0x00000100)
+#define AC_SLMF_MSK    ((uint32_t)0x00000400)
+
+/* Flash Control Register bits */
+#define CTRL_Set_PG       ((uint32_t)0x00000001)
+#define CTRL_Reset_PG     ((uint32_t)0x00003FFE)
+#define CTRL_Set_PER      ((uint32_t)0x00000002)
+#define CTRL_Reset_PER    ((uint32_t)0x00003FFD)
+#define CTRL_Set_MER      ((uint32_t)0x00000004)
+#define CTRL_Reset_MER    ((uint32_t)0x00003FFB)
+#define CTRL_Set_OPTPG    ((uint32_t)0x00000010)
+#define CTRL_Reset_OPTPG  ((uint32_t)0x00003FEF)
+#define CTRL_Set_OPTER    ((uint32_t)0x00000020)
+#define CTRL_Reset_OPTER  ((uint32_t)0x00003FDF)
+#define CTRL_Set_START    ((uint32_t)0x00000040)
+#define CTRL_Set_LOCK     ((uint32_t)0x00000080)
+#define CTRL_Reset_SMPSEL ((uint32_t)0x00003EFF)
+#define CTRL_SMPSEL_SMP1  ((uint32_t)0x00000000)
+#define CTRL_SMPSEL_SMP2  ((uint32_t)0x00000100)
+
+/* FLASH Mask */
+#define RDPRTL1_MSK  ((uint32_t)0x00000002)
+#define RDPRTL2_MSK  ((uint32_t)0x80000000)
+#define OBR_USER_MSK ((uint32_t)0x0000001C)
+#define WRP0_MSK     ((uint32_t)0x000000FF)
+#define WRP1_MSK     ((uint32_t)0x0000FF00)
+#define WRP2_MSK     ((uint32_t)0x00FF0000)
+#define WRP3_MSK     ((uint32_t)0xFF000000)
+
+/* FLASH Keys */
+#define L1_RDP_Key   ((uint32_t)0xFFFF00A5)
+#define RDP_USER_Key ((uint32_t)0xFFF000A5)
+#define L2_RDP_Key   ((uint32_t)0xFFFF33CC)
+#define FLASH_KEY1   ((uint32_t)0x45670123)
+#define FLASH_KEY2   ((uint32_t)0xCDEF89AB)
+
+/* Delay definition */
+#define EraseTimeout   ((uint32_t)0x000B0000)
+#define ProgramTimeout ((uint32_t)0x00002000)
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Sets the code latency value.
+ * @note   This function can be used for N32G43x devices.
+ * @param FLASH_Latency specifies the FLASH Latency value.
+ *   This parameter can be one of the following values:
+ *     @arg FLASH_LATENCY_0 FLASH Zero Latency cycle
+ *     @arg FLASH_LATENCY_1 FLASH One Latency cycle
+ *     @arg FLASH_LATENCY_2 FLASH Two Latency cycles
+ *     @arg FLASH_LATENCY_3 FLASH Three Latency cycles
+ */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+    uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+    /* Read the ACR register */
+    tmpregister = FLASH->AC;
+
+    /* Sets the Latency value */
+    tmpregister &= AC_LATENCY_MSK;
+    tmpregister |= FLASH_Latency;
+
+    /* Write the ACR register */
+    FLASH->AC = tmpregister;
+}
+
+/**
+ * @brief  Enables or disables the Prefetch Buffer.
+ * @note   This function can be used for N32G43x devices.
+ * @param FLASH_PrefetchBuf specifies the Prefetch buffer status.
+ *   This parameter can be one of the following values:
+ *     @arg FLASH_PrefetchBuf_EN FLASH Prefetch Buffer Enable
+ *     @arg FLASH_PrefetchBuf_DIS FLASH Prefetch Buffer Disable
+ */
+void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf)
+{
+    /* Check the parameters */
+    assert_param(IS_FLASH_PREFETCHBUF_STATE(FLASH_PrefetchBuf));
+
+    /* Enable or disable the Prefetch Buffer */
+    FLASH->AC &= AC_PRFTBE_MSK;
+    FLASH->AC |= FLASH_PrefetchBuf;
+}
+
+/**
+ * @brief  ICache Reset.
+ * @note   This function can be used for N32G43x devices.
+ */
+void FLASH_iCacheRST(void)
+{
+    /* ICache Reset */
+    FLASH->AC |= FLASH_AC_ICAHRST;
+}
+
+/**
+ * @brief  Enables or disables the iCache.
+ * @note   This function can be used for N32G43x devices.
+ * @param FLASH_iCache specifies the iCache status.
+ *   This parameter can be one of the following values:
+ *     @arg FLASH_iCache_EN  FLASH iCache Enable
+ *     @arg FLASH_iCache_DIS FLASH iCache Disable
+ */
+void FLASH_iCacheCmd(uint32_t FLASH_iCache)
+{
+    /* Check the parameters */
+    assert_param(IS_FLASH_ICACHE_STATE(FLASH_iCache));
+
+    /* Enable or disable the iCache */
+    FLASH->AC &= AC_ICAHEN_MSK;
+    FLASH->AC |= FLASH_iCache;
+}
+
+/**
+ * @brief  Enables or disables the Low Voltage Mode.
+ * @note   This function can be used for N32G43x devices.
+ * @param FLASH_LVM specifies the Low Voltage Mode status.
+ *   This parameter can be one of the following values:
+ *     @arg FLASH_LVM_EN  FLASH Low Voltage Mode Enable
+ *     @arg FLASH_LVM_DIS FLASH Low Voltage Mode Disable
+ */
+void FLASH_LowVoltageModeCmd(uint32_t FLASH_LVM)
+{
+    /* Check the parameters */
+    assert_param(IS_FLASH_LVM(FLASH_LVM));
+
+    /* Enable or disable LVM */
+    FLASH->AC &= AC_LVMEN_MSK;
+    FLASH->AC |= FLASH_LVM;
+}
+
+/**
+ * @brief  Checks whether the Low Voltage Mode status is SET or RESET.
+ * @note   This function can be used for N32G43x devices.
+ * @return Low Voltage Mode Status (SET or RESET).
+ */
+FlagStatus FLASH_GetLowVoltageModeSTS(void)
+{
+    FlagStatus bitstatus = RESET;
+
+    if ((FLASH->AC & AC_LVMF_MSK) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    /* Return the new state of FLASH Low Voltage Mode Status (SET or RESET) */
+    return bitstatus;
+}
+
+/**
+ * @brief  Enables or disables the FLASH Sleep Mode.
+ * @note   This function can be used for N32G43x devices.
+ * @param FLASH_SLM specifies the FLASH Sleep Mode status.
+ *   This parameter can be one of the following values:
+ *     @arg FLASH_SLM_EN  FLASH iCache Enable
+ *     @arg FLASH_SLM_DIS FLASH iCache Disable
+ */
+void FLASH_FLASHSleepModeCmd(uint32_t FLASH_SLM)
+{
+    /* Check the parameters */
+    assert_param(IS_FLASH_SLM(FLASH_SLM));
+
+    /* Enable or disable SLM */
+    FLASH->AC &= AC_SLMEN_MSK;
+    FLASH->AC |= FLASH_SLM;
+}
+
+/**
+ * @brief  Checks whether the FLASH Sleep Mode status is SET or RESET.
+ * @note   This function can be used for N32G43x devices.
+ * @return FLASH Sleep Mode Status (SET or RESET).
+ */
+FlagStatus FLASH_GetFLASHSleepModeSTS(void)
+{
+    FlagStatus bitstatus = RESET;
+
+    if ((FLASH->AC & AC_SLMF_MSK) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    /* Return the new state of FLASH Sleep Mode Status (SET or RESET) */
+    return bitstatus;
+}
+
+/**
+ * @brief  Checks whether the FLASH SMPSEL is SMP1 or SMP2.
+ * @note   This function can be used for N32G43x devices.
+ * @param FLASH_smpsel FLASH_SMPSEL_SMP1 or FLASH_SMPSEL_SMP2
+ */
+void FLASH_SetSMPSELStatus(uint32_t FLASH_smpsel)
+{
+    /* Check the parameters */
+    assert_param(IS_FLASH_SMPSEL_STATE(FLASH_smpsel));
+
+    /* SMP1 or SMP2 */
+    FLASH->CTRL &= CTRL_Reset_SMPSEL;
+    FLASH->CTRL |= FLASH_smpsel;
+}
+
+/**
+ * @brief  Configures the Internal High Speed oscillator
+ *         to program/erase FLASH.
+ * @note   This function can be used for N32G43x devices.
+ *         - For N32G43x devices this function enable HSI.
+ * @return FLASH_HSICLOCK (FLASH_HSICLOCK_ENABLE or FLASH_HSICLOCK_DISABLE).
+ */
+FLASH_HSICLOCK FLASH_ClockInit(void)
+{
+    bool HSIStatus = 0;
+    __IO uint32_t StartUpCounter = 0;
+    FLASH_HSICLOCK hsiclock_status = FLASH_HSICLOCK_ENABLE;
+
+    if ((RCC->CTRL & RCC_CTRL_HSIRDF) == RESET)
+    {
+        /* Enable HSI */
+        RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
+
+        /* Wait till HSI is ready and if Time out is reached exit */
+        do
+        {
+            HSIStatus = RCC->CTRL & RCC_CTRL_HSIRDF;
+            StartUpCounter++;
+        } while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
+
+        HSIStatus = ((RCC->CTRL & RCC_CTRL_HSIRDF) != RESET);
+        if (!HSIStatus)
+        {
+            hsiclock_status = FLASH_HSICLOCK_DISABLE;
+        }
+    }
+    return hsiclock_status;
+}
+
+/**
+ * @brief  Unlocks the FLASH Program Erase Controller.
+ * @note   This function can be used for N32G43x devices.
+ *         - For N32G43x devices this function unlocks Bank.
+ *           to FLASH_Unlock function..
+ */
+void FLASH_Unlock(void)
+{
+    /* Unlocks the FLASH Program Erase Controller */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+/**
+ * @brief  Locks the FLASH Program Erase Controller.
+ * @note   This function can be used for N32G43x devices.
+ *         - For N32G43x devices this function Locks Bank.
+ *           to FLASH_Lock function.
+ */
+void FLASH_Lock(void)
+{
+    /* Set the Lock Bit to lock the FLASH Program Erase Controller */
+    FLASH->CTRL |= CTRL_Set_LOCK;
+}
+
+/**
+ * @brief  Erases a specified FLASH page.
+ * @note   This function can be used for N32G43x devices.
+ * @param Page_Address The page address to be erased.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address)
+{
+    FLASH_STS status = FLASH_COMPL;
+    /* Check the parameters */
+    assert_param(IS_FLASH_ADDRESS(Page_Address));
+
+    /* Clears the FLASH's pending flags */
+    FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOpt(EraseTimeout);
+
+    if (status == FLASH_COMPL)
+    {
+        /* if the previous operation is completed, proceed to erase the page */
+        FLASH->CTRL |= CTRL_Set_PER;
+        FLASH->ADD = Page_Address;
+        FLASH->CTRL |= CTRL_Set_START;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOpt(EraseTimeout);
+
+        /* Disable the PER Bit */
+        FLASH->CTRL &= CTRL_Reset_PER;
+    }
+
+    /* Return the Erase Status */
+    return status;
+}
+
+/**
+ * @brief  Erases all FLASH pages.
+ * @note   This function can be used for all N32G43x devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_MassErase(void)
+{
+    FLASH_STS status = FLASH_COMPL;
+
+    /* Clears the FLASH's pending flags */
+    FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOpt(EraseTimeout);
+    if (status == FLASH_COMPL)
+    {
+        /* if the previous operation is completed, proceed to erase all pages */
+        FLASH->CTRL |= CTRL_Set_MER;
+        FLASH->CTRL |= CTRL_Set_START;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOpt(EraseTimeout);
+
+        /* Disable the MER Bit */
+        FLASH->CTRL &= CTRL_Reset_MER;
+    }
+
+    /* Return the Erase Status */
+    return status;
+}
+
+/**
+ * @brief  Erases the FLASH option bytes.
+ * @note   This functions erases all option bytes except the Read protection (RDP).
+ * @note   This function can be used for N32G43x devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EraseOB(void)
+{
+    uint32_t rdptmp = L1_RDP_Key;
+
+    FLASH_STS status = FLASH_COMPL;
+
+    /* Get the actual read protection L2 Option Byte value */
+    if (FLASH_GetReadOutProtectionL2STS() != RESET)
+    {
+        status = FLASH_ERR_RDP2;
+        return status;
+    }
+
+    /* Get the actual read protection Option Byte value */
+    if (FLASH_GetReadOutProtectionSTS() != RESET)
+    {
+        rdptmp = FLASH_USER_USER;
+    }
+
+    /* Clears the FLASH's pending flags */
+    FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOpt(EraseTimeout);
+
+    if (status == FLASH_COMPL)
+    {
+        /* Authorize the small information block programming */
+        FLASH->OPTKEY = FLASH_KEY1;
+        FLASH->OPTKEY = FLASH_KEY2;
+
+        /* if the previous operation is completed, proceed to erase the option bytes */
+        FLASH->CTRL |= CTRL_Set_OPTER;
+        FLASH->CTRL |= CTRL_Set_START;
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOpt(EraseTimeout);
+
+        if (status == FLASH_COMPL)
+        {
+            /* Clears the FLASH's pending flags */
+            FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+            /* if the erase operation is completed, disable the OPTER Bit */
+            FLASH->CTRL &= CTRL_Reset_OPTER;
+
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CTRL |= CTRL_Set_OPTPG;
+            /* Restore the last read protection Option Byte value */
+            OBT->USER_RDP = (uint32_t)rdptmp;
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+            if (status != FLASH_TIMEOUT)
+            {
+                /* if the program operation is completed, disable the OPTPG Bit */
+                FLASH->CTRL &= CTRL_Reset_OPTPG;
+            }
+        }
+        else
+        {
+            if (status != FLASH_TIMEOUT)
+            {
+                /* Disable the OPTER Bit */
+                FLASH->CTRL &= CTRL_Reset_OPTER;
+            }
+        }
+    }
+    /* Return the erase status */
+    return status;
+}
+
+
+/**
+ * @brief  Programs the FLASH User Option Byte:
+ *         RDP1 / IWDG_SW / RST_STOP2 / RST_STDBY / RST_PD / OB_Data0 / OB_Data1
+ *         WRP_Pages / RDP2 / nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0].
+ * @note   This function can be used for N32G43x devices.
+ * @param  OB_RDP1
+ *   This parameter can be one of the following values:
+ *     @arg OB_RDP1_ENABLE
+ *     @arg OB_RDP1_DISABLE
+ * @param  OB_IWDG Selects the IWDG mode
+ *   This parameter can be one of the following values:
+ *     @arg OB_IWDG_SW Software IWDG selected
+ *     @arg OB_IWDG_HW Hardware IWDG selected
+ * @param  OB_STOP2 Reset event when entering STOP2 mode.
+ *   This parameter can be one of the following values:
+ *     @arg OB_STOP2_NORST No reset generated when entering in STOP2
+ *     @arg OB_STOP2_RST Reset generated when entering in STOP2
+ * @param  OB_STDBY Reset event when entering Standby mode.
+ *   This parameter can be one of the following values:
+ *     @arg OB_STDBY_NORST No reset generated when entering in STANDBY
+ *     @arg OB_STDBY_RST Reset generated when entering in STANDBY
+ * @param  OB_PD Reset event when entering PowerDown mode.
+ *   This parameter can be one of the following values:
+ *     @arg OB_PD_NORST No reset generated when entering in PowerDown
+ *     @arg OB_PD_RST Reset generated when entering in PowerDown
+ * @param  OB_Data0
+ *   This parameter can be one of the following values:
+ *     @arg 0x00 ~ 0xFF
+ * @param  OB_Data1
+ *   This parameter can be one of the following values:
+ *     @arg 0x00 ~ 0xFF
+ * @param WRP_Pages specifies the address of the pages to be write protected.
+ *   This parameter can be:
+ *     @arg For @b N32G43x_devices: value between FLASH_WRP_Pages0to1 and
+ *       FLASH_WRP_Pages62to63 or FLASH_WRP_AllPages or (~FLASH_WRP_AllPages)
+ * @param  OB_RDP2
+ *   This parameter can be one of the following values:
+ *     @arg OB_RDP2_ENABLE
+ *     @arg OB_RDP2_DISABLE
+ * @param  OB2_nBOOT0
+ *   This parameter can be one of the following values:
+ *     @arg OB2_NBOOT0_SET Set nBOOT0
+ *     @arg OB2_NBOOT0_CLR Clear nBOOT0
+ * @param OB2_nBOOT1
+ *   This parameter can be one of the following values:
+ *     @arg OB2_NBOOT1_SET Set nBOOT1
+ *     @arg OB2_NBOOT1_CLR Clear nBOOT1
+ * @param OB2_nSWBOOT0
+ *   This parameter can be one of the following values:
+ *     @arg OB2_NSWBOOT0_SET Set nSWBOOT0
+ *     @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0
+* @param OB2_BOR_LEV[2:0]
+ *   This parameter can be one of the following values:
+ *     @arg OB2_BOR_LEV0
+ *     @arg OB2_BOR_LEV1
+ *     @arg OB2_BOR_LEV2
+ *     @arg OB2_BOR_LEV3
+ *     @arg OB2_BOR_LEV4
+ *     @arg OB2_BOR_LEV5
+ *     @arg OB2_BOR_LEV6
+ *     @arg OB2_BOR_LEV7
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigALLOptionByte(uint8_t OB_RDP1,    uint8_t OB_IWDG,    uint8_t OB_STOP2,
+                                    uint8_t OB_STDBY,   uint8_t OB_PD,      uint8_t OB_Data0,
+                                    uint8_t OB_Data1,   uint32_t WRP_Pages, uint8_t OB_RDP2,
+                                    uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1, uint8_t OB2_nSWBOOT0,
+                                    uint8_t OB2_BOR_LEV)
+{
+    uint32_t rdpuser_tmp, data0data1_tmp, wrp0wrp1_tmp, wrp2wrp3_tmp, rdp2user2_tmp;
+
+    FLASH_STS status = FLASH_COMPL;
+
+    /* Check the parameters */
+    assert_param(IS_OB_RDP1_SOURCE(OB_RDP1));
+    assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+    assert_param(IS_OB_STOP2_SOURCE(OB_STOP2));
+    assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+    assert_param(IS_OB_PD_SOURCE(OB_PD));
+    assert_param(IS_FLASH_WRP_PAGE(WRP_Pages));
+    assert_param(IS_OB_RDP2_SOURCE(OB_RDP2));
+    assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0));
+    assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1));
+    assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0));
+    assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV));
+
+    /* Get the actual read protection L2 Option Byte value */
+    if (FLASH_GetReadOutProtectionL2STS() != RESET)
+    {
+        status = FLASH_ERR_RDP2;
+        return status;
+    }
+
+    WRP_Pages      = (uint32_t)(~WRP_Pages);
+    rdpuser_tmp    = (((uint32_t)OB_RDP1) | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY | OB_PD)) << 16));
+    data0data1_tmp = (((uint32_t)OB_Data0) | (((uint32_t)OB_Data0) << 16));
+    wrp0wrp1_tmp   = ((WRP_Pages & FLASH_WRP0_WRP0) | ((WRP_Pages << 8) & FLASH_WRP1_WRP1));
+    wrp2wrp3_tmp   = (((WRP_Pages >> 16) & FLASH_WRP2_WRP2) | ((WRP_Pages >> 8) & FLASH_WRP3_WRP3));
+    rdp2user2_tmp  = (((uint32_t)OB_RDP2) | (((uint32_t)(OB2_nBOOT0 | OB2_nBOOT1 | OB2_nSWBOOT0 | OB2_BOR_LEV)) << 16));
+
+    /* Authorize the small information block programming */
+    FLASH->OPTKEY = FLASH_KEY1;
+    FLASH->OPTKEY = FLASH_KEY2;
+
+    /* Clears the FLASH's pending flags */
+    FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOpt(EraseTimeout);
+    if (status == FLASH_COMPL)
+    {
+        /* if the previous operation is completed, proceed to erase the option bytes */
+        FLASH->CTRL |= CTRL_Set_OPTER;
+        FLASH->CTRL |= CTRL_Set_START;
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOpt(EraseTimeout);
+
+        if (status == FLASH_COMPL)
+        {
+            /* Clears the FLASH's pending flags */
+            FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+            /* if the erase operation is completed, disable the OPTER Bit */
+            FLASH->CTRL &= CTRL_Reset_OPTER;
+
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CTRL |= CTRL_Set_OPTPG;
+
+            /* Program USER_RDP Option Byte value */
+            OBT->USER_RDP = (uint32_t)rdpuser_tmp;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+            if (status == FLASH_COMPL)
+            {
+                /* Clears the FLASH's pending flags */
+                FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+                /* Program Data1_Data0 Option Byte value */
+                OBT->Data1_Data0 = (uint32_t)data0data1_tmp;
+
+                /* Wait for last operation to be completed */
+                status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+                if (status == FLASH_COMPL)
+                {
+                    /* Clears the FLASH's pending flags */
+                    FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+                    /* Program WRP1_WRP0 Option Byte value */
+                    OBT->WRP1_WRP0 = (uint32_t)wrp0wrp1_tmp;
+
+                    /* Wait for last operation to be completed */
+                    status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+                    if (status == FLASH_COMPL)
+                    {
+                        /* Clears the FLASH's pending flags */
+                        FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+                        /* Program WRP3_WRP2 Option Byte value */
+                        OBT->WRP3_WRP2 = (uint32_t)wrp2wrp3_tmp;
+
+                        /* Wait for last operation to be completed */
+                        status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+                        if (status == FLASH_COMPL)
+                        {
+                            /* Clears the FLASH's pending flags */
+                            FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+                            /* Program USER2_RDP2 Option Byte value */
+                            OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp;
+
+                            /* Wait for last operation to be completed */
+                            status = FLASH_WaitForLastOpt(ProgramTimeout);
+                        }
+                    }
+                }
+            }
+
+            if (status != FLASH_TIMEOUT)
+            {
+                /* if the program operation is completed, disable the OPTPG Bit */
+                FLASH->CTRL &= CTRL_Reset_OPTPG;
+            }
+        }
+        else
+        {
+            if (status != FLASH_TIMEOUT)
+            {
+                /* Disable the OPTER Bit */
+                FLASH->CTRL &= CTRL_Reset_OPTER;
+            }
+        }
+    }
+
+    /* Return the Option Byte program Status */
+    return status;
+}
+
+/**
+ * @brief  Programs a word at a specified address.
+ * @note   This function can be used for N32G43x devices.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV, FLASH_ERR_ADD or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+    FLASH_STS status  = FLASH_COMPL;
+
+    /* Check the parameters */
+    assert_param(IS_FLASH_ADDRESS(Address));
+
+    if ((Address & (uint32_t)0x3) != 0)
+    {
+        /* The programming address is not a multiple of 4 */
+        status = FLASH_ERR_ADD;
+        return status;
+    }
+
+    /* Clears the FLASH's pending flags */
+    FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+    if (status == FLASH_COMPL)
+    {
+        /* if the previous operation is completed, proceed to program the new word */
+        FLASH->CTRL |= CTRL_Set_PG;
+
+        *(__IO uint32_t*)Address = (uint32_t)Data;
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+        /* Disable the PG Bit */
+        FLASH->CTRL &= CTRL_Reset_PG;
+    }
+
+    /* Return the Program Status */
+    return status;
+}
+
+/**
+ * @brief  Programs a half word at a specified Option Byte Data address.
+ * @note   This function can be used for N32G43x devices.
+ * @param Address specifies the address to be programmed.
+ *   This parameter can be 0x1FFFF804.
+ * @param Data specifies the data to be programmed(Data0 and Data1).
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data)
+{
+    FLASH_STS status = FLASH_COMPL;
+    /* Check the parameters */
+    assert_param(IS_OB_DATA_ADDRESS(Address));
+
+    /* Get the actual read protection L2 Option Byte value */
+    if (FLASH_GetReadOutProtectionL2STS() != RESET)
+    {
+        status = FLASH_ERR_RDP2;
+        return status;
+    }
+
+    /* Clears the FLASH's pending flags */
+    FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+    if (status == FLASH_COMPL)
+    {
+        /* Authorize the small information block programming */
+        FLASH->OPTKEY = FLASH_KEY1;
+        FLASH->OPTKEY = FLASH_KEY2;
+        /* Enables the Option Bytes Programming operation */
+        FLASH->CTRL |= CTRL_Set_OPTPG;
+        *(__IO uint32_t*)Address = (uint32_t)Data;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOpt(ProgramTimeout);
+        if (status != FLASH_TIMEOUT)
+        {
+            /* if the program operation is completed, disable the OPTPG Bit */
+            FLASH->CTRL &= CTRL_Reset_OPTPG;
+        }
+    }
+    /* Return the Option Byte Data Program Status */
+    return status;
+}
+
+/**
+ * @brief  Write protects the desired pages
+ * @note   This function can be used for N32G43x devices.
+ * @param FLASH_Pages specifies the address of the pages to be write protected.
+ *   This parameter can be:
+ *     @arg For @b N32G43x_devices: value between FLASH_WRP_Pages0to1 and
+ *       FLASH_WRP_Pages60to61 or FLASH_WRP_Pages62to63
+ *     @arg FLASH_WRP_AllPages
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages)
+{
+    uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+    FLASH_STS status = FLASH_COMPL;
+
+    /* Check the parameters */
+    assert_param(IS_FLASH_WRP_PAGE(FLASH_Pages));
+
+    /* Get the actual read protection L2 Option Byte value */
+    if (FLASH_GetReadOutProtectionL2STS() != RESET)
+    {
+        status = FLASH_ERR_RDP2;
+        return status;
+    }
+
+    FLASH_Pages = (uint32_t)(~FLASH_Pages);
+    WRP0_Data   = (uint16_t)(FLASH_Pages & WRP0_MSK);
+    WRP1_Data   = (uint16_t)((FLASH_Pages & WRP1_MSK) >> 8);
+    WRP2_Data   = (uint16_t)((FLASH_Pages & WRP2_MSK) >> 16);
+    WRP3_Data   = (uint16_t)((FLASH_Pages & WRP3_MSK) >> 24);
+
+    /* Clears the FLASH's pending flags */
+    FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+    if (status == FLASH_COMPL)
+    {
+        /* Authorizes the small information block programming */
+        FLASH->OPTKEY = FLASH_KEY1;
+        FLASH->OPTKEY = FLASH_KEY2;
+        FLASH->CTRL |= CTRL_Set_OPTPG;
+
+        if ((WRP0_Data != 0xFF) || (WRP1_Data != 0xFF))
+        {
+            OBT->WRP1_WRP0 = (((uint32_t)WRP0_Data) | (((uint32_t)WRP1_Data) << 16));
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOpt(ProgramTimeout);
+        }
+
+        if (((WRP2_Data != 0xFF) || (WRP3_Data != 0xFF)) && (status == FLASH_COMPL))
+        {
+            OBT->WRP3_WRP2 = (((uint32_t)WRP2_Data) | (((uint32_t)WRP3_Data) << 16));
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOpt(ProgramTimeout);
+        }
+
+        if (status != FLASH_TIMEOUT)
+        {
+            /* if the program operation is completed, disable the OPTPG Bit */
+            FLASH->CTRL &= CTRL_Reset_OPTPG;
+        }
+    }
+    /* Return the write protection operation Status */
+    return status;
+}
+
+/**
+ * @brief  Enables or disables the read out protection.
+ * @note   If the user has already programmed the other option bytes before calling
+ *   this function, he must re-program them since this function erases all option bytes.
+ * @note   This function can be used for N32G43x devices.
+ * @param Cmd new state of the ReadOut Protection.
+ *   This parameter can be: ENABLE or DISABLE.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd)
+{
+    uint32_t usertmp;
+    FLASH_STS status = FLASH_COMPL;
+
+    usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E);
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    /* Get the actual read protection L2 Option Byte value */
+    if (FLASH_GetReadOutProtectionL2STS() != RESET)
+    {
+        status = FLASH_ERR_RDP2;
+        return status;
+    }
+
+    /* Clears the FLASH's pending flags */
+    FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOpt(EraseTimeout);
+
+    if (status == FLASH_COMPL)
+    {
+        /* Authorizes the small information block programming */
+        FLASH->OPTKEY = FLASH_KEY1;
+        FLASH->OPTKEY = FLASH_KEY2;
+        FLASH->CTRL |= CTRL_Set_OPTER;
+        FLASH->CTRL |= CTRL_Set_START;
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOpt(EraseTimeout);
+        if (status == FLASH_COMPL)
+        {
+            /* Clears the FLASH's pending flags */
+            FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+            /* if the erase operation is completed, disable the OPTER Bit */
+            FLASH->CTRL &= CTRL_Reset_OPTER;
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CTRL |= CTRL_Set_OPTPG;
+            if (Cmd != DISABLE)
+            {
+                OBT->USER_RDP = (FLASH_USER_USER & usertmp);
+            }
+            else
+            {
+                OBT->USER_RDP = ((L1_RDP_Key & FLASH_RDP_RDP1) | usertmp);
+            }
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOpt(EraseTimeout);
+
+            if (status != FLASH_TIMEOUT)
+            {
+                /* if the program operation is completed, disable the OPTPG Bit */
+                FLASH->CTRL &= CTRL_Reset_OPTPG;
+            }
+        }
+        else
+        {
+            if (status != FLASH_TIMEOUT)
+            {
+                /* Disable the OPTER Bit */
+                FLASH->CTRL &= CTRL_Reset_OPTER;
+            }
+        }
+    }
+    /* Return the protection operation Status */
+    return status;
+}
+
+/**
+ * @brief  Enables or disables the read out protection L2.
+ * @note   If the user has already programmed the other option bytes before calling
+ *   this function, he must re-program them since this function erases all option bytes.
+ * @note   This function can be used for N32G43x devices.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void)
+{
+    uint32_t usertmp;
+    FLASH_STS status = FLASH_COMPL;
+
+    usertmp = ((OBR_USER_MSK & FLASH->OB) << 0x0E);
+
+    /* Get the actual read protection L1 Option Byte value */
+    if (FLASH_GetReadOutProtectionSTS() == RESET)
+    {
+        usertmp |= (L1_RDP_Key & FLASH_RDP_RDP1);
+    }
+    /* Get the actual read protection L2 Option Byte value */
+    if (FLASH_GetReadOutProtectionL2STS() != RESET)
+    {
+        status = FLASH_ERR_RDP2;
+        return status;
+    }
+
+    /* Clears the FLASH's pending flags */
+    FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOpt(EraseTimeout);
+
+    if (status == FLASH_COMPL)
+    {
+        /* Authorizes the small information block programming */
+        FLASH->OPTKEY = FLASH_KEY1;
+        FLASH->OPTKEY = FLASH_KEY2;
+        FLASH->CTRL |= CTRL_Set_OPTER;
+        FLASH->CTRL |= CTRL_Set_START;
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOpt(EraseTimeout);
+        if (status == FLASH_COMPL)
+        {
+            /* Clears the FLASH's pending flags */
+            FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+            /* if the erase operation is completed, disable the OPTER Bit */
+            FLASH->CTRL &= CTRL_Reset_OPTER;
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CTRL |= CTRL_Set_OPTPG;
+
+            OBT->USER_RDP = usertmp;
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOpt(EraseTimeout);
+
+            if (status == FLASH_COMPL)
+            {
+                /* Clears the FLASH's pending flags */
+                FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+                /* Enables the read out protection L2 */
+                OBT->USER2_RDP2 = L2_RDP_Key;
+
+                /* Wait for last operation to be completed */
+                status = FLASH_WaitForLastOpt(EraseTimeout);
+            }
+
+            if (status != FLASH_TIMEOUT)
+            {
+                /* if the program operation is completed, disable the OPTPG Bit */
+                FLASH->CTRL &= CTRL_Reset_OPTPG;
+            }
+        }
+        else
+        {
+            if (status != FLASH_TIMEOUT)
+            {
+                /* Disable the OPTER Bit */
+                FLASH->CTRL &= CTRL_Reset_OPTER;
+            }
+        }
+    }
+    /* Return the protection operation Status */
+    return status;
+}
+
+/**
+ * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @note   This function can be used for N32G43x devices.
+ * @param OB_IWDG Selects the IWDG mode
+ *   This parameter can be one of the following values:
+ *     @arg OB_IWDG_SW Software IWDG selected
+ *     @arg OB_IWDG_HW Hardware IWDG selected
+ * @param OB_STOP2 Reset event when entering STOP2 mode.
+ *   This parameter can be one of the following values:
+ *     @arg OB_STOP2_NORST No reset generated when entering in STOP2
+ *     @arg OB_STOP2_RST Reset generated when entering in STOP2
+ * @param OB_STDBY Reset event when entering Standby mode.
+ *   This parameter can be one of the following values:
+ *     @arg OB_STDBY_NORST No reset generated when entering in STANDBY
+ *     @arg OB_STDBY_RST Reset generated when entering in STANDBY
+ * @param OB_PD Reset event when entering PowerDown mode.
+ *   This parameter can be one of the following values:
+ *     @arg OB_PD_NORST No reset generated when entering in PowerDown
+ *     @arg OB_PD_RST Reset generated when entering in PowerDown
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigUserOB(uint8_t OB_IWDG, uint8_t OB_STOP2, uint8_t OB_STDBY, uint8_t OB_PD)
+{
+    uint32_t rdpuser_tmp = RDP_USER_Key;
+
+    FLASH_STS status = FLASH_COMPL;
+
+    /* Check the parameters */
+    assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+    assert_param(IS_OB_STOP2_SOURCE(OB_STOP2));
+    assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+    assert_param(IS_OB_PD_SOURCE(OB_PD));
+
+    /* Get the actual read protection L2 Option Byte value */
+    if (FLASH_GetReadOutProtectionL2STS() != RESET)
+    {
+        status = FLASH_ERR_RDP2;
+        return status;
+    }
+
+    /* Get the actual read protection Option Byte value */
+    if (FLASH_GetReadOutProtectionSTS() != RESET)
+    {
+        rdpuser_tmp = 0xFFF00000;
+    }
+
+    /* Authorize the small information block programming */
+    FLASH->OPTKEY = FLASH_KEY1;
+    FLASH->OPTKEY = FLASH_KEY2;
+
+    /* Clears the FLASH's pending flags */
+    FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOpt(EraseTimeout);
+
+    if (status == FLASH_COMPL)
+    {
+        /* if the previous operation is completed, proceed to erase the option bytes */
+        FLASH->CTRL |= CTRL_Set_OPTER;
+        FLASH->CTRL |= CTRL_Set_START;
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOpt(EraseTimeout);
+
+        if (status == FLASH_COMPL)
+        {
+            /* Clears the FLASH's pending flags */
+            FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+            /* if the erase operation is completed, disable the OPTER Bit */
+            FLASH->CTRL &= CTRL_Reset_OPTER;
+
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CTRL |= CTRL_Set_OPTPG;
+            /* Restore the last read protection Option Byte value */
+            OBT->USER_RDP =
+                (uint32_t)rdpuser_tmp
+                | (((uint32_t)(OB_IWDG | OB_STOP2 | OB_STDBY | OB_PD)) << 16);
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+            if (status != FLASH_TIMEOUT)
+            {
+                /* if the program operation is completed, disable the OPTPG Bit */
+                FLASH->CTRL &= CTRL_Reset_OPTPG;
+            }
+        }
+        else
+        {
+            if (status != FLASH_TIMEOUT)
+            {
+                /* Disable the OPTER Bit */
+                FLASH->CTRL &= CTRL_Reset_OPTER;
+            }
+        }
+    }
+
+    /* Return the Option Byte program Status */
+    return status;
+}
+
+/**
+ * @brief  Programs the FLASH User Option Byte: nBOOT0 / nBOOT1 / nSWBOOT0 / BOR_LEV[2:0].
+ * @note   This function can be used for N32G43x devices.
+ * @param OB2_nBOOT0
+ *   This parameter can be one of the following values:
+ *     @arg OB2_NBOOT0_SET Set nBOOT0
+ *     @arg OB2_NBOOT0_CLR Clear nBOOT0
+ * @param OB2_nBOOT1
+ *   This parameter can be one of the following values:
+ *     @arg OB2_NBOOT1_SET Set nBOOT1
+ *     @arg OB2_NBOOT1_CLR Clear nBOOT1
+ * @param OB2_nSWBOOT0
+ *   This parameter can be one of the following values:
+ *     @arg OB2_NSWBOOT0_SET Set nSWBOOT0
+ *     @arg OB2_NSWBOOT0_CLR Clear nSWBOOT0
+* @param OB2_BOR_LEV[2:0]
+ *   This parameter can be one of the following values:
+ *     @arg OB2_BOR_LEV0
+ *     @arg OB2_BOR_LEV1
+ *     @arg OB2_BOR_LEV2
+ *     @arg OB2_BOR_LEV3
+ *     @arg OB2_BOR_LEV4
+ *     @arg OB2_BOR_LEV5
+ *     @arg OB2_BOR_LEV6
+ *     @arg OB2_BOR_LEV7
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV, FLASH_ERR_RDP2 or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_ConfigUserOB2(uint8_t OB2_nBOOT0, uint8_t OB2_nBOOT1,
+                              uint8_t OB2_nSWBOOT0, uint8_t OB2_BOR_LEV)
+{
+    uint32_t rdpuser_tmp = (RDP_USER_Key | FLASH_USER_USER);
+    uint32_t rdp2user2_tmp = 0xFF00FFFF;
+
+    FLASH_STS status = FLASH_COMPL;
+
+    /* Check the parameters */
+    assert_param(IS_OB2_NBOOT0_SOURCE(OB2_nBOOT0));
+    assert_param(IS_OB2_NBOOT1_SOURCE(OB2_nBOOT1));
+    assert_param(IS_OB2_NSWBOOT0_SOURCE(OB2_nSWBOOT0));
+    assert_param(IS_OB2_BOR_LEV_SOURCE(OB2_BOR_LEV));
+
+    /* Get the actual read protection L2 Option Byte value */
+    if (FLASH_GetReadOutProtectionL2STS() != RESET)
+    {
+        status = FLASH_ERR_RDP2;
+        return status;
+    }
+
+    /* Get the actual read protection Option Byte value */
+    if (FLASH_GetReadOutProtectionSTS() != RESET)
+    {
+        rdpuser_tmp = 0xFFFF0000;
+    }
+
+    /* Authorize the small information block programming */
+    FLASH->OPTKEY = FLASH_KEY1;
+    FLASH->OPTKEY = FLASH_KEY2;
+
+    /* Clears the FLASH's pending flags */
+    FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOpt(EraseTimeout);
+
+    if (status == FLASH_COMPL)
+    {
+        /* if the previous operation is completed, proceed to erase the option bytes */
+        FLASH->CTRL |= CTRL_Set_OPTER;
+        FLASH->CTRL |= CTRL_Set_START;
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOpt(EraseTimeout);
+
+        if (status == FLASH_COMPL)
+        {
+            /* Clears the FLASH's pending flags */
+            FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+            /* if the erase operation is completed, disable the OPTER Bit */
+            FLASH->CTRL &= CTRL_Reset_OPTER;
+
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CTRL |= CTRL_Set_OPTPG;
+
+            /* Restore the last RDP1 Option Byte value */
+            OBT->USER_RDP = (uint32_t)rdpuser_tmp;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOpt(ProgramTimeout);
+
+            if (status == FLASH_COMPL)
+            {
+                /* Clears the FLASH's pending flags */
+                FLASH_ClearFlag(FLASH_STS_CLRFLAG);
+
+                /* Restore the last RDP2 Option Byte value */
+                OBT->USER2_RDP2 = (uint32_t)rdp2user2_tmp | (((uint32_t)(OB2_nBOOT0)   | (uint32_t)(OB2_nBOOT1)  \
+                                                         | (uint32_t)(OB2_nSWBOOT0) | (uint32_t)(OB2_BOR_LEV)) << 16);
+
+                /* Wait for last operation to be completed */
+                status = FLASH_WaitForLastOpt(ProgramTimeout);
+            }
+
+            if (status != FLASH_TIMEOUT)
+            {
+                /* if the program operation is completed, disable the OPTPG Bit */
+                FLASH->CTRL &= CTRL_Reset_OPTPG;
+            }
+        }
+        else
+        {
+            if (status != FLASH_TIMEOUT)
+            {
+                /* Disable the OPTER Bit */
+                FLASH->CTRL &= CTRL_Reset_OPTER;
+            }
+        }
+    }
+
+    /* Return the Option Byte program Status */
+    return status;
+}
+
+/**
+ * @brief  Returns the FLASH User Option Bytes values.
+ * @note   This function can be used for N32G43x devices.
+ * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ *         and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOB(void)
+{
+    /* Return the User Option Byte */
+    return (uint32_t)(FLASH->OB >> 2);
+}
+
+/**
+ * @brief  Returns the FLASH Write Protection Option Bytes Register value.
+ * @note   This function can be used for N32G43x devices.
+ * @return The FLASH Write Protection  Option Bytes Register value
+ */
+uint32_t FLASH_GetWriteProtectionOB(void)
+{
+    /* Return the Flash write protection Register value */
+    return (uint32_t)(FLASH->WRP);
+}
+
+/**
+ * @brief  Checks whether the FLASH Read Out Protection Status is set or not.
+ * @note   This function can be used for N32G43x devices.
+ * @return FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionSTS(void)
+{
+    FlagStatus readoutstatus = RESET;
+    if ((FLASH->OB & RDPRTL1_MSK) != (uint32_t)RESET)
+    {
+        readoutstatus = SET;
+    }
+    else
+    {
+        readoutstatus = RESET;
+    }
+    return readoutstatus;
+}
+
+/**
+ * @brief  Checks whether the FLASH Read Out Protection L2 Status is set or not.
+ * @note   This function can be used for N32G43x devices.
+ * @return FLASH ReadOut Protection L2 Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionL2STS(void)
+{
+    FlagStatus readoutstatus = RESET;
+    if ((FLASH->OB & RDPRTL2_MSK) != (uint32_t)RESET)
+    {
+        readoutstatus = SET;
+    }
+    else
+    {
+        readoutstatus = RESET;
+    }
+    return readoutstatus;
+}
+
+/**
+ * @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
+ * @note   This function can be used for N32G43x devices.
+ * @return FLASH Prefetch Buffer Status (SET or RESET).
+ */
+FlagStatus FLASH_GetPrefetchBufSTS(void)
+{
+    FlagStatus bitstatus = RESET;
+
+    if ((FLASH->AC & AC_PRFTBS_MSK) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+    return bitstatus;
+}
+
+/**
+ * @brief  Checks whether the FLASH SMPSEL is SMP1 or SMP2.
+ * @note   This function can be used for N32G43x devices.
+ * @return FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2).
+ */
+FLASH_SMPSEL FLASH_GetSMPSELStatus(void)
+{
+    FLASH_SMPSEL bitstatus = FLASH_SMP1;
+
+    if ((FLASH->CTRL & CTRL_Reset_SMPSEL) != (uint32_t)FLASH_SMP1)
+    {
+        bitstatus = FLASH_SMP2;
+    }
+    else
+    {
+        bitstatus = FLASH_SMP1;
+    }
+    /* Return the new state of FLASH SMPSEL (FLASH_SMP1 or FLASH_SMP2) */
+    return bitstatus;
+}
+
+/**
+ * @brief  Enables or disables the specified FLASH interrupts.
+ * @note   This function can be used for N32G43x devices.
+ * @param FLASH_INT specifies the FLASH interrupt sources to be enabled or disabled.
+ *   This parameter can be any combination of the following values:
+ *     @arg FLASH_IT_ERROR FLASH Error Interrupt
+ *     @arg FLASH_INT_FERR EVERR PVERR Interrupt
+ *     @arg FLASH_INT_EOP FLASH end of operation Interrupt
+ * @param Cmd new state of the specified Flash interrupts.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FLASH_INT(FLASH_INT));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the interrupt sources */
+        FLASH->CTRL |= FLASH_INT;
+    }
+    else
+    {
+        /* Disable the interrupt sources */
+        FLASH->CTRL &= ~(uint32_t)FLASH_INT;
+    }
+}
+
+/**
+ * @brief  Checks whether the specified FLASH flag is set or not.
+ * @note   This function can be used for N32G43x devices.
+ * @param FLASH_FLAG specifies the FLASH flag to check.
+ *   This parameter can be one of the following values:
+ *     @arg FLASH_FLAG_BUSY FLASH Busy flag
+ *     @arg FLASH_FLAG_PGERR FLASH Program error flag
+ *     @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag
+ *     @arg FLASH_FLAG_WRPERR FLASH Write protected error flag
+ *     @arg FLASH_FLAG_EOP FLASH End of Operation flag
+ *     @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag
+ *     @arg FLASH_FLAG_OBERR FLASH Option Byte error flag
+ * @return The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
+    if (FLASH_FLAG == FLASH_FLAG_OBERR)
+    {
+        if ((FLASH->OB & FLASH_FLAG_OBERR) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    else
+    {
+        if ((FLASH->STS & FLASH_FLAG) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+
+    /* Return the new state of FLASH_FLAG (SET or RESET) */
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the FLASH's pending flags.
+ * @note   This function can be used for N32G43x devices.
+ * @param FLASH_FLAG specifies the FLASH flags to clear.
+ *   This parameter can be any combination of the following values:
+ *     @arg FLASH_FLAG_PGERR FLASH Program error flag
+ *     @arg FLASH_FLAG_PVERR FLASH Program Verify ERROR flag
+ *     @arg FLASH_FLAG_WRPERR FLASH Write protected error flag
+ *     @arg FLASH_FLAG_EOP FLASH End of Operation flag
+ *     @arg FLASH_FLAG_EVERR FLASH Erase Verify ERROR flag
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
+
+    /* Clear the flags */
+    FLASH->STS |= FLASH_FLAG;
+}
+
+/**
+ * @brief  Returns the FLASH Status.
+ * @note   This function can be used for N32G43x devices, it is equivalent
+ *         to FLASH_GetBank1Status function.
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_GetSTS(void)
+{
+    FLASH_STS flashstatus = FLASH_COMPL;
+
+    if ((FLASH->STS & FLASH_FLAG_BUSY) == FLASH_FLAG_BUSY)
+    {
+        flashstatus = FLASH_BUSY;
+    }
+    else
+    {
+        if ((FLASH->STS & FLASH_FLAG_PGERR) != 0)
+        {
+            flashstatus = FLASH_ERR_PG;
+        }
+        else
+        {
+            if ((FLASH->STS & FLASH_FLAG_PVERR) != 0)
+            {
+                flashstatus = FLASH_ERR_PV;
+            }
+            else
+            {
+                if ((FLASH->STS & FLASH_FLAG_WRPERR) != 0)
+                {
+                    flashstatus = FLASH_ERR_WRP;
+                }
+                else
+                {
+                    if ((FLASH->STS & FLASH_FLAG_EVERR) != 0)
+                    {
+                        flashstatus = FLASH_ERR_EV;
+                    }
+                    else
+                    {
+                        flashstatus = FLASH_COMPL;
+                    }
+                }
+            }
+        }
+    }
+
+    /* Return the Flash Status */
+    return flashstatus;
+}
+
+/**
+ * @brief  Waits for a Flash operation to complete or a TIMEOUT to occur.
+ * @note   This function can be used for N32G43x devices,
+ *         it is equivalent to FLASH_WaitForLastBank1Operation..
+ * @param Timeout FLASH programming Timeout
+ * @return FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERR_RDKEY,
+ *         FLASH_ERR_PG, FLASH_ERR_PV, FLASH_ERR_WRP, FLASH_COMPL,
+ *         FLASH_ERR_EV or FLASH_TIMEOUT.
+ */
+FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout)
+{
+    FLASH_STS status = FLASH_COMPL;
+
+    /* Check for the Flash Status */
+    status = FLASH_GetSTS();
+    /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+    while ((status == FLASH_BUSY) && (Timeout != 0x00))
+    {
+        status = FLASH_GetSTS();
+        Timeout--;
+    }
+    if (Timeout == 0x00)
+    {
+        status = FLASH_TIMEOUT;
+    }
+    /* Return the operation status */
+    return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_gpio.c

@@ -0,0 +1,768 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_gpio.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_gpio.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+/** @addtogroup GPIO_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
+
+/* --- Event control register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET    (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber ((uint8_t)0x07)
+#define EVCR_EVOE_BB   (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+#define GPIO_MODE                       ((uint32_t)0x00000003)
+#define EXTI_MODE                       ((uint32_t)0x10000000)
+#define GPIO_MODE_IT                    ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT                   ((uint32_t)0x00020000)
+#define RISING_EDGE                     ((uint32_t)0x00100000)
+#define FALLING_EDGE                    ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE                ((uint32_t)0x00000010)
+#define GPIO_PULLUP_PULLDOWN            ((uint32_t)0x00000300)
+#define GPIO_NUMBER                     ((uint32_t)16)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ */
+void GPIO_DeInit(GPIO_Module* GPIOx)
+{
+
+    uint32_t position = 0x00U;
+    uint32_t iocurrent = 0x00U;
+    uint32_t tmp = 0x00U;
+    uint32_t GPIO_Pin = GPIO_PIN_ALL;
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    /* Check the parameters */
+    assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
+
+    if (GPIOx == GPIOA)
+    {
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, ENABLE);
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, DISABLE);
+    }
+    else if (GPIOx == GPIOB)
+    {
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, ENABLE);
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, DISABLE);
+    }
+    else if (GPIOx == GPIOC)
+    {
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, ENABLE);
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, DISABLE);
+    }
+    else if (GPIOx == GPIOD)
+    {
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, ENABLE);
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, DISABLE);
+    }
+    else
+    {
+        return;
+    }
+
+    /* Configure the port pins */
+    while ((GPIO_Pin >> position) != 0)
+    {
+        /* Get the IO position */
+        iocurrent = (GPIO_Pin) & ((uint32_t)0x01 << position);
+
+        if (iocurrent)
+        {
+            /*------------------------- EXTI Mode Configuration --------------------*/
+            /* Clear the External Interrupt or Event for the current IO */
+            tmp = AFIO->EXTI_CFG[position>>2];
+            tmp &= (0x0FuL << (4u*(position & 0x03u)));
+            if (tmp == (GPIO_GET_INDEX(GPIOx)<<(4u * (position & 0x03u))))
+            {
+                /* Clear EXTI line configuration */
+                EXTI->IMASK &= ~(iocurrent);
+                EXTI->EMASK &= ~(iocurrent);
+
+                /* Clear Rising Falling edge configuration */
+                EXTI->RT_CFG &= ~(iocurrent);
+                EXTI->FT_CFG &= ~(iocurrent);
+                tmp = 0x0FuL << (4u * (position & 0x03u));
+                AFIO->EXTI_CFG[position >> 2u] &= ~tmp;
+            }
+
+
+            /*------------------------- GPIO Mode Configuration --------------------*/
+            /* Configure IO Direction in Input Floting Mode */
+            GPIOx->PMODE &= ~(GPIO_PMODE0_Msk << (position * 2U));
+
+            /* Configure the default Alternate Function in current IO */
+            if (position & 0x08)
+                GPIOx->AFH |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U));
+            else
+                GPIOx->AFL |= ((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U));
+
+            /* Configure the default value IO Output Type */
+            GPIOx->POTYPE  &= ~(GPIO_POTYPE_POT_0 << position) ;
+
+            /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
+            GPIOx->PUPD &= ~(GPIO_PUPD0_Msk << (position * 2U));
+
+        }
+     position++;
+    }
+}
+
+
+/**
+ * @brief  Deinitializes the Alternate Functions (remap, event control
+ *   and EXTI configuration) registers to their default reset values.
+ */
+void GPIO_AFIOInitDefault(void)
+{
+    RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, ENABLE);
+    RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, DISABLE);
+}
+
+/**
+ * @brief  Initializes the GPIOx peripheral according to the specified
+ *         parameters in the GPIO_InitStruct.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param GPIO_InitStruct pointer to a GPIO_InitType structure that
+ *         contains the configuration information for the specified GPIO peripheral.
+ */
+
+void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType * GPIO_InitStruct)
+{
+    uint32_t pinpos = 0x00U;
+    uint32_t tmp = 0x00U,tmpregister=0x00U;
+    uint32_t position = 0x00U;
+    uint32_t iocurrent = 0x00U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+    assert_param(IS_GPIO_PIN(GPIO_InitStruct->Pin));
+    assert_param(IS_GPIO_PULL(GPIO_InitStruct->GPIO_Pull));
+    assert_param(IS_GPIO_SLEW_RATE(GPIO_InitStruct->GPIO_Slew_Rate));
+
+    /*---------------------------- GPIO Mode Configuration -----------------------*/
+
+    /*---------------------------- GPIO PL_CFG Configuration ------------------------*/
+
+    while (((GPIO_InitStruct->Pin)>>position) != 0)
+    {
+        iocurrent = (GPIO_InitStruct->Pin)&(1U<<position);
+        if (iocurrent)
+        {
+            pinpos = position * 2U;
+
+            if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Input) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Analog))
+            {
+                /* Check if the Alternate function is compliant with the GPIO in use */
+                assert_param(IS_GPIO_AF(GPIO_InitStruct->GPIO_Alternate));
+                /* Configure Alternate function mapped with the current IO */
+                if (position & 0x08)
+                {
+                    tmp = GPIOx->AFH;
+                    tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U));
+                    tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ;
+                    GPIOx->AFH = tmp;
+                }
+                else
+                {
+                    tmp = GPIOx->AFL;
+                    tmp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ;
+                    tmp |= ((uint32_t)(GPIO_InitStruct->GPIO_Alternate) << ((uint32_t)(position & (uint32_t)0x07) * 4U)) ;
+                    GPIOx->AFL = tmp;
+                }
+            }
+            /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+            tmpregister = GPIOx->PMODE;
+            tmp = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+            tmpregister &= ~(((uint32_t)0x03) << pinpos);
+            tmpregister |=( tmp << pinpos);
+            GPIOx->PMODE = tmpregister;
+
+            /* Configure pull-down mode */
+            tmpregister = GPIOx->PUPD;
+            tmp = (GPIO_InitStruct->GPIO_Pull & (uint32_t)0x03);
+            tmpregister &=~(((uint32_t)0x03) << pinpos);
+            tmpregister |= (tmp <<pinpos);
+            GPIOx->PUPD = tmpregister;
+
+
+            /* Configure driver current*/
+            if ((GPIO_InitStruct->GPIO_Mode & GPIO_MODE) && (GPIO_InitStruct->GPIO_Mode != GPIO_Mode_Analog))
+            {
+                assert_param(IS_GPIO_CURRENT(GPIO_InitStruct->GPIO_Current));
+                tmpregister = GPIOx->DS;
+                tmp = (GPIO_InitStruct->GPIO_Current &((uint32_t)0x03));
+                tmpregister &= ~(((uint32_t)0x03) << pinpos);
+                tmpregister |= (tmp<<pinpos);
+                GPIOx->DS = tmpregister;
+            }
+            /* Configure slew rate*/
+                tmp = GPIOx->SR;
+                tmp &=((uint32_t)(~((uint16_t)0x01 << position)));
+                tmp |= (GPIO_InitStruct->GPIO_Slew_Rate &((uint32_t)0x01))<<position;
+                GPIOx->SR = tmp;
+            /*Configure Set/Reset register*/
+            if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Down)
+            {
+                GPIOx->PBC |= (((uint32_t)0x01) << position);
+            }
+            else
+            {
+                /* Set the corresponding POD bit */
+                if (GPIO_InitStruct->GPIO_Pull == GPIO_Pull_Up)
+                {
+                    GPIOx->PBSC |= (((uint32_t)0x01) << position);
+                }
+            }
+
+            /* In case of Output or Alternate function mode selection */
+            if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_PP) ||
+             (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_Out_OD) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF_OD))
+            {
+                /* Configure the IO Output Type */
+
+                tmp= GPIOx->POTYPE;
+                tmp &= ~(((uint32_t)0x01U) << position) ;
+                tmp |= (((GPIO_InitStruct->GPIO_Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+                GPIOx->POTYPE = tmp;
+            }
+            /*--------------------- EXTI Mode Configuration ------------------------*/
+            /* Configure the External Interrupt or event for the current IO */
+            if (GPIO_InitStruct->GPIO_Mode & EXTI_MODE)
+            {
+                /* Clear EXTI line configuration */
+                tmp = EXTI->IMASK;
+                tmp &= ~((uint32_t)0x01<<position);
+                if ((GPIO_InitStruct->GPIO_Mode & GPIO_MODE_IT)== GPIO_MODE_IT)
+                {
+                    tmp |= ((uint32_t)0x01 << position);
+                }
+                EXTI->IMASK = tmp;
+
+                tmp = EXTI->EMASK;
+                tmp &= ~((uint32_t)0x01<<position);
+                if ((GPIO_InitStruct->GPIO_Mode & GPIO_MODE_EVT)== GPIO_MODE_EVT)
+                {
+                    tmp |= ((uint32_t)0x01 << position);
+                }
+                EXTI->EMASK = tmp;
+
+                /* Clear Rising Falling edge configuration */
+
+                tmp = EXTI->RT_CFG;
+                tmp &= ~((uint32_t)0x01<<position);
+                if ((GPIO_InitStruct->GPIO_Mode & RISING_EDGE)== RISING_EDGE)
+                {
+                    tmp |= ((uint32_t)0x01 << position);
+                }
+                EXTI->RT_CFG = tmp;
+
+                tmp = EXTI->FT_CFG;
+                tmp &= ~((uint32_t)0x01<<position);
+                if ((GPIO_InitStruct->GPIO_Mode & FALLING_EDGE)== FALLING_EDGE)
+                {
+                    tmp |= ((uint32_t)0x01 << position);
+                }
+                EXTI->FT_CFG = tmp;
+            }
+        }
+        position++;
+    }
+}
+
+/**
+ * @brief  Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct pointer to a GPIO_InitType structure which will
+ *         be initialized.
+ */
+void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct)
+{
+    /* Reset GPIO init structure parameters values */
+    GPIO_InitStruct->Pin        = GPIO_PIN_ALL;
+    GPIO_InitStruct->GPIO_Slew_Rate = GPIO_Slew_Rate_High;
+    GPIO_InitStruct->GPIO_Mode  = GPIO_Mode_Input;
+    GPIO_InitStruct->GPIO_Alternate = GPIO_NO_AF;
+    GPIO_InitStruct->GPIO_Pull = GPIO_No_Pull;
+    GPIO_InitStruct->GPIO_Current = GPIO_DC_2mA;
+}
+
+/**
+ * @brief  Reads the specified input port pin.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to read.
+ *   This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @return The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin)
+{
+    uint8_t bitstatus = 0x00;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GET_GPIO_PIN(Pin));
+
+    if ((GPIOx->PID & Pin) != (uint32_t)Bit_RESET)
+    {
+        bitstatus = (uint8_t)Bit_SET;
+    }
+    else
+    {
+        bitstatus = (uint8_t)Bit_RESET;
+    }
+    return bitstatus;
+}
+
+/**
+ * @brief  Reads the specified GPIO input data port.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @return GPIO input data port value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+    return ((uint16_t)GPIOx->PID);
+}
+
+/**
+ * @brief  Reads the specified output data port bit.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to read.
+ *   This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @return The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin)
+{
+    uint8_t bitstatus = 0x00;
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GET_GPIO_PIN(Pin));
+
+    if ((GPIOx->POD & Pin) != (uint32_t)Bit_RESET)
+    {
+        bitstatus = (uint8_t)Bit_SET;
+    }
+    else
+    {
+        bitstatus = (uint8_t)Bit_RESET;
+    }
+    return bitstatus;
+}
+
+/**
+ * @brief  Reads the specified GPIO output data port.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @return GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+    return ((uint16_t)GPIOx->POD);
+}
+
+/**
+ * @brief  Sets the selected data port bits.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bits to be written.
+ *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+
+    GPIOx->PBSC = Pin;
+}
+void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    // assert_param(IS_GPIO_PIN(Pin));
+
+    GPIOx->PBSC = Pin;
+}
+
+/**
+ * @brief  Clears the selected data port bits.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bits to be written.
+ *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+
+    GPIOx->PBC = Pin;
+}
+
+/**
+ * @brief  Sets or clears the selected data port bit.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to be written.
+ *   This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ * @param BitCmd specifies the value to be written to the selected bit.
+ *   This parameter can be one of the Bit_OperateType enum values:
+ *     @arg Bit_RESET to clear the port pin
+ *     @arg Bit_SET to set the port pin
+ */
+void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GET_GPIO_PIN(Pin));
+    assert_param(IS_GPIO_BIT_OPERATE(BitCmd));
+
+    if (BitCmd != Bit_RESET)
+    {
+        GPIOx->PBSC = Pin;
+    }
+    else
+    {
+        GPIOx->PBC = Pin;
+    }
+}
+
+/**
+ * @brief  Writes data to the specified GPIO data port.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param PortVal specifies the value to be written to the port output data register.
+ */
+void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+    GPIOx->POD = PortVal;
+}
+
+/**
+ * @brief  Locks GPIO Pins configuration registers.
+ * @param GPIOx where x can be (A..D) to select the GPIO peripheral.
+ * @param Pin specifies the port bit to be written.
+ *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ */
+void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin)
+{
+    uint32_t tmp = 0x00010000;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(Pin));
+
+    tmp |= Pin;
+    /* Set LCKK bit */
+    GPIOx->PLOCK = tmp;
+    /* Reset LCKK bit */
+    GPIOx->PLOCK = Pin;
+    /* Set LCKK bit */
+    GPIOx->PLOCK = tmp;
+    /* Read LCKK bit*/
+    tmp = GPIOx->PLOCK;
+    /* Read LCKK bit*/
+    tmp = GPIOx->PLOCK;
+}
+
+
+
+/**
+ * @brief  Changes the mapping of the specified pin.
+ * @param PortSource selects the GPIO port to be used.
+ * @param PinSource specifies the pin for the remaping.
+ *   This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @param AlternateFunction specifies the alternate function for the remaping.
+ */
+void GPIO_ConfigPinRemap(uint8_t PortSource, uint8_t PinSource, uint32_t AlternateFunction)
+{
+    uint32_t tmp = 0x00, tmpregister = 0x00;
+    GPIO_Module *GPIOx;
+    /* Check the parameters */
+    assert_param(IS_GPIO_REMAP_PORT_SOURCE(PortSource));
+    assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+    assert_param(IS_GPIO_AF(AlternateFunction));
+    /*Get Peripheral point*/
+    GPIOx = GPIO_GET_PERIPH(PortSource);
+    /**/
+    if (PinSource & (uint8_t)0x08)
+    {
+        tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+        /*Read GPIO_AFH register*/
+        tmpregister  = GPIOx->AFH;
+        /*Reset corresponding bits*/
+        tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+        /*Set corresponding bits*/
+        tmpregister |= AlternateFunction << (tmp*4U);
+        /*Write to the GPIO_AFH register*/
+        GPIOx->AFH = tmpregister;
+    }
+    else
+    {
+        tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+        /*Read GPIO_AFL register*/
+        tmpregister  = GPIOx->AFL;
+        /*Reset corresponding bits*/
+        tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+        /*Set corresponding bits*/
+        tmpregister |= AlternateFunction << (tmp*4U);
+        /*Write to the GPIO_AFL register*/
+        GPIOx->AFL = tmpregister;
+    }
+}
+
+/**
+ * @brief  Selects the GPIO pin used as Event output.
+ * @param PortSource selects the GPIO port to be used as source
+ *   for Event output.
+ *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..D).
+ * @param PinSource specifies the pin for the Event output.
+ *   This parameter can be GPIO_PinSourcex where x can be (0..15).
+ */
+void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource)
+{
+    uint32_t tmpregister = 0x00,tmp = 0x00;
+    GPIO_Module *GPIOx;
+    /* Check the parameters */
+    assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(PortSource));
+    assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+
+    /*Get Peripheral structure point*/
+    GPIOx = GPIO_GET_PERIPH(PortSource);
+    if (PinSource & (uint8_t)0x08)
+    {
+        tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+        /*Read GPIO_AFH register*/
+        tmpregister  = GPIOx->AFH;
+        /*Reset corresponding bits*/
+        tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+        /*Set corresponding bits*/
+        tmpregister |= GPIO_AF3_EVENTOUT;
+        /*Write to the GPIO_AFH register*/
+        GPIOx->AFH = tmpregister;
+    }
+    else
+    {
+        tmp = (uint32_t)(PinSource & (uint8_t)0x07);
+        /*Read GPIO_AFL register*/
+        tmpregister  = GPIOx->AFL;
+        /*Reset corresponding bits*/
+        tmpregister &=~((uint32_t)0x0F <<(tmp*4U));
+        /*Set corresponding bits*/
+        tmpregister |= GPIO_AF3_EVENTOUT;
+        /*Write to the GPIO_AFL register*/
+        GPIOx->AFL = tmpregister;
+    }
+}
+
+/**
+ * @brief  Enables or disables the Event Output.
+ * @param Cmd new state of the Event output.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void GPIO_CtrlEventOutput(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    *(__IO uint32_t*)EVCR_EVOE_BB = (uint32_t)Cmd;
+}
+
+
+/**
+ * @brief  Selects the GPIO pin used as EXTI Line.
+ * @param PortSource selects the GPIO port to be used as source for EXTI lines.
+ *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..D).
+ * @param PinSource specifies the EXTI line to be configured.
+ *   This parameter can be GPIO_PinSourcex where x can be (0..15).
+ */
+void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource)
+{
+    uint32_t port = (uint32_t)PortSource;
+    /* Check the parameters */
+    assert_param(IS_GPIO_EXTI_PORT_SOURCE(PortSource));
+    assert_param(IS_GPIO_PIN_SOURCE(PinSource));
+
+    AFIO->EXTI_CFG[(PinSource >> 0x02)] &= ~(((uint32_t)0x03) << ((PinSource & (uint8_t)0x03)*4u));
+    AFIO->EXTI_CFG[(PinSource >> 0x02)] |=  (port << ((PinSource & (uint8_t)0x03) *4u));
+}
+
+/**
+ * @brief  Selects the alternate function SPIx NSS mode.
+ * @param AFIO_SPIx_NSS choose which SPI configuration.
+ *   This parameter can be AFIO_SPI1_NSS and AFIO_SPI2_NSS.
+ * @param SpiNssType specifies the SPI_NSS mode to be configured.
+ *   This parameter can be AFIO_SPI1_NSS_High_IMPEDANCE and AFIO_SPI1_NSS_High_LEVEL.
+ */
+void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS,AFIO_SPI_NSSType SpiNssType)
+{
+    uint32_t tmp = 0x00;
+    /* Check the parameters */
+    assert_param(IS_AFIO_SPIX(AFIO_SPIx_NSS));
+    assert_param(IS_AFIO_SPI_NSS(SpiNssType));
+    tmp = AFIO->RMP_CFG;
+    tmp &=(~(0x01U << AFIO_SPIx_NSS));
+    tmp |=(SpiNssType << AFIO_SPIx_NSS);
+    AFIO->RMP_CFG = tmp;
+}
+
+/**
+ * @brief  Configurate ADC external trigger.
+ * @param ADCETRType choose whether to configure rule conversion or injection conversion .
+ *   This parameter can be AFIO_ADC_ETRI and AFIO_ADC_ETRR.
+ * @param ADCTrigRemap specifies the external trigger line be configured.
+ *   This parameter can be AFIO_ADC_TRIG_EXTI_x where x can be (0..15) or AFIO_ADC_TRIG_TIM8_CHy where y can be(3..4).
+ */
+void AFIO_ConfigADCExternalTrigRemap(AFIO_ADC_ETRType ADCETRType,AFIO_ADC_Trig_RemapType ADCTrigRemap)
+{
+    uint32_t tmp = 0x00;
+    /* Check the parameters */
+    assert_param(IS_AFIO_ADC_ETR(ADCETRType));
+    if (ADCETRType == AFIO_ADC_ETRI)
+    {
+        /* Check the parameters */
+        assert_param(IS_AFIO_ADC_ETRI(ADCTrigRemap));
+        tmp  = AFIO->RMP_CFG;
+        /* clear AFIO_RMP_CFG register ETRI bit*/
+        tmp &= (~(0x01U << AFIO_ADC_ETRI));
+        /* if ADCETRType is AFIO_ADC_ETRI then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH3*/
+        if (ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH4)
+        {
+            /* select TIM8_CH4 line to connect*/
+            tmp |= (0x01U << AFIO_ADC_ETRI);
+        }
+        else
+        {
+            /* select which external line is connected*/
+            tmp &=(~(0x0FU<<4U));
+            tmp |= (ADCTrigRemap<<4U);
+        }
+        AFIO->RMP_CFG = tmp;
+    }
+    else
+    {
+        if (ADCETRType == AFIO_ADC_ETRR)
+        {
+            /* Check the parameters */
+            assert_param(IS_AFIO_ADC_ETRR(ADCTrigRemap));
+            tmp  = AFIO->RMP_CFG;
+            /* clear AFIO_RMP_CFG register ETRR bit*/
+            tmp &= (~(0x01U << AFIO_ADC_ETRR));
+            /* if ADCETRType is AFIO_ADC_ETRR then ADCTrigRemap cannot be AFIO_ADC_TRIG_TIM8_CH4*/
+            if (ADCTrigRemap == AFIO_ADC_TRIG_TIM8_CH3)
+            {
+                /* select TIM8_CH3 line to connect*/
+                tmp |= (0x01U << AFIO_ADC_ETRR);
+            }
+            else
+            {
+                /* select which external line is connected*/
+                tmp &=(~(0x0FU<<0));
+                tmp |= ADCTrigRemap;
+            }
+            AFIO->RMP_CFG = tmp;
+        }
+    }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_i2c.c

@@ -0,0 +1,1301 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_i2c.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_i2c.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+/** @addtogroup I2C_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Defines
+ * @{
+ */
+
+/* I2C SPE mask */
+#define CTRL1_SPEN_SET   ((uint16_t)0x0001)
+#define CTRL1_SPEN_RESET ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CTRL1_START_SET   ((uint16_t)0x0100)
+#define CTRL1_START_RESET ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CTRL1_STOP_SET   ((uint16_t)0x0200)
+#define CTRL1_STOP_RESET ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CTRL1_ACK_SET   ((uint16_t)0x0400)
+#define CTRL1_ACK_RESET ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CTRL1_GCEN_SET   ((uint16_t)0x0040)
+#define CTRL1_GCEN_RESET ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CTRL1_SWRESET_SET   ((uint16_t)0x8000)
+#define CTRL1_SWRESET_RESET ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CTRL1_PEC_SET   ((uint16_t)0x1000)
+#define CTRL1_PEC_RESET ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CTRL1_PECEN_SET   ((uint16_t)0x0020)
+#define CTRL1_PECEN_RESET ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CTRL1_ARPEN_SET   ((uint16_t)0x0010)
+#define CTRL1_ARPEN_RESET ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CTRL1_NOEXTEND_SET   ((uint16_t)0x0080)
+#define CTRL1_NOEXTEND_RESET ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CTRL1_CLR_MASK ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CTRL2_DMAEN_SET   ((uint16_t)0x0800)
+#define CTRL2_DMAEN_RESET ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CTRL2_DMALAST_SET   ((uint16_t)0x1000)
+#define CTRL2_DMALAST_RESET ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CTRL2_CLKFREQ_RESET ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OADDR1_ADDR0_SET   ((uint16_t)0x0001)
+#define OADDR1_ADDR0_RESET ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OADDR2_DUALEN_SET   ((uint16_t)0x0001)
+#define OADDR2_DUALEN_RESET ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OADDR2_ADDR2_RESET ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CLKCTRL_FSMODE_SET ((uint16_t)0x8000)
+
+/* I2C CHCFG mask */
+#define CLKCTRL_CLKCTRL_SET ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_MASK ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define INTEN_MASK ((uint32_t)0x07000000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ */
+void I2C_DeInit(I2C_Module* I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    if (I2Cx == I2C1)
+    {
+        /* Enable I2C1 reset state */
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, ENABLE);
+        /* Release I2C1 from reset state */
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C1, DISABLE);
+    }
+    else
+    {
+        /* Enable I2C2 reset state */
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, ENABLE);
+        /* Release I2C2 from reset state */
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_I2C2, DISABLE);
+    }
+}
+
+/**
+ * @brief  Initializes the I2Cx peripheral according to the specified
+ *   parameters in the I2C_InitStruct.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_InitStruct pointer to a I2C_InitType structure that
+ *   contains the configuration information for the specified I2C peripheral.
+ */
+void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct)
+{
+    uint16_t tmpregister = 0, freqrange = 0;
+    uint16_t result = 0x04;
+    uint32_t pclk1  = 8000000;
+    RCC_ClocksType rcc_clocks;
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_CLK_SPEED(I2C_InitStruct->ClkSpeed));
+    assert_param(IS_I2C_BUS_MODE(I2C_InitStruct->BusMode));
+    assert_param(IS_I2C_FM_DUTY_CYCLE(I2C_InitStruct->FmDutyCycle));
+    assert_param(IS_I2C_OWN_ADDR1(I2C_InitStruct->OwnAddr1));
+    assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->AckEnable));
+    assert_param(IS_I2C_ADDR_MODE(I2C_InitStruct->AddrMode));
+
+    /*---------------------------- I2Cx CTRL2 Configuration ------------------------*/
+    /* Get the I2Cx CTRL2 value */
+    tmpregister = I2Cx->CTRL2;
+    /* Clear frequency FREQ[5:0] bits */
+    tmpregister &= CTRL2_CLKFREQ_RESET;
+    /* Get pclk1 frequency value */
+    RCC_GetClocksFreqValue(&rcc_clocks);
+    pclk1 = rcc_clocks.Pclk1Freq;
+    /* Set frequency bits depending on pclk1 value */
+    freqrange = (uint16_t)(pclk1 / 1000000);
+    tmpregister |= freqrange;
+    /* Write to I2Cx CTRL2 */
+    I2Cx->CTRL2 = tmpregister;
+
+    /*---------------------------- I2Cx CHCFG Configuration ------------------------*/
+    /* Disable the selected I2C peripheral to configure TMRISE */
+    I2Cx->CTRL1 &= CTRL1_SPEN_RESET;
+    /* Reset tmpregister value */
+    /* Clear F/S, DUTY and CHCFG[11:0] bits */
+    tmpregister = 0;
+
+    /* Configure speed in standard mode */
+    if (I2C_InitStruct->ClkSpeed <= 100000)
+    {
+        /* Standard mode speed calculate */
+        result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed << 1));
+        /* Test if CHCFG value is under 0x4*/
+        if (result < 0x04)
+        {
+            /* Set minimum allowed value */
+            result = 0x04;
+        }
+        /* Set speed value for standard mode */
+        tmpregister |= result;
+        /* Set Maximum Rise Time for standard mode */
+        I2Cx->TMRISE = freqrange + 1;
+    }
+    /* Configure speed in fast mode */
+    // else if ((I2C_InitStruct->ClkSpeed > 100000)&&(I2C_InitStruct->ClkSpeed <= 400000))/*(I2C_InitStruct->ClkSpeed <=
+    // 400000)*/
+    else
+    {
+        if (I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_2)
+        {
+            /* Fast mode speed calculate: Tlow/Thigh = 2 */
+            result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 3));
+        }
+        else /*I2C_InitStruct->FmDutyCycle == I2C_FMDUTYCYCLE_16_9*/
+        {
+            /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+            result = (uint16_t)(pclk1 / (I2C_InitStruct->ClkSpeed * 25));
+            /* Set DUTY bit */
+            result |= I2C_FMDUTYCYCLE_16_9;
+        }
+
+        /* Test if CHCFG value is under 0x1*/
+        if ((result & CLKCTRL_CLKCTRL_SET) == 0)
+        {
+            /* Set minimum allowed value */
+            result |= (uint16_t)0x0001;
+        }
+        /* Set speed value and set F/S bit for fast mode */
+        tmpregister |= (uint16_t)(result | CLKCTRL_FSMODE_SET);
+        /* Set Maximum Rise Time for fast mode */
+        // if (I2C_InitStruct->ClkSpeed <= 400000)
+        {
+            I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+        }
+        // else//add test
+        //{
+        //    I2Cx->TMRISE = (uint16_t)(((freqrange * (uint16_t)100) / (uint16_t)1000) + (uint16_t)1);
+        //}
+    }
+    /* Write to I2Cx CHCFG */
+    I2Cx->CLKCTRL = tmpregister;
+    /* Enable the selected I2C peripheral */
+    I2Cx->CTRL1 |= CTRL1_SPEN_SET;
+
+    /*---------------------------- I2Cx CTRL1 Configuration ------------------------*/
+    /* Get the I2Cx CTRL1 value */
+    tmpregister = I2Cx->CTRL1;
+    /* Clear ACK, SMBTYPE and  SMBUS bits */
+    tmpregister &= CTRL1_CLR_MASK;
+    /* Configure I2Cx: mode and acknowledgement */
+    /* Set SMBTYPE and SMBUS bits according to BusMode value */
+    /* Set ACK bit according to AckEnable value */
+    tmpregister |= (uint16_t)((uint32_t)I2C_InitStruct->BusMode | I2C_InitStruct->AckEnable);
+    /* Write to I2Cx CTRL1 */
+    I2Cx->CTRL1 = tmpregister;
+
+    /*---------------------------- I2Cx OADDR1 Configuration -----------------------*/
+    /* Set I2Cx Own Address1 and acknowledged address */
+    I2Cx->OADDR1 = (I2C_InitStruct->AddrMode | I2C_InitStruct->OwnAddr1);
+}
+
+/**
+ * @brief  Fills each I2C_InitStruct member with its default value.
+ * @param I2C_InitStruct pointer to an I2C_InitType structure which will be initialized.
+ */
+void I2C_InitStruct(I2C_InitType* I2C_InitStruct)
+{
+    /*---------------- Reset I2C init structure parameters values ----------------*/
+    /* initialize the ClkSpeed member */
+    I2C_InitStruct->ClkSpeed = 5000;
+    /* Initialize the BusMode member */
+    I2C_InitStruct->BusMode = I2C_BUSMODE_I2C;
+    /* Initialize the FmDutyCycle member */
+    I2C_InitStruct->FmDutyCycle = I2C_FMDUTYCYCLE_2;
+    /* Initialize the OwnAddr1 member */
+    I2C_InitStruct->OwnAddr1 = 0;
+    /* Initialize the AckEnable member */
+    I2C_InitStruct->AckEnable = I2C_ACKDIS;
+    /* Initialize the AddrMode member */
+    I2C_InitStruct->AddrMode = I2C_ADDR_MODE_7BIT;
+}
+
+/**
+ * @brief  Enables or disables the specified I2C peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx peripheral.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected I2C peripheral */
+        I2Cx->CTRL1 |= CTRL1_SPEN_SET;
+    }
+    else
+    {
+        /* Disable the selected I2C peripheral */
+        I2Cx->CTRL1 &= CTRL1_SPEN_RESET;
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified I2C DMA requests.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C DMA transfer.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected I2C DMA requests */
+        I2Cx->CTRL2 |= CTRL2_DMAEN_SET;
+    }
+    else
+    {
+        /* Disable the selected I2C DMA requests */
+        I2Cx->CTRL2 &= CTRL2_DMAEN_RESET;
+    }
+}
+
+/**
+ * @brief  Specifies if the next DMA transfer will be the last one.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C DMA last transfer.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Next DMA transfer is the last transfer */
+        I2Cx->CTRL2 |= CTRL2_DMALAST_SET;
+    }
+    else
+    {
+        /* Next DMA transfer is not the last transfer */
+        I2Cx->CTRL2 &= CTRL2_DMALAST_RESET;
+    }
+}
+
+/**
+ * @brief  Generates I2Cx communication START condition.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C START condition generation.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Generate a START condition */
+        I2Cx->CTRL1 |= CTRL1_START_SET;
+    }
+    else
+    {
+        /* Disable the START condition generation */
+        I2Cx->CTRL1 &= CTRL1_START_RESET;
+    }
+}
+
+/**
+ * @brief  Generates I2Cx communication STOP condition.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C STOP condition generation.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Generate a STOP condition */
+        I2Cx->CTRL1 |= CTRL1_STOP_SET;
+    }
+    else
+    {
+        /* Disable the STOP condition generation */
+        I2Cx->CTRL1 &= CTRL1_STOP_RESET;
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified I2C acknowledge feature.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C Acknowledgement.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the acknowledgement */
+        I2Cx->CTRL1 |= CTRL1_ACK_SET;
+    }
+    else
+    {
+        /* Disable the acknowledgement */
+        I2Cx->CTRL1 &= CTRL1_ACK_RESET;
+    }
+}
+
+/**
+ * @brief  Configures the specified I2C own address2.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address specifies the 7bit I2C own address2.
+ */
+void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address)
+{
+    uint16_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Get the old register value */
+    tmpregister = I2Cx->OADDR2;
+
+    /* Reset I2Cx Own address2 bit [7:1] */
+    tmpregister &= OADDR2_ADDR2_RESET;
+
+    /* Set I2Cx Own address2 */
+    tmpregister |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+    /* Store the new register value */
+    I2Cx->OADDR2 = tmpregister;
+}
+
+/**
+ * @brief  Enables or disables the specified I2C dual addressing mode.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C dual addressing mode.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable dual addressing mode */
+        I2Cx->OADDR2 |= OADDR2_DUALEN_SET;
+    }
+    else
+    {
+        /* Disable dual addressing mode */
+        I2Cx->OADDR2 &= OADDR2_DUALEN_RESET;
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified I2C general call feature.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C General call.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable generall call */
+        I2Cx->CTRL1 |= CTRL1_GCEN_SET;
+    }
+    else
+    {
+        /* Disable generall call */
+        I2Cx->CTRL1 &= CTRL1_GCEN_RESET;
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified I2C interrupts.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the I2C interrupts sources to be enabled or disabled.
+ *   This parameter can be any combination of the following values:
+ *     @arg I2C_INT_BUF Buffer interrupt mask
+ *     @arg I2C_INT_EVENT Event interrupt mask
+ *     @arg I2C_INT_ERR Error interrupt mask
+ * @param Cmd new state of the specified I2C interrupts.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    assert_param(IS_I2C_CFG_INT(I2C_IT));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected I2C interrupts */
+        I2Cx->CTRL2 |= I2C_IT;
+    }
+    else
+    {
+        /* Disable the selected I2C interrupts */
+        I2Cx->CTRL2 &= (uint16_t)~I2C_IT;
+    }
+}
+
+/**
+ * @brief  Sends a data byte through the I2Cx peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Data Byte to be transmitted..
+ */
+void I2C_SendData(I2C_Module* I2Cx, uint8_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    /* Write in the DAT register the data to be sent */
+    I2Cx->DAT = Data;
+}
+
+/**
+ * @brief  Returns the most recent received data by the I2Cx peripheral.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @return The value of the received data.
+ */
+uint8_t I2C_RecvData(I2C_Module* I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    /* Return the data in the DAT register */
+    return (uint8_t)I2Cx->DAT;
+}
+
+/**
+ * @brief  Transmits the address byte to select the slave device.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address specifies the slave address which will be transmitted
+ * @param I2C_Direction specifies whether the I2C device will be a
+ *   Transmitter or a Receiver. This parameter can be one of the following values
+ *     @arg I2C_DIRECTION_SEND Transmitter mode
+ *     @arg I2C_DIRECTION_RECV Receiver mode
+ */
+void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_DIRECTION(I2C_Direction));
+    /* Test on the direction to set/reset the read/write bit */
+    if (I2C_Direction != I2C_DIRECTION_SEND)
+    {
+        /* Set the address bit0 for read */
+        Address |= OADDR1_ADDR0_SET;
+    }
+    else
+    {
+        /* Reset the address bit0 for write */
+        Address &= OADDR1_ADDR0_RESET;
+    }
+    /* Send the address */
+    I2Cx->DAT = Address;
+}
+
+/**
+ * @brief  Reads the specified I2C register and returns its value.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_Register specifies the register to read.
+ *   This parameter can be one of the following values:
+ *     @arg I2C_REG_CTRL1 CTRL1 register.
+ *     @arg I2C_REG_CTRL2 CTRL2 register.
+ *     @arg I2C_REG_OADDR1 OADDR1 register.
+ *     @arg I2C_REG_OADDR2 OADDR2 register.
+ *     @arg I2C_REG_DAT DAT register.
+ *     @arg I2C_REG_STS1 STS1 register.
+ *     @arg I2C_REG_STS2 STS2 register.
+ *     @arg I2C_REG_CLKCTRL CHCFG register.
+ *     @arg I2C_REG_TMRISE TMRISE register.
+ * @return The value of the read register.
+ */
+uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register)
+{
+    __IO uint32_t tmp = 0;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_REG(I2C_Register));
+
+    tmp = (uint32_t)I2Cx;
+    tmp += I2C_Register;
+
+    /* Return the selected register value */
+    return (*(__IO uint16_t*)tmp);
+}
+
+/**
+ * @brief  Enables or disables the specified I2C software reset.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C software reset.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Peripheral under reset */
+        I2Cx->CTRL1 |= CTRL1_SWRESET_SET;
+    }
+    else
+    {
+        /* Peripheral not under reset */
+        I2Cx->CTRL1 &= CTRL1_SWRESET_RESET;
+    }
+}
+
+/**
+ * @brief  Selects the specified I2C NACK position in master receiver mode.
+ *         This function is useful in I2C Master Receiver mode when the number
+ *         of data to be received is equal to 2. In this case, this function
+ *         should be called (with parameter I2C_NACK_POS_NEXT) before data
+ *         reception starts,as described in the 2-byte reception procedure
+ *         recommended in Reference Manual in Section: Master receiver.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_NACKPosition specifies the NACK position.
+ *   This parameter can be one of the following values:
+ *     @arg I2C_NACK_POS_NEXT indicates that the next byte will be the last
+ *          received byte.
+ *     @arg I2C_NACK_POS_CURRENT indicates that current byte is the last
+ *          received byte.
+ *
+ * @note    This function configures the same bit (POS) as I2C_ConfigPecLocation()
+ *          but is intended to be used in I2C mode while I2C_ConfigPecLocation()
+ *          is intended to used in SMBUS mode.
+ *
+ */
+void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_NACK_POS(I2C_NACKPosition));
+
+    /* Check the input parameter */
+    if (I2C_NACKPosition == I2C_NACK_POS_NEXT)
+    {
+        /* Next byte in shift register is the last received byte */
+        I2Cx->CTRL1 |= I2C_NACK_POS_NEXT;
+    }
+    else
+    {
+        /* Current byte in shift register is the last received byte */
+        I2Cx->CTRL1 &= I2C_NACK_POS_CURRENT;
+    }
+}
+
+/**
+ * @brief  Drives the SMBusAlert pin high or low for the specified I2C.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_SMBusAlert specifies SMBAlert pin level.
+ *   This parameter can be one of the following values:
+ *     @arg I2C_SMBALERT_LOW SMBAlert pin driven low
+ *     @arg I2C_SMBALERT_HIGH SMBAlert pin driven high
+ */
+void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_SMB_ALERT(I2C_SMBusAlert));
+    if (I2C_SMBusAlert == I2C_SMBALERT_LOW)
+    {
+        /* Drive the SMBusAlert pin Low */
+        I2Cx->CTRL1 |= I2C_SMBALERT_LOW;
+    }
+    else
+    {
+        /* Drive the SMBusAlert pin High  */
+        I2Cx->CTRL1 &= I2C_SMBALERT_HIGH;
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified I2C PEC transfer.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2C PEC transmission.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected I2C PEC transmission */
+        I2Cx->CTRL1 |= CTRL1_PEC_SET;
+    }
+    else
+    {
+        /* Disable the selected I2C PEC transmission */
+        I2Cx->CTRL1 &= CTRL1_PEC_RESET;
+    }
+}
+
+/**
+ * @brief  Selects the specified I2C PEC position.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_PECPosition specifies the PEC position.
+ *   This parameter can be one of the following values:
+ *     @arg I2C_PEC_POS_NEXT indicates that the next byte is PEC
+ *     @arg I2C_PEC_POS_CURRENT indicates that current byte is PEC
+ *
+ * @note    This function configures the same bit (POS) as I2C_ConfigNackLocation()
+ *          but is intended to be used in SMBUS mode while I2C_ConfigNackLocation()
+ *          is intended to used in I2C mode.
+ *
+ */
+void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_PEC_POS(I2C_PECPosition));
+    if (I2C_PECPosition == I2C_PEC_POS_NEXT)
+    {
+        /* Next byte in shift register is PEC */
+        I2Cx->CTRL1 |= I2C_PEC_POS_NEXT;
+    }
+    else
+    {
+        /* Current byte in shift register is PEC */
+        I2Cx->CTRL1 &= I2C_PEC_POS_CURRENT;
+    }
+}
+
+/**
+ * @brief  Enables or disables the PEC value calculation of the transferred bytes.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx PEC value calculation.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected I2C PEC calculation */
+        I2Cx->CTRL1 |= CTRL1_PECEN_SET;
+    }
+    else
+    {
+        /* Disable the selected I2C PEC calculation */
+        I2Cx->CTRL1 &= CTRL1_PECEN_RESET;
+    }
+}
+
+/**
+ * @brief  Returns the PEC value for the specified I2C.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @return The PEC value.
+ */
+uint8_t I2C_GetPec(I2C_Module* I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    /* Return the selected I2C PEC value */
+    return ((I2Cx->STS2) >> 8);
+}
+
+/**
+ * @brief  Enables or disables the specified I2C ARP.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx ARP.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected I2C ARP */
+        I2Cx->CTRL1 |= CTRL1_ARPEN_SET;
+    }
+    else
+    {
+        /* Disable the selected I2C ARP */
+        I2Cx->CTRL1 &= CTRL1_ARPEN_RESET;
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified I2C Clock stretching.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param Cmd new state of the I2Cx Clock stretching.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd == DISABLE)
+    {
+        /* Enable the selected I2C Clock stretching */
+        I2Cx->CTRL1 |= CTRL1_NOEXTEND_SET;
+    }
+    else
+    {
+        /* Disable the selected I2C Clock stretching */
+        I2Cx->CTRL1 &= CTRL1_NOEXTEND_RESET;
+    }
+}
+
+/**
+ * @brief  Selects the specified I2C fast mode duty cycle.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param FmDutyCycle specifies the fast mode duty cycle.
+ *   This parameter can be one of the following values:
+ *     @arg I2C_FMDUTYCYCLE_2 I2C fast mode Tlow/Thigh = 2
+ *     @arg I2C_FMDUTYCYCLE_16_9 I2C fast mode Tlow/Thigh = 16/9
+ */
+void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_FM_DUTY_CYCLE(FmDutyCycle));
+    if (FmDutyCycle != I2C_FMDUTYCYCLE_16_9)
+    {
+        /* I2C fast mode Tlow/Thigh=2 */
+        I2Cx->CLKCTRL &= I2C_FMDUTYCYCLE_2;
+    }
+    else
+    {
+        /* I2C fast mode Tlow/Thigh=16/9 */
+        I2Cx->CLKCTRL |= I2C_FMDUTYCYCLE_16_9;
+    }
+}
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ *                         I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ *  depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ *    Using I2C_CheckEvent() function:
+ *    It compares the status registers (STS1 and STS2) content to a given event
+ *    (can be the combination of one or more flags).
+ *    It returns SUCCESS if the current status includes the given flags
+ *    and returns ERROR if one or more flags are missing in the current status.
+ *    - When to use:
+ *      - This function is suitable for most applications as well as for startup
+ *      activity since the events are fully described in the product reference manual
+ *      (RM0008).
+ *      - It is also suitable for users who need to define their own events.
+ *    - Limitations:
+ *      - If an error occurs (ie. error flags are set besides to the monitored flags),
+ *        the I2C_CheckEvent() function may return SUCCESS despite the communication
+ *        hold or corrupted real state.
+ *        In this case, it is advised to use error interrupts to monitor the error
+ *        events and handle them in the interrupt IRQ handler.
+ *
+ *        @note
+ *        For error management, it is advised to use the following functions:
+ *          - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR).
+ *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ *            Where x is the peripheral instance (I2C1, I2C2 ...)
+ *          - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler()
+ *            in order to determine which error occured.
+ *          - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset()
+ *            and/or I2C_GenerateStop() in order to clear the error flag and source,
+ *            and return to correct communication status.
+ *
+ *
+ *  2) Advanced state monitoring:
+ *     Using the function I2C_GetLastEvent() which returns the image of both status
+ *     registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ *     by 16 bits and concatenated to Status Register 1).
+ *     - When to use:
+ *       - This function is suitable for the same applications above but it allows to
+ *         overcome the mentioned limitation of I2C_GetFlag() function.
+ *         The returned value could be compared to events already defined in the
+ *         library (n32g43x_i2c.h) or to custom values defined by user.
+ *       - This function is suitable when multiple flags are monitored at the same time.
+ *       - At the opposite of I2C_CheckEvent() function, this function allows user to
+ *         choose when an event is accepted (when all events flags are set and no
+ *         other flags are set or just when the needed flags are set like
+ *         I2C_CheckEvent() function).
+ *     - Limitations:
+ *       - User may need to define his own events.
+ *       - Same remark concerning the error management is applicable for this
+ *         function if user decides to check only regular communication flags (and
+ *         ignores error flags).
+ *
+ *
+ *  3) Flag-based state monitoring:
+ *     Using the function I2C_GetFlag() which simply returns the status of
+ *     one single flag (ie. I2C_FLAG_RXDATNE ...).
+ *     - When to use:
+ *        - This function could be used for specific applications or in debug phase.
+ *        - It is suitable when only one flag checking is needed (most I2C events
+ *          are monitored through multiple flags).
+ *     - Limitations:
+ *        - When calling this function, the Status register is accessed. Some flags are
+ *          cleared when the status register is accessed. So checking the status
+ *          of one Flag, may clear other ones.
+ *        - Function may need to be called twice or more in order to monitor one
+ *          single event.
+ *
+ *  For detailed description of Events, please refer to section I2C_Events in
+ *  n32g43x_i2c.h file.
+ *
+ */
+
+/**
+ * @brief  Checks whether the last I2Cx Event is equal to the one passed
+ *   as parameter.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_EVENT specifies the event to be checked.
+ *   This parameter can be one of the following values:
+ *     @arg I2C_EVT_SLAVE_SEND_ADDR_MATCHED EV1
+ *     @arg I2C_EVT_SLAVE_RECV_ADDR_MATCHED EV1
+ *     @arg I2C_EVT_SLAVE_SEND_ADDR2_MATCHED EV1
+ *     @arg I2C_EVT_SLAVE_RECV_ADDR2_MATCHED EV1
+ *     @arg I2C_EVT_SLAVE_GCALLADDR_MATCHED EV1
+ *     @arg I2C_EVT_SLAVE_DATA_RECVD EV2
+ *     @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG)  EV2
+ *     @arg (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR) EV2
+ *     @arg I2C_EVT_SLAVE_DATA_SENDED EV3
+ *     @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG) EV3
+ *     @arg (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR) EV3
+ *     @arg I2C_EVT_SLAVE_ACK_MISS EV3_2
+ *     @arg I2C_EVT_SLAVE_STOP_RECVD EV4
+ *     @arg I2C_EVT_MASTER_MODE_FLAG EV5
+ *     @arg I2C_EVT_MASTER_TXMODE_FLAG EV6
+ *     @arg I2C_EVT_MASTER_RXMODE_FLAG EV6
+ *     @arg I2C_EVT_MASTER_DATA_RECVD_FLAG EV7
+ *     @arg I2C_EVT_MASTER_DATA_SENDING EV8
+ *     @arg I2C_EVT_MASTER_DATA_SENDED EV8_2
+ *     @arg I2C_EVT_MASTER_MODE_ADDRESS10_FLAG EV9
+ *
+ * @note: For detailed description of Events, please refer to section
+ *    I2C_Events in n32g43x_i2c.h file.
+ *
+ * @return An ErrorStatus enumeration value:
+ * - SUCCESS: Last event is equal to the I2C_EVENT
+ * - ERROR: Last event is different from the I2C_EVENT
+ */
+ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT)
+{
+    uint32_t lastevent = 0;
+    uint32_t flag1 = 0, flag2 = 0;
+    ErrorStatus status = ERROR;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_EVT(I2C_EVENT));
+
+    /* Read the I2Cx status register */
+    flag1 = I2Cx->STS1;
+    flag2 = I2Cx->STS2;
+    flag2 = flag2 << 16;
+
+    /* Get the last event value from I2C status register */
+    lastevent = (flag1 | flag2) & FLAG_MASK;
+
+    /* Check whether the last event contains the I2C_EVENT */
+    if ((lastevent & I2C_EVENT) == I2C_EVENT)
+    {
+        /* SUCCESS: last event is equal to I2C_EVENT */
+        status = SUCCESS;
+    }
+    else
+    {
+        /* ERROR: last event is different from I2C_EVENT */
+        status = ERROR;
+    }
+    /* Return status */
+    return status;
+}
+
+/**
+ * @brief  Returns the last I2Cx Event.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @note: For detailed description of Events, please refer to section
+ *    I2C_Events in n32g43x_i2c.h file.
+ *
+ * @return The last event
+ */
+uint32_t I2C_GetLastEvent(I2C_Module* I2Cx)
+{
+    uint32_t lastevent = 0;
+    uint32_t flag1 = 0, flag2 = 0;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Read the I2Cx status register */
+    flag1 = I2Cx->STS1;
+    flag2 = I2Cx->STS2;
+    flag2 = flag2 << 16;
+
+    /* Get the last event value from I2C status register */
+    lastevent = (flag1 | flag2) & FLAG_MASK;
+
+    /* Return status */
+    return lastevent;
+}
+
+/**
+ * @brief  Checks whether the specified I2C flag is set or not.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG specifies the flag to check.
+ *   This parameter can be one of the following values:
+ *     @arg I2C_FLAG_DUALFLAG Dual flag (Slave mode)
+ *     @arg I2C_FLAG_SMBHADDR SMBus host header (Slave mode)
+ *     @arg I2C_FLAG_SMBDADDR SMBus default header (Slave mode)
+ *     @arg I2C_FLAG_GCALLADDR General call header flag (Slave mode)
+ *     @arg I2C_FLAG_TRF Transmitter/Receiver flag
+ *     @arg I2C_FLAG_BUSY Bus busy flag
+ *     @arg I2C_FLAG_MSMODE Master/Slave flag
+ *     @arg I2C_FLAG_SMBALERT SMBus Alert flag
+ *     @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag
+ *     @arg I2C_FLAG_PECERR PEC error in reception flag
+ *     @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode)
+ *     @arg I2C_FLAG_ACKFAIL Acknowledge failure flag
+ *     @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode)
+ *     @arg I2C_FLAG_BUSERR Bus error flag
+ *     @arg I2C_FLAG_TXDATE Data register empty flag (Transmitter)
+ *     @arg I2C_FLAG_RXDATNE Data register not empty (Receiver) flag
+ *     @arg I2C_FLAG_STOPF Stop detection flag (Slave mode)
+ *     @arg I2C_FLAG_ADDR10F 10-bit header sent flag (Master mode)
+ *     @arg I2C_FLAG_BYTEF Byte transfer finished flag
+ *     @arg I2C_FLAG_ADDRF Address sent flag (Master mode) "ADSL"
+ *   Address matched flag (Slave mode)"ENDA"
+ *     @arg I2C_FLAG_STARTBF Start bit flag (Master mode)
+ * @return The new state of I2C_FLAG (SET or RESET).
+ */
+FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+    /* Get the I2Cx peripheral base address */
+    i2cxbase = (uint32_t)I2Cx;
+
+    /* Read flag register index */
+    i2creg = I2C_FLAG >> 28;
+
+    /* Get bit[23:0] of the flag */
+    I2C_FLAG &= FLAG_MASK;
+
+    if (i2creg != 0)
+    {
+        /* Get the I2Cx STS1 register address */
+        i2cxbase += 0x14;
+    }
+    else
+    {
+        /* Flag in I2Cx STS2 Register */
+        I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+        /* Get the I2Cx STS2 register address */
+        i2cxbase += 0x18;
+    }
+
+    if (((*(__IO uint32_t*)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+    {
+        /* I2C_FLAG is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* I2C_FLAG is reset */
+        bitstatus = RESET;
+    }
+
+    /* Return the I2C_FLAG status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the I2Cx's pending flags.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG specifies the flag to clear.
+ *   This parameter can be any combination of the following values:
+ *     @arg I2C_FLAG_SMBALERT SMBus Alert flag
+ *     @arg I2C_FLAG_TIMOUT Timeout or Tlow error flag
+ *     @arg I2C_FLAG_PECERR PEC error in reception flag
+ *     @arg I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode)
+ *     @arg I2C_FLAG_ACKFAIL Acknowledge failure flag
+ *     @arg I2C_FLAG_ARLOST Arbitration lost flag (Master mode)
+ *     @arg I2C_FLAG_BUSERR Bus error flag
+ *
+ * @note
+ *   - STOPF (STOP detection) is cleared by software sequence: a read operation
+ *     to I2C_STS1 register (I2C_GetFlag()) followed by a write operation
+ *     to I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral).
+ *   - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ *     operation to I2C_STS1 (I2C_GetFlag()) followed by writing the
+ *     second byte of the address in DAT register.
+ *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ *     operation to I2C_STS1 register (I2C_GetFlag()) followed by a
+ *     read/write to I2C_DAT register (I2C_SendData()).
+ *   - ADDR (Address sent) is cleared by software sequence: a read operation to
+ *     I2C_STS1 register (I2C_GetFlag()) followed by a read operation to
+ *     I2C_STS2 register ((void)(I2Cx->STS2)).
+ *   - SB (Start Bit) is cleared software sequence: a read operation to I2C_STS1
+ *     register (I2C_GetFlag()) followed by a write operation to I2C_DAT
+ *     register  (I2C_SendData()).
+ */
+void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG)
+{
+    uint32_t flagpos = 0;
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_CLR_FLAG(I2C_FLAG));
+    /* Get the I2C flag position */
+    flagpos = I2C_FLAG & FLAG_MASK;
+    /* Clear the selected I2C flag */
+    I2Cx->STS1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @brief  Checks whether the specified I2C interrupt has occurred or not.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the interrupt source to check.
+ *   This parameter can be one of the following values:
+ *     @arg I2C_INT_SMBALERT SMBus Alert flag
+ *     @arg I2C_INT_TIMOUT Timeout or Tlow error flag
+ *     @arg I2C_INT_PECERR PEC error in reception flag
+ *     @arg I2C_INT_OVERRUN Overrun/Underrun flag (Slave mode)
+ *     @arg I2C_INT_ACKFAIL Acknowledge failure flag
+ *     @arg I2C_INT_ARLOST Arbitration lost flag (Master mode)
+ *     @arg I2C_INT_BUSERR Bus error flag
+ *     @arg I2C_INT_TXDATE Data register empty flag (Transmitter)
+ *     @arg I2C_INT_RXDATNE Data register not empty (Receiver) flag
+ *     @arg I2C_INT_STOPF Stop detection flag (Slave mode)
+ *     @arg I2C_INT_ADDR10F 10-bit header sent flag (Master mode)
+ *     @arg I2C_INT_BYTEF Byte transfer finished flag
+ *     @arg I2C_INT_ADDRF Address sent flag (Master mode) "ADSL"
+ *                       Address matched flag (Slave mode)"ENDAD"
+ *     @arg I2C_INT_STARTBF Start bit flag (Master mode)
+ * @return The new state of I2C_IT (SET or RESET).
+ */
+INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT)
+{
+    INTStatus bitstatus   = RESET;
+    uint32_t enablestatus = 0;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_GET_INT(I2C_IT));
+
+    /* Check if the interrupt source is enabled or not */
+    enablestatus = (uint32_t)(((I2C_IT & INTEN_MASK) >> 16) & (I2Cx->CTRL2));
+
+    /* Get bit[23:0] of the flag */
+    I2C_IT &= FLAG_MASK;
+
+    /* Check the status of the specified I2C flag */
+    if (((I2Cx->STS1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+    {
+        /* I2C_IT is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* I2C_IT is reset */
+        bitstatus = RESET;
+    }
+    /* Return the I2C_IT status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the I2Cx's interrupt pending bits.
+ * @param I2Cx where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT specifies the interrupt pending bit to clear.
+ *   This parameter can be any combination of the following values:
+ *     @arg I2C_INT_SMBALERT SMBus Alert interrupt
+ *     @arg I2C_INT_TIMOUT Timeout or Tlow error interrupt
+ *     @arg I2C_INT_PECERR PEC error in reception  interrupt
+ *     @arg I2C_INT_OVERRUN Overrun/Underrun interrupt (Slave mode)
+ *     @arg I2C_INT_ACKFAIL Acknowledge failure interrupt
+ *     @arg I2C_INT_ARLOST Arbitration lost interrupt (Master mode)
+ *     @arg I2C_INT_BUSERR Bus error interrupt
+ *
+ * @note
+ *   - STOPF (STOP detection) is cleared by software sequence: a read operation
+ *     to I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to
+ *     I2C_CTRL1 register (I2C_Enable() to re-enable the I2C peripheral).
+ *   - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ *     operation to I2C_STS1 (I2C_GetIntStatus()) followed by writing the second
+ *     byte of the address in I2C_DAT register.
+ *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ *     operation to I2C_STS1 register (I2C_GetIntStatus()) followed by a
+ *     read/write to I2C_DAT register (I2C_SendData()).
+ *   - ADDR (Address sent) is cleared by software sequence: a read operation to
+ *     I2C_STS1 register (I2C_GetIntStatus()) followed by a read operation to
+ *     I2C_STS2 register ((void)(I2Cx->STS2)).
+ *   - SB (Start Bit) is cleared by software sequence: a read operation to
+ *     I2C_STS1 register (I2C_GetIntStatus()) followed by a write operation to
+ *     I2C_DAT register (I2C_SendData()).
+ */
+void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT)
+{
+    uint32_t flagpos = 0;
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_CLR_INT(I2C_IT));
+    /* Get the I2C flag position */
+    flagpos = I2C_IT & FLAG_MASK;
+    /* Clear the selected I2C flag */
+    I2Cx->STS1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_iwdg.c

@@ -0,0 +1,193 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_iwdg.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_iwdg.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @brief IWDG driver modules
+ * @{
+ */
+
+/** @addtogroup IWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Defines
+ * @{
+ */
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KEY register bit mask */
+#define KEY_ReloadKey ((uint16_t)0xAAAA)
+#define KEY_EnableKey ((uint16_t)0xCCCC)
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param IWDG_WriteAccess new state of write access to IWDG_PR and IWDG_RLR registers.
+ *   This parameter can be one of the following values:
+ *     @arg IWDG_WRITE_ENABLE Enable write access to IWDG_PR and IWDG_RLR registers
+ *     @arg IWDG_WRITE_DISABLE Disable write access to IWDG_PR and IWDG_RLR registers
+ */
+void IWDG_WriteConfig(uint16_t IWDG_WriteAccess)
+{
+    /* Check the parameters */
+    assert_param(IS_IWDG_WRITE(IWDG_WriteAccess));
+    IWDG->KEY = IWDG_WriteAccess;
+}
+
+/**
+ * @brief  Sets IWDG Prescaler value.
+ * @param IWDG_Prescaler specifies the IWDG Prescaler value.
+ *   This parameter can be one of the following values:
+ *     @arg IWDG_PRESCALER_DIV4 IWDG prescaler set to 4
+ *     @arg IWDG_PRESCALER_DIV8 IWDG prescaler set to 8
+ *     @arg IWDG_PRESCALER_DIV16 IWDG prescaler set to 16
+ *     @arg IWDG_PRESCALER_DIV32 IWDG prescaler set to 32
+ *     @arg IWDG_PRESCALER_DIV64 IWDG prescaler set to 64
+ *     @arg IWDG_PRESCALER_DIV128 IWDG prescaler set to 128
+ *     @arg IWDG_PRESCALER_DIV256 IWDG prescaler set to 256
+ */
+void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler)
+{
+    /* Check the parameters */
+    assert_param(IS_IWDG_PRESCALER_DIV(IWDG_Prescaler));
+    IWDG->PREDIV = IWDG_Prescaler;
+}
+
+/**
+ * @brief  Sets IWDG Reload value.
+ * @param Reload specifies the IWDG Reload value.
+ *   This parameter must be a number between 0 and 0x0FFF.
+ */
+void IWDG_CntReload(uint16_t Reload)
+{
+    /* Check the parameters */
+    assert_param(IS_IWDG_RELOAD(Reload));
+    IWDG->RELV = Reload;
+}
+
+/**
+ * @brief  Reloads IWDG counter with value defined in the reload register
+ *   (write access to IWDG_PR and IWDG_RLR registers disabled).
+ */
+void IWDG_ReloadKey(void)
+{
+    IWDG->KEY = KEY_ReloadKey;
+}
+
+/**
+ * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+ */
+void IWDG_Enable(void)
+{
+    IWDG->KEY = KEY_EnableKey;
+}
+
+/**
+ * @brief  Checks whether the specified IWDG flag is set or not.
+ * @param IWDG_FLAG specifies the flag to check.
+ *   This parameter can be one of the following values:
+ *     @arg IWDG_PVU_FLAG Prescaler Value Update on going
+ *     @arg IWDG_CRVU_FLAG Reload Value Update on going
+ * @return The new state of IWDG_FLAG (SET or RESET).
+ */
+FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+    if ((IWDG->STS & IWDG_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    /* Return the flag status */
+    return bitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lptim.c

@@ -0,0 +1,1258 @@
+/** ----------------------------------------------------------------------------
+ *         Nationz Technology Software Support  -  NATIONZ  -
+ * -----------------------------------------------------------------------------
+ * Copyright (c) 2022, Nationz Corporation  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Nationz's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+ * -----------------------------------------------------------------------------
+ */
+
+/** ****************************************************************************
+ * @copyright      Nationz Co.,Ltd
+ *                 Copyright (c) 2019 All Rights Reserved
+ *******************************************************************************
+ * @file     n32g43x_lptim.c
+ * @author
+ * @date
+ * @version  v1.2.0
+ * @brief
+ ******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "n32g43x_lptim.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup n32g43x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup LPTIM
+  * @brief LPTIM driver modules
+  * @{
+  */
+
+/** @defgroup LPTIM_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+//#define LPTIM
+//#if defined (LPTIM)//LPTIM
+
+/** @defgroup RCC_EC_LPTIM1 Peripheral LPTIM get clock source
+  * @{
+  */
+#define RCC_LPTIM_CLKSOURCE              ((uint32_t)0x00000007)/*!< LPTIM1 clock source selection bits */
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Macros
+  * @{
+  */
+#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LPTIM_CLK_SOURCE_INTERNAL) \
+                                       || ((__VALUE__) == LPTIM_CLK_SOURCE_EXTERNAL))
+
+#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LPTIM_PRESCALER_DIV1)   \
+                                          || ((__VALUE__) == LPTIM_PRESCALER_DIV2)   \
+                                          || ((__VALUE__) == LPTIM_PRESCALER_DIV4)   \
+                                          || ((__VALUE__) == LPTIM_PRESCALER_DIV8)   \
+                                          || ((__VALUE__) == LPTIM_PRESCALER_DIV16)  \
+                                          || ((__VALUE__) == LPTIM_PRESCALER_DIV32)  \
+                                          || ((__VALUE__) == LPTIM_PRESCALER_DIV64)  \
+                                          || ((__VALUE__) == LPTIM_PRESCALER_DIV128))
+
+#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_PWM) \
+                                   || ((__VALUE__) == LPTIM_OUTPUT_WAVEFORM_SETONCE))
+
+#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LPTIM_OUTPUT_POLARITY_REGULAR) \
+                                          || ((__VALUE__) == LPTIM_OUTPUT_POLARITY_INVERSE))
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+  * @{
+  */
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPTIM_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LPTIM_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Set LPTIMx registers to their reset values.
+  * @param  LPTIMx LP Timer instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPTIMx registers are de-initialized
+  *          - ERROR: invalid LPTIMx instance
+  */
+void LPTIM_DeInit(LPTIM_Module* LPTIMx)
+{
+  if (LPTIMx == LPTIM)
+  {
+        RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,ENABLE);
+        RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPTIM,DISABLE);
+  }
+}
+
+/**
+  * @brief  Set each fields of the LPTIM_InitStruct structure to its default
+  *         value.
+  * @param  LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure
+  * @retval None
+  */
+void LPTIM_StructInit(LPTIM_InitType* LPTIM_InitStruct)
+{
+  /* Set the default configuration */
+  LPTIM_InitStruct->ClockSource = LPTIM_CLK_SOURCE_INTERNAL;
+  LPTIM_InitStruct->Prescaler   = LPTIM_PRESCALER_DIV1;
+  LPTIM_InitStruct->Waveform    = LPTIM_OUTPUT_WAVEFORM_PWM;
+  LPTIM_InitStruct->Polarity    = LPTIM_OUTPUT_POLARITY_REGULAR;
+}
+
+/**
+  * @brief  Configure the LPTIMx peripheral according to the specified parameters.
+  * @note LPTIM_Init can only be called when the LPTIM instance is disabled.
+  * @note LPTIMx can be disabled using unitary function @ref LPTIM_Disable().
+  * @param  LPTIMx LP Timer Instance
+  * @param  LPTIM_InitStruct pointer to a @ref LPTIM_InitType structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPTIMx instance has been initialized
+  *          - ERROR: LPTIMx instance hasn't been initialized
+  */
+ErrorStatus LPTIM_Init(LPTIM_Module * LPTIMx, LPTIM_InitType* LPTIM_InitStruct)
+{
+  ErrorStatus result = SUCCESS;
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+  assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+  assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+  assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
+
+  /* The LPTIMx_CFG register must only be modified when the LPTIM is disabled
+     (ENABLE bit is reset to 0).
+  */
+  if (LPTIM_IsEnabled(LPTIMx) == 1UL)
+  {
+    result = ERROR;
+  }
+  else
+  {
+  /* Set CKSEL bitfield according to ClockSource value */
+  /* Set PRESC bitfield according to Prescaler value */
+  /* Set WAVE bitfield according to Waveform value */
+  /* Set WAVEPOL bitfield according to Polarity value */
+  MODIFY_REG(LPTIMx->CFG,
+             (LPTIM_CFG_CLKSEL | LPTIM_CFG_CLKPOL | LPTIM_CFG_WAVE| LPTIM_CFG_WAVEPOL),
+             LPTIM_InitStruct->ClockSource | \
+             LPTIM_InitStruct->Prescaler | \
+             LPTIM_InitStruct->Waveform | \
+             LPTIM_InitStruct->Polarity);
+  }
+
+  return result;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Disable the LPTIM instance
+  * @rmtoll CR           ENABLE        LPTIM_Disable
+  * @param  LPTIMx Low-Power Timer instance
+  * @note
+  * @retval None
+  */
+void LPTIM_Disable(LPTIM_Module *LPTIMx)
+{
+    CLEAR_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN);
+}
+
+/** @defgroup LPTIM_EF_LPTIM_Configuration LPTIM Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable the LPTIM instance
+  * @note After setting the ENABLE bit, a delay of two counter clock is needed
+  *       before the LPTIM instance is actually enabled.
+  * @rmtoll CR           ENABLE        LPTIM_Enable
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_Enable(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN);
+}
+
+/**
+  * @brief  Indicates whether the LPTIM instance is enabled.
+  * @rmtoll CR           ENABLE        LPTIM_IsEnabled
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN) == LPTIM_CTRL_LPTIMEN)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Starts the LPTIM counter in the desired mode.
+  * @note LPTIM instance must be enabled before starting the counter.
+  * @note It is possible to change on the fly from One Shot mode to
+  *       Continuous mode.
+  * @rmtoll CR           CNTSTRT       LPTIM_StartCounter\n
+  *         CR           SNGSTRT       LPTIM_StartCounter
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  OperatingMode This parameter can be one of the following values:
+  *         @arg @ref LPTIM_OPERATING_MODE_CONTINUOUS
+  *         @arg @ref LPTIM_OPERATING_MODE_ONESHOT
+  * @retval None
+  */
+void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode)
+{
+  MODIFY_REG(LPTIMx->CTRL, LPTIM_CTRL_TSTCM | LPTIM_CTRL_SNGMST, OperatingMode);
+}
+
+/**
+  * @brief  Set the LPTIM registers update mode (enable/disable register preload)
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFG         PRELOAD       LPTIM_SetUpdateMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  UpdateMode This parameter can be one of the following values:
+  *         @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE
+  *         @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD
+  * @retval None
+  */
+void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode)
+{
+  MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_RELOAD, UpdateMode);
+}
+
+/**
+  * @brief  Get the LPTIM registers update mode
+  * @rmtoll CFG         PRELOAD       LPTIM_GetUpdateMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LPTIM_UPDATE_MODE_IMMEDIATE
+  *         @arg @ref LPTIM_UPDATE_MODE_ENDOFPERIOD
+  */
+uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_RELOAD));
+}
+
+/**
+  * @brief  Set the auto reload value
+  * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
+  * @note After a write to the LPTIMx_ARR register a new write operation to the
+  *       same register can only be performed when the previous write operation
+  *       is completed. Any successive write before  the ARROK flag be set, will
+  *       lead to unpredictable results.
+  * @note autoreload value be strictly greater than the compare value.
+  * @rmtoll ARR          ARR           LPTIM_SetAutoReload
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload)
+{
+  MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARRVAL, AutoReload);
+}
+
+/**
+  * @brief  Get actual auto reload value
+  * @rmtoll ARR          ARR           LPTIM_GetAutoReload
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARRVAL));
+}
+
+/**
+  * @brief  Set the compare value
+  * @note After a write to the LPTIMx_CMP register a new write operation to the
+  *       same register can only be performed when the previous write operation
+  *       is completed. Any successive write before the CMPOK flag be set, will
+  *       lead to unpredictable results.
+  * @rmtoll CMP          CMP           LPTIM_SetCompare
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue)
+{
+  MODIFY_REG(LPTIMx->COMPx, LPTIM_COMP_CMPVAL, CompareValue);
+}
+
+/**
+  * @brief  Get actual compare value
+  * @rmtoll CMP          CMP           LPTIM_GetCompare
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->COMPx, LPTIM_COMP_CMPVAL));
+}
+
+/**
+  * @brief  Get actual counter value
+  * @note When the LPTIM instance is running with an asynchronous clock, reading
+  *       the LPTIMx_CNT register may return unreliable values. So in this case
+  *       it is necessary to perform two consecutive read accesses and verify
+  *       that the two returned values are identical.
+  * @rmtoll CNT          CNT           LPTIM_GetCounter
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Counter value
+  */
+uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNTVAL));
+}
+
+/**
+  * @brief  Set the counter mode (selection of the LPTIM counter clock source).
+  * @note The counter mode can be set only when the LPTIM instance is disabled.
+  * @rmtoll CFG         COUNTMODE     LPTIM_SetCounterMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LPTIM_COUNTER_MODE_INTERNAL
+  *         @arg @ref LPTIM_COUNTER_MODE_EXTERNAL
+  * @retval None
+  */
+void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CNTMEN, CounterMode);
+}
+
+/**
+  * @brief  Get the counter mode
+  * @rmtoll CFG         COUNTMODE     LPTIM_GetCounterMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LPTIM_COUNTER_MODE_INTERNAL
+  *         @arg @ref LPTIM_COUNTER_MODE_EXTERNAL
+  */
+uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CNTMEN));
+}
+
+/**
+  * @brief  Configure the LPTIM instance output (LPTIMx_OUT)
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note Regarding the LPTIM output polarity the change takes effect
+  *       immediately, so the output default value will change immediately after
+  *       the polarity is re-configured, even before the timer is enabled.
+  * @rmtoll CFG         WAVE          LPTIM_ConfigOutput\n
+  *         CFG         WAVPOL        LPTIM_ConfigOutput
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Waveform This parameter can be one of the following values:
+  *         @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM
+  *         @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR
+  *         @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE
+  * @retval None
+  */
+void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity)
+{
+  MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE | LPTIM_CFG_WAVEPOL, Waveform | Polarity);
+}
+
+/**
+  * @brief  Set  waveform shape
+  * @rmtoll CFG         WAVE          LPTIM_SetWaveform
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Waveform This parameter can be one of the following values:
+  *         @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM
+  *         @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE
+  * @retval None
+  */
+void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform)
+{
+  MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE, Waveform);
+}
+
+/**
+  * @brief  Get actual waveform shape
+  * @rmtoll CFG         WAVE          LPTIM_GetWaveform
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LPTIM_OUTPUT_WAVEFORM_PWM
+  *         @arg @ref LPTIM_OUTPUT_WAVEFORM_SETONCE
+  */
+uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVE));
+}
+
+/**
+  * @brief  Set  output polarity
+  * @rmtoll CFG         WAVPOL        LPTIM_SetPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR
+  *         @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE
+  * @retval None
+  */
+void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity)
+{
+  MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVEPOL, Polarity);
+}
+
+/**
+  * @brief  Get actual output polarity
+  * @rmtoll CFG         WAVPOL        LPTIM_GetPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LPTIM_OUTPUT_POLARITY_REGULAR
+  *         @arg @ref LPTIM_OUTPUT_POLARITY_INVERSE
+  */
+uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVEPOL));
+}
+
+/**
+  * @brief  Set actual prescaler division ratio.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note When the LPTIM is configured to be clocked by an internal clock source
+  *       and the LPTIM counter is configured to be updated by active edges
+  *       detected on the LPTIM external Input1, the internal clock provided to
+  *       the LPTIM must be not be prescaled.
+  * @rmtoll CFG         PRESC         LPTIM_SetPrescaler
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LPTIM_PRESCALER_DIV1
+  *         @arg @ref LPTIM_PRESCALER_DIV2
+  *         @arg @ref LPTIM_PRESCALER_DIV4
+  *         @arg @ref LPTIM_PRESCALER_DIV8
+  *         @arg @ref LPTIM_PRESCALER_DIV16
+  *         @arg @ref LPTIM_PRESCALER_DIV32
+  *         @arg @ref LPTIM_PRESCALER_DIV64
+  *         @arg @ref LPTIM_PRESCALER_DIV128
+  * @retval None
+  */
+void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler)
+{
+  MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPRE, Prescaler);
+}
+
+/**
+  * @brief  Get actual prescaler division ratio.
+  * @rmtoll CFG         PRESC         LPTIM_GetPrescaler
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LPTIM_PRESCALER_DIV1
+  *         @arg @ref LPTIM_PRESCALER_DIV2
+  *         @arg @ref LPTIM_PRESCALER_DIV4
+  *         @arg @ref LPTIM_PRESCALER_DIV8
+  *         @arg @ref LPTIM_PRESCALER_DIV16
+  *         @arg @ref LPTIM_PRESCALER_DIV32
+  *         @arg @ref LPTIM_PRESCALER_DIV64
+  *         @arg @ref LPTIM_PRESCALER_DIV128
+  */
+uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPRE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EF_Trigger_Configuration Trigger Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable the timeout function
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note The first trigger event will start the timer, any successive trigger
+  *       event will reset the counter and the timer will restart.
+  * @note The timeout value corresponds to the compare value; if no trigger
+  *       occurs within the expected time frame, the MCU is waked-up by the
+  *       compare match event.
+  * @rmtoll CFG         TIMOUT        LPTIM_EnableTimeout
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN);
+}
+
+/**
+  * @brief  Disable the timeout function
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note A trigger event arriving when the timer is already started will be
+  *       ignored.
+  * @rmtoll CFG         TIMOUT        LPTIM_DisableTimeout
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN);
+}
+
+/**
+  * @brief  Indicate whether the timeout function is enabled.
+  * @rmtoll CFG         TIMOUT        LPTIM_IsEnabledTimeout
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN) == LPTIM_CFG_TIMOUTEN)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Start the LPTIM counter
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFG         TRIGEN        LPTIM_TrigSw
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_TrigSw(LPTIM_Module *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN);
+}
+
+/**
+  * @brief  Configure the external trigger used as a trigger event for the LPTIM.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note An internal clock source must be present when a digital filter is
+  *       required for the trigger.
+  * @rmtoll CFG         TRIGSEL       LPTIM_ConfigTrigger\n
+  *         CFG         TRGFLT        LPTIM_ConfigTrigger\n
+  *         CFG         TRIGEN        LPTIM_ConfigTrigger
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LPTIM_TRIG_SOURCE_GPIO
+  *         @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA
+  *         @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB
+  *         @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
+  *         @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2
+  *         @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
+  *         @arg @ref LPTIM_TRIG_SOURCE_COMP1
+  *         @arg @ref LPTIM_TRIG_SOURCE_COMP2
+  *
+  *         (*)  Value not defined in all devices. \n
+  *
+  * @param  Filter This parameter can be one of the following values:
+  *         @arg @ref LPTIM_TRIG_FILTER_NONE
+  *         @arg @ref LPTIM_TRIG_FILTER_2
+  *         @arg @ref LPTIM_TRIG_FILTER_4
+  *         @arg @ref LPTIM_TRIG_FILTER_8
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LPTIM_TRIG_POLARITY_RISING
+  *         @arg @ref LPTIM_TRIG_POLARITY_FALLING
+  *         @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING
+  * @retval None
+  */
+void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
+{
+  MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_TRGSEL | LPTIM_CFG_TRIGFLT | LPTIM_CFG_TRGEN, Source | Filter | Polarity);
+}
+
+/**
+  * @brief  Get actual external trigger source.
+  * @rmtoll CFG         TRIGSEL       LPTIM_GetTriggerSource
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LPTIM_TRIG_SOURCE_GPIO
+  *         @arg @ref LPTIM_TRIG_SOURCE_RTCALARMA
+  *         @arg @ref LPTIM_TRIG_SOURCE_RTCALARMB
+  *         @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP1 (*)
+  *         @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP2
+  *         @arg @ref LPTIM_TRIG_SOURCE_RTCTAMP3 (*)
+  *         @arg @ref LPTIM_TRIG_SOURCE_COMP1
+  *         @arg @ref LPTIM_TRIG_SOURCE_COMP2
+  *
+  *         (*)  Value not defined in all devices. \n
+  *
+  */
+uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGSEL));
+}
+
+/**
+  * @brief  Get actual external trigger filter.
+  * @rmtoll CFG         TRGFLT        LPTIM_GetTriggerFilter
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LPTIM_TRIG_FILTER_NONE
+  *         @arg @ref LPTIM_TRIG_FILTER_2
+  *         @arg @ref LPTIM_TRIG_FILTER_4
+  *         @arg @ref LPTIM_TRIG_FILTER_8
+  */
+uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRIGFLT));
+}
+
+/**
+  * @brief  Get actual external trigger polarity.
+  * @rmtoll CFG         TRIGEN        LPTIM_GetTriggerPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LPTIM_TRIG_POLARITY_RISING
+  *         @arg @ref LPTIM_TRIG_POLARITY_FALLING
+  *         @arg @ref LPTIM_TRIG_POLARITY_RISING_FALLING
+  */
+uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EF_Clock_Configuration Clock Configuration
+  * @{
+  */
+
+/**
+  * @brief  Set the source of the clock used by the LPTIM instance.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFG         CKSEL         LPTIM_SetClockSource
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LPTIM_CLK_SOURCE_INTERNAL
+  *         @arg @ref LPTIM_CLK_SOURCE_EXTERNAL
+  * @retval None
+  */
+void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKSEL, ClockSource);
+}
+
+/**
+  * @brief  Get actual LPTIM instance clock source.
+  * @rmtoll CFG         CKSEL         LPTIM_GetClockSource
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LPTIM_CLK_SOURCE_INTERNAL
+  *         @arg @ref LPTIM_CLK_SOURCE_EXTERNAL
+  */
+uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKSEL));
+}
+
+/**
+  * @brief  Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note When both external clock signal edges are considered active ones,
+  *       the LPTIM must also be clocked by an internal clock source with a
+  *       frequency equal to at least four times the external clock frequency.
+  * @note An internal clock source must be present when a digital filter is
+  *       required for external clock.
+  * @rmtoll CFG         CKFLT         LPTIM_ConfigClock\n
+  *         CFG         CKPOL         LPTIM_ConfigClock
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  ClockFilter This parameter can be one of the following values:
+  *         @arg @ref LPTIM_CLK_FILTER_NONE
+  *         @arg @ref LPTIM_CLK_FILTER_2
+  *         @arg @ref LPTIM_CLK_FILTER_4
+  *         @arg @ref LPTIM_CLK_FILTER_8
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LPTIM_CLK_POLARITY_RISING
+  *         @arg @ref LPTIM_CLK_POLARITY_FALLING
+  *         @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING
+  * @retval None
+  */
+void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
+{
+  MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKFLT | LPTIM_CFG_CLKPOL, ClockFilter | ClockPolarity);
+}
+
+/**
+  * @brief  Get actual clock polarity
+  * @rmtoll CFG         CKPOL         LPTIM_GetClockPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LPTIM_CLK_POLARITY_RISING
+  *         @arg @ref LPTIM_CLK_POLARITY_FALLING
+  *         @arg @ref LPTIM_CLK_POLARITY_RISING_FALLING
+  */
+uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL));
+}
+
+/**
+  * @brief  Get actual clock digital filter
+  * @rmtoll CFG         CKFLT         LPTIM_GetClockFilter
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LPTIM_CLK_FILTER_NONE
+  *         @arg @ref LPTIM_CLK_FILTER_2
+  *         @arg @ref LPTIM_CLK_FILTER_4
+  *         @arg @ref LPTIM_CLK_FILTER_8
+  */
+uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKFLT));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EF_Encoder_Mode Encoder Mode
+  * @{
+  */
+
+/**
+  * @brief  Configure the encoder mode.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFG         CKPOL         LPTIM_SetEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LPTIM_ENCODER_MODE_RISING
+  *         @arg @ref LPTIM_ENCODER_MODE_FALLING
+  *         @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING
+  * @retval None
+  */
+void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPOL, EncoderMode);
+}
+
+/**
+  * @brief  Get actual encoder mode.
+  * @rmtoll CFG         CKPOL         LPTIM_GetEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LPTIM_ENCODER_MODE_RISING
+  *         @arg @ref LPTIM_ENCODER_MODE_FALLING
+  *         @arg @ref LPTIM_ENCODER_MODE_RISING_FALLING
+  */
+uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL));
+}
+
+/**
+  * @brief  Enable the encoder mode
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note In this mode the LPTIM instance must be clocked by an internal clock
+  *       source. Also, the prescaler division ratio must be equal to 1.
+  * @note LPTIM instance must be configured in continuous mode prior enabling
+  *       the encoder mode.
+  * @rmtoll CFG         ENC           LPTIM_EnableEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->CFG, LPTIM_CFG_ENC);
+}
+/**
+  * @brief  Enable the encoder mode
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note In this mode the LPTIM instance must be clocked by an internal clock
+  *       source. Also, the prescaler division ratio must be equal to 1.
+  * @note LPTIM instance must be configured in continuous mode prior enabling
+  *       the encoder mode.
+  * @rmtoll CFG         ENC           LPTIM_EnableEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->CFG, LPTIM_CFG_NENC);
+}
+/**
+  * @brief  Disable the encoder mode
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFG         ENC           LPTIM_DisableEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_ENC);
+}
+
+/**
+  * @brief  Indicates whether the LPTIM operates in encoder mode.
+  * @rmtoll CFG         ENC           LPTIM_IsEnabledEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_ENC) == LPTIM_CFG_ENC)? 1UL : 0UL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear the compare match flag (CMPMCF)
+  * @rmtoll ICR          CMPMCF        LPTIM_ClearFLAG_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPMCF);
+}
+
+/**
+  * @brief  Inform application whether a compare match interrupt has occurred.
+  * @rmtoll ISR          CMPM          LPTIM_IsActiveFlag_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPM) ==LPTIM_INTSTS_CMPM)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the autoreload match flag (ARRMCF)
+  * @rmtoll ICR          ARRMCF        LPTIM_ClearFLAG_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRMCF);
+}
+
+/**
+  * @brief  Inform application whether a autoreload match interrupt has occured.
+  * @rmtoll ISR          ARRM          LPTIM_IsActiveFlag_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRM) ==LPTIM_INTSTS_ARRM)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the external trigger valid edge flag(EXTTRIGCF).
+  * @rmtoll ICR          EXTTRIGCF     LPTIM_ClearFlag_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_EXTRIGCF);
+}
+
+/**
+  * @brief  Inform application whether a valid edge on the selected external trigger input has occurred.
+  * @rmtoll ISR          EXTTRIG       LPTIM_IsActiveFlag_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_EXTRIG) ==LPTIM_INTSTS_EXTRIG)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the compare register update interrupt flag (CMPOKCF).
+  * @rmtoll ICR          CMPOKCF       LPTIM_ClearFlag_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_CMPUPDCF);
+}
+
+/**
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
+  * @rmtoll ISR          CMPOK         LPTIM_IsActiveFlag_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_CMPUPD) ==LPTIM_INTSTS_CMPUPD)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the autoreload register update interrupt flag (ARROKCF).
+  * @rmtoll ICR          ARROKCF       LPTIM_ClearFlag_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_ARRUPDCF);
+}
+
+/**
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
+  * @rmtoll ISR          ARROK         LPTIM_IsActiveFlag_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_ARRUPD) ==LPTIM_INTSTS_ARRUPD)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the counter direction change to up interrupt flag (UPCF).
+  * @rmtoll ICR          UPCF          LPTIM_ClearFlag_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_UPCF);
+}
+
+/**
+  * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
+  * @rmtoll ISR          UP            LPTIM_IsActiveFlag_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTSTS, LPTIM_INTSTS_UP) == LPTIM_INTSTS_UP)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the counter direction change to down interrupt flag (DOWNCF).
+  * @rmtoll ICR          DOWNCF        LPTIM_ClearFlag_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTCLR, LPTIM_INTCLR_DOWNCF);
+}
+
+/**
+  * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
+  * @rmtoll ISR          DOWN          LPTIM_IsActiveFlag_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTSTS,LPTIM_INTSTS_DOWN) ==LPTIM_INTSTS_DOWN)? 1UL : 0UL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EF_IT_Management Interrupt Management
+  * @{
+  */
+
+/**
+  * @brief  Enable compare match interrupt (CMPMIE).
+  * @rmtoll IER          CMPMIE        LPTIM_EnableIT_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE);
+}
+
+/**
+  * @brief  Disable compare match interrupt (CMPMIE).
+  * @rmtoll IER          CMPMIE        LPTIM_DisableIT_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE);
+}
+
+/**
+  * @brief  Indicates whether the compare match interrupt (CMPMIE) is enabled.
+  * @rmtoll IER          CMPMIE        LPTIM_IsEnabledIT_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPMIE) == LPTIM_INTEN_CMPMIE)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable autoreload match interrupt (ARRMIE).
+  * @rmtoll IER          ARRMIE        LPTIM_EnableIT_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE);
+}
+
+/**
+  * @brief  Disable autoreload match interrupt (ARRMIE).
+  * @rmtoll IER          ARRMIE        LPTIM_DisableIT_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE);
+}
+
+/**
+  * @brief  Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
+  * @rmtoll IER          ARRMIE        LPTIM_IsEnabledIT_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRMIE) == LPTIM_INTEN_ARRMIE)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable external trigger valid edge interrupt (EXTTRIGIE).
+  * @rmtoll IER          EXTTRIGIE     LPTIM_EnableIT_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE);
+}
+
+/**
+  * @brief  Disable external trigger valid edge interrupt (EXTTRIGIE).
+  * @rmtoll IER          EXTTRIGIE     LPTIM_DisableIT_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE);
+}
+
+/**
+  * @brief  Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
+  * @rmtoll IER          EXTTRIGIE     LPTIM_IsEnabledIT_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_EXTRIGIE) == LPTIM_INTEN_EXTRIGIE)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable compare register write completed interrupt (CMPOKIE).
+  * @rmtoll IER          CMPOKIE       LPTIM_EnableIT_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE);
+}
+
+/**
+  * @brief  Disable compare register write completed interrupt (CMPOKIE).
+  * @rmtoll IER          CMPOKIE       LPTIM_DisableIT_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE);
+}
+
+/**
+  * @brief  Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
+  * @rmtoll IER          CMPOKIE       LPTIM_IsEnabledIT_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_CMPUPDIE) == LPTIM_INTEN_CMPUPDIE)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable autoreload register write completed interrupt (ARROKIE).
+  * @rmtoll IER          ARROKIE       LPTIM_EnableIT_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE);
+}
+
+/**
+  * @brief  Disable autoreload register write completed interrupt (ARROKIE).
+  * @rmtoll IER          ARROKIE       LPTIM_DisableIT_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE);
+}
+
+/**
+  * @brief  Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
+  * @rmtoll IER          ARROKIE       LPTIM_IsEnabledIT_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_ARRUPDIE) == LPTIM_INTEN_ARRUPDIE)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable direction change to up interrupt (UPIE).
+  * @rmtoll IER          UPIE          LPTIM_EnableIT_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE);
+}
+
+/**
+  * @brief  Disable direction change to up interrupt (UPIE).
+  * @rmtoll IER          UPIE          LPTIM_DisableIT_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE);
+}
+
+/**
+  * @brief  Indicates whether the direction change to up interrupt (UPIE) is enabled.
+  * @rmtoll IER          UPIE          LPTIM_IsEnabledIT_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_UPIE) == LPTIM_INTEN_UPIE)? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable direction change to down interrupt (DOWNIE).
+  * @rmtoll IER          DOWNIE        LPTIM_EnableIT_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx)
+{
+  SET_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE);
+}
+
+/**
+  * @brief  Disable direction change to down interrupt (DOWNIE).
+  * @rmtoll IER          DOWNIE        LPTIM_DisableIT_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE);
+}
+
+/**
+  * @brief  Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
+  * @rmtoll IER          DOWNIE        LPTIM_IsEnabledIT_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx)
+{
+  return ((READ_BIT(LPTIMx->INTEN, LPTIM_INTEN_DOWNIE) == LPTIM_INTEN_DOWNIE)? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+
+//#endif /* LPTIM */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/
+

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lpuart.c

@@ -0,0 +1,532 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_lpuart.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_lpuart.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup LPUART
+ * @brief LPUART driver modules
+ * @{
+ */
+
+/** @addtogroup LPUART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Defines
+ * @{
+ */
+
+#define STS_CLR_MASK        ((uint16_t)0x01BF) /*!< LPUART STS Mask */
+
+#define INTEN_CLR_MASK      ((uint16_t)0x0000) /*!< LPUART INTEN Mask */
+#define INT_MASK            ((uint16_t)0x007F) /*!< LPUART Interrupt Mask */
+
+#define CTRL_CLR_MASK       ((uint16_t)0x70F4) /*!< LPUART CTRL Mask */
+#define CTRL_SMPCNT_MASK        ((uint16_t)0x3FFF) /*!< LPUART Sampling Method Mask */
+#define CTRL_WUSTP_MASK         ((uint16_t)0x4FFF) /*!< LPUART WakeUp Method Mask */
+#define CTRL_WUSTP_SET          ((uint16_t)0x0080) /*!< LPUART stop mode Enable Mask */
+#define CTRL_WUSTP_RESET        ((uint16_t)0x7F7F) /*!< LPUART stop mode Disable Mask */
+#define CTRL_LOOPBACK_SET   ((uint16_t)0x0010) /*!< LPUART Loopback Test Enable Mask */
+#define CTRL_LOOPBACK_RESET ((uint16_t)0xFFEF) /*!< LPUART Loopback Test Disable Mask */
+#define CTRL_FLUSH_SET          ((uint16_t)0x0004) /*!< LPUART Flush Receiver FIFO Enable Mask */
+#define CTRL_FLUSH_RESET        ((uint16_t)0x7FFB) /*!< LPUART Flush Receiver FIFO Disable Mask */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup LPUART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the LPUART peripheral registers to their default reset values.
+ */
+void LPUART_DeInit(void)
+{
+    RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, ENABLE);
+    RCC_EnableRETPeriphReset(RCC_RET_PERIPH_LPUART, DISABLE);
+}
+
+/**
+ * @brief  Initializes the LPUART peripheral according to the specified
+ *         parameters in the LPUART_InitStruct.
+ * @param LPUART_InitStruct pointer to a LPUART_InitType structure
+ *         that contains the configuration information for the specified LPUART
+ *         peripheral.
+ */
+void LPUART_Init(LPUART_InitType* LPUART_InitStruct)
+{
+    uint32_t tmpregister = 0x00, clocksrc = 0x00, apbclock = 0x00;
+    uint32_t integerdivider    = 0x00;
+    uint32_t fractionaldivider = 0x00;
+    uint32_t tmpdivider = 0x00, lastdivider = 0x00, i = 0x00;
+    RCC_ClocksType RCC_ClocksStatus;
+
+    /* Check the parameters */
+    // assert_param(IS_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
+    assert_param(IS_LPUART_PARITY(LPUART_InitStruct->Parity));
+    assert_param(IS_LPUART_MODE(LPUART_InitStruct->Mode));
+    assert_param(IS_LPUART_RTSTHRESHOLD(LPUART_InitStruct->RtsThreshold));
+    assert_param(IS_LPUART_HARDWARE_FLOW_CONTROL(LPUART_InitStruct->HardwareFlowControl));
+
+    // 时钟源判断，波特率范围
+
+    /*---------------------------- LPUART CTRL Configuration -----------------------*/
+    tmpregister = LPUART->CTRL;
+    /* Clear FC_RXEN, FC_TXEN, RTS_THSEL[1:0], PCDIS, TRS and PSEL bits */
+    tmpregister &= CTRL_CLR_MASK;
+    /* Configure the LPUART Parity, Mode, RtsThrehold and HardwareFlowControl ----------------------- */
+    /* Set PCDIS and PSEL bits according to Parity value */
+    /* Set the TRS bit according to Mode */
+    /* Set RTS_THSEL[1:0] bits according to RtsThrehold */
+    /* Set FC_RXEN and FC_TXEN bits according to HardwareFlowControl */
+    tmpregister |= (uint32_t)LPUART_InitStruct->Parity | LPUART_InitStruct->Mode | LPUART_InitStruct->RtsThreshold | LPUART_InitStruct->HardwareFlowControl;
+    /* Write to LPUART CTRL */
+    LPUART->CTRL = (uint16_t)tmpregister;
+
+    /*---------------------------- LPUART BRCFG1 & 2 Configuration -----------------------*/
+    /* Configure the LPUART Baud Rate -------------------------------------------*/
+    clocksrc = RCC_GetLPUARTClkSrc();
+    if (clocksrc == RCC_LPUARTCLK_SRC_LSE)
+    {
+        apbclock = 0x8000; // 32.768kHz
+    }
+    else if (clocksrc == RCC_LPUARTCLK_SRC_HSI)
+    {
+        apbclock = 0xF42400; // 16MHz
+    }
+    else if (clocksrc == RCC_LPUARTCLK_SRC_SYSCLK)
+    {
+        RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+        apbclock = RCC_ClocksStatus.SysclkFreq;
+    }
+    else //(clocksrc ==RCC_LPUARTCLK_SRC_APB1)
+    {
+        RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+        apbclock = RCC_ClocksStatus.Pclk1Freq;
+    }
+
+    /* Determine the integer part */
+    integerdivider = apbclock / (LPUART_InitStruct->BaudRate);
+
+    /* Configure sampling method */
+    if (integerdivider <= 10)
+    {
+        LPUART_ConfigSamplingMethod(LPUART_SMPCNT_1B);
+    }
+    else
+    {
+        LPUART_ConfigSamplingMethod(LPUART_SMPCNT_3B);
+    }
+
+    /* Check baudrate */
+    assert_param(IS_LPUART_BAUDRATE(integerdivider));
+    /* Write to LPUART BRCFG1 */
+    LPUART->BRCFG1 = (uint16_t)integerdivider;
+
+    /* Determine the fractional part */
+    fractionaldivider = ((apbclock % (LPUART_InitStruct->BaudRate)) * 10000) / (LPUART_InitStruct->BaudRate);
+
+    tmpregister = 0x00;
+    tmpdivider = fractionaldivider;
+    /* Implement the fractional part in the register */
+    for( i = 0; i < 8; i++)
+    {
+        lastdivider = tmpdivider;
+        tmpdivider = lastdivider + fractionaldivider;
+        if ((tmpdivider / 10000) ^ (lastdivider / 10000))
+        {
+            tmpregister |= (0x01 << i);
+        }
+    }
+    /* Write to LPUART BRCFG2 */
+    LPUART->BRCFG2 = (uint8_t)tmpregister;
+}
+
+/**
+ * @brief  Fills each LPUART_InitStruct member with its default value.
+ * @param LPUART_InitStruct pointer to a LPUART_InitType structure
+ *         which will be initialized.
+ */
+void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct)
+{
+    /* LPUART_InitStruct members default value */
+    LPUART_InitStruct->BaudRate            = 9600;
+    LPUART_InitStruct->Parity              = LPUART_PE_NO;
+    LPUART_InitStruct->Mode                = LPUART_MODE_RX | LPUART_MODE_TX;
+    LPUART_InitStruct->RtsThreshold        = LPUART_RTSTH_FIFOFU;
+    LPUART_InitStruct->HardwareFlowControl = LPUART_HFCTRL_NONE;
+}
+
+/**
+ * @brief  Flushes Receiver FIFO.
+ */
+void LPUART_FlushRxFifo(void)
+{
+    /* Clear LPUART Flush Receiver FIFO */
+    LPUART->CTRL |= CTRL_FLUSH_SET;
+    while (LPUART_GetFlagStatus(LPUART_FLAG_FIFO_NE) != RESET)
+    {
+    }
+    LPUART->CTRL &= CTRL_FLUSH_RESET;
+}
+
+/**
+ * @brief  Enables or disables the specified LPUART interrupts.
+ * @param LPUART_INT specifies the LPUART interrupt sources to be enabled or disabled.
+ *   This parameter can be one of the following values:
+ *     @arg LPUART_INT_WUF Wake-Up Interrupt
+ *     @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt
+ *     @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt
+ *     @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable
+ *     @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt
+ *     @arg LPUART_INT_TXC TX Complete Interrupt
+ *     @arg LPUART_INT_PE Parity Check Error Interrupt
+ * @param Cmd new state of the specified LPUART interrupts.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_LPUART_CFG_INT(LPUART_INT));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+       LPUART->INTEN |= (uint8_t)LPUART_INT;
+    }
+    else
+    {
+        LPUART->INTEN &= (uint8_t)(~LPUART_INT);
+    }
+}
+
+/**
+ * @brief  Enables or disables the LPUART's DMA interface.
+ * @param LPUART_DMAReq specifies the DMA request.
+ *   This parameter can be any combination of the following values:
+ *     @arg LPUART_DMAREQ_TX LPUART DMA transmit request
+ *     @arg LPUART_DMAREQ_RX LPUART DMA receive request
+ * @param Cmd new state of the DMA Request sources.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_LPUART_DMAREQ(LPUART_DMAReq));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the DMA transfer by setting the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */
+        LPUART->CTRL |= LPUART_DMAReq;
+    }
+    else
+    {
+        /* Disable the DMA transfer by clearing the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */
+        LPUART->CTRL &= (uint16_t)(~LPUART_DMAReq);
+    }
+}
+
+/**
+ * @brief  Selects the LPUART WakeUp method.
+ * @param LPUART_WakeUpMethod specifies the LPUART wakeup method.
+ *   This parameter can be one of the following values:
+ *     @arg LPUART_WUSTP_STARTBIT WakeUp by Start Bit Detection
+ *     @arg LPUART_WUSTP_RXNE WakeUp by RXNE Detection
+ *     @arg LPUART_WUSTP_BYTE WakeUp by A Configurable Received Byte
+ *     @arg LPUART_WUSTP_FRAME WakeUp by A Programmed 4-Byte Frame
+ */
+void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod)
+{
+    /* Check the parameters */
+    assert_param(IS_LPUART_WAKEUP(LPUART_WakeUpMethod));
+
+    LPUART->CTRL &= CTRL_WUSTP_MASK;
+    LPUART->CTRL |= LPUART_WakeUpMethod;
+}
+
+/**
+ * @brief  Enables or disables LPUART Wakeup in STOP2 mode.
+ * @param Cmd new state of the LPUART Wakeup in STOP2 mode.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_EnableWakeUpStop(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable Wakeup in STOP2 mode by setting the WUSTP bit in the CTRL register */
+        LPUART->CTRL |= CTRL_WUSTP_SET;
+    }
+    else
+    {
+        /* Disable Wakeup in STOP2 mode by clearing the WUSTP bit in the CTRL register */
+        LPUART->CTRL &= CTRL_WUSTP_RESET;
+    }
+}
+
+/**
+ * @brief  Selects the LPUART Sampling method.
+ * @param LPUART_SamplingMethod specifies the LPAURT sampling method.
+ *   This parameter can be one of the following values:
+ *     @arg LPUART_SMPCNT_3B 3 Sample bit
+ *     @arg LPUART_SMPCNT_1B 1 Sample bit
+ */
+void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod)
+{
+    /* Check the parameters */
+    assert_param(IS_LPUART_SAMPLING(LPUART_SamplingMethod));
+
+    LPUART->CTRL &= CTRL_SMPCNT_MASK;
+    LPUART->CTRL |= LPUART_SamplingMethod;
+}
+
+/**
+ * @brief  Enables or disables LPUART Loop Back Self-Test.
+ * @param Cmd new state of the LPUART Loop Back Self-Test.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void LPUART_EnableLoopBack(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable LPUART Loop Back Self-Test by setting the LOOKBACK bit in the CTRL register */
+        LPUART->CTRL |= CTRL_LOOPBACK_SET;
+    }
+    else
+    {
+        /* Disable LPUART Loop Back Self-Test by clearing the LOOKBACK bit in the CTRL register */
+        LPUART->CTRL &= CTRL_LOOPBACK_RESET;
+    }
+}
+
+/**
+ * @brief  Transmits single data through the LPUART peripheral.
+ * @param Data the data to transmit.
+ */
+void LPUART_SendData(uint8_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_LPUART_DATA(Data));
+
+    /* Transmit Data */
+    LPUART->DAT = (Data & (uint8_t)0xFF);
+}
+
+/**
+ * @brief  Returns the most recent received data by the LPUART peripheral.
+ * @return The received data.
+ */
+uint8_t LPUART_ReceiveData(void)
+{
+    /* Receive Data */
+    return (uint8_t)(LPUART->DAT & (uint8_t)0xFF);
+}
+
+/**
+ * @brief  SConfigures LPUART detected byte or frame match for wakeup CPU from STOPS mode.
+ * @param LPUART_WakeUpData specifies the LPUART detected byte or frame match for wakeup CPU from STOP2 mode.
+ */
+void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData)
+{
+    LPUART->WUDAT = LPUART_WakeUpData;
+}
+
+/**
+ * @brief  Checks whether the specified LPUART flag is set or not.
+ * @param LPUART_FLAG specifies the flag to check.
+ *   This parameter can be one of the following values:
+ *     @arg LPUART_FLAG_PEF Parity Check Error Flag.
+ *     @arg LPUART_FLAG_TXC TX Complete Flag.
+ *     @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag.
+ *     @arg LPUART_FLAG_FIFO_FU FIFO Full Flag.
+ *     @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag.
+ *     @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag.
+ *     @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag.
+ *     @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag.
+ *     @arg LPUART_FLAG_NF Noise Detection Flag.
+ * @return The new state of LPUART_FLAG (SET or RESET).
+ */
+FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_LPUART_FLAG(LPUART_FLAG));
+
+    if ((LPUART->STS & LPUART_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the LPUART's pending flags.
+ * @param LPUART_FLAG specifies the flag to clear.
+ *   This parameter can be any combination of the following values:
+ *     @arg LPUART_FLAG_PEF Parity Check Error Flag.
+ *     @arg LPUART_FLAG_TXC TX Complete Flag.
+ *     @arg LPUART_FLAG_FIFO_OV FIFO Overflow Flag.
+ *     @arg LPUART_FLAG_FIFO_FU FIFO Full Flag.
+ *     @arg LPUART_FLAG_FIFO_HF FIFO Half Full Flag.
+ *     @arg LPUART_FLAG_FIFO_NE FIFO Non-Empty Flag.
+ *     @arg LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag.
+ *     @arg LPUART_FLAG_WUFWakeup from STOP2 mode Flag.
+ *     @arg LPUART_FLAG_NF Noise Detection Flag.
+ */
+void LPUART_ClrFlag(uint16_t LPUART_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_LPUART_CLEAR_FLAG(LPUART_FLAG));
+
+    LPUART->STS = (uint16_t)LPUART_FLAG;
+}
+
+/**
+ * @brief  Checks whether the specified LPUART interrupt has occurred or not.
+ * @param LPUART_INT specifies the LPUART interrupt source to check.
+ *   This parameter can be one of the following values:
+ *     @arg LPUART_INT_WUF Wake-Up Interrupt
+ *     @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt
+ *     @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt
+ *     @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable
+ *     @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt
+ *     @arg LPUART_INT_TXC TX Complete Interrupt
+ *     @arg LPUART_INT_PE Parity Check Error Interrupt
+ * @return The new state of LPUART_INT (SET or RESET).
+ */
+INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT)
+{
+    uint32_t bitpos = 0x00, itmask = 0x00;
+    INTStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_LPUART_GET_INT(LPUART_INT));
+
+    /* Get the interrupt position */
+    itmask = (uint8_t)(LPUART_INT >> 0x08) & INT_MASK;
+    itmask = (uint32_t)0x01 << itmask;
+    itmask &= LPUART->INTEN;
+
+    bitpos = ((uint8_t)LPUART_INT) & 0xFF;
+    if (LPUART_INT_WUF == LPUART_INT){
+        bitpos = (bitpos << 0x01);
+    }
+    bitpos &= LPUART->STS;
+    if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the LPUART's interrupt pending bits.
+ * @param LPUART_INT specifies the interrupt pending bit to clear.
+ *   This parameter can be one of the following values:
+ *     @arg LPUART_INT_WUF Wake-Up Interrupt
+ *     @arg LPUART_INT_FIFO_NE FIFO Non-Empty Interrupt
+ *     @arg LPUART_INT_FIFO_HF FIFO Half Full Interrupt
+ *     @arg LPUART_INT_FIFO_FU FIFO Full Interrupt Enable
+ *     @arg LPUART_INT_FIFO_OV FIFO Overflow Interrupt
+ *     @arg LPUART_INT_TXC TX Complete Interrupt
+ *     @arg LPUART_INT_PE Parity Check Error Interrupt
+ */
+void LPUART_ClrIntPendingBit(uint16_t LPUART_INT)
+{
+    uint16_t itmask = 0x00;
+    /* Check the parameters */
+    assert_param(IS_LPUART_CLR_INT(LPUART_INT));
+
+    itmask      = ((uint8_t)LPUART_INT) & 0xFF;
+    LPUART->STS = (uint16_t)itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_opamp.c

@@ -0,0 +1,198 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_opamp.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_opamp.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @brief OPAMP driver modules
+ * @{
+ */
+
+/** @addtogroup OPAMP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup OPAMP_Private_Functions
+ * @{
+ */
+#define SetBitMsk(reg, bit, msk) ((reg) = (((reg) & ~(msk)) | (bit)))
+#define ClrBit(reg, bit)         ((reg) &= ~(bit))
+#define SetBit(reg, bit)         ((reg) |= (bit))
+#define GetBit(reg, bit)         ((reg) & (bit))
+/**
+ * @brief  Deinitializes the OPAMP peripheral registers to their default reset values.
+ */
+void OPAMP_DeInit(void)
+{
+    RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, ENABLE);
+    RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_OPAMP, DISABLE);
+}
+void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct)
+{
+    OPAMP_InitStruct->Opa2SrcSel        = OPAMP2_CS_TIMSRCSEL_TIM1CC6;
+    OPAMP_InitStruct->Gain              = OPAMP_CS_PGA_GAIN_2;
+    OPAMP_InitStruct->HighVolRangeEn    = ENABLE;
+    OPAMP_InitStruct->TimeAutoMuxEn     = DISABLE;
+    OPAMP_InitStruct->Mod               = OPAMP_CS_PGA_EN;
+}
+void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct)
+{
+    __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+    __IO uint32_t tmp  = *pCs;
+    if (OPAMPx == OPAMP2)
+        SetBitMsk(tmp, OPAMP_InitStruct->Opa2SrcSel, OPAMP_CS_OPAMP2_TIMSRCSEL);
+    SetBitMsk(tmp, OPAMP_InitStruct->Gain, OPAMP_CS_PGA_GAIN_MASK);
+        if (OPAMP_InitStruct->HighVolRangeEn==ENABLE)
+            SetBitMsk(tmp, OPAMP_CS_RANGE_MASK, OPAMP_CS_RANGE_MASK);
+        else
+            ClrBit(tmp,OPAMP_CS_RANGE_MASK);
+        if (OPAMP_InitStruct->TimeAutoMuxEn==ENABLE)
+            SetBitMsk(tmp,OPAMP_CS_TCMEN_MASK, OPAMP_CS_TCMEN_MASK);
+        else
+            ClrBit(tmp,OPAMP_CS_TCMEN_MASK);
+    SetBitMsk(tmp, OPAMP_InitStruct->Mod, OPAMP_CS_MOD_MASK);
+    *pCs = tmp;
+}
+void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en)
+{
+    __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+    if (en)
+        SetBit(*pCs, OPAMP_CS_EN_MASK);
+    else
+        ClrBit(*pCs, OPAMP_CS_EN_MASK);
+}
+
+void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain)
+{
+    __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+    __IO uint32_t tmp  = *pCs;
+    SetBitMsk(tmp, Gain, OPAMP_CS_PGA_GAIN_MASK);
+    *pCs = tmp;
+}
+void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel)
+{
+    __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+    __IO uint32_t tmp  = *pCs;
+    SetBitMsk(tmp, VpSSel, OPAMP_CS_VPSEL_SECOND_MASK);
+    *pCs = tmp;
+}
+void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel)
+{
+    __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+    __IO uint32_t tmp  = *pCs;
+    SetBitMsk(tmp, VmSSel, OPAMP_CS_VMSEL_SECOND_MASK);
+    *pCs = tmp;
+}
+void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel)
+{
+    __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+    __IO uint32_t tmp  = *pCs;
+    SetBitMsk(tmp, VpSel, OPAMP_CS_VPSEL_MASK);
+    *pCs = tmp;
+}
+void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel)
+{
+    __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+    __IO uint32_t tmp  = *pCs;
+    SetBitMsk(tmp, VmSel, OPAMP_CS_VMSEL_MASK);
+    *pCs = tmp;
+}
+bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx)
+{
+    __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+    return (GetBit(*pCs, OPAMP_CS_CALOUT_MASK)) ? true : false;
+}
+void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en)
+{
+    __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
+    if (en)
+        SetBit(*pCs, OPAMP_CS_CALON_MASK);
+    else
+        ClrBit(*pCs, OPAMP_CS_CALON_MASK);
+}
+// Lock see @OPAMP_LOCK
+void OPAMP_SetLock(uint32_t Lock)
+{
+    OPAMP->LOCK = Lock;
+}
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_pwr.c

@@ -0,0 +1,576 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_pwr.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_pwr.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @brief PWR driver modules
+ * @{
+ */
+
+/** @addtogroup PWR_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Defines
+ * @{
+ */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of DBKP bit */
+#define CTRL_OFFSET  (PWR_OFFSET + 0x00)
+#define DBKP_BITN    0x08
+#define CTRL_DBKP_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (DBKP_BITN * 4))
+
+/* Alias word address of PVDEN bit */
+#define PVDEN_BITN    0x04
+#define CTRL_PVDEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PVDEN_BITN * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of WKUPEN bit */
+#define CTRLSTS_OFFSET    (PWR_OFFSET + 0x04)
+#define WKUPEN_BITN       0x08
+#define CTRLSTS_WKUPEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (WKUPEN_BITN * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+
+void SetSysClock_MSI(void);
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the PWR peripheral registers to their default reset values.
+ */
+void PWR_DeInit(void)
+{
+    RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, ENABLE);
+    RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, DISABLE);
+}
+
+/**
+ * @brief  Enables or disables access to the RTC and backup registers.
+ * @param Cmd new state of the access to the RTC and backup registers.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_BackupAccessEnable(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    *(__IO uint32_t*)CTRL_DBKP_BB = (uint32_t)Cmd;
+}
+/**
+ * @brief  MR voltage selection.
+ * @param voltage value: 1.0V and 1.1V.
+ *   This parameter can be: MR_1V0 or MR_1V1.
+ */
+void PWR_MRconfig(uint8_t voltage)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = PWR->CTRL1;
+  /* Clear MRSEL bits */
+  tmpreg &= (~PWR_CTRL1_MRSELMASK);
+  /* Set voltage*/
+  tmpreg |= (uint32_t)(voltage << 9);
+  PWR->CTRL1 = tmpreg;
+}
+/**
+ * @brief  Get MR voltage value.
+ * @param voltage value: 1.0V and 1.1V.
+ * @return The value of voltage.
+ */
+uint8_t GetMrVoltage(void)
+{
+  uint8_t tmp = 0;
+
+  tmp = (uint8_t)((PWR->CTRL1 >> 9) & 0x03);//2bits
+  return tmp ;
+}
+/**
+ * @brief  Enables or disables the Power Voltage Detector(PVD).
+ * @param Cmd new state of the PVD.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_PvdEnable(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    //*(__IO uint32_t*)CTRL_PVDEN_BB = (uint32_t)Cmd; //Can not enable the PVD bit
+    PWR->CTRL2 |= Cmd;
+
+}
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param  PWR_PVDLevel: specifies the PVD detection level
+  *   This parameter can be one of the following values:
+  *     @arg PWR_CTRL2_PLS1: PVD detection level set to 2.1V
+  *     @arg PWR_CTRL2_PLS2: PVD detection level set to 2.25V
+  *     @arg PWR_CTRL2_PLS3: PVD detection level set to 2.4V
+  *     @arg PWR_CTRL2_PLS4: PVD detection level set to 2.55V
+  *     @arg PWR_CTRL2_PLS5: PVD detection level set to 2.7V
+  *     @arg PWR_CTRL2_PLS6: PVD detection level set to 2.85V
+  *     @arg PWR_CTRL2_PLS7: PVD detection level set to 2.95V
+  *     @arg PWR_CTRL2_PLS8: external input analog voltage PVD_IN (compared internally to VREFINT)
+  * @retval None
+  */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+    tmpregister = PWR->CTRL2;
+    /* Clear PLS[7:5] bits */
+    tmpregister &= (~PWR_CTRL2_PLSMASK);
+    /* Set PRS[7:5] bits according to PWR_PVDLevel value */
+    tmpregister |= PWR_PVDLevel;
+    /* Store the new value */
+    PWR->CTRL2 = tmpregister;
+}
+
+/**
+ * @brief  Enables or disables the WakeUp Pin functionality.
+ * @param Pin: which PIN  select to wakeup.
+ *   This parameter can be one of the following values:
+ *     @arg WAKEUP_PIN0
+ *     @arg WAKEUP_PIN1
+ *     @arg WAKEUP_PIN2
+ * @param Cmd new state of the WakeUp Pin functionality.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd)
+{
+    uint32_t Temp = 0;
+    Temp = PWR->CTRL3;
+    if (ENABLE==Cmd)
+    {
+       Temp &= (~(PWR_CTRL3_WKUP0EN|PWR_CTRL3_WKUP1EN|PWR_CTRL3_WKUP2EN));
+       Temp |= (WKUP_Pin);
+       PWR->CTRL3 = Temp;
+    }
+    else
+    {
+       Temp &= (~(WKUP_Pin));
+       PWR->CTRL3 = Temp;
+    }
+}
+
+
+
+
+/**
+  * @brief  Enters SLEEP mode.
+  * @param  SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode.
+  *   This parameter can be one of the following values:
+  *     @arg 0: SLEEP mode with SLEEPONEXIT disable
+  *     @arg 1: SLEEP mode with SLEEPONEXIT enable
+  * @param  PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+  *     @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
+
+  /* CLEAR SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+
+    /* Select SLEEPONEXIT mode entry --------------------------------------------------*/
+  if (SLEEPONEXIT == 1)
+  {
+    /* the MCU enters Sleep mode as soon as it exits the lowest priority ISR */
+    SCB->SCR |= SCB_SCR_SLEEPONEXIT;
+  }
+  else if (SLEEPONEXIT == 0)
+  {
+    /* Sleep-now */
+    SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPONEXIT);
+  }
+
+  /* Select SLEEP mode entry --------------------------------------------------*/
+  if (PWR_SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+}
+
+
+
+/**
+ * @brief  Enters STOP2 mode.
+ * @param PWR_STOPEntry specifies if STOP2 mode in entered with WFI or WFE instruction.
+ *   This parameter can be one of the following values:
+ *     @arg PWR_STOPENTRY_WFI enter STOP2 mode with WFI instruction
+ *     @arg PWR_STOPENTRY_WFE enter STOP2 mode with WFE instruction
+ * @param RetentionMode: PWR_CTRL3_RAM1RET or PWR_CTRL3_RAM2RET
+ */
+void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+  /* Wait MR Voltage Adjust Complete */
+  while ((PWR->STS2 &0X2) != 2);
+  tmpreg = PWR->CTRL3;
+  /* Clear SRAMRET bits */
+  tmpreg &= (~PWR_CTRL3_RAMRETMASK);
+  /* Set SRAM1/2 select */
+  tmpreg |= RetentionMode;
+  PWR->CTRL3 = tmpreg;
+  /* Select the regulator state in STOP2 mode ---------------------------------*/
+  tmpreg = PWR->CTRL1;
+  /* Clear LPMS bits */
+  tmpreg &= (~PWR_CTRL1_LPMSELMASK);
+  /* Set stop2 mode select */
+  tmpreg |= PWR_CTRL1_STOP2;
+  /* Store the new value */
+  PWR->CTRL1 = tmpreg;
+  /*Clear PWR_CTRL3_PBDTSTP2 for BOR always on*/
+  tmpreg = PWR->CTRL3;
+  tmpreg &= (~PWR_CTRL3_PBDTSTP2);
+  PWR->CTRL3 = tmpreg;
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+
+  /* Select STOP mode entry --------------------------------------------------*/
+  if (PWR_STOPEntry ==  PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+}
+
+
+/**
+  * @brief  Enters Low power run mode.
+  * @param
+  *     @arg
+  *     @arg
+  * @retval None
+  */
+void PWR_EnterLowPowerRunMode(void)
+{
+    uint32_t tmpreg = 0;
+
+    SetSysClock_MSI();
+    FLASH_SetLatency(FLASH_LATENCY_2);    //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed
+    //config FLASH enter the low power voltage mode
+    FLASH->AC |= FLASH_AC_LVMEN;
+    while ((FLASH->AC & FLASH_AC_LVMF) != FLASH_AC_LVMF);
+    FLASH_SetLatency(FLASH_LATENCY_0);    //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time.
+
+    _SetLprunSramVoltage(0);
+    _SetBandGapMode(0);
+    _SetPvdBorMode(0);
+    /* Select the regulator state in LPRUN mode ---------------------------------*/
+    tmpreg = PWR->CTRL1;
+    /* Clear LPMS bits */
+    tmpreg &= (~PWR_CTRL1_LPMSELMASK);
+    /* Set lpr to run the main power domain*/
+    tmpreg |= PWR_CTRL1_LPREN;
+    /* Store the new value */
+    PWR->CTRL1 = tmpreg;
+    /*Clear PWR_CTRL3_PBDTLPR for BOR always on*/
+    tmpreg = PWR->CTRL3;
+    tmpreg &= (~PWR_CTRL3_PBDTLPR);
+    PWR->CTRL3 = tmpreg;
+    while ((PWR->STS2 &PWR_STS2_LPRUNF) != 0);//LPRCNT flag ready
+}
+
+/**
+  * @brief  Enters Low power run mode.
+  * @param
+  *     @arg
+  *     @arg
+  * @retval None
+  */
+void PWR_ExitLowPowerRunMode(void)
+{
+    PWR->CTRL1 &= ~PWR_CTRL1_LPREN;
+    while ((PWR->STS2 &PWR_STS2_LPRUNF) != PWR_STS2_LPRUNF);
+    FLASH_SetLatency(FLASH_LATENCY_2);    //Configure the Flash read latency to be grater than 2, so LVE/SE timing requirement is guaranteed
+    FLASH->AC &= ~FLASH_AC_LVMEN;                  //clear LVMREQ
+    while ((FLASH->AC &FLASH_AC_LVMF) != 0);   //wait LVE is deasserted by polling the LVMVLD bit
+
+    FLASH_SetLatency(FLASH_LATENCY_0);    //Configure the latency of Flash read cycle to proper value which depends on the Flash read access time.
+}
+
+/**
+  * @brief  Enters LP_SLEEP mode.
+  * @param  SLEEPONEXIT: specifies the SLEEPONEXIT state in SLEEP mode.
+  *   This parameter can be one of the following values:
+  *     @arg 0: SLEEP mode with SLEEPONEXIT disable
+  *     @arg 1: SLEEP mode with SLEEPONEXIT enable
+  * @param  PWR_STOPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+  *     @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry)
+{
+  PWR_EnterLowPowerRunMode();
+  PWR_EnterSLEEPMode(SLEEPONEXIT, PWR_SLEEPEntry);
+}
+
+ /**
+  * @brief  Enters STANDBY mode.
+  * @param  PWR_STANDBYEntry: specifies if STANDBY mode in entered with WFI or WFE instruction.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_STANDBYEntry_WFI: enter STANDBY mode with WFI instruction
+  *     @arg PWR_CTRL3_RAM2RET: SRAM2 whether to retention
+  * @retval None
+  */
+void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret)
+{
+    uint32_t tmpreg;
+    /* Clear Wake-up flag */
+    PWR->STSCLR |= PWR_STSCLR_CLRWKUP0;
+    PWR->STSCLR |= PWR_STSCLR_CLRWKUP1;
+    PWR->STSCLR |= PWR_STSCLR_CLRWKUP2;
+    tmpreg = PWR->CTRL3;
+    /* Clear SRAMRET bits */
+    tmpreg &= (~PWR_CTRL3_RAMRETMASK);
+    /* Set SRAM1/2 select */
+    tmpreg |= Sam2Ret;
+    PWR->CTRL3 = tmpreg;
+
+    tmpreg = PWR->CTRL1;
+    /* Clear LPMS bits */
+    tmpreg &= (~PWR_CTRL1_LPMSELMASK);
+    /* Select STANDBY mode */
+    tmpreg |= PWR_CTRL1_STANDBY;
+    PWR->CTRL1 = tmpreg;
+    /*Clear PWR_CTRL3_PBDTSTBY for BOR always on*/
+    tmpreg = PWR->CTRL3;
+    tmpreg &= (~PWR_CTRL3_PBDTSTBY);
+    PWR->CTRL3 = tmpreg;
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP;
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM   )
+  __force_stores();
+#endif
+ /* Select STANDBY mode entry --------------------------------------------------*/
+  if (PWR_STANDBYEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+}
+
+
+
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_WKUP0_FLAG/PWR_WKUP1_FLAG/PWR_WKUP2_FLAG: Wake Up flag
+  *     @arg PWR_STBY_FLAG: StandBy flag
+  *     @arg PWR_LPRUN_FLAG: low power work flag
+  *     @arg PWR_MR_FLAG: MR work statue flag
+  *     @arg PWR_PVDO_FLAG: PVD output flag
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(uint8_t STS,uint32_t PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+  if (STS == 1)
+    {
+        if ((PWR->STS1 & PWR_FLAG) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+
+    }
+    else
+    {
+        if ((PWR->STS2 & PWR_FLAG) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+
+    }
+
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+ * @brief  Clears the PWR's pending flags.
+ * @param PWR_FLAG specifies the flag to clear.
+ *   This parameter can be one of the following values:
+  *     @arg PWR_WKUP1_FLAG/PWR_WKUP2_FLAG/PWR_WKUP3_FLAG: Wake Up flag
+  *     @arg PWR_STBY_FLAG: StandBy flag
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+    PWR->STSCLR |=  PWR_FLAG ;
+}
+
+
+/**
+ * @brief  set system clock with MSI.
+ * @param void.
+ */
+void SetSysClock_MSI(void)
+{
+     RCC_DeInit();
+
+    if (RESET == RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD))
+    {
+        /* Enable MSI and Config Clock */
+        RCC_ConfigMsi(RCC_MSI_ENABLE, RCC_MSI_RANGE_4M);
+        /* Waits for MSI start-up */
+        while (SUCCESS != RCC_WaitMsiStable());
+    }
+
+    /* Enable Prefetch Buffer */
+    FLASH_PrefetchBufSet(FLASH_PrefetchBuf_EN);
+
+    /* Select MSI as system clock source */
+    RCC_ConfigSysclk(RCC_SYSCLK_SRC_MSI);
+
+    /* Wait till MSI is used as system clock source */
+    while (RCC_GetSysclkSrc() != 0x00)
+    {
+    }
+
+    /* Flash 0 wait state */
+    //FLASH_SetLatency(FLASH_LATENCY_0);
+
+    /* HCLK = SYSCLK */
+    RCC_ConfigHclk(RCC_SYSCLK_DIV1);
+
+    /* PCLK2 = HCLK */
+    RCC_ConfigPclk2(RCC_HCLK_DIV1);
+
+    /* PCLK1 = HCLK */
+    RCC_ConfigPclk1(RCC_HCLK_DIV1);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rcc.c

@@ -0,0 +1,1940 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_rcc.c
+ * @author Nations
+ * @version v1.0.3
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @brief RCC driver modules
+ * @{
+ */
+
+/** @addtogroup RCC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* --- CTRL Register ---*/
+
+/* Alias word address of HSIEN bit */
+#define CTRL_OFFSET   (RCC_OFFSET + 0x00)
+#define HSIEN_BITN    0x00
+#define CTRL_HSIEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (HSIEN_BITN * 4))
+
+/* Alias word address of PLLEN bit */
+#define PLLEN_BITN    0x18
+#define CTRL_PLLEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PLLEN_BITN * 4))
+
+/* Alias word address of CLKSSEN bit */
+#define CLKSSEN_BITN    0x13
+#define CTRL_CLKSSEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (CLKSSEN_BITN * 4))
+
+/* --- CFG Register ---*/
+
+/* Alias word address of USBPRES bit */
+#define CFG_OFFSET (RCC_OFFSET + 0x04)
+
+#define USBPRES_BITN   0x16
+#define CFG_USBPRES_BB (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRES_BITN * 4))
+
+#define USBPRE_Bit1Number   0x17
+#define CFGR_USBPRE_BB_BIT1 (PERIPH_BB_BASE + (CFG_OFFSET * 32) + (USBPRE_Bit1Number * 4))
+
+/* --- CLKINT Register ---*/
+
+#define CLKINT_OFFSET (RCC_OFFSET + 0x08)
+
+/* Alias word address of LSIRDIF bit */
+#define LSIRDIF_BITN   0x00
+#define CLKINT_LSIRDIF_BB (PERIPH_BB_BASE + (CLKINT_OFFSET * 32) + (LSIRDIF_BITN * 4))
+
+/* --- LDCTRL Register ---*/
+
+/* Alias word address of LSECLKSSEN bit */
+#define LSECLKSSEN_BITN    0x03
+#define LDCTRL_LSECLKSSEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LSECLKSSEN_BITN * 4))
+
+/* Alias word address of RTCEN bit */
+#define LDCTRL_OFFSET   (RCC_OFFSET + 0x20)
+#define RTCEN_BITN       0x0F
+#define LDCTRL_RTCEN_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (RTCEN_BITN * 4))
+
+/* Alias word address of LDSFTRST bit */
+#define LDSFTRST_BITN      0x10
+#define LDCTRL_LDSFTRST_BB (PERIPH_BB_BASE + (LDCTRL_OFFSET * 32) + (LDSFTRST_BITN * 4))
+
+/* --- CTRLSTS Register ---*/
+
+/* Alias word address of LSIEN bit */
+#define CTRLSTS_OFFSET   (RCC_OFFSET + 0x24)
+#define LSIEN_BITNUMBER  0x00
+#define CTRLSTS_LSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (LSIEN_BITNUMBER * 4))
+
+/* Alias word address of MSIEN bit */
+#define MSIEN_BITNUMBER  0x02
+#define CTRLSTS_MSIEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (MSIEN_BITNUMBER * 4))
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#define CTRL_HSEBP_RESET  ((uint32_t)0xFFFBFFFF)
+#define CTRL_HSEBP_SET    ((uint32_t)0x00040000)
+#define CTRL_HSEEN_RESET  ((uint32_t)0xFFFEFFFF)
+#define CTRL_HSEEN_SET    ((uint32_t)0x00010000)
+#define CTRL_HSITRIM_MASK ((uint32_t)0xFFFFFF83)
+#define CTRL_HSIEN_RESET  ((uint32_t)0xFFFFFFFE)
+#define CTRL_HSIEN_SET    ((uint32_t)0x00000001)
+
+/* CTRLSTS register bit mask */
+#define CTRLSTS_MSITRIM_MASK   ((uint32_t)0xFF807FFF)
+#define CTRLSTS_MSIEN_RESET    ((uint32_t)0xFFFFFFFB)
+#define CTRLSTS_MSIEN_SET      ((uint32_t)0x00000004)
+
+#define CTRLSTS_MSIRANGE_MASK  ((uint32_t)0xFFFFFF8F)
+#define CTRLSTS_MSIRANGE_RESET ((uint32_t)0x00000060) /* 4MHz */
+
+/* CFG register bit mask */
+#define CFG_PLL_MASK ((uint32_t)0xF7C0FFFF)
+
+#define CFG_PLLMULFCT_MASK      ((uint32_t)0x083C0000)
+#define CFG_PLLSRC_MASK         ((uint32_t)0x00010000)
+#define CFG_PLLHSEPRES_MASK     ((uint32_t)0x00020000)
+#define CFG_SCLKSTS_MASK        ((uint32_t)0x0000000C)
+#define CFG_SCLKSW_MASK         ((uint32_t)0xFFFFFFFC)
+#define CFG_AHBPRES_RESET_MASK  ((uint32_t)0xFFFFFF0F)
+#define CFG_AHBPRES_SET_MASK    ((uint32_t)0x000000F0)
+#define CFG_APB1PRES_RESET_MASK ((uint32_t)0xFFFFF8FF)
+#define CFG_APB1PRES_SET_MASK   ((uint32_t)0x00000700)
+#define CFG_APB2PRES_RESET_MASK ((uint32_t)0xFFFFC7FF)
+#define CFG_APB2PRES_SET_MASK   ((uint32_t)0x00003800)
+
+/* CFG2 register bit mask */
+#define CFG2_TIM18CLKSEL_SET_MASK   ((uint32_t)0x20000000)
+#define CFG2_TIM18CLKSEL_RESET_MASK ((uint32_t)0xDFFFFFFF)
+#define CFG2_RNGCPRES_SET_MASK      ((uint32_t)0x1F000000)
+#define CFG2_RNGCPRES_RESET_MASK    ((uint32_t)0xE0FFFFFF)
+#define CFG2_ETHCLKSEL_SET_MASK     ((uint32_t)0x00100000)
+#define CFG2_ETHCLKSEL_RESET_MASK   ((uint32_t)0xFFEFFFFF)
+#define CFG2_ADC1MSEL_SET_MASK      ((uint32_t)0x00020000)
+#define CFG2_ADC1MSEL_RESET_MASK    ((uint32_t)0xFFFDFFFF)
+#define CFG2_ADC1MPRES_SET_MASK     ((uint32_t)0x0001F000)
+#define CFG2_ADC1MPRES_RESET_MASK   ((uint32_t)0xFFFE0FFF)
+#define CFG2_ADCPLLPRES_SET_MASK    ((uint32_t)0x000001F0)
+#define CFG2_ADCPLLPRES_RESET_MASK  ((uint32_t)0xFFFFFE0F)
+#define CFG2_ADCHPRES_SET_MASK      ((uint32_t)0x0000000F)
+#define CFG2_ADCHPRES_RESET_MASK    ((uint32_t)0xFFFFFFF0)
+
+/* CFG3 register bit mask */
+#define CFGR3_TRNG1MSEL_SET_MASK    ((uint32_t)0x00020000)
+#define CFGR3_TRNG1MSEL_RESET_MASK  ((uint32_t)0xFFFDFFFF)
+#define CFGR3_TRNG1MPRES_SET_MASK   ((uint32_t)0x0000F800)
+#define CFGR3_TRNG1MPRES_RESET_MASK ((uint32_t)0xFFFF07FF)
+
+/* CTRLSTS register bit mask */
+#define CSR_RMRSTF_SET ((uint32_t)0x01000000)
+#define CSR_RMVF_Reset ((uint32_t)0xfeffffff)
+
+/* RCC Flag Mask */
+#define FLAG_MASK ((uint8_t)0x1F)
+
+/* CLKINT register(Bits[31:0]) base address */
+#define CLKINT_ADDR ((uint32_t)0x40021008)
+
+/* LDCTRL register base address */
+#define LDCTRL_ADDR (PERIPH_BASE + LDCTRL_OFFSET)
+
+/* RDCTRL register bit mask */
+#define RDCTRL_LPTIMCLKSEL_MASK      ((uint32_t)0x00000007)
+#define RDCTRL_LPUARTCLKSEL_MASK     ((uint32_t)0x00000018)
+
+/* PLLHSIPRE register bit mask */
+#define PLLHSIPRE_PLLHSI_PRE_MASK    ((uint32_t)0x00000001)
+#define PLLHSIPRE_PLLSRCDIV_MASK     ((uint32_t)0x00000002)
+
+#define LSE_TRIMR_ADDR               ((uint32_t)0x40001808)
+
+#define LSE_GM_MASK_VALUE            (0x1FF)
+#define LSE_GM_MAX_VALUE             (0x1FF)
+#define LSE_GM_DEFAULT_VALUE         (0x1FF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Variables
+ * @{
+ */
+
+static const uint8_t s_ApbAhbPresTable[16]     = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static const uint8_t s_AdcHclkPresTable[16]    = {1, 2, 4, 6, 8, 10, 12, 16, 32, 32, 32, 32, 32, 32, 32, 32};
+static const uint16_t s_AdcPllClkPresTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 256, 256, 256, 256};
+static const uint32_t s_msiClockTable[7]       = {MSI_VALUE_L0, MSI_VALUE_L1, MSI_VALUE_L2, MSI_VALUE_L3,
+                                                  MSI_VALUE_L4, MSI_VALUE_L5, MSI_VALUE_L6};
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Resets the RCC clock configuration to the default reset state.
+ */
+void RCC_DeInit(void)
+{
+    /* Set MSIEN bit */
+    RCC->CTRLSTS |= (uint32_t)0x00000004;
+
+    /* Reset SW, HPRE, PPRE1, PPRE2 and MCO bits */
+    RCC->CFG &= (uint32_t)0xF8FFC000;
+
+    /* Reset HSIEN, HSEEN, CLKSSEN and PLLEN bits */
+    RCC->CTRL &= (uint32_t)0xFEF6FFFE;
+
+    /* Reset HSEBYP bit */
+    RCC->CTRL &= (uint32_t)0xFFFBFFFF;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES bits */
+    RCC->CFG &= (uint32_t)0xF700FFFF;
+
+    /* Reset CFG2 register */
+    RCC->CFG2 = 0x00007000;
+
+    /* Reset CFG3 register */
+    RCC->CFG3 = 0x00003800;
+
+    /* Reset RDCTRL register */
+    RCC->RDCTRL = 0x00000000;
+
+    /* Reset PLLHSIPRE register */
+    RCC->PLLHSIPRE = 0x00000000;
+
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CLKINT = 0x04BF8000;
+}
+
+/**
+ * @brief  Configures the External High Speed oscillator (HSE).
+ * @note   HSE can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSE specifies the new state of the HSE.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_HSE_DISABLE HSE oscillator OFF
+ *     @arg RCC_HSE_ENABLE HSE oscillator ON
+ *     @arg RCC_HSE_BYPASS HSE oscillator bypassed with external clock
+ */
+void RCC_ConfigHse(uint32_t RCC_HSE)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_HSE));
+    /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+    /* Reset HSEON bit */
+    RCC->CTRL &= CTRL_HSEEN_RESET;
+    /* Reset HSEBYP bit */
+    RCC->CTRL &= CTRL_HSEBP_RESET;
+    /* Configure HSE (RCC_HSE_DISABLE is already covered by the code section above) */
+    switch (RCC_HSE)
+    {
+        case RCC_HSE_ENABLE:
+            /* Set HSEEN bit */
+            RCC->CTRL |= CTRL_HSEEN_SET;
+            break;
+
+        case RCC_HSE_BYPASS:
+            /* Set HSEBYP and HSEEN bits */
+            RCC->CTRL |= CTRL_HSEBP_SET | CTRL_HSEEN_SET;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/**
+ * @brief  Waits for HSE start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: HSE oscillator is stable and ready to use
+ * - ERROR: HSE oscillator not yet ready
+ */
+ErrorStatus RCC_WaitHseStable(void)
+{
+    __IO uint32_t StartUpCounter = 0;
+    ErrorStatus status           = ERROR;
+    FlagStatus HSEStatus         = RESET;
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF);
+        StartUpCounter++;
+    } while ((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+
+    if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSERDF) != RESET)
+    {
+        status = SUCCESS;
+    }
+    else
+    {
+        status = ERROR;
+    }
+    return (status);
+}
+
+/**
+ * @brief  Configures the Internal High Speed oscillator (HSI).
+ * @note   HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSI specifies the new state of the HSI.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_HSI_DISABLE HSI oscillator OFF
+ *     @arg RCC_HSI_ENABLE HSI oscillator ON
+ */
+void RCC_ConfigHsi(uint32_t RCC_HSI)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_HSI));
+    /* Reset HSIEN bit */
+    RCC->CTRL &= CTRL_HSIEN_RESET;
+    /* Configure HSI */
+    switch (RCC_HSI)
+    {
+        case RCC_HSI_ENABLE:
+            /* Set HSIEN bit */
+            RCC->CTRL |= CTRL_HSIEN_SET;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/**
+ * @brief  Waits for HSI start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: HSI oscillator is stable and ready to use
+ * - ERROR: HSI oscillator not yet ready
+ */
+ErrorStatus RCC_WaitHsiStable(void)
+{
+    __IO uint32_t StartUpCounter = 0;
+    ErrorStatus status           = ERROR;
+    FlagStatus HSIStatus         = RESET;
+
+    /* Wait till HSI is ready and if Time out is reached exit */
+    do
+    {
+        HSIStatus = RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF);
+        StartUpCounter++;
+    } while ((StartUpCounter != HSI_STARTUP_TIMEOUT) && (HSIStatus == RESET));
+
+    if (RCC_GetFlagStatus(RCC_CTRL_FLAG_HSIRDF) != RESET)
+    {
+        status = SUCCESS;
+    }
+    else
+    {
+        status = ERROR;
+    }
+    return (status);
+}
+
+/**
+ * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ * @param HSICalibrationValue specifies the calibration trimming value.
+ *   This parameter must be a number between 0 and 0x1F.
+ */
+void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_CALIB_VALUE(HSICalibrationValue));
+    tmpregister = RCC->CTRL;
+    /* Clear HSITRIM[4:0] bits */
+    tmpregister &= CTRL_HSITRIM_MASK;
+    /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+    tmpregister |= (uint32_t)HSICalibrationValue << 2;
+    /* Store the new value */
+    RCC->CTRL = tmpregister;
+}
+
+/**
+ * @brief  Enables or disables the Internal High Speed oscillator (HSI).
+ * @note   HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param Cmd new state of the HSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableHsi(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    *(__IO uint32_t*)CTRL_HSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief  Configures the Multi Speed oscillator (MSI).
+ * @param RCC_MSI specifies the new state of the MSI.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_MSI_DISABLE MSI oscillator OFF
+ *     @arg RCC_MSI_ENABLE MSI oscillator ON
+ * @param RCC_MSI_Range specifies the clock of the MSI.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_MSI_RANGE_100K 100KHz
+ *     @arg RCC_MSI_RANGE_200K 200KHz
+ *     @arg RCC_MSI_RANGE_400K 400KHz
+ *     @arg RCC_MSI_RANGE_800K 800KHz
+ *     @arg RCC_MSI_RANGE_1M   1MHz
+ *     @arg RCC_MSI_RANGE_2M   2MHz
+ *     @arg RCC_MSI_RANGE_4M   4MHz
+ */
+void RCC_ConfigMsi(uint32_t RCC_MSI, uint32_t RCC_MSI_Range)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_MSI(RCC_MSI));
+    assert_param(IS_RCC_MSI_RANGE(RCC_MSI_Range));
+    /* Set MSIRANGE[2:0] bit */
+    RCC->CTRLSTS &= CTRLSTS_MSIRANGE_MASK;
+    RCC->CTRLSTS |= RCC_MSI_Range;
+    /* Configure MSI */
+    switch (RCC_MSI)
+    {
+        case RCC_MSI_ENABLE:
+            /* Set MSIEN bit */
+            RCC->CTRLSTS |= CTRLSTS_MSIEN_SET;
+            break;
+        case RCC_MSI_DISABLE:
+            /* Reset MSIEN bit */
+            RCC->CTRLSTS &= CTRLSTS_MSIEN_RESET;
+            break;
+        default:
+            break;
+    }
+}
+
+/**
+ * @brief  Waits for MSI start-up.
+ * @return An ErrorStatus enumuration value:
+ * - SUCCESS: MSI oscillator is stable and ready to use
+ * - ERROR: MSI oscillator not yet ready
+ */
+ErrorStatus RCC_WaitMsiStable(void)
+{
+    __IO uint32_t StartUpCounter = 0;
+    ErrorStatus status           = ERROR;
+    FlagStatus MSIStatus         = RESET;
+
+    /* Wait till MSI is ready and if Time out is reached exit */
+    do
+    {
+        MSIStatus = RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD);
+        StartUpCounter++;
+    } while ((StartUpCounter != MSI_STARTUP_TIMEOUT) && (MSIStatus == RESET));
+
+    if (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_MSIRD) != RESET)
+    {
+        status = SUCCESS;
+    }
+    else
+    {
+        status = ERROR;
+    }
+    return (status);
+}
+
+/**
+ * @brief  Adjusts the Multi Speed oscillator (MSI) calibration value.
+ * @param MSICalibrationValue specifies the calibration trimming value.
+ *   This parameter must be a number between 0 and 0xFF.
+ */
+void RCC_SetMsiCalibValue(uint8_t MSICalibrationValue)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    //assert_param(IS_RCC_MSICALIB_VALUE(MSICalibrationValue));
+    tmpregister = RCC->CTRLSTS;
+    /* Clear MSITRIM[7:0] bits */
+    tmpregister &= CTRLSTS_MSITRIM_MASK;
+    /* Set the MSITRIM[7:0] bits according to MSICalibrationValue value */
+    tmpregister |= (uint32_t)MSICalibrationValue << 15;
+    /* Store the new value */
+    RCC->CTRLSTS = tmpregister;
+}
+
+/**
+ * @brief  Enables or disables the Multi Speed oscillator (MSI).
+ * @param Cmd new state of the MSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableMsi(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    *(__IO uint32_t*)CTRLSTS_MSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief  Configures the PLL clock source and multiplication factor.
+ * @note   This function must be used only when the PLL is disabled.
+ * @param RCC_PLLSource specifies the PLL entry clock source.
+ *   this parameter can be one of the following values:
+ *     @arg RCC_PLL_HSI_PRE_DIV1 HSI oscillator clock selected as PLL clock entry
+ *     @arg RCC_PLL_HSI_PRE_DIV2 HSI oscillator clock divided by 2 selected as PLL clock entry
+ *     @arg RCC_PLL_SRC_HSE_DIV1 HSE oscillator clock selected as PLL clock entry
+ *     @arg RCC_PLL_SRC_HSE_DIV2 HSE oscillator clock divided by 2 selected as PLL clock entry
+ * @param RCC_PLLMul specifies the PLL multiplication factor.
+ *    this parameter can be RCC_PLLMul_x where x:[2,32]
+ * @param RCC_PLLDIVCLK specifies the PLL divider feedback clock source.
+ *   this parameter can be one of the following values:
+ *     @arg RCC_PLLDIVCLK_DISABLE PLLSource clock selected as PLL clock entry
+ *     @arg RCC_PLLDIVCLK_ENABLE  PLLSource clock divided by 2 selected as PLL clock entry
+ */
+void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, uint32_t RCC_PLLDIVCLK)
+{
+    uint32_t tmpregister = 0;
+    uint32_t pllhsipreregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RCC_PLL_SRC(RCC_PLLSource));
+    assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+    assert_param(IS_RCC_PLL_DIVCLK(RCC_PLLDIVCLK));
+
+    tmpregister = RCC->CFG;
+    pllhsipreregister = RCC->PLLHSIPRE;
+    /* Clear PLLSRC, PLLXTPRE and PLLMUL[4:0] bits */
+    tmpregister &= CFG_PLL_MASK;
+    /* Clear PLLHSIPRE, PLLSRCDIV bits */
+    pllhsipreregister &= (~(PLLHSIPRE_PLLHSI_PRE_MASK | PLLHSIPRE_PLLSRCDIV_MASK));
+    /* Set the PLL configuration bits */
+    if ((RCC_PLLSource == RCC_PLL_HSI_PRE_DIV1) || (RCC_PLLSource == RCC_PLL_HSI_PRE_DIV2))
+    {
+        tmpregister       |= RCC_PLLMul;
+        pllhsipreregister |= RCC_PLLSource | RCC_PLLDIVCLK;
+    }
+    /* (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV1) || (RCC_PLLSource == RCC_PLL_SRC_HSE_DIV2) */
+    else
+    {
+        tmpregister       |= RCC_PLLSource | RCC_PLLMul;
+        pllhsipreregister |= RCC_PLLDIVCLK;
+    }
+    /* Store the new value */
+    RCC->CFG       = tmpregister;
+    RCC->PLLHSIPRE = pllhsipreregister;
+}
+
+/**
+ * @brief  Enables or disables the PLL.
+ * @note   The PLL can not be disabled if it is used as system clock.
+ * @param Cmd new state of the PLL. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnablePll(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    *(__IO uint32_t*)CTRL_PLLEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief  Configures the system clock (SYSCLK).
+ * @param RCC_SYSCLKSource specifies the clock source used as system clock.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_SYSCLK_SRC_MSI    HSI selected as system clock
+ *     @arg RCC_SYSCLK_SRC_HSI    HSI selected as system clock
+ *     @arg RCC_SYSCLK_SRC_HSE    HSE selected as system clock
+ *     @arg RCC_SYSCLK_SRC_PLLCLK PLL selected as system clock
+ */
+void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_SYSCLK_SRC(RCC_SYSCLKSource));
+    tmpregister = RCC->CFG;
+    /* Clear SW[1:0] bits */
+    tmpregister &= CFG_SCLKSW_MASK;
+    /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+    tmpregister |= RCC_SYSCLKSource;
+    /* Store the new value */
+    RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief  Returns the clock source used as system clock.
+ * @return The clock source used as system clock. The returned value can
+ *   be one of the following:
+ *     - 0x00: MSI used as system clock
+ *     - 0x04: HSI used as system clock
+ *     - 0x08: HSE used as system clock
+ *     - 0x0C: PLL used as system clock
+ */
+uint8_t RCC_GetSysclkSrc(void)
+{
+    return ((uint8_t)(RCC->CFG & CFG_SCLKSTS_MASK));
+}
+
+/**
+ * @brief  Configures the AHB clock (HCLK).
+ * @param RCC_SYSCLK defines the AHB clock divider. This clock is derived from
+ *   the system clock (SYSCLK).
+ *   This parameter can be one of the following values:
+ *     @arg RCC_SYSCLK_DIV1 AHB clock = SYSCLK
+ *     @arg RCC_SYSCLK_DIV2 AHB clock = SYSCLK/2
+ *     @arg RCC_SYSCLK_DIV4 AHB clock = SYSCLK/4
+ *     @arg RCC_SYSCLK_DIV8 AHB clock = SYSCLK/8
+ *     @arg RCC_SYSCLK_DIV16 AHB clock = SYSCLK/16
+ *     @arg RCC_SYSCLK_DIV64 AHB clock = SYSCLK/64
+ *     @arg RCC_SYSCLK_DIV128 AHB clock = SYSCLK/128
+ *     @arg RCC_SYSCLK_DIV256 AHB clock = SYSCLK/256
+ *     @arg RCC_SYSCLK_DIV512 AHB clock = SYSCLK/512
+ */
+void RCC_ConfigHclk(uint32_t RCC_SYSCLK)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_SYSCLK_DIV(RCC_SYSCLK));
+    tmpregister = RCC->CFG;
+    /* Clear HPRE[3:0] bits */
+    tmpregister &= CFG_AHBPRES_RESET_MASK;
+    /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+    tmpregister |= RCC_SYSCLK;
+    /* Store the new value */
+    RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief  Configures the Low Speed APB clock (PCLK1).
+ * @param RCC_HCLK defines the APB1 clock divider. This clock is derived from
+ *   the AHB clock (HCLK).
+ *   This parameter can be one of the following values:
+ *     @arg RCC_HCLK_DIV1 APB1 clock = HCLK
+ *     @arg RCC_HCLK_DIV2 APB1 clock = HCLK/2
+ *     @arg RCC_HCLK_DIV4 APB1 clock = HCLK/4
+ *     @arg RCC_HCLK_DIV8 APB1 clock = HCLK/8
+ *     @arg RCC_HCLK_DIV16 APB1 clock = HCLK/16
+ */
+void RCC_ConfigPclk1(uint32_t RCC_HCLK)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_HCLK_DIV(RCC_HCLK));
+    tmpregister = RCC->CFG;
+    /* Clear PPRE1[2:0] bits */
+    tmpregister &= CFG_APB1PRES_RESET_MASK;
+    /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+    tmpregister |= RCC_HCLK;
+    /* Store the new value */
+    RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief  Configures the High Speed APB clock (PCLK2).
+ * @param RCC_HCLK defines the APB2 clock divider. This clock is derived from
+ *   the AHB clock (HCLK).
+ *   This parameter can be one of the following values:
+ *     @arg RCC_HCLK_DIV1 APB2 clock = HCLK
+ *     @arg RCC_HCLK_DIV2 APB2 clock = HCLK/2
+ *     @arg RCC_HCLK_DIV4 APB2 clock = HCLK/4
+ *     @arg RCC_HCLK_DIV8 APB2 clock = HCLK/8
+ *     @arg RCC_HCLK_DIV16 APB2 clock = HCLK/16
+ */
+void RCC_ConfigPclk2(uint32_t RCC_HCLK)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_HCLK_DIV(RCC_HCLK));
+    tmpregister = RCC->CFG;
+    /* Clear PPRE2[2:0] bits */
+    tmpregister &= CFG_APB2PRES_RESET_MASK;
+    /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+    tmpregister |= RCC_HCLK << 3;
+    /* Store the new value */
+    RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief  Enables or disables the specified RCC interrupts.
+ * @param RccInt specifies the RCC interrupt sources to be enabled or disabled.
+ *
+ *   this parameter can be any combination of the following values
+ *     @arg RCC_INT_LSIRDIF LSI ready interrupt
+ *     @arg RCC_INT_LSERDIF LSE ready interrupt
+ *     @arg RCC_INT_HSIRDIF HSI ready interrupt
+ *     @arg RCC_INT_HSERDIF HSE ready interrupt
+ *     @arg RCC_INT_PLLRDIF PLL ready interrupt
+ *     @arg RCC_INT_BORIF   BOR interrupt
+ *     @arg RCC_INT_MSIRDIF MSI ready interrupt
+ *
+ * @param Cmd new state of the specified RCC interrupts.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_INT(RccInt));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Perform Byte access to RCC_CLKINT bits to enable the selected interrupts */
+        *(__IO uint32_t*)CLKINT_ADDR |= (((uint32_t)RccInt) << 8);
+    }
+    else
+    {
+        /* Perform Byte access to RCC_CLKINT bits to disable the selected interrupts */
+        *(__IO uint32_t*)CLKINT_ADDR &= (~(((uint32_t)RccInt) << 8));
+    }
+}
+
+/**
+ * @brief  Configures the USB clock (USBCLK).
+ * @param RCC_USBCLKSource specifies the USB clock source. This clock is
+ *   derived from the PLL output.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_USBCLK_SRC_PLLCLK_DIV1_5 PLL clock divided by 1,5 selected as USB clock source
+ *     @arg RCC_USBCLK_SRC_PLLCLK_DIV1   PLL clock divided by 1 selected as USB clock source
+ *     @arg RCC_USBCLK_SRC_PLLCLK_DIV2   PLL clock divided by 2 selected as USB clock source
+ *     @arg RCC_USBCLK_SRC_PLLCLK_DIV3   PLL clock divided by 3 selected as USB clock source
+ */
+void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_USBCLK_SRC(RCC_USBCLKSource));
+
+    *(__IO uint32_t*)CFG_USBPRES_BB      = RCC_USBCLKSource;
+    *(__IO uint32_t*)CFGR_USBPRE_BB_BIT1 = RCC_USBCLKSource >> 1;
+}
+
+/**
+ * @brief  Configures the TIM1/8 clock (TIM1/8CLK).
+ * @param RCC_TIM18CLKSource specifies the TIM1/8 clock source.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_TIM18CLK_SRC_TIM18CLK
+ *     @arg RCC_TIM18CLK_SRC_SYSCLK
+ */
+void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_TIM18CLKSRC(RCC_TIM18CLKSource));
+
+    tmpregister = RCC->CFG2;
+    /* Clear TIMCLK_SEL bits */
+    tmpregister &= CFG2_TIM18CLKSEL_RESET_MASK;
+    /* Set TIMCLK_SEL bits according to RCC_TIM18CLKSource value */
+    tmpregister |= RCC_TIM18CLKSource;
+
+    /* Store the new value */
+    RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief  Configures the RNGCCLK prescaler.
+ * @param RCC_RNGCCLKPrescaler specifies the RNGCCLK prescaler.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_RNGCCLK_SYSCLK_DIV1 RNGCPRE[24:28] = 00000, SYSCLK Divided By 1
+ *     @arg RCC_RNGCCLK_SYSCLK_DIV2 RNGCPRE[24:28] = 00001, SYSCLK Divided By 2
+ *     @arg RCC_RNGCCLK_SYSCLK_DIV3 RNGCPRE[24:28] = 00002, SYSCLK Divided By 3
+ *               ...
+ *     @arg RCC_RNGCCLK_SYSCLK_DIV31 RNGCPRE[24:28] = 11110, SYSCLK Divided By 31
+ *     @arg RCC_RNGCCLK_SYSCLK_DIV32 RNGCPRE[24:28] = 11111, SYSCLK Divided By 32
+ */
+void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_RNGCCLKPRE(RCC_RNGCCLKPrescaler));
+
+    tmpregister = RCC->CFG2;
+    /* Clear RNGCPRE[3:0] bits */
+    tmpregister &= CFG2_RNGCPRES_RESET_MASK;
+    /* Set RNGCPRE[3:0] bits according to RCC_RNGCCLKPrescaler value */
+    tmpregister |= RCC_RNGCCLKPrescaler;
+
+    /* Store the new value */
+    RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief  Configures the ADCx 1M clock (ADC1MCLK).
+ * @param RCC_ADC1MCLKSource specifies the ADC1M clock source.
+ *   This parameter can be on of the following values:
+ *     @arg RCC_ADC1MCLK_SRC_HSI
+ *     @arg RCC_ADC1MCLK_SRC_HSE
+ *
+ * @param RCC_ADC1MPrescaler specifies the ADC1M clock prescaler.
+ *   This parameter can be on of the following values:
+ *     @arg RCC_ADC1MCLK_DIV1 ADC1M clock = RCC_ADC1MCLKSource_xxx/1
+ *     @arg RCC_ADC1MCLK_DIV2 ADC1M clock = RCC_ADC1MCLKSource_xxx/2
+ *     @arg RCC_ADC1MCLK_DIV3 ADC1M clock = RCC_ADC1MCLKSource_xxx/3
+ *               ...
+ *     @arg RCC_ADC1MCLK_DIV31 ADC1M clock = RCC_ADC1MCLKSource_xxx/31
+ *     @arg RCC_ADC1MCLK_DIV32 ADC1M clock = RCC_ADC1MCLKSource_xxx/32
+ */
+void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_ADC1MCLKSRC(RCC_ADC1MCLKSource));
+    assert_param(IS_RCC_ADC1MCLKPRE(RCC_ADC1MPrescaler));
+
+    tmpregister = RCC->CFG2;
+    /* Clear ADC1MSEL and ADC1MPRE[4:0] bits */
+    tmpregister &= CFG2_ADC1MSEL_RESET_MASK;
+    tmpregister &= CFG2_ADC1MPRES_RESET_MASK;
+    /* Set ADC1MSEL bits according to RCC_ADC1MCLKSource value */
+    tmpregister |= RCC_ADC1MCLKSource;
+    /* Set ADC1MPRE[4:0] bits according to RCC_ADC1MPrescaler value */
+    tmpregister |= RCC_ADC1MPrescaler;
+
+    /* Store the new value */
+    RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief  Configures the ADCPLLCLK prescaler, and enable/disable ADCPLLCLK.
+ * @param RCC_ADCPLLCLKPrescaler specifies the ADCPLLCLK prescaler.
+ *   This parameter can be on of the following values:
+ *     @arg RCC_ADCPLLCLK_DIV1 ADCPLLCLKPRES[4:0] = 10000, Pll Clock Divided By 1
+ *     @arg RCC_ADCPLLCLK_DIV2 ADCPLLCLKPRES[4:0] = 10001, Pll Clock Divided By 2
+ *     @arg RCC_ADCPLLCLK_DIV4 ADCPLLCLKPRES[4:0] = 10010, Pll Clock Divided By 4
+ *     @arg RCC_ADCPLLCLK_DIV6 ADCPLLCLKPRES[4:0] = 10011, Pll Clock Divided By 6
+ *     @arg RCC_ADCPLLCLK_DIV8 ADCPLLCLKPRES[4:0] = 10100, Pll Clock Divided By 8
+ *     @arg RCC_ADCPLLCLK_DIV10 ADCPLLCLKPRES[4:0] = 10101, Pll Clock Divided By 10
+ *     @arg RCC_ADCPLLCLK_DIV12 ADCPLLCLKPRES[4:0] = 10110, Pll Clock Divided By 12
+ *     @arg RCC_ADCPLLCLK_DIV16 ADCPLLCLKPRES[4:0] = 10111, Pll Clock Divided By 16
+ *     @arg RCC_ADCPLLCLK_DIV32 ADCPLLCLKPRES[4:0] = 11000, Pll Clock Divided By 32
+ *     @arg RCC_ADCPLLCLK_DIV64 ADCPLLCLKPRES[4:0] = 11001, Pll Clock Divided By 64
+ *     @arg RCC_ADCPLLCLK_DIV128 ADCPLLCLKPRES[4:0] = 11010, Pll Clock Divided By 128
+ *     @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = 11011, Pll Clock Divided By 256
+ *     @arg RCC_ADCPLLCLK_DIV256 ADCPLLCLKPRES[4:0] = others, Pll Clock Divided By 256
+ *
+ * @param Cmd specifies the ADCPLLCLK enable/disable selection.
+ *   This parameter can be on of the following values:
+ *     @arg ENABLE enable ADCPLLCLK
+ *     @arg DISABLE disable ADCPLLCLK ADCPLLCLKPRES[4:0] = 0xxxx, ADC Pll Clock Disable
+ */
+void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_ADCPLLCLKPRE(RCC_ADCPLLCLKPrescaler));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    tmpregister = RCC->CFG2;
+    /* Clear ADCPLLPRES[4:0] bits */
+    tmpregister &= CFG2_ADCPLLPRES_RESET_MASK;
+
+    if (Cmd != DISABLE)
+    {
+        tmpregister |= RCC_ADCPLLCLKPrescaler;
+    }
+    else
+    {
+        tmpregister |= RCC_ADCPLLCLKPrescaler;
+        tmpregister &= RCC_ADCPLLCLK_DISABLE;
+    }
+
+    /* Store the new value */
+    RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief  Configures the ADCHCLK prescaler.
+ * @param RCC_ADCHCLKPrescaler specifies the ADCHCLK prescaler.
+ *   This parameter can be on of the following values:
+ *     @arg RCC_ADCHCLK_DIV1 ADCHCLKPRE[3:0] = 0000, HCLK Clock Divided By 1
+ *     @arg RCC_ADCHCLK_DIV2 ADCHCLKPRE[3:0] = 0001, HCLK Clock Divided By 2
+ *     @arg RCC_ADCHCLK_DIV4 ADCHCLKPRE[3:0] = 0010, HCLK Clock Divided By 4
+ *     @arg RCC_ADCHCLK_DIV6 ADCHCLKPRE[3:0] = 0011, HCLK Clock Divided By 6
+ *     @arg RCC_ADCHCLK_DIV8 ADCHCLKPRE[3:0] = 0100, HCLK Clock Divided By 8
+ *     @arg RCC_ADCHCLK_DIV10 ADCHCLKPRE[3:0] = 0101, HCLK Clock Divided By 10
+ *     @arg RCC_ADCHCLK_DIV12 ADCHCLKPRE[3:0] = 0110, HCLK Clock Divided By 12
+ *     @arg RCC_ADCHCLK_DIV16 ADCHCLKPRE[3:0] = 0111, HCLK Clock Divided By 16
+ *     @arg RCC_ADCHCLK_DIV32 ADCHCLKPRE[3:0] = 1000, HCLK Clock Divided By 32
+ *     @arg RCC_ADCHCLK_DIV_OTHERS ADCHCLKPRE[3:0] = others, HCLK Clock Divided By 32
+ */
+void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_ADCHCLKPRE(RCC_ADCHCLKPrescaler));
+
+    tmpregister = RCC->CFG2;
+    /* Clear ADCHPRE[3:0] bits */
+    tmpregister &= CFG2_ADCHPRES_RESET_MASK;
+    /* Set ADCHPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */
+    tmpregister |= RCC_ADCHCLKPrescaler;
+
+    /* Store the new value */
+    RCC->CFG2 = tmpregister;
+}
+
+/**
+ * @brief  Configures the TRNG 1M clock (TRNG1MCLK).
+ * @param RCC_TRNG1MCLKSource specifies the TRNG1M clock source.
+ *   This parameter can be on of the following values:
+ *     @arg RCC_TRNG1MCLK_SRC_HSI
+ *     @arg RCC_TRNG1MCLK_SRC_HSE
+ *
+ * @param RCC_TRNG1MPrescaler specifies the TRNG1M prescaler.
+ *   This parameter can be on of the following values:
+ *     @arg RCC_TRNG1MCLK_DIV2 TRNG1M clock = RCC_TRNG1MCLK_SRC_HSE/2
+ *     @arg RCC_TRNG1MCLK_DIV4 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/4
+ *     @arg RCC_TRNG1MCLK_DIV6 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/6
+ *               ...
+ *     @arg RCC_TRNG1MCLK_DIV60 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/60
+ *     @arg RCC_TRNG1MCLK_DIV62 TRNG1M clock = RCC_TRNG1MCLKSource_xxx/62
+ */
+void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_TRNG1MCLK_SRC(RCC_TRNG1MCLKSource));
+    assert_param(IS_RCC_TRNG1MCLKPRE(RCC_TRNG1MPrescaler));
+
+    tmpregister = RCC->CFG3;
+    /* Clear TRNG1MSEL and TRNG1MPRE[4:0] bits */
+    tmpregister &= CFGR3_TRNG1MSEL_RESET_MASK;
+    tmpregister &= CFGR3_TRNG1MPRES_RESET_MASK;
+    /* Set TRNG1MSEL bits according to RCC_TRNG1MCLKSource value */
+    tmpregister |= RCC_TRNG1MCLKSource;
+    /* Set TRNG1MPRE[4:0] bits according to RCC_TRNG1MPrescaler value */
+    tmpregister |= RCC_TRNG1MPrescaler;
+
+    /* Store the new value */
+    RCC->CFG3 = tmpregister;
+}
+
+/**
+ * @brief  Enable/disable TRNG clock (TRNGCLK).
+ * @param Cmd specifies the TRNGCLK enable/disable selection.
+ *   This parameter can be on of the following values:
+ *     @arg ENABLE enable TRNGCLK
+ *     @arg DISABLE disable TRNGCLK
+ */
+void RCC_EnableTrng1mClk(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        RCC->CFG3 |= RCC_TRNG1MCLK_ENABLE;
+    }
+    else
+    {
+        RCC->CFG3 &= RCC_TRNG1MCLK_DISABLE;
+    }
+}
+
+/**
+ * @brief  Configures the UCDR clock.
+ * @param RCC_UCDR300MSource specifies the UCDR clock source.
+ *   This parameter can be on of the following values:
+ *     @arg RCC_UCDR300M_SRC_OSC300M
+ *     @arg RCC_UCDR300M_SRC_PLLVCO
+ *
+ * @param Cmd enable/disable selection.
+ *   This parameter can be on of the following values:
+ *     @arg ENABLE enable UCDR
+ *     @arg DISABLE disable UCDR
+ */
+void RCC_ConfigUCDRClk(uint32_t RCC_UCDR300MSource, FunctionalState Cmd)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_UCDR300M_SRC(RCC_UCDR300MSource));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    tmpregister = RCC->CFG3;
+    /* Clear UCDR300MSEL bits */
+    tmpregister &= RCC_UCDR300MSource_MASK;
+    /* Set UCDR300MSEL bits */
+    tmpregister |= RCC_UCDR300MSource;
+
+    /* Store the new value */
+    RCC->CFG3 = tmpregister;
+
+    if (Cmd != DISABLE)
+    {
+        RCC->CFG3 |= RCC_UCDR_ENABLE;
+    }
+    else
+    {
+        RCC->CFG3 &= RCC_UCDR_DISABLE;
+    }
+}
+
+/**
+ * @brief  Configures the USB Crystal Mode.
+ * @param RCC_USBXTALESSMode specifies the USB Crystal Mode.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_USBXTALESS_MODE     USB work in crystal mode
+ *     @arg RCC_USBXTALESS_LESSMODE USB work in crystalless mode
+ */
+void RCC_ConfigUSBXTALESSMode(uint32_t RCC_USBXTALESSMode)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_USBXTALESS_MODE(RCC_USBXTALESSMode));
+
+    /* Clear the USB Crystal Mode bit */
+    RCC->CFG3 &= RCC_USBXTALESSMode_MASK;
+
+    /* Select the USB Crystal Mode */
+    RCC->CFG3 |= RCC_USBXTALESSMode;
+}
+
+/**
+ * @brief  Enables or disables the RET peripheral clock.
+ * @param RCC_RETPeriph specifies the RET peripheral to gates its clock.
+ *
+ *   this parameter can be any combination of the following values:
+ *     @arg RCC_RET_PERIPH_LPTIM
+ *     @arg RCC_RET_PERIPH_LPUART
+ *
+ * @param Cmd new state of the specified peripheral clock.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableRETPeriphClk(uint32_t RCC_RETPeriph, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        RCC->RDCTRL |= RCC_RETPeriph;
+    }
+    else
+    {
+        RCC->RDCTRL &= ~RCC_RETPeriph;
+    }
+}
+
+/**
+ * @brief Forces or releases RET peripheral reset.
+ * @param RCC_RETPeriph specifies the RET peripheral to reset.
+ *   This parameter can be any combination of the following values:
+ *     @arg   RCC_RET_PERIPH_LPTIM.
+ *            RCC_RET_PERIPH_LPUART.
+ * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE.
+ */
+void RCC_EnableRETPeriphReset(uint32_t RCC_RETPeriph, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_RET_PERIPH(RCC_RETPeriph));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        RCC->RDCTRL |= (RCC_RETPeriph << 4);
+    }
+    else
+    {
+        RCC->RDCTRL &= ~(RCC_RETPeriph << 4);
+    }
+}
+
+/**
+ * @brief  Configures the LPTIM clock (LPTIMCLK).
+ * @param RCC_LPTIMCLKSource specifies the LPTIM clock source.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_LPTIMCLK_SRC_APB1  APB1 clock selected as LPTIM clock
+ *     @arg RCC_LPTIMCLK_SRC_LSI   LSI selected as LPTIM clock
+ *     @arg RCC_LPTIMCLK_SRC_HSI   HSI selected as LPTIM clock
+ *     @arg RCC_LPTIMCLK_SRC_LSE   LSE selected as LPTIM clock
+ *     @arg RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock
+ *     @arg RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock
+ * @note When switching from comparator1/2 to other clock sources,
+ *       it is suggested to disable comparators first.
+ */
+void RCC_ConfigLPTIMClk(uint32_t RCC_LPTIMCLKSource)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM_CLK(RCC_LPTIMCLKSource));
+    //PWR DBP set 1
+    RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE);
+    PWR->CTRL1 |=  0x100;
+    /* Clear the LPTIM clock source */
+    RCC->RDCTRL &= RCC_LPTIMCLK_SRC_MASK;
+
+    /* Select the LPTIM clock source */
+    RCC->RDCTRL |= RCC_LPTIMCLKSource;
+}
+
+/**
+ * @brief  Returns the clock source used as LPTIM clock (LPTIMCLK).
+ * @return The clock source used as system clock. The returned value can
+ *   be one of the following:
+ *     - RCC_LPTIMCLK_SRC_APB1  APB1 clock selected as LPTIM clock
+ *     - RCC_LPTIMCLK_SRC_LSI   LSI selected as LPTIM clock
+ *     - RCC_LPTIMCLK_SRC_HSI   HSI selected as LPTIM clock
+ *     - RCC_LPTIMCLK_SRC_LSE   LSE selected as LPTIM clock
+ *     - RCC_LPTIMCLK_SRC_COMP1 COMP1 output selected as LPTIM clock
+ *     - RCC_LPTIMCLK_SRC_COMP2 COMP2 output selected as LPTIM clock
+ */
+uint32_t RCC_GetLPTIMClkSrc(void)
+{
+    return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPTIMCLKSEL_MASK));
+}
+
+/**
+ * @brief  Configures the LPUART clock (LPUARTCLK).
+ * @param RCC_LPUARTCLKSource specifies the LPUART clock source.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_LPUARTCLK_SRC_APB1   APB1 clock selected as LPTIM clock
+ *     @arg RCC_LPUARTCLK_SRC_SYSCLK SYSCLK selected as LPTIM clock
+ *     @arg RCC_LPUARTCLK_SRC_HSI    HSI selected as LPTIM clock
+ *     @arg RCC_LPUARTCLK_SRC_LSE    LSE selected as LPTIM clock
+ */
+void RCC_ConfigLPUARTClk(uint32_t RCC_LPUARTCLKSource)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_LPUART_CLK(RCC_LPUARTCLKSource));
+
+    /* Clear the LPUART clock source */
+    RCC->RDCTRL &= RCC_LPUARTCLK_SRC_MASK;
+
+    /* Select the LPTIM clock source */
+    RCC->RDCTRL |= RCC_LPUARTCLKSource;
+}
+
+/**
+ * @brief  Returns the clock source used as LPUART clock.
+ * @return The clock source used as system clock. The returned value can
+ *   be one of the following:
+ *     - RCC_RDCTRL_LPUARTSEL_APB1:   APB1 used as LPUART clock
+ *     - RCC_RDCTRL_LPUARTSEL_SYSCLK: SYSCLK used as LPUART clock
+ *     - RCC_RDCTRL_LPUARTSEL_HSI:    HSI used as LPUART clock
+ *     - RCC_RDCTRL_LPUARTSEL_LSE:    LSE used as LPUART clock
+ */
+uint32_t RCC_GetLPUARTClkSrc(void)
+{
+    return ((uint32_t)(RCC->RDCTRL & RDCTRL_LPUARTCLKSEL_MASK));
+}
+
+/**
+ * @brief  Enables or disables the specified SRAM1/2 parity error interrupts.
+ * @param SramErrorInt specifies the SRAM1/2 interrupt sources to be enabled or disabled.
+ *
+ *   this parameter can be any combination of the following values
+ *     @arg SRAM1_PARITYERROR_INT SRAM1 parity interrupt
+ *     @arg SRAM2_PARITYERROR_INT SRAM2 parity interrupt
+ *
+ * @param Cmd new state of the specified SRAM1/2 parity error interrupts.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigSRAMParityErrorInt(uint32_t SramErrorInt, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_SRAMERRORINT(SramErrorInt));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Set ERR1EN/ERR2EN bit to enable the selected parity error interrupts */
+        RCC->SRAM_CTRLSTS |= SramErrorInt;
+    }
+    else
+    {
+        /* Clear ERR1EN/ERR2EN bit to disable the selected parity error interrupts */
+        RCC->SRAM_CTRLSTS &= (~SramErrorInt);
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified SRAM1/2 parity error reset.
+ * @param SramErrorReset specifies the SRAM1/2 parity error reset to be enabled or disabled.
+ *
+ *   this parameter can be any combination of the following values
+ *     @arg SRAM1_PARITYERROR_RESET SRAM1 parity error reset
+ *     @arg SRAM2_PARITYERROR_RESET SRAM2 parity error reset
+ *
+ * @param Cmd new state of the specified SRAM1/2 parity error reset.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_ConfigSRAMParityErrorRESET(uint32_t SramErrorReset, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_SRAMERRORRESET(SramErrorReset));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Set ERR1EN/ERR2EN bit to enable SRAM1/2 parity error reset */
+        RCC->SRAM_CTRLSTS |= SramErrorReset;
+    }
+    else
+    {
+        /* Clear ERR1EN/ERR2EN bit to disable SRAM1/2 parity error reset */
+        RCC->SRAM_CTRLSTS &= (~SramErrorReset);
+    }
+}
+
+/**
+ * @brief Clears the specified SRAM1/2 parity error flag.
+ * @param SramErrorReset specifies the SRAM1/2 parity error flag.
+ *
+ *   this parameter can be any combination of the following values
+ *     @arg SRAM1_PARITYERROR_FLAG SRAM1 parity error flag
+ *     @arg SRAM2_PARITYERROR_FLAG SRAM2 parity error flag
+ */
+void RCC_ClrSRAMParityErrorFlag(uint32_t SramErrorflag)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_SRAMERRORFLAG(SramErrorflag));
+    RCC->SRAM_CTRLSTS |= SramErrorflag;
+}
+
+/**
+ * @brief  Configures the External Low Speed oscillator (LSE) Xtal bias.
+ * @param LSE_Trim specifies LSE Driver Trim Level.
+ *        Trim value rang 0x0~0x1FF
+ */
+void LSE_XtalConfig(uint16_t LSE_Trim)
+{
+    uint32_t tmpregister = 0;
+    tmpregister = *(__IO uint32_t*)LSE_TRIMR_ADDR;
+    //clear lse trim[8:0]
+    tmpregister &= (~(LSE_GM_MASK_VALUE));
+    (LSE_Trim>LSE_GM_MAX_VALUE) ? (LSE_Trim=LSE_GM_DEFAULT_VALUE):(LSE_Trim&=LSE_GM_MASK_VALUE);
+    tmpregister |= LSE_Trim;
+    *(__IO uint32_t*)LSE_TRIMR_ADDR = tmpregister;
+}
+
+/**
+ * @brief  Configures the External Low Speed oscillator (LSE).
+ * @param RCC_LSE specifies the new state of the LSE.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_LSE_DISABLE LSE oscillator OFF
+ *     @arg RCC_LSE_ENABLE LSE oscillator ON
+ *     @arg RCC_LSE_BYPASS LSE oscillator bypassed with external clock
+ * @param LSE_Trim specifies LSE Driver Trim Level.
+ *        Trim value rang 0x00~0x1FF
+ */
+void RCC_ConfigLse(uint8_t RCC_LSE,uint16_t LSE_Trim)
+{
+    //PWR DBP set 1
+    /* Enable PWR Clock */
+    RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR, ENABLE);
+    PWR->CTRL1 |=  0x100;
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_LSE));
+    /* Reset LSEEN LSEBYP and LSECLKSSEN bits before configuring the LSE ------------------*/
+    *(__IO uint32_t*)LDCTRL_ADDR &= (~(RCC_LDCTRL_LSEEN | RCC_LDCTRL_LSEBP | RCC_LDCTRL_LSECLKSSEN));
+    /* Configure LSE (RCC_LSE_DISABLE is already covered by the code section above) */
+    switch (RCC_LSE)
+    {
+    case RCC_LSE_ENABLE:
+        /* Set LSEON bit */
+        *(__IO uint32_t*)LDCTRL_ADDR |= RCC_LSE_ENABLE;
+        LSE_XtalConfig(LSE_Trim);
+        break;
+    case RCC_LSE_BYPASS:
+        /* Set LSEBYP and LSEON bits */
+        *(__IO uint32_t*)LDCTRL_ADDR |= (RCC_LSE_BYPASS | RCC_LSE_ENABLE);
+        break;
+    default:
+        break;
+    }
+}
+
+/**
+ * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
+ * @note   LSI can not be disabled if the IWDG is running.
+ * @param Cmd new state of the LSI. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLsi(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    *(__IO uint32_t*)CTRLSTS_LSIEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief  Configures the RTC clock (RTCCLK).
+ * @note   Once the RTC clock is selected it can't be changed unless the LowPower domain is reset.
+ * @param RCC_RTCCLKSource specifies the RTC clock source.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_RTCCLK_SRC_NONE:      No clock selected as RTC clock
+ *     @arg RCC_RTCCLK_SRC_LSE:       LSE selected as RTC clock
+ *     @arg RCC_RTCCLK_SRC_LSI:       LSI selected as RTC clock
+ *     @arg RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
+ */
+void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_RTCCLK_SRC(RCC_RTCCLKSource));
+
+    /* Clear the RTC clock source */
+    RCC->LDCTRL &= (~RCC_LDCTRL_RTCSEL);
+
+    /* Select the RTC clock source */
+    RCC->LDCTRL |= RCC_RTCCLKSource;
+}
+
+/**
+ * @brief  Returns the clock source used as RTC clock (RTCCLK).
+ * @return The clock source used as system clock. The returned value can
+ *   be one of the following:
+ *     - RCC_RTCCLK_SRC_NONE:      No clock used as RTC clock (RTCCLK)
+ *     - RCC_RTCCLK_SRC_LSE:       LSE used as RTC clock (RTCCLK)
+ *     - RCC_RTCCLK_SRC_LSI:       LSI used as RTC clock (RTCCLK)
+ *     - RCC_RTCCLK_SRC_HSE_DIV32: HSE clock divided by 32 used as RTC clock (RTCCLK)
+ */
+uint32_t RCC_GetRTCClkSrc(void)
+{
+    return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_RTCSEL));
+}
+
+/**
+ * @brief  Enables or disables the RTC clock.
+ * @note   This function must be used only after the RTC clock was selected using the RCC_ConfigRtcClk function.
+ * @param Cmd new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableRtcClk(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    *(__IO uint32_t*)LDCTRL_RTCEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief  Configures the LSX clock (for TSC).
+ * @note   Once the LSX clock is selected it can't be changed unless the LowPower domain is reset.
+ * @param RCC_RTCCLKSource specifies the RTC clock source.
+ *   This parameter can be one of the following values:
+ *     @arg RCC_LSXCLK_SRC_LSI LSI selected as RTC clock
+ *     @arg RCC_LSXCLK_SRC_LSE LSE selected as RTC clock
+ */
+void RCC_ConfigLSXClk(uint32_t RCC_LSXCLKSource)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_LSXCLK_SRC(RCC_LSXCLKSource));
+
+    /* Clear the LSX clock source */
+    RCC->LDCTRL &= (~RCC_LDCTRL_LSXSEL);
+
+    /* Select the LSX clock source */
+    RCC->LDCTRL |= RCC_LSXCLKSource;
+}
+
+/**
+ * @brief  Returns the clock source used as LSX clock (for TSC).
+ * @return The clock source used as system clock. The returned value can
+ *   be one of the following:
+ *     - RCC_LSXCLK_SRC_LSI: LSI used as LSX clock (for TSC)
+ *     - RCC_LSXCLK_SRC_LSE: LSE used as LSX clock (for TSC)
+ */
+uint32_t RCC_GetLSXClkSrc(void)
+{
+    return ((uint32_t)(RCC->LDCTRL & RCC_LDCTRL_LSXSEL));
+}
+
+/**
+ * @brief  Returns the frequencies of different on chip clocks.
+ * @param RCC_Clocks pointer to a RCC_ClocksType structure which will hold
+ *         the clocks frequencies.
+ * @note   The result of this function could be not correct when using
+ *         fractional value for HSE crystal.
+ */
+void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks)
+{
+    uint32_t tmp = 0, pllclk = 0, pllmull = 0, pllsource = 0, presc = 0;
+    uint8_t msi_clk = 0;
+
+    /* Get PLL clock source and multiplication factor ----------------------*/
+    pllmull   = RCC->CFG & CFG_PLLMULFCT_MASK;
+    pllsource = RCC->CFG & CFG_PLLSRC_MASK;
+    /* Get MSI clock --------------------------------------------------------*/
+    msi_clk = (uint8_t) ((RCC->CTRLSTS & RCC_CTRLSTS_MSIRANGE)>>4);
+
+    if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
+    {
+        pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
+    }
+    else
+    {
+        pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
+    }
+
+    if (pllsource == 0x00)
+    {
+        /* HSI selected as PLL clock entry */
+        if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLHSI_PRE_MASK) != (uint32_t)RESET)
+        { /* HSI oscillator clock divided by 2 */
+            pllclk = (HSI_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+            pllclk = HSI_VALUE * pllmull;
+        }
+
+    }
+    else
+    {
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFG & CFG_PLLHSEPRES_MASK) != (uint32_t)RESET)
+        { /* HSE oscillator clock divided by 2 */
+            pllclk = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+            pllclk = HSE_VALUE * pllmull;
+        }
+    }
+
+    /* PLL Div clock */
+    if ((RCC->PLLHSIPRE & PLLHSIPRE_PLLSRCDIV_MASK) != (uint32_t)RESET)
+    { /* PLL clock divided by 2 */
+        pllclk = (pllclk >> 1);
+    }
+
+    /* Get SYSCLK source -------------------------------------------------------*/
+    tmp = RCC->CFG & CFG_SCLKSTS_MASK;
+
+    switch (tmp)
+    {
+    case 0x00: /* MSI used as system clock */
+        RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk];
+        break;
+    case 0x04: /* HSI used as system clock */
+        RCC_Clocks->SysclkFreq = HSI_VALUE;
+        break;
+    case 0x08: /* HSE used as system clock */
+        RCC_Clocks->SysclkFreq = HSE_VALUE;
+        break;
+    case 0x0C: /* PLL used as system clock */
+        RCC_Clocks->SysclkFreq = pllclk;
+        break;
+
+    default:
+        RCC_Clocks->SysclkFreq = s_msiClockTable[msi_clk];
+        break;
+    }
+
+    /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+    /* Get HCLK prescaler */
+    tmp   = RCC->CFG & CFG_AHBPRES_SET_MASK;
+    tmp   = tmp >> 4;
+    presc = s_ApbAhbPresTable[tmp];
+    /* HCLK clock frequency */
+    RCC_Clocks->HclkFreq = RCC_Clocks->SysclkFreq >> presc;
+    /* Get PCLK1 prescaler */
+    tmp   = RCC->CFG & CFG_APB1PRES_SET_MASK;
+    tmp   = tmp >> 8;
+    presc = s_ApbAhbPresTable[tmp];
+    /* PCLK1 clock frequency */
+    RCC_Clocks->Pclk1Freq = RCC_Clocks->HclkFreq >> presc;
+    /* Get PCLK2 prescaler */
+    tmp   = RCC->CFG & CFG_APB2PRES_SET_MASK;
+    tmp   = tmp >> 11;
+    presc = s_ApbAhbPresTable[tmp];
+    /* PCLK2 clock frequency */
+    RCC_Clocks->Pclk2Freq = RCC_Clocks->HclkFreq >> presc;
+
+    /* Get ADCHCLK prescaler */
+    tmp   = RCC->CFG2 & CFG2_ADCHPRES_SET_MASK;
+    presc = s_AdcHclkPresTable[tmp];
+    /* ADCHCLK clock frequency */
+    RCC_Clocks->AdcHclkFreq = RCC_Clocks->HclkFreq / presc;
+    /* Get ADCPLLCLK prescaler */
+    tmp   = RCC->CFG2 & CFG2_ADCPLLPRES_SET_MASK;
+    tmp   = tmp >> 4;
+    presc = s_AdcPllClkPresTable[(tmp & 0xF)]; // ignore BIT5
+    /* ADCPLLCLK clock frequency */
+    RCC_Clocks->AdcPllClkFreq = pllclk / presc;
+}
+
+/**
+ * @brief  Enables or disables the AHB peripheral clock.
+ * @param RCC_AHBPeriph specifies the AHB peripheral to gates its clock.
+ *
+ *   this parameter can be any combination of the following values:
+ *     @arg RCC_AHB_PERIPH_DMA
+ *     @arg RCC_AHB_PERIPH_SRAM
+ *     @arg RCC_AHB_PERIPH_FLITF
+ *     @arg RCC_AHB_PERIPH_CRC
+ *     @arg RCC_AHB_PERIPH_RNGC
+ *     @arg RCC_AHB_PERIPH_SAC
+ *     @arg RCC_AHB_PERIPH_ADC
+ *
+ * @note SRAM and FLITF clock can be disabled only during sleep mode.
+ * @param Cmd new state of the specified peripheral clock.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        RCC->AHBPCLKEN |= RCC_AHBPeriph;
+    }
+    else
+    {
+        RCC->AHBPCLKEN &= ~RCC_AHBPeriph;
+    }
+}
+
+/**
+ * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
+ * @param RCC_APB2Periph specifies the APB2 peripheral to gates its clock.
+ *   This parameter can be any combination of the following values:
+ *     @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB,
+ *          RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1,
+ *          RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1,
+ *          RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2
+ * @param Cmd new state of the specified peripheral clock.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        RCC->APB2PCLKEN |= RCC_APB2Periph;
+    }
+    else
+    {
+        RCC->APB2PCLKEN &= ~RCC_APB2Periph;
+    }
+}
+
+/**
+ * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
+ * @param RCC_APB1Periph specifies the APB1 peripheral to gates its clock.
+ *   This parameter can be any combination of the following values:
+ *     @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4,
+ *          RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7,
+ *          RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC,
+ *          RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG,
+ *          RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1,
+ *          RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN,
+ *          RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP
+ *
+ * @param Cmd new state of the specified peripheral clock.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        RCC->APB1PCLKEN |= RCC_APB1Periph;
+    }
+    else
+    {
+        RCC->APB1PCLKEN &= ~RCC_APB1Periph;
+    }
+}
+
+/**
+ * @brief Forces or releases AHB peripheral reset.
+ * @param RCC_AHBPeriph specifies the AHB peripheral to reset.
+ *   This parameter can be any combination of the following values:
+ *     @arg   RCC_AHB_PERIPH_ADC.
+ *            RCC_AHB_PERIPH_SAC.
+ *            RCC_AHB_PERIPH_RNGC.
+ * @param Cmd new state of the specified peripheral reset. This parameter can be ENABLE or DISABLE.
+ */
+void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        RCC->AHBPRST |= RCC_AHBPeriph;
+    }
+    else
+    {
+        RCC->AHBPRST &= ~RCC_AHBPeriph;
+    }
+}
+
+/**
+ * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
+ * @param RCC_APB2Periph specifies the APB2 peripheral to reset.
+ *   This parameter can be any combination of the following values:
+ *     @arg RCC_APB2_PERIPH_AFIO, RCC_APB2_PERIPH_GPIOA, RCC_APB2_PERIPH_GPIOB,
+ *          RCC_APB2_PERIPH_GPIOC, RCC_APB2_PERIPH_GPIOD, RCC_APB2_PERIPH_TIM1,
+ *          RCC_APB2_PERIPH_SPI1, RCC_APB2_PERIPH_TIM8, RCC_APB2_PERIPH_USART1,
+ *          RCC_APB2_PERIPH_UART4, RCC_APB2_PERIPH_UART5, RCC_APB2_PERIPH_SPI2
+ * @param Cmd new state of the specified peripheral reset.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        RCC->APB2PRST |= RCC_APB2Periph;
+    }
+    else
+    {
+        RCC->APB2PRST &= ~RCC_APB2Periph;
+    }
+}
+
+/**
+ * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+ * @param RCC_APB1Periph specifies the APB1 peripheral to reset.
+ *   This parameter can be any combination of the following values:
+ *     @arg RCC_APB1_PERIPH_TIM2, RCC_APB1_PERIPH_TIM3, RCC_APB1_PERIPH_TIM4,
+ *          RCC_APB1_PERIPH_TIM5, RCC_APB1_PERIPH_TIM6, RCC_APB1_PERIPH_TIM7,
+ *          RCC_APB1_PERIPH_COMP, RCC_APB1_PERIPH_COMP_FILT, RCC_APB1_PERIPH_AFEC,
+ *          RCC_APB1_PERIPH_TIM9, RCC_APB1_PERIPH_TSC, RCC_APB1_PERIPH_WWDG,
+ *          RCC_APB1_PERIPH_USART2, RCC_APB1_PERIPH_USART3, RCC_APB1_PERIPH_I2C1,
+ *          RCC_APB1_PERIPH_I2C2, RCC_APB1_PERIPH_USB, RCC_APB1_PERIPH_CAN,
+ *          RCC_APB1_PERIPH_PWR, RCC_APB1_PERIPH_DAC, RCC_APB1_PERIPH_OPAMP
+ * @param Cmd new state of the specified peripheral clock.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        RCC->APB1PRST |= RCC_APB1Periph;
+    }
+    else
+    {
+        RCC->APB1PRST &= ~RCC_APB1Periph;
+    }
+}
+
+/**
+ * @brief  Forces or releases the LowPower domain reset.
+ * @param Cmd new state of the Backup domain reset.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLowPowerReset(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    *(__IO uint32_t*)LDCTRL_LDSFTRST_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief  Enables or disables the Clock Security System.
+ * @param Cmd new state of the Clock Security System..
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableClockSecuritySystem(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    *(__IO uint32_t*)CTRL_CLKSSEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief  Enables or disables the LSE Clock Security System.
+ * @param Cmd new state of the LSE Clock Security System..
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RCC_EnableLSEClockSecuritySystem(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    *(__IO uint32_t*)LDCTRL_LSECLKSSEN_BB = (uint32_t)Cmd;
+}
+
+/**
+ * @brief  Get LSE Clock Security System failure status.
+ * @return LSE Clock Security System failure status (SET or RESET).
+ */
+FlagStatus RCC_GetLSEClockSecuritySystemStatus(void)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the status of LSE Clock Security System */
+    if ((RCC->LDCTRL & RCC_LDCTRL_LSECLKSSF) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    /* Return LSE Clock Security System status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Configures the MCO PLL clock prescaler.
+ * @param RCC_MCOPLLCLKPrescaler specifies the MCO PLL clock prescaler.
+ *   This parameter can be on of the following values:
+ *     @arg RCC_MCO_CLK_NUM0  MCOPRE[3:0] = 0000, PLL Clock Divided By 1,  Duty cycle = clock source
+ *     @arg RCC_MCO_CLK_NUM1  MCOPRE[3:0] = 0001, PLL Clock Divided By 2,  Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ *     @arg RCC_MCO_CLK_NUM2  MCOPRE[3:0] = 0010, PLL Clock Divided By 3,  Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ *     @arg RCC_MCO_CLK_NUM3  MCOPRE[3:0] = 0011, PLL Clock Divided By 4,  Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ *     @arg RCC_MCO_CLK_NUM4  MCOPRE[3:0] = 0100, PLL Clock Divided By 5,  Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ *     @arg RCC_MCO_CLK_NUM5  MCOPRE[3:0] = 0101, PLL Clock Divided By 6,  Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ *     @arg RCC_MCO_CLK_NUM6  MCOPRE[3:0] = 0110, PLL Clock Divided By 7,  Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ *     @arg RCC_MCO_CLK_NUM7  MCOPRE[3:0] = 0111, PLL Clock Divided By 8,  Duty cycle = 1/((MCOPRE[3:0]+1)*2)
+ *     @arg RCC_MCO_CLK_NUM8  MCOPRE[3:0] = 1000, PLL Clock Divided By 2,  Duty cycle = 50%
+ *     @arg RCC_MCO_CLK_NUM9  MCOPRE[3:0] = 1001, PLL Clock Divided By 4,  Duty cycle = 50%
+ *     @arg RCC_MCO_CLK_NUM10 MCOPRE[3:0] = 1010, PLL Clock Divided By 6,  Duty cycle = 50%
+ *     @arg RCC_MCO_CLK_NUM11 MCOPRE[3:0] = 1011, PLL Clock Divided By 8,  Duty cycle = 50%
+ *     @arg RCC_MCO_CLK_NUM12 MCOPRE[3:0] = 1100, PLL Clock Divided By 10, Duty cycle = 50%
+ *     @arg RCC_MCO_CLK_NUM13 MCOPRE[3:0] = 1101, PLL Clock Divided By 12, Duty cycle = 50%
+ *     @arg RCC_MCO_CLK_NUM14 MCOPRE[3:0] = 1110, PLL Clock Divided By 14, Duty cycle = 50%
+ *     @arg RCC_MCO_CLK_NUM15 MCOPRE[3:0] = 1111, PLL Clock Divided By 16, Duty cycle = 50%
+ */
+void RCC_ConfigMcoClkPre(uint32_t RCC_MCOCLKPrescaler)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_MCOCLKPRE(RCC_MCOCLKPrescaler));
+
+    tmpregister = RCC->CFG;
+    /* Clear MCOPRE[3:0] bits */
+    tmpregister &= ((uint32_t)0x0FFFFFFF);
+    /* Set MCOPRE[3:0] bits according to RCC_ADCHCLKPrescaler value */
+    tmpregister |= RCC_MCOCLKPrescaler;
+
+    /* Store the new value */
+    RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief  Selects the clock source to output on MCO pin.
+ * @param RCC_MCO specifies the clock source to output.
+ *
+ *   this parameter can be one of the following values:
+ *     @arg RCC_MCO_NOCLK No clock selected
+ *     @arg RCC_MCO_LSI LSI oscillator clock selected
+ *     @arg RCC_MCO_LSE LSE oscillator clock selected
+ *     @arg RCC_MCO_MSI MSI oscillator clock selected
+ *     @arg RCC_MCO_SYSCLK System clock selected
+ *     @arg RCC_MCO_HSI HSI oscillator clock selected
+ *     @arg RCC_MCO_HSE HSE oscillator clock selected
+ *     @arg RCC_MCO_PLLCLK PLL clock selected
+ *
+ */
+void RCC_ConfigMco(uint8_t RCC_MCO)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_MCO(RCC_MCO));
+
+    tmpregister = RCC->CFG;
+    /* Clear MCO[2:0] bits */
+    tmpregister &= ((uint32_t)0xF8FFFFFF);
+    /* Set MCO[2:0] bits according to RCC_MCO value */
+    tmpregister |= ((uint32_t)(RCC_MCO << 24));
+
+    /* Store the new value */
+    RCC->CFG = tmpregister;
+}
+
+/**
+ * @brief  Checks whether the specified RCC flag is set or not.
+ * @param RCC_FLAG specifies the flag to check.
+ *
+ *   this parameter can be one of the following values:
+ *     @arg RCC_CTRL_FLAG_HSIRDF        HSI oscillator clock ready
+ *     @arg RCC_CTRL_FLAG_HSERDF        HSE oscillator clock ready
+ *     @arg RCC_CTRL_FLAG_PLLRDF        PLL clock ready
+ *     @arg RCC_LDCTRL_FLAG_LSERD       LSE oscillator clock ready
+ *     @arg RCC_LDCTRL_FLAG_LSECLKSSF   LSE Clock Security System failure status
+ *     @arg RCC_LDCTRL_FLAG_BORRSTF     BOR reset flag
+ *     @arg RCC_LDCTRL_FLAG_LDEMCRSTF   LowPower EMC reset flag
+ *     @arg RCC_CTRLSTS_FLAG_LSIRD      LSI oscillator clock ready
+ *     @arg RCC_CTRLSTS_FLAG_MSIRD      MSI oscillator clock ready
+ *     @arg RCC_CTRLSTS_FLAG_RAMRSTF    RAM reset flag
+ *     @arg RCC_CTRLSTS_FLAG_MMURSTF    MMU reset flag
+ *     @arg RCC_CTRLSTS_FLAG_PINRSTF    Pin reset
+ *     @arg RCC_CTRLSTS_FLAG_PORRSTF    POR reset
+ *     @arg RCC_CTRLSTS_FLAG_SFTRSTF    Software reset
+ *     @arg RCC_CTRLSTS_FLAG_IWDGRSTF   Independent Watchdog reset
+ *     @arg RCC_CTRLSTS_FLAG_WWDGRSTF   Window Watchdog reset
+ *     @arg RCC_CTRLSTS_FLAG_LPWRRSTF   Low Power reset
+ *
+ * @return The new state of RCC_FLAG (SET or RESET).
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+    uint32_t tmp         = 0;
+    uint32_t statusreg   = 0;
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+    /* Get the RCC register index */
+    tmp = RCC_FLAG >> 5;
+    if (tmp == 1) /* The flag to check is in CTRL register */
+    {
+        statusreg = RCC->CTRL;
+    }
+    else if (tmp == 2) /* The flag to check is in BDCTRL register */
+    {
+        statusreg = RCC->LDCTRL;
+    }
+    else /* The flag to check is in CTRLSTS register */
+    {
+        statusreg = RCC->CTRLSTS;
+    }
+
+    /* Get the flag position */
+    tmp = RCC_FLAG & FLAG_MASK;
+    if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    /* Return the flag status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the RCC reset flags.
+ * @note   The reset flags are: RCC_FLAG_LPEMCRST, RCC_FLAG_BORRST, RCC_FLAG_RAMRST, RCC_FLAG_MMURST,
+ *                              RCC_FLAG_PINRST, RCC_FLAG_PORRST,RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST,
+ *                              RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ */
+void RCC_ClrFlag(void)
+{
+    /* Set RMVF bit to clear the reset flags */
+    RCC->CTRLSTS |= CSR_RMRSTF_SET;
+    /* RMVF bit should be reset */
+    RCC->CTRLSTS &= CSR_RMVF_Reset;
+}
+
+/**
+ * @brief  Checks whether the specified RCC interrupt has occurred or not.
+ * @param RccInt specifies the RCC interrupt source to check.
+ *
+ *   this parameter can be one of the following values:
+ *     @arg RCC_INT_LSIRDIF LSI ready interrupt
+ *     @arg RCC_INT_LSERDIF LSE ready interrupt
+ *     @arg RCC_INT_HSIRDIF HSI ready interrupt
+ *     @arg RCC_INT_HSERDIF HSE ready interrupt
+ *     @arg RCC_INT_PLLRDIF PLL ready interrupt
+ *     @arg RCC_INT_BORIF interrupt
+ *     @arg RCC_INT_MSIRDIF MSI ready interrupt
+ *     @arg RCC_INT_CLKSSIF Clock Security System interrupt
+ *
+ * @return The new state of RccInt (SET or RESET).
+ */
+INTStatus RCC_GetIntStatus(uint8_t RccInt)
+{
+    INTStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_RCC_GET_INT(RccInt));
+
+    /* Check the status of the specified RCC interrupt */
+    if ((RCC->CLKINT & RccInt) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    /* Return the RccInt status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the RCC's interrupt pending bits.
+ * @param RccInt specifies the interrupt pending bit to clear.
+ *
+ *   this parameter can be any combination of the
+ *   following values:
+ *     @arg RCC_CLR_MSIRDIF Clear MSI ready interrupt flag
+ *     @arg RCC_CLR_LSIRDIF Clear LSI ready interrupt flag
+ *     @arg RCC_CLR_LSERDIF Clear LSE ready interrupt flag
+ *     @arg RCC_CLR_HSIRDIF Clear HSI ready interrupt flag
+ *     @arg RCC_CLR_HSERDIF Clear HSE ready interrupt flag
+ *     @arg RCC_CLR_PLLRDIF Clear PLL ready interrupt flag
+ *     @arg RCC_CLR_BORIF   Clear BOR interrupt flag
+ *     @arg RCC_CLR_CLKSSIF Clear Clock Security System interrupt flag
+ */
+void RCC_ClrIntPendingBit(uint32_t RccClrInt)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_CLR_INTF(RccClrInt));
+   /* Software set this bit to clear INT flag. */
+    RCC->CLKINT |= RccClrInt;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rtc.c

@@ -0,0 +1,2327 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_rtc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_rtc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @brief RTC driver modules
+ * @{
+ */
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK   ((uint32_t)0x007F7F7F)
+#define RTC_DATE_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+
+#define RTC_RSF_MASK           ((uint32_t)0xFFFFFFDF)
+#define RTC_FLAGS_MASK                                                                                                 \
+    ((uint32_t)(RTC_FLAG_TISOVF | RTC_FLAG_TISF | RTC_FLAG_WTF | RTC_FLAG_ALBF | RTC_FLAG_ALAF | RTC_FLAG_INITF        \
+                | RTC_FLAG_RSYF | RTC_FLAG_INITSF | RTC_FLAG_WTWF | RTC_FLAG_ALBWF | RTC_FLAG_ALAWF | RTC_FLAG_RECPF   \
+                | RTC_FLAG_SHOPF))
+
+#define INITMODE_TIMEOUT ((uint32_t)0x00002000)
+#define SYNCHRO_TIMEOUT  ((uint32_t)0x00008000)
+#define RECALPF_TIMEOUT  ((uint32_t)0x00001000)
+#define SHPF_TIMEOUT     ((uint32_t)0x00002000)
+
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/** @addtogroup RTC_Private_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to initialize and configure the
+         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+         RTC registers Write protection, enter and exit the RTC initialization mode,
+         RTC registers synchronization check and reference clock detection enable.
+         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+             It is split into 2 programmable prescalers to minimize power consumption.
+             (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+             (++) When both prescalers are used, it is recommended to configure the
+                 asynchronous prescaler to a high value to minimize consumption.
+         (#) All RTC registers are Write protected. Writing to the RTC registers
+             is enabled by writing a key into the Write Protection register, RTC_WRP.
+         (#) To Configure the RTC Calendar, user application should enter
+             initialization mode. In this mode, the calendar counter is stopped
+             and its value can be updated. When the initialization sequence is
+             complete, the calendar restarts counting after 4 RTCCLK cycles.
+         (#) To read the calendar through the shadow registers after Calendar
+             initialization, calendar update or after wakeup from low power modes
+             the software must first clear the RSYF flag. The software must then
+             wait until it is set again before reading the calendar, which means
+             that the calendar registers have been correctly copied into the
+             RTC_TSH and RTC_DATE shadow registers.The RTC_WaitForSynchro() function
+             implements the above software sequence (RSYF clear and RSYF check).
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Deinitializes the RTC registers to their default reset values.
+ * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
+ *         registers.
+ * @return An ErrorStatus enumeration value:
+ *          - SUCCESS: RTC registers are deinitialized
+ *          - ERROR: RTC registers are not deinitialized
+ */
+ErrorStatus RTC_DeInit(void)
+{
+    __IO uint32_t wutcounter = 0x00;
+    uint32_t wutwfstatus     = 0x00;
+    ErrorStatus status       = ERROR;
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Set Initialization mode */
+    if (RTC_EnterInitMode() == ERROR)
+    {
+        status = ERROR;
+    }
+    else
+    {
+        /* Reset TSH, DAT and CTRL registers */
+        RTC->TSH  = (uint32_t)0x00000000;
+        RTC->DATE = (uint32_t)0x00002101;
+
+        /* Reset All CTRL bits except CTRL[2:0] */
+        RTC->CTRL &= (uint32_t)0x00000007;
+
+        /* Wait till RTC WTWF flag is set and if Time out is reached exit */
+        do
+        {
+            wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF;
+            wutcounter++;
+        } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+
+        if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET)
+        {
+            status = ERROR;
+        }
+        else
+        {
+            /* Reset all RTC CTRL register bits */
+            RTC->CTRL &= (uint32_t)0x00000000;
+            RTC->WKUPT   = (uint32_t)0x0000FFFF;
+            RTC->PRE     = (uint32_t)0x007F00FF;
+            RTC->ALARMA  = (uint32_t)0x00000000;
+            RTC->ALARMB  = (uint32_t)0x00000000;
+            RTC->SCTRL   = (uint32_t)0x00000000;
+            RTC->CALIB   = (uint32_t)0x00000000;
+            RTC->ALRMASS = (uint32_t)0x00000000;
+            RTC->ALRMBSS = (uint32_t)0x00000000;
+
+            /* Reset INTSTS register and exit initialization mode */
+            RTC->INITSTS = (uint32_t)0x00000000;
+
+            RTC->OPT         = (uint32_t)0x00000000;
+            RTC->TSCWKUPCTRL = (uint32_t)0x00000008;
+            RTC->TSCWKUPCNT  = (uint32_t)0x000002FE;
+
+            /* Wait till the RTC RSYF flag is set */
+            if (RTC_WaitForSynchro() == ERROR)
+            {
+                status = ERROR;
+            }
+            else
+            {
+                status = SUCCESS;
+            }
+        }
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+
+    return status;
+}
+
+/**
+ * @brief  Initializes the RTC registers according to the specified parameters
+ *         in RTC_InitStruct.
+ * @param RTC_InitStruct pointer to a RTC_InitType structure that contains
+ *         the configuration information for the RTC peripheral.
+ * @note   The RTC Prescaler register is write protected and can be written in
+ *         initialization mode only.
+ * @return An ErrorStatus enumeration value:
+ *          - SUCCESS: RTC registers are initialized
+ *          - ERROR: RTC registers are not initialized
+ */
+ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct)
+{
+    ErrorStatus status = ERROR;
+    uint32_t i =0;
+    /* Check the parameters */
+    assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+    assert_param(IS_RTC_PREDIV_ASYNCH(RTC_InitStruct->RTC_AsynchPrediv));
+    assert_param(IS_RTC_PREDIV_SYNCH(RTC_InitStruct->RTC_SynchPrediv));
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+    /* Set Initialization mode */
+    if (RTC_EnterInitMode() == ERROR)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      /* Clear RTC CTRL HFMT Bit */
+      RTC->CTRL &= ((uint32_t) ~(RTC_CTRL_HFMT));
+      /* Set RTC_CTRL register */
+      RTC->CTRL |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
+      /* Configure the RTC PRE */
+      RTC->PRE = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
+      RTC->PRE |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
+      /* Exit Initialization mode */
+      RTC_ExitInitMode();
+      status = SUCCESS;
+    }
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+    /* Delay for the RTC prescale effect */
+    for(i=0;i<0x2FF;i++);
+    return status;
+}
+
+/**
+ * @brief  Fills each RTC_InitStruct member with its default value.
+ * @param RTC_InitStruct pointer to a RTC_InitType structure which will be
+ *         initialized.
+ */
+void RTC_StructInit(RTC_InitType* RTC_InitStruct)
+{
+    /* Initialize the RTC_HourFormat member */
+    RTC_InitStruct->RTC_HourFormat = RTC_24HOUR_FORMAT;
+
+    /* Initialize the RTC_AsynchPrediv member */
+    RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
+
+    /* Initialize the RTC_SynchPrediv member */
+    RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
+}
+
+/**
+ * @brief  Enables or disables the RTC registers write protection.
+ * @note   All the RTC registers are write protected except for RTC_INITSTS[13:8].
+ * @note   Writing a wrong key reactivates the write protection.
+ * @note   The protection mechanism is not affected by system reset.
+ * @param Cmd new state of the write protection.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableWriteProtection(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the write protection for RTC registers */
+        RTC->WRP = 0xFF;
+    }
+    else
+    {
+        /* Disable the write protection for RTC registers */
+        RTC->WRP = 0xCA;
+        RTC->WRP = 0x53;
+    }
+}
+
+/**
+ * @brief  Enters the RTC Initialization mode.
+ * @note   The RTC Initialization mode is write protected, use the
+ *         RTC_EnableWriteProtection(DISABLE) before calling this function.
+ * @return An ErrorStatus enumeration value:
+ *          - SUCCESS: RTC is in Init mode
+ *          - ERROR: RTC is not in Init mode
+ */
+ErrorStatus RTC_EnterInitMode(void)
+{
+    __IO uint32_t initcounter = 0x00;
+    ErrorStatus status        = ERROR;
+    uint32_t initstatus       = 0x00;
+
+    /* Check if the Initialization mode is set */
+    if ((RTC->INITSTS & RTC_INITSTS_INITF) == (uint32_t)RESET)
+    {
+        /* Set the Initialization mode */
+        RTC->INITSTS = (uint32_t)RTC_INITSTS_INITM;
+
+        /* Wait till RTC is in INIT state and if Time out is reached exit */
+        do
+        {
+            initstatus = RTC->INITSTS & RTC_INITSTS_INITF;
+            initcounter++;
+        } while ((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+
+        if ((RTC->INITSTS & RTC_INITSTS_INITF) != RESET)
+        {
+            status = SUCCESS;
+        }
+        else
+        {
+            status = ERROR;
+        }
+    }
+    else
+    {
+        status = SUCCESS;
+    }
+
+    return (status);
+}
+
+/**
+ * @brief  Exits the RTC Initialization mode.
+ * @note   When the initialization sequence is complete, the calendar restarts
+ *         counting after 4 RTCCLK cycles.
+ * @note   The RTC Initialization mode is write protected, use the
+ *         RTC_EnableWriteProtection(DISABLE) before calling this function.
+ */
+void RTC_ExitInitMode(void)
+{
+    /* Exit Initialization mode */
+    RTC->INITSTS &= (uint32_t)~RTC_INITSTS_INITM;
+}
+
+/**
+ * @brief  Waits until the RTC Time and Date registers (RTC_TSH and RTC_DATE) are
+ *         synchronized with RTC APB clock.
+ * @note   The RTC Resynchronization mode is write protected, use the
+ *         RTC_EnableWriteProtection(DISABLE) before calling this function.
+ * @note   To read the calendar through the shadow registers after Calendar
+ *         initialization, calendar update or after wakeup from low power modes
+ *         the software must first clear the RSYF flag.
+ *         The software must then wait until it is set again before reading
+ *         the calendar, which means that the calendar registers have been
+ *         correctly copied into the RTC_TSH and RTC_DATE shadow registers.
+ * @return An ErrorStatus enumeration value:
+ *          - SUCCESS: RTC registers are synchronised
+ *          - ERROR: RTC registers are not synchronised
+ */
+ErrorStatus RTC_WaitForSynchro(void)
+{
+    __IO uint32_t synchrocounter = 0;
+    ErrorStatus status           = ERROR;
+    uint32_t synchrostatus       = 0x00;
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Clear RSYF flag */
+    RTC->INITSTS &= (uint32_t)RTC_RSF_MASK;
+
+    /* Wait the registers to be synchronised */
+    do
+    {
+        synchrostatus = RTC->INITSTS & RTC_INITSTS_RSYF;
+        synchrocounter++;
+    } while ((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+
+    if ((RTC->INITSTS & RTC_INITSTS_RSYF) != RESET)
+    {
+        status = SUCCESS;
+    }
+    else
+    {
+        status = ERROR;
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+
+    return (status);
+}
+
+/**
+ * @brief  Enables or disables the RTC reference clock detection.
+ * @param Cmd new state of the RTC reference clock.
+ *   This parameter can be: ENABLE or DISABLE.
+ * @return An ErrorStatus enumeration value:
+ *          - SUCCESS: RTC reference clock detection is enabled
+ *          - ERROR: RTC reference clock detection is disabled
+ */
+ErrorStatus RTC_EnableRefClock(FunctionalState Cmd)
+{
+    ErrorStatus status = ERROR;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Set Initialization mode */
+    if (RTC_EnterInitMode() == ERROR)
+    {
+        status = ERROR;
+    }
+    else
+    {
+        if (Cmd != DISABLE)
+        {
+            /* Enable the RTC reference clock detection */
+            RTC->CTRL |= RTC_CTRL_REFCLKEN;
+        }
+        else
+        {
+            /* Disable the RTC reference clock detection */
+            RTC->CTRL &= ~RTC_CTRL_REFCLKEN;
+        }
+        /* Exit Initialization mode */
+        RTC_ExitInitMode();
+
+        status = SUCCESS;
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+
+    return status;
+}
+
+/**
+ * @brief  Enables or Disables the Bypass Shadow feature.
+ * @note   When the Bypass Shadow is enabled the calendar value are taken
+ *         directly from the Calendar counter.
+ * @param Cmd new state of the Bypass Shadow feature.
+ *         This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableBypassShadow(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    if (Cmd != DISABLE)
+    {
+        /* Set the BYPS bit */
+        RTC->CTRL |= (uint8_t)RTC_CTRL_BYPS;
+    }
+    else
+    {
+        /* Reset the BYPS bit */
+        RTC->CTRL &= (uint8_t)~RTC_CTRL_BYPS;
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group2 Time and Date configuration functions
+ *  @brief   Time and Date configuration functions
+ *
+@verbatim
+ ===============================================================================
+               ##### Time and Date configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to program and read the RTC
+         Calendar (Time and Date).
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Set the RTC current time.
+ * @param RTC_Format specifies the format of the entered parameters.
+ *   This parameter can be  one of the following values:
+ *     @arg RTC_FORMAT_BIN Binary data format.
+ *     @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure that contains
+ *                        the time configuration information for the RTC.
+ * @return An ErrorStatus enumeration value:
+ *          - SUCCESS: RTC Time register is configured
+ *          - ERROR: RTC Time register is not configured
+ */
+ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct)
+{
+    uint32_t tmpregister = 0;
+    ErrorStatus status   = ERROR;
+    /* Check the parameters */
+    assert_param(IS_RTC_FORMAT(RTC_Format));
+    if (RTC_Format == RTC_FORMAT_BIN)
+    {
+        if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+        {
+            assert_param(IS_RTC_12HOUR(RTC_TimeStruct->Hours));
+            assert_param(IS_RTC_H12(RTC_TimeStruct->H12));
+        }
+        else
+        {
+            RTC_TimeStruct->H12 = 0x00;
+            assert_param(IS_RTC_24HOUR(RTC_TimeStruct->Hours));
+        }
+        assert_param(IS_RTC_MINUTES(RTC_TimeStruct->Minutes));
+        assert_param(IS_RTC_SECONDS(RTC_TimeStruct->Seconds));
+    }
+    else
+    {
+        if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+        {
+            tmpregister = RTC_Bcd2ToByte(RTC_TimeStruct->Hours);
+            assert_param(IS_RTC_12HOUR(tmpregister));
+            assert_param(IS_RTC_H12(RTC_TimeStruct->H12));
+        }
+        else
+        {
+            RTC_TimeStruct->H12 = 0x00;
+            assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_TimeStruct->Hours)));
+        }
+        assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->Minutes)));
+        assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->Seconds)));
+    }
+    /* Check the input parameters format */
+    if (RTC_Format != RTC_FORMAT_BIN)
+    {
+        tmpregister = (((uint32_t)(RTC_TimeStruct->Hours) << 16) | ((uint32_t)(RTC_TimeStruct->Minutes) << 8)
+                       | ((uint32_t)RTC_TimeStruct->Seconds) | ((uint32_t)(RTC_TimeStruct->H12) << 16));
+    }
+    else
+    {
+        tmpregister =
+            (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Hours) << 16)
+                       | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Minutes) << 8)
+                       | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Seconds)) | (((uint32_t)RTC_TimeStruct->H12) << 16));
+    }
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+    /* Set Initialization mode */
+    if (RTC_EnterInitMode() == ERROR)
+    {
+        status = ERROR;
+    }
+    else
+    {
+        /* Set the RTC_TSH register */
+        RTC->TSH = (uint32_t)(tmpregister & RTC_TR_RESERVED_MASK);
+        /* Exit Initialization mode */
+        RTC_ExitInitMode();
+        /* If  RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */
+        if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET)
+        {
+            if (RTC_WaitForSynchro() == ERROR)
+            {
+                status = ERROR;
+            }
+            else
+            {
+                status = SUCCESS;
+            }
+        }
+        else
+        {
+            status = SUCCESS;
+        }
+    }
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+    /* Waits until the RTC Time and Date registers
+    (RTC_TSH and RTC_DATE) are  synchronized with RTC APB clock. */
+    status=RTC_WaitForSynchro();
+    return status;
+}
+
+/**
+ * @brief  Fills each RTC_TimeStruct member with its default value
+ *         (Time = 00h:00min:00sec).
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure which will be
+ *         initialized.
+ */
+void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct)
+{
+    /* Time = 00h:00min:00sec */
+    RTC_TimeStruct->H12     = RTC_AM_H12;
+    RTC_TimeStruct->Hours   = 0;
+    RTC_TimeStruct->Minutes = 0;
+    RTC_TimeStruct->Seconds = 0;
+}
+
+/**
+ * @brief  Get the RTC current Time.
+ * @param RTC_Format specifies the format of the returned parameters.
+ *   This parameter can be  one of the following values:
+ *     @arg RTC_FORMAT_BIN Binary data format.
+ *     @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_TimeStruct pointer to a RTC_TimeType structure that will
+ *                        contain the returned current time configuration.
+ */
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct)
+{
+    uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_FORMAT(RTC_Format));
+
+    /* Get the RTC_TSH register */
+    tmpregister = (uint32_t)(RTC->TSH & RTC_TR_RESERVED_MASK);
+
+    /* Fill the structure fields with the read parameters */
+    RTC_TimeStruct->Hours   = (uint8_t)((tmpregister & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16);
+    RTC_TimeStruct->Minutes = (uint8_t)((tmpregister & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8);
+    RTC_TimeStruct->Seconds = (uint8_t)(tmpregister & (RTC_TSH_SCT | RTC_TSH_SCU));
+    RTC_TimeStruct->H12     = (uint8_t)((tmpregister & (RTC_TSH_APM)) >> 16);
+
+    /* Check the input parameters format */
+    if (RTC_Format == RTC_FORMAT_BIN)
+    {
+        /* Convert the structure parameters to Binary format */
+        RTC_TimeStruct->Hours   = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Hours);
+        RTC_TimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Minutes);
+        RTC_TimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Seconds);
+    }
+}
+
+/**
+ * @brief  Gets the RTC current Calendar Subseconds value.
+ * @return RTC current Calendar Subseconds value.
+ */
+uint32_t RTC_GetSubSecond(void)
+{
+    uint32_t tmpregister = 0;
+
+    /* Get subseconds values from the correspondent registers*/
+    tmpregister = (uint32_t)(RTC->SUBS);
+
+    return (tmpregister);
+}
+
+/**
+ * @brief  Set the RTC current date.
+ * @param RTC_Format specifies the format of the entered parameters.
+ *   This parameter can be  one of the following values:
+ *     @arg RTC_FORMAT_BIN Binary data format.
+ *     @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_DateStruct pointer to a RTC_DateType structure that contains
+ *                         the date configuration information for the RTC.
+ * @return An ErrorStatus enumeration value:
+ *          - SUCCESS: RTC Date register is configured
+ *          - ERROR: RTC Date register is not configured
+ */
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct)
+{
+    uint32_t tmpregister = 0;
+    ErrorStatus status   = ERROR;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_FORMAT(RTC_Format));
+
+    if ((RTC_Format == RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10) == 0x10))
+    {
+        RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t) ~(0x10)) + 0x0A;
+    }
+    if (RTC_Format == RTC_FORMAT_BIN)
+    {
+        assert_param(IS_RTC_YEAR(RTC_DateStruct->Year));
+        assert_param(IS_RTC_MONTH(RTC_DateStruct->Month));
+        assert_param(IS_RTC_DATE(RTC_DateStruct->Date));
+    }
+    else
+    {
+        assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->Year)));
+        tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Month);
+        assert_param(IS_RTC_MONTH(tmpregister));
+        tmpregister = RTC_Bcd2ToByte(RTC_DateStruct->Date);
+        assert_param(IS_RTC_DATE(tmpregister));
+    }
+    assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+    /* Check the input parameters format */
+    if (RTC_Format != RTC_FORMAT_BIN)
+    {
+        tmpregister = ((((uint32_t)RTC_DateStruct->Year) << 16) | (((uint32_t)RTC_DateStruct->Month) << 8)
+                       | ((uint32_t)RTC_DateStruct->Date) | (((uint32_t)RTC_DateStruct->WeekDay) << 13));
+    }
+    else
+    {
+        tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Year) << 16)
+                       | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Month) << 8)
+                       | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Date)) | ((uint32_t)RTC_DateStruct->WeekDay << 13));
+    }
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Set Initialization mode */
+    if (RTC_EnterInitMode() == ERROR)
+    {
+        status = ERROR;
+    }
+    else
+    {
+        /* Set the RTC_DATE register */
+        RTC->DATE = (uint32_t)(tmpregister & RTC_DATE_RESERVED_MASK);
+
+        /* Exit Initialization mode */
+        RTC_ExitInitMode();
+
+        /* If  RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */
+        if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET)
+        {
+            if (RTC_WaitForSynchro() == ERROR)
+            {
+                status = ERROR;
+            }
+            else
+            {
+                status = SUCCESS;
+            }
+        }
+        else
+        {
+            status = SUCCESS;
+        }
+    }
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+    /* Waits until the RTC Time and Date registers
+    (RTC_TSH and RTC_DATE) are  synchronized with RTC APB clock. */
+    status=RTC_WaitForSynchro();
+    return status;
+}
+
+/**
+ * @brief  Fills each RTC_DateStruct member with its default value
+ *         (Monday, January 01 xx00).
+ * @param RTC_DateStruct pointer to a RTC_DateType structure which will be
+ *         initialized.
+ */
+void RTC_DateStructInit(RTC_DateType* RTC_DateStruct)
+{
+    /* Monday, January 01 xx00 */
+    RTC_DateStruct->WeekDay = RTC_WEEKDAY_MONDAY;
+    RTC_DateStruct->Date    = 1;
+    RTC_DateStruct->Month   = RTC_MONTH_JANUARY;
+    RTC_DateStruct->Year    = 0;
+}
+
+/**
+ * @brief  Get the RTC current date.
+ * @param RTC_Format specifies the format of the returned parameters.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_FORMAT_BIN Binary data format.
+ *     @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_DateStruct pointer to a RTC_DateType structure that will
+ *                        contain the returned current date configuration.
+ */
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct)
+{
+    uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_FORMAT(RTC_Format));
+
+    /* Get the RTC_TSH register */
+    tmpregister = (uint32_t)(RTC->DATE & RTC_DATE_RESERVED_MASK);
+
+    /* Fill the structure fields with the read parameters */
+    RTC_DateStruct->Year    = (uint8_t)((tmpregister & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16);
+    RTC_DateStruct->Month   = (uint8_t)((tmpregister & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8);
+    RTC_DateStruct->Date    = (uint8_t)(tmpregister & (RTC_DATE_DAT | RTC_DATE_DAU));
+    RTC_DateStruct->WeekDay = (uint8_t)((tmpregister & (RTC_DATE_WDU)) >> 13);
+
+    /* Check the input parameters format */
+    if (RTC_Format == RTC_FORMAT_BIN)
+    {
+        /* Convert the structure parameters to Binary format */
+        RTC_DateStruct->Year  = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Year);
+        RTC_DateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Month);
+        RTC_DateStruct->Date  = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Date);
+    }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group3 Alarms configuration functions
+ *  @brief   Alarms (Alarm A and Alarm B) configuration functions
+ *
+@verbatim
+ ===============================================================================
+         ##### Alarms (Alarm A and Alarm B) configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to program and read the RTC
+         Alarms.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Set the specified RTC Alarm.
+ * @note   The Alarm register can only be written when the corresponding Alarm
+ *         is disabled (Use the RTC_EnableAlarm(DISABLE)).
+ * @param RTC_Format specifies the format of the returned parameters.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_FORMAT_BIN Binary data format.
+ *     @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_A_ALARM to select Alarm A.
+ *     @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that
+ *                          contains the alarm configuration parameters.
+ */
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct)
+{
+    uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_FORMAT(RTC_Format));
+    assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+    assert_param(IS_ALARM_MASK(RTC_AlarmStruct->AlarmMask));
+    assert_param(IS_RTC_ALARM_WEEKDAY_SEL(RTC_AlarmStruct->DateWeekMode));
+
+    if (RTC_Format == RTC_FORMAT_BIN)
+    {
+        if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+        {
+            assert_param(IS_RTC_12HOUR(RTC_AlarmStruct->AlarmTime.Hours));
+            assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12));
+        }
+        else
+        {
+            RTC_AlarmStruct->AlarmTime.H12 = 0x00;
+            assert_param(IS_RTC_24HOUR(RTC_AlarmStruct->AlarmTime.Hours));
+        }
+        assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+        assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+        if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE)
+        {
+            assert_param(IS_RTC_ALARM_WEEKDAY_DATE(RTC_AlarmStruct->DateWeekValue));
+        }
+        else
+        {
+            assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(RTC_AlarmStruct->DateWeekValue));
+        }
+    }
+    else
+    {
+        if ((RTC->CTRL & RTC_CTRL_HFMT) != (uint32_t)RESET)
+        {
+            tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours);
+            assert_param(IS_RTC_12HOUR(tmpregister));
+            assert_param(IS_RTC_H12(RTC_AlarmStruct->AlarmTime.H12));
+        }
+        else
+        {
+            RTC_AlarmStruct->AlarmTime.H12 = 0x00;
+            assert_param(IS_RTC_24HOUR(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours)));
+        }
+
+        assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes)));
+        assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+        if (RTC_AlarmStruct->DateWeekMode == RTC_ALARM_SEL_WEEKDAY_DATE)
+        {
+            tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+            assert_param(IS_RTC_ALARM_WEEKDAY_DATE(tmpregister));
+        }
+        else
+        {
+            tmpregister = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+            assert_param(IS_RTC_ALARM_WEEKDAY_WEEKDAY(tmpregister));
+        }
+    }
+
+    /* Check the input parameters format */
+    if (RTC_Format != RTC_FORMAT_BIN)
+    {
+        tmpregister =
+            (((uint32_t)(RTC_AlarmStruct->AlarmTime.Hours) << 16)
+             | ((uint32_t)(RTC_AlarmStruct->AlarmTime.Minutes) << 8) | ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds)
+             | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) | ((uint32_t)(RTC_AlarmStruct->DateWeekValue) << 24)
+             | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask));
+    }
+    else
+    {
+        tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Hours) << 16)
+                       | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Minutes) << 8)
+                       | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Seconds))
+                       | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16)
+                       | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->DateWeekValue) << 24)
+                       | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask));
+    }
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Configure the Alarm register */
+    if (RTC_Alarm == RTC_A_ALARM)
+    {
+        RTC->ALARMA = (uint32_t)tmpregister;
+    }
+    else
+    {
+        RTC->ALARMB = (uint32_t)tmpregister;
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief  Fills each RTC_AlarmStruct member with its default value
+ *         (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+ *         all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref RTC_AlarmType structure which
+ *         will be initialized.
+ */
+void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct)
+{
+    /* Alarm Time Settings : Time = 00h:00mn:00sec */
+    RTC_AlarmStruct->AlarmTime.H12     = RTC_AM_H12;
+    RTC_AlarmStruct->AlarmTime.Hours   = 0;
+    RTC_AlarmStruct->AlarmTime.Minutes = 0;
+    RTC_AlarmStruct->AlarmTime.Seconds = 0;
+
+    /* Alarm Date Settings : Date = 1st day of the month */
+    RTC_AlarmStruct->DateWeekMode  = RTC_ALARM_SEL_WEEKDAY_DATE;
+    RTC_AlarmStruct->DateWeekValue = 1;
+
+    /* Alarm Masks Settings : Mask =  all fields are not masked */
+    RTC_AlarmStruct->AlarmMask = RTC_ALARMMASK_NONE;
+}
+
+/**
+ * @brief  Get the RTC Alarm value and masks.
+ * @param RTC_Format specifies the format of the output parameters.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_FORMAT_BIN Binary data format.
+ *     @arg RTC_FORMAT_BCD BCD data format.
+ * @param RTC_Alarm specifies the alarm to be read.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_A_ALARM to select Alarm A.
+ *     @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmStruct pointer to a RTC_AlarmType structure that will
+ *                          contains the output alarm configuration values.
+ */
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct)
+{
+    uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_FORMAT(RTC_Format));
+    assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+
+    /* Get the RTC_ALARMx register */
+    if (RTC_Alarm == RTC_A_ALARM)
+    {
+        tmpregister = (uint32_t)(RTC->ALARMA);
+    }
+    else
+    {
+        tmpregister = (uint32_t)(RTC->ALARMB);
+    }
+
+    /* Fill the structure with the read parameters */
+    RTC_AlarmStruct->AlarmTime.Hours   = (uint32_t)((tmpregister & (RTC_ALARMA_HOT | RTC_ALARMA_HOU)) >> 16);
+    RTC_AlarmStruct->AlarmTime.Minutes = (uint32_t)((tmpregister & (RTC_ALARMA_MIT | RTC_ALARMA_MIU)) >> 8);
+    RTC_AlarmStruct->AlarmTime.Seconds = (uint32_t)(tmpregister & (RTC_ALARMA_SET | RTC_ALARMA_SEU));
+    RTC_AlarmStruct->AlarmTime.H12     = (uint32_t)((tmpregister & RTC_ALARMA_APM) >> 16);
+    RTC_AlarmStruct->DateWeekValue     = (uint32_t)((tmpregister & (RTC_ALARMA_DTT | RTC_ALARMA_DTU)) >> 24);
+    RTC_AlarmStruct->DateWeekMode      = (uint32_t)(tmpregister & RTC_ALARMA_WKDSEL);
+    RTC_AlarmStruct->AlarmMask         = (uint32_t)(tmpregister & RTC_ALARMMASK_ALL);
+
+    if (RTC_Format == RTC_FORMAT_BIN)
+    {
+        RTC_AlarmStruct->AlarmTime.Hours   = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours);
+        RTC_AlarmStruct->AlarmTime.Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes);
+        RTC_AlarmStruct->AlarmTime.Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds);
+        RTC_AlarmStruct->DateWeekValue     = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue);
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified RTC Alarm.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ *   This parameter can be any combination of the following values:
+ *     @arg RTC_A_ALARM to select Alarm A.
+ *     @arg RTC_B_ALARM to select Alarm B.
+ * @param Cmd new state of the specified alarm.
+ *   This parameter can be: ENABLE or DISABLE.
+ * @return An ErrorStatus enumeration value:
+ *          - SUCCESS: RTC Alarm is enabled/disabled
+ *          - ERROR: RTC Alarm is not enabled/disabled
+ */
+ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd)
+{
+    __IO uint32_t alarmcounter = 0x00;
+    uint32_t alarmstatus       = 0x00;
+    ErrorStatus status         = ERROR;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_ALARM_ENABLE(RTC_Alarm));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Configure the Alarm state */
+    if (Cmd != DISABLE)
+    {
+        RTC->CTRL |= (uint32_t)RTC_Alarm;
+
+        status = SUCCESS;
+    }
+    else
+    {
+        /* Disable the Alarm in RTC_CTRL register */
+        RTC->CTRL &= (uint32_t)~RTC_Alarm;
+
+        /* Wait till RTC ALxWF flag is set and if Time out is reached exit */
+        do
+        {
+            alarmstatus = RTC->INITSTS & (RTC_Alarm >> 8);
+            alarmcounter++;
+        } while ((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
+
+        if ((RTC->INITSTS & (RTC_Alarm >> 8)) == RESET)
+        {
+            status = ERROR;
+        }
+        else
+        {
+            status = SUCCESS;
+        }
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+
+    return status;
+}
+
+/**
+ * @brief  Configure the RTC AlarmA/B Subseconds value and mask.*
+ * @note   This function is performed only when the Alarm is disabled.
+ * @param RTC_Alarm specifies the alarm to be configured.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_A_ALARM to select Alarm A.
+ *     @arg RTC_B_ALARM to select Alarm B.
+ * @param RTC_AlarmSubSecondValue specifies the Subseconds value.
+ *   This parameter can be a value from 0 to 0x00007FFF.
+ * @param RTC_AlarmSubSecondMask specifies the Subseconds Mask.
+ *   This parameter can be any combination of the following values:
+ *     @arg RTC_SUBS_MASK_ALL All Alarm SS fields are masked.
+ *                                      There is no comparison on sub seconds for Alarm.
+ *     @arg RTC_SUBS_MASK_SS14_1 SS[14:1] are don't care in Alarm comparison.
+ *                                         Only SS[0] is compared
+ *     @arg RTC_SUBS_MASK_SS14_2 SS[14:2] are don't care in Alarm comparison.
+ *                                          Only SS[1:0] are compared
+ *     @arg RTC_SUBS_MASK_SS14_3 SS[14:3] are don't care in Alarm comparison.
+ *                                          Only SS[2:0] are compared
+ *     @arg RTC_SUBS_MASK_SS14_4 SS[14:4] are don't care in Alarm comparison.
+ *                                          Only SS[3:0] are compared
+ *     @arg RTC_SUBS_MASK_SS14_5 SS[14:5] are don't care in Alarm comparison.
+ *                                          Only SS[4:0] are compared.
+ *     @arg RTC_SUBS_MASK_SS14_6 SS[14:6] are don't care in Alarm comparison.
+ *                                          Only SS[5:0] are compared.
+ *     @arg RTC_SUBS_MASK_SS14_7 SS[14:7] are don't care in Alarm comparison.
+ *                                          Only SS[6:0] are compared.
+ *     @arg RTC_SUBS_MASK_SS14_8 SS[14:8] are don't care in Alarm comparison.
+ *                                          Only SS[7:0] are compared.
+ *     @arg RTC_SUBS_MASK_SS14_9 SS[14:9] are don't care in Alarm comparison.
+ *                                          Only SS[8:0] are compared.
+ *     @arg RTC_SUBS_MASK_SS14_10 SS[14:10] are don't care in Alarm comparison.
+ *                                          Only SS[9:0] are compared.
+ *     @arg RTC_SUBS_MASK_SS14_11 SS[14:11] are don't care in Alarm comparison.
+ *                                          Only SS[10:0] are compared.
+ *     @arg RTC_SUBS_MASK_SS14_12 SS[14:12] are don't care in Alarm comparison.
+ *                                          Only SS[11:0] are compared.
+ *     @arg RTC_SUBS_MASK_SS14_13 SS[14:13] are don't care in Alarm comparison.
+ *                                          Only SS[12:0] are compared.
+ *     @arg RTC_SUBS_MASK_SS14_14 SS[14] is don't care in Alarm comparison.
+ *                                          Only SS[13:0] are compared.
+ *     @arg RTC_SUBS_MASK_NONE SS[14:0] are compared and must match
+ *                                          to activate alarm.
+ */
+void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
+{
+    uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_ALARM_SEL(RTC_Alarm));
+    assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
+    assert_param(IS_RTC_ALARM_SUB_SECOND_MASK_MODE(RTC_AlarmSubSecondMask));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Configure the Alarm A or Alarm B SubSecond registers */
+    tmpregister = (uint32_t)(uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
+
+    if (RTC_Alarm == RTC_A_ALARM)
+    {
+        /* Configure the AlarmA SubSecond register */
+        RTC->ALRMASS = tmpregister;
+    }
+    else
+    {
+        /* Configure the Alarm B SubSecond register */
+        RTC->ALRMBSS = tmpregister;
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief  Gets the RTC Alarm Subseconds value.
+ * @param RTC_Alarm specifies the alarm to be read.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_A_ALARM to select Alarm A.
+ *     @arg RTC_B_ALARM to select Alarm B.
+ * @return RTC Alarm Subseconds value.
+ */
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
+{
+    uint32_t tmpregister = 0;
+
+    /* Get the RTC_ALARMx register */
+    if (RTC_Alarm == RTC_A_ALARM)
+    {
+        tmpregister = (uint32_t)((RTC->ALRMASS) & RTC_ALRMASS_SSV);
+    }
+    else
+    {
+        tmpregister = (uint32_t)((RTC->ALRMBSS) & RTC_ALRMBSS_SSV);
+    }
+
+    return (tmpregister);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group4 WakeUp Timer configuration functions
+ *  @brief   WakeUp Timer configuration functions
+ *
+@verbatim
+ ===============================================================================
+               ##### WakeUp Timer configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to program and read the RTC WakeUp.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Configures the RTC Wakeup clock source.
+ * @note   The WakeUp Clock source can only be changed when the RTC WakeUp
+ *         is disabled (Use the RTC_EnableWakeUp(DISABLE)).
+ * @param RTC_WakeUpClock Wakeup Clock source.
+ *   This parameter can be one of the following values:
+ *            @arg RTC_WKUPCLK_RTCCLK_DIV16 RTC Wakeup Counter Clock = RTCCLK/16.
+ *            @arg RTC_WKUPCLK_RTCCLK_DIV8 RTC Wakeup Counter Clock = RTCCLK/8.
+ *            @arg RTC_WKUPCLK_RTCCLK_DIV4 RTC Wakeup Counter Clock = RTCCLK/4.
+ *            @arg RTC_WKUPCLK_RTCCLK_DIV2 RTC Wakeup Counter Clock = RTCCLK/2.
+ *            @arg RTC_WKUPCLK_CK_SPRE_16BITS RTC Wakeup Counter Clock = CK_SPRE.
+ *            @arg RTC_WKUPCLK_CK_SPRE_17BITS RTC Wakeup Counter Clock = CK_SPRE.
+ */
+void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_WKUP_CLOCK(RTC_WakeUpClock));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Clear the Wakeup Timer clock source bits in CTRL register */
+    RTC->CTRL &= (uint32_t)~RTC_CTRL_WKUPSEL;
+
+    /* Configure the clock source */
+    RTC->CTRL |= (uint32_t)RTC_WakeUpClock;
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief  Configures the RTC Wakeup counter.
+ * @note   The RTC WakeUp counter can only be written when the RTC WakeUp.
+ *         is disabled (Use the RTC_EnableWakeUp(DISABLE)).
+ * @param RTC_WakeUpCounter specifies the WakeUp counter.
+ *   This parameter can be a value from 0x0000 to 0xFFFF.
+ */
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_WKUP_COUNTER(RTC_WakeUpCounter));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Configure the Wakeup Timer counter */
+    RTC->WKUPT = (uint32_t)RTC_WakeUpCounter;
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief  Returns the RTC WakeUp timer counter value.
+ * @return The RTC WakeUp Counter value.
+ */
+uint32_t RTC_GetWakeUpCounter(void)
+{
+    /* Get the counter value */
+    return ((uint32_t)(RTC->WKUPT & RTC_WKUPT_WKUPT));
+}
+
+/**
+ * @brief  Enables or Disables the RTC WakeUp timer.
+ * @param Cmd new state of the WakeUp timer.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd)
+{
+    __IO uint32_t wutcounter = 0x00;
+    uint32_t wutwfstatus     = 0x00;
+    ErrorStatus status       = ERROR;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the Wakeup Timer */
+        RTC->CTRL |= (uint32_t)RTC_CTRL_WTEN;
+        status = SUCCESS;
+    }
+    else
+    {
+        /* Disable the Wakeup Timer */
+        RTC->CTRL &= (uint32_t)~RTC_CTRL_WTEN;
+        /* Wait till RTC WTWF flag is set and if Time out is reached exit */
+        do
+        {
+            wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF;
+            wutcounter++;
+        } while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+
+        if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET)
+        {
+            status = ERROR;
+        }
+        else
+        {
+            status = SUCCESS;
+        }
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+
+    return status;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group5 Daylight Saving configuration functions
+ *  @brief   Daylight Saving configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Daylight Saving configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to configure the RTC DayLight Saving.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Adds or substract one hour from the current time.
+ * @param RTC_DayLightSaving the value of hour adjustment.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_DAYLIGHT_SAVING_SUB1H Substract one hour (winter time).
+ *     @arg RTC_DAYLIGHT_SAVING_ADD1H Add one hour (summer time).
+ * @param RTC_StoreOperation Specifies the value to be written in the BCK bit
+ *                            in CTRL register to store the operation.
+ *   This parameter can be one of the following values:
+ *            @arg RTC_STORE_OPERATION_RESET BCK Bit Reset.
+ *            @arg RTC_STORE_OPERATION_SET BCK Bit Set.
+ */
+void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+    assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Clear the bits to be configured */
+    RTC->CTRL &= (uint32_t) ~(RTC_CTRL_BAKP);
+    /* Clear the SU1H and AD1H bits to be configured */
+    RTC->CTRL &= (uint32_t) ~(RTC_CTRL_SU1H & RTC_CTRL_AD1H);
+    /* Configure the RTC_CTRL register */
+    RTC->CTRL |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief  Returns the RTC Day Light Saving stored operation.
+ * @return RTC Day Light Saving stored operation.
+ *          - RTC_STORE_OPERATION_RESET
+ *          - RTC_STORE_OPERATION_SET
+ */
+uint32_t RTC_GetStoreOperation(void)
+{
+    return (RTC->CTRL & RTC_CTRL_BAKP);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group6 Output pin Configuration function
+ *  @brief   Output pin Configuration function
+ *
+@verbatim
+ ===============================================================================
+                  ##### Output pin Configuration function #####
+ ===============================================================================
+    [..] This section provide functions allowing to configure the RTC Output source.
+
+@endverbatim
+  * @{
+  */
+
+
+
+/**
+ * @brief  Configures the RTC output source (AFO_ALARM).
+ * @param RTC_Output Specifies which signal will be routed to the RTC output.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_OUTPUT_DIS No output selected
+ *     @arg RTC_OUTPUT_ALA signal of AlarmA mapped to output.
+ *     @arg RTC_OUTPUT_ALB signal of AlarmB mapped to output.
+ *     @arg RTC_OUTPUT_WKUP signal of WakeUp mapped to output.
+ * @param RTC_OutputPolarity Specifies the polarity of the output signal.
+ *   This parameter can be one of the following:
+ *     @arg RTC_OUTPOL_HIGH The output pin is high when the
+ *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL).
+ *     @arg RTC_OUTPOL_LOW The output pin is low when the
+ *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL).
+ */
+void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_OUTPUT_MODE(RTC_Output));
+    assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Clear the bits to be configured */
+    RTC->CTRL &= (uint32_t) ~(RTC_CTRL_OUTSEL | RTC_CTRL_OPOL);
+
+    /* Configure the output selection and polarity */
+    RTC->CTRL |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group7 Coarse and Smooth Calibrations configuration functions
+ *  @brief   Coarse and Smooth Calibrations configuration functions
+ *
+@verbatim
+ ===============================================================================
+        ##### Coarse and Smooth Calibrations configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Enables or disables the RTC clock to be output through the relative
+ *         pin.
+ * @param Cmd new state of the coarse calibration Output.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableCalibOutput(FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the RTC clock output */
+        RTC->CTRL |= (uint32_t)RTC_CTRL_COEN;
+    }
+    else
+    {
+        /* Disable the RTC clock output */
+        RTC->CTRL &= (uint32_t)~RTC_CTRL_COEN;
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param RTC_CalibOutput Select the Calibration output Selection .
+ *   This parameter can be one of the following values:
+ *     @arg RTC_CALIB_OUTPUT_256HZ A signal has a regular waveform at 256Hz.
+ *     @arg RTC_CALIB_OUTPUT_1HZ A signal has a regular waveform at 1Hz.
+ */
+void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /*clear flags before config*/
+    RTC->CTRL &= (uint32_t) ~(RTC_CTRL_CALOSEL);
+
+    /* Configure the RTC_CTRL register */
+    RTC->CTRL |= (uint32_t)RTC_CalibOutput;
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief  Configures the Smooth Calibration Settings.
+ * @param RTC_SmoothCalibPeriod Select the Smooth Calibration Period.
+ *   This parameter can be can be one of the following values:
+ *     @arg SMOOTH_CALIB_32SEC The smooth calibration periode is 32s.
+ *     @arg SMOOTH_CALIB_16SEC The smooth calibration periode is 16s.
+ *     @arg SMOOTH_CALIB_8SEC The smooth calibartion periode is 8s.
+ * @param RTC_SmoothCalibPlusPulses Select to Set or reset the CALP bit.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_SMOOTH_CALIB_PLUS_PULSES_SET Add one RTCCLK puls every 2**11 pulses.
+ *     @arg RTC_SMOOTH_CALIB_PLUS_PULSES__RESET No RTCCLK pulses are added.
+ * @param RTC_SmouthCalibMinusPulsesValue Select the value of CALM[8:0] bits.
+ *   This parameter can be one any value from 0 to 0x000001FF.
+ * @return An ErrorStatus enumeration value:
+ *          - SUCCESS: RTC Calib registers are configured
+ *          - ERROR: RTC Calib registers are not configured
+ */
+ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod,
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue)
+{
+    ErrorStatus status    = ERROR;
+    uint32_t recalpfcount = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_SMOOTH_CALIB_PERIOD_SEL(RTC_SmoothCalibPeriod));
+    assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+    assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* check if a calibration is pending*/
+    if ((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET)
+    {
+        /* wait until the Calibration is completed*/
+        while (((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+        {
+            recalpfcount++;
+        }
+    }
+
+    /* check if the calibration pending is completed or if there is no calibration operation at all*/
+    if ((RTC->INITSTS & RTC_INITSTS_RECPF) == RESET)
+    {
+        /* Configure the Smooth calibration settings */
+        RTC->CALIB = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses
+                                | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
+
+        status = SUCCESS;
+    }
+    else
+    {
+        status = ERROR;
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+
+    return (ErrorStatus)(status);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group8 TimeStamp configuration functions
+ *  @brief   TimeStamp configuration functions
+ *
+@verbatim
+ ===============================================================================
+                 ##### TimeStamp configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Enables or Disables the RTC TimeStamp functionality with the
+ *         specified time stamp pin stimulating edge.
+ * @param RTC_TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ *         activated.
+ *   This parameter can be one of the following:
+ *     @arg RTC_TIMESTAMP_EDGE_RISING the Time stamp event occurs on the rising
+ *                                    edge of the related pin.
+ *     @arg RTC_TIMESTAMP_EDGE_FALLING the Time stamp event occurs on the
+ *                                     falling edge of the related pin.
+ * @param Cmd new state of the TimeStamp.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd)
+{
+    uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_TIMESTAMP_EDGE_MODE(RTC_TimeStampEdge));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    /* Get the RTC_CTRL register and clear the bits to be configured */
+    tmpregister = (uint32_t)(RTC->CTRL & (uint32_t) ~(RTC_CTRL_TEDGE | RTC_CTRL_TSEN));
+
+    /* Get the new configuration */
+    if (Cmd != DISABLE)
+    {
+        tmpregister |= (uint32_t)(RTC_TimeStampEdge | RTC_CTRL_TSEN);
+    }
+    else
+    {
+        tmpregister |= (uint32_t)(RTC_TimeStampEdge);
+    }
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Configure the Time Stamp TSEDGE and Enable bits */
+    RTC->CTRL = (uint32_t)tmpregister;
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief  Get the RTC TimeStamp value and masks.
+ * @param RTC_Format specifies the format of the output parameters.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_FORMAT_BIN Binary data format
+ *     @arg RTC_FORMAT_BCD BCD data format
+ * @param RTC_StampTimeStruct pointer to a RTC_TimeType structure that will
+ *                             contains the TimeStamp time values.
+ * @param RTC_StampDateStruct pointer to a RTC_DateType structure that will
+ *                             contains the TimeStamp date values.
+ */
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct)
+{
+    uint32_t tmptime = 0, tmpdate = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_FORMAT(RTC_Format));
+
+    /* Get the TimeStamp time and date registers values */
+    tmptime = (uint32_t)(RTC->TST & RTC_TR_RESERVED_MASK);
+    tmpdate = (uint32_t)(RTC->TSD & RTC_DATE_RESERVED_MASK);
+
+    /* Fill the Time structure fields with the read parameters */
+    RTC_StampTimeStruct->Hours   = (uint8_t)((tmptime & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16);
+    RTC_StampTimeStruct->Minutes = (uint8_t)((tmptime & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8);
+    RTC_StampTimeStruct->Seconds = (uint8_t)(tmptime & (RTC_TSH_SCT | RTC_TSH_SCU));
+    RTC_StampTimeStruct->H12     = (uint8_t)((tmptime & (RTC_TSH_APM)) >> 16);
+
+    /* Fill the Date structure fields with the read parameters */
+    RTC_StampDateStruct->Year    = (uint8_t)((tmpdate & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16);
+    RTC_StampDateStruct->Month   = (uint8_t)((tmpdate & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8);
+    RTC_StampDateStruct->Date    = (uint8_t)(tmpdate & (RTC_DATE_DAT | RTC_DATE_DAU));
+    RTC_StampDateStruct->WeekDay = (uint8_t)((tmpdate & (RTC_DATE_WDU)) >> 13);
+
+    /* Check the input parameters format */
+    if (RTC_Format == RTC_FORMAT_BIN)
+    {
+        /* Convert the Time structure parameters to Binary format */
+        RTC_StampTimeStruct->Hours   = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Hours);
+        RTC_StampTimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Minutes);
+        RTC_StampTimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Seconds);
+
+        /* Convert the Date structure parameters to Binary format */
+        RTC_StampDateStruct->Month   = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Month);
+        RTC_StampDateStruct->Date    = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Date);
+        RTC_StampDateStruct->WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->WeekDay);
+    }
+}
+
+/**
+ * @brief  Get the RTC timestamp Subseconds value.
+ * @return RTC current timestamp Subseconds value.
+ */
+uint32_t RTC_GetTimeStampSubSecond(void)
+{
+    /* Get timestamp subseconds values from the correspondent registers */
+    return (uint32_t)(RTC->TSSS);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group11 Output Type Config configuration functions
+ *  @brief   Output Type Config configuration functions
+ *
+@verbatim
+ ===============================================================================
+             ##### Output Type Config configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Configures the RTC Output Pin mode.
+ * @param RTC_OutputType specifies the RTC Output (PC13) pin mode.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_OUTPUT_OPENDRAIN RTC Output (PC13) is configured in
+ *                                    Open Drain mode.
+ *     @arg RTC_OUTPUT_PUSHPULL RTC Output (PC13) is configured in
+ *                                    Push Pull mode.
+ */
+void RTC_ConfigOutputType(uint32_t RTC_OutputType)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
+
+    RTC->OPT &= (uint32_t) ~(RTC_OPT_TYPE);
+    RTC->OPT |= (uint32_t)(RTC_OutputType);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group12 Shift control synchronisation functions
+ *  @brief   Shift control synchronisation functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Shift control synchronisation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Configures the Synchronization Shift Control Settings.
+ * @note   When REFCKON is set, firmware must not write to Shift control register
+ * @param RTC_ShiftAdd1S Select to add or not 1 second to the time Calendar.
+ *   This parameter can be one of the following values :
+ *     @arg RTC_SHIFT_ADD1S_ENABLE Add one second to the clock calendar.
+ *     @arg RTC_SHIFT_ADD1S_DISABLE No effect.
+ * @param RTC_ShiftSubFS Select the number of Second Fractions to Substitute.
+ *         This parameter can be one any value from 0 to 0x7FFF.
+ * @return An ErrorStatus enumeration value:
+ *          - SUCCESS: RTC Shift registers are configured
+ *          - ERROR: RTC Shift registers are not configured
+ */
+ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
+{
+    ErrorStatus status = ERROR;
+    uint32_t shpfcount = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
+    assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    /* Check if a Shift is pending*/
+    if ((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET)
+    {
+        /* Wait until the shift is completed*/
+        while (((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+        {
+            shpfcount++;
+        }
+    }
+
+    /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+    if ((RTC->INITSTS & RTC_INITSTS_SHOPF) == RESET)
+    {
+        /* check if the reference clock detection is disabled */
+        if ((RTC->CTRL & RTC_CTRL_REFCLKEN) == RESET)
+        {
+            /* Configure the Shift settings */
+            RTC->SCTRL = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
+
+            if (RTC_WaitForSynchro() == ERROR)
+            {
+                status = ERROR;
+            }
+            else
+            {
+                status = SUCCESS;
+            }
+        }
+        else
+        {
+            status = ERROR;
+        }
+    }
+    else
+    {
+        status = ERROR;
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+
+    return (ErrorStatus)(status);
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Group13 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] All RTC interrupts are connected to the EXTI controller.
+         (+) To enable the RTC Alarm interrupt, the following sequence is required:
+         (+) Configure and enable the EXTI Line 17 in interrupt mode and select
+             the rising edge sensitivity using the EXTI_InitPeripheral() function.
+         (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using
+             the NVIC_Init() function.
+         (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B)
+             using the RTC_SetAlarm() and RTC_EnableAlarm() functions.
+
+         (+) To enable the RTC Wakeup interrupt, the following sequence is required:
+         (+) Configure and enable the EXTI Line 20 in interrupt mode and select
+             the rising edge sensitivity using the EXTI_InitPeripheral() function.
+         (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the
+             NVIC_Init() function.
+         (+) Configure the RTC to generate the RTC wakeup timer event using the
+             RTC_ConfigWakeUpClock(), RTC_SetWakeUpCounter() and RTC_EnableWakeUp()
+             functions.
+
+         (+) To enable the RTC Tamper interrupt, the following sequence is required:
+         (+) Configure and enable the EXTI Line 19 in interrupt mode and select
+             the rising edge sensitivity using the EXTI_InitPeripheral() function.
+         (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
+             the NVIC_Init() function.
+         (+) Configure the RTC to detect the RTC tamper event using the
+             RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+
+         (+) To enable the RTC TimeStamp interrupt, the following sequence is
+             required:
+         (+) Configure and enable the EXTI Line 19 in interrupt mode and select
+             the rising edge sensitivity using the EXTI_InitPeripheral() function.
+         (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using
+             the NVIC_Init() function.
+         (+) Configure the RTC to detect the RTC time-stamp event using the
+             RTC_EnableTimeStamp() functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+ * @brief  Enables or disables the specified RTC interrupts.
+ * @param RTC_INT specifies the RTC interrupt sources to be enabled or disabled.
+ *   This parameter can be any combination of the following values:
+ *     @arg RTC_INT_TS Time Stamp interrupt mask.
+ *     @arg RTC_INT_WUT WakeUp Timer interrupt mask.
+ *     @arg RTC_INT_ALRB Alarm B interrupt mask.
+ *     @arg RTC_INT_ALRA Alarm A interrupt mask.
+ * @param Cmd new state of the specified RTC interrupts.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_CONFIG_INT(RTC_INT));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    /* Disable the write protection for RTC registers */
+    RTC->WRP = 0xCA;
+    RTC->WRP = 0x53;
+
+    if (Cmd != DISABLE)
+    {
+        /* Configure the Interrupts in the RTC_CTRL register */
+        RTC->CTRL |= (uint32_t)(RTC_INT & ~RTC_TMPCFG_TPINTEN);
+    }
+    else
+    {
+        /* Configure the Interrupts in the RTC_CTRL register */
+        RTC->CTRL &= (uint32_t) ~(RTC_INT & (uint32_t)~RTC_TMPCFG_TPINTEN);
+    }
+    /* Enable the write protection for RTC registers */
+    RTC->WRP = 0xFF;
+}
+
+/**
+ * @brief  Checks whether the specified RTC flag is set or not.
+ * @param RTC_FLAG specifies the flag to check.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_FLAG_RECPF RECALPF event flag.
+ *     @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.
+ *     @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.
+ *     @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.
+ *     @arg RTC_FLAG_TISOVF Time Stamp OverFlow flag.
+ *     @arg RTC_FLAG_TISF Time Stamp event flag.
+ *     @arg RTC_FLAG_WTF WakeUp Timer flag.
+ *     @arg RTC_FLAG_ALBF Alarm B flag.
+ *     @arg RTC_FLAG_ALAF Alarm A flag.
+ *     @arg RTC_FLAG_INITF Initialization mode flag.
+ *     @arg RTC_FLAG_RSYF Registers Synchronized flag.
+ *     @arg RTC_FLAG_INITSF Registers Configured flag.
+ *     @arg RTC_FLAG_SHOPF Shift operation pending flag.
+ *     @arg RTC_FLAG_WTWF WakeUp Timer Write flag.
+ *     @arg RTC_FLAG_ALBWF Alarm B Write flag.
+ *     @arg RTC_FLAG_ALAWF Alarm A write flag.
+ * @return The new state of RTC_FLAG (SET or RESET).
+ */
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+    /* Get all the flags */
+    tmpregister = (uint32_t)(RTC->INITSTS & RTC_FLAGS_MASK);
+
+    /* Return the status of the flag */
+    if ((tmpregister & RTC_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the RTC's pending flags.
+ * @param RTC_FLAG specifies the RTC flag to clear.
+ *   This parameter can be any combination of the following values:.
+ *     @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.
+ *     @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.
+ *     @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.
+ *     @arg RTC_FLAG_TISOVF Time Stamp Overflow flag.
+ *     @arg RTC_FLAG_TISF Time Stamp event flag.
+ *     @arg RTC_FLAG_WTF WakeUp Timer flag.
+ *     @arg RTC_FLAG_ALBF Alarm B flag.
+ *     @arg RTC_FLAG_ALAF Alarm A flag.
+ *     @arg RTC_FLAG_RSYF Registers Synchronized flag.
+ */
+void RTC_ClrFlag(uint32_t RTC_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+    /* Clear the Flags in the RTC_INITSTS register */
+    RTC->INITSTS = (uint32_t)(
+        (uint32_t)(~((RTC_FLAG | RTC_INITSTS_INITM) & 0x0001FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM)));
+}
+
+/**
+ * @brief  Checks whether the specified RTC interrupt has occurred or not.
+ * @param RTC_INT specifies the RTC interrupt source to check.
+ *   This parameter can be one of the following values:
+ *     @arg RTC_INT_TS Time Stamp interrupt.
+ *     @arg RTC_INT_WUT WakeUp Timer interrupt.
+ *     @arg RTC_INT_ALRB Alarm B interrupt.
+ *     @arg RTC_INT_ALRA Alarm A interrupt.
+ * @return The new state of RTC_INT (SET or RESET).
+ */
+INTStatus RTC_GetITStatus(uint32_t RTC_INT)
+{
+    INTStatus bitstatus  = RESET;
+    uint32_t tmpregister = 0, enablestatus = 0;
+    uint8_t tamperEnable = 0;
+    /* Check the parameters */
+    assert_param(IS_RTC_GET_INT(RTC_INT));
+
+    /* Get the Interrupt enable Status */
+    if ((RTC_INT == RTC_INT_TAMP1) || (RTC_INT == RTC_INT_TAMP2)|| (RTC_INT == RTC_INT_TAMP3))
+    {
+        tamperEnable = ((RTC->TMPCFG & 0x00ff0000)>>16);
+        if (tamperEnable > 0)
+        {
+            enablestatus = SET;
+        }
+
+    }
+    else
+    {
+       enablestatus = (uint32_t)((RTC->CTRL & RTC_INT));
+
+    }
+    /* Get the Interrupt pending bit */
+    tmpregister = (uint32_t)((RTC->INITSTS & (uint32_t)(RTC_INT >> 4)));
+
+    /* Get the status of the Interrupt */
+    if ((enablestatus != (uint32_t)RESET) && ((tmpregister & 0x0000FFFF) != (uint32_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the RTC's interrupt pending bits.
+ * @param RTC_INT specifies the RTC interrupt pending bit to clear.
+ *   This parameter can be any combination of the following values:
+ *     @arg RTC_INT_TS Time Stamp interrupt
+ *     @arg RTC_INT_WUT WakeUp Timer interrupt
+ *     @arg RTC_INT_ALRB Alarm B interrupt
+ *     @arg RTC_INT_ALRA Alarm A interrupt
+ */
+void RTC_ClrIntPendingBit(uint32_t RTC_INT)
+{
+    uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_CLEAR_INT(RTC_INT));
+
+    /* Get the RTC_INITSTS Interrupt pending bits mask */
+    tmpregister = (uint32_t)(RTC_INT >> 4);
+
+    /* Clear the interrupt pending bits in the RTC_INITSTS register */
+    RTC->INITSTS = (uint32_t)(
+        (uint32_t)(~((tmpregister | RTC_INITSTS_INITM) & 0x0000FFFF) | (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM)));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @brief  Converts a 2 digit decimal to BCD format.
+ * @param Value Byte to be converted.
+ * @return Converted byte
+ */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+    uint8_t bcdhigh = 0;
+
+    while (Value >= 10)
+    {
+        bcdhigh++;
+        Value -= 10;
+    }
+
+    return ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+ * @brief  Convert from 2 digit BCD to Binary.
+ * @param Value BCD value to be converted.
+ * @return Converted word
+ */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+    uint8_t tmp = 0;
+    tmp         = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+    return (tmp + (Value & (uint8_t)0x0F));
+}
+/**
+ * @brief  Enable wakeup tsc functionand wakeup by the set time
+ * @param  count wakeup time.
+ */
+void RTC_EnableWakeUpTsc(uint32_t count)
+{
+    // Wait until bit RTC_TSCWKUPCTRL_WKUPOFF is 1
+    while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF))
+    {
+    }
+    // enter config  wakeup cnt mode
+    RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPCNF;
+    // config tsc wakeup cnt ,tsc wakeup module counting cycle = WAKUPCNT * LSE/LSI
+    RTC->TSCWKUPCNT = count;
+    // exit config wakeup cnt mode
+    RTC->TSCWKUPCTRL &= ~(RTC_TSCWKUPCTRL_WKUPCNF);
+    while (!(RTC->TSCWKUPCTRL & RTC_TSCWKUPCTRL_WKUPOFF))
+    {
+    }
+    // TSC wakeup enable
+    RTC->TSCWKUPCTRL = RTC_TSCWKUPCTRL_WKUPEN;
+}
+
+/** @defgroup RTC_Group9 Tampers configuration functions
+ *  @brief   Tampers configuration functions
+ *
+@verbatim
+ ===============================================================================
+                 ##### Tampers configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the select Tamper pin edge.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_Tamper_1: Select Tamper 1.
+  *     @arg RTC_Tamper_2: Select Tamper 2.
+  *     @arg RTC_Tamper_3: Select Tamper 3.
+  * @param  RTC_TamperTrigger: Specifies the trigger on the tamper pin that
+  *                            stimulates tamper event.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
+  *     @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
+  *     @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
+  *     @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
+  * @retval None
+  */
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_TAMPER(RTC_Tamper));
+    assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
+    if (RTC_Tamper == RTC_TAMPER_3)
+    {
+        RTC_TamperTrigger <<= 5;
+    }
+    else if (RTC_Tamper == RTC_TAMPER_2)
+    {
+        RTC_TamperTrigger <<= 3;
+    }
+    /* Configure the RTC_TAMPCR register */
+    RTC->TMPCFG |= (uint32_t)(RTC_Tamper | RTC_TamperTrigger);
+
+}
+
+/**
+  * @brief  Enables or Disables the Tamper detection.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_TAMPER_1: Select Tamper 1.
+  *     @arg RTC_TAMPER_2: Select Tamper 2.
+  *     @arg RTC_TAMPER_3: Select Tamper 3.
+  * @param  NewState: new state of the tamper pin.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected Tamper pin */
+    RTC->TMPCFG |= (uint32_t)RTC_Tamper;
+  }
+  else
+  {
+    /* Disable the selected Tamper pin */
+    RTC->TMPCFG &= (uint32_t)~RTC_Tamper;
+  }
+}
+
+/**
+  * @brief  Configures the Tampers Filter.
+  * @param  RTC_TamperFilter: Specifies the tampers filter.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
+  *     @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive
+  *                                    samples at the active level.
+  *     @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive
+  *                                    samples at the active level.
+  *     @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive
+  *                                    samples at the active level.
+  * @retval None
+  */
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
+
+  /* Clear TAMPFLT[1:0] bits in the RTC_TAMPCR register */
+  RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPFLT);
+
+  /* Configure the RTC_TAMPCR register */
+  RTC->TMPCFG |= (uint32_t)RTC_TamperFilter;
+}
+
+/**
+  * @brief  Configures the Tampers Sampling Frequency.
+  * @param  RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 32768
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 16384
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 8192
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 4096
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 2048
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 1024
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 512
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 256
+  * @retval None
+  */
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
+
+  /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */
+  RTC->TMPCFG &= (uint32_t)~(RTC_TAMPCR_TAMPFREQ);
+
+  /* Configure the RTC_TAMPCR register */
+  RTC->TMPCFG |= (uint32_t)RTC_TamperSamplingFreq;
+}
+
+/**
+  * @brief  Configures the Tampers Pins input Precharge Duration.
+  * @param  RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+  *         Precharge Duration.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle.
+  *     @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle.
+  *     @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle.
+  *     @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle.
+  * @retval None
+  */
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
+
+  /* Clear TAMPPRCH[1:0] bits in the RTC_TAMPCR register */
+  RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPPRCH);
+
+  /* Configure the RTC_TAMPCR register */
+  RTC->TMPCFG |= (uint32_t)RTC_TamperPrechargeDuration;
+}
+
+/**
+  * @brief  Enables or Disables the TimeStamp on Tamper Detection Event.
+  * @note   The timestamp is valid even the TSEN bit in tamper control register
+  *         is reset.
+  * @param  NewState: new state of the timestamp on tamper event.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Save timestamp on tamper detection event */
+    RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS;
+  }
+  else
+  {
+    /* Tamper detection does not cause a timestamp to be saved */
+    RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS;
+  }
+}
+
+/**
+  * @brief  Enables or Disables the Precharge of Tamper pin.
+  * @param  NewState: new state of tamper pull up.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TamperPullUpCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+  {
+    /* Enable precharge of the selected Tamper pin */
+    RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPPUDIS;
+  }
+  else
+  {
+    /* Disable precharge of the selected Tamper pin */
+    RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPPUDIS;
+  }
+}
+
+/**
+  * @brief  Enables or Disables the TAMPTS.
+  * @param  NewState: new state of TAMPTS.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TamperTAMPTSCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+  {
+    /* Enable precharge of the selected Tamper pin */
+    RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS;
+  }
+  else
+  {
+    /* Disable precharge of the selected Tamper pin */
+    RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS;
+  }
+}
+
+/**
+  * @brief  Enables or Disables the Tamper detection.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_TAMPER1_INT: Select Tamper 1.
+  *     @arg RTC_TAMPER2_INT: Select Tamper 2.
+  *     @arg RTC_TAMPER3_INT: Select Tamper 3.
+  * @param  NewState: new state of the tamper pin.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(TAMPxIE));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected Tamper pin */
+    RTC->TMPCFG |= (uint32_t)TAMPxIE;
+  }
+  else
+  {
+    /* Disable the selected Tamper pin */
+    RTC->TMPCFG &= (uint32_t)~TAMPxIE;
+  }
+}
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_spi.c

@@ -0,0 +1,853 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_spi.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_spi.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+/** @addtogroup SPI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Defines
+ * @{
+ */
+
+/* SPI SPIEN mask */
+#define CTRL1_SPIEN_ENABLE  ((uint16_t)0x0040)
+#define CTRL1_SPIEN_DISABLE ((uint16_t)0xFFBF)
+
+/* I2S I2SEN mask */
+#define I2SCFG_I2SEN_ENABLE  ((uint16_t)0x0400)
+#define I2SCFG_I2SEN_DISABLE ((uint16_t)0xFBFF)
+
+/* SPI CRCNEXT mask */
+#define CTRL1_CRCNEXT_ENABLE ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CTRL1_CRCEN_ENABLE  ((uint16_t)0x2000)
+#define CTRL1_CRCEN_DISABLE ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CTRL2_SSOEN_ENABLE  ((uint16_t)0x0004)
+#define CTRL2_SSOEN_DISABLE ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CTRL1_CLR_MASK  ((uint16_t)0x3040)
+#define I2SCFG_CLR_MASK ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_MODE_ENABLE ((uint16_t)0xF7FF)
+#define I2S_MODE_ENABLE ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S1_CLKSRC  ((uint32_t)(0x00020000))
+#define I2S2_CLKSRC  ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the SPIx peripheral registers to their default
+ *         reset values (Affects also the I2Ss).
+ * @param SPIx where x can be 1, 2 to select the SPI peripheral.
+ */
+void SPI_I2S_DeInit(SPI_Module* SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+
+    if (SPIx == SPI1)
+    {
+        /* Enable SPI1 reset state */
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, ENABLE);
+        /* Release SPI1 from reset state */
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, DISABLE);
+    }
+    else if (SPIx == SPI2)
+    {
+        /* Enable SPI2 reset state */
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, ENABLE);
+        /* Release SPI2 from reset state */
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI2, DISABLE);
+    }
+
+}
+
+/**
+ * @brief  Initializes the SPIx peripheral according to the specified
+ *         parameters in the SPI_InitStruct.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param SPI_InitStruct pointer to a SPI_InitType structure that
+ *         contains the configuration information for the specified SPI peripheral.
+ */
+void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct)
+{
+    uint16_t tmpregister = 0;
+
+    /* check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+
+    /* Check the SPI parameters */
+    assert_param(IS_SPI_DIR_MODE(SPI_InitStruct->DataDirection));
+    assert_param(IS_SPI_MODE(SPI_InitStruct->SpiMode));
+    assert_param(IS_SPI_DATASIZE(SPI_InitStruct->DataLen));
+    assert_param(IS_SPI_CLKPOL(SPI_InitStruct->CLKPOL));
+    assert_param(IS_SPI_CLKPHA(SPI_InitStruct->CLKPHA));
+    assert_param(IS_SPI_NSS(SPI_InitStruct->NSS));
+    assert_param(IS_SPI_BR_PRESCALER(SPI_InitStruct->BaudRatePres));
+    assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->FirstBit));
+    assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+
+    /*---------------------------- SPIx CTRL1 Configuration ------------------------*/
+    /* Get the SPIx CTRL1 value */
+    tmpregister = SPIx->CTRL1;
+    /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+    tmpregister &= CTRL1_CLR_MASK;
+    /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+       master/salve mode, CPOL and CPHA */
+    /* Set BIDImode, BIDIOE and RxONLY bits according to DataDirection value */
+    /* Set SSM, SSI and MSTR bits according to SpiMode and NSS values */
+    /* Set LSBFirst bit according to FirstBit value */
+    /* Set BR bits according to BaudRatePres value */
+    /* Set CPOL bit according to CLKPOL value */
+    /* Set CPHA bit according to CLKPHA value */
+    tmpregister |= (uint16_t)((uint32_t)SPI_InitStruct->DataDirection | SPI_InitStruct->SpiMode
+                              | SPI_InitStruct->DataLen | SPI_InitStruct->CLKPOL | SPI_InitStruct->CLKPHA
+                              | SPI_InitStruct->NSS | SPI_InitStruct->BaudRatePres | SPI_InitStruct->FirstBit);
+    /* Write to SPIx CTRL1 */
+    SPIx->CTRL1 = tmpregister;
+
+    /* Activate the SPI mode (Reset I2SMOD bit in I2SCFG register) */
+    SPIx->I2SCFG &= SPI_MODE_ENABLE;
+
+    /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+    /* Write to SPIx CRCPOLY */
+    SPIx->CRCPOLY = SPI_InitStruct->CRCPoly;
+}
+
+/**
+ * @brief  Initializes the SPIx peripheral according to the specified
+ *         parameters in the I2S_InitStruct.
+ * @param SPIx where x can be  1 or 2 to select the SPI peripheral
+ *         (configured in I2S mode).
+ * @param I2S_InitStruct pointer to an I2S_InitType structure that
+ *         contains the configuration information for the specified SPI peripheral
+ *         configured in I2S mode.
+ * @note
+ *  The function calculates the optimal prescaler needed to obtain the most
+ *  accurate audio frequency (depending on the I2S clock source, the PLL values
+ *  and the product configuration). But in case the prescaler value is greater
+ *  than 511, the default value (0x02) will be configured instead.  *
+ */
+void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct)
+{
+    uint16_t tmpregister = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+    uint32_t tmp = 0;
+    RCC_ClocksType RCC_Clocks;
+    uint32_t sourceclock = 0;
+
+    /* Check the I2S parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_I2S_MODE(I2S_InitStruct->I2sMode));
+    assert_param(IS_I2S_STANDARD(I2S_InitStruct->Standard));
+    assert_param(IS_I2S_DATA_FMT(I2S_InitStruct->DataFormat));
+    assert_param(IS_I2S_MCLK_ENABLE(I2S_InitStruct->MCLKEnable));
+    assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFrequency));
+    assert_param(IS_I2S_CLKPOL(I2S_InitStruct->CLKPOL));
+
+    /*----------------------- SPIx I2SCFG & I2SPREDIV Configuration -----------------*/
+    /* Clear I2SMOD, I2SE, MODCFG, PCMSYNC, STDSEL, CKPOL, TDATLEN and CHLEN bits */
+    SPIx->I2SCFG &= I2SCFG_CLR_MASK;
+    SPIx->I2SPREDIV = 0x0002;
+
+    /* Get the I2SCFG register value */
+    tmpregister = SPIx->I2SCFG;
+
+    /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+    if (I2S_InitStruct->AudioFrequency == I2S_AUDIO_FREQ_DEFAULT)
+    {
+        i2sodd = (uint16_t)0;
+        i2sdiv = (uint16_t)2;
+    }
+    /* If the requested audio frequency is not the default, compute the prescaler */
+    else
+    {
+        /* Check the frame length (For the Prescaler computing) */
+        if (I2S_InitStruct->DataFormat == I2S_DATA_FMT_16BITS)
+        {
+            /* Packet length is 16 bits */
+            packetlength = 1;
+        }
+        else
+        {
+            /* Packet length is 32 bits */
+            packetlength = 2;
+        }
+
+        /* Get the I2S clock source mask depending on the peripheral number */
+        if (((uint32_t)SPIx) == SPI2_BASE)
+        {
+            /* The mask is relative to I2S1 */
+            tmp = I2S1_CLKSRC;
+        }
+        else
+        {
+            /* The mask is relative to I2S2 */
+            tmp = I2S2_CLKSRC;
+        }
+
+        /* I2S Clock source is System clock: Get System Clock frequency */
+        RCC_GetClocksFreqValue(&RCC_Clocks);
+
+        /* Get the source clock value: based on System Clock value */
+        sourceclock = RCC_Clocks.SysclkFreq;
+
+        /* Compute the Real divider depending on the MCLK output state with a floating point */
+        if (I2S_InitStruct->MCLKEnable == I2S_MCLK_ENABLE)
+        {
+            /* MCLK output is enabled */
+            tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->AudioFrequency)) + 5);
+        }
+        else
+        {
+            /* MCLK output is disabled */
+            tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->AudioFrequency)) + 5);
+        }
+
+        /* Remove the floating point */
+        tmp = tmp / 10;
+
+        /* Check the parity of the divider */
+        i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+        /* Compute the i2sdiv prescaler */
+        i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+        /* Get the Mask for the Odd bit (SPI_I2SPREDIV[8]) register */
+        i2sodd = (uint16_t)(i2sodd << 8);
+    }
+
+    /* Test if the divider is 1 or 0 or greater than 0xFF */
+    if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+    {
+        /* Set the default values */
+        i2sdiv = 2;
+        i2sodd = 0;
+    }
+
+    /* Write to SPIx I2SPREDIV register the computed value */
+    SPIx->I2SPREDIV = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->MCLKEnable));
+
+    /* Configure the I2S with the SPI_InitStruct values */
+    tmpregister |= (uint16_t)(
+        I2S_MODE_ENABLE
+        | (uint16_t)(I2S_InitStruct->I2sMode
+                     | (uint16_t)(I2S_InitStruct->Standard
+                                  | (uint16_t)(I2S_InitStruct->DataFormat | (uint16_t)I2S_InitStruct->CLKPOL))));
+
+    /* Write to SPIx I2SCFG */
+    SPIx->I2SCFG = tmpregister;
+}
+
+/**
+ * @brief  Fills each SPI_InitStruct member with its default value.
+ * @param SPI_InitStruct pointer to a SPI_InitType structure which will be initialized.
+ */
+void SPI_InitStruct(SPI_InitType* SPI_InitStruct)
+{
+    /*--------------- Reset SPI init structure parameters values -----------------*/
+    /* Initialize the DataDirection member */
+    SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX;
+    /* initialize the SpiMode member */
+    SPI_InitStruct->SpiMode = SPI_MODE_SLAVE;
+    /* initialize the DataLen member */
+    SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS;
+    /* Initialize the CLKPOL member */
+    SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW;
+    /* Initialize the CLKPHA member */
+    SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE;
+    /* Initialize the NSS member */
+    SPI_InitStruct->NSS = SPI_NSS_HARD;
+    /* Initialize the BaudRatePres member */
+    SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2;
+    /* Initialize the FirstBit member */
+    SPI_InitStruct->FirstBit = SPI_FB_MSB;
+    /* Initialize the CRCPoly member */
+    SPI_InitStruct->CRCPoly = 7;
+}
+
+/**
+ * @brief  Fills each I2S_InitStruct member with its default value.
+ * @param I2S_InitStruct pointer to a I2S_InitType structure which will be initialized.
+ */
+void I2S_InitStruct(I2S_InitType* I2S_InitStruct)
+{
+    /*--------------- Reset I2S init structure parameters values -----------------*/
+    /* Initialize the I2sMode member */
+    I2S_InitStruct->I2sMode = I2S_MODE_SlAVE_TX;
+
+    /* Initialize the Standard member */
+    I2S_InitStruct->Standard = I2S_STD_PHILLIPS;
+
+    /* Initialize the DataFormat member */
+    I2S_InitStruct->DataFormat = I2S_DATA_FMT_16BITS;
+
+    /* Initialize the MCLKEnable member */
+    I2S_InitStruct->MCLKEnable = I2S_MCLK_DISABLE;
+
+    /* Initialize the AudioFrequency member */
+    I2S_InitStruct->AudioFrequency = I2S_AUDIO_FREQ_DEFAULT;
+
+    /* Initialize the CLKPOL member */
+    I2S_InitStruct->CLKPOL = I2S_CLKPOL_LOW;
+}
+
+/**
+ * @brief  Enables or disables the specified SPI peripheral.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx peripheral.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected SPI peripheral */
+        SPIx->CTRL1 |= CTRL1_SPIEN_ENABLE;
+    }
+    else
+    {
+        /* Disable the selected SPI peripheral */
+        SPIx->CTRL1 &= CTRL1_SPIEN_DISABLE;
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx peripheral.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected SPI peripheral (in I2S mode) */
+        SPIx->I2SCFG |= I2SCFG_I2SEN_ENABLE;
+    }
+    else
+    {
+        /* Disable the selected SPI peripheral (in I2S mode) */
+        SPIx->I2SCFG &= I2SCFG_I2SEN_DISABLE;
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified SPI/I2S interrupts.
+ * @param SPIx where x can be
+ *   - 1 or 2 in SPI mode
+ *   - 1 or 2 in I2S mode
+ * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to be enabled or disabled.
+ *   This parameter can be one of the following values:
+ *     @arg SPI_I2S_INT_TE Tx buffer empty interrupt mask
+ *     @arg SPI_I2S_INT_RNE Rx buffer not empty interrupt mask
+ *     @arg SPI_I2S_INT_ERR Error interrupt mask
+ * @param Cmd new state of the specified SPI/I2S interrupt.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd)
+{
+    uint16_t itpos = 0, itmask = 0;
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    assert_param(IS_SPI_I2S_CONFIG_INT(SPI_I2S_IT));
+
+    /* Get the SPI/I2S IT index */
+    itpos = SPI_I2S_IT >> 4;
+
+    /* Set the IT mask */
+    itmask = (uint16_t)1 << (uint16_t)itpos;
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected SPI/I2S interrupt */
+        SPIx->CTRL2 |= itmask;
+    }
+    else
+    {
+        /* Disable the selected SPI/I2S interrupt */
+        SPIx->CTRL2 &= (uint16_t)~itmask;
+    }
+}
+
+/**
+ * @brief  Enables or disables the SPIx/I2Sx DMA interface.
+ * @param SPIx where x can be
+ *   - 1 or 2 in SPI mode
+ *   - 1 or 2 in I2S mode
+ * @param SPI_I2S_DMAReq specifies the SPI/I2S DMA transfer request to be enabled or disabled.
+ *   This parameter can be any combination of the following values:
+ *     @arg SPI_I2S_DMA_TX Tx buffer DMA transfer request
+ *     @arg SPI_I2S_DMA_RX Rx buffer DMA transfer request
+ * @param Cmd new state of the selected SPI/I2S DMA transfer request.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    assert_param(IS_SPI_I2S_DMA(SPI_I2S_DMAReq));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected SPI/I2S DMA requests */
+        SPIx->CTRL2 |= SPI_I2S_DMAReq;
+    }
+    else
+    {
+        /* Disable the selected SPI/I2S DMA requests */
+        SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq;
+    }
+}
+
+/**
+ * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
+ * @param SPIx where x can be
+ *   - 1 or 2 in SPI mode
+ *   - 1 or 2 in I2S mode
+ * @param Data Data to be transmitted.
+ */
+void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+
+    /* Write in the DAT register the data to be sent */
+    SPIx->DAT = Data;
+}
+
+/**
+ * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral.
+ * @param SPIx where x can be
+ *   - 1 or 2 in SPI mode
+ *   - 1 or 2 in I2S mode
+ * @return The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+
+    /* Return the data in the DAT register */
+    return SPIx->DAT;
+}
+
+/**
+ * @brief  Configures internally by software the NSS pin for the selected SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param SPI_NSSInternalSoft specifies the SPI NSS internal state.
+ *   This parameter can be one of the following values:
+ *     @arg SPI_NSS_HIGH Set NSS pin internally
+ *     @arg SPI_NSS_LOW Reset NSS pin internally
+ */
+void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_SPI_NSS_LEVEL(SPI_NSSInternalSoft));
+    if (SPI_NSSInternalSoft != SPI_NSS_LOW)
+    {
+        /* Set NSS pin internally by software */
+        SPIx->CTRL1 |= SPI_NSS_HIGH;
+    }
+    else
+    {
+        /* Reset NSS pin internally by software */
+        SPIx->CTRL1 &= SPI_NSS_LOW;
+    }
+}
+
+/**
+ * @brief  Enables or disables the SS output for the selected SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx SS output.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected SPI SS output */
+        SPIx->CTRL2 |= CTRL2_SSOEN_ENABLE;
+    }
+    else
+    {
+        /* Disable the selected SPI SS output */
+        SPIx->CTRL2 &= CTRL2_SSOEN_DISABLE;
+    }
+}
+
+/**
+ * @brief  Configures the data size for the selected SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param DataLen specifies the SPI data size.
+ *   This parameter can be one of the following values:
+ *     @arg SPI_DATA_SIZE_16BITS Set data frame format to 16bit
+ *     @arg SPI_DATA_SIZE_8BITS Set data frame format to 8bit
+ */
+void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_SPI_DATASIZE(DataLen));
+    /* Clear DFF bit */
+    SPIx->CTRL1 &= (uint16_t)~SPI_DATA_SIZE_16BITS;
+    /* Set new DFF bit value */
+    SPIx->CTRL1 |= DataLen;
+}
+
+/**
+ * @brief  Transmit the SPIx CRC value.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ */
+void SPI_TransmitCrcNext(SPI_Module* SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+
+    /* Enable the selected SPI CRC transmission */
+    SPIx->CTRL1 |= CTRL1_CRCNEXT_ENABLE;
+}
+
+/**
+ * @brief  Enables or disables the CRC value calculation of the transferred bytes.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param Cmd new state of the SPIx CRC value calculation.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected SPI CRC calculation */
+        SPIx->CTRL1 |= CTRL1_CRCEN_ENABLE;
+    }
+    else
+    {
+        /* Disable the selected SPI CRC calculation */
+        SPIx->CTRL1 &= CTRL1_CRCEN_DISABLE;
+    }
+}
+
+/**
+ * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param SPI_CRC specifies the CRC register to be read.
+ *   This parameter can be one of the following values:
+ *     @arg SPI_CRC_TX Selects Tx CRC register
+ *     @arg SPI_CRC_RX Selects Rx CRC register
+ * @return The selected CRC register value..
+ */
+uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC)
+{
+    uint16_t crcreg = 0;
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_SPI_CRC(SPI_CRC));
+    if (SPI_CRC != SPI_CRC_RX)
+    {
+        /* Get the Tx CRC register */
+        crcreg = SPIx->CRCTDAT;
+    }
+    else
+    {
+        /* Get the Rx CRC register */
+        crcreg = SPIx->CRCRDAT;
+    }
+    /* Return the selected CRC register */
+    return crcreg;
+}
+
+/**
+ * @brief  Returns the CRC Polynomial register value for the specified SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @return The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPoly(SPI_Module* SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+
+    /* Return the CRC polynomial register */
+    return SPIx->CRCPOLY;
+}
+
+/**
+ * @brief  Selects the data transfer direction in bi-directional mode for the specified SPI.
+ * @param SPIx where x can be 1 or 2 to select the SPI peripheral.
+ * @param DataDirection specifies the data transfer direction in bi-directional mode.
+ *   This parameter can be one of the following values:
+ *     @arg SPI_BIDIRECTION_TX Selects Tx transmission direction
+ *     @arg SPI_BIDIRECTION_RX Selects Rx receive direction
+ */
+void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_SPI_BIDIRECTION(DataDirection));
+    if (DataDirection == SPI_BIDIRECTION_TX)
+    {
+        /* Set the Tx only mode */
+        SPIx->CTRL1 |= SPI_BIDIRECTION_TX;
+    }
+    else
+    {
+        /* Set the Rx only mode */
+        SPIx->CTRL1 &= SPI_BIDIRECTION_RX;
+    }
+}
+
+/**
+ * @brief  Checks whether the specified SPI/I2S flag is set or not.
+ * @param SPIx where x can be
+ *   - 1 or 2 in SPI mode
+ *   - 1 or 2 in I2S mode
+ * @param SPI_I2S_FLAG specifies the SPI/I2S flag to check.
+ *   This parameter can be one of the following values:
+ *     @arg SPI_I2S_TE_FLAG Transmit buffer empty flag.
+ *     @arg SPI_I2S_RNE_FLAG Receive buffer not empty flag.
+ *     @arg SPI_I2S_BUSY_FLAG Busy flag.
+ *     @arg SPI_I2S_OVER_FLAG Overrun flag.
+ *     @arg SPI_MODERR_FLAG Mode Fault flag.
+ *     @arg SPI_CRCERR_FLAG CRC Error flag.
+ *     @arg I2S_UNDER_FLAG Underrun Error flag.
+ *     @arg I2S_CHSIDE_FLAG Channel Side flag.
+ * @return The new state of SPI_I2S_FLAG (SET or RESET).
+ */
+FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+    /* Check the status of the specified SPI/I2S flag */
+    if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET)
+    {
+        /* SPI_I2S_FLAG is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* SPI_I2S_FLAG is reset */
+        bitstatus = RESET;
+    }
+    /* Return the SPI_I2S_FLAG status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the SPIx CRC Error (CRCERR) flag.
+ * @param SPIx where x can be
+ *   - 1 or 2 in SPI mode
+ * @param SPI_I2S_FLAG specifies the SPI flag to clear.
+ *   This function clears only CRCERR flag.
+ * @note
+ *   - OVR (OverRun error) flag is cleared by software sequence: a read
+ *     operation to SPI_DAT register (SPI_I2S_ReceiveData()) followed by a read
+ *     operation to SPI_STS register (SPI_I2S_GetStatus()).
+ *   - UDR (UnderRun error) flag is cleared by a read operation to
+ *     SPI_STS register (SPI_I2S_GetStatus()).
+ *   - MODF (Mode Fault) flag is cleared by software sequence: a read/write
+ *     operation to SPI_STS register (SPI_I2S_GetStatus()) followed by a
+ *     write operation to SPI_CTRL1 register (SPI_Enable() to enable the SPI).
+ */
+void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_SPI_I2S_CLR_FLAG(SPI_I2S_FLAG));
+
+    /* Clear the selected SPI CRC Error (CRCERR) flag */
+    SPIx->STS = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+ * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
+ * @param SPIx where x can be
+ *   - 1 or 2 in SPI mode
+ *   - 1 or 2 in I2S mode
+ * @param SPI_I2S_IT specifies the SPI/I2S interrupt source to check.
+ *   This parameter can be one of the following values:
+ *     @arg SPI_I2S_INT_TE Transmit buffer empty interrupt.
+ *     @arg SPI_I2S_INT_RNE Receive buffer not empty interrupt.
+ *     @arg SPI_I2S_INT_OVER Overrun interrupt.
+ *     @arg SPI_INT_MODERR Mode Fault interrupt.
+ *     @arg SPI_INT_CRCERR CRC Error interrupt.
+ *     @arg I2S_INT_UNDER Underrun Error interrupt.
+ * @return The new state of SPI_I2S_IT (SET or RESET).
+ */
+INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT)
+{
+    INTStatus bitstatus = RESET;
+    uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_SPI_I2S_GET_INT(SPI_I2S_IT));
+
+    /* Get the SPI/I2S IT index */
+    itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+    /* Get the SPI/I2S IT mask */
+    itmask = SPI_I2S_IT >> 4;
+
+    /* Set the IT mask */
+    itmask = 0x01 << itmask;
+
+    /* Get the SPI_I2S_IT enable bit status */
+    enablestatus = (SPIx->CTRL2 & itmask);
+
+    /* Check the status of the specified SPI/I2S interrupt */
+    if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus)
+    {
+        /* SPI_I2S_IT is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* SPI_I2S_IT is reset */
+        bitstatus = RESET;
+    }
+    /* Return the SPI_I2S_IT status */
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ * @param SPIx where x can be
+ *   - 1 or 2 in SPI mode
+ * @param SPI_I2S_IT specifies the SPI interrupt pending bit to clear.
+ *   This function clears only CRCERR interrupt pending bit.
+ * @note
+ *   - OVR (OverRun Error) interrupt pending bit is cleared by software
+ *     sequence: a read operation to SPI_DAT register (SPI_I2S_ReceiveData())
+ *     followed by a read operation to SPI_STS register (SPI_I2S_GetIntStatus()).
+ *   - UDR (UnderRun Error) interrupt pending bit is cleared by a read
+ *     operation to SPI_STS register (SPI_I2S_GetIntStatus()).
+ *   - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+ *     a read/write operation to SPI_STS register (SPI_I2S_GetIntStatus())
+ *     followed by a write operation to SPI_CTRL1 register (SPI_Enable() to enable
+ *     the SPI).
+ */
+void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT)
+{
+    uint16_t itpos = 0;
+    /* Check the parameters */
+    assert_param(IS_SPI_PERIPH(SPIx));
+    assert_param(IS_SPI_I2S_CLR_INT(SPI_I2S_IT));
+
+    /* Get the SPI IT index */
+    itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+    /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+    SPIx->STS = (uint16_t)~itpos;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tim.c

@@ -0,0 +1,3290 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_tim.c
+ * @author Nations
+ * @version V1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_tim.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @brief TIM driver modules
+ * @{
+ */
+
+/** @addtogroup TIM_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Defines
+ * @{
+ */
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCTRL_ETR_MASK   ((uint16_t)0x00FF)
+#define CAPCMPMOD_OFFSET  ((uint16_t)0x0018)
+#define CAPCMPEN_CCE_SET  ((uint16_t)0x0001)
+#define CAPCMPEN_CCNE_SET ((uint16_t)0x0004)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ */
+void TIM_DeInit(TIM_Module* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+
+    if (TIMx == TIM1)
+    {
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, ENABLE);
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM1, DISABLE);
+    }
+    else if (TIMx == TIM2)
+    {
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, ENABLE);
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM2, DISABLE);
+    }
+    else if (TIMx == TIM3)
+    {
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, ENABLE);
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM3, DISABLE);
+    }
+    else if (TIMx == TIM4)
+    {
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, ENABLE);
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM4, DISABLE);
+    }
+    else if (TIMx == TIM5)
+    {
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, ENABLE);
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM5, DISABLE);
+    }
+    else if (TIMx == TIM6)
+    {
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, ENABLE);
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM6, DISABLE);
+    }
+    else if (TIMx == TIM7)
+    {
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, ENABLE);
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM7, DISABLE);
+    }
+    else if (TIMx == TIM8)
+    {
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, ENABLE);
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_TIM8, DISABLE);
+    }
+        else if (TIMx == TIM9)
+    {
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, ENABLE);
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_TIM9, DISABLE);
+    }
+}
+
+/**
+ * @brief  Initializes the TIMx Time Base Unit peripheral according to
+ *         the specified parameters in the TIM_TimeBaseInitStruct.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType
+ *         structure that contains the configuration information for the
+ *         specified TIM peripheral.
+ */
+void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct)
+{
+    uint32_t tmpcr1 = 0;
+
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IsTimCntMode(TIM_TimeBaseInitStruct->CntMode));
+    assert_param(IsTimClkDiv(TIM_TimeBaseInitStruct->ClkDiv));
+
+    tmpcr1 = TIMx->CTRL1;
+
+    if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+    {
+        /* Select the Counter Mode */
+        tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)));
+        tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->CntMode;
+    }
+
+    if ((TIMx != TIM6) && (TIMx != TIM7))
+    {
+        /* Set the clock division */
+        tmpcr1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CLKD));
+        tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->ClkDiv;
+    }
+
+    TIMx->CTRL1 = tmpcr1;
+
+    /* Set the Autoreload value */
+    TIMx->AR = TIM_TimeBaseInitStruct->Period;
+
+    /* Set the Prescaler value */
+    TIMx->PSC = TIM_TimeBaseInitStruct->Prescaler;
+
+    if ((TIMx == TIM1) || (TIMx == TIM8))
+    {
+        /* Set the Repetition Counter value */
+        TIMx->REPCNT = TIM_TimeBaseInitStruct->RepetCnt;
+    }
+
+    /* Generate an update event to reload the Prescaler and the Repetition counter
+       values immediately */
+    TIMx->EVTGEN = TIM_PSC_RELOAD_MODE_IMMEDIATE;
+
+    /*channel input from comp or iom*/
+    tmpcr1 = TIMx->CTRL1;
+    if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+    {
+        if (TIM_TimeBaseInitStruct->CapCh1FromCompEn)
+            tmpcr1 |= (0x01L << 11);
+        else
+            tmpcr1 &= ~(0x01L << 11);
+    }
+        if (TIMx==TIM9)
+        {
+                if (TIM_TimeBaseInitStruct->CapCh2FromCompEn)
+            tmpcr1 |= (0x01L << 12);
+        else
+            tmpcr1 &= ~(0x01L << 12);
+        if (TIM_TimeBaseInitStruct->CapCh3FromCompEn)
+            tmpcr1 |= (0x01L << 13);
+        else
+            tmpcr1 &= ~(0x01L << 13);
+                if (TIM_TimeBaseInitStruct->CapCh4FromCompEn)
+            tmpcr1 |= (0x01L << 14);
+        else
+            tmpcr1 &= ~(0x01L << 14);
+        }
+    /*etr input from comp or iom*/
+    if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM9))
+    {
+        if (TIM_TimeBaseInitStruct->CapEtrClrFromCompEn)
+            tmpcr1 |= (0x01L << 15);
+        else
+            tmpcr1 &= ~(0x01L << 15);
+    }
+    TIMx->CTRL1 = tmpcr1;
+    /*sel etr from iom or tsc*/
+    tmpcr1 = TIMx->CTRL2;
+    if ((TIMx == TIM2) || (TIMx == TIM4))
+    {
+        if (TIM_TimeBaseInitStruct->CapEtrSelFromTscEn)
+            tmpcr1 |= (0x01L << 8);
+        else
+            tmpcr1 &= ~(0x01L << 8);
+    }
+    TIMx->CTRL2 = tmpcr1;
+}
+
+/**
+ * @brief  Initializes the TIMx Channel1 according to the specified
+ *         parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be  1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ *         that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0;
+    uint32_t tmpccer = 0, tmpcr2 = 0;
+
+    /* Check the parameters */
+    assert_param(IsTimList8Module(TIMx));
+    assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+    assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+    assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+    /* Disable the Channel 1: Reset the CC1E Bit */
+    TIMx->CCEN &= (uint32_t)(~(uint32_t)TIM_CCEN_CC1EN);
+    /* Get the TIMx CCEN register value */
+    tmpccer = TIMx->CCEN;
+    /* Get the TIMx CTRL2 register value */
+    tmpcr2 = TIMx->CTRL2;
+
+    /* Get the TIMx CCMOD1 register value */
+    tmpccmrx = TIMx->CCMOD1;
+
+    /* Reset the Output Compare Mode Bits */
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC1M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC1SEL));
+
+    /* Select the Output Compare Mode */
+    tmpccmrx |= TIM_OCInitStruct->OcMode;
+
+    /* Reset the Output Polarity level */
+    tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1P));
+    /* Set the Output Compare Polarity */
+    tmpccer |= TIM_OCInitStruct->OcPolarity;
+
+    /* Set the Output State */
+    tmpccer |= TIM_OCInitStruct->OutputState;
+
+    if ((TIMx == TIM1) || (TIMx == TIM8))
+    {
+        assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+        assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+        assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+        assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+        /* Reset the Output N Polarity level */
+        tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NP));
+        /* Set the Output N Polarity */
+        tmpccer |= TIM_OCInitStruct->OcNPolarity;
+
+        /* Reset the Output N State */
+        tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NEN));
+        /* Set the Output N State */
+        tmpccer |= TIM_OCInitStruct->OutputNState;
+
+        /* Reset the Output Compare and Output Compare N IDLE State */
+        tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1));
+        tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI1N));
+
+        /* Set the Output Idle state */
+        tmpcr2 |= TIM_OCInitStruct->OcIdleState;
+        /* Set the Output N Idle state */
+        tmpcr2 |= TIM_OCInitStruct->OcNIdleState;
+    }
+    /* Write to TIMx CTRL2 */
+    TIMx->CTRL2 = tmpcr2;
+
+    /* Write to TIMx CCMOD1 */
+    TIMx->CCMOD1 = tmpccmrx;
+
+    /* Set the Capture Compare Register value */
+    TIMx->CCDAT1 = TIM_OCInitStruct->Pulse;
+
+    /* Write to TIMx CCEN */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Initializes the TIMx Channel2 according to the specified
+ *         parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be  1, 2, 3, 4, 5, 8 to select
+ *         the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ *         that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0;
+    uint32_t tmpccer = 0, tmpcr2 = 0;
+
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+    assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+    assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+    /* Disable the Channel 2: Reset the CC2E Bit */
+    TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2EN));
+
+    /* Get the TIMx CCEN register value */
+    tmpccer = TIMx->CCEN;
+    /* Get the TIMx CTRL2 register value */
+    tmpcr2 = TIMx->CTRL2;
+
+    /* Get the TIMx CCMOD1 register value */
+    tmpccmrx = TIMx->CCMOD1;
+
+    /* Reset the Output Compare mode and Capture/Compare selection Bits */
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_OC2M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL));
+
+    /* Select the Output Compare Mode */
+    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+    /* Reset the Output Polarity level */
+    tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2P));
+    /* Set the Output Compare Polarity */
+    tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 4);
+
+    /* Set the Output State */
+    tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 4);
+
+    if ((TIMx == TIM1) || (TIMx == TIM8))
+    {
+        assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+        assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+        assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+        assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+        /* Reset the Output N Polarity level */
+        tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2NP));
+        /* Set the Output N Polarity */
+        tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 4);
+
+        /* Reset the Output N State */
+        tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC2NEN));
+        /* Set the Output N State */
+        tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 4);
+
+        /* Reset the Output Compare and Output Compare N IDLE State */
+        tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2));
+        tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI2N));
+
+        /* Set the Output Idle state */
+        tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 2);
+        /* Set the Output N Idle state */
+        tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 2);
+    }
+    /* Write to TIMx CTRL2 */
+    TIMx->CTRL2 = tmpcr2;
+
+    /* Write to TIMx CCMOD1 */
+    TIMx->CCMOD1 = tmpccmrx;
+
+    /* Set the Capture Compare Register value */
+    TIMx->CCDAT2 = TIM_OCInitStruct->Pulse;
+
+    /* Write to TIMx CCEN */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Initializes the TIMx Channel3 according to the specified
+ *         parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ *         that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0;
+    uint32_t tmpccer = 0, tmpcr2 = 0;
+
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+    assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+    assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+    /* Disable the Channel 2: Reset the CC2E Bit */
+    TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3EN));
+
+    /* Get the TIMx CCEN register value */
+    tmpccer = TIMx->CCEN;
+    /* Get the TIMx CTRL2 register value */
+    tmpcr2 = TIMx->CTRL2;
+
+    /* Get the TIMx CCMOD2 register value */
+    tmpccmrx = TIMx->CCMOD2;
+
+    /* Reset the Output Compare mode and Capture/Compare selection Bits */
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC3MD));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC3SEL));
+    /* Select the Output Compare Mode */
+    tmpccmrx |= TIM_OCInitStruct->OcMode;
+
+    /* Reset the Output Polarity level */
+    tmpccer &= (uint32_t)(~((uint16_t)TIM_CCEN_CC3P));
+    /* Set the Output Compare Polarity */
+    tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 8);
+
+    /* Set the Output State */
+    tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 8);
+
+    if ((TIMx == TIM1) || (TIMx == TIM8))
+    {
+        assert_param(IsTimOutputNState(TIM_OCInitStruct->OutputNState));
+        assert_param(IsTimOcnPolarity(TIM_OCInitStruct->OcNPolarity));
+        assert_param(IsTimOcnIdleState(TIM_OCInitStruct->OcNIdleState));
+        assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+
+        /* Reset the Output N Polarity level */
+        tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NP));
+        /* Set the Output N Polarity */
+        tmpccer |= (uint32_t)(TIM_OCInitStruct->OcNPolarity << 8);
+        /* Reset the Output N State */
+        tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NEN));
+
+        /* Set the Output N State */
+        tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputNState << 8);
+        /* Reset the Output Compare and Output Compare N IDLE State */
+        tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3));
+        tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI3N));
+        /* Set the Output Idle state */
+        tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 4);
+        /* Set the Output N Idle state */
+        tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 4);
+    }
+    /* Write to TIMx CTRL2 */
+    TIMx->CTRL2 = tmpcr2;
+
+    /* Write to TIMx CCMOD2 */
+    TIMx->CCMOD2 = tmpccmrx;
+
+    /* Set the Capture Compare Register value */
+    TIMx->CCDAT3 = TIM_OCInitStruct->Pulse;
+
+    /* Write to TIMx CCEN */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Initializes the TIMx Channel4 according to the specified
+ *         parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ *         that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0;
+    uint32_t tmpccer = 0, tmpcr2 = 0;
+
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+    assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+    assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+    /* Disable the Channel 2: Reset the CC4E Bit */
+    TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4EN));
+
+    /* Get the TIMx CCEN register value */
+    tmpccer = TIMx->CCEN;
+    /* Get the TIMx CTRL2 register value */
+    tmpcr2 = TIMx->CTRL2;
+
+    /* Get the TIMx CCMOD2 register value */
+    tmpccmrx = TIMx->CCMOD2;
+
+    /* Reset the Output Compare mode and Capture/Compare selection Bits */
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_OC4MD));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD2_CC4SEL));
+
+    /* Select the Output Compare Mode */
+    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+    /* Reset the Output Polarity level */
+    tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4P));
+    /* Set the Output Compare Polarity */
+    tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 12);
+
+    /* Set the Output State */
+    tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 12);
+
+    if ((TIMx == TIM1) || (TIMx == TIM8))
+    {
+        assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+        /* Reset the Output Compare IDLE State */
+        tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI4));
+        /* Set the Output Idle state */
+        tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 6);
+    }
+    /* Write to TIMx CTRL2 */
+    TIMx->CTRL2 = tmpcr2;
+
+    /* Write to TIMx CCMOD2 */
+    TIMx->CCMOD2 = tmpccmrx;
+
+    /* Set the Capture Compare Register value */
+    TIMx->CCDAT4 = TIM_OCInitStruct->Pulse;
+
+    /* Write to TIMx CCEN */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Initializes the TIMx Channel5 according to the specified
+ *         parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be  1 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ *         that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0;
+    uint32_t tmpccer = 0, tmpcr2 = 0;
+
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+    assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+    assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+    /* Disable the Channel 5: Reset the CC5E Bit */
+    TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5EN));
+
+    /* Get the TIMx CCEN register value */
+    tmpccer = TIMx->CCEN;
+    /* Get the TIMx CTRL2 register value */
+    tmpcr2 = TIMx->CTRL2;
+
+    /* Get the TIMx CCMOD3 register value */
+    tmpccmrx = TIMx->CCMOD3;
+
+    /* Reset the Output Compare mode and Capture/Compare selection Bits */
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC5MD));
+
+    /* Select the Output Compare Mode */
+    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode);
+
+    /* Reset the Output Polarity level */
+    tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5P));
+    /* Set the Output Compare Polarity */
+    tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 16);
+
+    /* Set the Output State */
+    tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 16);
+
+    if ((TIMx == TIM1) || (TIMx == TIM8))
+    {
+        assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+        /* Reset the Output Compare IDLE State */
+        tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI5));
+        /* Set the Output Idle state */
+        tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 8);
+    }
+    /* Write to TIMx CTRL2 */
+    TIMx->CTRL2 = tmpcr2;
+
+    /* Write to TIMx CCMOD3 */
+    TIMx->CCMOD3 = tmpccmrx;
+
+    /* Set the Capture Compare Register value */
+    TIMx->CCDAT5 = TIM_OCInitStruct->Pulse;
+
+    /* Write to TIMx CCEN */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Initializes the TIMx Channel6 according to the specified
+ *         parameters in the TIM_OCInitStruct.
+ * @param TIMx where x can be  1 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure
+ *         that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0;
+    uint32_t tmpccer = 0, tmpcr2 = 0;
+
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimOcMode(TIM_OCInitStruct->OcMode));
+    assert_param(IsTimOutputState(TIM_OCInitStruct->OutputState));
+    assert_param(IsTimOcPolarity(TIM_OCInitStruct->OcPolarity));
+    /* Disable the Channel 6: Reset the CC6E Bit */
+    TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6EN));
+
+    /* Get the TIMx CCEN register value */
+    tmpccer = TIMx->CCEN;
+    /* Get the TIMx CTRL2 register value */
+    tmpcr2 = TIMx->CTRL2;
+
+    /* Get the TIMx CCMOD3 register value */
+    tmpccmrx = TIMx->CCMOD3;
+
+    /* Reset the Output Compare mode and Capture/Compare selection Bits */
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMOD3_OC6MD));
+
+    /* Select the Output Compare Mode */
+    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->OcMode << 8);
+
+    /* Reset the Output Polarity level */
+    tmpccer &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6P));
+    /* Set the Output Compare Polarity */
+    tmpccer |= (uint32_t)(TIM_OCInitStruct->OcPolarity << 20);
+
+    /* Set the Output State */
+    tmpccer |= (uint32_t)(TIM_OCInitStruct->OutputState << 20);
+
+    if ((TIMx == TIM1) || (TIMx == TIM8))
+    {
+        assert_param(IsTimOcIdleState(TIM_OCInitStruct->OcIdleState));
+        /* Reset the Output Compare IDLE State */
+        tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_OI6));
+        /* Set the Output Idle state */
+        tmpcr2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 10);
+    }
+    /* Write to TIMx CTRL2 */
+    TIMx->CTRL2 = tmpcr2;
+
+    /* Write to TIMx CCMOD3 */
+    TIMx->CCMOD3 = tmpccmrx;
+
+    /* Set the Capture Compare Register value */
+    TIMx->CCDAT6 = TIM_OCInitStruct->Pulse;
+
+    /* Write to TIMx CCEN */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Initializes the TIM peripheral according to the specified
+ *         parameters in the TIM_ICInitStruct.
+ * @param TIMx where x can be  1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure
+ *         that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct)
+{
+    /* Check the parameters */
+    assert_param(IsTimCh(TIM_ICInitStruct->Channel));
+    assert_param(IsTimIcSelection(TIM_ICInitStruct->IcSelection));
+    assert_param(IsTimIcPrescaler(TIM_ICInitStruct->IcPrescaler));
+    assert_param(IsTimInCapFilter(TIM_ICInitStruct->IcFilter));
+
+    if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+    {
+        assert_param(IsTimIcPalaritySingleEdge(TIM_ICInitStruct->IcPolarity));
+    }
+    else
+    {
+        assert_param(IsTimIcPolarityAnyEdge(TIM_ICInitStruct->IcPolarity));
+    }
+    if (TIM_ICInitStruct->Channel == TIM_CH_1)
+    {
+        assert_param(IsTimList8Module(TIMx));
+        /* TI1 Configuration */
+        ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+    }
+    else if (TIM_ICInitStruct->Channel == TIM_CH_2)
+    {
+        assert_param(IsTimList6Module(TIMx));
+        /* TI2 Configuration */
+        ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+    }
+    else if (TIM_ICInitStruct->Channel == TIM_CH_3)
+    {
+        assert_param(IsTimList3Module(TIMx));
+        /* TI3 Configuration */
+        ConfigTI3(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetInCap3Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+    }
+    else
+    {
+        assert_param(IsTimList3Module(TIMx));
+        /* TI4 Configuration */
+        ConfigTI4(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetInCap4Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+    }
+}
+
+/**
+ * @brief  Configures the TIM peripheral according to the specified
+ *         parameters in the TIM_ICInitStruct to measure an external PWM signal.
+ * @param TIMx where x can be  1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure
+ *         that contains the configuration information for the specified TIM peripheral.
+ */
+void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct)
+{
+    uint16_t icoppositepolarity  = TIM_IC_POLARITY_RISING;
+    uint16_t icoppositeselection = TIM_IC_SELECTION_DIRECTTI;
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    /* Select the Opposite Input Polarity */
+    if (TIM_ICInitStruct->IcPolarity == TIM_IC_POLARITY_RISING)
+    {
+        icoppositepolarity = TIM_IC_POLARITY_FALLING;
+    }
+    else
+    {
+        icoppositepolarity = TIM_IC_POLARITY_RISING;
+    }
+    /* Select the Opposite Input */
+    if (TIM_ICInitStruct->IcSelection == TIM_IC_SELECTION_DIRECTTI)
+    {
+        icoppositeselection = TIM_IC_SELECTION_INDIRECTTI;
+    }
+    else
+    {
+        icoppositeselection = TIM_IC_SELECTION_DIRECTTI;
+    }
+    if (TIM_ICInitStruct->Channel == TIM_CH_1)
+    {
+        /* TI1 Configuration */
+        ConfigTI1(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+        /* TI2 Configuration */
+        ConfigTI2(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+    }
+    else
+    {
+        /* TI2 Configuration */
+        ConfigTI2(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+        /* TI1 Configuration */
+        ConfigTI1(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->IcFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->IcPrescaler);
+    }
+}
+
+/**
+ * @brief  Configures the: Break feature, dead time, Lock level, the OSSI,
+ *         the OSSR State and the AOE(automatic output enable).
+ * @param TIMx where x can be  1 or 8 to select the TIM
+ * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure that
+ *         contains the BKDT Register configuration  information for the TIM peripheral.
+ */
+void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct)
+{
+    uint32_t tmp;
+    /* Check the parameters */
+    assert_param(IsTimList2Module(TIMx));
+    assert_param(IsTimOssrState(TIM_BDTRInitStruct->OssrState));
+    assert_param(IsTimOssiState(TIM_BDTRInitStruct->OssiState));
+    assert_param(IsTimLockLevel(TIM_BDTRInitStruct->LockLevel));
+    assert_param(IsTimBreakInState(TIM_BDTRInitStruct->Break));
+    assert_param(IsTimBreakPalarity(TIM_BDTRInitStruct->BreakPolarity));
+    assert_param(IsTimAutoOutputState(TIM_BDTRInitStruct->AutomaticOutput));
+    /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+       the OSSI State, the dead time value and the Automatic Output Enable Bit */
+    TIMx->BKDT = (uint32_t)TIM_BDTRInitStruct->OssrState | TIM_BDTRInitStruct->OssiState | TIM_BDTRInitStruct->LockLevel
+                 | TIM_BDTRInitStruct->DeadTime | TIM_BDTRInitStruct->Break | TIM_BDTRInitStruct->BreakPolarity
+                 | TIM_BDTRInitStruct->AutomaticOutput;
+
+    /*cofigure other break in*/
+    tmp = TIMx->CTRL1;
+    /*IOMBKPEN 0 meaning iom as break enable*/
+    if (TIM_BDTRInitStruct->IomBreakEn)
+        tmp &= ~(0x01L << 10);
+    else
+        tmp |= (0x01L << 10);
+    if (TIM_BDTRInitStruct->LockUpBreakEn)
+        tmp |= (0x01L << 16);
+    else
+        tmp &= ~(0x01L << 16);
+    if (TIM_BDTRInitStruct->PvdBreakEn)
+        tmp |= (0x01L << 17);
+    else
+        tmp &= ~(0x01L << 17);
+    TIMx->CTRL1 = tmp;
+}
+
+/**
+ * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
+ * @param TIM_TimeBaseInitStruct pointer to a TIM_TimeBaseInitType
+ *         structure which will be initialized.
+ */
+void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct)
+{
+    /* Set the default configuration */
+    TIM_TimeBaseInitStruct->Period    = 0xFFFF;
+    TIM_TimeBaseInitStruct->Prescaler = 0x0000;
+    TIM_TimeBaseInitStruct->ClkDiv    = TIM_CLK_DIV1;
+    TIM_TimeBaseInitStruct->CntMode   = TIM_CNT_MODE_UP;
+    TIM_TimeBaseInitStruct->RepetCnt  = 0x0000;
+
+    TIM_TimeBaseInitStruct->CapCh1FromCompEn    = false;
+    TIM_TimeBaseInitStruct->CapCh2FromCompEn    = false;
+    TIM_TimeBaseInitStruct->CapCh3FromCompEn    = false;
+    TIM_TimeBaseInitStruct->CapCh4FromCompEn    = false;
+    TIM_TimeBaseInitStruct->CapEtrClrFromCompEn = false;
+    TIM_TimeBaseInitStruct->CapEtrSelFromTscEn  = false;
+}
+
+/**
+ * @brief  Fills each TIM_OCInitStruct member with its default value.
+ * @param TIM_OCInitStruct pointer to a OCInitType structure which will
+ *         be initialized.
+ */
+void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct)
+{
+    /* Set the default configuration */
+    TIM_OCInitStruct->OcMode       = TIM_OCMODE_TIMING;
+    TIM_OCInitStruct->OutputState  = TIM_OUTPUT_STATE_DISABLE;
+    TIM_OCInitStruct->OutputNState = TIM_OUTPUT_NSTATE_DISABLE;
+    TIM_OCInitStruct->Pulse        = 0x0000;
+    TIM_OCInitStruct->OcPolarity   = TIM_OC_POLARITY_HIGH;
+    TIM_OCInitStruct->OcNPolarity  = TIM_OC_POLARITY_HIGH;
+    TIM_OCInitStruct->OcIdleState  = TIM_OC_IDLE_STATE_RESET;
+    TIM_OCInitStruct->OcNIdleState = TIM_OCN_IDLE_STATE_RESET;
+}
+
+/**
+ * @brief  Fills each TIM_ICInitStruct member with its default value.
+ * @param TIM_ICInitStruct pointer to a TIM_ICInitType structure which will
+ *         be initialized.
+ */
+void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct)
+{
+    /* Set the default configuration */
+    TIM_ICInitStruct->Channel     = TIM_CH_1;
+    TIM_ICInitStruct->IcPolarity  = TIM_IC_POLARITY_RISING;
+    TIM_ICInitStruct->IcSelection = TIM_IC_SELECTION_DIRECTTI;
+    TIM_ICInitStruct->IcPrescaler = TIM_IC_PSC_DIV1;
+    TIM_ICInitStruct->IcFilter    = 0x00;
+}
+
+/**
+ * @brief  Fills each TIM_BDTRInitStruct member with its default value.
+ * @param TIM_BDTRInitStruct pointer to a TIM_BDTRInitType structure which
+ *         will be initialized.
+ */
+void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct)
+{
+    /* Set the default configuration */
+    TIM_BDTRInitStruct->OssrState       = TIM_OSSR_STATE_DISABLE;
+    TIM_BDTRInitStruct->OssiState       = TIM_OSSI_STATE_DISABLE;
+    TIM_BDTRInitStruct->LockLevel       = TIM_LOCK_LEVEL_OFF;
+    TIM_BDTRInitStruct->DeadTime        = 0x00;
+    TIM_BDTRInitStruct->Break           = TIM_BREAK_IN_DISABLE;
+    TIM_BDTRInitStruct->BreakPolarity   = TIM_BREAK_POLARITY_LOW;
+    TIM_BDTRInitStruct->AutomaticOutput = TIM_AUTO_OUTPUT_DISABLE;
+}
+
+/**
+ * @brief  Enables or disables the specified TIM peripheral.
+ * @param TIMx where x can be 1 to 8 to select the TIMx peripheral.
+ * @param Cmd new state of the TIMx peripheral.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the TIM Counter */
+        TIMx->CTRL1 |= TIM_CTRL1_CNTEN;
+    }
+    else
+    {
+        /* Disable the TIM Counter */
+        TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_CNTEN));
+    }
+}
+
+/**
+ * @brief  Enables or disables the TIM peripheral Main Outputs.
+ * @param TIMx where x can be 1, 8 to select the TIMx peripheral.
+ * @param Cmd new state of the TIM peripheral Main Outputs.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsTimList2Module(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the TIM Main Output */
+        TIMx->BKDT |= TIM_BKDT_MOEN;
+    }
+    else
+    {
+        /* Disable the TIM Main Output */
+        TIMx->BKDT &= (uint16_t)(~((uint16_t)TIM_BKDT_MOEN));
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified TIM interrupts.
+ * @param TIMx where x can be 1 to 8 to select the TIMx peripheral.
+ * @param TIM_IT specifies the TIM interrupts sources to be enabled or disabled.
+ *   This parameter can be any combination of the following values:
+ *     @arg TIM_INT_UPDATE TIM update Interrupt source
+ *     @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ *     @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ *     @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ *     @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ *     @arg TIM_INT_COM TIM Commutation Interrupt source
+ *     @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ *     @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ *   - TIM6 and TIM7 can only generate an update interrupt.
+ *   - TIM_INT_BREAK is used only with TIM1, TIM8.
+ *   - TIM_INT_COM is used only with TIM1, TIM8.
+ * @param Cmd new state of the TIM interrupts.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_ConfigInt(TIM_Module* TIMx, uint16_t TIM_IT, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IsTimInt(TIM_IT));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the Interrupt sources */
+        TIMx->DINTEN |= TIM_IT;
+    }
+    else
+    {
+        /* Disable the Interrupt sources */
+        TIMx->DINTEN &= (uint16_t)~TIM_IT;
+    }
+}
+
+/**
+ * @brief  Configures the TIMx event to be generate by software.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_EventSource specifies the event source.
+ *   This parameter can be one or more of the following values:
+ *     @arg TIM_EVT_SRC_UPDATE Timer update Event source
+ *     @arg TIM_EVT_SRC_CC1 Timer Capture Compare 1 Event source
+ *     @arg TIM_EVT_SRC_CC2 Timer Capture Compare 2 Event source
+ *     @arg TIM_EVT_SRC_CC3 Timer Capture Compare 3 Event source
+ *     @arg TIM_EVT_SRC_CC4 Timer Capture Compare 4 Event source
+ *     @arg TIM_EVT_SRC_COM Timer COM event source
+ *     @arg TIM_EVT_SRC_TRIG Timer Trigger Event source
+ *     @arg TIM_EVT_SRC_BREAK Timer Break event source
+ * @note
+ *   - TIM6 and TIM7 can only generate an update event.
+ *   - TIM_EVT_SRC_COM and TIM_EVT_SRC_BREAK are used only with TIM1 and TIM8.
+ */
+void TIM_GenerateEvent(TIM_Module* TIMx, uint16_t TIM_EventSource)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IsTimEvtSrc(TIM_EventSource));
+
+    /* Set the event sources */
+    TIMx->EVTGEN = TIM_EventSource;
+}
+
+/**
+ * @brief  Configures the TIMx's DMA interface.
+ * @param TIMx where x can be  1, 2, 3, 4, 5, 8 to select
+ *   the TIM peripheral.
+ * @param TIM_DMABase DMA Base address.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_DMABase_CR, TIM_DMABASE_CTRL2, TIM_DMABASE_SMCTRL,
+ *          TIM_DMABASE_DMAINTEN, TIM1_DMABase_SR, TIM_DMABASE_EVTGEN,
+ *          TIM_DMABASE_CAPCMPMOD1, TIM_DMABASE_CAPCMPMOD2, TIM_DMABASE_CAPCMPEN,
+ *          TIM_DMABASE_CNT, TIM_DMABASE_PSC, TIM_DMABASE_AR,
+ *          TIM_DMABASE_REPCNT, TIM_DMABASE_CAPCMPDAT1, TIM_DMABASE_CAPCMPDAT2,
+ *          TIM_DMABASE_CAPCMPDAT3, TIM_DMABASE_CAPCMPDAT4, TIM_DMABASE_BKDT,
+ *          TIM_DMABASE_DMACTRL.
+ * @param TIM_DMABurstLength DMA Burst length.
+ *   This parameter can be one value between:
+ *   TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_18TRANSFERS.
+ */
+void TIM_ConfigDma(TIM_Module* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+    /* Check the parameters */
+    assert_param(IsTimList4Module(TIMx));
+    assert_param(IsTimDmaBase(TIM_DMABase));
+    assert_param(IsTimDmaLength(TIM_DMABurstLength));
+    /* Set the DMA Base and the DMA Burst Length */
+    TIMx->DCTRL = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+ * @brief  Enables or disables the TIMx's DMA Requests.
+ * @param TIMx where x can be  1, 2, 3, 4, 5, 6, 7, 8
+ *   to select the TIM peripheral.
+ * @param TIM_DMASource specifies the DMA Request sources.
+ *   This parameter can be any combination of the following values:
+ *     @arg TIM_DMA_UPDATE TIM update Interrupt source
+ *     @arg TIM_DMA_CC1 TIM Capture Compare 1 DMA source
+ *     @arg TIM_DMA_CC2 TIM Capture Compare 2 DMA source
+ *     @arg TIM_DMA_CC3 TIM Capture Compare 3 DMA source
+ *     @arg TIM_DMA_CC4 TIM Capture Compare 4 DMA source
+ *     @arg TIM_DMA_COM TIM Commutation DMA source
+ *     @arg TIM_DMA_TRIG TIM Trigger DMA source
+ * @param Cmd new state of the DMA Request sources.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableDma(TIM_Module* TIMx, uint16_t TIM_DMASource, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsTimList9Module(TIMx));
+    assert_param(IsTimDmaSrc(TIM_DMASource));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the DMA sources */
+        TIMx->DINTEN |= TIM_DMASource;
+    }
+    else
+    {
+        /* Disable the DMA sources */
+        TIMx->DINTEN &= (uint16_t)~TIM_DMASource;
+    }
+}
+
+/**
+ * @brief  Configures the TIMx internal Clock
+ * @param TIMx where x can be  1, 2, 3, 4, 5, 8
+ *         to select the TIM peripheral.
+ */
+void TIM_ConfigInternalClk(TIM_Module* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    /* Disable slave mode to clock the prescaler directly with the internal clock */
+    TIMx->SMCTRL &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+}
+
+/**
+ * @brief  Configures the TIMx Internal Trigger as External Clock
+ * @param TIMx where x can be  1, 2, 3, 4, 5 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource Trigger source.
+ *   This parameter can be one of the following values:
+ *   @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0
+ *   @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1
+ *   @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2
+ *   @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3
+ */
+void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource)
+{
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    assert_param(IsTimInterTrigSel(TIM_InputTriggerSource));
+    /* Select the Internal Trigger */
+    TIM_SelectInputTrig(TIMx, TIM_InputTriggerSource);
+    /* Select the External clock mode1 */
+    TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1;
+}
+
+/**
+ * @brief  Configures the TIMx Trigger as External Clock
+ * @param TIMx where x can be  1, 2, 3, 4, 5 to select the TIM peripheral.
+ * @param TIM_TIxExternalCLKSource Trigger source.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_EXT_CLK_SRC_TI1ED TI1 Edge Detector
+ *     @arg TIM_EXT_CLK_SRC_TI1 Filtered Timer Input 1
+ *     @arg TIM_EXT_CLK_SRC_TI2 Filtered Timer Input 2
+ * @param IcPolarity specifies the TIx Polarity.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_POLARITY_RISING
+ *     @arg TIM_IC_POLARITY_FALLING
+ * @param ICFilter specifies the filter value.
+ *   This parameter must be a value between 0x0 and 0xF.
+ */
+void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t IcPolarity, uint16_t ICFilter)
+{
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    assert_param(IsTimExtClkSrc(TIM_TIxExternalCLKSource));
+    assert_param(IsTimIcPalaritySingleEdge(IcPolarity));
+    assert_param(IsTimInCapFilter(ICFilter));
+    /* Configure the Timer Input Clock Source */
+    if (TIM_TIxExternalCLKSource == TIM_EXT_CLK_SRC_TI2)
+    {
+        ConfigTI2(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter);
+    }
+    else
+    {
+        ConfigTI1(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter);
+    }
+    /* Select the Trigger source */
+    TIM_SelectInputTrig(TIMx, TIM_TIxExternalCLKSource);
+    /* Select the External clock mode1 */
+    TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1;
+}
+
+/**
+ * @brief  Configures the External clock Mode1
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ *     @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ *     @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ *     @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ *     @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ *   This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtClkMode1(TIM_Module* TIMx,
+                           uint16_t TIM_ExtTRGPrescaler,
+                           uint16_t TIM_ExtTRGPolarity,
+                           uint16_t ExtTRGFilter)
+{
+    uint16_t tmpsmcr = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+    assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+    assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+    /* Configure the ETR Clock source */
+    TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+    /* Get the TIMx SMCTRL register value */
+    tmpsmcr = TIMx->SMCTRL;
+    /* Reset the SMS Bits */
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+    /* Select the External clock mode1 */
+    tmpsmcr |= TIM_SLAVE_MODE_EXT1;
+    /* Select the Trigger selection : ETRF */
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL));
+    tmpsmcr |= TIM_TRIG_SEL_ETRF;
+    /* Write to TIMx SMCTRL */
+    TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief  Configures the External clock Mode2
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ *     @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ *     @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ *     @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ *     @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ *   This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtClkMode2(TIM_Module* TIMx,
+                           uint16_t TIM_ExtTRGPrescaler,
+                           uint16_t TIM_ExtTRGPolarity,
+                           uint16_t ExtTRGFilter)
+{
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+    assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+    assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+    /* Configure the ETR Clock source */
+    TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+    /* Enable the External clock mode2 */
+    TIMx->SMCTRL |= TIM_SMCTRL_EXCEN;
+}
+
+/**
+ * @brief  Configures the TIMx External Trigger (ETR).
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF.
+ *     @arg TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2.
+ *     @arg TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4.
+ *     @arg TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active.
+ *     @arg TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ *   This parameter must be a value between 0x00 and 0x0F
+ */
+void TIM_ConfigExtTrig(TIM_Module* TIMx,
+                       uint16_t TIM_ExtTRGPrescaler,
+                       uint16_t TIM_ExtTRGPolarity,
+                       uint16_t ExtTRGFilter)
+{
+    uint16_t tmpsmcr = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimExtPreDiv(TIM_ExtTRGPrescaler));
+    assert_param(IsTimExtTrigPolarity(TIM_ExtTRGPolarity));
+    assert_param(IsTimExtTrigFilter(ExtTRGFilter));
+    tmpsmcr = TIMx->SMCTRL;
+    /* Reset the ETR Bits */
+    tmpsmcr &= SMCTRL_ETR_MASK;
+    /* Set the Prescaler, the Filter value and the Polarity */
+    tmpsmcr |=
+        (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+    /* Write to TIMx SMCTRL */
+    TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief  Configures the TIMx Prescaler.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Prescaler specifies the Prescaler Register value
+ * @param TIM_PSCReloadMode specifies the TIM Prescaler Reload mode
+ *   This parameter can be one of the following values:
+ *     @arg TIM_PSC_RELOAD_MODE_UPDATE The Prescaler is loaded at the update event.
+ *     @arg TIM_PSC_RELOAD_MODE_IMMEDIATE The Prescaler is loaded immediately.
+ */
+void TIM_ConfigPrescaler(TIM_Module* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IsTimPscReloadMode(TIM_PSCReloadMode));
+    /* Set the Prescaler value */
+    TIMx->PSC = Prescaler;
+    /* Set or reset the UG Bit */
+    TIMx->EVTGEN = TIM_PSCReloadMode;
+}
+
+/**
+ * @brief  Specifies the TIMx Counter Mode to be used.
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param CntMode specifies the Counter Mode to be used
+ *   This parameter can be one of the following values:
+ *     @arg TIM_CNT_MODE_UP TIM Up Counting Mode
+ *     @arg TIM_CNT_MODE_DOWN TIM Down Counting Mode
+ *     @arg TIM_CNT_MODE_CENTER_ALIGN1 TIM Center Aligned Mode1
+ *     @arg TIM_CNT_MODE_CENTER_ALIGN2 TIM Center Aligned Mode2
+ *     @arg TIM_CNT_MODE_CENTER_ALIGN3 TIM Center Aligned Mode3
+ */
+void TIM_ConfigCntMode(TIM_Module* TIMx, uint16_t CntMode)
+{
+    uint32_t tmpcr1 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimCntMode(CntMode));
+    tmpcr1 = TIMx->CTRL1;
+    /* Reset the CMS and DIR Bits */
+    tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)));
+    /* Set the Counter Mode */
+    tmpcr1 |= CntMode;
+    /* Write to TIMx CTRL1 register */
+    TIMx->CTRL1 = tmpcr1;
+}
+
+/**
+ * @brief  Selects the Input Trigger source
+ * @param TIMx where x can be  1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource The Input Trigger source.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_TRIG_SEL_IN_TR0 Internal Trigger 0
+ *     @arg TIM_TRIG_SEL_IN_TR1 Internal Trigger 1
+ *     @arg TIM_TRIG_SEL_IN_TR2 Internal Trigger 2
+ *     @arg TIM_TRIG_SEL_IN_TR3 Internal Trigger 3
+ *     @arg TIM_TRIG_SEL_TI1F_ED TI1 Edge Detector
+ *     @arg TIM_TRIG_SEL_TI1FP1 Filtered Timer Input 1
+ *     @arg TIM_TRIG_SEL_TI2FP2 Filtered Timer Input 2
+ *     @arg TIM_TRIG_SEL_ETRF External Trigger input
+ */
+void TIM_SelectInputTrig(TIM_Module* TIMx, uint16_t TIM_InputTriggerSource)
+{
+    uint16_t tmpsmcr = 0;
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    assert_param(IsTimTrigSel(TIM_InputTriggerSource));
+    /* Get the TIMx SMCTRL register value */
+    tmpsmcr = TIMx->SMCTRL;
+    /* Reset the TS Bits */
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_TSEL));
+    /* Set the Input Trigger source */
+    tmpsmcr |= TIM_InputTriggerSource;
+    /* Write to TIMx SMCTRL */
+    TIMx->SMCTRL = tmpsmcr;
+}
+
+/**
+ * @brief  Configures the TIMx Encoder Interface.
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_EncoderMode specifies the TIMx Encoder Mode.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_ENCODE_MODE_TI1 Counter counts on TI1FP1 edge depending on TI2FP2 level.
+ *     @arg TIM_ENCODE_MODE_TI2 Counter counts on TI2FP2 edge depending on TI1FP1 level.
+ *     @arg TIM_ENCODE_MODE_TI12 Counter counts on both TI1FP1 and TI2FP2 edges depending
+ *                                on the level of the other input.
+ * @param TIM_IC1Polarity specifies the IC1 Polarity
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_POLARITY_FALLING IC Falling edge.
+ *     @arg TIM_IC_POLARITY_RISING IC Rising edge.
+ * @param TIM_IC2Polarity specifies the IC2 Polarity
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_POLARITY_FALLING IC Falling edge.
+ *     @arg TIM_IC_POLARITY_RISING IC Rising edge.
+ */
+void TIM_ConfigEncoderInterface(TIM_Module* TIMx,
+                                uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity,
+                                uint16_t TIM_IC2Polarity)
+{
+    uint16_t tmpsmcr  = 0;
+    uint16_t tmpccmr1 = 0;
+    uint32_t tmpccer  = 0;
+
+    /* Check the parameters */
+    assert_param(IsTimList5Module(TIMx));
+    assert_param(IsTimEncodeMode(TIM_EncoderMode));
+    assert_param(IsTimIcPalaritySingleEdge(TIM_IC1Polarity));
+    assert_param(IsTimIcPalaritySingleEdge(TIM_IC2Polarity));
+
+    /* Get the TIMx SMCTRL register value */
+    tmpsmcr = TIMx->SMCTRL;
+
+    /* Get the TIMx CCMOD1 register value */
+    tmpccmr1 = TIMx->CCMOD1;
+
+    /* Get the TIMx CCEN register value */
+    tmpccer = TIMx->CCEN;
+
+    /* Set the encoder Mode */
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCTRL_SMSEL));
+    tmpsmcr |= TIM_EncoderMode;
+
+    /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & (uint16_t)(~((uint16_t)TIM_CCMOD1_CC2SEL)));
+    tmpccmr1 |= TIM_CCMOD1_CC1SEL_0 | TIM_CCMOD1_CC2SEL_0;
+
+    /* Set the TI1 and the TI2 Polarities */
+    tmpccer &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCEN_CC1P)) & ((uint32_t) ~((uint32_t)TIM_CCEN_CC2P)));
+    tmpccer |= (uint32_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+    /* Write to TIMx SMCTRL */
+    TIMx->SMCTRL = tmpsmcr;
+    /* Write to TIMx CCMOD1 */
+    TIMx->CCMOD1 = tmpccmr1;
+    /* Write to TIMx CCEN */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Forces the TIMx output 1 waveform to active or inactive level.
+ * @param TIMx where x can be  1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC1REF
+ *     @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC1REF.
+ */
+void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList8Module(TIMx));
+    assert_param(IsTimForceActive(TIM_ForcedAction));
+    tmpccmr1 = TIMx->CCMOD1;
+    /* Reset the OC1M Bits */
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1M);
+    /* Configure The Forced output Mode */
+    tmpccmr1 |= TIM_ForcedAction;
+    /* Write to TIMx CCMOD1 register */
+    TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief  Forces the TIMx output 2 waveform to active or inactive level.
+ * @param TIMx where x can be  1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC2REF
+ *     @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC2REF.
+ */
+void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    assert_param(IsTimForceActive(TIM_ForcedAction));
+    tmpccmr1 = TIMx->CCMOD1;
+    /* Reset the OC2M Bits */
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2M);
+    /* Configure The Forced output Mode */
+    tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+    /* Write to TIMx CCMOD1 register */
+    TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief  Forces the TIMx output 3 waveform to active or inactive level.
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC3REF
+ *     @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC3REF.
+ */
+void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimForceActive(TIM_ForcedAction));
+    tmpccmr2 = TIMx->CCMOD2;
+    /* Reset the OC1M Bits */
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3MD);
+    /* Configure The Forced output Mode */
+    tmpccmr2 |= TIM_ForcedAction;
+    /* Write to TIMx CCMOD2 register */
+    TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief  Forces the TIMx output 4 waveform to active or inactive level.
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC4REF
+ *     @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC4REF.
+ */
+void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimForceActive(TIM_ForcedAction));
+    tmpccmr2 = TIMx->CCMOD2;
+    /* Reset the OC2M Bits */
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4MD);
+    /* Configure The Forced output Mode */
+    tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+    /* Write to TIMx CCMOD2 register */
+    TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief  Forces the TIMx output 5 waveform to active or inactive level.
+ * @param TIMx where x can be  1 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC5REF
+ *     @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC5REF.
+ */
+void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr3 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimForceActive(TIM_ForcedAction));
+    tmpccmr3 = TIMx->CCMOD3;
+    /* Reset the OC2M Bits */
+    tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5MD);
+    /* Configure The Forced output Mode */
+    tmpccmr3 |= (uint16_t)(TIM_ForcedAction);
+    /* Write to TIMx CCMOD2 register */
+    TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief  Forces the TIMx output 6 waveform to active or inactive level.
+ * @param TIMx where x can be  1 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction specifies the forced Action to be set to the output waveform.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_FORCED_ACTION_ACTIVE Force active level on OC6REF
+ *     @arg TIM_FORCED_ACTION_INACTIVE Force inactive level on OC6REF.
+ */
+void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr3 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimForceActive(TIM_ForcedAction));
+    tmpccmr3 = TIMx->CCMOD3;
+    /* Reset the OC2M Bits */
+    tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6MD);
+    /* Configure The Forced output Mode */
+    tmpccmr3 |= (uint16_t)(TIM_ForcedAction << 8);
+    /* Write to TIMx CCMOD2 register */
+    TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief  Enables or disables TIMx peripheral Preload register on AR.
+ * @param TIMx where x can be  1 to 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx peripheral Preload register
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Set the AR Preload Bit */
+        TIMx->CTRL1 |= TIM_CTRL1_ARPEN;
+    }
+    else
+    {
+        /* Reset the AR Preload Bit */
+        TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ARPEN);
+    }
+}
+
+/**
+ * @brief  Selects the TIM peripheral Commutation event.
+ * @param TIMx where x can be  1, 8 to select the TIMx peripheral
+ * @param Cmd new state of the Commutation event.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsTimList2Module(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Set the COM Bit */
+        TIMx->CTRL2 |= TIM_CTRL2_CCUSEL;
+    }
+    else
+    {
+        /* Reset the COM Bit */
+        TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCUSEL);
+    }
+}
+
+/**
+ * @brief  Selects the TIMx peripheral Capture Compare DMA source.
+ * @param TIMx where x can be  1, 2, 3, 4, 5, 8 to select
+ *         the TIM peripheral.
+ * @param Cmd new state of the Capture Compare DMA source
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsTimList4Module(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Set the CCDS Bit */
+        TIMx->CTRL2 |= TIM_CTRL2_CCDSEL;
+    }
+    else
+    {
+        /* Reset the CCDS Bit */
+        TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCDSEL);
+    }
+}
+
+/**
+ * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ * @param TIMx where x can be   1, 2, 3, 4, 5, 8
+ *         to select the TIMx peripheral
+ * @param Cmd new state of the Capture Compare Preload Control bit
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsTimList5Module(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Set the CCPC Bit */
+        TIMx->CTRL2 |= TIM_CTRL2_CCPCTL;
+    }
+    else
+    {
+        /* Reset the CCPC Bit */
+        TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_CCPCTL);
+    }
+}
+
+/**
+ * @brief  Enables or disables the TIMx peripheral Preload register on CCDAT1.
+ * @param TIMx where x can be  1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_PRE_LOAD_ENABLE
+ *     @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList8Module(TIMx));
+    assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+    tmpccmr1 = TIMx->CCMOD1;
+    /* Reset the OC1PE Bit */
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1PEN);
+    /* Enable or Disable the Output Compare Preload feature */
+    tmpccmr1 |= TIM_OCPreload;
+    /* Write to TIMx CCMOD1 register */
+    TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief  Enables or disables the TIMx peripheral Preload register on CCDAT2.
+ * @param TIMx where x can be  1, 2, 3, 4, 5, 8 to select
+ *         the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_PRE_LOAD_ENABLE
+ *     @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+    tmpccmr1 = TIMx->CCMOD1;
+    /* Reset the OC2PE Bit */
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2PEN);
+    /* Enable or Disable the Output Compare Preload feature */
+    tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+    /* Write to TIMx CCMOD1 register */
+    TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief  Enables or disables the TIMx peripheral Preload register on CCDAT3.
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_PRE_LOAD_ENABLE
+ *     @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+    tmpccmr2 = TIMx->CCMOD2;
+    /* Reset the OC3PE Bit */
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3PEN);
+    /* Enable or Disable the Output Compare Preload feature */
+    tmpccmr2 |= TIM_OCPreload;
+    /* Write to TIMx CCMOD2 register */
+    TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief  Enables or disables the TIMx peripheral Preload register on CCDAT4.
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_PRE_LOAD_ENABLE
+ *     @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+    tmpccmr2 = TIMx->CCMOD2;
+    /* Reset the OC4PE Bit */
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4PEN);
+    /* Enable or Disable the Output Compare Preload feature */
+    tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+    /* Write to TIMx CCMOD2 register */
+    TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief  Enables or disables the TIMx peripheral Preload register on CCDAT5.
+ * @param TIMx where x can be  1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_PRE_LOAD_ENABLE
+ *     @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr3 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+    tmpccmr3 = TIMx->CCMOD3;
+    /* Reset the OC5PE Bit */
+    tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5PEN);
+    /* Enable or Disable the Output Compare Preload feature */
+    tmpccmr3 |= (uint16_t)(TIM_OCPreload);
+    /* Write to TIMx CCMOD3 register */
+    TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief  Enables or disables the TIMx peripheral Preload register on CCDAT6.
+ * @param TIMx where x can be  1 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload new state of the TIMx peripheral Preload register
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_PRE_LOAD_ENABLE
+ *     @arg TIM_OC_PRE_LOAD_DISABLE
+ */
+void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr3 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimOcPreLoadState(TIM_OCPreload));
+    tmpccmr3 = TIMx->CCMOD3;
+    /* Reset the OC6PE Bit */
+    tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6PEN);
+    /* Enable or Disable the Output Compare Preload feature */
+    tmpccmr3 |= (uint16_t)(TIM_OCPreload << 8);
+    /* Write to TIMx CCMOD3 register */
+    TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief  Configures the TIMx Output Compare 1 Fast feature.
+ * @param TIMx where x can be  1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ *     @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList8Module(TIMx));
+    assert_param(IsTimOcFastState(TIM_OCFast));
+    /* Get the TIMx CCMOD1 register value */
+    tmpccmr1 = TIMx->CCMOD1;
+    /* Reset the OC1FE Bit */
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1FEN);
+    /* Enable or Disable the Output Compare Fast Bit */
+    tmpccmr1 |= TIM_OCFast;
+    /* Write to TIMx CCMOD1 */
+    TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief  Configures the TIMx Output Compare 2 Fast feature.
+ * @param TIMx where x can be  1, 2, 3, 4, 5, 8 to select
+ *         the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ *     @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    assert_param(IsTimOcFastState(TIM_OCFast));
+    /* Get the TIMx CCMOD1 register value */
+    tmpccmr1 = TIMx->CCMOD1;
+    /* Reset the OC2FE Bit */
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2FEN);
+    /* Enable or Disable the Output Compare Fast Bit */
+    tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+    /* Write to TIMx CCMOD1 */
+    TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief  Configures the TIMx Output Compare 3 Fast feature.
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ *     @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimOcFastState(TIM_OCFast));
+    /* Get the TIMx CCMOD2 register value */
+    tmpccmr2 = TIMx->CCMOD2;
+    /* Reset the OC3FE Bit */
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3FEN);
+    /* Enable or Disable the Output Compare Fast Bit */
+    tmpccmr2 |= TIM_OCFast;
+    /* Write to TIMx CCMOD2 */
+    TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief  Configures the TIMx Output Compare 4 Fast feature.
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ *     @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimOcFastState(TIM_OCFast));
+    /* Get the TIMx CCMOD2 register value */
+    tmpccmr2 = TIMx->CCMOD2;
+    /* Reset the OC4FE Bit */
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4FEN);
+    /* Enable or Disable the Output Compare Fast Bit */
+    tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+    /* Write to TIMx CCMOD2 */
+    TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief  Configures the TIMx Output Compare 5 Fast feature.
+ * @param TIMx where x can be  1 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ *     @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr3 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimOcFastState(TIM_OCFast));
+    /* Get the TIMx CCMOD2 register value */
+    tmpccmr3 = TIMx->CCMOD3;
+    /* Reset the OC4FE Bit */
+    tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5FEN);
+    /* Enable or Disable the Output Compare Fast Bit */
+    tmpccmr3 |= (uint16_t)(TIM_OCFast);
+    /* Write to TIMx CCMOD3 */
+    TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief  Configures the TIMx Output Compare 6 Fast feature.
+ * @param TIMx where x can be  1 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast new state of the Output Compare Fast Enable Bit.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_FAST_ENABLE TIM output compare fast enable
+ *     @arg TIM_OC_FAST_DISABLE TIM output compare fast disable
+ */
+void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr3 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimOcFastState(TIM_OCFast));
+    /* Get the TIMx CCMOD2 register value */
+    tmpccmr3 = TIMx->CCMOD3;
+    /* Reset the OC4FE Bit */
+    tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6FEN);
+    /* Enable or Disable the Output Compare Fast Bit */
+    tmpccmr3 |= (uint16_t)(TIM_OCFast << 8);
+    /* Write to TIMx CCMOD3 */
+    TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief  Clears or safeguards the OCREF1 signal on an external event
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ *     @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc1Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimOcClrState(TIM_OCClear));
+
+    tmpccmr1 = TIMx->CCMOD1;
+
+    /* Reset the OC1CE Bit */
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC1CEN);
+    /* Enable or Disable the Output Compare Clear Bit */
+    tmpccmr1 |= TIM_OCClear;
+    /* Write to TIMx CCMOD1 register */
+    TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief  Clears or safeguards the OCREF2 signal on an external event
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ *     @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc2Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimOcClrState(TIM_OCClear));
+    tmpccmr1 = TIMx->CCMOD1;
+    /* Reset the OC2CE Bit */
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2CEN);
+    /* Enable or Disable the Output Compare Clear Bit */
+    tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+    /* Write to TIMx CCMOD1 register */
+    TIMx->CCMOD1 = tmpccmr1;
+}
+
+/**
+ * @brief  Clears or safeguards the OCREF3 signal on an external event
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ *     @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc3Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimOcClrState(TIM_OCClear));
+    tmpccmr2 = TIMx->CCMOD2;
+    /* Reset the OC3CE Bit */
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3CEN);
+    /* Enable or Disable the Output Compare Clear Bit */
+    tmpccmr2 |= TIM_OCClear;
+    /* Write to TIMx CCMOD2 register */
+    TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief  Clears or safeguards the OCREF4 signal on an external event
+ * @param TIMx where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ *     @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc4Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimOcClrState(TIM_OCClear));
+    tmpccmr2 = TIMx->CCMOD2;
+    /* Reset the OC4CE Bit */
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4CEN);
+    /* Enable or Disable the Output Compare Clear Bit */
+    tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+    /* Write to TIMx CCMOD2 register */
+    TIMx->CCMOD2 = tmpccmr2;
+}
+
+/**
+ * @brief  Clears or safeguards the OCREF5 signal on an external event
+ * @param TIMx where x can be  1 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ *     @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc5Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr3 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimOcClrState(TIM_OCClear));
+    tmpccmr3 = TIMx->CCMOD3;
+    /* Reset the OC4CE Bit */
+    tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5CEN);
+    /* Enable or Disable the Output Compare Clear Bit */
+    tmpccmr3 |= (uint16_t)(TIM_OCClear);
+    /* Write to TIMx CCMOD3 register */
+    TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief  Clears or safeguards the OCREF6 signal on an external event
+ * @param TIMx where x can be  1 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear new state of the Output Compare Clear Enable Bit.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_CLR_ENABLE TIM Output clear enable
+ *     @arg TIM_OC_CLR_DISABLE TIM Output clear disable
+ */
+void TIM_ClrOc6Ref(TIM_Module* TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr3 = 0;
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimOcClrState(TIM_OCClear));
+    tmpccmr3 = TIMx->CCMOD3;
+    /* Reset the OC4CE Bit */
+    tmpccmr3 &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC6CEN);
+    /* Enable or Disable the Output Compare Clear Bit */
+    tmpccmr3 |= (uint16_t)(TIM_OCClear << 8);
+    /* Write to TIMx CCMOD3 register */
+    TIMx->CCMOD3 = tmpccmr3;
+}
+
+/**
+ * @brief  Configures the TIMx channel 1 polarity.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC1 Polarity
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ *     @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+    uint32_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IsTimList8Module(TIMx));
+    assert_param(IsTimOcPolarity(OcPolarity));
+    tmpccer = TIMx->CCEN;
+    /* Set or Reset the CC1P Bit */
+    tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1P);
+    tmpccer |= OcPolarity;
+    /* Write to TIMx CCEN register */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Configures the TIMx Channel 1N polarity.
+ * @param TIMx where x can be 1, 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC1N Polarity
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ *     @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+    uint32_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IsTimList2Module(TIMx));
+    assert_param(IsTimOcnPolarity(OcNPolarity));
+
+    tmpccer = TIMx->CCEN;
+    /* Set or Reset the CC1NP Bit */
+    tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1NP);
+    tmpccer |= OcNPolarity;
+    /* Write to TIMx CCEN register */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Configures the TIMx channel 2 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC2 Polarity
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ *     @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+    uint32_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    assert_param(IsTimOcPolarity(OcPolarity));
+    tmpccer = TIMx->CCEN;
+    /* Set or Reset the CC2P Bit */
+    tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2P);
+    tmpccer |= (uint32_t)(OcPolarity << 4);
+    /* Write to TIMx CCEN register */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Configures the TIMx Channel 2N polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC2N Polarity
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ *     @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+    uint32_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimOcnPolarity(OcNPolarity));
+
+    tmpccer = TIMx->CCEN;
+    /* Set or Reset the CC2NP Bit */
+    tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2NP);
+    tmpccer |= (uint32_t)(OcNPolarity << 4);
+    /* Write to TIMx CCEN register */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Configures the TIMx channel 3 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC3 Polarity
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ *     @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+    uint32_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimOcPolarity(OcPolarity));
+    tmpccer = TIMx->CCEN;
+    /* Set or Reset the CC3P Bit */
+    tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3P);
+    tmpccer |= (uint32_t)(OcPolarity << 8);
+    /* Write to TIMx CCEN register */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Configures the TIMx Channel 3N polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcNPolarity specifies the OC3N Polarity
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OCN_POLARITY_HIGH Output Compare active high
+ *     @arg TIM_OCN_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint16_t OcNPolarity)
+{
+    uint32_t tmpccer = 0;
+
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimOcnPolarity(OcNPolarity));
+
+    tmpccer = TIMx->CCEN;
+    /* Set or Reset the CC3NP Bit */
+    tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3NP);
+    tmpccer |= (uint32_t)(OcNPolarity << 8);
+    /* Write to TIMx CCEN register */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Configures the TIMx channel 4 polarity.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC4 Polarity
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ *     @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+    uint32_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimOcPolarity(OcPolarity));
+    tmpccer = TIMx->CCEN;
+    /* Set or Reset the CC4P Bit */
+    tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4P);
+    tmpccer |= (uint32_t)(OcPolarity << 12);
+    /* Write to TIMx CCEN register */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Configures the TIMx channel 5 polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC5 Polarity
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ *     @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+    uint32_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimOcPolarity(OcPolarity));
+    tmpccer = TIMx->CCEN;
+    /* Set or Reset the CC5P Bit */
+    tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC5P);
+    tmpccer |= (uint32_t)(OcPolarity << 16);
+    /* Write to TIMx CCEN register */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Configures the TIMx channel 6 polarity.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param OcPolarity specifies the OC6 Polarity
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OC_POLARITY_HIGH Output Compare active high
+ *     @arg TIM_OC_POLARITY_LOW Output Compare active low
+ */
+void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint16_t OcPolarity)
+{
+    uint32_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    assert_param(IsTimOcPolarity(OcPolarity));
+    tmpccer = TIMx->CCEN;
+    /* Set or Reset the CC6P Bit */
+    tmpccer &= (uint32_t) ~((uint32_t)TIM_CCEN_CC6P);
+    tmpccer |= (uint32_t)(OcPolarity << 20);
+    /* Write to TIMx CCEN register */
+    TIMx->CCEN = tmpccer;
+}
+
+/**
+ * @brief  Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ *   This parameter can be one of the following values:
+ *     @arg TIM_CH_1 TIM Channel 1
+ *     @arg TIM_CH_2 TIM Channel 2
+ *     @arg TIM_CH_3 TIM Channel 3
+ *     @arg TIM_CH_4 TIM Channel 4
+ * @param TIM_CCx specifies the TIM Channel CCxE bit new state.
+ *   This parameter can be: TIM_CAP_CMP_ENABLE or TIM_CAP_CMP_DISABLE.
+ */
+void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCx)
+{
+    uint16_t tmp = 0;
+
+    /* Check the parameters */
+    assert_param(IsTimList8Module(TIMx));
+    assert_param(IsTimCh(Channel));
+    assert_param(IsTimCapCmpState(TIM_CCx));
+
+    tmp = CAPCMPEN_CCE_SET << Channel;
+
+    /* Reset the CCxE Bit */
+    TIMx->CCEN &= (uint32_t)~tmp;
+
+    /* Set or reset the CCxE Bit */
+    TIMx->CCEN |= (uint32_t)(TIM_CCx << Channel);
+}
+
+/**
+ * @brief  Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx where x can be 1, 8 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ *   This parameter can be one of the following values:
+ *     @arg TIM_CH_1 TIM Channel 1
+ *     @arg TIM_CH_2 TIM Channel 2
+ *     @arg TIM_CH_3 TIM Channel 3
+ * @param TIM_CCxN specifies the TIM Channel CCxNE bit new state.
+ *   This parameter can be: TIM_CAP_CMP_N_ENABLE or TIM_CAP_CMP_N_DISABLE.
+ */
+void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint16_t Channel, uint32_t TIM_CCxN)
+{
+    uint16_t tmp = 0;
+
+    /* Check the parameters */
+    assert_param(IsTimList2Module(TIMx));
+    assert_param(IsTimComplementaryCh(Channel));
+    assert_param(IsTimCapCmpNState(TIM_CCxN));
+
+    tmp = CAPCMPEN_CCNE_SET << Channel;
+
+    /* Reset the CCxNE Bit */
+    TIMx->CCEN &= (uint32_t)~tmp;
+
+    /* Set or reset the CCxNE Bit */
+    TIMx->CCEN |= (uint32_t)(TIM_CCxN << Channel);
+}
+
+/**
+ * @brief  Selects the TIM Output Compare Mode.
+ * @note   This function disables the selected channel before changing the Output
+ *         Compare Mode.
+ *         User has to enable this channel using TIM_EnableCapCmpCh and TIM_EnableCapCmpChN functions.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ *   This parameter can be one of the following values:
+ *     @arg TIM_CH_1 TIM Channel 1
+ *     @arg TIM_CH_2 TIM Channel 2
+ *     @arg TIM_CH_3 TIM Channel 3
+ *     @arg TIM_CH_4 TIM Channel 4
+ * @param OcMode specifies the TIM Output Compare Mode.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OCMODE_TIMING
+ *     @arg TIM_OCMODE_ACTIVE
+ *     @arg TIM_OCMODE_TOGGLE
+ *     @arg TIM_OCMODE_PWM1
+ *     @arg TIM_OCMODE_PWM2
+ *     @arg TIM_FORCED_ACTION_ACTIVE
+ *     @arg TIM_FORCED_ACTION_INACTIVE
+ */
+void TIM_SelectOcMode(TIM_Module* TIMx, uint16_t Channel, uint16_t OcMode)
+{
+    uint32_t tmp  = 0;
+    uint16_t tmp1 = 0;
+
+    /* Check the parameters */
+    assert_param(IsTimList8Module(TIMx));
+    assert_param(IsTimCh(Channel));
+    assert_param(IsTimOc(OcMode));
+
+    tmp = (uint32_t)TIMx;
+    tmp += CAPCMPMOD_OFFSET;
+
+    tmp1 = CAPCMPEN_CCE_SET << (uint16_t)Channel;
+
+    /* Disable the Channel: Reset the CCxE Bit */
+    TIMx->CCEN &= (uint16_t)~tmp1;
+
+    if ((Channel == TIM_CH_1) || (Channel == TIM_CH_3))
+    {
+        tmp += (Channel >> 1);
+
+        /* Reset the OCxM bits in the CCMRx register */
+        *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC1M);
+
+        /* Configure the OCxM bits in the CCMRx register */
+        *(__IO uint32_t*)tmp |= OcMode;
+    }
+    else
+    {
+        tmp += (uint16_t)(Channel - (uint16_t)4) >> (uint16_t)1;
+
+        /* Reset the OCxM bits in the CCMRx register */
+        *(__IO uint32_t*)tmp &= (uint32_t) ~((uint32_t)TIM_CCMOD1_OC2M);
+
+        /* Configure the OCxM bits in the CCMRx register */
+        *(__IO uint32_t*)tmp |= (uint16_t)(OcMode << 8);
+    }
+}
+
+/**
+ * @brief  Enables or Disables the TIMx Update event.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx UDIS bit
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Set the Update Disable Bit */
+        TIMx->CTRL1 |= TIM_CTRL1_UPDIS;
+    }
+    else
+    {
+        /* Reset the Update Disable Bit */
+        TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPDIS);
+    }
+}
+
+/**
+  * @brief  Configures the TIMx Update Request Interrupt source.
+  * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+  * @param TIM_UpdateSource specifies the Update source.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_UPDATE_SRC_REGULAr Source of update is the counter overflow/underflow
+                                       or the setting of UG bit, or an update generation
+                                       through the slave mode controller.
+  *     @arg TIM_UPDATE_SRC_GLOBAL Source of update is counter overflow/underflow.
+  */
+void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint16_t TIM_UpdateSource)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IsTimUpdateSrc(TIM_UpdateSource));
+    if (TIM_UpdateSource != TIM_UPDATE_SRC_GLOBAL)
+    {
+        /* Set the URS Bit */
+        TIMx->CTRL1 |= TIM_CTRL1_UPRS;
+    }
+    else
+    {
+        /* Reset the URS Bit */
+        TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_UPRS);
+    }
+}
+
+/**
+ * @brief  Enables or disables the TIMx's Hall sensor interface.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Cmd new state of the TIMx Hall sensor interface.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Set the TI1S Bit */
+        TIMx->CTRL2 |= TIM_CTRL2_TI1SEL;
+    }
+    else
+    {
+        /* Reset the TI1S Bit */
+        TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_TI1SEL);
+    }
+}
+
+/**
+ * @brief  Selects the TIMx's One Pulse Mode.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_OPMode specifies the OPM Mode to be used.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_OPMODE_SINGLE
+ *     @arg TIM_OPMODE_REPET
+ */
+void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint16_t TIM_OPMode)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IsTimOpMOde(TIM_OPMode));
+    /* Reset the OPM Bit */
+    TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_ONEPM);
+    /* Configure the OPM Mode */
+    TIMx->CTRL1 |= TIM_OPMode;
+}
+
+/**
+ * @brief  Selects the TIMx Trigger Output Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 6, 7, 8 to select the TIM peripheral.
+ * @param TIM_TRGOSource specifies the Trigger Output source.
+ *   This paramter can be one of the following values:
+ *
+ *  - For all TIMx
+ *     @arg TIM_TRGO_SRC_RESET The UG bit in the TIM_EVTGEN register is used as the trigger output (TRGO).
+ *     @arg TIM_TRGO_SRC_ENABLE The Counter Enable CEN is used as the trigger output (TRGO).
+ *     @arg TIM_TRGO_SRC_UPDATE The update event is selected as the trigger output (TRGO).
+ *
+ *  - For all TIMx except TIM6 and TIM7
+ *     @arg TIM_TRGO_SRC_OC1 The trigger output sends a positive pulse when the CC1IF flag
+ *                              is to be set, as soon as a capture or compare match occurs (TRGO).
+ *     @arg TIM_TRGO_SRC_OC1REF OC1REF signal is used as the trigger output (TRGO).
+ *     @arg TIM_TRGO_SRC_OC2REF OC2REF signal is used as the trigger output (TRGO).
+ *     @arg TIM_TRGO_SRC_OC3REF OC3REF signal is used as the trigger output (TRGO).
+ *     @arg TIM_TRGO_SRC_OC4REF OC4REF signal is used as the trigger output (TRGO).
+ *
+ */
+void TIM_SelectOutputTrig(TIM_Module* TIMx, uint16_t TIM_TRGOSource)
+{
+    /* Check the parameters */
+    assert_param(IsTimList7Module(TIMx));
+    assert_param(IsTimTrgoSrc(TIM_TRGOSource));
+    /* Reset the MMS Bits */
+    TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CTRL2_MMSEL);
+    /* Select the TRGO source */
+    TIMx->CTRL2 |= TIM_TRGOSource;
+}
+
+/**
+ * @brief  Selects the TIMx Slave Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_SlaveMode specifies the Timer Slave Mode.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_SLAVE_MODE_RESET Rising edge of the selected trigger signal (TRGI) re-initializes
+ *                               the counter and triggers an update of the registers.
+ *     @arg TIM_SLAVE_MODE_GATED The counter clock is enabled when the trigger signal (TRGI) is high.
+ *     @arg TIM_SLAVE_MODE_TRIG The counter starts at a rising edge of the trigger TRGI.
+ *     @arg TIM_SLAVE_MODE_EXT1 Rising edges of the selected trigger (TRGI) clock the counter.
+ */
+void TIM_SelectSlaveMode(TIM_Module* TIMx, uint16_t TIM_SlaveMode)
+{
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    assert_param(IsTimSlaveMode(TIM_SlaveMode));
+    /* Reset the SMS Bits */
+    TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_SMSEL);
+    /* Select the Slave Mode */
+    TIMx->SMCTRL |= TIM_SlaveMode;
+}
+
+/**
+ * @brief  Sets or Resets the TIMx Master/Slave Mode.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_MasterSlaveMode specifies the Timer Master Slave Mode.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_MASTER_SLAVE_MODE_ENABLE synchronization between the current timer
+ *                                      and its slaves (through TRGO).
+ *     @arg TIM_MASTER_SLAVE_MODE_DISABLE No action
+ */
+void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    assert_param(IsTimMasterSlaveMode(TIM_MasterSlaveMode));
+    /* Reset the MSM Bit */
+    TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SMCTRL_MSMD);
+
+    /* Set or Reset the MSM Bit */
+    TIMx->SMCTRL |= TIM_MasterSlaveMode;
+}
+
+/**
+ * @brief  Sets the TIMx Counter Register value
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Counter specifies the Counter register new value.
+ */
+void TIM_SetCnt(TIM_Module* TIMx, uint16_t Counter)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    /* Set the Counter Register value */
+    TIMx->CNT = Counter;
+}
+
+/**
+ * @brief  Sets the TIMx Autoreload Register value
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param Autoreload specifies the Autoreload register new value.
+ */
+void TIM_SetAutoReload(TIM_Module* TIMx, uint16_t Autoreload)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    /* Set the Autoreload Register value */
+    TIMx->AR = Autoreload;
+}
+
+/**
+ * @brief  Sets the TIMx Capture Compare1 Register value
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param Compare1 specifies the Capture Compare1 register new value.
+ */
+void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1)
+{
+    /* Check the parameters */
+    assert_param(IsTimList8Module(TIMx));
+    /* Set the Capture Compare1 Register value */
+    TIMx->CCDAT1 = Compare1;
+}
+
+/**
+ * @brief  Sets the TIMx Capture Compare2 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param Compare2 specifies the Capture Compare2 register new value.
+ */
+void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2)
+{
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    /* Set the Capture Compare2 Register value */
+    TIMx->CCDAT2 = Compare2;
+}
+
+/**
+ * @brief  Sets the TIMx Capture Compare3 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare3 specifies the Capture Compare3 register new value.
+ */
+void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3)
+{
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    /* Set the Capture Compare3 Register value */
+    TIMx->CCDAT3 = Compare3;
+}
+
+/**
+ * @brief  Sets the TIMx Capture Compare4 Register value
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare4 specifies the Capture Compare4 register new value.
+ */
+void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4)
+{
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    /* Set the Capture Compare4 Register value */
+    TIMx->CCDAT4 = Compare4;
+}
+
+/**
+ * @brief  Sets the TIMx Capture Compare5 Register value
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param Compare5 specifies the Capture Compare5 register new value.
+ */
+void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5)
+{
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    /* Set the Capture Compare4 Register value */
+    TIMx->CCDAT5 = Compare5;
+}
+
+/**
+ * @brief  Sets the TIMx Capture Compare4 Register value
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @param Compare6 specifies the Capture Compare6 register new value.
+ */
+void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6)
+{
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    /* Set the Capture Compare4 Register value */
+    TIMx->CCDAT6 = Compare6;
+}
+
+/**
+ * @brief  Sets the TIMx Input Capture 1 prescaler.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture1 prescaler new value.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_PSC_DIV1 no prescaler
+ *     @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ *     @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ *     @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+    /* Check the parameters */
+    assert_param(IsTimList8Module(TIMx));
+    assert_param(IsTimIcPrescaler(TIM_ICPSC));
+    /* Reset the IC1PSC Bits */
+    TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC1PSC);
+    /* Set the IC1PSC value */
+    TIMx->CCMOD1 |= TIM_ICPSC;
+}
+
+/**
+ * @brief  Sets the TIMx Input Capture 2 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture2 prescaler new value.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_PSC_DIV1 no prescaler
+ *     @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ *     @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ *     @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    assert_param(IsTimIcPrescaler(TIM_ICPSC));
+    /* Reset the IC2PSC Bits */
+    TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_CCMOD1_IC2PSC);
+    /* Set the IC2PSC value */
+    TIMx->CCMOD1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief  Sets the TIMx Input Capture 3 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture3 prescaler new value.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_PSC_DIV1 no prescaler
+ *     @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ *     @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ *     @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimIcPrescaler(TIM_ICPSC));
+    /* Reset the IC3PSC Bits */
+    TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC3PSC);
+    /* Set the IC3PSC value */
+    TIMx->CCMOD2 |= TIM_ICPSC;
+}
+
+/**
+ * @brief  Sets the TIMx Input Capture 4 prescaler.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC specifies the Input Capture4 prescaler new value.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_PSC_DIV1 no prescaler
+ *     @arg TIM_IC_PSC_DIV2 capture is done once every 2 events
+ *     @arg TIM_IC_PSC_DIV4 capture is done once every 4 events
+ *     @arg TIM_IC_PSC_DIV8 capture is done once every 8 events
+ */
+void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint16_t TIM_ICPSC)
+{
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    assert_param(IsTimIcPrescaler(TIM_ICPSC));
+    /* Reset the IC4PSC Bits */
+    TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_CCMOD2_IC4PSC);
+    /* Set the IC4PSC value */
+    TIMx->CCMOD2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief  Sets the TIMx Clock Division value.
+ * @param TIMx where x can be  1 to 8 except 6 and 7 to select
+ *   the TIM peripheral.
+ * @param TIM_CKD specifies the clock division value.
+ *   This parameter can be one of the following value:
+ *     @arg TIM_CLK_DIV1 TDTS = Tck_tim
+ *     @arg TIM_CLK_DIV2 TDTS = 2*Tck_tim
+ *     @arg TIM_CLK_DIV4 TDTS = 4*Tck_tim
+ */
+void TIM_SetClkDiv(TIM_Module* TIMx, uint16_t TIM_CKD)
+{
+    /* Check the parameters */
+    assert_param(IsTimList8Module(TIMx));
+    assert_param(IsTimClkDiv(TIM_CKD));
+    /* Reset the CKD Bits */
+    TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CTRL1_CLKD);
+    /* Set the CKD value */
+    TIMx->CTRL1 |= TIM_CKD;
+}
+
+/**
+ * @brief  Gets the TIMx Input Capture 1 value.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @return Capture Compare 1 Register value.
+ */
+uint16_t TIM_GetCap1(TIM_Module* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IsTimList8Module(TIMx));
+    /* Get the Capture 1 Register value */
+    return TIMx->CCDAT1;
+}
+
+/**
+ * @brief  Gets the TIMx Input Capture 2 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @return Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCap2(TIM_Module* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IsTimList6Module(TIMx));
+    /* Get the Capture 2 Register value */
+    return TIMx->CCDAT2;
+}
+
+/**
+ * @brief  Gets the TIMx Input Capture 3 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @return Capture Compare 3 Register value.
+ */
+uint16_t TIM_GetCap3(TIM_Module* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    /* Get the Capture 3 Register value */
+    return TIMx->CCDAT3;
+}
+
+/**
+ * @brief  Gets the TIMx Input Capture 4 value.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @return Capture Compare 4 Register value.
+ */
+uint16_t TIM_GetCap4(TIM_Module* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+    /* Get the Capture 4 Register value */
+    return TIMx->CCDAT4;
+}
+
+/**
+ * @brief  Gets the TIMx Input Capture 5 value.
+ * @param TIMx where x can be 1 8 to select the TIM peripheral.
+ * @return Capture Compare 5 Register value.
+ */
+uint16_t TIM_GetCap5(TIM_Module* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    /* Get the Capture 5 Register value */
+    return TIMx->CCDAT5;
+}
+
+/**
+ * @brief  Gets the TIMx Input Capture 6 value.
+ * @param TIMx where x can be 1 or 8 to select the TIM peripheral.
+ * @return Capture Compare 6 Register value.
+ */
+uint16_t TIM_GetCap6(TIM_Module* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IsTimList1Module(TIMx));
+    /* Get the Capture 6 Register value */
+    return TIMx->CCDAT6;
+}
+
+/**
+ * @brief  Gets the TIMx Counter value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Counter Register value.
+ */
+uint16_t TIM_GetCnt(TIM_Module* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    /* Get the Counter Register value */
+    return TIMx->CNT;
+}
+
+/**
+ * @brief  Gets the TIMx Prescaler value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_Module* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    /* Get the Prescaler Register value */
+    return TIMx->PSC;
+}
+
+/**
+ * @brief  Gets the TIMx Prescaler value.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @return Prescaler Register value.
+ */
+uint16_t TIM_GetAutoReload(TIM_Module* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    /* Get the Prescaler Register value */
+    return TIMx->AR;
+}
+
+/**
+ * @brief  Checks whether the specified TIM flag is set or not.
+ * @param TIMx where x can be 1 to 5 , 8 ,9 to select the TIM peripheral.
+ * @param TIM_CCEN specifies the Bit to check.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_CC1EN    CC1EN Bit
+ *     @arg TIM_CC1NEN   CC1NEN Bit
+ *     @arg TIM_CC2EN    CC2EN Bit
+ *     @arg TIM_CC2NEN   CC2NEN Bit
+ *     @arg TIM_CC3EN    CC3EN Bit
+ *     @arg TIM_CC3NEN   CC3NEN Bit
+ *     @arg TIM_CC4EN    CC4EN Bit
+ *     @arg TIM_CC5EN    CC5EN Bit
+ *     @arg TIM_CC6EN    CC6EN Bit
+ * @note
+ *   - TIM_CC1NEN TIM_CC2NEN TIM_CC3NEN is used only with TIM1, TIM8.
+ * @return The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN)
+{
+    INTStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IsTimList3Module(TIMx));
+
+    if (TIMx==TIM1 || TIMx==TIM8){
+        assert_param(IsAdvancedTimCCENFlag(TIM_CCEN));
+        if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }else if (TIMx==TIM2 || TIMx==TIM3 || TIMx==TIM4 || TIMx==TIM5 || TIMx==TIM9){
+        assert_param(IsGeneralTimCCENFlag(TIM_CCEN));
+        if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+
+    return bitstatus;
+}
+
+/**
+ * @brief  Checks whether the specified TIM flag is set or not.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG specifies the flag to check.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_FLAG_UPDATE TIM update Flag
+ *     @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag
+ *     @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag
+ *     @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag
+ *     @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag
+ *     @arg TIM_FLAG_COM TIM Commutation Flag
+ *     @arg TIM_FLAG_TRIG TIM Trigger Flag
+ *     @arg TIM_FLAG_BREAK TIM Break Flag
+ *     @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag
+ *     @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag
+ *     @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag
+ *     @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag
+ *     @arg TIM_FLAG_CC5 TIM Capture Compare 5 Flag
+ *     @arg TIM_FLAG_CC6 TIM Capture Compare 6 Flag
+ * @note
+ *   - TIM6 and TIM7 can have only one update flag.
+ *   - TIM_FLAG_BREAK is used only with TIM1, TIM8.
+ *   - TIM_FLAG_COM is used only with TIM1, TIM8.
+ * @return The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG)
+{
+    INTStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IsTimGetFlag(TIM_FLAG));
+
+    if ((TIMx->STS & TIM_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the TIMx's pending flags.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG specifies the flag bit to clear.
+ *   This parameter can be any combination of the following values:
+ *     @arg TIM_FLAG_UPDATE TIM update Flag
+ *     @arg TIM_FLAG_CC1 TIM Capture Compare 1 Flag
+ *     @arg TIM_FLAG_CC2 TIM Capture Compare 2 Flag
+ *     @arg TIM_FLAG_CC3 TIM Capture Compare 3 Flag
+ *     @arg TIM_FLAG_CC4 TIM Capture Compare 4 Flag
+ *     @arg TIM_FLAG_COM TIM Commutation Flag
+ *     @arg TIM_FLAG_TRIG TIM Trigger Flag
+ *     @arg TIM_FLAG_BREAK TIM Break Flag
+ *     @arg TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag
+ *     @arg TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag
+ *     @arg TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag
+ *     @arg TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag
+ * @note
+ *   - TIM6 and TIM7 can have only one update flag.
+ *   - TIM_FLAG_BREAK is used only with TIM1, TIM8.
+ *   - TIM_FLAG_COM is used only with TIM1, TIM8.
+ */
+void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IsTimClrFlag(TIM_FLAG));
+
+    /* Clear the flags */
+    TIMx->STS = (uint32_t)~TIM_FLAG;
+}
+
+/**
+ * @brief  Checks whether the TIM interrupt has occurred or not.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT specifies the TIM interrupt source to check.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_INT_UPDATE TIM update Interrupt source
+ *     @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ *     @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ *     @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ *     @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ *     @arg TIM_INT_COM TIM Commutation Interrupt source
+ *     @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ *     @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ *   - TIM6 and TIM7 can generate only an update interrupt.
+ *   - TIM_INT_BREAK is used only with TIM1, TIM8.
+ *   - TIM_INT_COM is used only with TIM1, TIM8.
+ * @return The new state of the TIM_IT(SET or RESET).
+ */
+INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT)
+{
+    INTStatus bitstatus = RESET;
+    uint32_t itstatus = 0x0, itenable = 0x0;
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IsTimGetInt(TIM_IT));
+
+    itstatus = TIMx->STS & TIM_IT;
+
+    itenable = TIMx->DINTEN & TIM_IT;
+    if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the TIMx's interrupt pending bits.
+ * @param TIMx where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT specifies the pending bit to clear.
+ *   This parameter can be any combination of the following values:
+ *     @arg TIM_INT_UPDATE TIM1 update Interrupt source
+ *     @arg TIM_INT_CC1 TIM Capture Compare 1 Interrupt source
+ *     @arg TIM_INT_CC2 TIM Capture Compare 2 Interrupt source
+ *     @arg TIM_INT_CC3 TIM Capture Compare 3 Interrupt source
+ *     @arg TIM_INT_CC4 TIM Capture Compare 4 Interrupt source
+ *     @arg TIM_INT_COM TIM Commutation Interrupt source
+ *     @arg TIM_INT_TRIG TIM Trigger Interrupt source
+ *     @arg TIM_INT_BREAK TIM Break Interrupt source
+ * @note
+ *   - TIM6 and TIM7 can generate only an update interrupt.
+ *   - TIM_INT_BREAK is used only with TIM1, TIM8.
+ *   - TIM_INT_COM is used only with TIM1, TIM8.
+ */
+void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT)
+{
+    /* Check the parameters */
+    assert_param(IsTimAllModule(TIMx));
+    assert_param(IsTimInt(TIM_IT));
+    /* Clear the IT pending Bit */
+    TIMx->STS = (uint32_t)~TIM_IT;
+}
+
+/**
+ * @brief  Configure the TI1 as Input.
+ * @param TIMx where x can be 1 to 8 except 6 and 7 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_POLARITY_RISING
+ *     @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_SELECTION_DIRECTTI TIM Input 1 is selected to be connected to IC1.
+ *     @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 1 is selected to be connected to IC2.
+ *     @arg TIM_IC_SELECTION_TRC TIM Input 1 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ *   This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI1(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+    uint16_t tmpccmr1 = 0;
+    uint32_t tmpccer  = 0;
+    /* Disable the Channel 1: Reset the CC1E Bit */
+    TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC1EN);
+    tmpccmr1 = TIMx->CCMOD1;
+    tmpccer  = TIMx->CCEN;
+    /* Select the Input and set the filter */
+    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC1SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC1F)));
+    tmpccmr1 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4));
+
+    if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+    {
+        /* Select the Polarity and set the CC1E Bit */
+        tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P));
+        tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN);
+    }
+    else
+    {
+        /* Select the Polarity and set the CC1E Bit */
+        tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC1P | TIM_CCEN_CC1NP));
+        tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC1EN);
+    }
+
+    /* Write to TIMx CCMOD1 and CCEN registers */
+    TIMx->CCMOD1 = tmpccmr1;
+    TIMx->CCEN   = tmpccer;
+}
+
+/**
+ * @brief  Configure the TI2 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5, 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_POLARITY_RISING
+ *     @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_SELECTION_DIRECTTI TIM Input 2 is selected to be connected to IC2.
+ *     @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 2 is selected to be connected to IC1.
+ *     @arg TIM_IC_SELECTION_TRC TIM Input 2 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ *   This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI2(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+    uint16_t tmpccmr1 = 0;
+    uint32_t tmpccer = 0, tmp = 0;
+    /* Disable the Channel 2: Reset the CC2E Bit */
+    TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC2EN);
+    tmpccmr1 = TIMx->CCMOD1;
+    tmpccer  = TIMx->CCEN;
+    tmp      = (uint32_t)(IcPolarity << 4);
+    /* Select the Input and set the filter */
+    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD1_CC2SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD1_IC2F)));
+    tmpccmr1 |= (uint16_t)(IcFilter << 12);
+    tmpccmr1 |= (uint16_t)(IcSelection << 8);
+
+    if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+    {
+        /* Select the Polarity and set the CC2E Bit */
+        tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P));
+        tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC2EN);
+    }
+    else
+    {
+        /* Select the Polarity and set the CC2E Bit */
+        tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC2P | TIM_CCEN_CC2NP));
+        tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC2EN);
+    }
+
+    /* Write to TIMx CCMOD1 and CCEN registers */
+    TIMx->CCMOD1 = tmpccmr1;
+    TIMx->CCEN   = tmpccer;
+}
+
+/**
+ * @brief  Configure the TI3 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_POLARITY_RISING
+ *     @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_SELECTION_DIRECTTI TIM Input 3 is selected to be connected to IC3.
+ *     @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 3 is selected to be connected to IC4.
+ *     @arg TIM_IC_SELECTION_TRC TIM Input 3 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ *   This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI3(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+    uint16_t tmpccmr2 = 0;
+    uint32_t tmpccer = 0, tmp = 0;
+    /* Disable the Channel 3: Reset the CC3E Bit */
+    TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC3EN);
+    tmpccmr2 = TIMx->CCMOD2;
+    tmpccer  = TIMx->CCEN;
+    tmp      = (uint32_t)(IcPolarity << 8);
+    /* Select the Input and set the filter */
+    tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CCMOD2_CC3SEL)) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC3F)));
+    tmpccmr2 |= (uint16_t)(IcSelection | (uint16_t)(IcFilter << (uint16_t)4));
+
+    if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+    {
+        /* Select the Polarity and set the CC3E Bit */
+        tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P));
+        tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC3EN);
+    }
+    else
+    {
+        /* Select the Polarity and set the CC3E Bit */
+        tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC3P | TIM_CCEN_CC3NP));
+        tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC3EN);
+    }
+
+    /* Write to TIMx CCMOD2 and CCEN registers */
+    TIMx->CCMOD2 = tmpccmr2;
+    TIMx->CCEN   = tmpccer;
+}
+
+/**
+ * @brief  Configure the TI4 as Input.
+ * @param TIMx where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param IcPolarity The Input Polarity.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_POLARITY_RISING
+ *     @arg TIM_IC_POLARITY_FALLING
+ * @param IcSelection specifies the input to be used.
+ *   This parameter can be one of the following values:
+ *     @arg TIM_IC_SELECTION_DIRECTTI TIM Input 4 is selected to be connected to IC4.
+ *     @arg TIM_IC_SELECTION_INDIRECTTI TIM Input 4 is selected to be connected to IC3.
+ *     @arg TIM_IC_SELECTION_TRC TIM Input 4 is selected to be connected to TRC.
+ * @param IcFilter Specifies the Input Capture Filter.
+ *   This parameter must be a value between 0x00 and 0x0F.
+ */
+static void ConfigTI4(TIM_Module* TIMx, uint16_t IcPolarity, uint16_t IcSelection, uint16_t IcFilter)
+{
+    uint16_t tmpccmr2 = 0;
+    uint32_t tmpccer = 0, tmp = 0;
+
+    /* Disable the Channel 4: Reset the CC4E Bit */
+    TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CCEN_CC4EN);
+    tmpccmr2 = TIMx->CCMOD2;
+    tmpccer  = TIMx->CCEN;
+    tmp      = (uint32_t)(IcPolarity << 12);
+    /* Select the Input and set the filter */
+    tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMOD2_CC4SEL) & ((uint16_t) ~((uint16_t)TIM_CCMOD2_IC4F)));
+    tmpccmr2 |= (uint16_t)(IcSelection << 8);
+    tmpccmr2 |= (uint16_t)(IcFilter << 12);
+
+    if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM9))
+    {
+        /* Select the Polarity and set the CC4E Bit */
+        tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P));
+        tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC4EN);
+    }
+    else
+    {
+        /* Select the Polarity and set the CC4E Bit */
+        tmpccer &= (uint32_t) ~((uint32_t)(TIM_CCEN_CC4P));
+        tmpccer |= (uint32_t)(IcPolarity | (uint32_t)TIM_CCEN_CC4EN);
+    }
+    /* Write to TIMx CCMOD2 and CCEN registers */
+    TIMx->CCMOD2 = tmpccmr2;
+    TIMx->CCEN   = tmpccer;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tsc.c

@@ -0,0 +1,279 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_tsc.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x.h"
+#include "n32g43x_tsc.h"
+
+/**
+* @brief  Init TSC config
+* @param  InitParam: TSC initialize structure
+* @return : TSC_ErrorTypeDef
+*/
+TSC_ErrorTypeDef TSC_Init(TSC_InitType* InitParam)
+{
+    uint32_t tempreg,timeout;
+
+    assert_param(IS_TSC_DET_MODE(InitParam->Mode));
+    assert_param(IS_TSC_PAD_OPTION(InitParam->PadOpt));
+    assert_param(IS_TSC_PAD_SPEED(InitParam->Speed));
+
+    /* waiting tsc hw for idle status.*/
+    timeout = 0;
+    do
+    {
+        __TSC_HW_DISABLE();
+
+        if (++timeout > TSC_TIMEOUT)
+            return TSC_ERROR_HW_MODE;
+    }while (__TSC_GET_HW_MODE());
+
+    /*TSC_CTRL config*/
+    tempreg = 0;
+    if (InitParam->Mode == TSC_HW_DETECT_MODE)
+    {
+        assert_param(IS_TSC_DET_PERIOD(InitParam->Period));
+        assert_param(IS_TSC_FILTER(InitParam->Filter));
+        assert_param(IS_TSC_DET_TYPE(InitParam->Type));
+        assert_param(IS_TSC_INT(InitParam->Int));
+
+        tempreg |= InitParam->Period;
+        tempreg |= InitParam->Filter;
+        tempreg |= InitParam->Type;
+        tempreg |= InitParam->Int;
+    }
+    else
+    {
+        assert_param(IS_TSC_OUT(InitParam->Out));
+        tempreg |= InitParam->Out;
+    }
+
+    TSC->CTRL = tempreg;
+
+    /*TSC_ANA_SEL config*/
+    TSC->ANA_SEL = InitParam->PadOpt | InitParam->Speed;
+
+    return TSC_ERROR_OK;
+}
+
+/**
+ * @brief  Config the clock source of TSC
+ * @param  TSC_ClkSource specifies the clock source of TSC
+ *   This parameter can be one of the following values:
+ *     @arg TSC_CLK_SRC_LSI:              TSC clock source is LSI(default)
+ *     @arg TSC_CLK_SRC_LSE:              TSC clock source is LSE,and LSE is oscillator
+ *     @arg TSC_CLK_SRC_LSE_BYPASS:       TSC clock source is LSE,and LSE is extennal clock
+ * @retval TSC error code
+ */
+TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource)
+{
+    uint32_t timeout;
+
+    /*Enable PWR  peripheral Clock*/
+    RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE);
+
+    if (TSC_CLK_SRC_LSI == TSC_ClkSource)
+    {
+        /*enable LSI clock*/
+        RCC_EnableLsi(ENABLE);
+
+        /*Wait LSI stable*/
+        timeout = 0;
+        while (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET)
+        {
+            if (++timeout >TSC_TIMEOUT)
+                return TSC_ERROR_CLOCK;
+        }
+    }
+    else if ((TSC_CLK_SRC_LSE_BYPASS==TSC_ClkSource)||(TSC_CLK_SRC_LSE==TSC_ClkSource))
+    {
+        if (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD)==RESET)
+        {
+            RCC_ConfigLse((TSC_ClkSource & (~RCC_LDCTRL_LSXSEL)),0x28);
+            timeout = 0;
+            while (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET)
+            {
+                if (++timeout >TSC_TIMEOUT)
+                    return TSC_ERROR_CLOCK;
+            }
+        }
+    }
+    else
+        return TSC_ERROR_PARAMETER;
+
+    // Set bit 8 of PWR_CTRL1.Open PWR DBP.
+    PWR_BackupAccessEnable(ENABLE); //PWR->CTRL1 |=  0x100;
+
+    /*set LSI as TSC clock source*/
+    RCC_ConfigLSXClk(TSC_ClkSource & RCC_LDCTRL_LSXSEL);
+
+    /*Enable TSC clk*/
+    RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TSC,ENABLE);
+
+    return TSC_ERROR_OK;
+}
+
+/**
+* @brief  Configure internal charge resistor for some channels
+* @param  res:  internal resistor selecte
+*   This parameter can be one of the following values:
+*      @arg TSC_RESR_CHN_RESIST_0:    1M OHM
+*      @arg TSC_RESR_CHN_RESIST_1:    882K OHM
+*      @arg TSC_RESR_CHN_RESIST_2:    756K OHM
+*      @arg TSC_RESR_CHN_RESIST_3:    630K OHM
+*      @arg TSC_RESR_CHN_RESIST_4:    504K OHM
+*      @arg TSC_RESR_CHN_RESIST_5:    378K OHM
+*      @arg TSC_RESR_CHN_RESIST_6:    252K OHM
+*      @arg TSC_RESR_CHN_RESIST_7:    126K OHM
+* @param  Channels: channels to be configed, as TSC_CHNEN defined
+*   This parameter:bit[0:23] used,bit[24:31] must be 0
+*                  bitx: TSC channel x
+* @return: none
+*/
+TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res )
+{
+    uint32_t i,chn,timeout,nReg,nPos;
+
+    assert_param(IS_TSC_CHN(Channels));
+    assert_param(IS_TSC_RESISTOR_VALUE(res));
+
+    /*Check charge resistor value */
+    if (res > TSC_RESRx_CHN_RESIST_7)
+        return TSC_ERROR_PARAMETER;
+
+    /* waiting tsc hw for idle status.*/
+    timeout = 0;
+    do
+    {
+        __TSC_HW_DISABLE();
+
+        if (++timeout > TSC_TIMEOUT)
+            return TSC_ERROR_HW_MODE;
+    }while (__TSC_GET_HW_MODE());
+
+    /* Mask invalie bits*/
+    chn  = Channels & TSC_CHNEN_CHN_SELx_Msk;
+
+    /* Set resistance for each channel one by one*/
+    for (i = 0; i<MAX_TSC_HW_CHN; i++)
+    {
+        if (chn & 0x00000001)
+        {
+            nReg = i >> 3;
+            nPos = (i & 0x7UL)*4;
+            MODIFY_REG(TSC->RESR[nReg],TSC_RESRx_CHN_RESIST_Msk<<nPos,res<<nPos);
+        }
+
+        chn >>= 1;
+    }
+
+    return TSC_ERROR_OK;
+}
+
+/**
+* @brief  Configure threshold value for some channels
+* @param  Channels: channels to be configed, as TSC_CHNEN defined
+*   This parameter:bit[0:23] used,bit[24:31] must be 0
+*                  bitx: TSC channel x
+* @param  base:   base value of threshold, 0-MAX_TSC_THRESHOLD_BASE
+* @param  delta:  delta value of threshold,0-MAX_TSC_THRESHOLD_DELRA
+* @return: None
+*/
+TSC_ErrorTypeDef TSC_ConfigThreshold(  uint32_t Channels, uint32_t base, uint32_t delta)
+{
+    uint32_t i, chn,timeout;
+    assert_param(IS_TSC_CHN(Channels));
+    assert_param(IS_TSC_THRESHOLD_BASE(base));
+    assert_param(IS_TSC_THRESHOLD_DELTA(delta));
+
+    /*Check the base and delta value*/
+    if ( (base>MAX_TSC_THRESHOLD_BASE)||(delta>MAX_TSC_THRESHOLD_DELTA))
+        return TSC_ERROR_PARAMETER;
+
+    /* waiting tsc hw for idle status.*/
+    timeout = 0;
+    do
+    {
+        __TSC_HW_DISABLE();
+
+        if (++timeout > TSC_TIMEOUT)
+            return TSC_ERROR_HW_MODE;
+    }while (__TSC_GET_HW_MODE());
+
+    /*Mask invalie bits*/
+    chn = Channels & TSC_CHNEN_CHN_SELx_Msk;
+
+    /* Set the base and delta for each channnel one by one*/
+    for (i = 0; i<MAX_TSC_HW_CHN; i++)
+    {
+        if (chn & 0x00000001)
+        {
+            TSC->THRHD[i] = (base<<TSC_THRHDx_BASE_Pos)|(delta<<TSC_THRHDx_DELTA_Pos);
+        }
+
+        chn >>= 1;
+    }
+
+    return TSC_ERROR_OK;
+}
+
+
+/**
+* @brief  Get parameters of one channel.
+* @param  ChnCfg: Pointer of TSC_ChnCfg structure.
+* @param  ChannelNum: The channel number of which we want to get parameters,must be less then MAX_TSC_HW_CHN
+* @return: None
+*/
+TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum)
+{
+    uint32_t nReg,nPos;
+
+    assert_param(IS_TSC_CHN_NUMBER(ChannelNum));
+
+    /*Check channel number*/
+    if (!(IS_TSC_CHN_NUMBER(ChannelNum)))
+        return TSC_ERROR_PARAMETER;
+
+    /* Get the base and delta value for a channel*/
+    ChnCfg->TSC_Base     = (TSC->THRHD[ChannelNum] & TSC_THRHDx_BASE_Msk) >> TSC_THRHDx_BASE_Pos;
+    ChnCfg->TSC_Delta    = (TSC->THRHD[ChannelNum] & TSC_THRHDx_DELTA_Msk)>> TSC_THRHDx_DELTA_Pos;
+
+    /* Get the charge resistor type for a channel*/
+    nReg = ChannelNum>>3;
+    nPos = (ChannelNum & 0x7UL)*4;
+    ChnCfg->TSC_Resistor = (TSC->RESR[nReg] >> nPos) & TSC_RESRx_CHN_RESIST_Msk;
+
+    return TSC_ERROR_OK;
+}
+
+

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_usart.c

@@ -0,0 +1,956 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_usart.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_usart.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @brief USART driver modules
+ * @{
+ */
+
+/** @addtogroup USART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Defines
+ * @{
+ */
+
+#define CTRL1_UEN_SET   ((uint16_t)0x2000) /*!< USART Enable Mask */
+#define CTRL1_UEN_RESET ((uint16_t)0xDFFF) /*!< USART Disable Mask */
+
+#define CTRL1_WUM_MASK ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */
+
+#define CTRL1_RCVWU_SET   ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */
+#define CTRL1_RCVWU_RESET ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */
+#define CTRL1_SDBRK_SET   ((uint16_t)0x0001) /*!< USART Break Character send Mask */
+#define CTRL1_CLR_MASK    ((uint16_t)0xE9F3) /*!< USART CTRL1 Mask */
+#define CTRL2_ADDR_MASK   ((uint16_t)0xFFF0) /*!< USART address Mask */
+
+#define CTRL2_LINMEN_SET   ((uint16_t)0x4000) /*!< USART LIN Enable Mask */
+#define CTRL2_LINMEN_RESET ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */
+
+#define CTRL2_LINBDL_MASK    ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */
+#define CTRL2_STPB_CLR_MASK  ((uint16_t)0xCFFF) /*!< USART CTRL2 STOP Bits Mask */
+#define CTRL2_CLOCK_CLR_MASK ((uint16_t)0xF0FF) /*!< USART CTRL2 Clock Mask */
+
+#define CTRL3_SCMEN_SET   ((uint16_t)0x0020) /*!< USART SC Enable Mask */
+#define CTRL3_SCMEN_RESET ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */
+
+#define CTRL3_SCNACK_SET   ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */
+#define CTRL3_SCNACK_RESET ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */
+
+#define CTRL3_HDMEN_SET   ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */
+#define CTRL3_HDMEN_RESET ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */
+
+#define CTRL3_IRDALP_MASK ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */
+#define CTRL3_CLR_MASK    ((uint16_t)0xFCFF) /*!< USART CTRL3 Mask */
+
+#define CTRL3_IRDAMEN_SET   ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */
+#define CTRL3_IRDAMEN_RESET ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */
+#define GTP_LSB_MASK        ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */
+#define GTP_MSB_MASK        ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
+#define INT_MASK            ((uint16_t)0x001F) /*!< USART Interrupt Mask */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *      USART1, USART2, USART3, UART4 or UART5.
+ */
+void USART_DeInit(USART_Module* USARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+    if (USARTx == USART1)
+    {
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, ENABLE);
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_USART1, DISABLE);
+    }
+    else if (USARTx == USART2)
+    {
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, ENABLE);
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART2, DISABLE);
+    }
+    else if (USARTx == USART3)
+    {
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, ENABLE);
+        RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_USART3, DISABLE);
+    }
+    else if (USARTx == UART4)
+    {
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, ENABLE);
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART4, DISABLE);
+    }
+    else if (USARTx == UART5)
+    {
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, ENABLE);
+        RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_UART5, DISABLE);
+    }
+}
+
+/**
+ * @brief  Initializes the USARTx peripheral according to the specified
+ *         parameters in the USART_InitStruct .
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_InitStruct pointer to a USART_InitType structure
+ *         that contains the configuration information for the specified USART
+ *         peripheral.
+ */
+void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct)
+{
+    uint32_t tmpregister = 0x00, apbclock = 0x00;
+    uint32_t integerdivider    = 0x00;
+    uint32_t fractionaldivider = 0x00;
+    uint32_t usartxbase        = 0;
+    RCC_ClocksType RCC_ClocksStatus;
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_USART_BAUDRATE(USART_InitStruct->BaudRate));
+    assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->WordLength));
+    assert_param(IS_USART_STOPBITS(USART_InitStruct->StopBits));
+    assert_param(IS_USART_PARITY(USART_InitStruct->Parity));
+    assert_param(IS_USART_MODE(USART_InitStruct->Mode));
+    assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->HardwareFlowControl));
+    /* The hardware flow control is available only for USART1, USART2 and USART3 */
+    if (USART_InitStruct->HardwareFlowControl != USART_HFCTRL_NONE)
+    {
+        assert_param(IS_USART_123_PERIPH(USARTx));
+    }
+
+    usartxbase = (uint32_t)USARTx;
+
+    /*---------------------------- USART CTRL2 Configuration -----------------------*/
+    tmpregister = USARTx->CTRL2;
+    /* Clear STOP[13:12] bits */
+    tmpregister &= CTRL2_STPB_CLR_MASK;
+    /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+    /* Set STOP[13:12] bits according to StopBits value */
+    tmpregister |= (uint32_t)USART_InitStruct->StopBits;
+
+    /* Write to USART CTRL2 */
+    USARTx->CTRL2 = (uint16_t)tmpregister;
+
+    /*---------------------------- USART CTRL1 Configuration -----------------------*/
+    tmpregister = USARTx->CTRL1;
+    /* Clear M, PCE, PS, TE and RE bits */
+    tmpregister &= CTRL1_CLR_MASK;
+    /* Configure the USART Word Length, Parity and mode ----------------------- */
+    /* Set the M bits according to WordLength value */
+    /* Set PCE and PS bits according to Parity value */
+    /* Set TE and RE bits according to Mode value */
+    tmpregister |= (uint32_t)USART_InitStruct->WordLength | USART_InitStruct->Parity | USART_InitStruct->Mode;
+    /* Write to USART CTRL1 */
+    USARTx->CTRL1 = (uint16_t)tmpregister;
+
+    /*---------------------------- USART CTRL3 Configuration -----------------------*/
+    tmpregister = USARTx->CTRL3;
+    /* Clear CTSE and RTSE bits */
+    tmpregister &= CTRL3_CLR_MASK;
+    /* Configure the USART HFC -------------------------------------------------*/
+    /* Set CTSE and RTSE bits according to HardwareFlowControl value */
+    tmpregister |= USART_InitStruct->HardwareFlowControl;
+    /* Write to USART CTRL3 */
+    USARTx->CTRL3 = (uint16_t)tmpregister;
+
+    /*---------------------------- USART PBC Configuration -----------------------*/
+    /* Configure the USART Baud Rate -------------------------------------------*/
+    RCC_GetClocksFreqValue(&RCC_ClocksStatus);
+    if ((usartxbase == USART1_BASE) || (usartxbase == UART4_BASE) || (usartxbase == UART5_BASE))
+    {
+        apbclock = RCC_ClocksStatus.Pclk2Freq;
+    }
+    else
+    {
+        apbclock = RCC_ClocksStatus.Pclk1Freq;
+    }
+
+    /* Determine the integer part */
+    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->BaudRate)));
+    tmpregister = (integerdivider / 100) << 4;
+
+    /* Determine the fractional part */
+    fractionaldivider = integerdivider - (100 * (tmpregister >> 4));
+
+    /* Implement the fractional part in the register */
+    tmpregister |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+
+    /* Write to USART PBC */
+    USARTx->BRCF = (uint16_t)tmpregister;
+}
+
+/**
+ * @brief  Fills each USART_InitStruct member with its default value.
+ * @param USART_InitStruct pointer to a USART_InitType structure
+ *         which will be initialized.
+ */
+void USART_StructInit(USART_InitType* USART_InitStruct)
+{
+    /* USART_InitStruct members default value */
+    USART_InitStruct->BaudRate            = 9600;
+    USART_InitStruct->WordLength          = USART_WL_8B;
+    USART_InitStruct->StopBits            = USART_STPB_1;
+    USART_InitStruct->Parity              = USART_PE_NO;
+    USART_InitStruct->Mode                = USART_MODE_RX | USART_MODE_TX;
+    USART_InitStruct->HardwareFlowControl = USART_HFCTRL_NONE;
+}
+
+/**
+ * @brief  Initializes the USARTx peripheral Clock according to the
+ *          specified parameters in the USART_ClockInitStruct .
+ * @param USARTx where x can be 1, 2, 3 to select the USART peripheral.
+ * @param USART_ClockInitStruct pointer to a USART_ClockInitType
+ *         structure that contains the configuration information for the specified
+ *         USART peripheral.
+ * @note The Smart Card and Synchronous modes are not available for UART4/UART5.
+ */
+void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct)
+{
+    uint32_t tmpregister = 0x00;
+    /* Check the parameters */
+    assert_param(IS_USART_123_PERIPH(USARTx));
+    assert_param(IS_USART_CLOCK(USART_ClockInitStruct->Clock));
+    assert_param(IS_USART_CPOL(USART_ClockInitStruct->Polarity));
+    assert_param(IS_USART_CPHA(USART_ClockInitStruct->Phase));
+    assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->LastBit));
+
+    /*---------------------------- USART CTRL2 Configuration -----------------------*/
+    tmpregister = USARTx->CTRL2;
+    /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+    tmpregister &= CTRL2_CLOCK_CLR_MASK;
+    /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+    /* Set CLKEN bit according to Clock value */
+    /* Set CPOL bit according to Polarity value */
+    /* Set CPHA bit according to Phase value */
+    /* Set LBCL bit according to LastBit value */
+    tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity
+                   | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit;
+    /* Write to USART CTRL2 */
+    USARTx->CTRL2 = (uint16_t)tmpregister;
+}
+
+/**
+ * @brief  Fills each USART_ClockInitStruct member with its default value.
+ * @param USART_ClockInitStruct pointer to a USART_ClockInitType
+ *         structure which will be initialized.
+ */
+void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct)
+{
+    /* USART_ClockInitStruct members default value */
+    USART_ClockInitStruct->Clock    = USART_CLK_DISABLE;
+    USART_ClockInitStruct->Polarity = USART_CLKPOL_LOW;
+    USART_ClockInitStruct->Phase    = USART_CLKPHA_1EDGE;
+    USART_ClockInitStruct->LastBit  = USART_CLKLB_DISABLE;
+}
+
+/**
+ * @brief  Enables or disables the specified USART peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ *         This parameter can be one of the following values:
+ *           USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USARTx peripheral.
+ *         This parameter can be: ENABLE or DISABLE.
+ */
+void USART_Enable(USART_Module* USARTx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the selected USART by setting the UE bit in the CTRL1 register */
+        USARTx->CTRL1 |= CTRL1_UEN_SET;
+    }
+    else
+    {
+        /* Disable the selected USART by clearing the UE bit in the CTRL1 register */
+        USARTx->CTRL1 &= CTRL1_UEN_RESET;
+    }
+}
+
+/**
+ * @brief  Enables or disables the specified USART interrupts.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_INT specifies the USART interrupt sources to be enabled or disabled.
+ *   This parameter can be one of the following values:
+ *     @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ *     @arg USART_INT_LINBD LIN Break detection interrupt
+ *     @arg USART_INT_TXDE Transmit Data Register empty interrupt
+ *     @arg USART_INT_TXC Transmission complete interrupt
+ *     @arg USART_INT_RXDNE Receive Data register not empty interrupt
+ *     @arg USART_INT_IDLEF Idle line detection interrupt
+ *     @arg USART_INT_PEF Parity Error interrupt
+ *     @arg USART_INT_ERRF Error interrupt(Frame error, noise error, overrun error)
+ * @param Cmd new state of the specified USARTx interrupts.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd)
+{
+    uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+    uint32_t usartxbase = 0x00;
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_USART_CFG_INT(USART_INT));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    /* The CTS interrupt is not available for UART4/UART5 */
+    if (USART_INT == USART_INT_CTSF)
+    {
+        assert_param(IS_USART_123_PERIPH(USARTx));
+    }
+
+    usartxbase = (uint32_t)USARTx;
+
+    /* Get the USART register index */
+    usartreg = (((uint8_t)USART_INT) >> 0x05);
+
+    /* Get the interrupt position */
+    itpos  = USART_INT & INT_MASK;
+    itmask = (((uint32_t)0x01) << itpos);
+
+    if (usartreg == 0x01) /* The IT is in CTRL1 register */
+    {
+        usartxbase += 0x0C;
+    }
+    else if (usartreg == 0x02) /* The IT is in CTRL2 register */
+    {
+        usartxbase += 0x10;
+    }
+    else /* The IT is in CTRL3 register */
+    {
+        usartxbase += 0x14;
+    }
+    if (Cmd != DISABLE)
+    {
+        *(__IO uint32_t*)usartxbase |= itmask;
+    }
+    else
+    {
+        *(__IO uint32_t*)usartxbase &= ~itmask;
+    }
+}
+
+/**
+ * @brief  Enables or disables the USART's DMA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_DMAReq specifies the DMA request.
+ *   This parameter can be any combination of the following values:
+ *     @arg USART_DMAREQ_TX USART DMA transmit request
+ *     @arg USART_DMAREQ_RX USART DMA receive request
+ * @param Cmd new state of the DMA Request sources.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_USART_DMAREQ(USART_DMAReq));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+           DADDR bits in the USART CTRL3 register */
+        USARTx->CTRL3 |= USART_DMAReq;
+    }
+    else
+    {
+        /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+           DADDR bits in the USART CTRL3 register */
+        USARTx->CTRL3 &= (uint16_t)~USART_DMAReq;
+    }
+}
+
+/**
+ * @brief  Sets the address of the USART node.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Addr Indicates the address of the USART node.
+ */
+void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_USART_ADDRESS(USART_Addr));
+
+    /* Clear the USART address */
+    USARTx->CTRL2 &= CTRL2_ADDR_MASK;
+    /* Set the USART address node */
+    USARTx->CTRL2 |= USART_Addr;
+}
+
+/**
+ * @brief  Selects the USART WakeUp method.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_WakeUpMode specifies the USART wakeup method.
+ *   This parameter can be one of the following values:
+ *     @arg USART_WUM_IDLELINE WakeUp by an idle line detection
+ *     @arg USART_WUM_ADDRMASK WakeUp by an address mark
+ */
+void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_USART_WAKEUP(USART_WakeUpMode));
+
+    USARTx->CTRL1 &= CTRL1_WUM_MASK;
+    USARTx->CTRL1 |= USART_WakeUpMode;
+}
+
+/**
+ * @brief  Determines if the USART is in mute mode or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USART mute mode.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the USART mute mode  by setting the RWU bit in the CTRL1 register */
+        USARTx->CTRL1 |= CTRL1_RCVWU_SET;
+    }
+    else
+    {
+        /* Disable the USART mute mode by clearing the RWU bit in the CTRL1 register */
+        USARTx->CTRL1 &= CTRL1_RCVWU_RESET;
+    }
+}
+
+/**
+ * @brief  Sets the USART LIN Break detection length.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_LINBreakDetectLength specifies the LIN break detection length.
+ *   This parameter can be one of the following values:
+ *     @arg USART_LINBDL_10B 10-bit break detection
+ *     @arg USART_LINBDL_11B 11-bit break detection
+ */
+void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+    USARTx->CTRL2 &= CTRL2_LINBDL_MASK;
+    USARTx->CTRL2 |= USART_LINBreakDetectLength;
+}
+
+/**
+ * @brief  Enables or disables the USART's LIN mode.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USART LIN mode.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the LIN mode by setting the LINEN bit in the CTRL2 register */
+        USARTx->CTRL2 |= CTRL2_LINMEN_SET;
+    }
+    else
+    {
+        /* Disable the LIN mode by clearing the LINEN bit in the CTRL2 register */
+        USARTx->CTRL2 &= CTRL2_LINMEN_RESET;
+    }
+}
+
+/**
+ * @brief  Transmits single data through the USARTx peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param Data the data to transmit.
+ */
+void USART_SendData(USART_Module* USARTx, uint16_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_USART_DATA(Data));
+
+    /* Transmit Data */
+    USARTx->DAT = (Data & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief  Returns the most recent received data by the USARTx peripheral.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @return The received data.
+ */
+uint16_t USART_ReceiveData(USART_Module* USARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+    /* Receive Data */
+    return (uint16_t)(USARTx->DAT & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief  Transmits break characters.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ */
+void USART_SendBreak(USART_Module* USARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+    /* Send break characters */
+    USARTx->CTRL1 |= CTRL1_SDBRK_SET;
+}
+
+/**
+ * @brief  Sets the specified USART guard time.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param USART_GuardTime specifies the guard time.
+ * @note The guard time bits are not available for UART4/UART5.
+ */
+void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_123_PERIPH(USARTx));
+
+    /* Clear the USART Guard time */
+    USARTx->GTP &= GTP_LSB_MASK;
+    /* Set the USART guard time */
+    USARTx->GTP |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+ * @brief  Sets the system clock prescaler.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Prescaler specifies the prescaler clock.
+ * @note   The function is used for IrDA mode with UART4 and UART5.
+ */
+void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+    /* Clear the USART prescaler */
+    USARTx->GTP &= GTP_MSB_MASK;
+    /* Set the USART prescaler */
+    USARTx->GTP |= USART_Prescaler;
+}
+
+/**
+ * @brief  Enables or disables the USART's Smart Card mode.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param Cmd new state of the Smart Card mode.
+ *   This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4/UART5.
+ */
+void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_123_PERIPH(USARTx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the SC mode by setting the SCEN bit in the CTRL3 register */
+        USARTx->CTRL3 |= CTRL3_SCMEN_SET;
+    }
+    else
+    {
+        /* Disable the SC mode by clearing the SCEN bit in the CTRL3 register */
+        USARTx->CTRL3 &= CTRL3_SCMEN_RESET;
+    }
+}
+
+/**
+ * @brief  Enables or disables NACK transmission.
+ * @param USARTx where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param Cmd new state of the NACK transmission.
+ *   This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4/UART5.
+ */
+void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_123_PERIPH(USARTx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+    if (Cmd != DISABLE)
+    {
+        /* Enable the NACK transmission by setting the NACK bit in the CTRL3 register */
+        USARTx->CTRL3 |= CTRL3_SCNACK_SET;
+    }
+    else
+    {
+        /* Disable the NACK transmission by clearing the NACK bit in the CTRL3 register */
+        USARTx->CTRL3 &= CTRL3_SCNACK_RESET;
+    }
+}
+
+/**
+ * @brief  Enables or disables the USART's Half Duplex communication.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the USART Communication.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the Half-Duplex mode by setting the HDSEL bit in the CTRL3 register */
+        USARTx->CTRL3 |= CTRL3_HDMEN_SET;
+    }
+    else
+    {
+        /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CTRL3 register */
+        USARTx->CTRL3 &= CTRL3_HDMEN_RESET;
+    }
+}
+
+/**
+ * @brief  Configures the USART's IrDA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IrDAMode specifies the IrDA mode.
+ *   This parameter can be one of the following values:
+ *     @arg USART_IRDAMODE_LOWPPWER
+ *     @arg USART_IRDAMODE_NORMAL
+ */
+void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+    USARTx->CTRL3 &= CTRL3_IRDALP_MASK;
+    USARTx->CTRL3 |= USART_IrDAMode;
+}
+
+/**
+ * @brief  Enables or disables the USART's IrDA interface.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param Cmd new state of the IrDA mode.
+ *   This parameter can be: ENABLE or DISABLE.
+ */
+void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_FUNCTIONAL_STATE(Cmd));
+
+    if (Cmd != DISABLE)
+    {
+        /* Enable the IrDA mode by setting the IREN bit in the CTRL3 register */
+        USARTx->CTRL3 |= CTRL3_IRDAMEN_SET;
+    }
+    else
+    {
+        /* Disable the IrDA mode by clearing the IREN bit in the CTRL3 register */
+        USARTx->CTRL3 &= CTRL3_IRDAMEN_RESET;
+    }
+}
+
+/**
+ * @brief  Checks whether the specified USART flag is set or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG specifies the flag to check.
+ *   This parameter can be one of the following values:
+ *     @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5)
+ *     @arg USART_FLAG_LINBD LIN Break detection flag
+ *     @arg USART_FLAG_TXDE Transmit data register empty flag
+ *     @arg USART_FLAG_TXC Transmission Complete flag
+ *     @arg USART_FLAG_RXDNE Receive data register not empty flag
+ *     @arg USART_FLAG_IDLEF Idle Line detection flag
+ *     @arg USART_FLAG_OREF OverRun Error flag
+ *     @arg USART_FLAG_NEF Noise Error flag
+ *     @arg USART_FLAG_FEF Framing Error flag
+ *     @arg USART_FLAG_PEF Parity Error flag
+ * @return The new state of USART_FLAG (SET or RESET).
+ */
+FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_USART_FLAG(USART_FLAG));
+    /* The CTS flag is not available for UART4/UART5 */
+    if (USART_FLAG == USART_FLAG_CTSF)
+    {
+        assert_param(IS_USART_123_PERIPH(USARTx));
+    }
+
+    if ((USARTx->STS & USART_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the USARTx's pending flags.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG specifies the flag to clear.
+ *   This parameter can be any combination of the following values:
+ *     @arg USART_FLAG_CTSF CTS Change flag (not available for UART4 and UART5).
+ *     @arg USART_FLAG_LINBD LIN Break detection flag.
+ *     @arg USART_FLAG_TXC Transmission Complete flag.
+ *     @arg USART_FLAG_RXDNE Receive data register not empty flag.
+ *
+ * @note
+ *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ *     error) and IDLE (Idle line detected) flags are cleared by software
+ *     sequence: a read operation to USART_SR register (USART_GetFlagStatus())
+ *     followed by a read operation to USART_DR register (USART_ReceiveData()).
+ *   - RXNE flag can be also cleared by a read to the USART_DR register
+ *     (USART_ReceiveData()).
+ *   - TC flag can be also cleared by software sequence: a read operation to
+ *     USART_SR register (USART_GetFlagStatus()) followed by a write operation
+ *     to USART_DR register (USART_SendData()).
+ *   - TXE flag is cleared only by a write to the USART_DR register
+ *     (USART_SendData()).
+ */
+void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+    /* The CTS flag is not available for UART4/UART5 */
+    if ((USART_FLAG & USART_FLAG_CTSF) == USART_FLAG_CTSF)
+    {
+        assert_param(IS_USART_123_PERIPH(USARTx));
+    }
+
+    USARTx->STS = (uint16_t)~USART_FLAG;
+}
+
+/**
+ * @brief  Checks whether the specified USART interrupt has occurred or not.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_INT specifies the USART interrupt source to check.
+ *   This parameter can be one of the following values:
+ *     @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ *     @arg USART_INT_LINBD LIN Break detection interrupt
+ *     @arg USART_INT_TXDE Tansmit Data Register empty interrupt
+ *     @arg USART_INT_TXC Transmission complete interrupt
+ *     @arg USART_INT_RXDNE Receive Data register not empty interrupt
+ *     @arg USART_INT_IDLEF Idle line detection interrupt
+ *     @arg USART_INT_OREF OverRun Error interrupt
+ *     @arg USART_INT_NEF Noise Error interrupt
+ *     @arg USART_INT_FEF Framing Error interrupt
+ *     @arg USART_INT_PEF Parity Error interrupt
+ * @return The new state of USART_INT (SET or RESET).
+ */
+INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT)
+{
+    uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+    INTStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_USART_GET_INT(USART_INT));
+    /* The CTS interrupt is not available for UART4/UART5 */
+    if (USART_INT == USART_INT_CTSF)
+    {
+        assert_param(IS_USART_123_PERIPH(USARTx));
+    }
+
+    /* Get the USART register index */
+    usartreg = (((uint8_t)USART_INT) >> 0x05);
+    /* Get the interrupt position */
+    itmask = USART_INT & INT_MASK;
+    itmask = (uint32_t)0x01 << itmask;
+
+    if (usartreg == 0x01) /* The IT  is in CTRL1 register */
+    {
+        itmask &= USARTx->CTRL1;
+    }
+    else if (usartreg == 0x02) /* The IT  is in CTRL2 register */
+    {
+        itmask &= USARTx->CTRL2;
+    }
+    else /* The IT  is in CTRL3 register */
+    {
+        itmask &= USARTx->CTRL3;
+    }
+
+    bitpos = USART_INT >> 0x08;
+    bitpos = (uint32_t)0x01 << bitpos;
+    bitpos &= USARTx->STS;
+    if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/**
+ * @brief  Clears the USARTx's interrupt pending bits.
+ * @param USARTx Select the USART or the UART peripheral.
+ *   This parameter can be one of the following values:
+ *   USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_INT specifies the interrupt pending bit to clear.
+ *   This parameter can be one of the following values:
+ *     @arg USART_INT_CTSF CTS change interrupt (not available for UART4 and UART5)
+ *     @arg USART_INT_LINBD LIN Break detection interrupt
+ *     @arg USART_INT_TXC Transmission complete interrupt.
+ *     @arg USART_INT_RXDNE Receive Data register not empty interrupt.
+ *
+ * @note
+ *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ *     error) and IDLE (Idle line detected) pending bits are cleared by
+ *     software sequence: a read operation to USART_SR register
+ *     (USART_GetIntStatus()) followed by a read operation to USART_DR register
+ *     (USART_ReceiveData()).
+ *   - RXNE pending bit can be also cleared by a read to the USART_DR register
+ *     (USART_ReceiveData()).
+ *   - TC pending bit can be also cleared by software sequence: a read
+ *     operation to USART_SR register (USART_GetIntStatus()) followed by a write
+ *     operation to USART_DR register (USART_SendData()).
+ *   - TXE pending bit is cleared only by a write to the USART_DR register
+ *     (USART_SendData()).
+ */
+void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT)
+{
+    uint16_t bitpos = 0x00, itmask = 0x00;
+    /* Check the parameters */
+    assert_param(IS_USART_ALL_PERIPH(USARTx));
+    assert_param(IS_USART_CLR_INT(USART_INT));
+    /* The CTS interrupt is not available for UART4/UART5 */
+    if (USART_INT == USART_INT_CTSF)
+    {
+        assert_param(IS_USART_123_PERIPH(USARTx));
+    }
+
+    bitpos      = USART_INT >> 0x08;
+    itmask      = ((uint16_t)0x01 << (uint16_t)bitpos);
+    USARTx->STS = (uint16_t)~itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_wwdg.c

@@ -0,0 +1,223 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file n32g43x_wwdg.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "n32g43x_wwdg.h"
+#include "n32g43x_rcc.h"
+
+/** @addtogroup N32G43x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @brief WWDG driver modules
+ * @{
+ */
+
+/** @addtogroup WWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Defines
+ * @{
+ */
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFADDR (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFG_OFFADDR  (WWDG_OFFADDR + 0x04)
+#define EWINT_BIT    0x09
+#define CFG_EWINT_BB (PERIPH_BB_BASE + (CFG_OFFADDR * 32) + (EWINT_BIT * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CTRL register bit mask */
+#define CTRL_ACTB_SET ((uint32_t)0x00000080)
+
+/* CFG register bit mask */
+#define CFG_TIMERB_MASK ((uint32_t)0xFFFFFE7F)
+#define CFG_W_MASK      ((uint32_t)0xFFFFFF80)
+#define BIT_MASK        ((uint8_t)0x7F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
+ */
+void WWDG_DeInit(void)
+{
+    RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, ENABLE);
+    RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, DISABLE);
+}
+
+/**
+ * @brief  Sets the WWDG Prescaler.
+ * @param WWDG_Prescaler specifies the WWDG Prescaler.
+ *   This parameter can be one of the following values:
+ *     @arg WWDG_PRESCALER_DIV1 WWDG counter clock = (PCLK1/4096)/1
+ *     @arg WWDG_PRESCALER_DIV2 WWDG counter clock = (PCLK1/4096)/2
+ *     @arg WWDG_PRESCALER_DIV4 WWDG counter clock = (PCLK1/4096)/4
+ *     @arg WWDG_PRESCALER_DIV8 WWDG counter clock = (PCLK1/4096)/8
+ */
+void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler)
+{
+    uint32_t tmpregister = 0;
+    /* Check the parameters */
+    assert_param(IS_WWDG_PRESCALER_DIV(WWDG_Prescaler));
+    /* Clear WDGTB[1:0] bits */
+    tmpregister = WWDG->CFG & CFG_TIMERB_MASK;
+    /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+    tmpregister |= WWDG_Prescaler;
+    /* Store the new value */
+    WWDG->CFG = tmpregister;
+}
+
+/**
+ * @brief  Sets the WWDG window value.
+ * @param WindowValue specifies the window value to be compared to the downcounter.
+ *   This parameter value must be lower than 0x80.
+ */
+void WWDG_SetWValue(uint8_t WindowValue)
+{
+    __IO uint32_t tmpregister = 0;
+
+    /* Check the parameters */
+    assert_param(IS_WWDG_WVALUE(WindowValue));
+    /* Clear W[6:0] bits */
+
+    tmpregister = WWDG->CFG & CFG_W_MASK;
+
+    /* Set W[6:0] bits according to WindowValue value */
+    tmpregister |= WindowValue & (uint32_t)BIT_MASK;
+
+    /* Store the new value */
+    WWDG->CFG = tmpregister;
+}
+
+/**
+ * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
+ */
+void WWDG_EnableInt(void)
+{
+    *(__IO uint32_t*)CFG_EWINT_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief  Sets the WWDG counter value.
+ * @param Counter specifies the watchdog counter value.
+ *   This parameter must be a number between 0x40 and 0x7F.
+ */
+void WWDG_SetCnt(uint8_t Counter)
+{
+    /* Check the parameters */
+    assert_param(IS_WWDG_CNT(Counter));
+    /* Write to T[6:0] bits to configure the counter value, no need to do
+       a read-modify-write; writing a 0 to WDGA bit does nothing */
+    WWDG->CTRL = Counter & BIT_MASK;
+}
+
+/**
+ * @brief  Enables WWDG and load the counter value.
+ * @param Counter specifies the watchdog counter value.
+ *   This parameter must be a number between 0x40 and 0x7F.
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+    /* Check the parameters */
+    assert_param(IS_WWDG_CNT(Counter));
+    WWDG->CTRL = CTRL_ACTB_SET | Counter;
+}
+
+/**
+ * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
+ * @return The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetEWINTF(void)
+{
+    return (FlagStatus)(WWDG->STS);
+}
+
+/**
+ * @brief  Clears Early Wakeup interrupt flag.
+ */
+void WWDG_ClrEWINTF(void)
+{
+    WWDG->STS = (uint32_t)RESET;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_core.h

@@ -0,0 +1,264 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_core.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_CORE_H__
+#define __USB_CORE_H__
+
+#include "n32g43x.h"
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @brief N32G43x USB low level driver
+ * @{
+ */
+
+typedef enum _CONTROL_STATE
+{
+    WaitSetup,      /* 0 */
+    SettingUp,      /* 1 */
+    InData,         /* 2 */
+    OutData,        /* 3 */
+    LastInData,     /* 4 */
+    LastOutData,    /* 5 */
+    WaitStatusIn,   /* 6 */
+    WaitStatusOut,  /* 7 */
+    Stalled,        /* 8 */
+    Pause           /* 9 */
+} USB_ControlState; /* The state machine states of a control pipe */
+
+typedef struct OneDescriptor
+{
+    uint8_t* Descriptor;
+    uint16_t Descriptor_Size;
+} USB_OneDescriptor, *PONE_DESCRIPTOR;
+/* All the request process routines return a value of this type
+   If the return value is not SUCCESS or NOT_READY,
+   the software will STALL the correspond endpoint */
+typedef enum _RESULT
+{
+    Success = 0, /* Process successfully */
+    Error,
+    UnSupport,
+    Not_Ready /* The process has not been finished, endpoint will be
+                     NAK to further request */
+} USB_Result;
+
+/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/
+typedef struct _ENDPOINT_INFO
+{
+    /* When send data out of the device,
+     CopyData() is used to get data buffer 'Length' bytes data
+     if Length is 0,
+      CopyData() returns the total length of the data
+      if the request is not supported, returns 0
+      (NEW Feature )
+       if CopyData() returns -1, the calling routine should not proceed
+       further and will resume the SETUP process by the class device
+     if Length is not 0,
+      CopyData() returns a pointer to indicate the data location
+     Usb_wLength is the data remain to be sent,
+     Usb_wOffset is the Offset of original data
+    When receive data from the host,
+     CopyData() is used to get user data buffer which is capable
+     of Length bytes data to copy data from the endpoint buffer.
+     if Length is 0,
+      CopyData() returns the available data length,
+     if Length is not 0,
+      CopyData() returns user buffer address
+     Usb_rLength is the data remain to be received,
+     Usb_rPointer is the Offset of data buffer
+    */
+    uint16_t Usb_wLength;
+    uint16_t Usb_wOffset;
+    uint16_t PacketSize;
+    uint8_t* (*CopyData)(uint16_t Length);
+} USB_EndpointMess;
+
+/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/
+
+typedef struct _DEVICE
+{
+    uint8_t TotalEndpoint;      /* Number of endpoints that are used */
+    uint8_t TotalConfiguration; /* Number of configuration available */
+} USB_Device;
+
+typedef union
+{
+    uint16_t w;
+    struct BW
+    {
+        uint8_t bb1;
+        uint8_t bb0;
+    } bw;
+} uint16_t_uint8_t;
+
+typedef struct _DEVICE_INFO
+{
+    uint8_t bmRequestType;     /* bmRequestType */
+    uint8_t bRequest;          /* bRequest */
+    uint16_t_uint8_t wValues;  /* wValue */
+    uint16_t_uint8_t wIndexs;  /* wIndex */
+    uint16_t_uint8_t wLengths; /* wLength */
+
+    uint8_t CtrlState; /* of type USB_ControlState */
+    uint8_t CurrentFeature;
+    uint8_t CurrentConfiguration;    /* Selected configuration */
+    uint8_t CurrentInterface;        /* Selected interface of current configuration */
+    uint8_t CurrentAlternateSetting; /* Selected Alternate Setting of current
+                                        interface*/
+
+    USB_EndpointMess Ctrl_Info;
+} USB_DeviceMess;
+
+typedef struct _DEVICE_PROP
+{
+    void (*Init)(void);  /* Initialize the device */
+    void (*Reset)(void); /* Reset routine of this device */
+
+    /* Device dependent process after the status stage */
+    void (*Process_Status_IN)(void);
+    void (*Process_Status_OUT)(void);
+
+    /* Procedure of process on setup stage of a class specified request with data stage */
+    /* All class specified requests with data stage are processed in Class_Data_Setup
+     Class_Data_Setup()
+      responses to check all special requests and fills USB_EndpointMess
+      according to the request
+      If IN tokens are expected, then wLength & wOffset will be filled
+      with the total transferring bytes and the starting position
+      If OUT tokens are expected, then rLength & rOffset will be filled
+      with the total expected bytes and the starting position in the buffer
+
+      If the request is valid, Class_Data_Setup returns SUCCESS, else UNSUPPORT
+
+     CAUTION:
+      Since GET_CONFIGURATION & GET_INTERFACE are highly related to
+      the individual classes, they will be checked and processed here.
+    */
+    USB_Result (*Class_Data_Setup)(uint8_t RequestNo);
+
+    /* Procedure of process on setup stage of a class specified request without data stage */
+    /* All class specified requests without data stage are processed in Class_NoData_Setup
+     Class_NoData_Setup
+      responses to check all special requests and perform the request
+
+     CAUTION:
+      Since SET_CONFIGURATION & SET_INTERFACE are highly related to
+      the individual classes, they will be checked and processed here.
+    */
+    USB_Result (*Class_NoData_Setup)(uint8_t RequestNo);
+
+    /*Class_Get_Interface_Setting
+     This function is used by the file usb_core.c to test if the selected Interface
+     and Alternate Setting (uint8_t Interface, uint8_t AlternateSetting) are supported by
+     the application.
+     This function is writing by user. It should return "SUCCESS" if the Interface
+     and Alternate Setting are supported by the application or "UNSUPPORT" if they
+     are not supported. */
+
+    USB_Result (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting);
+
+    uint8_t* (*GetDeviceDescriptor)(uint16_t Length);
+    uint8_t* (*GetConfigDescriptor)(uint16_t Length);
+    uint8_t* (*GetStringDescriptor)(uint16_t Length);
+
+    /* This field is not used in current library version. It is kept only for
+     compatibility with previous versions */
+    void* RxEP_buffer;
+
+    uint8_t MaxPacketSize;
+
+} DEVICE_PROP;
+
+typedef struct _USER_STANDARD_REQUESTS
+{
+    void (*User_GetConfiguration)(void);   /* Get Configuration */
+    void (*User_SetConfiguration)(void);   /* Set Configuration */
+    void (*User_GetInterface)(void);       /* Get Interface */
+    void (*User_SetInterface)(void);       /* Set Interface */
+    void (*User_GetStatus)(void);          /* Get Status */
+    void (*User_ClearFeature)(void);       /* Clear Feature */
+    void (*User_SetEndPointFeature)(void); /* Set Endpoint Feature */
+    void (*User_SetDeviceFeature)(void);   /* Set Device Feature */
+    void (*User_SetDeviceAddress)(void);   /* Set Device Address */
+} USER_STANDARD_REQUESTS;
+
+#define Type_Recipient (pInformation->bmRequestType & (REQUEST_TYPE | RECIPIENT))
+
+#define Usb_rLength Usb_wLength
+#define Usb_rOffset Usb_wOffset
+
+#define USBwValue   wValues.w
+#define USBwValue0  wValues.bw.bb0
+#define USBwValue1  wValues.bw.bb1
+#define USBwIndex   wIndexs.w
+#define USBwIndex0  wIndexs.bw.bb0
+#define USBwIndex1  wIndexs.bw.bb1
+#define USBwLength  wLengths.w
+#define USBwLength0 wLengths.bw.bb0
+#define USBwLength1 wLengths.bw.bb1
+
+uint8_t USB_ProcessSetup0(void);
+uint8_t USB_ProcessPost0(void);
+uint8_t USB_ProcessOut0(void);
+uint8_t USB_ProcessIn0(void);
+
+USB_Result Standard_SetEndPointFeature(void);
+USB_Result Standard_SetDeviceFeature(void);
+
+uint8_t* Standard_GetConfiguration(uint16_t Length);
+USB_Result Standard_SetConfiguration(void);
+uint8_t* Standard_GetInterface(uint16_t Length);
+USB_Result Standard_SetInterface(void);
+uint8_t* Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc);
+
+uint8_t* Standard_GetStatus(uint16_t Length);
+USB_Result Standard_ClearFeature(void);
+void USB_SetDeviceAddress(uint8_t);
+void USB_ProcessNop(void);
+
+extern DEVICE_PROP Device_Property;
+extern USER_STANDARD_REQUESTS User_Standard_Requests;
+extern USB_Device Device_Table;
+extern USB_DeviceMess Device_Info;
+
+/* cells saving status during interrupt servicing */
+extern __IO uint16_t SaveRState;
+extern __IO uint16_t SaveTState;
+
+/**
+ * @}
+ */
+
+#endif /* __USB_CORE_H__ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_def.h

@@ -0,0 +1,98 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_def.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_DEF_H__
+#define __USB_DEF_H__
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+typedef enum _RECIPIENT_TYPE
+{
+    DEVICE_RECIPIENT,    /* Recipient device */
+    INTERFACE_RECIPIENT, /* Recipient interface */
+    ENDPOINT_RECIPIENT,  /* Recipient endpoint */
+    OTHER_RECIPIENT
+} RECIPIENT_TYPE;
+
+typedef enum _STANDARD_REQUESTS
+{
+    GET_STATUS = 0,
+    CLR_FEATURE,
+    RESERVED1,
+    SET_FEATURE,
+    RESERVED2,
+    SET_ADDRESS,
+    GET_DESCRIPTOR,
+    SET_DESCRIPTOR,
+    GET_CONFIGURATION,
+    SET_CONFIGURATION,
+    GET_INTERFACE,
+    SET_INTERFACE,
+    TOTAL_SREQUEST, /* Total number of Standard request */
+    SYNCH_FRAME = 12
+} STANDARD_REQUESTS;
+
+/* Definition of "USBwValue" */
+typedef enum _DESCRIPTOR_TYPE
+{
+    DEVICE_DESCRIPTOR = 1,
+    CONFIG_DESCRIPTOR,
+    STRING_DESCRIPTOR,
+    INTERFACE_DESCRIPTOR,
+    ENDPOINT_DESCRIPTOR
+} DESCRIPTOR_TYPE;
+
+/* Feature selector of a SET_FEATURE or CLR_FEATURE */
+typedef enum _FEATURE_SELECTOR
+{
+    ENDPOINT_STALL,
+    DEVICE_REMOTE_WAKEUP
+} FEATURE_SELECTOR;
+
+/* Definition of "bmRequestType" */
+#define REQUEST_TYPE     0x60 /* Mask to get request type */
+#define STANDARD_REQUEST 0x00 /* Standard request */
+#define CLASS_REQUEST    0x20 /* Class request */
+#define VENDOR_REQUEST   0x40 /* Vendor request */
+
+#define RECIPIENT 0x1F /* Mask to get recipient */
+
+/**
+ * @}
+ */
+
+#endif /* __USB_DEF_H__ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_init.h

@@ -0,0 +1,71 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_init.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_INIT_H__
+#define __USB_INIT_H__
+
+#include "n32g43x.h"
+#include "usb_core.h"
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+void USB_Init(void);
+
+/*  The number of current endpoint, it will be used to specify an endpoint */
+extern uint8_t EPindex;
+/*  The number of current device, it is an index to the Device_Table */
+/*extern uint8_t Device_no; */
+/*  Points to the USB_DeviceMess structure of current device */
+/*  The purpose of this register is to speed up the execution */
+extern USB_DeviceMess* pInformation;
+/*  Points to the DEVICE_PROP structure of current device */
+/*  The purpose of this register is to speed up the execution */
+extern DEVICE_PROP* pProperty;
+/*  Temporary save the state of Rx & Tx status. */
+/*  Whenever the Rx or Tx state is changed, its value is saved */
+/*  in this variable first and will be set to the EPRB or EPRA */
+/*  at the end of interrupt process */
+extern USER_STANDARD_REQUESTS* pUser_Standard_Requests;
+
+extern uint16_t SaveState;
+extern uint16_t wInterrupt_Mask;
+
+/**
+ * @}
+ */
+
+#endif /* __USB_INIT_H__ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_int.h

@@ -0,0 +1,50 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_int.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_INT_H__
+#define __USB_INT_H__
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+void USB_CorrectTransferLp(void);
+void USB_CorrectTransferHp(void);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_INT_H__ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_lib.h

@@ -0,0 +1,47 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_lib.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_LIB_H__
+#define __USB_LIB_H__
+
+#include "usb_type.h"
+#include "usb_regs.h"
+#include "usb_def.h"
+#include "usb_core.h"
+#include "usb_init.h"
+#include "usb_sil.h"
+#include "usb_mem.h"
+#include "usb_int.h"
+
+#endif /* __USB_LIB_H__ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_mem.h

@@ -0,0 +1,52 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_mem.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_MEM_H__
+#define __USB_MEM_H__
+
+#include "n32g43x.h"
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+/**
+ * @}
+ */
+
+#endif /*__USB_MEM_H__*/

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_regs.h

@@ -0,0 +1,716 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_regs.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_REGS_H__
+#define __USB_REGS_H__
+
+#include "n32g43x.h"
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+typedef enum _EP_DBUF_DIR
+{
+    /* double buffered endpoint direction */
+    EP_DBUF_ERR,
+    EP_DBUF_OUT,
+    EP_DBUF_IN
+} EP_DBUF_DIR;
+
+/* endpoint buffer number */
+enum EP_BUF_NUM
+{
+    EP_NOBUF,
+    EP_BUF0,
+    EP_BUF1
+};
+
+#define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */
+#define PMAAddr (0x40006000L) /* USB_IP Packet Memory Area base address   */
+
+/******************************************************************************/
+/*                         Special registers                                  */
+/******************************************************************************/
+/* Pull up controller register */
+#define DP_CTRL ((__IO unsigned*)(0x40001824))
+
+#define _ClrDPCtrl() (*DP_CTRL = (*DP_CTRL) & (~0x8000000));
+#define _EnPortPullup() (*DP_CTRL = (*DP_CTRL) | 0x02000000);
+#define _DisPortPullup() (*DP_CTRL = (*DP_CTRL) & 0xFDFFFFFF);
+
+/******************************************************************************/
+/*                         General registers                                  */
+/******************************************************************************/
+
+/* Control register */
+#define USB_CTRL ((__IO unsigned*)(RegBase + 0x40))
+/* Interrupt status register */
+#define USB_STS ((__IO unsigned*)(RegBase + 0x44))
+/* Frame number register */
+#define USB_FN ((__IO unsigned*)(RegBase + 0x48))
+/* Device address register */
+#define USB_ADDR ((__IO unsigned*)(RegBase + 0x4C))
+/* Buffer Table address register */
+#define USB_BUFTAB ((__IO unsigned*)(RegBase + 0x50))
+/******************************************************************************/
+/*                         Endpoint registers                                 */
+/******************************************************************************/
+#define EP0REG ((__IO unsigned*)(RegBase)) /* endpoint 0 register address */
+
+/* Endpoint Addresses (w/direction) */
+#define EP0_OUT ((uint8_t)0x00)
+#define EP0_IN  ((uint8_t)0x80)
+#define EP1_OUT ((uint8_t)0x01)
+#define EP1_IN  ((uint8_t)0x81)
+#define EP2_OUT ((uint8_t)0x02)
+#define EP2_IN  ((uint8_t)0x82)
+#define EP3_OUT ((uint8_t)0x03)
+#define EP3_IN  ((uint8_t)0x83)
+#define EP4_OUT ((uint8_t)0x04)
+#define EP4_IN  ((uint8_t)0x84)
+#define EP5_OUT ((uint8_t)0x05)
+#define EP5_IN  ((uint8_t)0x85)
+#define EP6_OUT ((uint8_t)0x06)
+#define EP6_IN  ((uint8_t)0x86)
+#define EP7_OUT ((uint8_t)0x07)
+#define EP7_IN  ((uint8_t)0x87)
+
+/* endpoints enumeration */
+#define ENDP0 ((uint8_t)0)
+#define ENDP1 ((uint8_t)1)
+#define ENDP2 ((uint8_t)2)
+#define ENDP3 ((uint8_t)3)
+#define ENDP4 ((uint8_t)4)
+#define ENDP5 ((uint8_t)5)
+#define ENDP6 ((uint8_t)6)
+#define ENDP7 ((uint8_t)7)
+
+/******************************************************************************/
+/*                       USB_STS interrupt events                                */
+/******************************************************************************/
+#define STS_CTRS  (0x8000) /* Correct TRansfer (clear-only bit) */
+#define STS_DOVR  (0x4000) /* DMA OVeR/underrun (clear-only bit) */
+#define STS_ERROR (0x2000) /* ERRor (clear-only bit) */
+#define STS_WKUP  (0x1000) /* WaKe UP (clear-only bit) */
+#define STS_SUSPD (0x0800) /* SUSPend (clear-only bit) */
+#define STS_RST   (0x0400) /* RESET (clear-only bit) */
+#define STS_SOF   (0x0200) /* Start Of Frame (clear-only bit) */
+#define STS_ESOF  (0x0100) /* Expected Start Of Frame (clear-only bit) */
+
+#define STS_DIR   (0x0010) /* DIRection of transaction (read-only bit)  */
+#define STS_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit)  */
+
+#define CLR_CTRS  (~STS_CTRS)  /* clear Correct TRansfer bit */
+#define CLR_DOVR  (~STS_DOVR)  /* clear DMA OVeR/underrun bit*/
+#define CLR_ERROR (~STS_ERROR) /* clear ERRor bit */
+#define CLR_WKUP  (~STS_WKUP)  /* clear WaKe UP bit     */
+#define CLR_SUSPD (~STS_SUSPD) /* clear SUSPend bit     */
+#define CLR_RST   (~STS_RST)   /* clear RESET bit      */
+#define CLR_SOF   (~STS_SOF)   /* clear Start Of Frame bit   */
+#define CLR_ESOF  (~STS_ESOF)  /* clear Expected Start Of Frame bit */
+
+/******************************************************************************/
+/*             USB_CTRL control register bits definitions                         */
+/******************************************************************************/
+#define CTRL_CTRSM  (0x8000) /* Correct TRansfer Mask */
+#define CTRL_DOVRM  (0x4000) /* DMA OVeR/underrun Mask */
+#define CTRL_ERRORM (0x2000) /* ERRor Mask */
+#define CTRL_WKUPM  (0x1000) /* WaKe UP Mask */
+#define CTRL_SUSPDM (0x0800) /* SUSPend Mask */
+#define CTRL_RSTM   (0x0400) /* RESET Mask   */
+#define CTRL_SOFM   (0x0200) /* Start Of Frame Mask */
+#define CTRL_ESOFM  (0x0100) /* Expected Start Of Frame Mask */
+
+#define CTRL_RESUM   (0x0010) /* RESUME request */
+#define CTRL_FSUSPD  (0x0008) /* Force SUSPend */
+#define CTRL_LP_MODE (0x0004) /* Low-power MODE */
+#define CTRL_PD      (0x0002) /* Power DoWN */
+#define CTRL_FRST    (0x0001) /* Force USB RESet */
+
+/******************************************************************************/
+/*                USB_FN Frame Number Register bit definitions                   */
+/******************************************************************************/
+#define FN_RXDP (0x8000) /* status of D+ data line */
+#define FN_RXDM (0x4000) /* status of D- data line */
+#define FN_LCK  (0x2000) /* LoCKed */
+#define FN_LSOF (0x1800) /* Lost SOF */
+#define FN_FNUM (0x07FF) /* Frame Number */
+/******************************************************************************/
+/*               USB_ADDR Device ADDRess bit definitions                         */
+/******************************************************************************/
+#define ADDR_EFUC (0x80)
+#define ADDR_ADDR (0x7F)
+/******************************************************************************/
+/*                            Endpoint register                               */
+/******************************************************************************/
+/* bit positions */
+#define EP_CTRS_RX   (0x8000) /* EndPoint Correct TRansfer RX */
+#define EP_DATTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */
+#define EPRX_STS     (0x3000) /* EndPoint RX STATus bit field */
+#define EP_SETUP     (0x0800) /* EndPoint SETUP */
+#define EP_T_FIELD   (0x0600) /* EndPoint TYPE */
+#define EP_KIND      (0x0100) /* EndPoint KIND */
+#define EP_CTRS_TX   (0x0080) /* EndPoint Correct TRansfer TX */
+#define EP_DATTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */
+#define EPTX_STS     (0x0030) /* EndPoint TX STATus bit field */
+#define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */
+
+/* EndPoint REGister INTEN (no toggle fields) */
+#define EPREG_MASK (EP_CTRS_RX | EP_SETUP | EP_T_FIELD | EP_KIND | EP_CTRS_TX | EPADDR_FIELD)
+
+/* EP_TYPE[1:0] EndPoint TYPE */
+#define EP_TYPE_MASK   (0x0600) /* EndPoint TYPE Mask */
+#define EP_BULK        (0x0000) /* EndPoint BULK */
+#define EP_CONTROL     (0x0200) /* EndPoint CONTROL */
+#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
+#define EP_INTERRUPT   (0x0600) /* EndPoint INTERRUPT */
+#define EP_T_MASK      (~EP_T_FIELD & EPREG_MASK)
+
+/* EP_KIND EndPoint KIND */
+#define EPKIND_MASK (~EP_KIND & EPREG_MASK)
+
+/* STAT_TX[1:0] STATus for TX transfer */
+#define EP_TX_DIS       (0x0000) /* EndPoint TX DISabled */
+#define EP_TX_STALL     (0x0010) /* EndPoint TX STALLed */
+#define EP_TX_NAK       (0x0020) /* EndPoint TX NAKed */
+#define EP_TX_VALID     (0x0030) /* EndPoint TX VALID */
+#define EPTX_DATTOG1    (0x0010) /* EndPoint TX Data TOGgle bit1 */
+#define EPTX_DATTOG2    (0x0020) /* EndPoint TX Data TOGgle bit2 */
+#define EPTX_DATTOGMASK (EPTX_STS | EPREG_MASK)
+
+/* STAT_RX[1:0] STATus for RX transfer */
+#define EP_RX_DIS       (0x0000) /* EndPoint RX DISabled */
+#define EP_RX_STALL     (0x1000) /* EndPoint RX STALLed */
+#define EP_RX_NAK       (0x2000) /* EndPoint RX NAKed */
+#define EP_RX_VALID     (0x3000) /* EndPoint RX VALID */
+#define EPRX_DATTOG1    (0x1000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DATTOG2    (0x2000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DATTOGMASK (EPRX_STS | EPREG_MASK)
+
+/* USB_SetCtrl */
+#define _SetCNTR(wRegValue) (*USB_CTRL = (uint16_t)wRegValue)
+
+/* USB_SetSts */
+#define _SetISTR(wRegValue) (*USB_STS = (uint16_t)wRegValue)
+
+/* USB_SetAddr */
+#define _SetDADDR(wRegValue) (*USB_ADDR = (uint16_t)wRegValue)
+
+/* USB_SetBuftab */
+#define _SetBTABLE(wRegValue) (*USB_BUFTAB = (uint16_t)(wRegValue & 0xFFF8))
+
+/* USB_GetCtrl */
+#define _GetCNTR() ((uint16_t)*USB_CTRL)
+
+/* USB_GetSts */
+#define _GetISTR() ((uint16_t)*USB_STS)
+
+/* USB_GetFn */
+#define _GetFNR() ((uint16_t)*USB_FN)
+
+/* USB_GetAddr */
+#define _GetDADDR() ((uint16_t)*USB_ADDR)
+
+/* USB_GetBTABLE */
+#define _GetBTABLE() ((uint16_t)*USB_BUFTAB)
+
+/* USB_SetEndPoint */
+#define _SetENDPOINT(bEpNum, wRegValue) (*(EP0REG + bEpNum) = (uint16_t)wRegValue)
+
+/* USB_GetEndPoint */
+#define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum)))
+
+/*******************************************************************************
+ * Macro Name     : USB_SetEpType
+ * Description    : sets the type in the endpoint register(bits EP_TYPE[1:0])
+ * Input          : bEpNum: Endpoint Number.
+ *                  wType
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEPType(bEpNum, wType) (_SetENDPOINT(bEpNum, ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType)))
+
+/*******************************************************************************
+ * Macro Name     : USB_GetEpType
+ * Description    : gets the type in the endpoint register(bits EP_TYPE[1:0])
+ * Input          : bEpNum: Endpoint Number.
+ * Output         : None.
+ * Return         : Endpoint Type
+ *******************************************************************************/
+#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
+
+/*******************************************************************************
+ * Macro Name     : SetEPTxStatus
+ * Description    : sets the status for tx transfer (bits STAT_TX[1:0]).
+ * Input          : bEpNum: Endpoint Number.
+ *                  wState: new state
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEPTxStatus(bEpNum, wState)                                                                                 \
+    {                                                                                                                  \
+        register uint16_t _wRegVal;                                                                                    \
+        _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DATTOGMASK;                                                             \
+        /* toggle first bit ? */                                                                                       \
+        if ((EPTX_DATTOG1 & wState) != 0)                                                                              \
+            _wRegVal ^= EPTX_DATTOG1;                                                                                  \
+        /* toggle second bit ?  */                                                                                     \
+        if ((EPTX_DATTOG2 & wState) != 0)                                                                              \
+            _wRegVal ^= EPTX_DATTOG2;                                                                                  \
+        _SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX));                                                    \
+    } /* _SetEPTxStatus */
+
+/*******************************************************************************
+ * Macro Name     : SetEPRxStatus
+ * Description    : sets the status for rx transfer (bits STAT_TX[1:0])
+ * Input          : bEpNum: Endpoint Number.
+ *                  wState: new state.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEPRxStatus(bEpNum, wState)                                                                                 \
+    {                                                                                                                  \
+        register uint16_t _wRegVal;                                                                                    \
+                                                                                                                       \
+        _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DATTOGMASK;                                                             \
+        /* toggle first bit ? */                                                                                       \
+        if ((EPRX_DATTOG1 & wState) != 0)                                                                              \
+            _wRegVal ^= EPRX_DATTOG1;                                                                                  \
+        /* toggle second bit ? */                                                                                      \
+        if ((EPRX_DATTOG2 & wState) != 0)                                                                              \
+            _wRegVal ^= EPRX_DATTOG2;                                                                                  \
+        _SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX));                                                    \
+    } /* _SetEPRxStatus */
+
+/*******************************************************************************
+ * Macro Name     : SetEPRxTxStatus
+ * Description    : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+ * Input          : bEpNum: Endpoint Number.
+ *                  wStaterx: new state.
+ *                  wStatetx: new state.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEPRxTxStatus(bEpNum, wStaterx, wStatetx)                                                                   \
+    {                                                                                                                  \
+        register uint32_t _wRegVal;                                                                                    \
+                                                                                                                       \
+        _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DATTOGMASK | EPTX_STS);                                                \
+        /* toggle first bit ? */                                                                                       \
+        if ((EPRX_DATTOG1 & wStaterx) != 0)                                                                            \
+            _wRegVal ^= EPRX_DATTOG1;                                                                                  \
+        /* toggle second bit ? */                                                                                      \
+        if ((EPRX_DATTOG2 & wStaterx) != 0)                                                                            \
+            _wRegVal ^= EPRX_DATTOG2;                                                                                  \
+        /* toggle first bit ? */                                                                                       \
+        if ((EPTX_DATTOG1 & wStatetx) != 0)                                                                            \
+            _wRegVal ^= EPTX_DATTOG1;                                                                                  \
+        /* toggle second bit ?  */                                                                                     \
+        if ((EPTX_DATTOG2 & wStatetx) != 0)                                                                            \
+            _wRegVal ^= EPTX_DATTOG2;                                                                                  \
+        _SetENDPOINT(bEpNum, _wRegVal | EP_CTRS_RX | EP_CTRS_TX);                                                      \
+    } /* _SetEPRxTxStatus */
+/*******************************************************************************
+ * Macro Name     : USB_GetEpTxSts / USB_GetEpRxSts
+ * Description    : gets the status for tx/rx transfer (bits STAT_TX[1:0]
+ *                  /STAT_RX[1:0])
+ * Input          : bEpNum: Endpoint Number.
+ * Output         : None.
+ * Return         : status .
+ *******************************************************************************/
+#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STS)
+
+#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STS)
+
+/*******************************************************************************
+ * Macro Name     : USB_SetEpTxValid / USB_SetEpRxValid
+ * Description    : sets directly the VALID tx/rx-status into the enpoint register
+ * Input          : bEpNum: Endpoint Number.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID))
+
+#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID))
+
+/*******************************************************************************
+ * Macro Name     : USB_GetTxStallSts / USB_GetRxStallSts.
+ * Description    : checks stall condition in an endpoint.
+ * Input          : bEpNum: Endpoint Number.
+ * Output         : None.
+ * Return         : TRUE = endpoint in stall condition.
+ *******************************************************************************/
+#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) == EP_TX_STALL)
+#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) == EP_RX_STALL)
+
+/*******************************************************************************
+ * Macro Name     : USB_SetEpKind / USB_ClrEpKind.
+ * Description    : set & clear EP_KIND bit.
+ * Input          : bEpNum: Endpoint Number.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEP_KIND(bEpNum)                                                                                            \
+    (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | ((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))))
+#define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPKIND_MASK))))
+
+/*******************************************************************************
+ * Macro Name     : USB_SetStsOut / USB_ClrStsOut.
+ * Description    : Sets/clears directly STATUS_OUT bit in the endpoint register.
+ * Input          : bEpNum: Endpoint Number.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _Set_Status_Out(bEpNum)   _SetEP_KIND(bEpNum)
+#define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum)
+
+/*******************************************************************************
+ * Macro Name     : USB_SetEpDoubleBufer / USB_ClrEpDoubleBufer.
+ * Description    : Sets/clears directly EP_KIND bit in the endpoint register.
+ * Input          : bEpNum: Endpoint Number.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEPDoubleBuff(bEpNum)   _SetEP_KIND(bEpNum)
+#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum)
+
+/*******************************************************************************
+ * Macro Name     : USB_ClrEpCtrsRx / USB_ClrEpCtrsTx.
+ * Description    : Clears bit CTR_RX / CTR_TX in the endpoint register.
+ * Input          : bEpNum: Endpoint Number.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
+#define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
+
+/*******************************************************************************
+ * Macro Name     : USB_DattogRx / USB_DattogTx .
+ * Description    : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+ * Input          : bEpNum: Endpoint Number.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _ToggleDTOG_RX(bEpNum)                                                                                         \
+    (_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+#define _ToggleDTOG_TX(bEpNum)                                                                                         \
+    (_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+
+/*******************************************************************************
+ * Macro Name     : USB_ClrDattogRx / USB_ClrDattogTx.
+ * Description    : Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+ * Input          : bEpNum: Endpoint Number.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _ClearDTOG_RX(bEpNum)                                                                                          \
+    if ((_GetENDPOINT(bEpNum) & EP_DATTOG_RX) != 0)                                                                    \
+    _ToggleDTOG_RX(bEpNum)
+#define _ClearDTOG_TX(bEpNum)                                                                                          \
+    if ((_GetENDPOINT(bEpNum) & EP_DATTOG_TX) != 0)                                                                    \
+    _ToggleDTOG_TX(bEpNum)
+/*******************************************************************************
+ * Macro Name     : USB_SetEpAddress.
+ * Description    : Sets address in an endpoint register.
+ * Input          : bEpNum: Endpoint Number.
+ *                  bAddr: Address.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEPAddress(bEpNum, bAddr)                                                                                   \
+    _SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
+
+/*******************************************************************************
+ * Macro Name     : USB_GetEpAddress.
+ * Description    : Gets address in an endpoint register.
+ * Input          : bEpNum: Endpoint Number.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD))
+
+#define _pEPTxAddr(bEpNum)  ((uint32_t*)((_GetBTABLE() + bEpNum * 8) * 2 + PMAAddr))
+#define _pEPTxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 2) * 2 + PMAAddr))
+#define _pEPRxAddr(bEpNum)  ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 4) * 2 + PMAAddr))
+#define _pEPRxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 6) * 2 + PMAAddr))
+
+/*******************************************************************************
+ * Macro Name     : USB_SetEpTxAddr / USB_SetEpRxAddr.
+ * Description    : sets address of the tx/rx buffer.
+ * Input          : bEpNum: Endpoint Number.
+ *                  wAddr: address to be set (must be word aligned).
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEPTxAddr(bEpNum, wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
+#define _SetEPRxAddr(bEpNum, wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
+
+/*******************************************************************************
+ * Macro Name     : USB_GetEpTxAddr / USB_GetEpRxAddr.
+ * Description    : Gets address of the tx/rx buffer.
+ * Input          : bEpNum: Endpoint Number.
+ * Output         : None.
+ * Return         : address of the buffer.
+ *******************************************************************************/
+#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum))
+#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum))
+
+/*******************************************************************************
+ * Macro Name     : USB_SetEpCntRxReg.
+ * Description    : Sets counter of rx buffer with no. of blocks.
+ * Input          : pdwReg: pointer to counter.
+ *                  wCount: Counter.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _BlocksOf32(dwReg, wCount, wNBlocks)                                                                           \
+    {                                                                                                                  \
+        wNBlocks = wCount >> 5;                                                                                        \
+        if ((wCount & 0x1f) == 0)                                                                                      \
+            wNBlocks--;                                                                                                \
+        *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000);                                                               \
+    } /* _BlocksOf32 */
+
+#define _BlocksOf2(dwReg, wCount, wNBlocks)                                                                            \
+    {                                                                                                                  \
+        wNBlocks = wCount >> 1;                                                                                        \
+        if ((wCount & 0x1) != 0)                                                                                       \
+            wNBlocks++;                                                                                                \
+        *pdwReg = (uint32_t)(wNBlocks << 10);                                                                          \
+    } /* _BlocksOf2 */
+
+#define _SetEPCountRxReg(dwReg, wCount)                                                                                \
+    {                                                                                                                  \
+        uint16_t wNBlocks;                                                                                             \
+        if (wCount > 62)                                                                                               \
+        {                                                                                                              \
+            _BlocksOf32(dwReg, wCount, wNBlocks);                                                                      \
+        }                                                                                                              \
+        else                                                                                                           \
+        {                                                                                                              \
+            _BlocksOf2(dwReg, wCount, wNBlocks);                                                                       \
+        }                                                                                                              \
+    } /* _SetEPCountRxReg */
+
+#define _SetEPRxDblBuf0Count(bEpNum, wCount)                                                                           \
+    {                                                                                                                  \
+        uint32_t* pdwReg = _pEPTxCount(bEpNum);                                                                        \
+        _SetEPCountRxReg(pdwReg, wCount);                                                                              \
+    }
+/*******************************************************************************
+ * Macro Name     : USB_SetEpTxCnt / USB_SetEpRxCnt.
+ * Description    : sets counter for the tx/rx buffer.
+ * Input          : bEpNum: endpoint number.
+ *                  wCount: Counter value.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEPTxCount(bEpNum, wCount) (*_pEPTxCount(bEpNum) = wCount)
+#define _SetEPRxCount(bEpNum, wCount)                                                                                  \
+    {                                                                                                                  \
+        uint32_t* pdwReg = _pEPRxCount(bEpNum);                                                                        \
+        _SetEPCountRxReg(pdwReg, wCount);                                                                              \
+    }
+/*******************************************************************************
+ * Macro Name     : USB_GetEpTxCnt / USB_GetEpRxCnt.
+ * Description    : gets counter of the tx buffer.
+ * Input          : bEpNum: endpoint number.
+ * Output         : None.
+ * Return         : Counter value.
+ *******************************************************************************/
+#define _GetEPTxCount(bEpNum) ((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff)
+#define _GetEPRxCount(bEpNum) ((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff)
+
+/*******************************************************************************
+ * Macro Name     : USB_SetEpDblBuf0Addr / USB_SetEpDblBuf1Addr.
+ * Description    : Sets buffer 0/1 address in a double buffer endpoint.
+ * Input          : bEpNum: endpoint number.
+ *                : wBuf0Addr: buffer 0 address.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEPDblBuf0Addr(bEpNum, wBuf0Addr)                                                                           \
+    {                                                                                                                  \
+        _SetEPTxAddr(bEpNum, wBuf0Addr);                                                                               \
+    }
+#define _SetEPDblBuf1Addr(bEpNum, wBuf1Addr)                                                                           \
+    {                                                                                                                  \
+        _SetEPRxAddr(bEpNum, wBuf1Addr);                                                                               \
+    }
+
+/*******************************************************************************
+ * Macro Name     : USB_SetEpDblBuferAddr.
+ * Description    : Sets addresses in a double buffer endpoint.
+ * Input          : bEpNum: endpoint number.
+ *                : wBuf0Addr: buffer 0 address.
+ *                : wBuf1Addr = buffer 1 address.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr)                                                                \
+    {                                                                                                                  \
+        _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);                                                                          \
+        _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);                                                                          \
+    } /* _SetEPDblBuffAddr */
+
+/*******************************************************************************
+ * Macro Name     : USB_GetEpDblBuf0Addr / USB_GetEpDblBuf1Addr.
+ * Description    : Gets buffer 0/1 address of a double buffer endpoint.
+ * Input          : bEpNum: endpoint number.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
+#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
+
+/*******************************************************************************
+ * Macro Name     : USB_SetEpDblBuferCnt / USB_SetEpDblBuf0Cnt / USB_SetEpDblBuf1Cnt.
+ * Description    : Gets buffer 0/1 address of a double buffer endpoint.
+ * Input          : bEpNum: endpoint number.
+ *                : bDir: endpoint dir  EP_DBUF_OUT = OUT
+ *                                      EP_DBUF_IN  = IN
+ *                : wCount: Counter value
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _SetEPDblBuf0Count(bEpNum, bDir, wCount)                                                                       \
+    {                                                                                                                  \
+        if (bDir == EP_DBUF_OUT)                                                                                       \
+        /* OUT endpoint */                                                                                             \
+        {                                                                                                              \
+            _SetEPRxDblBuf0Count(bEpNum, wCount);                                                                      \
+        }                                                                                                              \
+        else if (bDir == EP_DBUF_IN)                                                                                   \
+            /* IN endpoint */                                                                                          \
+            *_pEPTxCount(bEpNum) = (uint32_t)wCount;                                                                   \
+    } /* USB_SetEpDblBuf0Cnt*/
+
+#define _SetEPDblBuf1Count(bEpNum, bDir, wCount)                                                                       \
+    {                                                                                                                  \
+        if (bDir == EP_DBUF_OUT)                                                                                       \
+        /* OUT endpoint */                                                                                             \
+        {                                                                                                              \
+            _SetEPRxCount(bEpNum, wCount);                                                                             \
+        }                                                                                                              \
+        else if (bDir == EP_DBUF_IN)                                                                                   \
+            /* IN endpoint */                                                                                          \
+            *_pEPRxCount(bEpNum) = (uint32_t)wCount;                                                                   \
+    } /* USB_SetEpDblBuf1Cnt */
+
+#define _SetEPDblBuffCount(bEpNum, bDir, wCount)                                                                       \
+    {                                                                                                                  \
+        _SetEPDblBuf0Count(bEpNum, bDir, wCount);                                                                      \
+        _SetEPDblBuf1Count(bEpNum, bDir, wCount);                                                                      \
+    } /* _SetEPDblBuffCount  */
+
+/*******************************************************************************
+ * Macro Name     : USB_GetEpDblBuf0Cnt / USB_GetEpDblBuf1Cnt.
+ * Description    : Gets buffer 0/1 rx/tx counter for double buffering.
+ * Input          : bEpNum: endpoint number.
+ * Output         : None.
+ * Return         : None.
+ *******************************************************************************/
+#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
+#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
+
+extern __IO uint16_t wIstr; /* USB_STS register last read value */
+
+void USB_SetCtrl(uint16_t /*wRegValue*/);
+void USB_SetSts(uint16_t /*wRegValue*/);
+void USB_SetAddr(uint16_t /*wRegValue*/);
+void USB_SetBuftab(uint16_t /*wRegValue*/);
+void USB_SetBuftab(uint16_t /*wRegValue*/);
+uint16_t USB_GetCtrl(void);
+uint16_t USB_GetSts(void);
+uint16_t USB_GetFn(void);
+uint16_t USB_GetAddr(void);
+uint16_t USB_GetBTABLE(void);
+void USB_SetEndPoint(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/);
+uint16_t USB_GetEndPoint(uint8_t /*bEpNum*/);
+void USB_SetEpType(uint8_t /*bEpNum*/, uint16_t /*wType*/);
+uint16_t USB_GetEpType(uint8_t /*bEpNum*/);
+void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void USB_SetDouBleBuferEpStall(uint8_t /*bEpNum*/, uint8_t bDir);
+uint16_t USB_GetEpTxSts(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxSts(uint8_t /*bEpNum*/);
+void USB_SetEpTxValid(uint8_t /*bEpNum*/);
+void USB_SetEpRxValid(uint8_t /*bEpNum*/);
+uint16_t USB_GetTxStallSts(uint8_t /*bEpNum*/);
+uint16_t USB_GetRxStallSts(uint8_t /*bEpNum*/);
+void USB_SetEpKind(uint8_t /*bEpNum*/);
+void USB_ClrEpKind(uint8_t /*bEpNum*/);
+void USB_SetStsOut(uint8_t /*bEpNum*/);
+void USB_ClrStsOut(uint8_t /*bEpNum*/);
+void USB_SetEpDoubleBufer(uint8_t /*bEpNum*/);
+void USB_ClrEpDoubleBufer(uint8_t /*bEpNum*/);
+void USB_ClrEpCtrsRx(uint8_t /*bEpNum*/);
+void USB_ClrEpCtrsTx(uint8_t /*bEpNum*/);
+void USB_DattogRx(uint8_t /*bEpNum*/);
+void USB_DattogTx(uint8_t /*bEpNum*/);
+void USB_ClrDattogRx(uint8_t /*bEpNum*/);
+void USB_ClrDattogTx(uint8_t /*bEpNum*/);
+void USB_SetEpAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/);
+uint8_t USB_GetEpAddress(uint8_t /*bEpNum*/);
+void USB_SetEpTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+void USB_SetEpRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+uint16_t USB_GetEpTxAddr(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxAddr(uint8_t /*bEpNum*/);
+void USB_SetEpCntRxReg(uint32_t* /*pdwReg*/, uint16_t /*wCount*/);
+void USB_SetEpTxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+void USB_SetEpRxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+uint16_t USB_GetEpTxCnt(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpRxCnt(uint8_t /*bEpNum*/);
+void USB_SetEpDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/);
+void USB_SetEpDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/);
+void USB_SetEpDblBuferAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/);
+uint16_t USB_GetEpDblBuf0Addr(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpDblBuf1Addr(uint8_t /*bEpNum*/);
+void USB_SetEpDblBuferCnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void USB_SetEpDblBuf0Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void USB_SetEpDblBuf1Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+uint16_t USB_GetEpDblBuf0Cnt(uint8_t /*bEpNum*/);
+uint16_t USB_GetEpDblBuf1Cnt(uint8_t /*bEpNum*/);
+EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/);
+void USB_FreeUserBuf(uint8_t bEpNum /*bEpNum*/, uint8_t bDir);
+uint16_t USB_ToWord(uint8_t, uint8_t);
+uint16_t USB_ByteSwap(uint16_t);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_REGS_H__ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_sil.h

@@ -0,0 +1,53 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_sil.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_SIL_H__
+#define __USB_SIL_H__
+
+#include "n32g43x.h"
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+uint32_t USB_SilInit(void);
+uint32_t USB_SilWrite(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize);
+uint32_t USB_SilRead(uint8_t bEpAddr, uint8_t* pBufferPointer);
+
+/**
+ * @}
+ */
+
+#endif /* __USB_SIL_H__ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_type.h

@@ -0,0 +1,54 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_type.h
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#ifndef __USB_TYPE_H__
+#define __USB_TYPE_H__
+
+#include "usb_conf.h"
+#include <stdbool.h>
+
+/**
+ * @addtogroup N32G43X_USB_Driver
+ * @{
+ */
+
+#ifndef NULL
+#define NULL ((void*)0)
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __USB_TYPE_H__ */

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_core.c

@@ -0,0 +1,950 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_core.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+#define ValBit(VAR, Place) (VAR & (1 << Place))
+#define SetBit(VAR, Place) (VAR |= (1 << Place))
+#define ClrBit(VAR, Place) (VAR &= ((1 << Place) ^ 255))
+
+#define Send0LengthData()                                                                                              \
+    {                                                                                                                  \
+        _SetEPTxCount(ENDP0, 0);                                                                                       \
+        vSetEPTxStatus(EP_TX_VALID);                                                                                   \
+    }
+
+#define vSetEPRxStatus(st) (SaveRState = st)
+#define vSetEPTxStatus(st) (SaveTState = st)
+
+#define USB_StatusIn()  Send0LengthData()
+#define USB_StatusOut() vSetEPRxStatus(EP_RX_VALID)
+
+#define StatusInfo0 StatusInfo.bw.bb1 /* Reverse bb0 & bb1 */
+#define StatusInfo1 StatusInfo.bw.bb0
+
+uint16_t_uint8_t StatusInfo;
+
+bool Data_Mul_MaxPacketSize = false;
+
+static void DataStageOut(void);
+static void DataStageIn(void);
+static void NoData_Setup0(void);
+static void Data_Setup0(void);
+
+/**
+ * @brief Return the current configuration variable address.
+ * @param  Length: How many bytes are needed.
+ * @return Return 1 , if the request is invalid when "Length" is 0.
+ *                  Return "Buffer" if the "Length" is not 0.
+ */
+uint8_t* Standard_GetConfiguration(uint16_t Length)
+{
+    if (Length == 0)
+    {
+        pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->CurrentConfiguration);
+        return 0;
+    }
+    pUser_Standard_Requests->User_GetConfiguration();
+    return (uint8_t*)&pInformation->CurrentConfiguration;
+}
+
+/**
+ * @brief This routine is called to set the configuration value
+ *                  Then each class should configure device itself.
+ * @return
+ * - Success, if the request is performed.
+ * - UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetConfiguration(void)
+{
+    if ((pInformation->USBwValue0 <= Device_Table.TotalConfiguration) && (pInformation->USBwValue1 == 0)
+        && (pInformation->USBwIndex == 0)) /*call Back usb spec 2.0*/
+    {
+        pInformation->CurrentConfiguration = pInformation->USBwValue0;
+        pUser_Standard_Requests->User_SetConfiguration();
+        return Success;
+    }
+    else
+    {
+        return UnSupport;
+    }
+}
+
+/**
+ * @brief Return the Alternate Setting of the current interface.
+ * @param  Length: How many bytes are needed.
+ * @return
+ * - NULL, if the request is invalid when "Length" is 0.
+ * - "Buffer" if the "Length" is not 0.
+ */
+uint8_t* Standard_GetInterface(uint16_t Length)
+{
+    if (Length == 0)
+    {
+        pInformation->Ctrl_Info.Usb_wLength = sizeof(pInformation->CurrentAlternateSetting);
+        return 0;
+    }
+    pUser_Standard_Requests->User_GetInterface();
+    return (uint8_t*)&pInformation->CurrentAlternateSetting;
+}
+
+/**
+ * @brief This routine is called to set the interface.
+ *                  Then each class should configure the interface them self.
+ * @return
+ * - Success, if the request is performed.
+ * - UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetInterface(void)
+{
+    USB_Result Re;
+    /*Test if the specified Interface and Alternate Setting are supported by
+      the application Firmware*/
+    Re = (*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, pInformation->USBwValue0);
+
+    if (pInformation->CurrentConfiguration != 0)
+    {
+        if ((Re != Success) || (pInformation->USBwIndex1 != 0) || (pInformation->USBwValue1 != 0))
+        {
+            return UnSupport;
+        }
+        else if (Re == Success)
+        {
+            pUser_Standard_Requests->User_SetInterface();
+            pInformation->CurrentInterface        = pInformation->USBwIndex0;
+            pInformation->CurrentAlternateSetting = pInformation->USBwValue0;
+            return Success;
+        }
+    }
+
+    return UnSupport;
+}
+
+/**
+ * @brief Copy the device request data to "StatusInfo buffer".
+ * @param  Length: How many bytes are needed.
+ * @return Return 0, if the request is at end of data block,
+ *                  or is invalid when "Length" is 0.
+ */
+uint8_t* Standard_GetStatus(uint16_t Length)
+{
+    if (Length == 0)
+    {
+        pInformation->Ctrl_Info.Usb_wLength = 2;
+        return 0;
+    }
+
+    /* Reset Status Information */
+    StatusInfo.w = 0;
+
+    if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+    {
+        /*Get Device Status */
+        uint8_t Feature = pInformation->CurrentFeature;
+
+        /* Remote Wakeup enabled */
+        if (ValBit(Feature, 5))
+        {
+            SetBit(StatusInfo0, 1);
+        }
+        else
+        {
+            ClrBit(StatusInfo0, 1);
+        }
+
+        /* Bus-powered */
+        if (ValBit(Feature, 6))
+        {
+            SetBit(StatusInfo0, 0);
+        }
+        else /* Self-powered */
+        {
+            ClrBit(StatusInfo0, 0);
+        }
+    }
+    /*Interface Status*/
+    else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+    {
+        return (uint8_t*)&StatusInfo;
+    }
+    /*Get EndPoint Status*/
+    else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+    {
+        uint8_t Related_Endpoint;
+        uint8_t wIndex0 = pInformation->USBwIndex0;
+
+        Related_Endpoint = (wIndex0 & 0x0f);
+        if (ValBit(wIndex0, 7))
+        {
+            /* IN endpoint */
+            if (_GetTxStallStatus(Related_Endpoint))
+            {
+                SetBit(StatusInfo0, 0); /* IN Endpoint stalled */
+            }
+        }
+        else
+        {
+            /* OUT endpoint */
+            if (_GetRxStallStatus(Related_Endpoint))
+            {
+                SetBit(StatusInfo0, 0); /* OUT Endpoint stalled */
+            }
+        }
+    }
+    else
+    {
+        return NULL;
+    }
+    pUser_Standard_Requests->User_GetStatus();
+    return (uint8_t*)&StatusInfo;
+}
+
+/**
+ * @brief Clear or disable a specific feature.
+ * @return - Return Success, if the request is performed.
+ *                  - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_ClearFeature(void)
+{
+    uint32_t Type_Rec = Type_Recipient;
+    uint32_t Status;
+
+    if (Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+    { /*Device Clear Feature*/
+        ClrBit(pInformation->CurrentFeature, 5);
+        return Success;
+    }
+    else if (Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+    { /*EndPoint Clear Feature*/
+        USB_Device* pDev;
+        uint32_t Related_Endpoint;
+        uint32_t wIndex0;
+        uint32_t rEP;
+
+        if ((pInformation->USBwValue != ENDPOINT_STALL) || (pInformation->USBwIndex1 != 0))
+        {
+            return UnSupport;
+        }
+
+        pDev             = &Device_Table;
+        wIndex0          = pInformation->USBwIndex0;
+        rEP              = wIndex0 & ~0x80;
+        Related_Endpoint = ENDP0 + rEP;
+
+        if (ValBit(pInformation->USBwIndex0, 7))
+        {
+            /*Get Status of endpoint & stall the request if the related_ENdpoint
+            is Disabled*/
+            Status = _GetEPTxStatus(Related_Endpoint);
+        }
+        else
+        {
+            Status = _GetEPRxStatus(Related_Endpoint);
+        }
+
+        if ((rEP >= pDev->TotalEndpoint) || (Status == 0) || (pInformation->CurrentConfiguration == 0))
+        {
+            return UnSupport;
+        }
+
+        if (wIndex0 & 0x80)
+        {
+            /* IN endpoint */
+            if (_GetTxStallStatus(Related_Endpoint))
+            {
+                USB_ClrDattogTx(Related_Endpoint);
+                SetEPTxStatus(Related_Endpoint, EP_TX_VALID);
+            }
+        }
+        else
+        {
+            /* OUT endpoint */
+            if (_GetRxStallStatus(Related_Endpoint))
+            {
+                if (Related_Endpoint == ENDP0)
+                {
+                    /* After clear the STALL, enable the default endpoint receiver */
+                    USB_SetEpRxCnt(Related_Endpoint, Device_Property.MaxPacketSize);
+                    _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+                }
+                else
+                {
+                    USB_ClrDattogRx(Related_Endpoint);
+                    _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+                }
+            }
+        }
+        pUser_Standard_Requests->User_ClearFeature();
+        return Success;
+    }
+
+    return UnSupport;
+}
+
+/**
+ * @brief Set or enable a specific feature of EndPoint
+ * @return - Return Success, if the request is performed.
+ *                  - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetEndPointFeature(void)
+{
+    uint32_t wIndex0;
+    uint32_t Related_Endpoint;
+    uint32_t rEP;
+    uint32_t Status;
+
+    wIndex0          = pInformation->USBwIndex0;
+    rEP              = wIndex0 & ~0x80;
+    Related_Endpoint = ENDP0 + rEP;
+
+    if (ValBit(pInformation->USBwIndex0, 7))
+    {
+        /* get Status of endpoint & stall the request if the related_ENdpoint
+        is Disabled*/
+        Status = _GetEPTxStatus(Related_Endpoint);
+    }
+    else
+    {
+        Status = _GetEPRxStatus(Related_Endpoint);
+    }
+
+    if (Related_Endpoint >= Device_Table.TotalEndpoint || pInformation->USBwValue != 0 || Status == 0
+        || pInformation->CurrentConfiguration == 0)
+    {
+        return UnSupport;
+    }
+    else
+    {
+        if (wIndex0 & 0x80)
+        {
+            /* IN endpoint */
+            _SetEPTxStatus(Related_Endpoint, EP_TX_STALL);
+        }
+
+        else
+        {
+            /* OUT endpoint */
+            _SetEPRxStatus(Related_Endpoint, EP_RX_STALL);
+        }
+    }
+    pUser_Standard_Requests->User_SetEndPointFeature();
+    return Success;
+}
+
+/**
+ * @brief Set or enable a specific feature of Device.
+ * @return - Return Success, if the request is performed.
+ *                  - Return UnSupport, if the request is invalid.
+ */
+USB_Result Standard_SetDeviceFeature(void)
+{
+    SetBit(pInformation->CurrentFeature, 5);
+    pUser_Standard_Requests->User_SetDeviceFeature();
+    return Success;
+}
+
+/**
+ * @brief Standard_GetDescriptorData is used for descriptors transfer.
+ *                : This routine is used for the descriptors resident in Flash
+ *                  or RAM
+ *                  pDesc can be in either Flash or RAM
+ *                  The purpose of this routine is to have a versatile way to
+ *                  response descriptors request. It allows user to generate
+ *                  certain descriptors with software or read descriptors from
+ *                  external storage part by part.
+ * @param  Length:  Length of the data in this transfer.
+ * @param  pDesc:   A pointer points to descriptor struct.
+ *                  The structure gives the initial address of the descriptor and
+ *                  its original size.
+ * @return Address of a part of the descriptor pointed by the Usb_
+ *                  wOffset The buffer pointed by this address contains at least
+ *                  Length bytes.
+ */
+uint8_t* Standard_GetDescriptorData(uint16_t Length, USB_OneDescriptor* pDesc)
+{
+    uint32_t wOffset;
+
+    wOffset = pInformation->Ctrl_Info.Usb_wOffset;
+    if (Length == 0)
+    {
+        pInformation->Ctrl_Info.Usb_wLength = pDesc->Descriptor_Size - wOffset;
+        return 0;
+    }
+
+    return pDesc->Descriptor + wOffset;
+}
+
+/**
+ * @brief Data stage of a Control Write Transfer.
+ */
+void DataStageOut(void)
+{
+    USB_EndpointMess* pEPinfo = &pInformation->Ctrl_Info;
+    uint32_t save_rLength;
+
+    save_rLength = pEPinfo->Usb_rLength;
+
+    if (pEPinfo->CopyData && save_rLength)
+    {
+        uint8_t* Buffer;
+        uint32_t Length;
+
+        Length = pEPinfo->PacketSize;
+        if (Length > save_rLength)
+        {
+            Length = save_rLength;
+        }
+
+        Buffer = (*pEPinfo->CopyData)(Length);
+        pEPinfo->Usb_rLength -= Length;
+        pEPinfo->Usb_rOffset += Length;
+
+        USB_CopyPMAToUserBuf(Buffer, USB_GetEpRxAddr(ENDP0), Length);
+    }
+
+    if (pEPinfo->Usb_rLength != 0)
+    {
+        vSetEPRxStatus(EP_RX_VALID); /* re-enable for next data reception */
+        USB_SetEpTxCnt(ENDP0, 0);
+        vSetEPTxStatus(EP_TX_VALID); /* Expect the host to abort the data OUT stage */
+    }
+    /* Set the next State*/
+    if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize)
+    {
+        pInformation->CtrlState = OutData;
+    }
+    else
+    {
+        if (pEPinfo->Usb_rLength > 0)
+        {
+            pInformation->CtrlState = LastOutData;
+        }
+        else if (pEPinfo->Usb_rLength == 0)
+        {
+            pInformation->CtrlState = WaitStatusIn;
+            USB_StatusIn();
+        }
+    }
+}
+
+/**
+ * @brief Data stage of a Control Read Transfer.
+ */
+void DataStageIn(void)
+{
+    USB_EndpointMess* pEPinfo = &pInformation->Ctrl_Info;
+    uint32_t save_wLength     = pEPinfo->Usb_wLength;
+    uint32_t CtrlState        = pInformation->CtrlState;
+
+    uint8_t* DataBuffer;
+    uint32_t Length;
+
+    if ((save_wLength == 0) && (CtrlState == LastInData))
+    {
+        if (Data_Mul_MaxPacketSize == true)
+        {
+            /* No more data to send and empty packet */
+            Send0LengthData();
+            CtrlState              = LastInData;
+            Data_Mul_MaxPacketSize = false;
+        }
+        else
+        {
+            /* No more data to send so STALL the TX Status*/
+            CtrlState = WaitStatusOut;
+            vSetEPTxStatus(EP_TX_STALL);
+        }
+
+        goto Expect_Status_Out;
+    }
+
+    Length    = pEPinfo->PacketSize;
+    CtrlState = (save_wLength <= Length) ? LastInData : InData;
+
+    if (Length > save_wLength)
+    {
+        Length = save_wLength;
+    }
+
+    DataBuffer = (*pEPinfo->CopyData)(Length);
+
+    USB_CopyUserToPMABuf(DataBuffer, USB_GetEpTxAddr(ENDP0), Length);
+
+    USB_SetEpTxCnt(ENDP0, Length);
+
+    pEPinfo->Usb_wLength -= Length;
+    pEPinfo->Usb_wOffset += Length;
+    vSetEPTxStatus(EP_TX_VALID);
+
+    USB_StatusOut(); /* Expect the host to abort the data IN stage */
+
+Expect_Status_Out:
+    pInformation->CtrlState = CtrlState;
+}
+
+/**
+ * @brief Proceed the processing of setup request without data stage.
+ */
+void NoData_Setup0(void)
+{
+    USB_Result Result  = UnSupport;
+    uint32_t RequestNo = pInformation->bRequest;
+    uint32_t CtrlState;
+
+    if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+    {
+        /* Device Request*/
+        /* SET_CONFIGURATION*/
+        if (RequestNo == SET_CONFIGURATION)
+        {
+            Result = Standard_SetConfiguration();
+        }
+
+        /*SET ADDRESS*/
+        else if (RequestNo == SET_ADDRESS)
+        {
+            if ((pInformation->USBwValue0 > 127) || (pInformation->USBwValue1 != 0) || (pInformation->USBwIndex != 0)
+                || (pInformation->CurrentConfiguration != 0))
+            /* Device Address should be 127 or less*/
+            {
+                CtrlState = Stalled;
+                goto exit_NoData_Setup0;
+            }
+            else
+            {
+                Result = Success;
+            }
+        }
+        /*SET FEATURE for Device*/
+        else if (RequestNo == SET_FEATURE)
+        {
+            if ((pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP) && (pInformation->USBwIndex == 0))
+            {
+                Result = Standard_SetDeviceFeature();
+            }
+            else
+            {
+                Result = UnSupport;
+            }
+        }
+        /*Clear FEATURE for Device */
+        else if (RequestNo == CLR_FEATURE)
+        {
+            if (pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP && pInformation->USBwIndex == 0
+                && ValBit(pInformation->CurrentFeature, 5))
+            {
+                Result = Standard_ClearFeature();
+            }
+            else
+            {
+                Result = UnSupport;
+            }
+        }
+    }
+
+    /* Interface Request*/
+    else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+    {
+        /*SET INTERFACE*/
+        if (RequestNo == SET_INTERFACE)
+        {
+            Result = Standard_SetInterface();
+        }
+    }
+
+    /* EndPoint Request*/
+    else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+    {
+        /*CLEAR FEATURE for EndPoint*/
+        if (RequestNo == CLR_FEATURE)
+        {
+            Result = Standard_ClearFeature();
+        }
+        /* SET FEATURE for EndPoint*/
+        else if (RequestNo == SET_FEATURE)
+        {
+            Result = Standard_SetEndPointFeature();
+        }
+    }
+    else
+    {
+        Result = UnSupport;
+    }
+
+    if (Result != Success)
+    {
+        Result = (*pProperty->Class_NoData_Setup)(RequestNo);
+        if (Result == Not_Ready)
+        {
+            CtrlState = Pause;
+            goto exit_NoData_Setup0;
+        }
+    }
+
+    if (Result != Success)
+    {
+        CtrlState = Stalled;
+        goto exit_NoData_Setup0;
+    }
+
+    CtrlState = WaitStatusIn; /* After no data stage SETUP */
+
+    USB_StatusIn();
+
+exit_NoData_Setup0:
+    pInformation->CtrlState = CtrlState;
+    return;
+}
+
+/**
+ * @brief Proceed the processing of setup request with data stage.
+ */
+void Data_Setup0(void)
+{
+    uint8_t* (*CopyRoutine)(uint16_t);
+    USB_Result Result;
+    uint32_t Request_No = pInformation->bRequest;
+
+    uint32_t Related_Endpoint, Reserved;
+    uint32_t wOffset, Status;
+
+    CopyRoutine = NULL;
+    wOffset     = 0;
+
+    /*GET DESCRIPTOR*/
+    if (Request_No == GET_DESCRIPTOR)
+    {
+        if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+        {
+            uint8_t wValue1 = pInformation->USBwValue1;
+            if (wValue1 == DEVICE_DESCRIPTOR)
+            {
+                CopyRoutine = pProperty->GetDeviceDescriptor;
+            }
+            else if (wValue1 == CONFIG_DESCRIPTOR)
+            {
+                CopyRoutine = pProperty->GetConfigDescriptor;
+            }
+            else if (wValue1 == STRING_DESCRIPTOR)
+            {
+                CopyRoutine = pProperty->GetStringDescriptor;
+            } /* End of GET_DESCRIPTOR */
+        }
+    }
+
+    /*GET STATUS*/
+    else if ((Request_No == GET_STATUS) && (pInformation->USBwValue == 0) && (pInformation->USBwLength == 0x0002)
+             && (pInformation->USBwIndex1 == 0))
+    {
+        /* GET STATUS for Device*/
+        if ((Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) && (pInformation->USBwIndex == 0))
+        {
+            CopyRoutine = Standard_GetStatus;
+        }
+
+        /* GET STATUS for Interface*/
+        else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+        {
+            if (((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == Success)
+                && (pInformation->CurrentConfiguration != 0))
+            {
+                CopyRoutine = Standard_GetStatus;
+            }
+        }
+
+        /* GET STATUS for EndPoint*/
+        else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+        {
+            Related_Endpoint = (pInformation->USBwIndex0 & 0x0f);
+            Reserved         = pInformation->USBwIndex0 & 0x70;
+
+            if (ValBit(pInformation->USBwIndex0, 7))
+            {
+                /*Get Status of endpoint & stall the request if the related_ENdpoint
+                is Disabled*/
+                Status = _GetEPTxStatus(Related_Endpoint);
+            }
+            else
+            {
+                Status = _GetEPRxStatus(Related_Endpoint);
+            }
+
+            if ((Related_Endpoint < Device_Table.TotalEndpoint) && (Reserved == 0) && (Status != 0))
+            {
+                CopyRoutine = Standard_GetStatus;
+            }
+        }
+    }
+
+    /*GET CONFIGURATION*/
+    else if (Request_No == GET_CONFIGURATION)
+    {
+        if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+        {
+            CopyRoutine = Standard_GetConfiguration;
+        }
+    }
+    /*GET INTERFACE*/
+    else if (Request_No == GET_INTERFACE)
+    {
+        if ((Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) && (pInformation->CurrentConfiguration != 0)
+            && (pInformation->USBwValue == 0) && (pInformation->USBwIndex1 == 0) && (pInformation->USBwLength == 0x0001)
+            && ((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == Success))
+        {
+            CopyRoutine = Standard_GetInterface;
+        }
+    }
+
+    if (CopyRoutine)
+    {
+        pInformation->Ctrl_Info.Usb_wOffset = wOffset;
+        pInformation->Ctrl_Info.CopyData    = CopyRoutine;
+        /* sb in the original the cast to word was directly */
+        /* now the cast is made step by step */
+        (*CopyRoutine)(0);
+        Result = Success;
+    }
+    else
+    {
+        Result = (*pProperty->Class_Data_Setup)(pInformation->bRequest);
+        if (Result == Not_Ready)
+        {
+            pInformation->CtrlState = Pause;
+            return;
+        }
+    }
+
+    if (pInformation->Ctrl_Info.Usb_wLength == 0xFFFF)
+    {
+        /* Data is not ready, wait it */
+        pInformation->CtrlState = Pause;
+        return;
+    }
+    if ((Result == UnSupport) || (pInformation->Ctrl_Info.Usb_wLength == 0))
+    {
+        /* Unsupported request */
+        pInformation->CtrlState = Stalled;
+        return;
+    }
+
+    if (ValBit(pInformation->bmRequestType, 7))
+    {
+        /* Device ==> Host */
+        __IO uint32_t wLength = pInformation->USBwLength;
+
+        /* Restrict the data length to be the one host asks for */
+        if (pInformation->Ctrl_Info.Usb_wLength > wLength)
+        {
+            pInformation->Ctrl_Info.Usb_wLength = wLength;
+        }
+
+        else if (pInformation->Ctrl_Info.Usb_wLength < pInformation->USBwLength)
+        {
+            if (pInformation->Ctrl_Info.Usb_wLength < pProperty->MaxPacketSize)
+            {
+                Data_Mul_MaxPacketSize = false;
+            }
+            else if ((pInformation->Ctrl_Info.Usb_wLength % pProperty->MaxPacketSize) == 0)
+            {
+                Data_Mul_MaxPacketSize = true;
+            }
+        }
+
+        pInformation->Ctrl_Info.PacketSize = pProperty->MaxPacketSize;
+        DataStageIn();
+    }
+    else
+    {
+        pInformation->CtrlState = OutData;
+        vSetEPRxStatus(EP_RX_VALID); /* enable for next data reception */
+    }
+
+    return;
+}
+
+/**
+ * @brief Get the device request data and dispatch to individual process.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessSetup0(void)
+{
+    union
+    {
+        uint8_t* b;
+        uint16_t* w;
+    } pBuf;
+
+    uint16_t offset = 1;
+
+    pBuf.b = PMAAddr + (uint8_t*)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */
+
+    if (pInformation->CtrlState != Pause)
+    {
+        pInformation->bmRequestType = *pBuf.b++;           /* bmRequestType */
+        pInformation->bRequest      = *pBuf.b++;           /* bRequest */
+        pBuf.w += offset;                                  /* word not accessed because of 32 bits addressing */
+        pInformation->USBwValue = USB_ByteSwap(*pBuf.w++); /* wValue */
+        pBuf.w += offset;                                  /* word not accessed because of 32 bits addressing */
+        pInformation->USBwIndex = USB_ByteSwap(*pBuf.w++); /* wIndex */
+        pBuf.w += offset;                                  /* word not accessed because of 32 bits addressing */
+        pInformation->USBwLength = *pBuf.w;                /* wLength */
+    }
+
+    pInformation->CtrlState = SettingUp;
+    if (pInformation->USBwLength == 0)
+    {
+        /* Setup with no data stage */
+        NoData_Setup0();
+    }
+    else
+    {
+        /* Setup with data stage */
+        Data_Setup0();
+    }
+    return USB_ProcessPost0();
+}
+
+/**
+ * @brief Process the IN token on all default endpoint.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessIn0(void)
+{
+    uint32_t CtrlState = pInformation->CtrlState;
+
+    if ((CtrlState == InData) || (CtrlState == LastInData))
+    {
+        DataStageIn();
+        /* CtrlState may be changed outside the function */
+        CtrlState = pInformation->CtrlState;
+    }
+
+    else if (CtrlState == WaitStatusIn)
+    {
+        if ((pInformation->bRequest == SET_ADDRESS) && (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)))
+        {
+            USB_SetDeviceAddress(pInformation->USBwValue0);
+            pUser_Standard_Requests->User_SetDeviceAddress();
+        }
+        (*pProperty->Process_Status_IN)();
+        CtrlState = Stalled;
+    }
+
+    else
+    {
+        CtrlState = Stalled;
+    }
+
+    pInformation->CtrlState = CtrlState;
+
+    return USB_ProcessPost0();
+}
+
+/**
+ * @brief Process the OUT token on all default endpoint.
+ * @return USB_ProcessPost0.
+ */
+uint8_t USB_ProcessOut0(void)
+{
+    uint32_t CtrlState = pInformation->CtrlState;
+
+    if ((CtrlState == InData) || (CtrlState == LastInData))
+    {
+        /* host aborts the transfer before finish */
+        CtrlState = Stalled;
+    }
+    else if ((CtrlState == OutData) || (CtrlState == LastOutData))
+    {
+        DataStageOut();
+        CtrlState = pInformation->CtrlState; /* may be changed outside the function */
+    }
+
+    else if (CtrlState == WaitStatusOut)
+    {
+        (*pProperty->Process_Status_OUT)();
+        CtrlState = Stalled;
+    }
+
+    /* Unexpect state, STALL the endpoint */
+    else
+    {
+        CtrlState = Stalled;
+    }
+
+    pInformation->CtrlState = CtrlState;
+
+    return USB_ProcessPost0();
+}
+
+/**
+ * @brief Stall the Endpoint 0 in case of error.
+ * @return
+ * - 0 if the control State is in Pause
+ * - 1 if not.
+ */
+uint8_t USB_ProcessPost0(void)
+{
+    USB_SetEpRxCnt(ENDP0, Device_Property.MaxPacketSize);
+
+    if (pInformation->CtrlState == Stalled)
+    {
+        vSetEPRxStatus(EP_RX_STALL);
+        vSetEPTxStatus(EP_TX_STALL);
+    }
+    return (pInformation->CtrlState == Pause);
+}
+
+/**
+ * @brief Set the device and all the used Endpoints addresses.
+ * @param Val device address.
+ */
+void USB_SetDeviceAddress(uint8_t Val)
+{
+    uint32_t i;
+    uint32_t nEP = Device_Table.TotalEndpoint;
+
+    /* set address in every used endpoint */
+    for (i = 0; i < nEP; i++)
+    {
+        _SetEPAddress((uint8_t)i, (uint8_t)i);
+    }                           /* for */
+    _SetDADDR(Val | ADDR_EFUC); /* set device address and enable function */
+}
+
+/**
+ * @brief No operation function.
+ */
+void USB_ProcessNop(void)
+{
+}

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_init.c

@@ -0,0 +1,71 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_init.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/*  The number of current endpoint, it will be used to specify an endpoint */
+uint8_t EPindex;
+/*  The number of current device, it is an index to the Device_Table */
+/* uint8_t Device_no; */
+/*  Points to the USB_DeviceMess structure of current device */
+/*  The purpose of this register is to speed up the execution */
+USB_DeviceMess* pInformation;
+/*  Points to the DEVICE_PROP structure of current device */
+/*  The purpose of this register is to speed up the execution */
+DEVICE_PROP* pProperty;
+/*  Temporary save the state of Rx & Tx status. */
+/*  Whenever the Rx or Tx state is changed, its value is saved */
+/*  in this variable first and will be set to the EPRB or EPRA */
+/*  at the end of interrupt process */
+uint16_t SaveState;
+uint16_t wInterrupt_Mask;
+USB_DeviceMess Device_Info;
+USER_STANDARD_REQUESTS* pUser_Standard_Requests;
+
+/**
+ * @brief USB system initialization
+ */
+void USB_Init(void)
+{
+    pInformation            = &Device_Info;
+    pInformation->CtrlState = 2;
+    pProperty               = &Device_Property;
+    pUser_Standard_Requests = &User_Standard_Requests;
+    /* Initialize devices one by one */
+    pProperty->Init();
+    /*Pull up DP*/
+//    _ClrDPCtrl();
+    _EnPortPullup();
+//    printf("DP_CTRL=%x\r\n", (*DP_CTRL));
+}

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_int.c

@@ -0,0 +1,179 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_int.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+__IO uint16_t SaveRState;
+__IO uint16_t SaveTState;
+
+extern void (*pEpInt_IN[7])(void);  /*  Handles IN  interrupts   */
+extern void (*pEpInt_OUT[7])(void); /*  Handles OUT interrupts   */
+
+/**
+ * @brief Low priority Endpoint Correct Transfer interrupt's service routine.
+ */
+void USB_CorrectTransferLp(void)
+{
+    __IO uint16_t wEPVal = 0;
+    /* stay in loop while pending interrupts */
+    while (((wIstr = _GetISTR()) & STS_CTRS) != 0)
+    {
+        /* extract highest priority endpoint number */
+        EPindex = (uint8_t)(wIstr & STS_EP_ID);
+        if (EPindex == 0)
+        {
+            /* Decode and service control endpoint interrupt */
+            /* calling related service routine */
+            /* (USB_ProcessSetup0, USB_ProcessIn0, USB_ProcessOut0) */
+
+            /* save RX & TX status */
+            /* and set both to NAK */
+
+            SaveRState = _GetENDPOINT(ENDP0);
+            SaveTState = SaveRState & EPTX_STS;
+            SaveRState &= EPRX_STS;
+            _SetEPRxTxStatus(ENDP0, EP_RX_NAK, EP_TX_NAK);
+
+            /* DIR bit = origin of the interrupt */
+
+            if ((wIstr & STS_DIR) == 0)
+            {
+                /* DIR = 0 */
+
+                /* DIR = 0      => IN  int */
+                /* DIR = 0 implies that (EP_CTRS_TX = 1) always  */
+
+                _ClearEP_CTR_TX(ENDP0);
+                USB_ProcessIn0();
+
+                /* before terminate set Tx & Rx status */
+
+                _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+                return;
+            }
+            else
+            {
+                /* DIR = 1 */
+
+                /* DIR = 1 & CTR_RX       => SETUP or OUT int */
+                /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+
+                wEPVal = _GetENDPOINT(ENDP0);
+
+                if ((wEPVal & EP_SETUP) != 0)
+                {
+                    _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */
+                    USB_ProcessSetup0();
+                    /* before terminate set Tx & Rx status */
+
+                    _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+                    return;
+                }
+
+                else if ((wEPVal & EP_CTRS_RX) != 0)
+                {
+                    _ClearEP_CTR_RX(ENDP0);
+                    USB_ProcessOut0();
+                    /* before terminate set Tx & Rx status */
+
+                    _SetEPRxTxStatus(ENDP0, SaveRState, SaveTState);
+                    return;
+                }
+            }
+        } /* if (EPindex == 0) */
+        else
+        {
+            /* Decode and service non control endpoints interrupt  */
+
+            /* process related endpoint register */
+            wEPVal = _GetENDPOINT(EPindex);
+            if ((wEPVal & EP_CTRS_RX) != 0)
+            {
+                /* clear int flag */
+                _ClearEP_CTR_RX(EPindex);
+
+                /* call OUT service function */
+                (*pEpInt_OUT[EPindex - 1])();
+
+            } /* if ((wEPVal & EP_CTRS_RX) */
+
+            if ((wEPVal & EP_CTRS_TX) != 0)
+            {
+                /* clear int flag */
+                _ClearEP_CTR_TX(EPindex);
+
+                /* call IN service function */
+                (*pEpInt_IN[EPindex - 1])();
+            } /* if ((wEPVal & EP_CTRS_TX) != 0) */
+
+        } /* if (EPindex == 0) else */
+
+    } /* while (...) */
+}
+
+/**
+ * @brief High Priority Endpoint Correct Transfer interrupt's service routine.
+ */
+void USB_CorrectTransferHp(void)
+{
+    uint32_t wEPVal = 0;
+
+    while (((wIstr = _GetISTR()) & STS_CTRS) != 0)
+    {
+        _SetISTR((uint16_t)CLR_CTRS); /* clear CTR flag */
+        /* extract highest priority endpoint number */
+        EPindex = (uint8_t)(wIstr & STS_EP_ID);
+        /* process related endpoint register */
+        wEPVal = _GetENDPOINT(EPindex);
+        if ((wEPVal & EP_CTRS_RX) != 0)
+        {
+            /* clear int flag */
+            _ClearEP_CTR_RX(EPindex);
+
+            /* call OUT service function */
+            (*pEpInt_OUT[EPindex - 1])();
+
+        } /* if ((wEPVal & EP_CTRS_RX) */
+        else if ((wEPVal & EP_CTRS_TX) != 0)
+        {
+            /* clear int flag */
+            _ClearEP_CTR_TX(EPindex);
+
+            /* call IN service function */
+            (*pEpInt_IN[EPindex - 1])();
+
+        } /* if ((wEPVal & EP_CTRS_TX) != 0) */
+
+    } /* while (...) */
+}

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_mem.c

@@ -0,0 +1,81 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_mem.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+u8* EpOutDataPtrTmp;
+u8* EpInDataPtrTmp;
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes no. of bytes to be copied.
+ */
+void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+    uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */
+    uint32_t i, temp1, temp2;
+    uint16_t* pdwVal;
+    pdwVal = (uint16_t*)(wPMABufAddr * 2 + PMAAddr);
+    for (i = n; i != 0; i--)
+    {
+        temp1 = (uint16_t)*pbUsrBuf;
+        pbUsrBuf++;
+        temp2     = temp1 | (uint16_t)*pbUsrBuf << 8;
+        *pdwVal++ = temp2;
+        pdwVal++;
+        pbUsrBuf++;
+        EpInDataPtrTmp = pbUsrBuf;
+    }
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param pbUsrBuf    pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes     no. of bytes to be copied.
+ */
+void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+    uint32_t n = (wNBytes + 1) >> 1; /* /2*/
+    uint32_t i;
+    uint32_t* pdwVal;
+    pdwVal = (uint32_t*)(wPMABufAddr * 2 + PMAAddr);
+    for (i = n; i != 0; i--)
+    {
+        *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+        pbUsrBuf++;
+        EpOutDataPtrTmp = pbUsrBuf;
+    }
+}

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_regs.c

@@ -0,0 +1,598 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_regs.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/**
+ * @brief Set the CTRL register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetCtrl(uint16_t wRegValue)
+{
+    _SetCNTR(wRegValue);
+}
+
+/**
+ * @brief returns the CTRL register value.
+ * @return CTRL register Value.
+ */
+uint16_t USB_GetCtrl(void)
+{
+    return (_GetCNTR());
+}
+
+/**
+ * @brief Set the STS register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetSts(uint16_t wRegValue)
+{
+    _SetISTR(wRegValue);
+}
+
+/**
+ * @brief Returns the STS register value.
+ * @return STS register Value
+ */
+uint16_t USB_GetSts(void)
+{
+    return (_GetISTR());
+}
+
+/**
+ * @brief Returns the FN register value.
+ * @return FN register Value
+ */
+uint16_t USB_GetFn(void)
+{
+    return (_GetFNR());
+}
+
+/**
+ * @brief Set the ADDR register value.
+ * @param wRegValue new register value.
+ */
+void USB_SetAddr(uint16_t wRegValue)
+{
+    _SetDADDR(wRegValue);
+}
+
+/**
+ * @brief Returns the ADDR register value.
+ * @return ADDR register Value
+ */
+uint16_t USB_GetAddr(void)
+{
+    return (_GetDADDR());
+}
+
+/**
+ * @brief Set the BUFTAB.
+ * @param wRegValue New register value.
+ */
+void USB_SetBuftab(uint16_t wRegValue)
+{
+    _SetBTABLE(wRegValue);
+}
+
+/**
+ * @brief Returns the BUFTAB register value.
+ * @return BUFTAB address.
+ */
+uint16_t USB_GetBTABLE(void)
+{
+    return (_GetBTABLE());
+}
+
+/**
+ * @brief Set the Endpoint register value.
+ * @param bEpNum Endpoint Number.
+ * @param wRegValue New register value.
+ */
+void USB_SetEndPoint(uint8_t bEpNum, uint16_t wRegValue)
+{
+    _SetENDPOINT(bEpNum, wRegValue);
+}
+
+/**
+ * @brief Return the Endpoint register value.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint register value.
+ */
+uint16_t USB_GetEndPoint(uint8_t bEpNum)
+{
+    return (_GetENDPOINT(bEpNum));
+}
+
+/**
+ * @brief sets the type in the endpoint register.
+ * @param bEpNum Endpoint Number.
+ * @param wType type definition.
+ */
+void USB_SetEpType(uint8_t bEpNum, uint16_t wType)
+{
+    _SetEPType(bEpNum, wType);
+}
+
+/**
+ * @brief Returns the endpoint type.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Type
+ */
+uint16_t USB_GetEpType(uint8_t bEpNum)
+{
+    return (_GetEPType(bEpNum));
+}
+
+/**
+ * @brief Set the status of Tx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state.
+ */
+void SetEPTxStatus(uint8_t bEpNum, uint16_t wState)
+{
+    _SetEPTxStatus(bEpNum, wState);
+}
+
+/**
+ * @brief Set the status of Rx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @param wState new state.
+ */
+void SetEPRxStatus(uint8_t bEpNum, uint16_t wState)
+{
+    _SetEPRxStatus(bEpNum, wState);
+}
+
+/**
+ * @brief sets the status for Double Buffer Endpoint to STALL
+ * @param bEpNum Endpoint Number.
+ * @param bDir Endpoint direction.
+ */
+void USB_SetDouBleBuferEpStall(uint8_t bEpNum, uint8_t bDir)
+{
+    uint16_t Endpoint_DTOG_Status;
+    Endpoint_DTOG_Status = USB_GetEndPoint(bEpNum);
+    if (bDir == EP_DBUF_OUT)
+    { /* OUT double buffered endpoint */
+        _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPRX_DATTOG1);
+    }
+    else if (bDir == EP_DBUF_IN)
+    { /* IN double buffered endpoint */
+        _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPTX_DATTOG1);
+    }
+}
+
+/**
+ * @brief Returns the endpoint Tx status.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint TX Status
+ */
+uint16_t USB_GetEpTxSts(uint8_t bEpNum)
+{
+    return (_GetEPTxStatus(bEpNum));
+}
+
+/**
+ * @brief Returns the endpoint Rx status.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint RX Status
+ */
+uint16_t USB_GetEpRxSts(uint8_t bEpNum)
+{
+    return (_GetEPRxStatus(bEpNum));
+}
+
+/**
+ * @brief Valid the endpoint Tx Status.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpTxValid(uint8_t bEpNum)
+{
+    _SetEPTxStatus(bEpNum, EP_TX_VALID);
+}
+
+/**
+ * @brief Valid the endpoint Rx Status.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpRxValid(uint8_t bEpNum)
+{
+    _SetEPRxStatus(bEpNum, EP_RX_VALID);
+}
+
+/**
+ * @brief Clear the EP_KIND bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpKind(uint8_t bEpNum)
+{
+    _SetEP_KIND(bEpNum);
+}
+
+/**
+ * @brief set the  EP_KIND bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpKind(uint8_t bEpNum)
+{
+    _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Clear the Status Out of the related Endpoint
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrStsOut(uint8_t bEpNum)
+{
+    _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Set the Status Out of the related Endpoint
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetStsOut(uint8_t bEpNum)
+{
+    _SetEP_KIND(bEpNum);
+}
+/**
+ * @brief Enable the double buffer feature for the endpoint.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_SetEpDoubleBufer(uint8_t bEpNum)
+{
+    _SetEP_KIND(bEpNum);
+}
+/**
+ * @brief Disable the double buffer feature for the endpoint.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpDoubleBufer(uint8_t bEpNum)
+{
+    _ClearEP_KIND(bEpNum);
+}
+/**
+ * @brief Returns the Stall status of the Tx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Tx Stall status.
+ */
+uint16_t USB_GetTxStallSts(uint8_t bEpNum)
+{
+    return (_GetTxStallStatus(bEpNum));
+}
+/**
+ * @brief Returns the Stall status of the Rx endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Rx Stall status.
+ */
+uint16_t USB_GetRxStallSts(uint8_t bEpNum)
+{
+    return (_GetRxStallStatus(bEpNum));
+}
+/**
+ * @brief Clear the CTR_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpCtrsRx(uint8_t bEpNum)
+{
+    _ClearEP_CTR_RX(bEpNum);
+}
+/**
+ * @brief Clear the CTR_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrEpCtrsTx(uint8_t bEpNum)
+{
+    _ClearEP_CTR_TX(bEpNum);
+}
+/**
+ * @brief Toggle the DTOG_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_DattogRx(uint8_t bEpNum)
+{
+    _ToggleDTOG_RX(bEpNum);
+}
+/**
+ * @brief Toggle the DTOG_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_DattogTx(uint8_t bEpNum)
+{
+    _ToggleDTOG_TX(bEpNum);
+}
+/**
+ * @brief Clear the DTOG_RX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrDattogRx(uint8_t bEpNum)
+{
+    _ClearDTOG_RX(bEpNum);
+}
+/**
+ * @brief Clear the DTOG_TX bit.
+ * @param bEpNum Endpoint Number.
+ */
+void USB_ClrDattogTx(uint8_t bEpNum)
+{
+    _ClearDTOG_TX(bEpNum);
+}
+/**
+ * @brief Set the endpoint address.
+ * @param bEpNum Endpoint Number.
+ * @param bAddr New endpoint address.
+ */
+void USB_SetEpAddress(uint8_t bEpNum, uint8_t bAddr)
+{
+    _SetEPAddress(bEpNum, bAddr);
+}
+/**
+ * @brief Get the endpoint address.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint address.
+ */
+uint8_t USB_GetEpAddress(uint8_t bEpNum)
+{
+    return (_GetEPAddress(bEpNum));
+}
+/**
+ * @brief Set the endpoint Tx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @param wAddr new address.
+ */
+void USB_SetEpTxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+    _SetEPTxAddr(bEpNum, wAddr);
+}
+/**
+ * @brief Set the endpoint Rx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @param wAddr new address.
+ */
+void USB_SetEpRxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+    _SetEPRxAddr(bEpNum, wAddr);
+}
+/**
+ * @brief Returns the endpoint Tx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @return Rx buffer address.
+ */
+uint16_t USB_GetEpTxAddr(uint8_t bEpNum)
+{
+    return (_GetEPTxAddr(bEpNum));
+}
+/**
+ * @brief Returns the endpoint Rx buffer address.
+ * @param bEpNum Endpoint Number.
+ * @return Rx buffer address.
+ */
+uint16_t USB_GetEpRxAddr(uint8_t bEpNum)
+{
+    return (_GetEPRxAddr(bEpNum));
+}
+/**
+ * @brief Set the Tx count.
+ * @param bEpNum Endpoint Number.
+ * @param wCount new count value.
+ */
+void USB_SetEpTxCnt(uint8_t bEpNum, uint16_t wCount)
+{
+    _SetEPTxCount(bEpNum, wCount);
+}
+/**
+ * @brief Set the Count Rx Register value.
+ * @param pdwReg point to the register.
+ * @param wCount the new register value.
+ */
+void USB_SetEpCntRxReg(uint32_t* pdwReg, uint16_t wCount)
+{
+    _SetEPCountRxReg(dwReg, wCount);
+}
+/**
+ * @brief Set the Rx count.
+ * @param bEpNum Endpoint Number.
+ * @param wCount the new count value.
+ */
+void USB_SetEpRxCnt(uint8_t bEpNum, uint16_t wCount)
+{
+    _SetEPRxCount(bEpNum, wCount);
+}
+/**
+ * @brief Get the Tx count.
+ * @param bEpNum Endpoint Number.
+ * @return Tx count value.
+ */
+uint16_t USB_GetEpTxCnt(uint8_t bEpNum)
+{
+    return (_GetEPTxCount(bEpNum));
+}
+/**
+ * @brief Get the Rx count.
+ * @param bEpNum Endpoint Number.
+ * @return Rx count value.
+ */
+uint16_t USB_GetEpRxCnt(uint8_t bEpNum)
+{
+    return (_GetEPRxCount(bEpNum));
+}
+/**
+ * @brief Set the addresses of the buffer 0 and 1.
+ * @param bEpNum Endpoint Number.
+ * @param wBuf0Addr new address of buffer 0.
+ * @param wBuf1Addr new address of buffer 1.
+ */
+void USB_SetEpDblBuferAddr(uint8_t bEpNum, uint16_t wBuf0Addr, uint16_t wBuf1Addr)
+{
+    _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr);
+}
+/**
+ * @brief Set the Buffer 1 address.
+ * @param bEpNum Endpoint Number
+ * @param wBuf0Addr new address.
+ */
+void USB_SetEpDblBuf0Addr(uint8_t bEpNum, uint16_t wBuf0Addr)
+{
+    _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);
+}
+/**
+ * @brief Set the Buffer 1 address.
+ * @param bEpNum Endpoint Number
+ * @param wBuf1Addr new address.
+ */
+void USB_SetEpDblBuf1Addr(uint8_t bEpNum, uint16_t wBuf1Addr)
+{
+    _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);
+}
+/**
+ * @brief Returns the address of the Buffer 0.
+ * @param bEpNum Endpoint Number.
+ */
+uint16_t USB_GetEpDblBuf0Addr(uint8_t bEpNum)
+{
+    return (_GetEPDblBuf0Addr(bEpNum));
+}
+/**
+ * @brief Returns the address of the Buffer 1.
+ * @param bEpNum Endpoint Number.
+ * @return Address of the Buffer 1.
+ */
+uint16_t USB_GetEpDblBuf1Addr(uint8_t bEpNum)
+{
+    return (_GetEPDblBuf1Addr(bEpNum));
+}
+/**
+ * @brief Set the number of bytes for a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuferCnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+    _SetEPDblBuffCount(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuf0Cnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+    _SetEPDblBuf0Count(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum
+ * @param bDir
+ * @param wCount
+ */
+void USB_SetEpDblBuf1Cnt(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+    _SetEPDblBuf1Count(bEpNum, bDir, wCount);
+}
+/**
+ * @brief Returns the number of byte received in the buffer 0 of a double Buffer endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Buffer 0 count
+ */
+uint16_t USB_GetEpDblBuf0Cnt(uint8_t bEpNum)
+{
+    return (_GetEPDblBuf0Count(bEpNum));
+}
+/**
+ * @brief Returns the number of data received in the buffer 1 of a double Buffer endpoint.
+ * @param bEpNum Endpoint Number.
+ * @return Endpoint Buffer 1 count.
+ */
+uint16_t USB_GetEpDblBuf1Cnt(uint8_t bEpNum)
+{
+    return (_GetEPDblBuf1Count(bEpNum));
+}
+/**
+ * @brief gets direction of the double buffered endpoint
+ * @param bEpNum Endpoint Number.
+ * @return EP_DBUF_OUT, EP_DBUF_IN, EP_DBUF_ERR if the endpoint counter not yet programmed.
+ */
+EP_DBUF_DIR GetEPDblBufDir(uint8_t bEpNum)
+{
+    if ((uint16_t)(*_pEPRxCount(bEpNum) & 0xFC00) != 0)
+        return (EP_DBUF_OUT);
+    else if (((uint16_t)(*_pEPTxCount(bEpNum)) & 0x03FF) != 0)
+        return (EP_DBUF_IN);
+    else
+        return (EP_DBUF_ERR);
+}
+/**
+ * @brief free buffer used from the application realizing it to the line toggles
+ * bit SW_BUF in the double buffered endpoint register
+ * @param bEpNum
+ * @param bDir
+ */
+void USB_FreeUserBuf(uint8_t bEpNum, uint8_t bDir)
+{
+    if (bDir == EP_DBUF_OUT)
+    { /* OUT double buffered endpoint */
+        _ToggleDTOG_TX(bEpNum);
+    }
+    else if (bDir == EP_DBUF_IN)
+    { /* IN double buffered endpoint */
+        _ToggleDTOG_RX(bEpNum);
+    }
+}
+
+/**
+ * @brief merge two byte in a word.
+ * @param bh byte high
+ * @param bl bytes low.
+ * @return resulted word.
+ */
+uint16_t USB_ToWord(uint8_t bh, uint8_t bl)
+{
+    uint16_t wRet;
+    wRet = (uint16_t)bl | ((uint16_t)bh << 8);
+    return (wRet);
+}
+/**
+ * @brief Swap two byte in a word.
+ * @param wSwW word to Swap.
+ * @return resulted word.
+ */
+uint16_t USB_ByteSwap(uint16_t wSwW)
+{
+    uint8_t bTemp;
+    uint16_t wRet;
+    bTemp = (uint8_t)(wSwW & 0xff);
+    wRet  = (wSwW >> 8) | ((uint16_t)bTemp << 8);
+    return (wRet);
+}

bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_sil.c

@@ -0,0 +1,83 @@
+/*****************************************************************************
+ * Copyright (c) 2022, Nations Technologies Inc.
+ *
+ * All rights reserved.
+ * ****************************************************************************
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Nations' name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ****************************************************************************/
+
+/**
+ * @file usb_sil.c
+ * @author Nations
+ * @version v1.2.0
+ *
+ * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
+ */
+#include "usb_lib.h"
+
+/**
+ * @brief Initialize the USB Device IP and the Endpoint 0.
+ * @return Status.
+ */
+uint32_t USB_SilInit(void)
+{
+    /* USB interrupts initialization */
+    /* clear pending interrupts */
+    _SetISTR(0);
+    wInterrupt_Mask = IMR_MSK;
+    /* set interrupts mask */
+    _SetCNTR(wInterrupt_Mask);
+    return 0;
+}
+
+/**
+ * @brief Write a buffer of data to a selected endpoint.
+ * @param bEpAddr The address of the non control endpoint.
+ * @param pBufferPointer The pointer to the buffer of data to be written to the endpoint.
+ * @param wBufferSize Number of data to be written (in bytes).
+ * @return Status.
+ */
+uint32_t USB_SilWrite(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize)
+{
+    /* Use the memory interface function to write to the selected endpoint */
+    USB_CopyUserToPMABuf(pBufferPointer, USB_GetEpTxAddr(bEpAddr & 0x7F), wBufferSize);
+    /* Update the data length in the control register */
+    USB_SetEpTxCnt((bEpAddr & 0x7F), wBufferSize);
+    return 0;
+}
+
+/**
+ * @brief Write a buffer of data to a selected endpoint.
+ * @param bEpAddr The address of the non control endpoint.
+ * @param pBufferPointer The pointer to which will be saved the received data buffer.
+ * @return Number of received data (in Bytes).
+ */
+uint32_t USB_SilRead(uint8_t bEpAddr, uint8_t* pBufferPointer)
+{
+    uint32_t DataLength = 0;
+    /* Get the number of received data on the selected Endpoint */
+    DataLength = USB_GetEpRxCnt(bEpAddr & 0x7F);
+    /* Use the memory interface function to write to the selected endpoint */
+    USB_CopyPMAToUserBuf(pBufferPointer, USB_GetEpRxAddr(bEpAddr & 0x7F), DataLength);
+    /* Return the number of received data */
+    return DataLength;
+}

bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_math.h

@@ -77,7 +77,7 @@
    * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
    * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
    * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
-   * 
+   *
    *
    * Examples
    * --------

bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armcc.h

@@ -58,9 +58,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static __inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   static __forceinline
-#endif           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __declspec(noreturn)
 #endif
@@ -443,7 +443,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
                    __schedule_barrier();\
                 } while (0U)
 
-                  
+
 /**
   \brief   Reverse byte order (32 bit)
   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armclang.h

@@ -43,9 +43,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static __inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
-#endif                                           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __attribute__((__noreturn__))
 #endif
@@ -570,7 +570,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always in non-secure
   mode.
-  
+
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
  */
@@ -616,7 +616,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence the write is silently ignored in non-secure
   mode.
-  
+
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */

bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_gcc.h

@@ -46,9 +46,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
-#endif                                           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __attribute__((__noreturn__))
 #endif
@@ -585,7 +585,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always in non-secure
   mode.
-  
+
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
  */
@@ -630,7 +630,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence the write is silently ignored in non-secure
   mode.
-  
+
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */
@@ -767,7 +767,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_get_fpscr) 
+#if __has_builtin(__builtin_arm_get_fpscr)
 // Re-enable using built-in when GCC has been fixed
 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/mpu_armv7.h

@@ -21,13 +21,13 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
- 
+
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
   #pragma clang system_header    /* treat file as system include file */
 #endif
- 
+
 #ifndef ARM_MPU_ARMV7_H
 #define ARM_MPU_ARMV7_H
 
@@ -79,12 +79,12 @@
 
 /**
 * MPU Memory Access Attributes
-* 
+*
 * \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
 * \param IsShareable       Region is shareable between multiple bus masters.
 * \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
 * \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
-*/  
+*/
 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
   ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
    (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
@@ -93,7 +93,7 @@
 
 /**
 * MPU Region Attribute and Size Register Value
-* 
+*
 * \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
 * \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
 * \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
@@ -104,10 +104,10 @@
   ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
    (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
    (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
-  
+
 /**
 * MPU Region Attribute and Size Register Value
-* 
+*
 * \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
 * \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
 * \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
@@ -116,7 +116,7 @@
 * \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
 * \param SubRegionDisable  Sub-region disable field.
 * \param Size              Region size of the region to be configured, for example 4K, 8K.
-*/                         
+*/
 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
   ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
 
@@ -126,7 +126,7 @@
 *  - Shareable
 *  - Non-cacheable
 *  - Non-bufferable
-*/ 
+*/
 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
 
 /**
@@ -137,7 +137,7 @@
 *  - Bufferable (if shareable) or non-bufferable (if non-shareable)
 *
 * \param IsShareable Configures the device memory as shareable or non-shareable.
-*/ 
+*/
 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
 
 /**
@@ -150,7 +150,7 @@
 * \param OuterCp Configures the outer cache policy.
 * \param InnerCp Configures the inner cache policy.
 * \param IsShareable Configures the memory as shareable or non-shareable.
-*/ 
+*/
 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
 
 /**
@@ -181,7 +181,7 @@ typedef struct {
   uint32_t RBAR; //!< The region base address register value (RBAR)
   uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
 } ARM_MPU_Region_t;
-    
+
 /** Enable the MPU.
 * \param MPU_Control Default access permissions for unconfigured regions.
 */
@@ -219,7 +219,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
 /** Configure an MPU region.
 * \param rbar Value for RBAR register.
 * \param rsar Value for RSAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
 {
   MPU->RBAR = rbar;
@@ -230,7 +230,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rsar Value for RSAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
 {
   MPU->RNR = rnr;
@@ -246,7 +246,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
 {
   uint32_t i;
-  for (i = 0U; i < len; ++i) 
+  for (i = 0U; i < len; ++i)
   {
     dst[i] = src[i];
   }
@@ -256,7 +256,7 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
 {
   const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
   while (cnt > MPU_TYPE_RALIASES) {

bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x.h

@@ -1044,8 +1044,8 @@ typedef struct
     __IO uint32_t DMA_CTRL;
     __IO uint32_t DMATDL_CTRL;
     __IO uint32_t DMARDL_CTRL;
-    __IO uint32_t IDCODE;
-    __IO uint32_t RESERVED;
+    __IO uint32_t RESERVED0;
+    __IO uint32_t RESERVED1;
     __IO uint32_t DAT0;
     __IO uint32_t DAT1;
     __IO uint32_t DAT2;
@@ -7910,58 +7910,58 @@ typedef struct
 #define QSPI_CTRL0_DFS_2                            ((uint32_t)0x00000004) /*!< Bit 2 */
 #define QSPI_CTRL0_DFS_3                            ((uint32_t)0x00000008) /*!< Bit 3 */
 #define QSPI_CTRL0_DFS_4                            ((uint32_t)0x00000010) /*!< Bit 4 */
-#define QSPI_CTRL0_DFS_4_BIT                                ((uint32_t)0x00000003)
-#define QSPI_CTRL0_DFS_5_BIT                                ((uint32_t)0x00000004)
-#define QSPI_CTRL0_DFS_6_BIT                                ((uint32_t)0x00000005)
-#define QSPI_CTRL0_DFS_7_BIT                                ((uint32_t)0x00000006)
-#define QSPI_CTRL0_DFS_8_BIT                                ((uint32_t)0x00000007)
-#define QSPI_CTRL0_DFS_9_BIT                                ((uint32_t)0x00000008)
-#define QSPI_CTRL0_DFS_10_BIT                               ((uint32_t)0x00000009)
-#define QSPI_CTRL0_DFS_11_BIT                               ((uint32_t)0x0000000A)
-#define QSPI_CTRL0_DFS_12_BIT                               ((uint32_t)0x0000000B)
-#define QSPI_CTRL0_DFS_13_BIT                               ((uint32_t)0x0000000C)
-#define QSPI_CTRL0_DFS_14_BIT                               ((uint32_t)0x0000000D)
-#define QSPI_CTRL0_DFS_15_BIT                               ((uint32_t)0x0000000E)
-#define QSPI_CTRL0_DFS_16_BIT                               ((uint32_t)0x0000000F)
-#define QSPI_CTRL0_DFS_17_BIT                               ((uint32_t)0x00000010)
-#define QSPI_CTRL0_DFS_18_BIT                               ((uint32_t)0x00000011)
-#define QSPI_CTRL0_DFS_19_BIT                               ((uint32_t)0x00000012)
-#define QSPI_CTRL0_DFS_20_BIT                               ((uint32_t)0x00000013)
-#define QSPI_CTRL0_DFS_21_BIT                               ((uint32_t)0x00000014)
-#define QSPI_CTRL0_DFS_22_BIT                               ((uint32_t)0x00000015)
-#define QSPI_CTRL0_DFS_23_BIT                               ((uint32_t)0x00000016)
-#define QSPI_CTRL0_DFS_24_BIT                               ((uint32_t)0x00000017)
-#define QSPI_CTRL0_DFS_25_BIT                               ((uint32_t)0x00000018)
-#define QSPI_CTRL0_DFS_26_BIT                               ((uint32_t)0x00000019)
-#define QSPI_CTRL0_DFS_27_BIT                               ((uint32_t)0x0000001A)
-#define QSPI_CTRL0_DFS_28_BIT                               ((uint32_t)0x0000001B)
-#define QSPI_CTRL0_DFS_29_BIT                               ((uint32_t)0x0000001C)
-#define QSPI_CTRL0_DFS_30_BIT                               ((uint32_t)0x0000001D)
-#define QSPI_CTRL0_DFS_31_BIT                               ((uint32_t)0x0000001E)
-#define QSPI_CTRL0_DFS_32_BIT                               ((uint32_t)0x0000001F)
+#define QSPI_CTRL0_DFS_4_BIT                        ((uint32_t)0x00000003)
+#define QSPI_CTRL0_DFS_5_BIT                        ((uint32_t)0x00000004)
+#define QSPI_CTRL0_DFS_6_BIT                        ((uint32_t)0x00000005)
+#define QSPI_CTRL0_DFS_7_BIT                        ((uint32_t)0x00000006)
+#define QSPI_CTRL0_DFS_8_BIT                        ((uint32_t)0x00000007)
+#define QSPI_CTRL0_DFS_9_BIT                        ((uint32_t)0x00000008)
+#define QSPI_CTRL0_DFS_10_BIT                       ((uint32_t)0x00000009)
+#define QSPI_CTRL0_DFS_11_BIT                       ((uint32_t)0x0000000A)
+#define QSPI_CTRL0_DFS_12_BIT                       ((uint32_t)0x0000000B)
+#define QSPI_CTRL0_DFS_13_BIT                       ((uint32_t)0x0000000C)
+#define QSPI_CTRL0_DFS_14_BIT                       ((uint32_t)0x0000000D)
+#define QSPI_CTRL0_DFS_15_BIT                       ((uint32_t)0x0000000E)
+#define QSPI_CTRL0_DFS_16_BIT                       ((uint32_t)0x0000000F)
+#define QSPI_CTRL0_DFS_17_BIT                       ((uint32_t)0x00000010)
+#define QSPI_CTRL0_DFS_18_BIT                       ((uint32_t)0x00000011)
+#define QSPI_CTRL0_DFS_19_BIT                       ((uint32_t)0x00000012)
+#define QSPI_CTRL0_DFS_20_BIT                       ((uint32_t)0x00000013)
+#define QSPI_CTRL0_DFS_21_BIT                       ((uint32_t)0x00000014)
+#define QSPI_CTRL0_DFS_22_BIT                       ((uint32_t)0x00000015)
+#define QSPI_CTRL0_DFS_23_BIT                       ((uint32_t)0x00000016)
+#define QSPI_CTRL0_DFS_24_BIT                       ((uint32_t)0x00000017)
+#define QSPI_CTRL0_DFS_25_BIT                       ((uint32_t)0x00000018)
+#define QSPI_CTRL0_DFS_26_BIT                       ((uint32_t)0x00000019)
+#define QSPI_CTRL0_DFS_27_BIT                       ((uint32_t)0x0000001A)
+#define QSPI_CTRL0_DFS_28_BIT                       ((uint32_t)0x0000001B)
+#define QSPI_CTRL0_DFS_29_BIT                       ((uint32_t)0x0000001C)
+#define QSPI_CTRL0_DFS_30_BIT                       ((uint32_t)0x0000001D)
+#define QSPI_CTRL0_DFS_31_BIT                       ((uint32_t)0x0000001E)
+#define QSPI_CTRL0_DFS_32_BIT                       ((uint32_t)0x0000001F)
 
 #define QSPI_CTRL0_FRF                              ((uint32_t)0x000000C0) /*!< FRF[1:0] bits (Frame Format) */
 #define QSPI_CTRL0_FRF_0                            ((uint32_t)0x00000040) /*!< Bit 0 */
 #define QSPI_CTRL0_FRF_1                            ((uint32_t)0x00000080) /*!< Bit 1 */
-#define QSPI_CTRL0_FRF_MOTOROLA                             ((uint32_t)0x00000000)
-#define QSPI_CTRL0_FRF_TI                                   ((uint32_t)0x00000040)
-#define QSPI_CTRL0_FRF_MICROWIRE                            ((uint32_t)0x00000080)
+#define QSPI_CTRL0_FRF_MOTOROLA                     ((uint32_t)0x00000000)
+#define QSPI_CTRL0_FRF_TI                           ((uint32_t)0x00000040)
+#define QSPI_CTRL0_FRF_MICROWIRE                    ((uint32_t)0x00000080)
 
 #define QSPI_CTRL0_SCPH                             ((uint32_t)0x00000100) /*!< SCPH (Serial Clock Phase) */
-#define QSPI_CTRL0_SCPH_FIRST_EDGE                          ((uint32_t)0x00000000)
-#define QSPI_CTRL0_SCPH_SECOND_EDGE                         ((uint32_t)0x00000100)
+#define QSPI_CTRL0_SCPH_FIRST_EDGE                  ((uint32_t)0x00000000)
+#define QSPI_CTRL0_SCPH_SECOND_EDGE                 ((uint32_t)0x00000100)
 
 #define QSPI_CTRL0_SCPOL                            ((uint32_t)0x00000200) /*!< SCPOL(Serial Clock Polarity) */
-#define QSPI_CTRL0_SCPOL_LOW                                ((uint32_t)0x00000000)
-#define QSPI_CTRL0_SCPOL_HIGH                               ((uint32_t)0x00000200)
+#define QSPI_CTRL0_SCPOL_LOW                        ((uint32_t)0x00000000)
+#define QSPI_CTRL0_SCPOL_HIGH                       ((uint32_t)0x00000200)
 
 #define QSPI_CTRL0_TMOD                             ((uint32_t)0x00000C00) /*!< TMOD[1:0] bits (Transfer Mode) */
 #define QSPI_CTRL0_TMOD_0                           ((uint32_t)0x00000400) /*!< Bit 0 */
 #define QSPI_CTRL0_TMOD_1                           ((uint32_t)0x00000800) /*!< Bit 1 */
-#define QSPI_CTRL0_TMOD_TX_AND_RX                           ((uint32_t)0x00000000)
-#define QSPI_CTRL0_TMOD_TX_ONLY                             ((uint32_t)0x00000400)
-#define QSPI_CTRL0_TMOD_RX_ONLY                             ((uint32_t)0x00000800)
-#define QSPI_CTRL0_TMOD_EEPROM_READ                         ((uint32_t)0x00000C00)
+#define QSPI_CTRL0_TMOD_TX_AND_RX                   ((uint32_t)0x00000000)
+#define QSPI_CTRL0_TMOD_TX_ONLY                     ((uint32_t)0x00000400)
+#define QSPI_CTRL0_TMOD_RX_ONLY                     ((uint32_t)0x00000800)
+#define QSPI_CTRL0_TMOD_EEPROM_READ                 ((uint32_t)0x00000C00)
 
 #define QSPI_CTRL0_SRL_EN                           ((uint32_t)0x00002000) /*!< SRL (Shift Register Loop) */
 #define QSPI_CTRL0_SSTE_EN                          ((uint32_t)0x00004000) /*!< SSTE(Slave Select Toggle Enable) */
@@ -7971,29 +7971,29 @@ typedef struct
 #define QSPI_CTRL0_CFS_1                            ((uint32_t)0x00020000) /*!< Bit 1 */
 #define QSPI_CTRL0_CFS_2                            ((uint32_t)0x00040000) /*!< Bit 2 */
 #define QSPI_CTRL0_CFS_3                            ((uint32_t)0x00080000) /*!< Bit 3 */
-#define QSPI_CTRL0_CFS_1_BIT                                ((uint32_t)0x00000000)
-#define QSPI_CTRL0_CFS_2_BIT                                ((uint32_t)0x00010000)
-#define QSPI_CTRL0_CFS_3_BIT                                ((uint32_t)0x00020000)
-#define QSPI_CTRL0_CFS_4_BIT                                ((uint32_t)0x00030000)
-#define QSPI_CTRL0_CFS_5_BIT                                ((uint32_t)0x00040000)
-#define QSPI_CTRL0_CFS_6_BIT                                ((uint32_t)0x00050000)
-#define QSPI_CTRL0_CFS_7_BIT                                ((uint32_t)0x00060000)
-#define QSPI_CTRL0_CFS_8_BIT                                ((uint32_t)0x00070000)
-#define QSPI_CTRL0_CFS_9_BIT                                ((uint32_t)0x00080000)
-#define QSPI_CTRL0_CFS_10_BIT                               ((uint32_t)0x00090000)
-#define QSPI_CTRL0_CFS_11_BIT                               ((uint32_t)0x000A0000)
-#define QSPI_CTRL0_CFS_12_BIT                               ((uint32_t)0x000B0000)
-#define QSPI_CTRL0_CFS_13_BIT                               ((uint32_t)0x000C0000)
-#define QSPI_CTRL0_CFS_14_BIT                               ((uint32_t)0x000D0000)
-#define QSPI_CTRL0_CFS_15_BIT                               ((uint32_t)0x000E0000)
-#define QSPI_CTRL0_CFS_16_BIT                               ((uint32_t)0x000F0000)
+#define QSPI_CTRL0_CFS_1_BIT                        ((uint32_t)0x00000000)
+#define QSPI_CTRL0_CFS_2_BIT                        ((uint32_t)0x00010000)
+#define QSPI_CTRL0_CFS_3_BIT                        ((uint32_t)0x00020000)
+#define QSPI_CTRL0_CFS_4_BIT                        ((uint32_t)0x00030000)
+#define QSPI_CTRL0_CFS_5_BIT                        ((uint32_t)0x00040000)
+#define QSPI_CTRL0_CFS_6_BIT                        ((uint32_t)0x00050000)
+#define QSPI_CTRL0_CFS_7_BIT                        ((uint32_t)0x00060000)
+#define QSPI_CTRL0_CFS_8_BIT                        ((uint32_t)0x00070000)
+#define QSPI_CTRL0_CFS_9_BIT                        ((uint32_t)0x00080000)
+#define QSPI_CTRL0_CFS_10_BIT                       ((uint32_t)0x00090000)
+#define QSPI_CTRL0_CFS_11_BIT                       ((uint32_t)0x000A0000)
+#define QSPI_CTRL0_CFS_12_BIT                       ((uint32_t)0x000B0000)
+#define QSPI_CTRL0_CFS_13_BIT                       ((uint32_t)0x000C0000)
+#define QSPI_CTRL0_CFS_14_BIT                       ((uint32_t)0x000D0000)
+#define QSPI_CTRL0_CFS_15_BIT                       ((uint32_t)0x000E0000)
+#define QSPI_CTRL0_CFS_16_BIT                       ((uint32_t)0x000F0000)
 
 #define QSPI_CTRL0_SPI_FRF                          ((uint32_t)0x00C00000) /*!< SPI_FRF[1:0] bits (SPI Frame Format) */
 #define QSPI_CTRL0_SPI_FRF_0                        ((uint32_t)0x00400000) /*!< Bit 0 */
 #define QSPI_CTRL0_SPI_FRF_1                        ((uint32_t)0x00800000) /*!< Bit 1 */
-#define QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT                  ((uint32_t)0x00000000)
-#define QSPI_CTRL0_SPI_FRF_DUAL_FORMAT                      ((uint32_t)0x00400000)
-#define QSPI_CTRL0_SPI_FRF_QUAD_FORMAT                      ((uint32_t)0x00800000)
+#define QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT          ((uint32_t)0x00000000)
+#define QSPI_CTRL0_SPI_FRF_DUAL_FORMAT              ((uint32_t)0x00400000)
+#define QSPI_CTRL0_SPI_FRF_QUAD_FORMAT              ((uint32_t)0x00800000)
 
 /*******************  Bit definition for QSPI_CTRL1 register  *******************/
 #define QSPI_CTRL1_NDF                              ((uint32_t)0x0000FFFF) /*!< NDF[15:0] bits (Numver of Data Frames) */
@@ -8019,12 +8019,12 @@ typedef struct
 
 /*******************  Bit definition for QSPI_MW_CTRL register  *******************/
 #define QSPI_MW_CTRL_MWMOD                          ((uint32_t)0x00000001) /*!< MWMO (Microwire Transfer Mode) */
-#define QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL                     ((uint32_t)0x00000000)
-#define QSPI_MW_CTRL_MWMOD_SEQUENTIAL                           ((uint32_t)0x00000001)
+#define QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL             ((uint32_t)0x00000000)
+#define QSPI_MW_CTRL_MWMOD_SEQUENTIAL               ((uint32_t)0x00000001)
 
 #define QSPI_MW_CTRL_MC_DIR                         ((uint32_t)0x00000002) /*!< MC_DIR (Direction of Data when Microwire Control) */
-#define QSPI_MW_CTRL_MC_DIR_RX                              ((uint32_t)0x00000000)
-#define QSPI_MW_CTRL_MC_DIR_TX                              ((uint32_t)0x00000002)
+#define QSPI_MW_CTRL_MC_DIR_RX                      ((uint32_t)0x00000000)
+#define QSPI_MW_CTRL_MC_DIR_TX                      ((uint32_t)0x00000002)
 
 #define QSPI_MW_CTRL_MHS_EN                         ((uint32_t)0x00000004) /*!< MHS_EN (Microwire Handshaking Enable) */
 
@@ -8098,8 +8098,7 @@ typedef struct
 #define QSPI_STS_TXFE                               ((uint32_t)0x00000004) /*!< TXFE (Transmit FIFO not Empty) */
 #define QSPI_STS_RXFNE                              ((uint32_t)0x00000008) /*!< RXFNE (Receive FIFO not Empty) */
 #define QSPI_STS_RXFF                               ((uint32_t)0x00000010) /*!< RXFF (Receive FIFO not Full) */
-#define QSPI_STS_TX_ERR                             ((uint32_t)0x00000020) /*!< TX_ERR (Transmit Error) */
-#define QSPI_STS_DC_ERR                                 ((uint32_t)0x00000040) /*!< DC_ERR (Data Conflict Error) */
+#define QSPI_STS_DC_ERR                             ((uint32_t)0x00000040) /*!< DC_ERR (Data Conflict Error) */
 
 /*******************  Bit definition for QSPI_IMASK register  *******************/
 #define QSPI_IMASK                                  ((uint32_t)0x0000007F) /*!< IMASK[6:0] (Interrupt of Mask) */
@@ -8168,41 +8167,6 @@ typedef struct
 #define QSPI_DMARDL_CTRL_DMARDL_4                   ((uint32_t)0x00000010) /*!< Bit 4 */
 #define QSPI_DMARDL_CTRL_DMARDL_5                   ((uint32_t)0x00000020) /*!< Bit 5 */
 
-/*******************  Bit definition for QSPI_IDCODE register  *******************/
-#define QSPI_IDCODE                                 ((uint32_t)0x0000FFFF) /*!< IDCODE[31:0] (Identification Code) */
-#define QSPI_IDCODE_0                               ((uint32_t)0x00000001) /*!< Bit 0 */
-#define QSPI_IDCODE_1                               ((uint32_t)0x00000002) /*!< Bit 1 */
-#define QSPI_IDCODE_2                               ((uint32_t)0x00000004) /*!< Bit 2 */
-#define QSPI_IDCODE_3                               ((uint32_t)0x00000008) /*!< Bit 3 */
-#define QSPI_IDCODE_4                               ((uint32_t)0x00000010) /*!< Bit 4 */
-#define QSPI_IDCODE_5                               ((uint32_t)0x00000020) /*!< Bit 5 */
-#define QSPI_IDCODE_6                               ((uint32_t)0x00000040) /*!< Bit 6 */
-#define QSPI_IDCODE_7                               ((uint32_t)0x00000080) /*!< Bit 7 */
-#define QSPI_IDCODE_8                               ((uint32_t)0x00000100) /*!< Bit 8 */
-#define QSPI_IDCODE_9                               ((uint32_t)0x00000200) /*!< Bit 9 */
-#define QSPI_IDCODE_10                              ((uint32_t)0x00000400) /*!< Bit 10 */
-#define QSPI_IDCODE_11                              ((uint32_t)0x00000800) /*!< Bit 11 */
-#define QSPI_IDCODE_12                              ((uint32_t)0x00001000) /*!< Bit 12 */
-#define QSPI_IDCODE_13                              ((uint32_t)0x00002000) /*!< Bit 13 */
-#define QSPI_IDCODE_14                              ((uint32_t)0x00004000) /*!< Bit 14 */
-#define QSPI_IDCODE_15                              ((uint32_t)0x00008000) /*!< Bit 15 */
-#define QSPI_IDCODE_16                              ((uint32_t)0x00010000) /*!< Bit 16 */
-#define QSPI_IDCODE_17                              ((uint32_t)0x00020000) /*!< Bit 17 */
-#define QSPI_IDCODE_18                              ((uint32_t)0x00040000) /*!< Bit 18 */
-#define QSPI_IDCODE_19                              ((uint32_t)0x00080000) /*!< Bit 19 */
-#define QSPI_IDCODE_20                              ((uint32_t)0x00100000) /*!< Bit 20 */
-#define QSPI_IDCODE_21                              ((uint32_t)0x00200000) /*!< Bit 21 */
-#define QSPI_IDCODE_22                              ((uint32_t)0x00400000) /*!< Bit 22 */
-#define QSPI_IDCODE_23                              ((uint32_t)0x00800000) /*!< Bit 23 */
-#define QSPI_IDCODE_24                              ((uint32_t)0x01000000) /*!< Bit 24 */
-#define QSPI_IDCODE_25                              ((uint32_t)0x02000000) /*!< Bit 25 */
-#define QSPI_IDCODE_26                              ((uint32_t)0x04000000) /*!< Bit 26 */
-#define QSPI_IDCODE_27                              ((uint32_t)0x08000000) /*!< Bit 27 */
-#define QSPI_IDCODE_28                              ((uint32_t)0x10000000) /*!< Bit 28 */
-#define QSPI_IDCODE_29                              ((uint32_t)0x20000000) /*!< Bit 29 */
-#define QSPI_IDCODE_30                              ((uint32_t)0x40000000) /*!< Bit 30 */
-#define QSPI_IDCODE_31                              ((uint32_t)0x80000000) /*!< Bit 31 */
-
 /*******************  Bit definition for QSPI_DAT0~QSPI_DAT31 register  *******************/
 #define QSPI_DATA_ALL                               ((uint32_t)0x0000FFFF) /*!< QSPI_DAT[31:0] (DATA Register) */
 #define QSPI_DATA_0                                 ((uint32_t)0x00000001) /*!< Bit 0 */
@@ -8248,24 +8212,24 @@ typedef struct
 #define QSPI_RS_DELAY_SDCN_5                        ((uint32_t)0x00000020) /*!< Bit 5 */
 #define QSPI_RS_DELAY_SDCN_6                        ((uint32_t)0x00000040) /*!< Bit 6 */
 #define QSPI_RS_DELAY_SDCN_7                        ((uint32_t)0x00000080) /*!< Bit 7 */
-#define QSPI_RS_DELAY_SDCN_0_CYCLES                             ((uint32_t)0x00000000)
-#define QSPI_RS_DELAY_SDCN_1_CYCLES                             ((uint32_t)0x00000001)
-#define QSPI_RS_DELAY_SDCN_2_CYCLES                             ((uint32_t)0x00000002)
-#define QSPI_RS_DELAY_SDCN_3_CYCLES                             ((uint32_t)0x00000003)
-#define QSPI_RS_DELAY_SDCN_4_CYCLES                             ((uint32_t)0x00000004)
-#define QSPI_RS_DELAY_SDCN_5_CYCLES                             ((uint32_t)0x00000005)
-#define QSPI_RS_DELAY_SDCN_6_CYCLES                             ((uint32_t)0x00000006)
-
-#define QSPI_RS_DELAY_SES                               ((uint32_t)0x00010000) /*!< SES (Sample Edge Select of Receive Data) */
-#define QSPI_RS_DELAY_SES_RISING_EDGE                           ((uint32_t)0x00000000)
-#define QSPI_RS_DELAY_SES_FALLING_EDGE                          ((uint32_t)0x00010000)
+#define QSPI_RS_DELAY_SDCN_0_CYCLES                 ((uint32_t)0x00000000)
+#define QSPI_RS_DELAY_SDCN_1_CYCLES                 ((uint32_t)0x00000001)
+#define QSPI_RS_DELAY_SDCN_2_CYCLES                 ((uint32_t)0x00000002)
+#define QSPI_RS_DELAY_SDCN_3_CYCLES                 ((uint32_t)0x00000003)
+#define QSPI_RS_DELAY_SDCN_4_CYCLES                 ((uint32_t)0x00000004)
+#define QSPI_RS_DELAY_SDCN_5_CYCLES                 ((uint32_t)0x00000005)
+#define QSPI_RS_DELAY_SDCN_6_CYCLES                 ((uint32_t)0x00000006)
+
+#define QSPI_RS_DELAY_SES                           ((uint32_t)0x00010000) /*!< SES (Sample Edge Select of Receive Data) */
+#define QSPI_RS_DELAY_SES_RISING_EDGE               ((uint32_t)0x00000000)
+#define QSPI_RS_DELAY_SES_FALLING_EDGE              ((uint32_t)0x00010000)
 /*******************  Bit definition for QSPI_ENH_CTRL0 register  *******************/
 #define QSPI_ENH_CTRL0_TRANS_TYPE                   ((uint32_t)0x00000003) /*!< TRANS_TYPE[1:0] (Address and instruction transfer format) */
 #define QSPI_ENH_CTRL0_TRANS_TYPE_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
 #define QSPI_ENH_CTRL0_TRANS_TYPE_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD              ((uint32_t)0x00000000)
-#define QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF        ((uint32_t)0x00000001)
-#define QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF            ((uint32_t)0x00000002)
+#define QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD          ((uint32_t)0x00000000)
+#define QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF    ((uint32_t)0x00000001)
+#define QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF        ((uint32_t)0x00000002)
 
 #define QSPI_ENH_CTRL0_ADDR_LEN                     ((uint32_t)0x0000003C) /*!< ADDR_LEN[3:0] (Length of Address to transmit) */
 #define QSPI_ENH_CTRL0_ADDR_LEN_0                   ((uint32_t)0x00000004) /*!< Bit 0 */
@@ -8288,15 +8252,13 @@ typedef struct
 #define QSPI_ENH_CTRL0_ADDR_LEN_56_BIT              ((uint32_t)0x00000038)
 #define QSPI_ENH_CTRL0_ADDR_LEN_60_BIT              ((uint32_t)0x0000003C)
 
-#define QSPI_ENH_CTRL0_MD_BIT_EN                    ((uint32_t)0x00000080) /*!< MD_BIT_EN (Mode bits enable in XIP mode) */
-
 #define QSPI_ENH_CTRL0_INST_L                       ((uint32_t)0x00000300) /*!< INST_L[1:0] (Dual/Quad mode instruction length in bits) */
 #define QSPI_ENH_CTRL0_INST_L_0                     ((uint32_t)0x00000100) /*!< Bit 0 */
 #define QSPI_ENH_CTRL0_INST_L_1                     ((uint32_t)0x00000200) /*!< Bit 1 */
-#define QSPI_ENH_CTRL0_INST_L_0_LINE                        ((uint32_t)0x00000000)
-#define QSPI_ENH_CTRL0_INST_L_4_LINE                        ((uint32_t)0x00000100)
-#define QSPI_ENH_CTRL0_INST_L_8_LINE                        ((uint32_t)0x00000200)
-#define QSPI_ENH_CTRL0_INST_L_16_LINE                       ((uint32_t)0x00000300)
+#define QSPI_ENH_CTRL0_INST_L_0_LINE                ((uint32_t)0x00000000)
+#define QSPI_ENH_CTRL0_INST_L_4_LINE                ((uint32_t)0x00000100)
+#define QSPI_ENH_CTRL0_INST_L_8_LINE                ((uint32_t)0x00000200)
+#define QSPI_ENH_CTRL0_INST_L_16_LINE               ((uint32_t)0x00000300)
 
 #define QSPI_ENH_CTRL0_WAIT_CYCLES                  ((uint32_t)0x0000F800) /*!< WAIT_CYCLES[4:0] (Wait Cycles in Dual/Quad mode between control frames transmit and data reception) */
 #define QSPI_ENH_CTRL0_WAIT_CYCLES_0                ((uint32_t)0x00000800) /*!< Bit 0 */
@@ -8336,23 +8298,10 @@ typedef struct
 #define QSPI_ENH_CTRL0_WAIT_30CYCLES                ((uint32_t)0x0000F000)
 #define QSPI_ENH_CTRL0_WAIT_31CYCLES                ((uint32_t)0x0000F800)
 
-
 #define QSPI_ENH_CTRL0_SPI_DDR_EN                   ((uint32_t)0x00010000) /*!< SPI_DDR_EN (SPI DDR Enable) */
 #define QSPI_ENH_CTRL0_INST_DDR_EN                  ((uint32_t)0x00020000) /*!< INST_DDR_EN (XIP instruction enable) */
-#define QSPI_ENH_CTRL0_XIP_DFS_HC                   ((uint32_t)0x00080000) /*!< XIP_DFS_HC (Fix DFS for XIP transfers) */
-#define QSPI_ENH_CTRL0_XIP_INST_EN                  ((uint32_t)0x00100000) /*!< XIP_INST_EN (XIP instruction enable) */
-#define QSPI_ENH_CTRL0_XIP_CT_EN                    ((uint32_t)0x00200000) /*!< XIP_CT_EN (Enable Continuous Transfer in XIP mode) */
-
-#define QSPI_ENH_CTRL0_XIP_MBL                      ((uint32_t)0x0C000000) /*!< XIP_MBL[1:0] (XIP Mode bits length) */
-#define QSPI_ENH_CTRL0_XIP_MBL_0                    ((uint32_t)0x04000000) /*!< Bit 0 */
-#define QSPI_ENH_CTRL0_XIP_MBL_1                    ((uint32_t)0x08000000) /*!< Bit 1 */
-#define QSPI_ENH_CTRL0_XIP_MBL_2_BIT                            ((uint32_t)0x00000000)
-#define QSPI_ENH_CTRL0_XIP_MBL_4_BIT                            ((uint32_t)0x04000000)
-#define QSPI_ENH_CTRL0_XIP_MBL_8_BIT                            ((uint32_t)0x08000000)
-#define QSPI_ENH_CTRL0_XIP_MBL_16_BIT                           ((uint32_t)0x0C000000)
 
-
-#define QSPI_ENH_CTRL0_CLK_STRETCH_EN               ((uint32_t)0x40000000) /*!< CLK_STRETCH_EN (Enable Continuous Transfer in XIP mode) */
+#define QSPI_ENH_CTRL0_CLK_STRETCH_EN               ((uint32_t)0x40000000) /*!< CLK_STRETCH_EN (Enable clock stretch capablity in SPI tramsfers) */
 
 /*******************  Bit definition for QSPI_DDR_TXDE register  *******************/
 #define QSPI_DDR_TXDE                               ((uint32_t)0x000000FF) /*!< TXDE[7:0] (Transmit Drive Edge) */
@@ -9022,17 +8971,17 @@ typedef struct
   */
 
 #define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-    
+
 #define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-    
+
 #define READ_BIT(REG, BIT)    ((REG) & (BIT))
-    
+
 #define CLEAR_REG(REG)        ((REG) = (0x0))
-    
+
 #define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-    
+
 #define READ_REG(REG)         ((REG))
-    
+
 #define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
 /**
  * @}

bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_gcc.s

@@ -57,7 +57,7 @@ defined in linker script */
  * @retval : None
 */
 
-  .section  .text.Reset_Handler
+    .section  .text.Reset_Handler
   .weak  Reset_Handler
   .type  Reset_Handler, %function
 Reset_Handler:  

bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.c

@@ -171,10 +171,10 @@ void SystemInit(void)
     RCC->CFG &= (uint32_t)0xF700FFFF;
 
     /* Reset CFG2 register */
-    RCC->CFG2 = 0x00000000;
+    RCC->CFG2 = 0x00003800;
 
     /* Reset CFG3 register */
-    RCC->CFG3 = 0x00000000;
+    RCC->CFG3 = 0x00003840;
 
     /* Disable all interrupts and clear pending bits  */
     RCC->CLKINT = 0x009F0000;

bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_aes.h

@@ -44,7 +44,7 @@
  * @brief AES symmetrical cipher algorithm
  * @{
  */
- 
+
 #define AES_ECB (0x11111111)
 #define AES_CBC (0x22222222)
 #define AES_CTR (0x33333333)
@@ -58,7 +58,7 @@ enum
     AES_Init_OK = 0x0,   //AES Init opreation success
     AES_Crypto_ModeError = 0x5a5a5a5a,   //Working mode error(Neither ECB nor CBC nor CTR)
     AES_Crypto_EnOrDeError,    //En&De error(Neither encryption nor decryption)
-    AES_Crypto_ParaNull,    // the part of input(output/iv) Null    
+    AES_Crypto_ParaNull,    // the part of input(output/iv) Null
     AES_Crypto_LengthError,     // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
                                 //if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
 
@@ -81,7 +81,7 @@ typedef struct
  /**
  * @brief AES_Init
  * @return AES_Init_OK, AES Init success; othets: AES Init fail
- * @note    
+ * @note
  */
 
 uint32_t  AES_Init(AES_PARM *parm);
@@ -89,8 +89,8 @@ uint32_t  AES_Init(AES_PARM *parm);
 /**
  * @brief AES crypto
  * @param[in] parm pointer to AES context and the detail please refer to struct AES_PARM in AES.h
- * @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation) 
- * @note  1.Please refer to the demo in user guidance before using this function  
+ * @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation)
+ * @note  1.Please refer to the demo in user guidance before using this function
  *        2.Input and output can be the same buffer
  *        3. IV can be NULL when ECB mode
  *        4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
@@ -111,7 +111,7 @@ void AES_Close(void);
  * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
  * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
  * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
- * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
  * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
  * @return none
  * @1.You can recall this function to get AES lib information

bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_algo_common.h

@@ -55,7 +55,7 @@ enum{
  * @param[in] rand pointer to random number
  * @param[in] the length of order
  * @return RandomSort_OK:  disturb order success;  Others: disturb order fail;
- * @note 
+ * @note
  */
 uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len);
 
@@ -63,7 +63,7 @@ uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len);
  * @brief Copy data by byte
  * @param[in]  dst pointer to destination data
  * @param[in]  src pointer to source data
- * @param[in]  byte length 
+ * @param[in]  byte length
  * @return Cpy_OK: success; others: fail.
  * @note 1. dst and  src cannot be same
  */
@@ -73,7 +73,7 @@ uint32_t Cpy_U8(uint8_t *dst, uint8_t *src, uint32_t byteLen);
  * @brief Copy data by word
  * @param[in]  dst pointer to destination data
  * @param[in]  src pointer to source data
- * @param[in]  word length 
+ * @param[in]  word length
  * @return Cpy_OK: success; others: fail.
  * @note 1. dst and  src must be aligned by word
  */
@@ -85,7 +85,7 @@ uint32_t Cpy_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);
  * @param[in] b pointer to another data to be XORed
  * @param[in] the length of order
  * @return XOR_OK:  operation success;  Others: operation fail;
- * @note 
+ * @note
  */
 uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
 
@@ -95,33 +95,33 @@ uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
  * @param[in] b pointer to another data to be XORed
  * @param[in] the length of order
  * @return XOR_OK:  operation success;  Others: operation fail;
- * @note 
+ * @note
  */
 uint32_t XOR_U32(uint32_t *a,uint32_t *b,uint32_t *c,uint32_t wordLen);
 
 /**
  * @brief set zero by byte
- * @param[in] dst pointer to the address to be set zero 
- * @param[in]  byte length 
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in]  byte length
  * @return SetZero_OK: success; others: fail.
- * @note 
+ * @note
  */
 uint32_t SetZero_U8(uint8_t *dst, uint32_t byteLen);
 
 /**
  * @brief set zero by word
- * @param[in] dst pointer to the address to be set zero 
- * @param[in]  word length 
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in]  word length
  * @return SetZero_OK: success; others: fail.
- * @note 
+ * @note
  */
 uint32_t SetZero_U32(uint32_t *dst, uint32_t wordLen);
 
 /**
  * @brief reverse byte order of every word, the words stay the same
  * @param[in]  dst pointer to the destination address
- * @param[in]  src pointer to the source address 
- * @param[in]  word length 
+ * @param[in]  src pointer to the source address
+ * @param[in]  word length
  * @return Reverse_OK: success; others: fail.
  * @note 1.dst and src can be same
  */
@@ -134,7 +134,7 @@ uint32_t ReverseBytesInWord_U32(uint32_t *dst, const uint32_t *src, uint32_t wor
  * @param[in] b pointer to another big number
  * @param[in]  word length of b
  * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
- * 
+ *
  */
 int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_t bWordLen);
 
@@ -145,7 +145,7 @@ int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_
  * @param[in] b pointer to another big number
  * @param[in]  word length of b
  * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
- * 
+ *
  */
 int32_t Cmp_U8(const uint8_t *a, uint32_t aByteLen, const uint8_t *b, uint32_t bByteLen);
 

bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_des.h

@@ -83,15 +83,15 @@ typedef struct
  /**
  * @brief DES_Init
  * @return DES_Init_OK, DES/TDES Init success; othets: DES/TDES Init fail
- * @note    
+ * @note
  */
 uint32_t DES_Init(DES_PARM* parm);
 
 /**
  * @brief DES crypto
  * @param[in] parm pointer to DES/TDES context and the detail please refer to struct DES_PARM in DES.h
- * @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation) 
- * @note  1.Please refer to the demo in user guidance before using this function  
+ * @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation)
+ * @note  1.Please refer to the demo in user guidance before using this function
  *        2.Input and output can be the same buffer
  *        3. IV can be NULL when ECB mode
  *        4. The word lengrh of message must be as times as 2.
@@ -111,7 +111,7 @@ void DES_Close(void);
  * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
  * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
  * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
- * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
  * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
  * @return none
  * @1.You can recall this function to get DES/TDES lib information

bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_hash.h

@@ -53,7 +53,7 @@
 enum
 {
     HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
-    HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV 
+    HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV
     HASH_Init_OK = 0,//hash init success
     HASH_Start_OK = 0,//hash update success
     HASH_Update_OK = 0,//hash update success
@@ -67,7 +67,7 @@ enum
     SHA224_Hash_OK = 0,//sha224 operation success
     SHA256_Hash_OK = 0,//sha256 operation success
     MD5_Hash_OK = 0,//MD5 operation success
-    
+
     HASH_Init_ERROR = 0x01044400,//hash init error
     HASH_Start_ERROR, //hash start error
     HASH_Update_ERROR, //hash update error
@@ -93,7 +93,7 @@ typedef struct _HASH_CTX_
 {
     const HASH_ALG  *hashAlg;//pointer to HASH_ALG
     uint32_t        sequence;   // TRUE if the IV should be saved
-    uint32_t    IV[16]; 
+    uint32_t    IV[16];
     uint32_t    msgByteLen[4];
     uint8_t     msgBuf[128+4];
     uint32_t    msgIdx;
@@ -109,7 +109,7 @@ extern const HASH_ALG HASH_ALG_SM3[1];
  * @brief  Hash init
  * @param[in] ctx pointer to HASH_CTX struct
  * @return HASH_Init_OK,  Hash init success; othets:  Hash init fail
- * @note   1.Please refer to the demo in user guidance before using this function 
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t HASH_Init(HASH_CTX *ctx);
 
@@ -117,8 +117,8 @@ uint32_t HASH_Init(HASH_CTX *ctx);
  * @brief  Hash start
  * @param[in] ctx pointer to HASH_CTX struct
  * @return HASH_Start_OK,  Hash start success; othets:  Hash start fail
- * @note   1.Please refer to the demo in user guidance before using this function 
- *         2.HASH_Init() should be recalled before use this function 
+ * @note   1.Please refer to the demo in user guidance before using this function
+ *         2.HASH_Init() should be recalled before use this function
  */
 uint32_t HASH_Start(HASH_CTX *ctx);
 
@@ -128,8 +128,8 @@ uint32_t HASH_Start(HASH_CTX *ctx);
  * @param[in] in pointer to message
  * @param[out] out pointer tohash result,digest
  * @return HASH_Update_OK,  Hash update success; othets:  Hash update fail
- * @note   1.Please refer to the demo in user guidance before using this function 
- *         2.HASH_Init() and HASH_Start() should be recalled before use this function 
+ * @note   1.Please refer to the demo in user guidance before using this function
+ *         2.HASH_Init() and HASH_Start() should be recalled before use this function
  */
 uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen);
 
@@ -138,15 +138,15 @@ uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen);
  * @param[in] ctx pointer to HASH_CTX struct
  * @param[out] out pointer tohash result,digest
  * @return HASH_Complete_OK,  Hash complete success; othets:  Hash complete fail
- * @note   1.Please refer to the demo in user guidance before using this function 
- *         2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function 
+ * @note   1.Please refer to the demo in user guidance before using this function
+ *         2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function
  */
 uint32_t HASH_Complete(HASH_CTX *ctx, uint8_t *out);
 
 /**
  * @brief  Hash close
  * @return HASH_Close_OK, Hash close success; othets: Hash close fail
- * @note   1.Please refer to the demo in user guidance before using this function  
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t HASH_Close(void);
 
@@ -156,7 +156,7 @@ uint32_t HASH_Close(void);
  * @param[in] byte length of in
  * @param[out] out pointer tohash result,digest
  * @return SM3_Hash_OK, SM3 hash success; othets: SM3 hash fail
- * @note   1.Please refer to the demo in user guidance before using this function  
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t SM3_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
 
@@ -167,7 +167,7 @@ uint32_t SM3_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
  * @param[in] byte length of in
  * @param[out] out pointer tohash result,digest
  * @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail
- * @note   1.Please refer to the demo in user guidance before using this function  
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t SHA1_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
 
@@ -177,7 +177,7 @@ uint32_t SHA1_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
  * @param[in] byte length of in
  * @param[out] out pointer tohash result,digest
  * @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail
- * @note   1.Please refer to the demo in user guidance before using this function  
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
 
@@ -188,7 +188,7 @@ uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
  * @param[in] byte length of in
  * @param[out] out pointer tohash result,digest
  * @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail
- * @note   1.Please refer to the demo in user guidance before using this function  
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
 
@@ -198,7 +198,7 @@ uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
  * @param[in] byte length of in
  * @param[in] out pointer tohash result,digest
  * @return MD5_Hash_OK, MD5 hash success; othets: MD5 hash fail
- * @note   1.Please refer to the demo in user guidance before using this function  
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t MD5_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
 
@@ -207,7 +207,7 @@ uint32_t MD5_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
  * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
  * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
  * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
- * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
  * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
  * @return none
  * @1.You can recall this function to get RSA lib information