update es32f0654 , es32f369x libraries

bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/gcc/startup_es32f065x.s

@@ -0,0 +1,299 @@
+/**
+  ******************************************************************************
+  * @file      startup_es32f065x.s
+  * @author    AE Team
+  * @brief     ES32F065x devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M0 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          10 Dec 2018     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+  .syntax unified
+  .arch armv6-m
+  .cpu cortex-m0
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+  bl __libc_init_array
+
+  bl main
+
+LoopForever:
+    b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack                        /* 0,  load top of stack */
+  .word  Reset_Handler                  /* 1,  reset handler */
+  .word  NMI_Handler                    /* 2,  nmi handler */
+  .word  HardFault_Handler              /* 3,  hard fault handler */
+  .word  0                              /* 4,  Reserved */
+  .word  0                              /* 5,  Reserved */
+  .word  0                              /* 6,  Reserved */
+  .word  0                              /* 7,  Reserved */
+  .word  0                              /* 8,  Reserved */
+  .word  0                              /* 9,  Reserved */
+  .word  0                              /* 10, Reserved */
+  .word  SVC_Handler                    /* 11, svcall handler */
+  .word  DebugMon_Handler               /* 12, Debug Monitor Handler */
+  .word  0                              /* 13, Reserved */
+  .word  PendSV_Handler                 /* 14, pendsv handler */
+  .word  SysTick_Handler                /* 15, systick handler */
+  .word  WWDG_IWDG_Handler                   /* 16, irq0    WWDG_IWDG handler */
+  .word  LVD_Handler                   /* 17, irq1    LVD handler */
+  .word  RTC_TSENSE_Handler                    /* 18, irq2    RTC handler */
+  .word  CRYPT_TRNG_Handler                    /* 19, irq3    CRYPT handler */
+  .word  CMU_Handler                              /* 20, irq4    CMU handler */
+  .word  EXTI0_3_Handler                              /* 21, irq5    EXTI0_3 handler */
+  .word  EXTI4_7_Handler                    /* 22, irq6    EXTI4_7 handler */
+  .word  EXTI8_11_Handler                   /* 23, irq7    EXTI8_11 handler */
+  .word  EXTI12_15_Handler                /* 24, irq8    EXTI12_15 handler */
+  .word  DMA_Handler               /* 25, irq9    DMA handler */
+  .word  CAN0_Handler               /* 26, irq10   CAN0_CRYPT_TRNG handler */
+  .word  LPTIM0_SPI2_Handler         /* 27, irq11   LPTIM0_SPI2 handler */
+  .word  ADC_ACMP_Handler           /* 28, irq12   ADC_ACMP handler */
+  .word  AD16C4T0_BRK_UP_TRIG_COM_Handler            /* 29, irq13   AD16C4T0_BRK_UP_TRIG_COM handler */
+  .word  AD16C4T0_CC_Handler      /* 30, irq14   AD16C4T0_CC handler */
+  .word  BS16T0_Handler            /* 31, irq15   BS16T0 handler */
+  .word  0           /* 32, irq16  Reserved */
+  .word  GP16C2T0_Handler            /* 33, irq17   GP16C2T0 handler */
+  .word  GP16C2T1_Handler      /* 34, irq18   GP16C2T1 handler */
+  .word  BS16T1_UART2_Handler            /* 35, irq19   BS16T1_UART2 handler */
+  .word  BS16T2_UART3_Handler               /* 36, irq20   BS16T2_UART3 handler */
+  .word  GP16C4T0_LCD_Handler               /* 37, irq21   GP16C4T0_LCD handler */
+  .word  BS16T3_DAC0_Handler                 /* 38, irq22   BS16T3_DAC0  handler */
+  .word  I2C0_Handler                 /* 39, irq23   I2C0 handler */
+  .word  I2C1_Handler               /* 40, irq24   I2C1 handler */
+  .word  SPI0_Handler               /* 41, irq25   SPI0 handler */
+  .word  SPI1_Handler                              /* 42, irq26   SPI1 handler */
+  .word  UART0_Handler                /* 43, irq27   UART0 handler */
+  .word  UART1_Handler                /* 44, irq28   UART1 handler */
+  .word  USART0_Handler               /* 45, irq29   USART0 handler */
+  .word  USART1_Handler                /* 46  irq30   USART1 handler */
+  .word  LPUART0_Handler               /* 47, irq31   LPUART0 handler */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+  
+   .weak      DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+  
+   .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDG_IWDG_Handler
+  .thumb_set WWDG_IWDG_Handler,Default_Handler
+  
+   .weak      LVD_Handler
+  .thumb_set LVD_Handler,Default_Handler
+
+   .weak      RTC_TSENSE_Handler
+  .thumb_set RTC_TSENSE_Handler,Default_Handler
+  
+   .weak      CRYPT_TRNG_Handler
+  .thumb_set CRYPT_TRNG_Handler,Default_Handler
+
+   .weak      CMU_Handler
+  .thumb_set CMU_Handler,Default_Handler
+  
+   .weak      EXTI0_3_Handler
+  .thumb_set EXTI0_3_Handler,Default_Handler
+
+   .weak      EXTI4_7_Handler
+  .thumb_set EXTI4_7_Handler,Default_Handler
+  
+   .weak      EXTI8_11_Handler
+  .thumb_set EXTI8_11_Handler,Default_Handler
+
+  .weak      EXTI12_15_Handler
+  .thumb_set EXTI12_15_Handler,Default_Handler
+  
+   .weak      DMA_Handler
+  .thumb_set DMA_Handler,Default_Handler
+
+   .weak      CAN0_Handler
+  .thumb_set CAN0_Handler,Default_Handler
+  
+   .weak      LPTIM0_SPI2_Handler
+  .thumb_set LPTIM0_SPI2_Handler,Default_Handler
+
+   .weak      ADC_ACMP_Handler
+  .thumb_set ADC_ACMP_Handler,Default_Handler
+  
+   .weak      AD16C4T0_BRK_UP_TRIG_COM_Handler
+  .thumb_set AD16C4T0_BRK_UP_TRIG_COM_Handler,Default_Handler
+
+   .weak      AD16C4T0_CC_Handler
+  .thumb_set AD16C4T0_CC_Handler,Default_Handler
+  
+   .weak      BS16T0_Handler
+  .thumb_set BS16T0_Handler,Default_Handler
+
+   .weak      GP16C2T0_Handler
+  .thumb_set GP16C2T0_Handler,Default_Handler
+  
+   .weak      GP16C2T1_Handler
+  .thumb_set GP16C2T1_Handler,Default_Handler
+
+   .weak      BS16T1_UART2_Handler
+  .thumb_set BS16T1_UART2_Handler,Default_Handler
+  
+   .weak      BS16T2_UART3_Handler
+  .thumb_set BS16T2_UART3_Handler,Default_Handler
+
+  .weak      GP16C4T0_LCD_Handler
+  .thumb_set GP16C4T0_LCD_Handler,Default_Handler
+  
+   .weak      BS16T3_DAC0_Handler
+  .thumb_set BS16T3_DAC0_Handler,Default_Handler
+
+   .weak      I2C0_Handler
+  .thumb_set I2C0_Handler,Default_Handler
+  
+   .weak      I2C1_Handler
+  .thumb_set I2C1_Handler,Default_Handler
+
+   .weak      SPI0_Handler
+  .thumb_set SPI0_Handler,Default_Handler
+  
+   .weak      SPI1_Handler
+  .thumb_set SPI1_Handler,Default_Handler
+
+   .weak      UART0_Handler
+  .thumb_set UART0_Handler,Default_Handler
+  
+   .weak      UART1_Handler
+  .thumb_set UART1_Handler,Default_Handler
+
+   .weak      USART0_Handler
+  .thumb_set USART0_Handler,Default_Handler
+  
+   .weak      USART1_Handler
+  .thumb_set USART1_Handler,Default_Handler
+
+   .weak      LPUART0_Handler
+  .thumb_set LPUART0_Handler,Default_Handler
+ 

bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s

@@ -3,8 +3,27 @@
 ; description: es32f065x Device Startup File
 ; author     : AE Team
 ; data       : 10 Dec 2018
+; note
+;          Change Logs:
+;          Date            Author          Notes
+;          10 Dec 2018     AE Team         The first version
+;
 ; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-;*******************************************************************************
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Licensed under the Apache License, Version 2.0 (the License); you may
+; not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+; www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;*********************************************************************************
 
         MODULE  ?cstartup
 
@@ -35,7 +54,7 @@ __vector_table
         DCD     SysTick_Handler				;15, systick handler
         DCD     WWDG_IWDG_Handler			;16, irq0    WWDG_IWDG handler
         DCD     LVD_Handler				;17, irq1    LVD handler
-        DCD     RTC_TEMP_Handler			;18, irq2    RTC handler
+        DCD     RTC_TSENSE_Handler			;18, irq2    RTC handler
         DCD     CRYPT_TRNG_Handler			;19, irq3    CRYPT handler
         DCD     CMU_Handler				;20, irq4    CMU handler
         DCD     EXTI0_3_Handler				;21, irq5    EXTI0_3 handler
@@ -118,10 +137,10 @@ WWDG_IWDG_Handler
 LVD_Handler
 	B LVD_Handler
 		
-	PUBWEAK RTC_TEMP_Handler
+	PUBWEAK RTC_TSENSE_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_TEMP_Handler
-        B RTC_TEMP_Handler
+RTC_TSENSE_Handler
+        B RTC_TSENSE_Handler
 
         PUBWEAK CRYPT_TRNG_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)

bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s

@@ -3,8 +3,27 @@
 ; description: es32f065x Device Startup File
 ; author     : AE Team
 ; data       : 29 Aug 2017
+; note
+;          Change Logs:
+;          Date            Author          Notes
+;          29 Aug 2017     AE Team         The first version
+;
 ; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-;*******************************************************************************
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Licensed under the Apache License, Version 2.0 (the License); you may
+; not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+; www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;*********************************************************************************
 
 ;Stack Configuration------------------------------------------------------------
 Stack_Size      EQU     0x00000400

bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S

@@ -11,7 +11,27 @@
   *                  calls main()).
   *            After Reset the Cortex-M3 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          23 Jan 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
   */
 
   .syntax unified
@@ -41,6 +61,48 @@ defined in linker script */
 Reset_Handler:
   ldr   r0, =_estack
   mov   sp, r0          /* set stack pointer */
+  
+  ldr r0, =0x55AA6996
+  ldr r1, =0x40080000
+  str r0, [r1]
+  
+  ldr r0, =0x5A962814
+  ldr r1, =0x40080100
+  str r0, [r1]
+  ldr r0, =0xE7CB69A5
+  str r0, [r1]
+  
+  ldr r0, =0x40083C00
+  ldr r1, [r0]
+  ldr r2, =0xffff
+  and r1, r2
+  ldr r2, =0x55AA0000
+  orr r1, r2
+  str r1, [r0]
+  str r1, [r0]
+  str r1, [r0]
+  str r1, [r0]
+  str r1, [r0]
+  str r1, [r0]
+  str r1, [r0]
+  str r1, [r0]
+  str r1, [r0]
+  str r1, [r0]
+  
+  mov r0, r0
+  mov r0, r0
+  
+  ldr r0, =0x123456
+  ldr r1, =0x40080100
+  str r0, [r1]
+  
+  ldr r0, =0x40080404
+  ldr r1, =0x4000000
+  str r1, [r0]
+  
+  ldr r0, =0x123456
+  ldr r1, =0x40080000
+  str r0, [r1]
 
 /* Copy the data segment initializers from flash to SRAM */
   ldr r0, =_sdata
@@ -72,11 +134,13 @@ FillZerobss:
 LoopFillZerobss:
   cmp r2, r4
   bcc FillZerobss
+  
+  bl sys_config
+  bl adc_config
 
-/*bl __libc_init_array
+  bl __libc_init_array
 
-  bl main */
-  bl entry
+  bl main
 
 LoopForever:
     b LoopForever

bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s

@@ -3,8 +3,27 @@
 ; description: es32f36xx Device Startup File
 ; author     : AE Team
 ; data       : 04 Jul 2019
+; note
+;          Change Logs:
+;          Date            Author          Notes
+;          04 Jul 2019     AE Team         The first version
+;
 ; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-;*******************************************************************************
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Licensed under the Apache License, Version 2.0 (the License); you may
+; not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+; www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;*********************************************************************************
 
         MODULE  ?cstartup
 
@@ -12,6 +31,8 @@
         SECTION CSTACK:DATA:NOROOT(3)
         SECTION .intvec:CODE:NOROOT(2)
 
+		EXTERN  sys_config
+		EXTERN  adc_config
         EXTERN  __iar_program_start
         PUBLIC  __vector_table
 
@@ -116,8 +137,56 @@ __vector_table
         PUBWEAK RESET_Handler
         SECTION .text:CODE:NOROOT:REORDER(2)
 RESET_Handler
-        LDR     R0, =__iar_program_start
-        BX      R0
+	ldr r0, =0x55AA6996
+	ldr r1, =0x40080000
+	str r0, [r1]
+
+	ldr r0, =0x5A962814
+	ldr r1, =0x40080100
+	str r0, [r1]
+	ldr r0, =0xE7CB69A5
+	str r0, [r1]
+
+	ldr r0, =0x40083C00
+	ldr r1, [r0]
+	ldr r2, =0xffff
+	and r1, r2, r1
+	ldr r2, =0x55AA0000
+	orr r1, r2, r1
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+
+	mov r0, r0
+	mov r0, r0
+
+	ldr r0, =0x123456
+	ldr r1, =0x40080100
+	str r0, [r1]
+
+	ldr r0, =0x40080404
+	ldr r1, =0x4000000
+	str r1, [r0]
+	
+	ldr r0, =0x123456
+	ldr r1, =0x40080000
+	str r0, [r1]
+	
+	LDR     R0, =sys_config
+    BLX     R0
+	
+	LDR     R0, =adc_config
+    BLX     R0
+	
+    LDR     R0, =__iar_program_start
+    BX      R0
         
         PUBWEAK NMI_Handler
         SECTION .text:CODE:NOROOT:REORDER(1)

bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s

@@ -3,22 +3,27 @@
 ; description: es32f36xx Device Startup File
 ; author     : AE Team
 ; data       : 23 Jan 2019
+; note
+;          Change Logs:
+;          Date            Author          Notes
+;          23 Jan 2019     AE Team         The first version
+;
 ; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-; 
+;
 ; SPDX-License-Identifier: Apache-2.0
-; 
+;
 ; Licensed under the Apache License, Version 2.0 (the License); you may
 ; not use this file except in compliance with the License.
 ; You may obtain a copy of the License at
-; 
+;
 ; www.apache.org/licenses/LICENSE-2.0
-; 
+;
 ; Unless required by applicable law or agreed to in writing, software
 ; distributed under the License is distributed on an AS IS BASIS, WITHOUT
 ; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 ; See the License for the specific language governing permissions and
 ; limitations under the License.
-;*******************************************************************************
+;*********************************************************************************
 
 ;Stack Configuration------------------------------------------------------------
 Stack_Size      EQU     0x00000800
@@ -137,6 +142,57 @@ __Vectors       DCD     __initial_sp                    ;0,  load top of stack
 ;Reset Handler----------------------------------------------
 RESET_Handler   PROC
 	EXPORT  RESET_Handler                  [WEAK]
+
+	ldr r0, =0x55AA6996
+	ldr r1, =0x40080000
+	str r0, [r1]
+
+	ldr r0, =0x5A962814
+	ldr r1, =0x40080100
+	str r0, [r1]
+	ldr r0, =0xE7CB69A5
+	str r0, [r1]
+
+	ldr r0, =0x40083C00
+	ldr r1, [r0]
+	ldr r2, =0xffff
+	and r1, r2
+	ldr r2, =0x55AA0000
+	orr r1, r2
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+	str r1, [r0]
+
+	mov r0, r0
+	mov r0, r0
+
+	ldr r0, =0x123456
+	ldr r1, =0x40080100
+	str r0, [r1]
+
+	ldr r0, =0x40080404
+	ldr r1, =0x4000000
+	str r1, [r0]
+	
+	ldr r0, =0x123456
+	ldr r1, =0x40080000
+	str r0, [r1]
+	
+	IMPORT sys_config
+	LDR R0, =sys_config
+	BLX R0
+	
+	IMPORT adc_config
+	LDR R0, =adc_config
+	BLX R0
+
 	IMPORT  __main
 	LDR     R0, =__main
 	BX      R0

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h

@@ -50,23 +50,63 @@
   * @defgroup GPIO_Public_Macros GPIO Public Macros
   * @{
   */
-#define GPIO_PIN_0	(1U << 0)
-#define GPIO_PIN_1	(1U << 1)
-#define GPIO_PIN_2	(1U << 2)
-#define GPIO_PIN_3	(1U << 3)
-#define GPIO_PIN_4	(1U << 4)
-#define GPIO_PIN_5	(1U << 5)
-#define GPIO_PIN_6	(1U << 6)
-#define GPIO_PIN_7	(1U << 7)
-#define GPIO_PIN_8	(1U << 8)
-#define GPIO_PIN_9	(1U << 9)
-#define GPIO_PIN_10	(1U << 10)
-#define GPIO_PIN_11	(1U << 11)
-#define GPIO_PIN_12	(1U << 12)
-#define GPIO_PIN_13	(1U << 13)
-#define GPIO_PIN_14	(1U << 14)
-#define GPIO_PIN_15	(1U << 15)
-#define GPIO_PIN_ALL	(0xFFFF)
+#define GPIO_PIN_0      (0x1U)
+#define GPIO_PIN_1      (0x2U)
+#define GPIO_PIN_2      (0x4U)
+#define GPIO_PIN_3      (0x8U)
+#define GPIO_PIN_4      (0x10U)
+#define GPIO_PIN_5      (0x20U)
+#define GPIO_PIN_6      (0x40U)
+#define GPIO_PIN_7      (0x80U)
+#define GPIO_PIN_8      (0x100U)
+#define GPIO_PIN_9      (0x200U)
+#define GPIO_PIN_10     (0x400U)
+#define GPIO_PIN_11     (0x800U)
+#define GPIO_PIN_12     (0x1000U)
+#define GPIO_PIN_13     (0x2000U)
+#define GPIO_PIN_14     (0x4000U)
+#define GPIO_PIN_15     (0x8000U)
+#define GPIO_PIN_ALL    (0xFFFF)
+
+/* Toggle IO */
+#define ALD_GPIOA_TOGGLE_PIN(x)    (GPIOA->BIR = (x))
+#define ALD_GPIOB_TOGGLE_PIN(x)    (GPIOB->BIR = (x))
+#define ALD_GPIOC_TOGGLE_PIN(x)    (GPIOC->BIR = (x))
+#define ALD_GPIOD_TOGGLE_PIN(x)    (GPIOD->BIR = (x))
+#define ALD_GPIOE_TOGGLE_PIN(x)    (GPIOE->BIR = (x))
+#define ALD_GPIOF_TOGGLE_PIN(x)    (GPIOF->BIR = (x))
+#define ALD_GPIOG_TOGGLE_PIN(x)    (GPIOG->BIR = (x))
+#define ALD_GPIOH_TOGGLE_PIN(x)    (GPIOH->BIR = (x))
+
+/* Read IO level */
+#define ALD_GPIOA_READ_PIN(x)      ((GPIOA->DIN & (x)) ? 1 : 0)
+#define ALD_GPIOB_READ_PIN(x)      ((GPIOB->DIN & (x)) ? 1 : 0)
+#define ALD_GPIOC_READ_PIN(x)      ((GPIOC->DIN & (x)) ? 1 : 0)
+#define ALD_GPIOD_READ_PIN(x)      ((GPIOD->DIN & (x)) ? 1 : 0)
+#define ALD_GPIOE_READ_PIN(x)      ((GPIOE->DIN & (x)) ? 1 : 0)
+#define ALD_GPIOF_READ_PIN(x)      ((GPIOF->DIN & (x)) ? 1 : 0)
+#define ALD_GPIOG_READ_PIN(x)      ((GPIOG->DIN & (x)) ? 1 : 0)
+#define ALD_GPIOH_READ_PIN(x)      ((GPIOH->DIN & (x)) ? 1 : 0)
+
+/* Set IO as high */
+#define ALD_GPIOA_SET_PIN(x)       (GPIOA->BSRR = (x))
+#define ALD_GPIOB_SET_PIN(x)       (GPIOB->BSRR = (x))
+#define ALD_GPIOC_SET_PIN(x)       (GPIOC->BSRR = (x))
+#define ALD_GPIOD_SET_PIN(x)       (GPIOD->BSRR = (x))
+#define ALD_GPIOE_SET_PIN(x)       (GPIOE->BSRR = (x))
+#define ALD_GPIOF_SET_PIN(x)       (GPIOF->BSRR = (x))
+#define ALD_GPIOG_SET_PIN(x)       (GPIOG->BSRR = (x))
+#define ALD_GPIOH_SET_PIN(x)       (GPIOH->BSRR = (x))
+
+/* Set IO as low */
+#define ALD_GPIOA_RESET_PIN(x)     (GPIOA->BSRR = ((x) << 16))
+#define ALD_GPIOB_RESET_PIN(x)     (GPIOB->BSRR = ((x) << 16))
+#define ALD_GPIOC_RESET_PIN(x)     (GPIOC->BSRR = ((x) << 16))
+#define ALD_GPIOD_RESET_PIN(x)     (GPIOD->BSRR = ((x) << 16))
+#define ALD_GPIOE_RESET_PIN(x)     (GPIOE->BSRR = ((x) << 16))
+#define ALD_GPIOF_RESET_PIN(x)     (GPIOF->BSRR = ((x) << 16))
+#define ALD_GPIOG_RESET_PIN(x)     (GPIOG->BSRR = ((x) << 16))
+#define ALD_GPIOH_RESET_PIN(x)     (GPIOH->BSRR = ((x) << 16))
 /**
   * @}
   */

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h

@@ -320,7 +320,7 @@ typedef struct i2c_handle_s {
 #define I2C_GET_IT_SOURCE(x, y) ((((x)->perh->IFM & (y))  == (y)) ? SET : RESET)
 #define I2C_GET_FLAG(x, y) ((((x)->perh->STAT) & ((y) & I2C_FLAG_MASK)) != RESET)
 #define I2C_MASTER_GET_DIR(x) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK))
-#define I2C_SLAVE_GET_DIR(x) (READ_BIT(hperh->perh->STAT, I2C_STAT_DIR_MSK))
+#define I2C_SLAVE_GET_DIR(x) (READ_BIT(((x)->perh->STAT), I2C_STAT_DIR_MSK))
 #define I2C_ENABLE(x)  (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK))
 #define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK))
 /**

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h

@@ -841,18 +841,15 @@ do {						\
 					 ((y) == TIMER_CHANNEL_3)   || \
 					 ((y) == TIMER_CHANNEL_4))))
 
-#define IS_TIMER_CCXN_INSTANCE(x, y)	((((x) == NULL)          || \
-					 ((x) == NULL))         && \
+#define IS_TIMER_CCXN_INSTANCE(x, y)	((((x) == NULL))           && \
                                          (((y) == TIMER_CHANNEL_1) || \
                                          ((y) == TIMER_CHANNEL_2)  || \
                                          ((y) == TIMER_CHANNEL_3)  || \
                                          ((y) == TIMER_CHANNEL_4)))
 
-#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x)	(((x) == NULL) || \
-                                                 ((x) == NULL))
+#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x)	(((x) == NULL))
 
-#define IS_TIMER_BREAK_INSTANCE(x) (((x) == NULL) || \
-                                    ((x) == NULL))
+#define IS_TIMER_BREAK_INSTANCE(x) (((x) == NULL))
 
 #define IS_TIMER_CLOCK_DIVISION_INSTANCE(x)	IS_TIMER_CC2_INSTANCE(x)
 
@@ -1050,7 +1047,7 @@ void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch);
 void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch);
 void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
 void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
-void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq);
+void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint32_t freq);
 void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty);
 void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch);
 #ifdef ALD_DMA

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h

@@ -213,16 +213,6 @@ typedef struct {
 	uint8_t addr;		/**< Address for compare */
 } uart_rs485_config_t;
 
-/**
-  * @brief Smart_card clock division
-  */
-typedef enum {
-	SCARD_CLOCK_DIV1 = 0x0U,	/**< No prescaler is used */
-	SCARD_CLOCK_DIV2 = 0x1U,	/** Clock is divided by 2 */
-	SCARD_CLOCK_DIV4 = 0x2U,	/** Clock is divided by 4 */
-	SCARD_CLOCK_DIV6 = 0x3U,	/** Clock is divided by 6 */
-} scard_clk_div_t;
-
 /**
   * @brief Smart_card Rx/Tx handle retry time
   */
@@ -244,7 +234,7 @@ typedef struct {
 	uint8_t block_len;       /**< Specifies the data block length.*/
 	uint8_t pt;	         /**< Specifies the protect time*/
 	scard_retry_t retry;	 /**< Specifies retry time.*/
-	scard_clk_div_t clk_div; /**< Specifies the clock division.*/
+	uint8_t clk_div;         /**< Specifies the clock division.*/
 	type_func_t clk_out;     /**< Specifies the clock out */
 } uart_scard_config_t;
 
@@ -458,10 +448,7 @@ typedef enum {
                                  ((x) == UART_IF_TFTH)    || \
                                  ((x) == UART_IF_TFEMPTY) || \
                                  ((x) == UART_IF_TFOVER))
-#define IS_UART_SCARD_CLK(x) (((x) == SCARD_CLOCK_DIV1) || \
-                              ((x) == SCARD_CLOCK_DIV2) || \
-                              ((x) == SCARD_CLOCK_DIV4) || \
-                              ((x) == SCARD_CLOCK_DIV6))
+#define IS_UART_SCARD_CLK(x) (((x) <= 0x1F))
 #define IS_UART_BAUDRATE(x)	(((x) > 0) && ((x) < 0x44AA21))
 #define IS_UART_DATA(x)		((x) <= 0x1FF)
 

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h

@@ -130,7 +130,7 @@ do {			\
   */
 #define MCU_UID0_ADDR	0x000803E0U
 #define MCU_UID1_ADDR	0x000803E8U
-#define MCU_UID2_ADDR	0x000803F0U
+#define MCU_UID2_ADDR	0x000803ECU
 #define MCU_CHIPID_ADDR	0x000803F8U
 #define DWT_CR		*(uint32_t *)0xE0001000U
 #define DWT_CYCCNT	*(volatile uint32_t *)0xE0001004U
@@ -170,6 +170,7 @@ void ald_systick_interval_select(systick_interval_t value);
 /* Peripheral Control functions */
 void ald_inc_tick(void);
 void ald_systick_irq_cbk(void);
+void ald_delay_us(__IO uint32_t delay);
 void ald_delay_ms(__IO uint32_t delay);
 uint32_t ald_get_tick(void);
 void ald_suspend_tick(void);

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c

@@ -133,19 +133,30 @@ ald_status_t ald_adc_init(adc_handle_t *hperh)
 
 	MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont << ADC_CON1_CM_POS);
 	MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan << ADC_CON0_SCANEN_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS);
+	
+	ADC0->CCR = 0;
+	MODIFY_REG(ADC0->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS);
+	MODIFY_REG(ADC0->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS);
 	/* if the ADC clock less than 1MHz,PWRMOD should be disable*/
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS);
+	MODIFY_REG(ADC0->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS);
+	MODIFY_REG(ADC0->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS);
+	MODIFY_REG(ADC0->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS);
+	MODIFY_REG(ADC0->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS);
+	MODIFY_REG(ADC0->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS);
+	MODIFY_REG(ADC0->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS);
+	MODIFY_REG(ADC0->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS);
+
+	if (hperh->perh == ADC1)
+		ADC1->CCR = ADC0->CCR;
+	
+	MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS);
 	MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.div << ADC_CCR_CKDIV_POSS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS);
-	MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS);
-	MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS);
+	/* Enable adc calibration */
+	SET_BIT(ADC0->CCR, ADC_CCR_TRMEN_MSK);
+	SET_BIT(ADC1->CCR, ADC_CCR_TRMEN_MSK);
+
+	
+MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS);
 	ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE);
 	ADC_ENABLE(hperh);
 
@@ -430,12 +441,12 @@ static void adc_dma_timer_trigger_cplt(void *arg)
 }
 
 /**
-  * @brief  Config Timer trigger adc function
+  * @brief  Config timer trigger adc insert channel conversion.
   * @param  config: Pointer to a adc_timer_config_t structure that
   *         contains the configuration information for the specified function.
   * @retval Status, see @ref ald_status_t.
   */
-ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config)
+ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config)
 {
 	config->h_pis.perh               = PIS;
 	config->h_pis.init.producer_clk  = PIS_CLK_PCLK1;
@@ -467,13 +478,13 @@ ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config)
 	#endif
 
 	if (config->p_adc == ADC0)
-		config->h_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL;
+		config->h_pis.init.consumer_trig = PIS_CH7_ADC0_INSERT;
 	else
 		return ERROR;
 
 	ald_pis_create(&config->h_pis);
 
-	/* Initialize TIMER0 */
+	/* Initialize TIMER */
 	config->h_timer.perh           = config->p_timer;
 	config->h_timer.init.prescaler = 0;
 	config->h_timer.init.mode      = TIMER_CNT_MODE_UP;
@@ -486,7 +497,7 @@ ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config)
 	config->h_adc.init.align      = ADC_DATAALIGN_RIGHT;
 	config->h_adc.init.scan       = DISABLE;
 	config->h_adc.init.cont       = DISABLE;
-	config->h_adc.init.nch_nr     = ADC_NCH_NR_1;
+	config->h_adc.init.ich_nr     = ADC_ICH_NR_1;
 	config->h_adc.init.disc       = ADC_ALL_DISABLE;
 	config->h_adc.init.disc_nr    = ADC_DISC_NR_1;
 	config->h_adc.init.data_bit   = ADC_CONV_BIT_12;
@@ -500,49 +511,30 @@ ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config)
 	config->h_adc.error_cbk       = NULL;
 	config->h_adc.ovr_cbk         = NULL;
 	ald_adc_init(&config->h_adc);
-
-
-
-	config->h_adc.perh->CON1 |= 0x10000000;
-	config->config.ch   = config->adc_ch;
-	config->config.idx  = ADC_NCH_IDX_1;
-	config->config.samp = ADC_SAMPLETIME_4;
- 	ald_adc_normal_channel_config(&config->h_adc, &config->config);
-
-	config->h_dma.cplt_cbk = adc_dma_timer_trigger_cplt;
-	config->h_dma.cplt_arg = config;
-	config->h_dma.err_cbk  = adc_dma_error;
-	config->h_dma.err_arg  = &config->h_adc;
-
-	ald_dma_config_struct(&config->h_dma.config);
-	config->h_dma.perh              = DMA0;
-	config->h_dma.config.src        = (void *)&config->h_adc.perh->NCHDR;
-	config->h_dma.config.dst        = (void *)config->buf;
-	config->h_dma.config.size       = config->size;
-	config->h_dma.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	config->h_dma.config.src_inc    = DMA_DATA_INC_NONE;
-	config->h_dma.config.dst_inc    = DMA_DATA_INC_HALFWORD;
-	config->h_dma.config.msel       = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1;
-	config->h_dma.config.msigsel    = DMA_MSIGSEL_ADC;
-	config->h_dma.config.burst      = ENABLE;
-	config->h_dma.config.channel    = config->dma_ch;
-	ald_dma_config_basic(&config->h_dma);
-
-	SET_BIT(config->h_adc.perh->CON1, ADC_CON1_DMA_MSK);
+	
+	config->h_adc.perh->CON1   |= 0x00100000;   /* rising edge trigger insert channel convert */
+	config->i_config.ch         = config->adc_ch;
+	config->i_config.idx        = ADC_ICH_IDX_1;
+	config->i_config.samp       = ADC_SAMPLETIME_4;
+	config->i_config.nr         = ADC_ICH_NR_1;
+	config->i_config.auto_m     = DISABLE;
+	ald_adc_insert_channel_config(&config->h_adc, &config->i_config);
+	
 	ADC_ENABLE(&config->h_adc);
 	ald_timer_base_start(&config->h_timer);
-
+	
 	return OK;
 }
 
 
+
 /**
-  * @brief  Config timer trigger adc insert channel conversion.
+  * @brief  Config Timer trigger adc function
   * @param  config: Pointer to a adc_timer_config_t structure that
   *         contains the configuration information for the specified function.
   * @retval Status, see @ref ald_status_t.
   */
-ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config)
+ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config)
 {
 	config->h_pis.perh               = PIS;
 	config->h_pis.init.producer_clk  = PIS_CLK_PCLK1;
@@ -574,7 +566,7 @@ ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config)
 	#endif
 
 	if (config->p_adc == ADC0)
-		config->h_pis.init.consumer_trig = PIS_CH7_ADC0_INSERT;
+		config->h_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL;
 	else
 		return ERROR;
 
@@ -593,7 +585,7 @@ ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config)
 	config->h_adc.init.align      = ADC_DATAALIGN_RIGHT;
 	config->h_adc.init.scan       = DISABLE;
 	config->h_adc.init.cont       = DISABLE;
-	config->h_adc.init.ich_nr     = ADC_ICH_NR_1;
+	config->h_adc.init.nch_nr     = ADC_NCH_NR_1;
 	config->h_adc.init.disc       = ADC_ALL_DISABLE;
 	config->h_adc.init.disc_nr    = ADC_DISC_NR_1;
 	config->h_adc.init.data_bit   = ADC_CONV_BIT_12;
@@ -608,12 +600,32 @@ ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config)
 	config->h_adc.ovr_cbk         = NULL;
 	ald_adc_init(&config->h_adc);
 
-	config->h_adc.perh->CON1 |= 0x00100000;	/* rising edge trigger insert channel convert */
-	config->i_config.ch       = config->adc_ch;
-	config->i_config.idx      = ADC_ICH_IDX_1;
-	config->i_config.samp     = ADC_SAMPLETIME_4;
-	config->i_config.auto_m   = DISABLE;
- 	ald_adc_insert_channel_config(&config->h_adc, &config->i_config);
+	config->h_adc.perh->CON1 |= 0x10000000;
+	config->config.ch   = config->adc_ch;
+	config->config.idx  = ADC_NCH_IDX_1;
+	config->config.samp = ADC_SAMPLETIME_4;
+ 	ald_adc_normal_channel_config(&config->h_adc, &config->config);
+
+	config->h_dma.cplt_cbk = adc_dma_timer_trigger_cplt;
+	config->h_dma.cplt_arg = config;
+	config->h_dma.err_cbk  = adc_dma_error;
+	config->h_dma.err_arg  = &config->h_adc;
+
+	ald_dma_config_struct(&config->h_dma.config);
+	config->h_dma.perh              = DMA0;
+	config->h_dma.config.src        = (void *)&config->h_adc.perh->NCHDR;
+	config->h_dma.config.dst        = (void *)config->buf;
+	config->h_dma.config.size       = config->size;
+	config->h_dma.config.data_width = DMA_DATA_SIZE_HALFWORD;
+	config->h_dma.config.src_inc    = DMA_DATA_INC_NONE;
+	config->h_dma.config.dst_inc    = DMA_DATA_INC_HALFWORD;
+	config->h_dma.config.msel       = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1;
+	config->h_dma.config.msigsel    = DMA_MSIGSEL_ADC;
+	config->h_dma.config.burst      = ENABLE;
+	config->h_dma.config.channel    = config->dma_ch;
+	ald_dma_config_basic(&config->h_dma);
+
+	SET_BIT(config->h_adc.perh->CON1, ADC_CON1_DMA_MSK);
 	ADC_ENABLE(&config->h_adc);
 	ald_timer_base_start(&config->h_timer);
 

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c

@@ -99,6 +99,7 @@
 static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num);
 static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err);
 static ald_status_t __can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num);
+static int __can_rx_check(can_handle_t *hperh, can_rx_fifo_t num);
 /**
   * @}
   */
@@ -138,7 +139,7 @@ ald_status_t ald_can_init(can_handle_t *hperh)
 	assert_param(IS_FUNC_STATE(hperh->init.ttcm));
 	assert_param(IS_FUNC_STATE(hperh->init.abom));
 	assert_param(IS_FUNC_STATE(hperh->init.awk));
-	assert_param(IS_FUNC_STATE(hperh->init.abom));
+	assert_param(IS_FUNC_STATE(hperh->init.artx));
 	assert_param(IS_FUNC_STATE(hperh->init.rfom));
 	assert_param(IS_FUNC_STATE(hperh->init.txmp));
 	assert_param(IS_CAN_MODE(hperh->init.mode));
@@ -442,6 +443,9 @@ ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *
 		}
 	}
 
+	if (__can_rx_check(hperh, num))
+		return ERROR;
+
 	stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS);
 	exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS);
 	msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS);

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c

@@ -290,12 +290,11 @@ ald_status_t ald_cmu_clock_config_default(void)
 		return ERROR;
 	}
 
-	WRITE_REG(CMU->CFGR, 0x0);
-	CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK);	/* Select 24Mhz */
+	WRITE_REG(CMU->CFGR, 0x4000000);	/* Select 24MHz */
 
 	tmp = READ_REG(CMU->CLKENR);
-	/* Enable HRC/LRC/LOSC */
-	SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK | CMU_CLKENR_LOSCEN_MSK);
+	/* Enable HRC/LRC */
+	SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK);
 	WRITE_REG(CMU->CLKENR, tmp);
 	/* Reset LRC */
 	for (cnt = 0; cnt < 10000; ++cnt);

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c

@@ -186,19 +186,20 @@ void ald_dma_irq_handler(void)
 	uint32_t i, reg = DMA0->IFLAG;
 
 	for (i = 0; i < DMA_CH_COUNT; ++i) {
-		if (READ_BIT(reg, (1 << i))) {
+		if (READ_BIT(reg, (1U << i))) {
+			DMA0->ICFR    = (1U << i);
+			DMA0->CHENCLR = (1U << i);
+
 			if (dma0_cbk[i].cplt_cbk != NULL)
 				dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg);
-
-			ald_dma_clear_flag_status(DMA0, i);
 		}
 	}
 
 	if (READ_BIT(reg, (1U << DMA_ERR))) {
-		ald_dma_clear_flag_status(DMA0, DMA_ERR);
+		DMA0->ICFR = (1U << DMA_ERR);
 
 		for (i = 0; i < DMA_CH_COUNT; ++i) {
-			if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL))
+			if (dma0_cbk[i].err_cbk != NULL)
 				dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg);
 		}
 	}

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c

@@ -415,9 +415,9 @@ void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val)
 	assert_param(IS_GPIO_PIN(pin));
 
 	if ((val & (0x01)) == 0x00)
-		CLEAR_BIT(GPIOx->DOUT, pin);
+		GPIOx->BSRR = pin << 16U;
 	else
-		SET_BIT(GPIOx->DOUT, pin);
+		GPIOx->BSRR = pin;
 
 	return;
 }

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c

@@ -305,7 +305,9 @@ ald_status_t ald_nand_read_page_8b(nand_handle_t *hperh, nand_address_t *addr, u
 			*(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00);
 		}
 
-		/* Get Data into Buffer */    
+        ald_delay_us(25);  /*ÑÓʱ25us,nand flash ÊÖ²áÖеÄ×î´óÖµ*/
+        
+        /* Get Data into Buffer */    
 		for (; index < size; index++) {
 			*(uint8_t *)buf++ = *(uint8_t *)deviceaddr;
 		}

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c

@@ -737,7 +737,7 @@ void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
   * @param  freq: PWM freq to set
   * @retval None
   */
-void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq)
+void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint32_t freq)
 {
 	uint32_t _arr;
 
@@ -758,12 +758,12 @@ void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq)
   *		@arg TIMER_CHANNEL_2: TIMER Channel 2 selected
   *		@arg TIMER_CHANNEL_3: TIMER Channel 3 selected
   *		@arg TIMER_CHANNEL_4: TIMER Channel 4 selected
-  * @param  duty: PWM duty to set
+  * @param  duty: PWM duty to set [0, 100]
   * @retval None
   */
 void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty)
 {
-	uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1;
+	uint32_t tmp = (hperh->init.period + 1) * duty / 100;
 
 	if (ch == TIMER_CHANNEL_1)
 		WRITE_REG(hperh->perh->CCVAL1, tmp);

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c

@@ -144,12 +144,29 @@ static void uart_dma_send_cplt(void *arg)
   */
 static void uart_dma_recv_cplt(void *arg)
 {
+	uint32_t stat = 0;
+
 	uart_handle_t *hperh = (uart_handle_t *)arg;
 	hperh->tx_count = hperh->tx_size;
 
 	ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE);
 	hperh->rx_count = 0;
 	CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
+	stat = hperh->perh->STAT;
+
+	/* Handle parity error */
+	if ((READ_BIT(stat, UART_STATUS_PERR)) != RESET)
+		hperh->err_code |= UART_ERROR_PE;
+
+	/* Handle frame error */
+	if ((READ_BIT(stat, UART_STATUS_FERR)) != RESET)
+		hperh->err_code |= UART_ERROR_FE;
+
+	/* Handle rx overflow error */
+	if ((READ_BIT(stat, UART_STATUS_RFOERR)) != RESET) {
+		hperh->err_code |= UART_ERROR_ORE;
+		UART_FIFO_RX_RESET(hperh);
+	}
 
 	if (hperh->rx_cplt_cbk)
 		hperh->rx_cplt_cbk(hperh);
@@ -552,12 +569,16 @@ ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui
   */
 ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
 {
+	uint32_t stat = 0;
+	uint32_t err  = 0;
+	uint32_t tick = 0;
+
 	assert_param(IS_UART_ALL(hperh->perh));
 
 	if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
 		return BUSY;
 
-	if ((buf == NULL) || (size == 0))
+	if ((buf == NULL) || (size == 0) || (timeout == 0))
 		return  ERROR;
 
 	__LOCK(hperh);
@@ -568,15 +589,47 @@ ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui
 	hperh->rx_count = 0;
 	SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
 
+	err = (UART_STATUS_PERR | UART_STATUS_FERR | UART_STATUS_RFOERR);
+
 	while (size-- > 0) {
-		if (uart_wait_flag(hperh, UART_STATUS_RFTH, SET, timeout) != OK) {
-			__UNLOCK(hperh);
-			hperh->state = UART_STATE_READY;
-			return TIMEOUT;
+		tick = ald_get_tick();
+
+		/* Waiting for flag */
+		while (1) {
+			stat = hperh->perh->STAT;
+			if (READ_BIT(stat, UART_STATUS_RFTH) != RESET)
+				break;
+
+			if (((ald_get_tick()) - tick) > timeout) {
+				__UNLOCK(hperh);
+				hperh->state = UART_STATE_READY;
+				return TIMEOUT;
+			}
 		}
+		if ((stat & err) == RESET) {
+			*buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF);
+			hperh->rx_count++;
+		}
+		else {
+			/* Handle parity error */
+			if ((READ_BIT(stat, UART_STATUS_PERR)) != RESET)
+				hperh->err_code |= UART_ERROR_PE;
 
-		*buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF);
-		hperh->rx_count++;
+			/* Handle frame error */
+			if ((READ_BIT(stat, UART_STATUS_FERR)) != RESET)
+				hperh->err_code |= UART_ERROR_FE;
+
+			/* Handle rx overflow error */
+			if ((READ_BIT(stat, UART_STATUS_RFOERR)) != RESET) {
+				hperh->err_code |= UART_ERROR_ORE;
+				UART_FIFO_RX_RESET(hperh);
+			}
+
+			CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
+			__UNLOCK(hperh);
+
+			return ERROR;
+		}
 	}
 
 	CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
@@ -898,7 +951,7 @@ ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t s
 		hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR;
 	}
 
-	hperh->hdmatx.config.burst   = ENABLE;
+	hperh->hdmarx.config.burst   = ENABLE;
 	hperh->hdmarx.config.channel = channel;
 
 	if (hperh->init.mode == UART_MODE_RS485) {
@@ -915,9 +968,9 @@ ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t s
 	else if (hperh->perh == UART3)
 		hperh->hdmarx.config.msel = DMA_MSEL_UART3;
 	else if (hperh->perh == UART4)
-		hperh->hdmatx.config.msel = DMA_MSEL_UART4;
+		hperh->hdmarx.config.msel = DMA_MSEL_UART4;
 	else if (hperh->perh == UART5)
-		hperh->hdmatx.config.msel = DMA_MSEL_UART5;
+		hperh->hdmarx.config.msel = DMA_MSEL_UART5;
 	else
 		;
 
@@ -980,27 +1033,35 @@ ald_status_t ald_uart_dma_stop(uart_handle_t *hperh)
   */
 void ald_uart_irq_handler(uart_handle_t *hperh)
 {
+	uint32_t stat = 0;
+
 	assert_param(IS_UART_ALL(hperh->perh));
 
+	stat = hperh->perh->STAT;
+
 	/* Handle parity error */
-	if (((ald_uart_get_status(hperh, UART_STATUS_PERR)) != RESET) && \
+	if (((READ_BIT(stat, UART_STATUS_PERR)) != RESET) && \
 		(ald_uart_get_state(hperh)) == UART_STATE_RX_MASK)
 		hperh->err_code |= UART_ERROR_PE;
 
 	/* Handle frame error */
-	if (((ald_uart_get_status(hperh, UART_STATUS_FERR)) != RESET) && \
+	if (((READ_BIT(stat, UART_STATUS_FERR)) != RESET) && \
 		(ald_uart_get_state(hperh)) == UART_STATE_RX_MASK)
 		hperh->err_code |= UART_ERROR_FE;
 
 	/* Handle rx overflow error */
-	if (((ald_uart_get_status(hperh, UART_STATUS_RFOERR)) != RESET) && \
-		(ald_uart_get_state(hperh)) == UART_STATE_RX_MASK)
+	if (((READ_BIT(stat, UART_STATUS_RFOERR)) != RESET) && \
+		(ald_uart_get_state(hperh)) == UART_STATE_RX_MASK) {
 		hperh->err_code |= UART_ERROR_ORE;
+		UART_FIFO_RX_RESET(hperh);
+	}
 
 	/* Handle tx overflow error */
-	if (((ald_uart_get_status(hperh, UART_STATUS_TFOERR)) != RESET) && \
-		(ald_uart_get_state(hperh)) == UART_STATE_TX_MASK)
+	if (((READ_BIT(stat, UART_STATUS_TFOERR)) != RESET) && \
+		(ald_uart_get_state(hperh)) == UART_STATE_TX_MASK) {
 		hperh->err_code |= UART_ERROR_ORE;
+		UART_FIFO_TX_RESET(hperh);
+	}
 
 	/* Receive */
 	if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RFTH)) != RESET) {

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c

@@ -4,10 +4,14 @@
   * @file    utils.c
   * @brief   This file contains the Utilities functions/types for the driver.
   *
-  * @version V1.0
-  * @date    07 Nov 2019
+  * @version V1.1
+  * @date    13 Apr 2021
   * @author  AE Team
   * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          07 Nov 2019     AE Team         The first version
+  *          13 Apr 2021     AE Team         Add API: sys_config()
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
@@ -31,7 +35,8 @@
 #include <string.h>
 #include "utils.h"
 #include "ald_dma.h"
-#include "ald_cmu.h"
+#include "ald_cmu.h"  
+#include "ald_iap.h"
 
 
 /** @defgroup ES32FXXX_ALD EASTSOFT ES32F3xx ALD
@@ -152,9 +157,9 @@ void ald_cmu_init(void)
 __weak void ald_tick_init(uint32_t prio)
 {
 	/* Configure the SysTick IRQ */
-	NVIC_SetPriority(SysTick_IRQn, prio);
 	SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS);
-
+	NVIC_SetPriority(SysTick_IRQn, prio);
+	
 	return;
 }
 
@@ -246,6 +251,31 @@ __weak uint32_t ald_get_tick(void)
 {
 	return lib_tick;
 }
+ 
+/**
+  * @brief  This function provides accurate delay (in milliseconds) based
+  *         on variable incremented.
+  * @note   In the default implementation, SysTick timer is the source of time base.
+  *         It is used to generate interrupts at regular time intervals where lib_tick
+  *         is incremented.
+  * @note   This function is declared as __weak to be overwritten in case of other
+  *         implementations in user file.
+  * @param  delay: specifies the delay time length, in microseconds(us).
+  * @retval None
+  */
+__weak void ald_delay_us(__IO uint32_t delay)
+{
+    uint32_t start, now, delta, reload, us_tick;
+    start = SysTick->VAL;
+    reload = SysTick->LOAD;
+    us_tick = ald_cmu_get_sys_clock() / 1000000UL;
+    do
+    {
+        now = SysTick->VAL;
+        delta = (start > now) ? (start - now) : (reload + start - now);
+    }
+    while (delta <  (us_tick * delay));
+}
 
 /**
   * @brief  This function provides accurate delay (in milliseconds) based
@@ -467,6 +497,205 @@ uint32_t ald_mcu_get_chipid(void)
 {
 	return (uint32_t)*(uint32_t *)MCU_CHIPID_ADDR;
 }
+
+/**
+  * @brief  Bypass bootroom and set VR1_Ref 0xA
+  * @retval None
+  */
+void sys_config(void)
+{
+	uint32_t i = 0, tmp = 0;
+	uint8_t err = 0, flag = 0;
+	uint32_t inf014 = 0, inf0154 = 0;
+	uint8_t cnt = 4;
+
+	uint32_t *inf0_addr = (uint32_t *)0x20003C00;
+	/* read bootroom cfg register */
+	inf014  = *((uint32_t *)(0x80000 + 56));
+	/* read VR1_VREF register */
+	inf0154 = *((uint32_t *)(0x80000 + 616));
+
+	if (inf0154 == 0xFFFFFFFF)
+		while(1);
+	
+	/* if bypass bootroom */
+	if ((0xFFFFFFFF != inf014)) { 
+		/* change cfg_boot value = 0xffff */
+		inf014 = 0xFFFFFFFF; 
+		flag   = 0x1;
+	}
+
+	/* change CFG_VR1_VREF value, FLASH ref 0xA */
+	tmp = (inf0154 >> 8) & 0xF;
+	if (0xA != tmp) {
+		inf0154 &= ~(0xF << 8);
+		inf0154 |= (0xA << 8);
+		inf0154 = (inf0154 & (0x0000FFFF)) | ((~(inf0154 & 0xFFFF)) << 16);
+		flag = 0x1;
+	}
+	
+	/* if flag reset, return */
+	if (0x0 == flag)
+		return;
+	
+	/* 0x80000, 256words,INFO0 value */
+	for (i = 0; i < 256; i++)
+		inf0_addr[i] = *((uint32_t *)(0x80000 + i * 4));
+
+	/* refresh value */
+	inf0_addr[14]  = inf014;
+	inf0_addr[154] = inf0154;
+
+	while(--cnt) {
+		err = 0;
+		/* unlock */
+		*((volatile uint32_t *)(0x40080000)) = 0x55AA6996;
+		*((volatile uint32_t *)(0x40080100)) = 0x5A962814;
+		*((volatile uint32_t *)(0x40080100)) = 0xE7CB69A5;	
+
+		/* erase */
+		if (ald_iap_erase_page(0x80000) == OK) {
+			/* program 256*4bytes, info0 */
+			if (ald_iap_program_words(0x80000, (uint8_t *)inf0_addr, 1024, 0) == OK) {
+				/* check */
+				for (i = 0; i < 256; i++) {
+					if (inf0_addr[i] != *((uint32_t *)(0x80000 + i * 4))) {
+						err = 1;
+						break;;
+					}
+				}
+				if (err == 0) { 
+					/* lock */
+					*((volatile uint32_t *)(0x40080100)) = 0x123456;
+					*((volatile uint32_t *)(0x40080100)) = 0x123456;
+					*((volatile uint32_t *)(0x40080000)) = 0x123456;
+					return;
+				}
+			}
+			else {
+				err = 1;
+			}
+		}
+		else {
+			err = 1;
+		}
+	}
+
+	if (err) {
+		ald_iap_erase_page(0x80000);
+		/* lock */
+		*((volatile uint32_t *)(0x40080100)) = 0x123456;
+		*((volatile uint32_t *)(0x40080100)) = 0x123456;
+		*((volatile uint32_t *)(0x40080000)) = 0x123456;
+		while(1);
+	}
+}
+
+/**
+  * @brief  ADC adjust parameter config
+  * @retval None
+  */
+void adc_config(void)
+{
+	uint32_t inf0176 = 0, inf0178 = 0;
+	uint32_t inf0250 = 0, inf0251 = 0;
+	uint32_t inf0242 = 0, i = 0;
+	uint8_t flag = 0, err = 0;
+	uint8_t cnt = 4;
+	/* ram store inf0 1k buffer, 15k ~ 16k */
+	uint32_t *inf0_addr = (uint32_t *)0x20003C00;
+
+	/* Read ADC_GE */
+	inf0242 = *((uint32_t *)(0x80000 + 968));
+
+	if (0xF5230ADC == inf0242)  return;
+
+	/* read Lot ID */
+	inf0250 = *((uint32_t *)(0x80000 + 1000));
+	inf0251 = *((uint32_t *)(0x80000 + 1004));
+	inf0251 = (inf0251 & 0xFFFF0000) >> 16;
+
+	/* read CFG_ADC0DA/CFG_ADC1DA */
+	inf0176 = *((uint32_t *)(0x80000 + 704));
+	inf0178 = *((uint32_t *)(0x80000 + 712));
+
+	switch(inf0250) {
+		case 0x45465537:
+			if ((inf0251 == 0x3034) || (inf0251 == 0x3035))
+				flag = 1;
+			break;
+		case 0x45503931:
+			if ((inf0251 == 0x3732) || (inf0251 == 0x3734))
+				flag = 1;
+			break;
+		case 0x45503935:
+			if ((inf0251 == 0x3837) || (inf0251 == 0x3839))
+				flag = 1;
+			break;
+		default:
+			break;
+	}
+
+	if (!flag)  return;
+        
+	inf0176 ^= (0x1 << 15);
+	inf0176  = (inf0176 & 0x0000FFFF) | ((~(inf0176 & 0xFFFF)) << 16);
+
+	inf0178 ^= (0x1 << 15);
+	inf0178  = (inf0178 & 0x0000FFFF) | ((~(inf0178 & 0xFFFF)) << 16);
+
+	/* 0x80000, 256words,INFO0 value */
+	for (i = 0; i < 256; i++)
+		inf0_addr[i] = *((uint32_t *)(0x80000 + i * 4));
+
+	inf0_addr[176] = inf0176;
+	inf0_addr[178] = inf0178;
+	inf0_addr[242] = 0xF5230ADC;
+
+	while(--cnt) {
+		err = 0;
+		/* unlock */
+		*((volatile uint32_t *)(0x40080000)) = 0x55AA6996;
+		*((volatile uint32_t *)(0x40080100)) = 0x5A962814;
+		*((volatile uint32_t *)(0x40080100)) = 0xE7CB69A5;	
+
+		/* erase */
+		if (ald_iap_erase_page(0x80000) == OK) {
+			/* program 256*4bytes, info0 */
+			if (ald_iap_program_words(0x80000, (uint8_t *)inf0_addr, 1024, 0) == OK) {
+				/* check */
+				for (i = 0; i < 256; i++) {
+					if (inf0_addr[i] != *((uint32_t *)(0x80000 + i * 4))) {
+						err = 1;
+						break;;
+					}
+				}
+				if (err == 0) { 
+					/* lock */
+					*((volatile uint32_t *)(0x40080100)) = 0x123456;
+					*((volatile uint32_t *)(0x40080100)) = 0x123456;
+					*((volatile uint32_t *)(0x40080000)) = 0x123456;
+					return;
+				}
+			}
+			else {
+				err = 1;
+			}
+		}
+		else {
+			err = 1;
+		}
+	}
+
+	if (err) {
+		ald_iap_erase_page(0x80000);
+		/* lock */
+		*((volatile uint32_t *)(0x40080100)) = 0x123456;
+		*((volatile uint32_t *)(0x40080100)) = 0x123456;
+		*((volatile uint32_t *)(0x40080000)) = 0x123456;
+		while(1);
+	}
+}
 /**
   * @}
   */