Merge pull request #17 from RT-Thread/master

pr

bsp/apollo2/board/rtc.c

@@ -25,6 +25,7 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 #include "am_mcu_apollo.h"
+#include <sys/time.h>
 
 #define XT              1
 #define LFRC            2
@@ -78,13 +79,13 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
             /* Seconds 0-59 : the 0-59 range */
             time_temp.tm_sec = hal_time.ui32Second;
 
-            *time = mktime(&time_temp);
+            *time = timegm(&time_temp);
 
             break;
 
         case RT_DEVICE_CTRL_RTC_SET_TIME:
             time = (time_t *)args;
-            time_new = localtime(time);
+            time_new = gmtime(time);
 
             hal_time.ui32Hour = time_new->tm_hour;
             hal_time.ui32Minute = time_new->tm_min;

bsp/at32/Libraries/rt_drivers/drv_rtc.c

@@ -10,6 +10,7 @@
 
 #include "board.h"
 #include <rtthread.h>
+#include <sys/time.h>
 
 #ifdef BSP_USING_RTC
 
@@ -42,7 +43,7 @@ static time_t get_rtc_timestamp(void)
     tm_new.tm_year = ERTC_DateStruct.ERTC_Year + 100;
 
     LOG_D("get rtc time.");
-    return mktime(&tm_new);
+    return timegm(&tm_new);
 #else
     return RTC_GetCounter();
 #endif
@@ -56,7 +57,7 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
 
     struct tm *p_tm;
 
-    p_tm = localtime(&time_stamp);
+    p_tm = gmtime(&time_stamp);
     if (p_tm->tm_year < 100)
     {
         return -RT_ERROR;

bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c

@@ -43,18 +43,18 @@ void adpll_init(uint8_t out_spr)
     PLL1CON |= BIT(18);                             //pll1 sdm enable
 
     if (out_spr) {
-        CLKCON2  |= BIT(4) | BIT(7);                 //adpll_div = 10
+        CLKCON2  |= BIT(4) | BIT(7);                //adpll_div = 10
         PLL1DIV = (245.76 * 65536) / 26;            //245.76Mhz for 48K
         // sys.aupll_type = 1;
     } else {
-        CLKCON2  |= BIT(5) | BIT(7);                 //adpll_div = 11
+        CLKCON2  |= BIT(5) | BIT(7);                //adpll_div = 11
         PLL1DIV = (248.3712 * 65536) / 26;          //248.3712MHz for 44.1k
         // sys.aupll_type = 0;
     }
     hal_mdelay(1);
     PLL1CON |= BIT(20);                             //update pll1div
     PLL1CON |= BIT(6);                              //enable analog pll1
-    hal_mdelay(1);                                 //wait pll1 stable
+    hal_mdelay(1);                                  //wait pll1 stable
 }
 
 void dac_start(void)
@@ -453,7 +453,6 @@ static int rt_hw_sound_init(void)
         return -RT_ENOMEM;
     }
 
-    rt_memset(tx_fifo, 0, TX_FIFO_SIZE);
     snd_dev.tx_fifo = tx_fifo;
 
     /* 分配 DMA 搬运 buffer */ 
@@ -463,7 +462,6 @@ static int rt_hw_sound_init(void)
         return -RT_ENOMEM;
     }
 
-    rt_memset(rx_fifo, 0, TX_FIFO_SIZE);
     snd_dev.rx_fifo = rx_fifo;
 
     /* init default configuration */

bsp/bluetrum/libraries/hal_drivers/drv_rtc.c

@@ -10,6 +10,7 @@
 
 #include "board.h"
 #include <time.h>
+#include <sys/time.h>
 
 #ifdef BSP_USING_ONCHIP_RTC
 
@@ -26,7 +27,7 @@ static struct rt_device rtc;
 uint8_t get_weekday(struct tm *const _tm)
 {
     uint8_t weekday;
-    time_t secs = mktime(_tm);
+    time_t secs = timegm(_tm);
 
     weekday = (secs / 86400 + 4) % 7;
     return weekday;
@@ -115,7 +116,7 @@ void hal_rtc_init(void)
     tm_new.tm_mday = 29;
     tm_new.tm_mon  = 1 - 1;
     tm_new.tm_year = 2021 - 1900;
-    sec = mktime(&tm_new);
+    sec = timegm(&tm_new);
 
     irtc_time_write(RTCCNT_CMD, sec);
 }

bsp/dm365/applications/board.c

@@ -41,7 +41,7 @@
 	rt_uint8_t _fiq_stack_start[1024];
 	rt_uint8_t _undefined_stack_start[512];
 	rt_uint8_t _abort_stack_start[512];
-	rt_uint8_t _svc_stack_start[1024] SECTION(".nobss");
+	rt_uint8_t _svc_stack_start[1024] RT_SECTION(".nobss");
 	extern unsigned char __bss_start;
 	extern unsigned char __bss_end;
 #endif

bsp/essemi/es32f0271/drivers/drv_rtc.c

@@ -12,6 +12,7 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 #include <string.h>
+#include <sys/time.h>
 #include "board.h"
 #include "drv_rtc.h"
 
@@ -96,14 +97,14 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
             time_temp.tm_mday   = date->day;
             time_temp.tm_mon    = date->month - 1;
             time_temp.tm_year   = date->year - 1900 + 2000;
-            *((time_t *)args) = mktime(&time_temp);
+            *((time_t *)args) = timegm(&time_temp);
             break;
         }
         case RT_DEVICE_CTRL_RTC_SET_TIME:
         {
             rt_enter_critical();
             /* converts calendar time time into local time. */
-            pNow = localtime((const time_t *)args);
+            pNow = gmtime((const time_t *)args);
             /* copy the statically located variable */
             memcpy(&time_temp, pNow, sizeof(struct tm));
             /* unlock scheduler. */

bsp/essemi/es32f0334/drivers/drv_rtc.c

@@ -12,6 +12,7 @@
 #include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>
+#include <sys/time.h>
 #include <string.h>
 #include "board.h"
 #include "drv_rtc.h"
@@ -59,14 +60,14 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
         time_temp.tm_mday = date.day;
         time_temp.tm_mon = date.month - 1;
         time_temp.tm_year = date.year - 1900 + 2000;
-        *((time_t *)args) = mktime(&time_temp);
+        *((time_t *)args) = timegm(&time_temp);
         break;
 
     case RT_DEVICE_CTRL_RTC_SET_TIME:
 
         rt_enter_critical();
         /* converts calendar time time into local time. */
-        pNow = localtime((const time_t *)args);
+        pNow = gmtime((const time_t *)args);
         /* copy the statically located variable */
         memcpy(&time_temp, pNow, sizeof(struct tm));
         /* unlock scheduler. */

bsp/essemi/es32f0654/drivers/drv_rtc.c

@@ -12,6 +12,7 @@
 #include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>
+#include <sys/time.h>
 #include <string.h>
 #include "board.h"
 #include "drv_rtc.h"
@@ -59,14 +60,14 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
         time_temp.tm_mday = date.day;
         time_temp.tm_mon = date.month - 1;
         time_temp.tm_year = date.year - 1900 + 2000;
-        *((time_t *)args) = mktime(&time_temp);
+        *((time_t *)args) = timegm(&time_temp);
         break;
 
     case RT_DEVICE_CTRL_RTC_SET_TIME:
 
         rt_enter_critical();
         /* converts calendar time time into local time. */
-        pNow = localtime((const time_t *)args);
+        pNow = gmtime((const time_t *)args);
         /* copy the statically located variable */
         memcpy(&time_temp, pNow, sizeof(struct tm));
         /* unlock scheduler. */

bsp/essemi/es32f369x/drivers/drv_rtc.c

@@ -12,6 +12,7 @@
 #include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>
+#include <sys/time.h>
 #include <string.h>
 #include "board.h"
 #include "drv_rtc.h"
@@ -59,14 +60,14 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
         time_temp.tm_mday = date.day;
         time_temp.tm_mon = date.month - 1;
         time_temp.tm_year = date.year - 1900 + 2000;
-        *((time_t *)args) = mktime(&time_temp);
+        *((time_t *)args) = timegm(&time_temp);
         break;
 
     case RT_DEVICE_CTRL_RTC_SET_TIME:
 
         rt_enter_critical();
         /* converts calendar time time into local time. */
-        pNow = localtime((const time_t *)args);
+        pNow = gmtime((const time_t *)args);
         /* copy the statically located variable */
         memcpy(&time_temp, pNow, sizeof(struct tm));
         /* unlock scheduler. */

bsp/fh8620/drivers/i2c.c

@@ -392,8 +392,12 @@ int fh_i2c_probe(void *priv_data)
 
     PRINT_I2C_DBG("%s start\n", __func__);
 
-    i2c_bus_dev = (struct rt_i2c_bus_device*)rt_malloc(sizeof(struct rt_i2c_bus_device));
-    rt_memset(i2c_bus_dev, 0, sizeof(struct rt_i2c_bus_device));
+    i2c_bus_dev = (struct rt_i2c_bus_device*)rt_calloc(1, sizeof(struct rt_i2c_bus_device));
+    if (RT_NULL == i2c_bus_dev)
+    {
+        return -RT_ENOMEM;
+    }
+
     i2c_bus_dev->ops = &fh_i2c_ops;
 
     rt_sprintf(i2c_dev_name, "%s%d", "i2c", i2c_obj->id);
@@ -406,8 +410,11 @@ int fh_i2c_probe(void *priv_data)
     }
 
     //priv struct init
-    i2c_drv = (struct i2c_driver*)rt_malloc(sizeof(struct i2c_driver));
-    rt_memset(i2c_drv, 0, sizeof(struct i2c_driver));
+    i2c_drv = (struct i2c_driver*)rt_calloc(1, sizeof(struct i2c_driver));
+    if (RT_NULL == i2c_drv)
+    {
+        return -RT_ENOMEM;
+    }
 
     i2c_drv->i2c_bus_dev = i2c_bus_dev;
     i2c_drv->priv = priv_data;

bsp/fh8620/platform/fh8620/iot_cam/startup.c

@@ -63,7 +63,7 @@ rt_uint8_t _irq_stack_start[1024];
 rt_uint8_t _fiq_stack_start[1024];
 rt_uint8_t _undefined_stack_start[512];
 rt_uint8_t _abort_stack_start[512];
-rt_uint8_t _svc_stack_start[4096] SECTION(".nobss");
+rt_uint8_t _svc_stack_start[4096] RT_SECTION(".nobss");
 extern unsigned char __bss_start;
 extern unsigned char __bss_end;
 

bsp/hc32f4a0/drivers/drv_rtc.c

@@ -8,8 +8,11 @@
  * 2020-10-30     CDT          first version
  */
  
-#include "board.h"
+#include <board.h>
 #include <rtdbg.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <sys/time.h>
 
 #ifdef BSP_USING_RTC
 
@@ -33,7 +36,7 @@ static time_t hc32_rtc_get_time_stamp(void)
     tm_new.tm_wday = stcRtcDate.u8Weekday;
 
     LOG_D("get rtc time.");
-    return mktime(&tm_new);
+    return timegm(&tm_new);
 }
 
 static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp)
@@ -42,7 +45,7 @@ static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp)
     stc_rtc_date_t stcRtcDate = {0};
     struct tm *p_tm;
 
-    p_tm = localtime(&time_stamp);
+    p_tm = gmtime(&time_stamp);
     if (p_tm->tm_year < 100)
     {
         return -RT_ERROR;

bsp/imxrt/libraries/drivers/drv_lcd.c

@@ -46,7 +46,7 @@ struct imxrt_lcd
 };
 
 static struct imxrt_lcd lcd;
-ALIGN(64) static uint16_t frame_buffer[LCD_HEIGHT][LCD_WIDTH] SECTION("NonCacheable");
+ALIGN(64) static uint16_t frame_buffer[LCD_HEIGHT][LCD_WIDTH] RT_SECTION("NonCacheable");
 
 static rt_err_t imxrt_lcd_init(rt_device_t device)
 {

bsp/imxrt/libraries/drivers/drv_rtc.c

@@ -10,6 +10,8 @@
  *
  */
 #include <rtthread.h>
+#include <rtdevice.h>
+#include <sys/time.h>
 
 #ifdef BSP_USING_RTC
 
@@ -39,7 +41,7 @@ static time_t get_timestamp(void)
     tm_new.tm_mon  = rtcDate.month - 1;
     tm_new.tm_year = rtcDate.year - 1900;
 
-    return mktime(&tm_new);
+    return timegm(&tm_new);
 }
 
 static int set_timestamp(time_t timestamp)
@@ -47,7 +49,7 @@ static int set_timestamp(time_t timestamp)
     struct tm *p_tm;
     snvs_hp_rtc_datetime_t rtcDate = {0};
 
-    p_tm = localtime(&timestamp);
+    p_tm = gmtime(&timestamp);
 
     rtcDate.second = p_tm->tm_sec ;
     rtcDate.minute = p_tm->tm_min ;

bsp/imxrt/libraries/drivers/drv_sdio.c

@@ -61,7 +61,7 @@ static int enable_log = 1;
 /* Endian mode. */
 #define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle
 
-ALIGN(USDHC_ADMA2_ADDR_ALIGN) uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS] SECTION("NonCacheable");
+ALIGN(USDHC_ADMA2_ADDR_ALIGN) uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS] RT_SECTION("NonCacheable");
 
 struct imxrt_mmcsd
 {

bsp/lpc43xx/M0/applications/vbus_drv.c

@@ -14,7 +14,7 @@
 #include <vbus.h>
 #include <board.h>
 
-struct rt_vbus_ring rt_vbus_rings[2] SECTION("vbus_ring");
+struct rt_vbus_ring rt_vbus_rings[2] RT_SECTION("vbus_ring");
 
 int rt_vbus_do_init(void)
 {

bsp/lpc43xx/M4/applications/application.c

@@ -22,7 +22,7 @@
 #include <vbus.h>
 #endif
 
-static const unsigned char _M0_CODE[] SECTION("M0_CODE") = {
+static const unsigned char _M0_CODE[] RT_SECTION("M0_CODE") = {
 #include "M0_CODE.h"
 };
 

bsp/lpc43xx/M4/applications/vbus_drv.c

@@ -14,7 +14,7 @@
 #include <vbus.h>
 #include <board.h>
 
-struct rt_vbus_ring rt_vbus_rings[2] SECTION("vbus_ring");
+struct rt_vbus_ring rt_vbus_rings[2] RT_SECTION("vbus_ring");
 
 int rt_vbus_do_init(void)
 {

bsp/lpc43xx/drivers/drv_emac.c

@@ -20,7 +20,7 @@
 #define EMAC_PHY_100MBIT    2
 
 #define MAX_ADDR_LEN 6
-static rt_uint32_t ETH_RAM_BASE[4 * 1024] SECTION("ETH_RAM");
+static rt_uint32_t ETH_RAM_BASE[4 * 1024] RT_SECTION("ETH_RAM");
 
 /* EMAC variables located in 16K Ethernet SRAM */
 #define RX_DESC_BASE         (uint32_t)&ETH_RAM_BASE[0]

bsp/lpc55sxx/Libraries/drivers/drv_rtc.c

@@ -8,12 +8,13 @@
  * 2018-03-15     Liuguang     the first version.
  * 2019-07-19     Magicoe      The first version for LPC55S6x
  */
-
+ 
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <sys/time.h>
 #include "drv_rtc.h" 
-
 #include "fsl_common.h" 
 #include "fsl_rtc.h"
-#include <time.h>
 
 #ifdef RT_USING_RTC
 
@@ -37,7 +38,7 @@ static time_t get_timestamp(void)
     tm_new.tm_mon  = rtcDate.month - 1; 
     tm_new.tm_year = rtcDate.year - 1900; 
 
-    return mktime(&tm_new);
+    return timegm(&tm_new);
 }
 
 static int set_timestamp(time_t timestamp)
@@ -45,7 +46,7 @@ static int set_timestamp(time_t timestamp)
     struct tm *p_tm;
     rtc_datetime_t rtcDate; 
     
-    p_tm = localtime(&timestamp);
+    p_tm = gmtime(&timestamp);
     
     rtcDate.second = p_tm->tm_sec ; 
     rtcDate.minute = p_tm->tm_min ; 

bsp/ls1cdev/drivers/drv_rtc.c

@@ -12,6 +12,7 @@
 #include "board.h"
 #include "drv_rtc.h"
 #include <rtdevice.h>
+#include <sys/time.h>
 
 #include "../libraries/ls1c_regs.h"
 #include "../libraries/ls1c_rtc.h"
@@ -44,7 +45,7 @@ static time_t get_timestamp(void)
     tm_new.tm_mon  = rtcDate.Month- 1; 
     tm_new.tm_year = rtcDate.Year + 2000 - 1900; 
 
-    return mktime(&tm_new);
+    return timegm(&tm_new);
 }
 
 static int set_timestamp(time_t timestamp)
@@ -52,7 +53,7 @@ static int set_timestamp(time_t timestamp)
     struct tm *p_tm;
     RTC_TimeTypeDef rtcDate; 
     
-    p_tm = localtime(&timestamp);
+    p_tm = gmtime(&timestamp);
     
     rtcDate.Seconds= p_tm->tm_sec ; 
     rtcDate.Minutes= p_tm->tm_min ; 

bsp/ls2kdev/drivers/drv_rtc.c

@@ -14,7 +14,7 @@
 #include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>
-#include <rtthread.h>
+#include <sys/time.h>
 #include "ls2k1000.h"
 
 #ifdef RT_USING_RTC
@@ -128,7 +128,7 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args)
     hw_rtc = dev->user_data;
 
     t = (time_t *)args;
-    time = *localtime(t);
+    time = *gmtime(t);
 
     rtctm.sys_toyread0 = hw_rtc->sys_toyread0;
     rtctm.sys_toyread1 = hw_rtc->sys_toyread1;
@@ -137,29 +137,29 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args)
 
     switch (cmd)
     {
-    case RT_DEVICE_CTRL_RTC_GET_TIME:
-        *t = mktime(&tmptime);
-        break;
-    case RT_DEVICE_CTRL_RTC_SET_TIME:
-        tmptime.tm_hour = time.tm_hour;
-        tmptime.tm_min  = time.tm_min;
-        tmptime.tm_sec  = time.tm_sec;
-
-        tmptime.tm_year = time.tm_year;
-        tmptime.tm_mon  = time.tm_mon;
-        tmptime.tm_mday = time.tm_mday;
-
-        rtctm = mkrtctime(&tmptime);
-        /* write to hw RTC */
-        hw_rtc->sys_toywrite0 = rtctm.sys_toyread0;
-        hw_rtc->sys_toywrite1 = rtctm.sys_toyread1;
-        break;
-    case RT_DEVICE_CTRL_RTC_GET_ALARM:
-        break;
-    case RT_DEVICE_CTRL_RTC_SET_ALARM:
-        break;
-    default:
-        break;
+        case RT_DEVICE_CTRL_RTC_GET_TIME:
+            *t = timegm(&tmptime);
+            break;
+        case RT_DEVICE_CTRL_RTC_SET_TIME:
+            tmptime.tm_hour = time.tm_hour;
+            tmptime.tm_min  = time.tm_min;
+            tmptime.tm_sec  = time.tm_sec;
+
+            tmptime.tm_year = time.tm_year;
+            tmptime.tm_mon  = time.tm_mon;
+            tmptime.tm_mday = time.tm_mday;
+
+            rtctm = mkrtctime(&tmptime);
+            /* write to hw RTC */
+            hw_rtc->sys_toywrite0 = rtctm.sys_toyread0;
+            hw_rtc->sys_toywrite1 = rtctm.sys_toyread1;
+            break;
+        case RT_DEVICE_CTRL_RTC_GET_ALARM:
+            break;
+        case RT_DEVICE_CTRL_RTC_SET_ALARM:
+            break;
+        default:
+            break;
     }
 
     return RT_EOK;

bsp/maxim/MAX32660_EVSYS/.config

@@ -0,0 +1,486 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_LIBC_USING_TIME is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_PPOOL is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_BSAL is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# games: games run on RT-Thread console
+#
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_MAX32660=y
+CONFIG_SOC_MAXIM=y
+
+#
+# On-chip Peripheral Drivers
+#
+# CONFIG_BSP_USING_GPIO is not set
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_UART0 is not set
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_UART1_RX_USING_DMA is not set
+# CONFIG_BSP_USING_ON_CHIP_FLASH is not set

bsp/maxim/MAX32660_EVSYS/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+

bsp/maxim/MAX32660_EVSYS/README.md

@@ -0,0 +1,105 @@
+# Maxim-MAX32660- EVSYS说明
+
+## 简介
+
+该文件夹主要存放所有主芯片为MAX32660的板级支持包。开发板上面的主芯片是[MAX32660](https://www.maximintegrated.com/en/products/microcontrollers/MAX32660.html)
+
+芯片Datasheet: [MAX32660_datasheet](https://datasheets.maximintegrated.com/en/ds/MAX32660.pdf)
+
+芯片User Guide：[MAX32660_UserGuide](https://pdfserv.maximintegrated.com/en/an/AN6659.pdf)
+
+开发板介绍页面:  [MAX32660-EVSYS](https://www.maximintegrated.com/en/products/microcontrollers/MAX32660-EVSYS.html)
+
+开发板datasheet： [MAX32660-EVSYS.pdf)](https://datasheets.maximintegrated.com/en/ds/MAX32660-EVSYS.pdf)
+
+支持IDE: [keil pack](http://www.mxim.net/microcontroller/pack/Maxim.MAX32660.1.2.0.pack)， [eclipse](https://www.maximintegrated.com/en/design/software-description.html/swpart=SFW0001500A)
+
+本文主要内容如下：
+
+- 开发板资源介绍
+
+## MAX32660芯片介绍
+
+- RAM  96KB    0x20000000~0x20018000
+
+- ROM  256KB   0x0 ~ 0x40000
+
+- 16KB I-cache
+
+- UART 2个  UART0  UART1
+
+- GPIO  14个
+
+- I2C  2个 Master/Slave 高速3.4Mbps
+
+- ARM Cortex-M4F, 96MHz
+
+- MPU
+
+- SPI 2个  Master/Slave 
+
+- I2S  Master/Slave
+
+- 4 channel DMA
+
+- 3个 32bit  Timer
+
+- Watchdog 
+
+- RTC
+
+  
+
+## 开发板介绍
+
+MAX32660-EVSYS是美信官方的开发板，搭载MAX32660芯片，基于ARM Cortex-M4F内核，最高主频96MHz，具有丰富的外设资源，内核带有FPU。
+
+开发板外观如下图所示
+
+![](doc/images/board.jpg)
+
+MAX32660-EVSYS开发板常用 **板载资源** 如下：
+
+- MCU：MAX32660
+- 板载设
+  - LED：1个，GPIO P0_13 ，高电平点亮，低电平灭 。
+  - 按键：1个，GPIO P0_12,   按下低电平，松开高电平。
+- 调试接口：板载CMSIS-DAP调试器。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** |       **备注**        |
+| :----------- | :----------: | :-------------------: |
+| GPIO         |              |                       |
+| UART         |     支持     | UART0, UART1(console) |
+| PWM          |              |                       |
+| SPI          |              |                       |
+| RTC          |              |                       |
+| I2S          |              |                       |
+| I2C          |              |                       |
+| TIMER        |              |                       |
+| Watchdog     |              |                       |
+
+
+
+### 进阶使用
+
+此 BSP 默认只开启了串口 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+## 注意事项
+
+目前仅支持keil5环境
+
+## 联系人信息
+
+维护人:
+
+-  [supperthomas], 邮箱：<78900636@qq.com>

bsp/maxim/MAX32660_EVSYS/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/maxim/MAX32660_EVSYS/SConstruct

@@ -0,0 +1,57 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+print(SDK_LIB)
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# include cmsis
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'MAX32660PeriphDriver', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/maxim/MAX32660_EVSYS/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/maxim/MAX32660_EVSYS/applications/application.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-11     supperthomas first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "gpio.h"
+
+const gpio_cfg_t led_pin[] =
+{
+    {PORT_0, PIN_13, GPIO_FUNC_OUT, GPIO_PAD_NONE},
+};
+
+int main(void)
+{
+    int count = 1;
+    GPIO_Config(&led_pin[0]);
+    GPIO_OutSet(&led_pin[0]);
+    while (count++)
+    {
+        rt_thread_mdelay(500);
+        GPIO_OutToggle(&led_pin[0]);
+    }
+    return RT_EOK;
+}

bsp/maxim/MAX32660_EVSYS/board/Kconfig

@@ -0,0 +1,56 @@
+menu "Hardware Drivers Config"
+
+config SOC_MAX32660
+    bool
+    config SOC_MAX32660
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select BSP_USING_UART
+    select BSP_USING_UART1
+    default y
+        
+config SOC_MAXIM
+    bool 
+    config SOC_MAXIM
+    default y
+
+menu "On-chip Peripheral Drivers"
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default n
+
+            config BSP_UART0_RX_USING_DMA
+                bool "Enable UART0 RX DMA"
+                depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                default n   
+                
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default y
+
+            config BSP_UART1_RX_USING_DMA
+                bool "Enable UART1 RX DMA"
+                depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                default n
+        endif
+    config BSP_USING_ON_CHIP_FLASH
+        select PKG_USING_FAL
+        bool "Enable on-chip FLASH"
+        default n
+        
+endmenu
+
+
+endmenu
+
+

bsp/maxim/MAX32660_EVSYS/board/SConscript

@@ -0,0 +1,28 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+path =  [cwd]
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [startup_path_prefix + '/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [startup_path_prefix + '/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/ARM/startup_max32660.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [startup_path_prefix + '/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/ARM/startup_max32660.s']
+
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/maxim/MAX32660_EVSYS/board/board.c

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-11     supperthomas first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <stdio.h>
+#include "board.h"
+#include "mxc_sys.h"
+#ifdef RT_USING_SERIAL
+#include "drv_usart.h"
+#endif
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void rt_hw_systick_init(void)
+{
+    uint32_t error;
+    error = SYS_SysTick_Config(SYS_SysTick_GetFreq() / RT_TICK_PER_SECOND, 1, MXC_TMR0);
+
+    if (error != E_NO_ERROR)
+    {
+        printf("ERROR: Ticks is not valid");
+    }
+}
+
+void rt_hw_board_init(void)
+{
+
+    rt_hw_systick_init();
+
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)(HEAP_BEGIN), (void *)(HEAP_END));
+#endif
+
+#ifdef RT_USING_SERIAL
+    rt_hw_usart_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+

bsp/maxim/MAX32660_EVSYS/board/board.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-11     supperthomas first version
+ *
+ */
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#define MCU_FLASH_START_ADRESS       ((uint32_t)0x0)
+#define MCU_FLASH_SIZE_KB               (256)
+#define MCU_FLASH_END_ADDRESS        ((uint32_t)(MCU_FLASH_START_ADRESS + MCU_FLASH_SIZE*1024))
+
+#define MCU_SRAM_SIZE_KB               (96)
+#define MCU_SRAM_START              (0x20000000)
+#define MCU_SRAM_END                (MCU_SRAM_START + MCU_SRAM_SIZE_KB * 1024)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int _ebss;
+#define HEAP_BEGIN      ((void *)&_ebss)
+#endif
+
+#define HEAP_END       MCU_SRAM_END
+
+void rt_hw_board_init(void);
+
+#endif
+

bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds

@@ -0,0 +1,102 @@
+/* Linker script to configure memory regions. */
+
+MEMORY {
+    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+
+SECTIONS {
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        *(.text*)    /* program code */
+        *(.rodata*)  /* read-only data: "const" */
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > FLASH
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx*)
+        __exidx_end = .;
+    } > FLASH
+
+    .data :
+    {
+        _data = ALIGN(., 4);
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+        *(.spix_config*)    /* SPIX configuration functions need to be run from SRAM */
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        _edata = ALIGN(., 4);
+    } > SRAM AT>FLASH
+    __load_data = LOADADDR(.data);
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialzed global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM
+
+    .heap (COPY):
+    {
+        . = ALIGN(4);
+        *(.heap*)
+        __HeapLimit = ABSOLUTE(__StackLimit);
+    } > SRAM
+
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}
+
+
+
+

bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.sct

@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00018000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/maxim/MAX32660_EVSYS/project.uvoptx

@@ -0,0 +1,804 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>96000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"CMSIS-DAP" -U04440000e28e0cd70000000000000000 -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0MAX32660.FLM -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0MAX32660 -FL040000 -FS00 -FP0($$Device:MAX32660$Flash\MAX32660.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>1</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Applications</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>applications\application.c</PathWithFileName>
+      <FilenameWithoutPath>application.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>CPU</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\common\backtrace.c</PathWithFileName>
+      <FilenameWithoutPath>backtrace.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\common\div0.c</PathWithFileName>
+      <FilenameWithoutPath>div0.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\common\showmem.c</PathWithFileName>
+      <FilenameWithoutPath>showmem.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\cortex-m4\cpuport.c</PathWithFileName>
+      <FilenameWithoutPath>cpuport.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\cortex-m4\context_rvds.S</PathWithFileName>
+      <FilenameWithoutPath>context_rvds.S</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>DeviceDrivers</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>7</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\serial\serial.c</PathWithFileName>
+      <FilenameWithoutPath>serial.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>8</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\completion.c</PathWithFileName>
+      <FilenameWithoutPath>completion.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
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bsp/maxim/MAX32660_EVSYS/project.uvprojx

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+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
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+      <TargetName>rtthread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
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+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
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+          <Vendor>Maxim</Vendor>
+          <PackID>Maxim.MAX32660.1.2.0</PackID>
+          <PackURL>http://www.mxim.net/microcontroller/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
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+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:MAX32660$SVD\MAX32660\max32660.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> </SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x18000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x18000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>TARGET=32660, TARGET_REV=0x4131, __RTTHREAD__</Define>
+              <Undefine></Undefine>
+              <IncludePath>applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\HAL_Drivers;..\..\..\components\finsh;.;..\..\..\include;..\libraries\MAX32660PeriphDriver\CMSIS\Device\Maxim\MAX32660\Include;..\libraries\MAX32660PeriphDriver\CMSIS\Core\Include;..\libraries\MAX32660PeriphDriver\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>application.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\application.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CPU</GroupName>
+          <Files>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <Files>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\completion.c</FilePath>
+            </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\dataqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\pipe.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringblk_buf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\ringblk_buf.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>waitqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\waitqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_max32660.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\CMSIS\Device\Maxim\MAX32660\Source\ARM\startup_max32660.s</FilePath>
+            </File>
+            <File>
+              <FileName>drv_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\HAL_Drivers\drv_uart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\components.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Libraries</GroupName>
+          <Files>
+            <File>
+              <FileName>system_max32660.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\CMSIS\Device\Maxim\MAX32660\Source\system_max32660.c</FilePath>
+            </File>
+            <File>
+              <FileName>gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>lp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\lp.c</FilePath>
+            </File>
+            <File>
+              <FileName>tmr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\tmr.c</FilePath>
+            </File>
+            <File>
+              <FileName>tmr_utils.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\tmr_utils.c</FilePath>
+            </File>
+            <File>
+              <FileName>rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\rtc.c</FilePath>
+            </File>
+            <File>
+              <FileName>icc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\icc.c</FilePath>
+            </File>
+            <File>
+              <FileName>mxc_lock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_lock.c</FilePath>
+            </File>
+            <File>
+              <FileName>mxc_assert.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_assert.c</FilePath>
+            </File>
+            <File>
+              <FileName>mxc_delay.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_delay.c</FilePath>
+            </File>
+            <File>
+              <FileName>mxc_pins.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_pins.c</FilePath>
+            </File>
+            <File>
+              <FileName>mxc_sys.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_sys.c</FilePath>
+            </File>
+            <File>
+              <FileName>nvic_table.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\nvic_table.c</FilePath>
+            </File>
+            <File>
+              <FileName>uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\MAX32660PeriphDriver\Source\uart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>

bsp/maxim/MAX32660_EVSYS/rtconfig.h

@@ -0,0 +1,165 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40003
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_USING_MSH_ONLY
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* games: games run on RT-Thread console */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_MAX32660
+#define SOC_MAXIM
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define BSP_USING_UART1
+
+#endif

bsp/maxim/MAX32660_EVSYS/rtconfig.py

@@ -0,0 +1,134 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = 'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    print('================ERROR============================')
+    print('Not support iar yet!')
+    print('=================================================')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+        
+    CXXFLAGS = CFLAGS 
+
+    POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M4.fp'
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict --scatter "board\linker_scripts\link.sct"'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/ARM/ARMCC/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+    
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M4'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=VFPv4_sp'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M4'
+    AFLAGS += ' --fpu VFPv4_sp'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "board/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'
+
+    CXXFLAGS = CFLAGS
+    
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'

bsp/maxim/MAX32660_EVSYS/template.uvoptx

@@ -0,0 +1,184 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>96000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"CMSIS-DAP" -U04440000e28e0cd70000000000000000 -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0MAX32660.FLM -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0MAX32660 -FL040000 -FS00 -FP0($$Device:MAX32660$Flash\MAX32660.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>1</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>

bsp/maxim/MAX32660_EVSYS/template.uvprojx

@@ -0,0 +1,390 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MAX32660</Device>
+          <Vendor>Maxim</Vendor>
+          <PackID>Maxim.MAX32660.1.2.0</PackID>
+          <PackURL>http://www.mxim.net/microcontroller/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MAX32660 -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:MAX32660$Libraries\Device\Maxim\MAX32660\Include\max32660.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:MAX32660$SVD\MAX32660\max32660.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> </SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x18000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x18000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>

bsp/maxim/libraries/HAL_Drivers/SConscript

@@ -0,0 +1,34 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['drv_uart.c']
+    
+if GetDepend(['RT_USING_PWM']):
+    src += ['drv_pwm.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
+    src += ['drv_soft_i2c.c']
+
+
+if GetDepend(['BSP_USING_WDT']):
+    src += ['drv_wdt.c']
+    
+path =  [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/maxim/libraries/HAL_Drivers/drv_uart.c

@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-11     supperthomas first version
+ *
+ */
+
+
+#include "board.h"
+#include "uart.h"
+#include "rtdevice.h"
+#ifdef RT_USING_SERIAL
+
+//#define DRV_DEBUG
+//#define LOG_TAG             "drv.usart"
+//#include <drv_log.h>
+
+#define UART0_CONFIG                                                \
+    {                                                               \
+        .name = "uart0",                                            \
+        .Instance = MXC_UART_GET_UART(0),                           \
+        .irq_type = MXC_UART_GET_IRQ(0),                            \
+    }
+
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = MXC_UART_GET_UART(1),                           \
+        .irq_type = MXC_UART_GET_IRQ(1),                            \
+    }
+
+struct mcu_uart_config
+{
+    const char *name;
+    mxc_uart_regs_t *Instance;
+    IRQn_Type irq_type;
+};
+
+struct mcu_uart
+{
+    mxc_uart_regs_t *handle;
+    struct mcu_uart_config *config;
+
+    rt_uint16_t uart_dma_flag;
+    struct rt_serial_device serial;
+};
+
+
+
+
+#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1)
+
+#error "Please define at least one BSP_USING_UARTx"
+/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+enum
+{
+#ifdef BSP_USING_UART0
+    UART0_INDEX,
+#endif
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+
+};
+
+static struct mcu_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART0
+    UART0_CONFIG,
+#endif
+#ifdef BSP_USING_UART1
+    UART1_CONFIG,
+#endif
+};
+
+static struct mcu_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+
+#ifdef BSP_USING_UART1
+void UART1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    rt_hw_serial_isr(&(uart_obj[UART1_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
+
+    uint32_t  intst = 0;
+    intst = MXC_UART1->int_fl;
+    MXC_UART1->int_fl = intst;
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_UART0
+void UART0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_hw_serial_isr(&(uart_obj[UART0_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
+    /* clear flags */
+
+    uint32_t  intst = 0;
+    intst = MXC_UART0->int_fl;
+    MXC_UART0->int_fl = intst;
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+
+static rt_err_t mcu_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    int error;
+    struct mcu_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    const sys_cfg_uart_t sys_uart_cfg =
+    {
+        MAP_A,
+        UART_FLOW_DISABLE,
+    };
+    uart = rt_container_of(serial, struct mcu_uart, serial);
+    uart_cfg_t mcu_cfg;
+    uart->handle = uart->config->Instance;
+    mcu_cfg.baud = cfg->baud_rate;
+    mcu_cfg.stop = UART_STOP_1;
+    mcu_cfg.parity = UART_PARITY_DISABLE;
+    mcu_cfg.size = UART_DATA_SIZE_8_BITS;
+    mcu_cfg.flow = UART_FLOW_CTRL_EN;
+    mcu_cfg.pol = UART_FLOW_POL_EN;
+
+    error = UART_Init(uart->handle, &mcu_cfg, &sys_uart_cfg);
+    if (error != E_NO_ERROR)
+    {
+        rt_kprintf("Error initializing UART %d\n", error);
+        while (1) {}
+    }
+    return RT_EOK;
+}
+
+static rt_err_t mcu_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct mcu_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct mcu_uart, serial);
+
+    switch (cmd)
+    {
+    /* disable interrupt */
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        NVIC_ClearPendingIRQ(uart->config->irq_type);
+        NVIC_DisableIRQ(uart->config->irq_type);
+        /* disable interrupt */
+        break;
+
+    /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        NVIC_SetPriority(uart->config->irq_type, 1);
+        NVIC_EnableIRQ(uart->config->irq_type);
+        /* enable interrupt */
+        uart->handle->ctrl |=  0x05 << MXC_F_UART_CTRL_RX_TO_POS;
+        uart->handle->int_en |= MXC_F_UART_INT_EN_RX_FIFO_THRESH | \
+                                MXC_F_UART_INT_EN_RX_TIMEOUT;
+
+        uart->handle->int_en |= MXC_F_UART_INT_EN_RX_FRAME_ERROR | \
+                                MXC_F_UART_INT_EN_RX_PARITY_ERROR | \
+                                MXC_F_UART_INT_EN_RX_OVERRUN ;
+
+        uart->handle->thresh_ctrl = MXC_UART_FIFO_DEPTH <<
+                                    MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS;
+        break;
+
+    case RT_DEVICE_CTRL_CLOSE:
+        UART_Shutdown(uart->handle);
+        break;
+
+    }
+    return RT_EOK;
+}
+
+static int mcu_putc(struct rt_serial_device *serial, char c)
+{
+    struct mcu_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct mcu_uart, serial);
+    UART_WriteByte(uart->handle, c);
+    return 1;
+}
+
+static int mcu_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct mcu_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct mcu_uart, serial);
+
+    ch = -1;
+
+    if (UART_NumReadAvail(uart->handle))
+    {
+        ch = UART_ReadByte(uart->handle);
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops mcu_uart_ops =
+{
+    .configure = mcu_configure,
+    .control = mcu_control,
+    .putc = mcu_putc,
+    .getc = mcu_getc,
+};
+
+int rt_hw_usart_init(void)
+{
+    rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct mcu_uart);
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t result = 0;
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        /* init UART object */
+        uart_obj[i].config = &uart_config[i];
+        uart_obj[i].serial.ops    = &mcu_uart_ops;
+        uart_obj[i].serial.config = config;
+
+        /* register UART device */
+        result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
+                                       RT_DEVICE_FLAG_RDWR
+                                       | RT_DEVICE_FLAG_INT_RX
+                                       | RT_DEVICE_FLAG_INT_TX
+                                       , NULL);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+//INIT_BOARD_EXPORT(rt_hw_usart_init);
+#endif /* RT_USING_SERIAL */

components/libc/compilers/dlib/syscalls.h → bsp/maxim/libraries/HAL_Drivers/drv_usart.h

@@ -5,6 +5,13 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2015-01-28     Bernard      first version
+ * 2021-02-08     Supperthomas first version
  */
 
+
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
+
+int rt_hw_usart_init(void);
+
+#endif  /* __DRV_USART_H__ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/RTE_Components.h

@@ -0,0 +1,24 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'Hello_World' 
+ * Target:  'Debug' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "max32660.h"
+
+#define BOARD EvKit_V1 /* Target Board */
+#define RTE_USING_FINSH
+#define TARGET 32660   /* Target Device Part Number */
+#define TARGET_REV 0x4131 /* Target Device Revision Number */
+
+#endif /* RTE_COMPONENTS_H */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/arm_common_tables.h

@@ -0,0 +1,100 @@
+/**
+ * @file    arm_common_tables.h
+ * @brief   External declaration for common tables like Bitreverse, reciprocal etc.
+ */
+
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
+*
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/arm_const_structs.h

@@ -0,0 +1,85 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_const_structs.h
+*
+* Description:  This file has constant structs that are initialized for
+*               user convenience.  For example, some can be given as
+*               arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
+      16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
+      32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
+      64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
+      128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
+      256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
+      512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
+      1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
+      2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
+      4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
+   };
+
+#endif

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/arm_math.h

@@ -0,0 +1,7306 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_math.h
+*
+* Description:  Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * <b>Introduction</b>
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * <b>Using the Library</b>
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * <b>Examples</b>
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * <b>Toolchain Support</b>
+   *
+   * The library has been developed and tested with MDK-ARM version 4.60.
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * <b>Building the Library</b>
+   *
+   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM0b_math.uvproj
+   * - arm_cortexM0l_math.uvproj
+   * - arm_cortexM3b_math.uvproj
+   * - arm_cortexM3l_math.uvproj
+   * - arm_cortexM4b_math.uvproj
+   * - arm_cortexM4l_math.uvproj
+   * - arm_cortexM4bf_math.uvproj
+   * - arm_cortexM4lf_math.uvproj
+   *
+   *
+   * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+   *
+   * <b>Pre-processor Macros</b>
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <b>Copyright Notice</b>
+   *
+   * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define TABLE_SIZE			256
+#define TABLE_SPACING_Q31	0x800000
+#define TABLE_SPACING_Q15	0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) -
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) +
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) y)) +
+      ((short) x * (short) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q15 *pCfft;          /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in > 0)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+#if   defined ( __CC_ARM ) //Keil
+//SMMLAR
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+  #define LOW_OPTIMIZATION_ENTER \
+     _Pragma ("push")         \
+     _Pragma ("O1")
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT \
+     _Pragma ("pop")
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+ //SMMLA
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+  #define LOW_OPTIMIZATION_ENTER \
+     _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+     _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ //SMMLA
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y ) >> 32)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_cm3.h

@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_cm4.h

@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_cm4_simd.h

@@ -0,0 +1,671 @@
+/**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ ******************************************************************************/
+
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_cmFunc.h

@@ -0,0 +1,633 @@
+/**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ ******************************************************************************/
+
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** @ingroup  CMSIS_Core_FunctionInterface
+    @defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** @brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    @return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** @brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    @param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** @brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    @return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** @brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    @return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** @brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    @return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** @brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    @return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** @brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    @param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** @brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    @return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** @brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    @param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** @brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    @return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** @brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    @param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** @brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** @brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** @brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    @return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** @brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    @param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** @brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    @return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** @brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    @param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** @brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    @return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** @brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    @param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** @brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** @brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** @brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    @return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** @brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    @param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** @brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    @return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** @brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    @return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** @brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    @return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** @brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    @return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** @brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    @param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** @brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    @return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** @brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    @param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** @brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    @return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** @brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    @param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** @brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** @brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** @brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    @return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** @brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    @param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** @brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    @return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** @brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    @param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** @brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    @return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** @brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    @param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/core_cmInstr.h

@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/bbfc_regs.h

@@ -0,0 +1,127 @@
+/**
+ * @file    bbfc_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the BBFC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _BBFC_REGS_H_
+#define _BBFC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     bbfc
+ * @defgroup    bbfc_registers BBFC_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the BBFC Peripheral Module.
+ * @details Battery-Backed Function Control.
+ */
+
+/**
+ * @ingroup bbfc_registers
+ * Structure type to access the BBFC Registers.
+ */
+typedef struct {
+    __IO uint32_t bbfcr0;               /**< <tt>\b 0x00:</tt> BBFC BBFCR0 Register */
+} mxc_bbfc_regs_t;
+
+/* Register offsets for module BBFC */
+/**
+ * @ingroup    bbfc_registers
+ * @defgroup   BBFC_Register_Offsets Register Offsets
+ * @brief      BBFC Peripheral Register Offsets from the BBFC Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_BBFC_BBFCR0                  ((uint32_t)0x00000000UL) /**< Offset from BBFC Base Address: <tt> 0x0000</tt> */ 
+/**@} end of group bbfc_registers */
+
+/**
+ * @ingroup  bbfc_registers
+ * @defgroup BBFC_BBFCR0 BBFC_BBFCR0
+ * @brief    Function Control Register 0.
+ * @{
+ */
+ #define MXC_F_BBFC_BBFCR0_CKPDRV_POS                   0 /**< BBFCR0_CKPDRV Position */
+ #define MXC_F_BBFC_BBFCR0_CKPDRV                       ((uint32_t)(0xFUL << MXC_F_BBFC_BBFCR0_CKPDRV_POS)) /**< BBFCR0_CKPDRV Mask */
+
+ #define MXC_F_BBFC_BBFCR0_CKNPDRV_POS                  4 /**< BBFCR0_CKNPDRV Position */
+ #define MXC_F_BBFC_BBFCR0_CKNPDRV                      ((uint32_t)(0xFUL << MXC_F_BBFC_BBFCR0_CKNPDRV_POS)) /**< BBFCR0_CKNPDRV Mask */
+
+ #define MXC_F_BBFC_BBFCR0_RDSDLLEN_POS                 8 /**< BBFCR0_RDSDLLEN Position */
+ #define MXC_F_BBFC_BBFCR0_RDSDLLEN                     ((uint32_t)(0x1UL << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS)) /**< BBFCR0_RDSDLLEN Mask */
+ #define MXC_V_BBFC_BBFCR0_RDSDLLEN_DIS                 ((uint32_t)0x0UL) /**< BBFCR0_RDSDLLEN_DIS Value */
+ #define MXC_S_BBFC_BBFCR0_RDSDLLEN_DIS                 (MXC_V_BBFC_BBFCR0_RDSDLLEN_DIS << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS) /**< BBFCR0_RDSDLLEN_DIS Setting */
+ #define MXC_V_BBFC_BBFCR0_RDSDLLEN_EN                  ((uint32_t)0x1UL) /**< BBFCR0_RDSDLLEN_EN Value */
+ #define MXC_S_BBFC_BBFCR0_RDSDLLEN_EN                  (MXC_V_BBFC_BBFCR0_RDSDLLEN_EN << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS) /**< BBFCR0_RDSDLLEN_EN Setting */
+
+/**@} end of group BBFC_BBFCR0_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BBFC_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/bbsir_regs.h

@@ -0,0 +1,111 @@
+/**
+ * @file    bbsir_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the BBSIR Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _BBSIR_REGS_H_
+#define _BBSIR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     bbsir
+ * @defgroup    bbsir_registers BBSIR_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the BBSIR Peripheral Module.
+ * @details Battery-Backed Registers.
+ */
+
+/**
+ * @ingroup bbsir_registers
+ * Structure type to access the BBSIR Registers.
+ */
+typedef struct {
+    __IO uint32_t rsv0;                 /**< <tt>\b 0x00:</tt> BBSIR RSV0 Register */
+    __R  uint32_t rsv_0x4;
+    __I  uint32_t bb_sir2;              /**< <tt>\b 0x08:</tt> BBSIR BB_SIR2 Register */
+    __I  uint32_t bb_sir3;              /**< <tt>\b 0x0C:</tt> BBSIR BB_SIR3 Register */
+} mxc_bbsir_regs_t;
+
+/* Register offsets for module BBSIR */
+/**
+ * @ingroup    bbsir_registers
+ * @defgroup   BBSIR_Register_Offsets Register Offsets
+ * @brief      BBSIR Peripheral Register Offsets from the BBSIR Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_BBSIR_RSV0                   ((uint32_t)0x00000000UL) /**< Offset from BBSIR Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_BBSIR_BB_SIR2                ((uint32_t)0x00000008UL) /**< Offset from BBSIR Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_BBSIR_BB_SIR3                ((uint32_t)0x0000000CUL) /**< Offset from BBSIR Base Address: <tt> 0x000C</tt> */ 
+/**@} end of group bbsir_registers */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BBSIR_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h

@@ -0,0 +1,470 @@
+/**
+ * @file    dma_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _DMA_REGS_H_
+#define _DMA_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     dma
+ * @defgroup    dma_registers DMA_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
+ * @details DMA Controller Fully programmable, chaining capable DMA channels.
+ */
+
+/**
+ * @ingroup dma_registers
+ * Structure type to access the DMA Registers.
+ */
+typedef struct {
+    __IO uint32_t cfg;                  /**< <tt>\b 0x100:</tt> DMA CFG Register */
+    __IO uint32_t st;                   /**< <tt>\b 0x104:</tt> DMA ST Register */
+    __IO uint32_t src;                  /**< <tt>\b 0x108:</tt> DMA SRC Register */
+    __IO uint32_t dst;                  /**< <tt>\b 0x10C:</tt> DMA DST Register */
+    __IO uint32_t cnt;                  /**< <tt>\b 0x110:</tt> DMA CNT Register */
+    __IO uint32_t src_rld;              /**< <tt>\b 0x114:</tt> DMA SRC_RLD Register */
+    __IO uint32_t dst_rld;              /**< <tt>\b 0x118:</tt> DMA DST_RLD Register */
+    __IO uint32_t cnt_rld;              /**< <tt>\b 0x11C:</tt> DMA CNT_RLD Register */
+} mxc_dma_ch_regs_t;
+
+typedef struct {
+    __IO uint32_t cn;                   /**< <tt>\b 0x000:</tt> DMA CN Register */
+    __I  uint32_t intr;                 /**< <tt>\b 0x004:</tt> DMA INTR Register */
+    __R  uint32_t rsv_0x8_0xff[62];
+    __IO mxc_dma_ch_regs_t    ch[4];    /**< <tt>\b 0x100:</tt> DMA CH Register */
+} mxc_dma_regs_t;
+
+/* Register offsets for module DMA */
+/**
+ * @ingroup    dma_registers
+ * @defgroup   DMA_Register_Offsets Register Offsets
+ * @brief      DMA Peripheral Register Offsets from the DMA Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_DMA_CFG                      ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ 
+ #define MXC_R_DMA_ST                       ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */ 
+ #define MXC_R_DMA_SRC                      ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */ 
+ #define MXC_R_DMA_DST                      ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */ 
+ #define MXC_R_DMA_CNT                      ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */ 
+ #define MXC_R_DMA_SRC_RLD                  ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */ 
+ #define MXC_R_DMA_DST_RLD                  ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */ 
+ #define MXC_R_DMA_CNT_RLD                  ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */ 
+ #define MXC_R_DMA_CN                       ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_DMA_INTR                     ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_DMA_CH                       ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ 
+/**@} end of group dma_registers */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_CN DMA_CN
+ * @brief    DMA Control Register.
+ * @{
+ */
+ #define MXC_F_DMA_CN_CH0_IEN_POS                       0 /**< CN_CH0_IEN Position */
+ #define MXC_F_DMA_CN_CH0_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH0_IEN_POS)) /**< CN_CH0_IEN Mask */
+ #define MXC_V_DMA_CN_CH0_IEN_DIS                       ((uint32_t)0x0UL) /**< CN_CH0_IEN_DIS Value */
+ #define MXC_S_DMA_CN_CH0_IEN_DIS                       (MXC_V_DMA_CN_CH0_IEN_DIS << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_DIS Setting */
+ #define MXC_V_DMA_CN_CH0_IEN_EN                        ((uint32_t)0x1UL) /**< CN_CH0_IEN_EN Value */
+ #define MXC_S_DMA_CN_CH0_IEN_EN                        (MXC_V_DMA_CN_CH0_IEN_EN << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_EN Setting */
+
+ #define MXC_F_DMA_CN_CH1_IEN_POS                       1 /**< CN_CH1_IEN Position */
+ #define MXC_F_DMA_CN_CH1_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH1_IEN_POS)) /**< CN_CH1_IEN Mask */
+
+ #define MXC_F_DMA_CN_CH2_IEN_POS                       2 /**< CN_CH2_IEN Position */
+ #define MXC_F_DMA_CN_CH2_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH2_IEN_POS)) /**< CN_CH2_IEN Mask */
+
+ #define MXC_F_DMA_CN_CH3_IEN_POS                       3 /**< CN_CH3_IEN Position */
+ #define MXC_F_DMA_CN_CH3_IEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH3_IEN_POS)) /**< CN_CH3_IEN Mask */
+
+/**@} end of group DMA_CN_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_INTR DMA_INTR
+ * @brief    DMA Interrupt Register.
+ * @{
+ */
+ #define MXC_F_DMA_INTR_CH0_IPEND_POS                   0 /**< INTR_CH0_IPEND Position */
+ #define MXC_F_DMA_INTR_CH0_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS)) /**< INTR_CH0_IPEND Mask */
+ #define MXC_V_DMA_INTR_CH0_IPEND_INACTIVE              ((uint32_t)0x0UL) /**< INTR_CH0_IPEND_INACTIVE Value */
+ #define MXC_S_DMA_INTR_CH0_IPEND_INACTIVE              (MXC_V_DMA_INTR_CH0_IPEND_INACTIVE << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_INACTIVE Setting */
+ #define MXC_V_DMA_INTR_CH0_IPEND_PENDING               ((uint32_t)0x1UL) /**< INTR_CH0_IPEND_PENDING Value */
+ #define MXC_S_DMA_INTR_CH0_IPEND_PENDING               (MXC_V_DMA_INTR_CH0_IPEND_PENDING << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_PENDING Setting */
+
+ #define MXC_F_DMA_INTR_CH1_IPEND_POS                   1 /**< INTR_CH1_IPEND Position */
+ #define MXC_F_DMA_INTR_CH1_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS)) /**< INTR_CH1_IPEND Mask */
+
+ #define MXC_F_DMA_INTR_CH2_IPEND_POS                   2 /**< INTR_CH2_IPEND Position */
+ #define MXC_F_DMA_INTR_CH2_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS)) /**< INTR_CH2_IPEND Mask */
+
+ #define MXC_F_DMA_INTR_CH3_IPEND_POS                   3 /**< INTR_CH3_IPEND Position */
+ #define MXC_F_DMA_INTR_CH3_IPEND                       ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS)) /**< INTR_CH3_IPEND Mask */
+
+/**@} end of group DMA_INTR_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_CFG DMA_CFG
+ * @brief    DMA Channel Configuration Register.
+ * @{
+ */
+ #define MXC_F_DMA_CFG_CHEN_POS                         0 /**< CFG_CHEN Position */
+ #define MXC_F_DMA_CFG_CHEN                             ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */
+ #define MXC_V_DMA_CFG_CHEN_DIS                         ((uint32_t)0x0UL) /**< CFG_CHEN_DIS Value */
+ #define MXC_S_DMA_CFG_CHEN_DIS                         (MXC_V_DMA_CFG_CHEN_DIS << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_DIS Setting */
+ #define MXC_V_DMA_CFG_CHEN_EN                          ((uint32_t)0x1UL) /**< CFG_CHEN_EN Value */
+ #define MXC_S_DMA_CFG_CHEN_EN                          (MXC_V_DMA_CFG_CHEN_EN << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_EN Setting */
+
+ #define MXC_F_DMA_CFG_RLDEN_POS                        1 /**< CFG_RLDEN Position */
+ #define MXC_F_DMA_CFG_RLDEN                            ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */
+ #define MXC_V_DMA_CFG_RLDEN_DIS                        ((uint32_t)0x0UL) /**< CFG_RLDEN_DIS Value */
+ #define MXC_S_DMA_CFG_RLDEN_DIS                        (MXC_V_DMA_CFG_RLDEN_DIS << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_DIS Setting */
+ #define MXC_V_DMA_CFG_RLDEN_EN                         ((uint32_t)0x1UL) /**< CFG_RLDEN_EN Value */
+ #define MXC_S_DMA_CFG_RLDEN_EN                         (MXC_V_DMA_CFG_RLDEN_EN << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_EN Setting */
+
+ #define MXC_F_DMA_CFG_PRI_POS                          2 /**< CFG_PRI Position */
+ #define MXC_F_DMA_CFG_PRI                              ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */
+ #define MXC_V_DMA_CFG_PRI_HIGH                         ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */
+ #define MXC_S_DMA_CFG_PRI_HIGH                         (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */
+ #define MXC_V_DMA_CFG_PRI_MEDHIGH                      ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */
+ #define MXC_S_DMA_CFG_PRI_MEDHIGH                      (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */
+ #define MXC_V_DMA_CFG_PRI_MEDLOW                       ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */
+ #define MXC_S_DMA_CFG_PRI_MEDLOW                       (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */
+ #define MXC_V_DMA_CFG_PRI_LOW                          ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */
+ #define MXC_S_DMA_CFG_PRI_LOW                          (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */
+
+ #define MXC_F_DMA_CFG_REQSEL_POS                       4 /**< CFG_REQSEL Position */
+ #define MXC_F_DMA_CFG_REQSEL                           ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */
+ #define MXC_V_DMA_CFG_REQSEL_MEMTOMEM                  ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */
+ #define MXC_S_DMA_CFG_REQSEL_MEMTOMEM                  (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */
+ #define MXC_V_DMA_CFG_REQSEL_SPI0RX                    ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */
+ #define MXC_S_DMA_CFG_REQSEL_SPI0RX                    (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_SPI1RX                    ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */
+ #define MXC_S_DMA_CFG_REQSEL_SPI1RX                    (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_UART0RX                   ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */
+ #define MXC_S_DMA_CFG_REQSEL_UART0RX                   (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_UART1RX                   ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */
+ #define MXC_S_DMA_CFG_REQSEL_UART1RX                   (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_I2C0RX                    ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */
+ #define MXC_S_DMA_CFG_REQSEL_I2C0RX                    (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_I2C1RX                    ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */
+ #define MXC_S_DMA_CFG_REQSEL_I2C1RX                    (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_SPI0TX                    ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */
+ #define MXC_S_DMA_CFG_REQSEL_SPI0TX                    (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_SPI1TX                    ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */
+ #define MXC_S_DMA_CFG_REQSEL_SPI1TX                    (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_UART0TX                   ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */
+ #define MXC_S_DMA_CFG_REQSEL_UART0TX                   (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_UART1TX                   ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */
+ #define MXC_S_DMA_CFG_REQSEL_UART1TX                   (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_I2C0TX                    ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */
+ #define MXC_S_DMA_CFG_REQSEL_I2C0TX                    (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_I2C1TX                    ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */
+ #define MXC_S_DMA_CFG_REQSEL_I2C1TX                    (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */
+
+ #define MXC_F_DMA_CFG_REQWAIT_POS                      10 /**< CFG_REQWAIT Position */
+ #define MXC_F_DMA_CFG_REQWAIT                          ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */
+ #define MXC_V_DMA_CFG_REQWAIT_DIS                      ((uint32_t)0x0UL) /**< CFG_REQWAIT_DIS Value */
+ #define MXC_S_DMA_CFG_REQWAIT_DIS                      (MXC_V_DMA_CFG_REQWAIT_DIS << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_DIS Setting */
+ #define MXC_V_DMA_CFG_REQWAIT_EN                       ((uint32_t)0x1UL) /**< CFG_REQWAIT_EN Value */
+ #define MXC_S_DMA_CFG_REQWAIT_EN                       (MXC_V_DMA_CFG_REQWAIT_EN << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_EN Setting */
+
+ #define MXC_F_DMA_CFG_TOSEL_POS                        11 /**< CFG_TOSEL Position */
+ #define MXC_F_DMA_CFG_TOSEL                            ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */
+ #define MXC_V_DMA_CFG_TOSEL_TO4                        ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */
+ #define MXC_S_DMA_CFG_TOSEL_TO4                        (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */
+ #define MXC_V_DMA_CFG_TOSEL_TO8                        ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */
+ #define MXC_S_DMA_CFG_TOSEL_TO8                        (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */
+ #define MXC_V_DMA_CFG_TOSEL_TO16                       ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */
+ #define MXC_S_DMA_CFG_TOSEL_TO16                       (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */
+ #define MXC_V_DMA_CFG_TOSEL_TO32                       ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */
+ #define MXC_S_DMA_CFG_TOSEL_TO32                       (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */
+ #define MXC_V_DMA_CFG_TOSEL_TO64                       ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */
+ #define MXC_S_DMA_CFG_TOSEL_TO64                       (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */
+ #define MXC_V_DMA_CFG_TOSEL_TO128                      ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */
+ #define MXC_S_DMA_CFG_TOSEL_TO128                      (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */
+ #define MXC_V_DMA_CFG_TOSEL_TO256                      ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */
+ #define MXC_S_DMA_CFG_TOSEL_TO256                      (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */
+ #define MXC_V_DMA_CFG_TOSEL_TO512                      ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */
+ #define MXC_S_DMA_CFG_TOSEL_TO512                      (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */
+
+ #define MXC_F_DMA_CFG_PSSEL_POS                        14 /**< CFG_PSSEL Position */
+ #define MXC_F_DMA_CFG_PSSEL                            ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */
+ #define MXC_V_DMA_CFG_PSSEL_DIS                        ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */
+ #define MXC_S_DMA_CFG_PSSEL_DIS                        (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */
+ #define MXC_V_DMA_CFG_PSSEL_DIV256                     ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */
+ #define MXC_S_DMA_CFG_PSSEL_DIV256                     (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */
+ #define MXC_V_DMA_CFG_PSSEL_DIV64K                     ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */
+ #define MXC_S_DMA_CFG_PSSEL_DIV64K                     (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */
+ #define MXC_V_DMA_CFG_PSSEL_DIV16M                     ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */
+ #define MXC_S_DMA_CFG_PSSEL_DIV16M                     (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */
+
+ #define MXC_F_DMA_CFG_SRCWD_POS                        16 /**< CFG_SRCWD Position */
+ #define MXC_F_DMA_CFG_SRCWD                            ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */
+ #define MXC_V_DMA_CFG_SRCWD_BYTE                       ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */
+ #define MXC_S_DMA_CFG_SRCWD_BYTE                       (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */
+ #define MXC_V_DMA_CFG_SRCWD_HALFWORD                   ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */
+ #define MXC_S_DMA_CFG_SRCWD_HALFWORD                   (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */
+ #define MXC_V_DMA_CFG_SRCWD_WORD                       ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */
+ #define MXC_S_DMA_CFG_SRCWD_WORD                       (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */
+
+ #define MXC_F_DMA_CFG_SRCINC_POS                       18 /**< CFG_SRCINC Position */
+ #define MXC_F_DMA_CFG_SRCINC                           ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) /**< CFG_SRCINC Mask */
+ #define MXC_V_DMA_CFG_SRCINC_DIS                       ((uint32_t)0x0UL) /**< CFG_SRCINC_DIS Value */
+ #define MXC_S_DMA_CFG_SRCINC_DIS                       (MXC_V_DMA_CFG_SRCINC_DIS << MXC_F_DMA_CFG_SRCINC_POS) /**< CFG_SRCINC_DIS Setting */
+ #define MXC_V_DMA_CFG_SRCINC_EN                        ((uint32_t)0x1UL) /**< CFG_SRCINC_EN Value */
+ #define MXC_S_DMA_CFG_SRCINC_EN                        (MXC_V_DMA_CFG_SRCINC_EN << MXC_F_DMA_CFG_SRCINC_POS) /**< CFG_SRCINC_EN Setting */
+
+ #define MXC_F_DMA_CFG_DSTWD_POS                        20 /**< CFG_DSTWD Position */
+ #define MXC_F_DMA_CFG_DSTWD                            ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */
+ #define MXC_V_DMA_CFG_DSTWD_BYTE                       ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */
+ #define MXC_S_DMA_CFG_DSTWD_BYTE                       (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */
+ #define MXC_V_DMA_CFG_DSTWD_HALFWORD                   ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */
+ #define MXC_S_DMA_CFG_DSTWD_HALFWORD                   (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */
+ #define MXC_V_DMA_CFG_DSTWD_WORD                       ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */
+ #define MXC_S_DMA_CFG_DSTWD_WORD                       (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */
+
+ #define MXC_F_DMA_CFG_DSTINC_POS                       22 /**< CFG_DSTINC Position */
+ #define MXC_F_DMA_CFG_DSTINC                           ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */
+ #define MXC_V_DMA_CFG_DSTINC_DIS                       ((uint32_t)0x0UL) /**< CFG_DSTINC_DIS Value */
+ #define MXC_S_DMA_CFG_DSTINC_DIS                       (MXC_V_DMA_CFG_DSTINC_DIS << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_DIS Setting */
+ #define MXC_V_DMA_CFG_DSTINC_EN                        ((uint32_t)0x1UL) /**< CFG_DSTINC_EN Value */
+ #define MXC_S_DMA_CFG_DSTINC_EN                        (MXC_V_DMA_CFG_DSTINC_EN << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_EN Setting */
+
+ #define MXC_F_DMA_CFG_BRST_POS                         24 /**< CFG_BRST Position */
+ #define MXC_F_DMA_CFG_BRST                             ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */
+
+ #define MXC_F_DMA_CFG_CHDIEN_POS                       30 /**< CFG_CHDIEN Position */
+ #define MXC_F_DMA_CFG_CHDIEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */
+ #define MXC_V_DMA_CFG_CHDIEN_DIS                       ((uint32_t)0x0UL) /**< CFG_CHDIEN_DIS Value */
+ #define MXC_S_DMA_CFG_CHDIEN_DIS                       (MXC_V_DMA_CFG_CHDIEN_DIS << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_DIS Setting */
+ #define MXC_V_DMA_CFG_CHDIEN_EN                        ((uint32_t)0x1UL) /**< CFG_CHDIEN_EN Value */
+ #define MXC_S_DMA_CFG_CHDIEN_EN                        (MXC_V_DMA_CFG_CHDIEN_EN << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_EN Setting */
+
+ #define MXC_F_DMA_CFG_CTZIEN_POS                       31 /**< CFG_CTZIEN Position */
+ #define MXC_F_DMA_CFG_CTZIEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */
+ #define MXC_V_DMA_CFG_CTZIEN_DIS                       ((uint32_t)0x0UL) /**< CFG_CTZIEN_DIS Value */
+ #define MXC_S_DMA_CFG_CTZIEN_DIS                       (MXC_V_DMA_CFG_CTZIEN_DIS << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_DIS Setting */
+ #define MXC_V_DMA_CFG_CTZIEN_EN                        ((uint32_t)0x1UL) /**< CFG_CTZIEN_EN Value */
+ #define MXC_S_DMA_CFG_CTZIEN_EN                        (MXC_V_DMA_CFG_CTZIEN_EN << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_EN Setting */
+
+/**@} end of group DMA_CFG_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_ST DMA_ST
+ * @brief    DMA Channel Status Register.
+ * @{
+ */
+ #define MXC_F_DMA_ST_CH_ST_POS                         0 /**< ST_CH_ST Position */
+ #define MXC_F_DMA_ST_CH_ST                             ((uint32_t)(0x1UL << MXC_F_DMA_ST_CH_ST_POS)) /**< ST_CH_ST Mask */
+ #define MXC_V_DMA_ST_CH_ST_DIS                         ((uint32_t)0x0UL) /**< ST_CH_ST_DIS Value */
+ #define MXC_S_DMA_ST_CH_ST_DIS                         (MXC_V_DMA_ST_CH_ST_DIS << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_DIS Setting */
+ #define MXC_V_DMA_ST_CH_ST_EN                          ((uint32_t)0x1UL) /**< ST_CH_ST_EN Value */
+ #define MXC_S_DMA_ST_CH_ST_EN                          (MXC_V_DMA_ST_CH_ST_EN << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_EN Setting */
+
+ #define MXC_F_DMA_ST_IPEND_POS                         1 /**< ST_IPEND Position */
+ #define MXC_F_DMA_ST_IPEND                             ((uint32_t)(0x1UL << MXC_F_DMA_ST_IPEND_POS)) /**< ST_IPEND Mask */
+ #define MXC_V_DMA_ST_IPEND_INACTIVE                    ((uint32_t)0x0UL) /**< ST_IPEND_INACTIVE Value */
+ #define MXC_S_DMA_ST_IPEND_INACTIVE                    (MXC_V_DMA_ST_IPEND_INACTIVE << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_INACTIVE Setting */
+ #define MXC_V_DMA_ST_IPEND_PENDING                     ((uint32_t)0x1UL) /**< ST_IPEND_PENDING Value */
+ #define MXC_S_DMA_ST_IPEND_PENDING                     (MXC_V_DMA_ST_IPEND_PENDING << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_PENDING Setting */
+
+ #define MXC_F_DMA_ST_CTZ_ST_POS                        2 /**< ST_CTZ_ST Position */
+ #define MXC_F_DMA_ST_CTZ_ST                            ((uint32_t)(0x1UL << MXC_F_DMA_ST_CTZ_ST_POS)) /**< ST_CTZ_ST Mask */
+ #define MXC_V_DMA_ST_CTZ_ST_NOEVENT                    ((uint32_t)0x0UL) /**< ST_CTZ_ST_NOEVENT Value */
+ #define MXC_S_DMA_ST_CTZ_ST_NOEVENT                    (MXC_V_DMA_ST_CTZ_ST_NOEVENT << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_NOEVENT Setting */
+ #define MXC_V_DMA_ST_CTZ_ST_OCCURRED                   ((uint32_t)0x1UL) /**< ST_CTZ_ST_OCCURRED Value */
+ #define MXC_S_DMA_ST_CTZ_ST_OCCURRED                   (MXC_V_DMA_ST_CTZ_ST_OCCURRED << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_OCCURRED Setting */
+ #define MXC_V_DMA_ST_CTZ_ST_CLEAR                      ((uint32_t)0x1UL) /**< ST_CTZ_ST_CLEAR Value */
+ #define MXC_S_DMA_ST_CTZ_ST_CLEAR                      (MXC_V_DMA_ST_CTZ_ST_CLEAR << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_CLEAR Setting */
+
+ #define MXC_F_DMA_ST_RLD_ST_POS                        3 /**< ST_RLD_ST Position */
+ #define MXC_F_DMA_ST_RLD_ST                            ((uint32_t)(0x1UL << MXC_F_DMA_ST_RLD_ST_POS)) /**< ST_RLD_ST Mask */
+ #define MXC_V_DMA_ST_RLD_ST_NOEVENT                    ((uint32_t)0x0UL) /**< ST_RLD_ST_NOEVENT Value */
+ #define MXC_S_DMA_ST_RLD_ST_NOEVENT                    (MXC_V_DMA_ST_RLD_ST_NOEVENT << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_NOEVENT Setting */
+ #define MXC_V_DMA_ST_RLD_ST_OCCURRED                   ((uint32_t)0x1UL) /**< ST_RLD_ST_OCCURRED Value */
+ #define MXC_S_DMA_ST_RLD_ST_OCCURRED                   (MXC_V_DMA_ST_RLD_ST_OCCURRED << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_OCCURRED Setting */
+ #define MXC_V_DMA_ST_RLD_ST_CLEAR                      ((uint32_t)0x1UL) /**< ST_RLD_ST_CLEAR Value */
+ #define MXC_S_DMA_ST_RLD_ST_CLEAR                      (MXC_V_DMA_ST_RLD_ST_CLEAR << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_CLEAR Setting */
+
+ #define MXC_F_DMA_ST_BUS_ERR_POS                       4 /**< ST_BUS_ERR Position */
+ #define MXC_F_DMA_ST_BUS_ERR                           ((uint32_t)(0x1UL << MXC_F_DMA_ST_BUS_ERR_POS)) /**< ST_BUS_ERR Mask */
+ #define MXC_V_DMA_ST_BUS_ERR_NOEVENT                   ((uint32_t)0x0UL) /**< ST_BUS_ERR_NOEVENT Value */
+ #define MXC_S_DMA_ST_BUS_ERR_NOEVENT                   (MXC_V_DMA_ST_BUS_ERR_NOEVENT << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_NOEVENT Setting */
+ #define MXC_V_DMA_ST_BUS_ERR_OCCURRED                  ((uint32_t)0x1UL) /**< ST_BUS_ERR_OCCURRED Value */
+ #define MXC_S_DMA_ST_BUS_ERR_OCCURRED                  (MXC_V_DMA_ST_BUS_ERR_OCCURRED << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_OCCURRED Setting */
+ #define MXC_V_DMA_ST_BUS_ERR_CLEAR                     ((uint32_t)0x1UL) /**< ST_BUS_ERR_CLEAR Value */
+ #define MXC_S_DMA_ST_BUS_ERR_CLEAR                     (MXC_V_DMA_ST_BUS_ERR_CLEAR << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_CLEAR Setting */
+
+ #define MXC_F_DMA_ST_TO_ST_POS                         6 /**< ST_TO_ST Position */
+ #define MXC_F_DMA_ST_TO_ST                             ((uint32_t)(0x1UL << MXC_F_DMA_ST_TO_ST_POS)) /**< ST_TO_ST Mask */
+ #define MXC_V_DMA_ST_TO_ST_NOEVENT                     ((uint32_t)0x0UL) /**< ST_TO_ST_NOEVENT Value */
+ #define MXC_S_DMA_ST_TO_ST_NOEVENT                     (MXC_V_DMA_ST_TO_ST_NOEVENT << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_NOEVENT Setting */
+ #define MXC_V_DMA_ST_TO_ST_OCCURRED                    ((uint32_t)0x1UL) /**< ST_TO_ST_OCCURRED Value */
+ #define MXC_S_DMA_ST_TO_ST_OCCURRED                    (MXC_V_DMA_ST_TO_ST_OCCURRED << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_OCCURRED Setting */
+ #define MXC_V_DMA_ST_TO_ST_CLEAR                       ((uint32_t)0x1UL) /**< ST_TO_ST_CLEAR Value */
+ #define MXC_S_DMA_ST_TO_ST_CLEAR                       (MXC_V_DMA_ST_TO_ST_CLEAR << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_CLEAR Setting */
+
+/**@} end of group DMA_ST_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_SRC DMA_SRC
+ * @brief    Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or
+ *           4, depending on the data width of each AHB cycle. For peripheral transfers, some
+ *           or all of the actual address bits are fixed. If SRCINC=0, this register remains
+ *           constant. In the case where a count-to-zero condition occurs while RLDEN=1, the
+ *           register is reloaded with the contents of DMA_SRC_RLD.
+ * @{
+ */
+ #define MXC_F_DMA_SRC_ADDR_POS                         0 /**< SRC_ADDR Position */
+ #define MXC_F_DMA_SRC_ADDR                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */
+
+/**@} end of group DMA_SRC_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_DST DMA_DST
+ * @brief    Destination Device Address. For peripheral transfers, some or all of the actual
+ *           address bits are fixed. If DSTINC=1, this register is incremented on every AHB
+ *           write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the
+ *           data width of each AHB cycle. In the case where a count-to-zero condition occurs
+ *           while RLDEN=1, the register is reloaded with DMA_DST_RLD.
+ * @{
+ */
+ #define MXC_F_DMA_DST_ADDR_POS                         0 /**< DST_ADDR Position */
+ #define MXC_F_DMA_DST_ADDR                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */
+
+/**@} end of group DMA_DST_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_CNT DMA_CNT
+ * @brief    DMA Counter. The user loads this register with the number of bytes to transfer.
+ *           This counter decreases on every AHB cycle into the DMA FIFO. The decrement will
+ *           be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter
+ *           reaches 0, a count-to-zero condition is triggered.
+ * @{
+ */
+ #define MXC_F_DMA_CNT_CNT_POS                          0 /**< CNT_CNT Position */
+ #define MXC_F_DMA_CNT_CNT                              ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */
+
+/**@} end of group DMA_CNT_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_SRC_RLD DMA_SRC_RLD
+ * @brief    Source Address Reload Value. The value of this register is loaded into DMA0_SRC
+ *           upon a count-to-zero condition.
+ * @{
+ */
+ #define MXC_F_DMA_SRC_RLD_SRC_RLD_POS                  0 /**< SRC_RLD_SRC_RLD Position */
+ #define MXC_F_DMA_SRC_RLD_SRC_RLD                      ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */
+
+/**@} end of group DMA_SRC_RLD_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_DST_RLD DMA_DST_RLD
+ * @brief    Destination Address Reload Value. The value of this register is loaded into
+ *           DMA0_DST upon a count-to-zero condition.
+ * @{
+ */
+ #define MXC_F_DMA_DST_RLD_DST_RLD_POS                  0 /**< DST_RLD_DST_RLD Position */
+ #define MXC_F_DMA_DST_RLD_DST_RLD                      ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */
+
+/**@} end of group DMA_DST_RLD_Register */
+
+/**
+ * @ingroup  dma_registers
+ * @defgroup DMA_CNT_RLD DMA_CNT_RLD
+ * @brief    DMA Channel Count Reload Register.
+ * @{
+ */
+ #define MXC_F_DMA_CNT_RLD_CNT_RLD_POS                  0 /**< CNT_RLD_CNT_RLD Position */
+ #define MXC_F_DMA_CNT_RLD_CNT_RLD                      ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */
+
+ #define MXC_F_DMA_CNT_RLD_RLDEN_POS                    31 /**< CNT_RLD_RLDEN Position */
+ #define MXC_F_DMA_CNT_RLD_RLDEN                        ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */
+ #define MXC_V_DMA_CNT_RLD_RLDEN_DIS                    ((uint32_t)0x0UL) /**< CNT_RLD_RLDEN_DIS Value */
+ #define MXC_S_DMA_CNT_RLD_RLDEN_DIS                    (MXC_V_DMA_CNT_RLD_RLDEN_DIS << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_DIS Setting */
+ #define MXC_V_DMA_CNT_RLD_RLDEN_EN                     ((uint32_t)0x1UL) /**< CNT_RLD_RLDEN_EN Value */
+ #define MXC_S_DMA_CNT_RLD_RLDEN_EN                     (MXC_V_DMA_CNT_RLD_RLDEN_EN << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_EN Setting */
+
+/**@} end of group DMA_CNT_RLD_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DMA_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h

@@ -0,0 +1,264 @@
+/**
+ * @file    flc_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _FLC_REGS_H_
+#define _FLC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     flc
+ * @defgroup    flc_registers FLC_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
+ * @details Flash Memory Control.
+ */
+
+/**
+ * @ingroup flc_registers
+ * Structure type to access the FLC Registers.
+ */
+typedef struct {
+    __IO uint32_t addr;                 /**< <tt>\b 0x00:</tt> FLC ADDR Register */
+    __IO uint32_t clkdiv;               /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */
+    __IO uint32_t cn;                   /**< <tt>\b 0x08:</tt> FLC CN Register */
+    __R  uint32_t rsv_0xc_0x23[6];
+    __IO uint32_t intr;                 /**< <tt>\b 0x024:</tt> FLC INTR Register */
+    __R  uint32_t rsv_0x28_0x2f[2];
+    __IO uint32_t data[4];              /**< <tt>\b 0x30:</tt> FLC DATA Register */
+    __O  uint32_t acntl;                /**< <tt>\b 0x40:</tt> FLC ACNTL Register */
+} mxc_flc_regs_t;
+
+/* Register offsets for module FLC */
+/**
+ * @ingroup    flc_registers
+ * @defgroup   FLC_Register_Offsets Register Offsets
+ * @brief      FLC Peripheral Register Offsets from the FLC Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_FLC_ADDR                     ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_FLC_CLKDIV                   ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_FLC_CN                       ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_FLC_INTR                     ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_FLC_DATA                     ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */ 
+ #define MXC_R_FLC_ACNTL                    ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */ 
+/**@} end of group flc_registers */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_ADDR FLC_ADDR
+ * @brief    Flash Write Address.
+ * @{
+ */
+ #define MXC_F_FLC_ADDR_ADDR_POS                        0 /**< ADDR_ADDR Position */
+ #define MXC_F_FLC_ADDR_ADDR                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
+
+/**@} end of group FLC_ADDR_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_CLKDIV FLC_CLKDIV
+ * @brief    Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
+ *           MHz clock for Flash controller.
+ * @{
+ */
+ #define MXC_F_FLC_CLKDIV_CLKDIV_POS                    0 /**< CLKDIV_CLKDIV Position */
+ #define MXC_F_FLC_CLKDIV_CLKDIV                        ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
+
+/**@} end of group FLC_CLKDIV_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_CN FLC_CN
+ * @brief    Flash Control Register.
+ * @{
+ */
+ #define MXC_F_FLC_CN_WR_POS                            0 /**< CN_WR Position */
+ #define MXC_F_FLC_CN_WR                                ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */
+ #define MXC_V_FLC_CN_WR_COMPLETE                       ((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value */
+ #define MXC_S_FLC_CN_WR_COMPLETE                       (MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE Setting */
+ #define MXC_V_FLC_CN_WR_START                          ((uint32_t)0x1UL) /**< CN_WR_START Value */
+ #define MXC_S_FLC_CN_WR_START                          (MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */
+
+ #define MXC_F_FLC_CN_ME_POS                            1 /**< CN_ME Position */
+ #define MXC_F_FLC_CN_ME                                ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */
+
+ #define MXC_F_FLC_CN_PGE_POS                           2 /**< CN_PGE Position */
+ #define MXC_F_FLC_CN_PGE                               ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */
+
+ #define MXC_F_FLC_CN_WDTH_POS                          4 /**< CN_WDTH Position */
+ #define MXC_F_FLC_CN_WDTH                              ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */
+ #define MXC_V_FLC_CN_WDTH_SIZE128                      ((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */
+ #define MXC_S_FLC_CN_WDTH_SIZE128                      (MXC_V_FLC_CN_WDTH_SIZE128 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */
+ #define MXC_V_FLC_CN_WDTH_SIZE32                       ((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value */
+ #define MXC_S_FLC_CN_WDTH_SIZE32                       (MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */
+
+ #define MXC_F_FLC_CN_ERASE_CODE_POS                    8 /**< CN_ERASE_CODE Position */
+ #define MXC_F_FLC_CN_ERASE_CODE                        ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */
+ #define MXC_V_FLC_CN_ERASE_CODE_NOP                    ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */
+ #define MXC_S_FLC_CN_ERASE_CODE_NOP                    (MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */
+ #define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE              ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */
+ #define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE              (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting */
+ #define MXC_V_FLC_CN_ERASE_CODE_ERASEALL               ((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */
+ #define MXC_S_FLC_CN_ERASE_CODE_ERASEALL               (MXC_V_FLC_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting */
+
+ #define MXC_F_FLC_CN_PEND_POS                          24 /**< CN_PEND Position */
+ #define MXC_F_FLC_CN_PEND                              ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */
+ #define MXC_V_FLC_CN_PEND_IDLE                         ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */
+ #define MXC_S_FLC_CN_PEND_IDLE                         (MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE Setting */
+ #define MXC_V_FLC_CN_PEND_BUSY                         ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */
+ #define MXC_S_FLC_CN_PEND_BUSY                         (MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */
+
+ #define MXC_F_FLC_CN_LVE_POS                           25 /**< CN_LVE Position */
+ #define MXC_F_FLC_CN_LVE                               ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */
+ #define MXC_V_FLC_CN_LVE_DIS                           ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */
+ #define MXC_S_FLC_CN_LVE_DIS                           (MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting */
+ #define MXC_V_FLC_CN_LVE_EN                            ((uint32_t)0x1UL) /**< CN_LVE_EN Value */
+ #define MXC_S_FLC_CN_LVE_EN                            (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting */
+
+ #define MXC_F_FLC_CN_BRST_POS                          27 /**< CN_BRST Position */
+ #define MXC_F_FLC_CN_BRST                              ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */
+ #define MXC_V_FLC_CN_BRST_DISABLE                      ((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */
+ #define MXC_S_FLC_CN_BRST_DISABLE                      (MXC_V_FLC_CN_BRST_DISABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */
+ #define MXC_V_FLC_CN_BRST_ENABLE                       ((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value */
+ #define MXC_S_FLC_CN_BRST_ENABLE                       (MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */
+
+ #define MXC_F_FLC_CN_UNLOCK_POS                        28 /**< CN_UNLOCK Position */
+ #define MXC_F_FLC_CN_UNLOCK                            ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */
+ #define MXC_V_FLC_CN_UNLOCK_UNLOCKED                   ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */
+ #define MXC_S_FLC_CN_UNLOCK_UNLOCKED                   (MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */
+ #define MXC_V_FLC_CN_UNLOCK_LOCKED                     ((uint32_t)0x3UL) /**< CN_UNLOCK_LOCKED Value */
+ #define MXC_S_FLC_CN_UNLOCK_LOCKED                     (MXC_V_FLC_CN_UNLOCK_LOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_LOCKED Setting */
+
+/**@} end of group FLC_CN_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_INTR FLC_INTR
+ * @brief    Flash Interrupt Register.
+ * @{
+ */
+ #define MXC_F_FLC_INTR_DONE_POS                        0 /**< INTR_DONE Position */
+ #define MXC_F_FLC_INTR_DONE                            ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
+ #define MXC_V_FLC_INTR_DONE_INACTIVE                   ((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */
+ #define MXC_S_FLC_INTR_DONE_INACTIVE                   (MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */
+ #define MXC_V_FLC_INTR_DONE_PENDING                    ((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */
+ #define MXC_S_FLC_INTR_DONE_PENDING                    (MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */
+
+ #define MXC_F_FLC_INTR_AF_POS                          1 /**< INTR_AF Position */
+ #define MXC_F_FLC_INTR_AF                              ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */
+ #define MXC_V_FLC_INTR_AF_NOERROR                      ((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */
+ #define MXC_S_FLC_INTR_AF_NOERROR                      (MXC_V_FLC_INTR_AF_NOERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */
+ #define MXC_V_FLC_INTR_AF_ERROR                        ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */
+ #define MXC_S_FLC_INTR_AF_ERROR                        (MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */
+
+ #define MXC_F_FLC_INTR_DONEIE_POS                      8 /**< INTR_DONEIE Position */
+ #define MXC_F_FLC_INTR_DONEIE                          ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
+ #define MXC_V_FLC_INTR_DONEIE_DISABLE                  ((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */
+ #define MXC_S_FLC_INTR_DONEIE_DISABLE                  (MXC_V_FLC_INTR_DONEIE_DISABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */
+ #define MXC_V_FLC_INTR_DONEIE_ENABLE                   ((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */
+ #define MXC_S_FLC_INTR_DONEIE_ENABLE                   (MXC_V_FLC_INTR_DONEIE_ENABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */
+
+ #define MXC_F_FLC_INTR_AFIE_POS                        9 /**< INTR_AFIE Position */
+ #define MXC_F_FLC_INTR_AFIE                            ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
+
+/**@} end of group FLC_INTR_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_DATA FLC_DATA
+ * @brief    Flash Write Data.
+ * @{
+ */
+ #define MXC_F_FLC_DATA_DATA_POS                        0 /**< DATA_DATA Position */
+ #define MXC_F_FLC_DATA_DATA                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
+
+/**@} end of group FLC_DATA_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup FLC_ACNTL FLC_ACNTL
+ * @brief    Access Control Register. Writing the ACNTL register with the following values in
+ *           the order shown, allows read and write access to the system and user Information
+ *           block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl =
+ *           0x9608b2c1. When unlocked, a write of any word will disable access to system and
+ *           user information block. Readback of this register is always zero.
+ * @{
+ */
+ #define MXC_F_FLC_ACNTL_ACNTL_POS                      0 /**< ACNTL_ACNTL Position */
+ #define MXC_F_FLC_ACNTL_ACNTL                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */
+
+/**@} end of group FLC_ACNTL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLC_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h

@@ -0,0 +1,769 @@
+/**
+ * @file    gcr_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _GCR_REGS_H_
+#define _GCR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     gcr
+ * @defgroup    gcr_registers GCR_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
+ * @details Global Control Registers.
+ */
+
+/**
+ * @ingroup gcr_registers
+ * Structure type to access the GCR Registers.
+ */
+typedef struct {
+    __IO uint32_t scon;                 /**< <tt>\b 0x00:</tt> GCR SCON Register */
+    __IO uint32_t rstr0;                /**< <tt>\b 0x04:</tt> GCR RSTR0 Register */
+    __IO uint32_t clkcn;                /**< <tt>\b 0x08:</tt> GCR CLKCN Register */
+    __IO uint32_t pm;                   /**< <tt>\b 0x0C:</tt> GCR PM Register */
+    __R  uint32_t rsv_0x10_0x17[2];
+    __IO uint32_t pckdiv;               /**< <tt>\b 0x18:</tt> GCR PCKDIV Register */
+    __R  uint32_t rsv_0x1c_0x23[2];
+    __IO uint32_t perckcn0;             /**< <tt>\b 0x24:</tt> GCR PERCKCN0 Register */
+    __IO uint32_t memckcn;              /**< <tt>\b 0x28:</tt> GCR MEMCKCN Register */
+    __IO uint32_t memzcn;               /**< <tt>\b 0x2C:</tt> GCR MEMZCN Register */
+    __R  uint32_t rsv_0x30;
+    __IO uint32_t scck;                 /**< <tt>\b 0x34:</tt> GCR SCCK Register */
+    __IO uint32_t mpri0;                /**< <tt>\b 0x38:</tt> GCR MPRI0 Register */
+    __IO uint32_t mpri1;                /**< <tt>\b 0x3C:</tt> GCR MPRI1 Register */
+    __IO uint32_t sysst;                /**< <tt>\b 0x40:</tt> GCR SYSST Register */
+    __IO uint32_t rstr1;                /**< <tt>\b 0x44:</tt> GCR RSTR1 Register */
+    __IO uint32_t perckcn1;             /**< <tt>\b 0x48:</tt> GCR PERCKCN1 Register */
+    __IO uint32_t evten;                /**< <tt>\b 0x4C:</tt> GCR EVTEN Register */
+    __I  uint32_t revision;             /**< <tt>\b 0x50:</tt> GCR REVISION Register */
+    __IO uint32_t syssie;               /**< <tt>\b 0x54:</tt> GCR SYSSIE Register */
+} mxc_gcr_regs_t;
+
+/* Register offsets for module GCR */
+/**
+ * @ingroup    gcr_registers
+ * @defgroup   GCR_Register_Offsets Register Offsets
+ * @brief      GCR Peripheral Register Offsets from the GCR Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_GCR_SCON                     ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_GCR_RSTR0                    ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_GCR_CLKCN                    ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_GCR_PM                       ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_GCR_PCKDIV                   ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_GCR_PERCKCN0                 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_GCR_MEMCKCN                  ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */ 
+ #define MXC_R_GCR_MEMZCN                   ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */ 
+ #define MXC_R_GCR_SCCK                     ((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: <tt> 0x0034</tt> */ 
+ #define MXC_R_GCR_MPRI0                    ((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: <tt> 0x0038</tt> */ 
+ #define MXC_R_GCR_MPRI1                    ((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: <tt> 0x003C</tt> */ 
+ #define MXC_R_GCR_SYSST                    ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */ 
+ #define MXC_R_GCR_RSTR1                    ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */ 
+ #define MXC_R_GCR_PERCKCN1                 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */ 
+ #define MXC_R_GCR_EVTEN                    ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */ 
+ #define MXC_R_GCR_REVISION                 ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */ 
+ #define MXC_R_GCR_SYSSIE                   ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */ 
+/**@} end of group gcr_registers */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_SCON GCR_SCON
+ * @brief    System Control.
+ * @{
+ */
+ #define MXC_F_GCR_SCON_SBUSARB_POS                     1 /**< SCON_SBUSARB Position */
+ #define MXC_F_GCR_SCON_SBUSARB                         ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */
+ #define MXC_V_GCR_SCON_SBUSARB_FIX                     ((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */
+ #define MXC_S_GCR_SCON_SBUSARB_FIX                     (MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */
+ #define MXC_V_GCR_SCON_SBUSARB_ROUND                   ((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */
+ #define MXC_S_GCR_SCON_SBUSARB_ROUND                   (MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */
+
+ #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS             4 /**< SCON_FLASH_PAGE_FLIP Position */
+ #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP                 ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */
+ #define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL          ((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */
+ #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL          (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_NORMAL Setting */
+ #define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED         ((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */
+ #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED         (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Setting */
+
+ #define MXC_F_GCR_SCON_FPU_DIS_POS                     5 /**< SCON_FPU_DIS Position */
+ #define MXC_F_GCR_SCON_FPU_DIS                         ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */
+ #define MXC_V_GCR_SCON_FPU_DIS_ENABLE                  ((uint32_t)0x0UL) /**< SCON_FPU_DIS_ENABLE Value */
+ #define MXC_S_GCR_SCON_FPU_DIS_ENABLE                  (MXC_V_GCR_SCON_FPU_DIS_ENABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_ENABLE Setting */
+ #define MXC_V_GCR_SCON_FPU_DIS_DISABLE                 ((uint32_t)0x1UL) /**< SCON_FPU_DIS_DISABLE Value */
+ #define MXC_S_GCR_SCON_FPU_DIS_DISABLE                 (MXC_V_GCR_SCON_FPU_DIS_DISABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_DISABLE Setting */
+
+ #define MXC_F_GCR_SCON_CCACHE_FLUSH_POS                6 /**< SCON_CCACHE_FLUSH Position */
+ #define MXC_F_GCR_SCON_CCACHE_FLUSH                    ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH Mask */
+ #define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL             ((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */
+ #define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL             (MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL Setting */
+ #define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH              ((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */
+ #define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH              (MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH Setting */
+
+ #define MXC_F_GCR_SCON_SWD_DIS_POS                     14 /**< SCON_SWD_DIS Position */
+ #define MXC_F_GCR_SCON_SWD_DIS                         ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */
+ #define MXC_V_GCR_SCON_SWD_DIS_ENABLE                  ((uint32_t)0x0UL) /**< SCON_SWD_DIS_ENABLE Value */
+ #define MXC_S_GCR_SCON_SWD_DIS_ENABLE                  (MXC_V_GCR_SCON_SWD_DIS_ENABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_ENABLE Setting */
+ #define MXC_V_GCR_SCON_SWD_DIS_DISABLE                 ((uint32_t)0x1UL) /**< SCON_SWD_DIS_DISABLE Value */
+ #define MXC_S_GCR_SCON_SWD_DIS_DISABLE                 (MXC_V_GCR_SCON_SWD_DIS_DISABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_DISABLE Setting */
+
+/**@} end of group GCR_SCON_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_RSTR0 GCR_RSTR0
+ * @brief    Reset.
+ * @{
+ */
+ #define MXC_F_GCR_RSTR0_DMA_POS                        0 /**< RSTR0_DMA Position */
+ #define MXC_F_GCR_RSTR0_DMA                            ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */
+ #define MXC_V_GCR_RSTR0_DMA_RFU                        ((uint32_t)0x0UL) /**< RSTR0_DMA_RFU Value */
+ #define MXC_S_GCR_RSTR0_DMA_RFU                        (MXC_V_GCR_RSTR0_DMA_RFU << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RFU Setting */
+ #define MXC_V_GCR_RSTR0_DMA_RESET                      ((uint32_t)0x1UL) /**< RSTR0_DMA_RESET Value */
+ #define MXC_S_GCR_RSTR0_DMA_RESET                      (MXC_V_GCR_RSTR0_DMA_RESET << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET Setting */
+ #define MXC_V_GCR_RSTR0_DMA_RESET_DONE                 ((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_DMA_RESET_DONE                 (MXC_V_GCR_RSTR0_DMA_RESET_DONE << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_DMA_BUSY                       ((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value */
+ #define MXC_S_GCR_RSTR0_DMA_BUSY                       (MXC_V_GCR_RSTR0_DMA_BUSY << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_WDT_POS                        1 /**< RSTR0_WDT Position */
+ #define MXC_F_GCR_RSTR0_WDT                            ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */
+ #define MXC_V_GCR_RSTR0_WDT_RFU                        ((uint32_t)0x0UL) /**< RSTR0_WDT_RFU Value */
+ #define MXC_S_GCR_RSTR0_WDT_RFU                        (MXC_V_GCR_RSTR0_WDT_RFU << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RFU Setting */
+ #define MXC_V_GCR_RSTR0_WDT_RESET                      ((uint32_t)0x1UL) /**< RSTR0_WDT_RESET Value */
+ #define MXC_S_GCR_RSTR0_WDT_RESET                      (MXC_V_GCR_RSTR0_WDT_RESET << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET Setting */
+ #define MXC_V_GCR_RSTR0_WDT_RESET_DONE                 ((uint32_t)0x0UL) /**< RSTR0_WDT_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_WDT_RESET_DONE                 (MXC_V_GCR_RSTR0_WDT_RESET_DONE << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_WDT_BUSY                       ((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value */
+ #define MXC_S_GCR_RSTR0_WDT_BUSY                       (MXC_V_GCR_RSTR0_WDT_BUSY << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_GPIO0_POS                      2 /**< RSTR0_GPIO0 Position */
+ #define MXC_F_GCR_RSTR0_GPIO0                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */
+ #define MXC_V_GCR_RSTR0_GPIO0_RFU                      ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RFU Value */
+ #define MXC_S_GCR_RSTR0_GPIO0_RFU                      (MXC_V_GCR_RSTR0_GPIO0_RFU << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RFU Setting */
+ #define MXC_V_GCR_RSTR0_GPIO0_RESET                    ((uint32_t)0x1UL) /**< RSTR0_GPIO0_RESET Value */
+ #define MXC_S_GCR_RSTR0_GPIO0_RESET                    (MXC_V_GCR_RSTR0_GPIO0_RESET << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET Setting */
+ #define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE               ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE               (MXC_V_GCR_RSTR0_GPIO0_RESET_DONE << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_GPIO0_BUSY                     ((uint32_t)0x1UL) /**< RSTR0_GPIO0_BUSY Value */
+ #define MXC_S_GCR_RSTR0_GPIO0_BUSY                     (MXC_V_GCR_RSTR0_GPIO0_BUSY << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_TIMER0_POS                     5 /**< RSTR0_TIMER0 Position */
+ #define MXC_F_GCR_RSTR0_TIMER0                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */
+ #define MXC_V_GCR_RSTR0_TIMER0_RFU                     ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RFU Value */
+ #define MXC_S_GCR_RSTR0_TIMER0_RFU                     (MXC_V_GCR_RSTR0_TIMER0_RFU << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RFU Setting */
+ #define MXC_V_GCR_RSTR0_TIMER0_RESET                   ((uint32_t)0x1UL) /**< RSTR0_TIMER0_RESET Value */
+ #define MXC_S_GCR_RSTR0_TIMER0_RESET                   (MXC_V_GCR_RSTR0_TIMER0_RESET << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET Setting */
+ #define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE              ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE              (MXC_V_GCR_RSTR0_TIMER0_RESET_DONE << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_TIMER0_BUSY                    ((uint32_t)0x1UL) /**< RSTR0_TIMER0_BUSY Value */
+ #define MXC_S_GCR_RSTR0_TIMER0_BUSY                    (MXC_V_GCR_RSTR0_TIMER0_BUSY << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_TIMER1_POS                     6 /**< RSTR0_TIMER1 Position */
+ #define MXC_F_GCR_RSTR0_TIMER1                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */
+ #define MXC_V_GCR_RSTR0_TIMER1_RFU                     ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RFU Value */
+ #define MXC_S_GCR_RSTR0_TIMER1_RFU                     (MXC_V_GCR_RSTR0_TIMER1_RFU << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RFU Setting */
+ #define MXC_V_GCR_RSTR0_TIMER1_RESET                   ((uint32_t)0x1UL) /**< RSTR0_TIMER1_RESET Value */
+ #define MXC_S_GCR_RSTR0_TIMER1_RESET                   (MXC_V_GCR_RSTR0_TIMER1_RESET << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET Setting */
+ #define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE              ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE              (MXC_V_GCR_RSTR0_TIMER1_RESET_DONE << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_TIMER1_BUSY                    ((uint32_t)0x1UL) /**< RSTR0_TIMER1_BUSY Value */
+ #define MXC_S_GCR_RSTR0_TIMER1_BUSY                    (MXC_V_GCR_RSTR0_TIMER1_BUSY << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_TIMER2_POS                     7 /**< RSTR0_TIMER2 Position */
+ #define MXC_F_GCR_RSTR0_TIMER2                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */
+ #define MXC_V_GCR_RSTR0_TIMER2_RFU                     ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RFU Value */
+ #define MXC_S_GCR_RSTR0_TIMER2_RFU                     (MXC_V_GCR_RSTR0_TIMER2_RFU << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RFU Setting */
+ #define MXC_V_GCR_RSTR0_TIMER2_RESET                   ((uint32_t)0x1UL) /**< RSTR0_TIMER2_RESET Value */
+ #define MXC_S_GCR_RSTR0_TIMER2_RESET                   (MXC_V_GCR_RSTR0_TIMER2_RESET << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET Setting */
+ #define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE              ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE              (MXC_V_GCR_RSTR0_TIMER2_RESET_DONE << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_TIMER2_BUSY                    ((uint32_t)0x1UL) /**< RSTR0_TIMER2_BUSY Value */
+ #define MXC_S_GCR_RSTR0_TIMER2_BUSY                    (MXC_V_GCR_RSTR0_TIMER2_BUSY << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_UART0_POS                      11 /**< RSTR0_UART0 Position */
+ #define MXC_F_GCR_RSTR0_UART0                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */
+ #define MXC_V_GCR_RSTR0_UART0_RFU                      ((uint32_t)0x0UL) /**< RSTR0_UART0_RFU Value */
+ #define MXC_S_GCR_RSTR0_UART0_RFU                      (MXC_V_GCR_RSTR0_UART0_RFU << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RFU Setting */
+ #define MXC_V_GCR_RSTR0_UART0_RESET                    ((uint32_t)0x1UL) /**< RSTR0_UART0_RESET Value */
+ #define MXC_S_GCR_RSTR0_UART0_RESET                    (MXC_V_GCR_RSTR0_UART0_RESET << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET Setting */
+ #define MXC_V_GCR_RSTR0_UART0_RESET_DONE               ((uint32_t)0x0UL) /**< RSTR0_UART0_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_UART0_RESET_DONE               (MXC_V_GCR_RSTR0_UART0_RESET_DONE << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_UART0_BUSY                     ((uint32_t)0x1UL) /**< RSTR0_UART0_BUSY Value */
+ #define MXC_S_GCR_RSTR0_UART0_BUSY                     (MXC_V_GCR_RSTR0_UART0_BUSY << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_UART1_POS                      12 /**< RSTR0_UART1 Position */
+ #define MXC_F_GCR_RSTR0_UART1                          ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */
+ #define MXC_V_GCR_RSTR0_UART1_RFU                      ((uint32_t)0x0UL) /**< RSTR0_UART1_RFU Value */
+ #define MXC_S_GCR_RSTR0_UART1_RFU                      (MXC_V_GCR_RSTR0_UART1_RFU << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RFU Setting */
+ #define MXC_V_GCR_RSTR0_UART1_RESET                    ((uint32_t)0x1UL) /**< RSTR0_UART1_RESET Value */
+ #define MXC_S_GCR_RSTR0_UART1_RESET                    (MXC_V_GCR_RSTR0_UART1_RESET << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET Setting */
+ #define MXC_V_GCR_RSTR0_UART1_RESET_DONE               ((uint32_t)0x0UL) /**< RSTR0_UART1_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_UART1_RESET_DONE               (MXC_V_GCR_RSTR0_UART1_RESET_DONE << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_UART1_BUSY                     ((uint32_t)0x1UL) /**< RSTR0_UART1_BUSY Value */
+ #define MXC_S_GCR_RSTR0_UART1_BUSY                     (MXC_V_GCR_RSTR0_UART1_BUSY << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_SPI0_POS                       13 /**< RSTR0_SPI0 Position */
+ #define MXC_F_GCR_RSTR0_SPI0                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask */
+ #define MXC_V_GCR_RSTR0_SPI0_RFU                       ((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value */
+ #define MXC_S_GCR_RSTR0_SPI0_RFU                       (MXC_V_GCR_RSTR0_SPI0_RFU << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RFU Setting */
+ #define MXC_V_GCR_RSTR0_SPI0_RESET                     ((uint32_t)0x1UL) /**< RSTR0_SPI0_RESET Value */
+ #define MXC_S_GCR_RSTR0_SPI0_RESET                     (MXC_V_GCR_RSTR0_SPI0_RESET << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET Setting */
+ #define MXC_V_GCR_RSTR0_SPI0_RESET_DONE                ((uint32_t)0x0UL) /**< RSTR0_SPI0_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_SPI0_RESET_DONE                (MXC_V_GCR_RSTR0_SPI0_RESET_DONE << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_SPI0_BUSY                      ((uint32_t)0x1UL) /**< RSTR0_SPI0_BUSY Value */
+ #define MXC_S_GCR_RSTR0_SPI0_BUSY                      (MXC_V_GCR_RSTR0_SPI0_BUSY << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_SPI1_POS                       14 /**< RSTR0_SPI1 Position */
+ #define MXC_F_GCR_RSTR0_SPI1                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask */
+ #define MXC_V_GCR_RSTR0_SPI1_RFU                       ((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value */
+ #define MXC_S_GCR_RSTR0_SPI1_RFU                       (MXC_V_GCR_RSTR0_SPI1_RFU << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RFU Setting */
+ #define MXC_V_GCR_RSTR0_SPI1_RESET                     ((uint32_t)0x1UL) /**< RSTR0_SPI1_RESET Value */
+ #define MXC_S_GCR_RSTR0_SPI1_RESET                     (MXC_V_GCR_RSTR0_SPI1_RESET << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET Setting */
+ #define MXC_V_GCR_RSTR0_SPI1_RESET_DONE                ((uint32_t)0x0UL) /**< RSTR0_SPI1_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_SPI1_RESET_DONE                (MXC_V_GCR_RSTR0_SPI1_RESET_DONE << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_SPI1_BUSY                      ((uint32_t)0x1UL) /**< RSTR0_SPI1_BUSY Value */
+ #define MXC_S_GCR_RSTR0_SPI1_BUSY                      (MXC_V_GCR_RSTR0_SPI1_BUSY << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_I2C0_POS                       16 /**< RSTR0_I2C0 Position */
+ #define MXC_F_GCR_RSTR0_I2C0                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask */
+ #define MXC_V_GCR_RSTR0_I2C0_RFU                       ((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value */
+ #define MXC_S_GCR_RSTR0_I2C0_RFU                       (MXC_V_GCR_RSTR0_I2C0_RFU << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RFU Setting */
+ #define MXC_V_GCR_RSTR0_I2C0_RESET                     ((uint32_t)0x1UL) /**< RSTR0_I2C0_RESET Value */
+ #define MXC_S_GCR_RSTR0_I2C0_RESET                     (MXC_V_GCR_RSTR0_I2C0_RESET << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET Setting */
+ #define MXC_V_GCR_RSTR0_I2C0_RESET_DONE                ((uint32_t)0x0UL) /**< RSTR0_I2C0_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_I2C0_RESET_DONE                (MXC_V_GCR_RSTR0_I2C0_RESET_DONE << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_I2C0_BUSY                      ((uint32_t)0x1UL) /**< RSTR0_I2C0_BUSY Value */
+ #define MXC_S_GCR_RSTR0_I2C0_BUSY                      (MXC_V_GCR_RSTR0_I2C0_BUSY << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_RTC_POS                        17 /**< RSTR0_RTC Position */
+ #define MXC_F_GCR_RSTR0_RTC                            ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) /**< RSTR0_RTC Mask */
+ #define MXC_V_GCR_RSTR0_RTC_RFU                        ((uint32_t)0x0UL) /**< RSTR0_RTC_RFU Value */
+ #define MXC_S_GCR_RSTR0_RTC_RFU                        (MXC_V_GCR_RSTR0_RTC_RFU << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RFU Setting */
+ #define MXC_V_GCR_RSTR0_RTC_RESET                      ((uint32_t)0x1UL) /**< RSTR0_RTC_RESET Value */
+ #define MXC_S_GCR_RSTR0_RTC_RESET                      (MXC_V_GCR_RSTR0_RTC_RESET << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET Setting */
+ #define MXC_V_GCR_RSTR0_RTC_RESET_DONE                 ((uint32_t)0x0UL) /**< RSTR0_RTC_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_RTC_RESET_DONE                 (MXC_V_GCR_RSTR0_RTC_RESET_DONE << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_RTC_BUSY                       ((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value */
+ #define MXC_S_GCR_RSTR0_RTC_BUSY                       (MXC_V_GCR_RSTR0_RTC_BUSY << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_SRST_POS                       29 /**< RSTR0_SRST Position */
+ #define MXC_F_GCR_RSTR0_SRST                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask */
+ #define MXC_V_GCR_RSTR0_SRST_RFU                       ((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value */
+ #define MXC_S_GCR_RSTR0_SRST_RFU                       (MXC_V_GCR_RSTR0_SRST_RFU << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RFU Setting */
+ #define MXC_V_GCR_RSTR0_SRST_RESET                     ((uint32_t)0x1UL) /**< RSTR0_SRST_RESET Value */
+ #define MXC_S_GCR_RSTR0_SRST_RESET                     (MXC_V_GCR_RSTR0_SRST_RESET << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET Setting */
+ #define MXC_V_GCR_RSTR0_SRST_RESET_DONE                ((uint32_t)0x0UL) /**< RSTR0_SRST_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_SRST_RESET_DONE                (MXC_V_GCR_RSTR0_SRST_RESET_DONE << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_SRST_BUSY                      ((uint32_t)0x1UL) /**< RSTR0_SRST_BUSY Value */
+ #define MXC_S_GCR_RSTR0_SRST_BUSY                      (MXC_V_GCR_RSTR0_SRST_BUSY << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_PRST_POS                       30 /**< RSTR0_PRST Position */
+ #define MXC_F_GCR_RSTR0_PRST                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask */
+ #define MXC_V_GCR_RSTR0_PRST_RFU                       ((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value */
+ #define MXC_S_GCR_RSTR0_PRST_RFU                       (MXC_V_GCR_RSTR0_PRST_RFU << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RFU Setting */
+ #define MXC_V_GCR_RSTR0_PRST_RESET                     ((uint32_t)0x1UL) /**< RSTR0_PRST_RESET Value */
+ #define MXC_S_GCR_RSTR0_PRST_RESET                     (MXC_V_GCR_RSTR0_PRST_RESET << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET Setting */
+ #define MXC_V_GCR_RSTR0_PRST_RESET_DONE                ((uint32_t)0x0UL) /**< RSTR0_PRST_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_PRST_RESET_DONE                (MXC_V_GCR_RSTR0_PRST_RESET_DONE << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_PRST_BUSY                      ((uint32_t)0x1UL) /**< RSTR0_PRST_BUSY Value */
+ #define MXC_S_GCR_RSTR0_PRST_BUSY                      (MXC_V_GCR_RSTR0_PRST_BUSY << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_SYSTEM_POS                     31 /**< RSTR0_SYSTEM Position */
+ #define MXC_F_GCR_RSTR0_SYSTEM                         ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */
+ #define MXC_V_GCR_RSTR0_SYSTEM_RFU                     ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RFU Value */
+ #define MXC_S_GCR_RSTR0_SYSTEM_RFU                     (MXC_V_GCR_RSTR0_SYSTEM_RFU << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RFU Setting */
+ #define MXC_V_GCR_RSTR0_SYSTEM_RESET                   ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_RESET Value */
+ #define MXC_S_GCR_RSTR0_SYSTEM_RESET                   (MXC_V_GCR_RSTR0_SYSTEM_RESET << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET Setting */
+ #define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE              ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE              (MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_SYSTEM_BUSY                    ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_BUSY Value */
+ #define MXC_S_GCR_RSTR0_SYSTEM_BUSY                    (MXC_V_GCR_RSTR0_SYSTEM_BUSY << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_BUSY Setting */
+
+/**@} end of group GCR_RSTR0_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_CLKCN GCR_CLKCN
+ * @brief    Clock Control.
+ * @{
+ */
+ #define MXC_F_GCR_CLKCN_PSC_POS                        6 /**< CLKCN_PSC Position */
+ #define MXC_F_GCR_CLKCN_PSC                            ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */
+ #define MXC_V_GCR_CLKCN_PSC_DIV1                       ((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV1                       (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV2                       ((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV2                       (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV4                       ((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV4                       (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV8                       ((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV8                       (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV16                      ((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV16                      (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV32                      ((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV32                      (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV64                      ((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV64                      (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV128                     ((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV128                     (MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */
+
+ #define MXC_F_GCR_CLKCN_CLKSEL_POS                     9 /**< CLKCN_CLKSEL Position */
+ #define MXC_F_GCR_CLKCN_CLKSEL                         ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */
+ #define MXC_V_GCR_CLKCN_CLKSEL_HIRC                    ((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */
+ #define MXC_S_GCR_CLKCN_CLKSEL_HIRC                    (MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */
+ #define MXC_V_GCR_CLKCN_CLKSEL_NANORING                ((uint32_t)0x3UL) /**< CLKCN_CLKSEL_NANORING Value */
+ #define MXC_S_GCR_CLKCN_CLKSEL_NANORING                (MXC_V_GCR_CLKCN_CLKSEL_NANORING << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_NANORING Setting */
+ #define MXC_V_GCR_CLKCN_CLKSEL_HFXIN                   ((uint32_t)0x6UL) /**< CLKCN_CLKSEL_HFXIN Value */
+ #define MXC_S_GCR_CLKCN_CLKSEL_HFXIN                   (MXC_V_GCR_CLKCN_CLKSEL_HFXIN << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HFXIN Setting */
+
+ #define MXC_F_GCR_CLKCN_CKRDY_POS                      13 /**< CLKCN_CKRDY Position */
+ #define MXC_F_GCR_CLKCN_CKRDY                          ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */
+ #define MXC_V_GCR_CLKCN_CKRDY_BUSY                     ((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */
+ #define MXC_S_GCR_CLKCN_CKRDY_BUSY                     (MXC_V_GCR_CLKCN_CKRDY_BUSY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */
+ #define MXC_V_GCR_CLKCN_CKRDY_READY                    ((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */
+ #define MXC_S_GCR_CLKCN_CKRDY_READY                    (MXC_V_GCR_CLKCN_CKRDY_READY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */
+
+ #define MXC_F_GCR_CLKCN_X32K_EN_POS                    17 /**< CLKCN_X32K_EN Position */
+ #define MXC_F_GCR_CLKCN_X32K_EN                        ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN Mask */
+ #define MXC_V_GCR_CLKCN_X32K_EN_DIS                    ((uint32_t)0x0UL) /**< CLKCN_X32K_EN_DIS Value */
+ #define MXC_S_GCR_CLKCN_X32K_EN_DIS                    (MXC_V_GCR_CLKCN_X32K_EN_DIS << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_DIS Setting */
+ #define MXC_V_GCR_CLKCN_X32K_EN_EN                     ((uint32_t)0x1UL) /**< CLKCN_X32K_EN_EN Value */
+ #define MXC_S_GCR_CLKCN_X32K_EN_EN                     (MXC_V_GCR_CLKCN_X32K_EN_EN << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_EN Setting */
+
+ #define MXC_F_GCR_CLKCN_HIRC_EN_POS                    18 /**< CLKCN_HIRC_EN Position */
+ #define MXC_F_GCR_CLKCN_HIRC_EN                        ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */
+ #define MXC_V_GCR_CLKCN_HIRC_EN_DIS                    ((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */
+ #define MXC_S_GCR_CLKCN_HIRC_EN_DIS                    (MXC_V_GCR_CLKCN_HIRC_EN_DIS << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */
+ #define MXC_V_GCR_CLKCN_HIRC_EN_EN                     ((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */
+ #define MXC_S_GCR_CLKCN_HIRC_EN_EN                     (MXC_V_GCR_CLKCN_HIRC_EN_EN << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */
+
+ #define MXC_F_GCR_CLKCN_X32K_RDY_POS                   25 /**< CLKCN_X32K_RDY Position */
+ #define MXC_F_GCR_CLKCN_X32K_RDY                       ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< CLKCN_X32K_RDY Mask */
+ #define MXC_V_GCR_CLKCN_X32K_RDY_NOT                   ((uint32_t)0x0UL) /**< CLKCN_X32K_RDY_NOT Value */
+ #define MXC_S_GCR_CLKCN_X32K_RDY_NOT                   (MXC_V_GCR_CLKCN_X32K_RDY_NOT << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_NOT Setting */
+ #define MXC_V_GCR_CLKCN_X32K_RDY_READY                 ((uint32_t)0x1UL) /**< CLKCN_X32K_RDY_READY Value */
+ #define MXC_S_GCR_CLKCN_X32K_RDY_READY                 (MXC_V_GCR_CLKCN_X32K_RDY_READY << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_READY Setting */
+
+ #define MXC_F_GCR_CLKCN_HIRC_RDY_POS                   26 /**< CLKCN_HIRC_RDY Position */
+ #define MXC_F_GCR_CLKCN_HIRC_RDY                       ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */
+ #define MXC_V_GCR_CLKCN_HIRC_RDY_NOT                   ((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */
+ #define MXC_S_GCR_CLKCN_HIRC_RDY_NOT                   (MXC_V_GCR_CLKCN_HIRC_RDY_NOT << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */
+ #define MXC_V_GCR_CLKCN_HIRC_RDY_READY                 ((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */
+ #define MXC_S_GCR_CLKCN_HIRC_RDY_READY                 (MXC_V_GCR_CLKCN_HIRC_RDY_READY << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */
+
+ #define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS                 29 /**< CLKCN_LIRC8K_RDY Position */
+ #define MXC_F_GCR_CLKCN_LIRC8K_RDY                     ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY Mask */
+ #define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT                 ((uint32_t)0x0UL) /**< CLKCN_LIRC8K_RDY_NOT Value */
+ #define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT                 (MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting */
+ #define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY               ((uint32_t)0x1UL) /**< CLKCN_LIRC8K_RDY_READY Value */
+ #define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY               (MXC_V_GCR_CLKCN_LIRC8K_RDY_READY << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY Setting */
+
+/**@} end of group GCR_CLKCN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PM GCR_PM
+ * @brief    Power Management.
+ * @{
+ */
+ #define MXC_F_GCR_PM_MODE_POS                          0 /**< PM_MODE Position */
+ #define MXC_F_GCR_PM_MODE                              ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
+ #define MXC_V_GCR_PM_MODE_ACTIVE                       ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */
+ #define MXC_S_GCR_PM_MODE_ACTIVE                       (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
+ #define MXC_V_GCR_PM_MODE_SHUTDOWN                     ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
+ #define MXC_S_GCR_PM_MODE_SHUTDOWN                     (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
+ #define MXC_V_GCR_PM_MODE_BACKUP                       ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */
+ #define MXC_S_GCR_PM_MODE_BACKUP                       (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
+
+ #define MXC_F_GCR_PM_GPIOWKEN_POS                      4 /**< PM_GPIOWKEN Position */
+ #define MXC_F_GCR_PM_GPIOWKEN                          ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */
+ #define MXC_V_GCR_PM_GPIOWKEN_DIS                      ((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */
+ #define MXC_S_GCR_PM_GPIOWKEN_DIS                      (MXC_V_GCR_PM_GPIOWKEN_DIS << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */
+ #define MXC_V_GCR_PM_GPIOWKEN_EN                       ((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value */
+ #define MXC_S_GCR_PM_GPIOWKEN_EN                       (MXC_V_GCR_PM_GPIOWKEN_EN << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting */
+
+ #define MXC_F_GCR_PM_RTCWKEN_POS                       5 /**< PM_RTCWKEN Position */
+ #define MXC_F_GCR_PM_RTCWKEN                           ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask */
+ #define MXC_V_GCR_PM_RTCWKEN_DIS                       ((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value */
+ #define MXC_S_GCR_PM_RTCWKEN_DIS                       (MXC_V_GCR_PM_RTCWKEN_DIS << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_DIS Setting */
+ #define MXC_V_GCR_PM_RTCWKEN_EN                        ((uint32_t)0x1UL) /**< PM_RTCWKEN_EN Value */
+ #define MXC_S_GCR_PM_RTCWKEN_EN                        (MXC_V_GCR_PM_RTCWKEN_EN << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_EN Setting */
+
+ #define MXC_F_GCR_PM_HIRCPD_POS                        15 /**< PM_HIRCPD Position */
+ #define MXC_F_GCR_PM_HIRCPD                            ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */
+ #define MXC_V_GCR_PM_HIRCPD_ACTIVE                     ((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */
+ #define MXC_S_GCR_PM_HIRCPD_ACTIVE                     (MXC_V_GCR_PM_HIRCPD_ACTIVE << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */
+ #define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP                  ((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */
+ #define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP                  (MXC_V_GCR_PM_HIRCPD_DEEPSLEEP << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */
+
+/**@} end of group GCR_PM_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PCKDIV GCR_PCKDIV
+ * @brief    Peripheral Clock Divider.
+ * @{
+ */
+ #define MXC_F_GCR_PCKDIV_AONCD_POS                     0 /**< PCKDIV_AONCD Position */
+ #define MXC_F_GCR_PCKDIV_AONCD                         ((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */
+ #define MXC_V_GCR_PCKDIV_AONCD_DIV_4                   ((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */
+ #define MXC_S_GCR_PCKDIV_AONCD_DIV_4                   (MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */
+ #define MXC_V_GCR_PCKDIV_AONCD_DIV_8                   ((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */
+ #define MXC_S_GCR_PCKDIV_AONCD_DIV_8                   (MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */
+ #define MXC_V_GCR_PCKDIV_AONCD_DIV_16                  ((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */
+ #define MXC_S_GCR_PCKDIV_AONCD_DIV_16                  (MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */
+ #define MXC_V_GCR_PCKDIV_AONCD_DIV_32                  ((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */
+ #define MXC_S_GCR_PCKDIV_AONCD_DIV_32                  (MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */
+
+/**@} end of group GCR_PCKDIV_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PERCKCN0 GCR_PERCKCN0
+ * @brief    Peripheral Clock Disable.
+ * @{
+ */
+ #define MXC_F_GCR_PERCKCN0_GPIO0D_POS                  0 /**< PERCKCN0_GPIO0D Position */
+ #define MXC_F_GCR_PERCKCN0_GPIO0D                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D Mask */
+ #define MXC_V_GCR_PERCKCN0_GPIO0D_EN                   ((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */
+ #define MXC_S_GCR_PERCKCN0_GPIO0D_EN                   (MXC_V_GCR_PERCKCN0_GPIO0D_EN << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */
+ #define MXC_V_GCR_PERCKCN0_GPIO0D_DIS                  ((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */
+ #define MXC_S_GCR_PERCKCN0_GPIO0D_DIS                  (MXC_V_GCR_PERCKCN0_GPIO0D_DIS << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN0_DMAD_POS                    5 /**< PERCKCN0_DMAD Position */
+ #define MXC_F_GCR_PERCKCN0_DMAD                        ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */
+ #define MXC_V_GCR_PERCKCN0_DMAD_EN                     ((uint32_t)0x0UL) /**< PERCKCN0_DMAD_EN Value */
+ #define MXC_S_GCR_PERCKCN0_DMAD_EN                     (MXC_V_GCR_PERCKCN0_DMAD_EN << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_EN Setting */
+ #define MXC_V_GCR_PERCKCN0_DMAD_DIS                    ((uint32_t)0x1UL) /**< PERCKCN0_DMAD_DIS Value */
+ #define MXC_S_GCR_PERCKCN0_DMAD_DIS                    (MXC_V_GCR_PERCKCN0_DMAD_DIS << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN0_SPI0D_POS                   6 /**< PERCKCN0_SPI0D Position */
+ #define MXC_F_GCR_PERCKCN0_SPI0D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */
+ #define MXC_V_GCR_PERCKCN0_SPI0D_EN                    ((uint32_t)0x0UL) /**< PERCKCN0_SPI0D_EN Value */
+ #define MXC_S_GCR_PERCKCN0_SPI0D_EN                    (MXC_V_GCR_PERCKCN0_SPI0D_EN << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_EN Setting */
+ #define MXC_V_GCR_PERCKCN0_SPI0D_DIS                   ((uint32_t)0x1UL) /**< PERCKCN0_SPI0D_DIS Value */
+ #define MXC_S_GCR_PERCKCN0_SPI0D_DIS                   (MXC_V_GCR_PERCKCN0_SPI0D_DIS << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN0_SPI1D_POS                   7 /**< PERCKCN0_SPI1D Position */
+ #define MXC_F_GCR_PERCKCN0_SPI1D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */
+ #define MXC_V_GCR_PERCKCN0_SPI1D_EN                    ((uint32_t)0x0UL) /**< PERCKCN0_SPI1D_EN Value */
+ #define MXC_S_GCR_PERCKCN0_SPI1D_EN                    (MXC_V_GCR_PERCKCN0_SPI1D_EN << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_EN Setting */
+ #define MXC_V_GCR_PERCKCN0_SPI1D_DIS                   ((uint32_t)0x1UL) /**< PERCKCN0_SPI1D_DIS Value */
+ #define MXC_S_GCR_PERCKCN0_SPI1D_DIS                   (MXC_V_GCR_PERCKCN0_SPI1D_DIS << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN0_UART0D_POS                  9 /**< PERCKCN0_UART0D Position */
+ #define MXC_F_GCR_PERCKCN0_UART0D                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D Mask */
+ #define MXC_V_GCR_PERCKCN0_UART0D_EN                   ((uint32_t)0x0UL) /**< PERCKCN0_UART0D_EN Value */
+ #define MXC_S_GCR_PERCKCN0_UART0D_EN                   (MXC_V_GCR_PERCKCN0_UART0D_EN << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_EN Setting */
+ #define MXC_V_GCR_PERCKCN0_UART0D_DIS                  ((uint32_t)0x1UL) /**< PERCKCN0_UART0D_DIS Value */
+ #define MXC_S_GCR_PERCKCN0_UART0D_DIS                  (MXC_V_GCR_PERCKCN0_UART0D_DIS << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN0_UART1D_POS                  10 /**< PERCKCN0_UART1D Position */
+ #define MXC_F_GCR_PERCKCN0_UART1D                      ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D Mask */
+ #define MXC_V_GCR_PERCKCN0_UART1D_EN                   ((uint32_t)0x0UL) /**< PERCKCN0_UART1D_EN Value */
+ #define MXC_S_GCR_PERCKCN0_UART1D_EN                   (MXC_V_GCR_PERCKCN0_UART1D_EN << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_EN Setting */
+ #define MXC_V_GCR_PERCKCN0_UART1D_DIS                  ((uint32_t)0x1UL) /**< PERCKCN0_UART1D_DIS Value */
+ #define MXC_S_GCR_PERCKCN0_UART1D_DIS                  (MXC_V_GCR_PERCKCN0_UART1D_DIS << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN0_I2C0D_POS                   13 /**< PERCKCN0_I2C0D Position */
+ #define MXC_F_GCR_PERCKCN0_I2C0D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */
+ #define MXC_V_GCR_PERCKCN0_I2C0D_EN                    ((uint32_t)0x0UL) /**< PERCKCN0_I2C0D_EN Value */
+ #define MXC_S_GCR_PERCKCN0_I2C0D_EN                    (MXC_V_GCR_PERCKCN0_I2C0D_EN << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_EN Setting */
+ #define MXC_V_GCR_PERCKCN0_I2C0D_DIS                   ((uint32_t)0x1UL) /**< PERCKCN0_I2C0D_DIS Value */
+ #define MXC_S_GCR_PERCKCN0_I2C0D_DIS                   (MXC_V_GCR_PERCKCN0_I2C0D_DIS << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN0_T0D_POS                     15 /**< PERCKCN0_T0D Position */
+ #define MXC_F_GCR_PERCKCN0_T0D                         ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */
+ #define MXC_V_GCR_PERCKCN0_T0D_EN                      ((uint32_t)0x0UL) /**< PERCKCN0_T0D_EN Value */
+ #define MXC_S_GCR_PERCKCN0_T0D_EN                      (MXC_V_GCR_PERCKCN0_T0D_EN << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_EN Setting */
+ #define MXC_V_GCR_PERCKCN0_T0D_DIS                     ((uint32_t)0x1UL) /**< PERCKCN0_T0D_DIS Value */
+ #define MXC_S_GCR_PERCKCN0_T0D_DIS                     (MXC_V_GCR_PERCKCN0_T0D_DIS << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN0_T1D_POS                     16 /**< PERCKCN0_T1D Position */
+ #define MXC_F_GCR_PERCKCN0_T1D                         ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */
+ #define MXC_V_GCR_PERCKCN0_T1D_EN                      ((uint32_t)0x0UL) /**< PERCKCN0_T1D_EN Value */
+ #define MXC_S_GCR_PERCKCN0_T1D_EN                      (MXC_V_GCR_PERCKCN0_T1D_EN << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_EN Setting */
+ #define MXC_V_GCR_PERCKCN0_T1D_DIS                     ((uint32_t)0x1UL) /**< PERCKCN0_T1D_DIS Value */
+ #define MXC_S_GCR_PERCKCN0_T1D_DIS                     (MXC_V_GCR_PERCKCN0_T1D_DIS << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN0_T2D_POS                     17 /**< PERCKCN0_T2D Position */
+ #define MXC_F_GCR_PERCKCN0_T2D                         ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */
+ #define MXC_V_GCR_PERCKCN0_T2D_EN                      ((uint32_t)0x0UL) /**< PERCKCN0_T2D_EN Value */
+ #define MXC_S_GCR_PERCKCN0_T2D_EN                      (MXC_V_GCR_PERCKCN0_T2D_EN << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_EN Setting */
+ #define MXC_V_GCR_PERCKCN0_T2D_DIS                     ((uint32_t)0x1UL) /**< PERCKCN0_T2D_DIS Value */
+ #define MXC_S_GCR_PERCKCN0_T2D_DIS                     (MXC_V_GCR_PERCKCN0_T2D_DIS << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN0_I2C1D_POS                   28 /**< PERCKCN0_I2C1D Position */
+ #define MXC_F_GCR_PERCKCN0_I2C1D                       ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< PERCKCN0_I2C1D Mask */
+ #define MXC_V_GCR_PERCKCN0_I2C1D_EN                    ((uint32_t)0x0UL) /**< PERCKCN0_I2C1D_EN Value */
+ #define MXC_S_GCR_PERCKCN0_I2C1D_EN                    (MXC_V_GCR_PERCKCN0_I2C1D_EN << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_EN Setting */
+ #define MXC_V_GCR_PERCKCN0_I2C1D_DIS                   ((uint32_t)0x1UL) /**< PERCKCN0_I2C1D_DIS Value */
+ #define MXC_S_GCR_PERCKCN0_I2C1D_DIS                   (MXC_V_GCR_PERCKCN0_I2C1D_DIS << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_DIS Setting */
+
+/**@} end of group GCR_PERCKCN0_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_MEMCKCN GCR_MEMCKCN
+ * @brief    Memory Clock Control Register.
+ * @{
+ */
+ #define MXC_F_GCR_MEMCKCN_FWS_POS                      0 /**< MEMCKCN_FWS Position */
+ #define MXC_F_GCR_MEMCKCN_FWS                          ((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */
+
+ #define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS                8 /**< MEMCKCN_SYSRAM0LS Position */
+ #define MXC_F_GCR_MEMCKCN_SYSRAM0LS                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS Mask */
+ #define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE             ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */
+ #define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE             (MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE Setting */
+ #define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP        ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */
+ #define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP        (MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Setting */
+
+ #define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS                9 /**< MEMCKCN_SYSRAM1LS Position */
+ #define MXC_F_GCR_MEMCKCN_SYSRAM1LS                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS Mask */
+ #define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE             ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM1LS_ACTIVE Value */
+ #define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE             (MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE Setting */
+ #define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP        ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Value */
+ #define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP        (MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Setting */
+
+ #define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS                10 /**< MEMCKCN_SYSRAM2LS Position */
+ #define MXC_F_GCR_MEMCKCN_SYSRAM2LS                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS Mask */
+ #define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE             ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM2LS_ACTIVE Value */
+ #define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE             (MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE Setting */
+ #define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP        ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Value */
+ #define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP        (MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Setting */
+
+ #define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS                11 /**< MEMCKCN_SYSRAM3LS Position */
+ #define MXC_F_GCR_MEMCKCN_SYSRAM3LS                    ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS Mask */
+ #define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE             ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM3LS_ACTIVE Value */
+ #define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE             (MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE Setting */
+ #define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP        ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Value */
+ #define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP        (MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Setting */
+
+ #define MXC_F_GCR_MEMCKCN_ICACHELS_POS                 12 /**< MEMCKCN_ICACHELS Position */
+ #define MXC_F_GCR_MEMCKCN_ICACHELS                     ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS Mask */
+ #define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE              ((uint32_t)0x0UL) /**< MEMCKCN_ICACHELS_ACTIVE Value */
+ #define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE              (MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE Setting */
+ #define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP         ((uint32_t)0x1UL) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Value */
+ #define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP         (MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Setting */
+
+/**@} end of group GCR_MEMCKCN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_MEMZCN GCR_MEMZCN
+ * @brief    Memory Zeroize Control.
+ * @{
+ */
+ #define MXC_F_GCR_MEMZCN_SRAM0Z_POS                    0 /**< MEMZCN_SRAM0Z Position */
+ #define MXC_F_GCR_MEMZCN_SRAM0Z                        ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */
+ #define MXC_V_GCR_MEMZCN_SRAM0Z_NOP                    ((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */
+ #define MXC_S_GCR_MEMZCN_SRAM0Z_NOP                    (MXC_V_GCR_MEMZCN_SRAM0Z_NOP << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */
+ #define MXC_V_GCR_MEMZCN_SRAM0Z_START                  ((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */
+ #define MXC_S_GCR_MEMZCN_SRAM0Z_START                  (MXC_V_GCR_MEMZCN_SRAM0Z_START << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */
+
+ #define MXC_F_GCR_MEMZCN_ICACHEZ_POS                   1 /**< MEMZCN_ICACHEZ Position */
+ #define MXC_F_GCR_MEMZCN_ICACHEZ                       ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */
+ #define MXC_V_GCR_MEMZCN_ICACHEZ_NOP                   ((uint32_t)0x0UL) /**< MEMZCN_ICACHEZ_NOP Value */
+ #define MXC_S_GCR_MEMZCN_ICACHEZ_NOP                   (MXC_V_GCR_MEMZCN_ICACHEZ_NOP << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_NOP Setting */
+ #define MXC_V_GCR_MEMZCN_ICACHEZ_START                 ((uint32_t)0x1UL) /**< MEMZCN_ICACHEZ_START Value */
+ #define MXC_S_GCR_MEMZCN_ICACHEZ_START                 (MXC_V_GCR_MEMZCN_ICACHEZ_START << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_START Setting */
+
+/**@} end of group GCR_MEMZCN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_SYSST GCR_SYSST
+ * @brief    System Status Register.
+ * @{
+ */
+ #define MXC_F_GCR_SYSST_ICECLOCK_POS                   0 /**< SYSST_ICECLOCK Position */
+ #define MXC_F_GCR_SYSST_ICECLOCK                       ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */
+ #define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED              ((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */
+ #define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED              (MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting */
+ #define MXC_V_GCR_SYSST_ICECLOCK_LOCKED                ((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */
+ #define MXC_S_GCR_SYSST_ICECLOCK_LOCKED                (MXC_V_GCR_SYSST_ICECLOCK_LOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting */
+
+ #define MXC_F_GCR_SYSST_CODEINTERR_POS                 1 /**< SYSST_CODEINTERR Position */
+ #define MXC_F_GCR_SYSST_CODEINTERR                     ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR Mask */
+ #define MXC_V_GCR_SYSST_CODEINTERR_NORM                ((uint32_t)0x0UL) /**< SYSST_CODEINTERR_NORM Value */
+ #define MXC_S_GCR_SYSST_CODEINTERR_NORM                (MXC_V_GCR_SYSST_CODEINTERR_NORM << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_NORM Setting */
+ #define MXC_V_GCR_SYSST_CODEINTERR_CODE                ((uint32_t)0x1UL) /**< SYSST_CODEINTERR_CODE Value */
+ #define MXC_S_GCR_SYSST_CODEINTERR_CODE                (MXC_V_GCR_SYSST_CODEINTERR_CODE << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_CODE Setting */
+
+ #define MXC_F_GCR_SYSST_SCMEMF_POS                     5 /**< SYSST_SCMEMF Position */
+ #define MXC_F_GCR_SYSST_SCMEMF                         ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */
+ #define MXC_V_GCR_SYSST_SCMEMF_NORM                    ((uint32_t)0x0UL) /**< SYSST_SCMEMF_NORM Value */
+ #define MXC_S_GCR_SYSST_SCMEMF_NORM                    (MXC_V_GCR_SYSST_SCMEMF_NORM << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_NORM Setting */
+ #define MXC_V_GCR_SYSST_SCMEMF_MEMORY                  ((uint32_t)0x1UL) /**< SYSST_SCMEMF_MEMORY Value */
+ #define MXC_S_GCR_SYSST_SCMEMF_MEMORY                  (MXC_V_GCR_SYSST_SCMEMF_MEMORY << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_MEMORY Setting */
+
+/**@} end of group GCR_SYSST_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_RSTR1 GCR_RSTR1
+ * @brief    Reset 1.
+ * @{
+ */
+ #define MXC_F_GCR_RSTR1_I2C1_POS                       0 /**< RSTR1_I2C1 Position */
+ #define MXC_F_GCR_RSTR1_I2C1                           ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask */
+ #define MXC_V_GCR_RSTR1_I2C1_RFU                       ((uint32_t)0x0UL) /**< RSTR1_I2C1_RFU Value */
+ #define MXC_S_GCR_RSTR1_I2C1_RFU                       (MXC_V_GCR_RSTR1_I2C1_RFU << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RFU Setting */
+ #define MXC_V_GCR_RSTR1_I2C1_RESET                     ((uint32_t)0x1UL) /**< RSTR1_I2C1_RESET Value */
+ #define MXC_S_GCR_RSTR1_I2C1_RESET                     (MXC_V_GCR_RSTR1_I2C1_RESET << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET Setting */
+ #define MXC_V_GCR_RSTR1_I2C1_RESET_DONE                ((uint32_t)0x0UL) /**< RSTR1_I2C1_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR1_I2C1_RESET_DONE                (MXC_V_GCR_RSTR1_I2C1_RESET_DONE << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR1_I2C1_BUSY                      ((uint32_t)0x1UL) /**< RSTR1_I2C1_BUSY Value */
+ #define MXC_S_GCR_RSTR1_I2C1_BUSY                      (MXC_V_GCR_RSTR1_I2C1_BUSY << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_BUSY Setting */
+
+/**@} end of group GCR_RSTR1_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PERCKCN1 GCR_PERCKCN1
+ * @brief    Peripheral Clock Disable.
+ * @{
+ */
+ #define MXC_F_GCR_PERCKCN1_FLCD_POS                    3 /**< PERCKCN1_FLCD Position */
+ #define MXC_F_GCR_PERCKCN1_FLCD                        ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD Mask */
+ #define MXC_V_GCR_PERCKCN1_FLCD_EN                     ((uint32_t)0x0UL) /**< PERCKCN1_FLCD_EN Value */
+ #define MXC_S_GCR_PERCKCN1_FLCD_EN                     (MXC_V_GCR_PERCKCN1_FLCD_EN << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_EN Setting */
+ #define MXC_V_GCR_PERCKCN1_FLCD_DIS                    ((uint32_t)0x1UL) /**< PERCKCN1_FLCD_DIS Value */
+ #define MXC_S_GCR_PERCKCN1_FLCD_DIS                    (MXC_V_GCR_PERCKCN1_FLCD_DIS << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN1_ICACHED_POS                 11 /**< PERCKCN1_ICACHED Position */
+ #define MXC_F_GCR_PERCKCN1_ICACHED                     ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED Mask */
+ #define MXC_V_GCR_PERCKCN1_ICACHED_EN                  ((uint32_t)0x0UL) /**< PERCKCN1_ICACHED_EN Value */
+ #define MXC_S_GCR_PERCKCN1_ICACHED_EN                  (MXC_V_GCR_PERCKCN1_ICACHED_EN << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting */
+ #define MXC_V_GCR_PERCKCN1_ICACHED_DIS                 ((uint32_t)0x1UL) /**< PERCKCN1_ICACHED_DIS Value */
+ #define MXC_S_GCR_PERCKCN1_ICACHED_DIS                 (MXC_V_GCR_PERCKCN1_ICACHED_DIS << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting */
+
+/**@} end of group GCR_PERCKCN1_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_EVTEN GCR_EVTEN
+ * @brief    Event Enable Register.
+ * @{
+ */
+ #define MXC_F_GCR_EVTEN_DMAEVENT_POS                   0 /**< EVTEN_DMAEVENT Position */
+ #define MXC_F_GCR_EVTEN_DMAEVENT                       ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */
+
+ #define MXC_F_GCR_EVTEN_RXEVENT_POS                    1 /**< EVTEN_RXEVENT Position */
+ #define MXC_F_GCR_EVTEN_RXEVENT                        ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT Mask */
+
+/**@} end of group GCR_EVTEN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_REVISION GCR_REVISION
+ * @brief    Revision Register.
+ * @{
+ */
+ #define MXC_F_GCR_REVISION_REVISION_POS                0 /**< REVISION_REVISION Position */
+ #define MXC_F_GCR_REVISION_REVISION                    ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */
+
+/**@} end of group GCR_REVISION_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_SYSSIE GCR_SYSSIE
+ * @brief    System Status Interrupt Enable Register.
+ * @{
+ */
+ #define MXC_F_GCR_SYSSIE_ICEULIE_POS                   0 /**< SYSSIE_ICEULIE Position */
+ #define MXC_F_GCR_SYSSIE_ICEULIE                       ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */
+ #define MXC_V_GCR_SYSSIE_ICEULIE_DIS                   ((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */
+ #define MXC_S_GCR_SYSSIE_ICEULIE_DIS                   (MXC_V_GCR_SYSSIE_ICEULIE_DIS << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */
+ #define MXC_V_GCR_SYSSIE_ICEULIE_EN                    ((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */
+ #define MXC_S_GCR_SYSSIE_ICEULIE_EN                    (MXC_V_GCR_SYSSIE_ICEULIE_EN << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */
+
+ #define MXC_F_GCR_SYSSIE_CIEIE_POS                     1 /**< SYSSIE_CIEIE Position */
+ #define MXC_F_GCR_SYSSIE_CIEIE                         ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE Mask */
+ #define MXC_V_GCR_SYSSIE_CIEIE_DIS                     ((uint32_t)0x0UL) /**< SYSSIE_CIEIE_DIS Value */
+ #define MXC_S_GCR_SYSSIE_CIEIE_DIS                     (MXC_V_GCR_SYSSIE_CIEIE_DIS << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_DIS Setting */
+ #define MXC_V_GCR_SYSSIE_CIEIE_EN                      ((uint32_t)0x1UL) /**< SYSSIE_CIEIE_EN Value */
+ #define MXC_S_GCR_SYSSIE_CIEIE_EN                      (MXC_V_GCR_SYSSIE_CIEIE_EN << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_EN Setting */
+
+ #define MXC_F_GCR_SYSSIE_SCMFIE_POS                    5 /**< SYSSIE_SCMFIE Position */
+ #define MXC_F_GCR_SYSSIE_SCMFIE                        ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE Mask */
+ #define MXC_V_GCR_SYSSIE_SCMFIE_DIS                    ((uint32_t)0x0UL) /**< SYSSIE_SCMFIE_DIS Value */
+ #define MXC_S_GCR_SYSSIE_SCMFIE_DIS                    (MXC_V_GCR_SYSSIE_SCMFIE_DIS << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_DIS Setting */
+ #define MXC_V_GCR_SYSSIE_SCMFIE_EN                     ((uint32_t)0x1UL) /**< SYSSIE_SCMFIE_EN Value */
+ #define MXC_S_GCR_SYSSIE_SCMFIE_EN                     (MXC_V_GCR_SYSSIE_SCMFIE_EN << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_EN Setting */
+
+/**@} end of group GCR_SYSSIE_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GCR_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h

@@ -0,0 +1,663 @@
+/**
+ * @file    gpio_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _GPIO_REGS_H_
+#define _GPIO_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     gpio
+ * @defgroup    gpio_registers GPIO_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
+ * @details Individual I/O for each GPIO
+ */
+
+/**
+ * @ingroup gpio_registers
+ * Structure type to access the GPIO Registers.
+ */
+typedef struct {
+    __IO uint32_t en;                   /**< <tt>\b 0x00:</tt> GPIO EN Register */
+    __IO uint32_t en_set;               /**< <tt>\b 0x04:</tt> GPIO EN_SET Register */
+    __IO uint32_t en_clr;               /**< <tt>\b 0x08:</tt> GPIO EN_CLR Register */
+    __IO uint32_t out_en;               /**< <tt>\b 0x0C:</tt> GPIO OUT_EN Register */
+    __IO uint32_t out_en_set;           /**< <tt>\b 0x10:</tt> GPIO OUT_EN_SET Register */
+    __IO uint32_t out_en_clr;           /**< <tt>\b 0x14:</tt> GPIO OUT_EN_CLR Register */
+    __IO uint32_t out;                  /**< <tt>\b 0x18:</tt> GPIO OUT Register */
+    __O  uint32_t out_set;              /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */
+    __O  uint32_t out_clr;              /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */
+    __I  uint32_t in;                   /**< <tt>\b 0x24:</tt> GPIO IN Register */
+    __IO uint32_t int_mod;              /**< <tt>\b 0x28:</tt> GPIO INT_MOD Register */
+    __IO uint32_t int_pol;              /**< <tt>\b 0x2C:</tt> GPIO INT_POL Register */
+    __R  uint32_t rsv_0x30;
+    __IO uint32_t int_en;               /**< <tt>\b 0x34:</tt> GPIO INT_EN Register */
+    __IO uint32_t int_en_set;           /**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */
+    __IO uint32_t int_en_clr;           /**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */
+    __I  uint32_t int_stat;             /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */
+    __R  uint32_t rsv_0x44;
+    __IO uint32_t int_clr;              /**< <tt>\b 0x48:</tt> GPIO INT_CLR Register */
+    __IO uint32_t wake_en;              /**< <tt>\b 0x4C:</tt> GPIO WAKE_EN Register */
+    __IO uint32_t wake_en_set;          /**< <tt>\b 0x50:</tt> GPIO WAKE_EN_SET Register */
+    __IO uint32_t wake_en_clr;          /**< <tt>\b 0x54:</tt> GPIO WAKE_EN_CLR Register */
+    __R  uint32_t rsv_0x58;
+    __IO uint32_t int_dual_edge;        /**< <tt>\b 0x5C:</tt> GPIO INT_DUAL_EDGE Register */
+    __IO uint32_t pad_cfg1;             /**< <tt>\b 0x60:</tt> GPIO PAD_CFG1 Register */
+    __IO uint32_t pad_cfg2;             /**< <tt>\b 0x64:</tt> GPIO PAD_CFG2 Register */
+    __IO uint32_t en1;                  /**< <tt>\b 0x68:</tt> GPIO EN1 Register */
+    __IO uint32_t en1_set;              /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */
+    __IO uint32_t en1_clr;              /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */
+    __IO uint32_t en2;                  /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
+    __IO uint32_t en2_set;              /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
+    __IO uint32_t en2_clr;              /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
+    __R  uint32_t rsv_0x80_0xa7[10];
+    __IO uint32_t is;                   /**< <tt>\b 0xA8:</tt> GPIO IS Register */
+    __IO uint32_t sr;                   /**< <tt>\b 0xAC:</tt> GPIO SR Register */
+    __IO uint32_t ds;                   /**< <tt>\b 0xB0:</tt> GPIO DS Register */
+    __IO uint32_t ds1;                  /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */
+    __IO uint32_t ps;                   /**< <tt>\b 0xB8:</tt> GPIO PS Register */
+    __R  uint32_t rsv_0xbc;
+    __IO uint32_t vssel;                /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */
+} mxc_gpio_regs_t;
+
+/* Register offsets for module GPIO */
+/**
+ * @ingroup    gpio_registers
+ * @defgroup   GPIO_Register_Offsets Register Offsets
+ * @brief      GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_GPIO_EN                      ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_GPIO_EN_SET                  ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_GPIO_EN_CLR                  ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_GPIO_OUT_EN                  ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_GPIO_OUT_EN_SET              ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_GPIO_OUT_EN_CLR              ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_GPIO_OUT                     ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_GPIO_OUT_SET                 ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */ 
+ #define MXC_R_GPIO_OUT_CLR                 ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */ 
+ #define MXC_R_GPIO_IN                      ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_GPIO_INT_MOD                 ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */ 
+ #define MXC_R_GPIO_INT_POL                 ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */ 
+ #define MXC_R_GPIO_INT_EN                  ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */ 
+ #define MXC_R_GPIO_INT_EN_SET              ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */ 
+ #define MXC_R_GPIO_INT_EN_CLR              ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */ 
+ #define MXC_R_GPIO_INT_STAT                ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */ 
+ #define MXC_R_GPIO_INT_CLR                 ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */ 
+ #define MXC_R_GPIO_WAKE_EN                 ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */ 
+ #define MXC_R_GPIO_WAKE_EN_SET             ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */ 
+ #define MXC_R_GPIO_WAKE_EN_CLR             ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */ 
+ #define MXC_R_GPIO_INT_DUAL_EDGE           ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */ 
+ #define MXC_R_GPIO_PAD_CFG1                ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */ 
+ #define MXC_R_GPIO_PAD_CFG2                ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */ 
+ #define MXC_R_GPIO_EN1                     ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */ 
+ #define MXC_R_GPIO_EN1_SET                 ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */ 
+ #define MXC_R_GPIO_EN1_CLR                 ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */ 
+ #define MXC_R_GPIO_EN2                     ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */ 
+ #define MXC_R_GPIO_EN2_SET                 ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */ 
+ #define MXC_R_GPIO_EN2_CLR                 ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */ 
+ #define MXC_R_GPIO_IS                      ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */ 
+ #define MXC_R_GPIO_SR                      ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */ 
+ #define MXC_R_GPIO_DS                      ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */ 
+ #define MXC_R_GPIO_DS1                     ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */ 
+ #define MXC_R_GPIO_PS                      ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */ 
+ #define MXC_R_GPIO_VSSEL                   ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */ 
+/**@} end of group gpio_registers */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN GPIO_EN
+ * @brief    GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one
+ *           GPIO pin on the associated port.
+ * @{
+ */
+ #define MXC_F_GPIO_EN_GPIO_EN_POS                      0 /**< EN_GPIO_EN Position */
+ #define MXC_F_GPIO_EN_GPIO_EN                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */
+ #define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                ((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */
+ #define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE                (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */
+ #define MXC_V_GPIO_EN_GPIO_EN_GPIO                     ((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */
+ #define MXC_S_GPIO_EN_GPIO_EN_GPIO                     (MXC_V_GPIO_EN_GPIO_EN_GPIO << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */
+
+/**@} end of group GPIO_EN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN_SET GPIO_EN_SET
+ * @brief    GPIO Set Function Enable Register. Writing a 1 to one or more bits in this
+ *           register sets the bits in the same positions in GPIO_EN to 1, without affecting
+ *           other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_EN_SET_ALL_POS                      0 /**< EN_SET_ALL Position */
+ #define MXC_F_GPIO_EN_SET_ALL                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */
+
+/**@} end of group GPIO_EN_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN_CLR GPIO_EN_CLR
+ * @brief    GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this
+ *           register clears the bits in the same positions in GPIO_EN to 0, without
+ *           affecting other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_EN_CLR_ALL_POS                      0 /**< EN_CLR_ALL Position */
+ #define MXC_F_GPIO_EN_CLR_ALL                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */
+
+/**@} end of group GPIO_EN_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUT_EN GPIO_OUT_EN
+ * @brief    GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one
+ *           GPIO pin in the associated port.
+ * @{
+ */
+ #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS              0 /**< OUT_EN_GPIO_OUT_EN Position */
+ #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN                  ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */
+ #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS              ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */
+ #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS              (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */
+ #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN               ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */
+ #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN               (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */
+
+/**@} end of group GPIO_OUT_EN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUT_EN_SET GPIO_OUT_EN_SET
+ * @brief    GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits
+ *           in this register sets the bits in the same positions in GPIO_OUT_EN to 1,
+ *           without affecting other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_OUT_EN_SET_ALL_POS                  0 /**< OUT_EN_SET_ALL Position */
+ #define MXC_F_GPIO_OUT_EN_SET_ALL                      ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */
+
+/**@} end of group GPIO_OUT_EN_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUT_EN_CLR GPIO_OUT_EN_CLR
+ * @brief    GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more
+ *           bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0,
+ *           without affecting other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS                  0 /**< OUT_EN_CLR_ALL Position */
+ #define MXC_F_GPIO_OUT_EN_CLR_ALL                      ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */
+
+/**@} end of group GPIO_OUT_EN_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUT GPIO_OUT
+ * @brief    GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the
+ *           associated port.  This register can be written either directly, or by using the
+ *           GPIO_OUT_SET and GPIO_OUT_CLR registers.
+ * @{
+ */
+ #define MXC_F_GPIO_OUT_GPIO_OUT_POS                    0 /**< OUT_GPIO_OUT Position */
+ #define MXC_F_GPIO_OUT_GPIO_OUT                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
+ #define MXC_V_GPIO_OUT_GPIO_OUT_LOW                    ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
+ #define MXC_S_GPIO_OUT_GPIO_OUT_LOW                    (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
+ #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH                   ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
+ #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH                   (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
+
+/**@} end of group GPIO_OUT_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUT_SET GPIO_OUT_SET
+ * @brief    GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits
+ *           in the same positions in GPIO_OUT to 1, without affecting other bits in that
+ *           register.
+ * @{
+ */
+ #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS            0 /**< OUT_SET_GPIO_OUT_SET Position */
+ #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET                ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */
+ #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO             ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
+ #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO             (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */
+ #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET            ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
+ #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET            (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */
+
+/**@} end of group GPIO_OUT_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR
+ * @brief    GPIO Output Clear. Writing a 1 to one or more bits in this register clears the
+ *           bits in the same positions in GPIO_OUT to 0, without affecting other bits in
+ *           that register.
+ * @{
+ */
+ #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS            0 /**< OUT_CLR_GPIO_OUT_CLR Position */
+ #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR                ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */
+
+/**@} end of group GPIO_OUT_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_IN GPIO_IN
+ * @brief    GPIO Input Register. Read-only register to read from the logic states of the
+ *           GPIO pins on this port.
+ * @{
+ */
+ #define MXC_F_GPIO_IN_GPIO_IN_POS                      0 /**< IN_GPIO_IN Position */
+ #define MXC_F_GPIO_IN_GPIO_IN                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
+
+/**@} end of group GPIO_IN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INT_MOD GPIO_INT_MOD
+ * @brief    GPIO Interrupt Mode Register. Each bit in this register controls the interrupt
+ *           mode setting for the associated GPIO pin on this port.
+ * @{
+ */
+ #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS            0 /**< INT_MOD_GPIO_INT_MOD Position */
+ #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD                ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */
+ #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL          ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */
+ #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL          (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */
+ #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE           ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */
+ #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE           (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */
+
+/**@} end of group GPIO_INT_MOD_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INT_POL GPIO_INT_POL
+ * @brief    GPIO Interrupt Polarity Register. Each bit in this register controls the
+ *           interrupt polarity setting for one GPIO pin in the associated port.
+ * @{
+ */
+ #define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS            0 /**< INT_POL_GPIO_INT_POL Position */
+ #define MXC_F_GPIO_INT_POL_GPIO_INT_POL                ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */
+ #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING        ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */
+ #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING        (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */
+ #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING         ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */
+ #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING         (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */
+
+/**@} end of group GPIO_INT_POL_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INT_EN GPIO_INT_EN
+ * @brief    GPIO Interrupt Enable Register. Each bit in this register controls the GPIO
+ *           interrupt enable for the associated pin on the GPIO port.
+ * @{
+ */
+ #define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS              0 /**< INT_EN_GPIO_INT_EN Position */
+ #define MXC_F_GPIO_INT_EN_GPIO_INT_EN                  ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */
+ #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS              ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */
+ #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS              (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */
+ #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN               ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */
+ #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN               (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */
+
+/**@} end of group GPIO_INT_EN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INT_EN_SET GPIO_INT_EN_SET
+ * @brief    GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets
+ *           the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits
+ *           in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS      0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */
+ #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET          ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */
+ #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO       ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */
+ #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO       (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */
+ #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET      ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */
+ #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET      (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */
+
+/**@} end of group GPIO_INT_EN_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INT_EN_CLR GPIO_INT_EN_CLR
+ * @brief    GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register
+ *           clears the bits in the same positions in GPIO_INT_EN to 0, without affecting
+ *           other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS      0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */
+ #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR          ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */
+ #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO       ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */
+ #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO       (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */
+ #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR    ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */
+ #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR    (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */
+
+/**@} end of group GPIO_INT_EN_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INT_STAT GPIO_INT_STAT
+ * @brief    GPIO Interrupt Status Register. Each bit in this register contains the pending
+ *           interrupt status for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS          0 /**< INT_STAT_GPIO_INT_STAT Position */
+ #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT              ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */
+ #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO           ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */
+ #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO           (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */
+ #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING      ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */
+ #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING      (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */
+
+/**@} end of group GPIO_INT_STAT_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INT_CLR GPIO_INT_CLR
+ * @brief    GPIO Status Clear. Writing a 1 to one or more bits in this register clears the
+ *           bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits
+ *           in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_INT_CLR_ALL_POS                     0 /**< INT_CLR_ALL Position */
+ #define MXC_F_GPIO_INT_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */
+
+/**@} end of group GPIO_INT_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_WAKE_EN GPIO_WAKE_EN
+ * @brief    GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup
+ *           enable for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS            0 /**< WAKE_EN_GPIO_WAKE_EN Position */
+ #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN                ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */
+ #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS            ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */
+ #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS            (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */
+ #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN             ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */
+ #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN             (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */
+
+/**@} end of group GPIO_WAKE_EN_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_WAKE_EN_SET GPIO_WAKE_EN_SET
+ * @brief    GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the
+ *           bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in
+ *           that register.
+ * @{
+ */
+ #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS                 0 /**< WAKE_EN_SET_ALL Position */
+ #define MXC_F_GPIO_WAKE_EN_SET_ALL                     ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */
+
+/**@} end of group GPIO_WAKE_EN_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_WAKE_EN_CLR GPIO_WAKE_EN_CLR
+ * @brief    GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears
+ *           the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other
+ *           bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS                 0 /**< WAKE_EN_CLR_ALL Position */
+ #define MXC_F_GPIO_WAKE_EN_CLR_ALL                     ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */
+
+/**@} end of group GPIO_WAKE_EN_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_INT_DUAL_EDGE GPIO_INT_DUAL_EDGE
+ * @brief    GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual
+ *           edge mode for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */
+ #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE    ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */
+ #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */
+ #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */
+ #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */
+ #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */
+
+/**@} end of group GPIO_INT_DUAL_EDGE_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_PAD_CFG1 GPIO_PAD_CFG1
+ * @brief    GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for
+ *           the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS          0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */
+ #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1              ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */
+ #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE    ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */
+ #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE    (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */
+ #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU           ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */
+ #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU           (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */
+ #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD           ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */
+ #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD           (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */
+
+/**@} end of group GPIO_PAD_CFG1_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_PAD_CFG2 GPIO_PAD_CFG2
+ * @brief    GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for
+ *           the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS          0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */
+ #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2              ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */
+ #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE    ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */
+ #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE    (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */
+ #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU           ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */
+ #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU           (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */
+ #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD           ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */
+ #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD           (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */
+
+/**@} end of group GPIO_PAD_CFG2_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN1 GPIO_EN1
+ * @brief    GPIO Alternate Function Enable Register. Each bit in this register selects
+ *           between primary/secondary functions for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_EN1_GPIO_EN1_POS                    0 /**< EN1_GPIO_EN1 Position */
+ #define MXC_F_GPIO_EN1_GPIO_EN1                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
+ #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
+ #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY                (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
+ #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY              ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
+ #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY              (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */
+
+/**@} end of group GPIO_EN1_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN1_SET GPIO_EN1_SET
+ * @brief    GPIO Alternate Function Set. Writing a 1 to one or more bits in this register
+ *           sets the bits in the same positions in GPIO_EN1 to 1, without affecting other
+ *           bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_EN1_SET_ALL_POS                     0 /**< EN1_SET_ALL Position */
+ #define MXC_F_GPIO_EN1_SET_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
+
+/**@} end of group GPIO_EN1_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR
+ * @brief    GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register
+ *           clears the bits in the same positions in GPIO_EN1 to 0, without affecting other
+ *           bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_EN1_CLR_ALL_POS                     0 /**< EN1_CLR_ALL Position */
+ #define MXC_F_GPIO_EN1_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
+
+/**@} end of group GPIO_EN1_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN2 GPIO_EN2
+ * @brief    GPIO Alternate Function Enable Register. Each bit in this register selects
+ *           between primary/secondary functions for the associated GPIO pin in this port.
+ * @{
+ */
+ #define MXC_F_GPIO_EN2_GPIO_EN2_POS                    0 /**< EN2_GPIO_EN2 Position */
+ #define MXC_F_GPIO_EN2_GPIO_EN2                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
+ #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
+ #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY                (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
+ #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY              ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
+ #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY              (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */
+
+/**@} end of group GPIO_EN2_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN2_SET GPIO_EN2_SET
+ * @brief    GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register
+ *           sets the bits in the same positions in GPIO_EN2 to 1, without affecting other
+ *           bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_EN2_SET_ALL_POS                     0 /**< EN2_SET_ALL Position */
+ #define MXC_F_GPIO_EN2_SET_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
+
+/**@} end of group GPIO_EN2_SET_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR
+ * @brief    GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this
+ *           register clears the bits in the same positions in GPIO_EN2 to 0, without
+ *           affecting other bits in that register.
+ * @{
+ */
+ #define MXC_F_GPIO_EN2_CLR_ALL_POS                     0 /**< EN2_CLR_ALL Position */
+ #define MXC_F_GPIO_EN2_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
+
+/**@} end of group GPIO_EN2_CLR_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_DS GPIO_DS
+ * @brief    GPIO Drive Strength  Register. Each bit in this register selects the drive
+ *           strength for the associated GPIO pin in this port. Refer to the Datasheet for
+ *           sink/source current of GPIO pins in each mode.
+ * @{
+ */
+ #define MXC_F_GPIO_DS_DS_POS                           0 /**< DS_DS Position */
+ #define MXC_F_GPIO_DS_DS                               ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */
+ #define MXC_V_GPIO_DS_DS_LD                            ((uint32_t)0x0UL) /**< DS_DS_LD Value */
+ #define MXC_S_GPIO_DS_DS_LD                            (MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */
+ #define MXC_V_GPIO_DS_DS_HD                            ((uint32_t)0x1UL) /**< DS_DS_HD Value */
+ #define MXC_S_GPIO_DS_DS_HD                            (MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */
+
+/**@} end of group GPIO_DS_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_DS1 GPIO_DS1
+ * @brief    GPIO Drive Strength 1 Register. Each bit in this register selects the drive
+ *           strength for the associated GPIO pin in this port. Refer to the Datasheet for
+ *           sink/source current of GPIO pins in each mode.
+ * @{
+ */
+ #define MXC_F_GPIO_DS1_ALL_POS                         0 /**< DS1_ALL Position */
+ #define MXC_F_GPIO_DS1_ALL                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */
+
+/**@} end of group GPIO_DS1_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_PS GPIO_PS
+ * @brief    GPIO Pull Select Mode.
+ * @{
+ */
+ #define MXC_F_GPIO_PS_ALL_POS                          0 /**< PS_ALL Position */
+ #define MXC_F_GPIO_PS_ALL                              ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */
+
+/**@} end of group GPIO_PS_Register */
+
+/**
+ * @ingroup  gpio_registers
+ * @defgroup GPIO_VSSEL GPIO_VSSEL
+ * @brief    GPIO Voltage Select.
+ * @{
+ */
+ #define MXC_F_GPIO_VSSEL_ALL_POS                       0 /**< VSSEL_ALL Position */
+ #define MXC_F_GPIO_VSSEL_ALL                           ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
+
+/**@} end of group GPIO_VSSEL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GPIO_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h

@@ -0,0 +1,843 @@
+/**
+ * @file    i2c_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _I2C_REGS_H_
+#define _I2C_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     i2c
+ * @defgroup    i2c_registers I2C_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
+ * @details Inter-Integrated Circuit.
+ */
+
+/**
+ * @ingroup i2c_registers
+ * Structure type to access the I2C Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x00:</tt> I2C CTRL Register */
+    __IO uint32_t status;               /**< <tt>\b 0x04:</tt> I2C STATUS Register */
+    __IO uint32_t int_fl0;              /**< <tt>\b 0x08:</tt> I2C INT_FL0 Register */
+    __IO uint32_t int_en0;              /**< <tt>\b 0x0C:</tt> I2C INT_EN0 Register */
+    __IO uint32_t int_fl1;              /**< <tt>\b 0x10:</tt> I2C INT_FL1 Register */
+    __IO uint32_t int_en1;              /**< <tt>\b 0x14:</tt> I2C INT_EN1 Register */
+    __IO uint32_t fifo_len;             /**< <tt>\b 0x18:</tt> I2C FIFO_LEN Register */
+    __IO uint32_t rx_ctrl0;             /**< <tt>\b 0x1C:</tt> I2C RX_CTRL0 Register */
+    __IO uint32_t rx_ctrl1;             /**< <tt>\b 0x20:</tt> I2C RX_CTRL1 Register */
+    __IO uint32_t tx_ctrl0;             /**< <tt>\b 0x24:</tt> I2C TX_CTRL0 Register */
+    __IO uint32_t tx_ctrl1;             /**< <tt>\b 0x28:</tt> I2C TX_CTRL1 Register */
+    __IO uint32_t fifo;                 /**< <tt>\b 0x2C:</tt> I2C FIFO Register */
+    __IO uint32_t master_ctrl;          /**< <tt>\b 0x30:</tt> I2C MASTER_CTRL Register */
+    __IO uint32_t clk_lo;               /**< <tt>\b 0x34:</tt> I2C CLK_LO Register */
+    __IO uint32_t clk_hi;               /**< <tt>\b 0x38:</tt> I2C CLK_HI Register */
+    __IO uint32_t hs_clk;               /**< <tt>\b 0x3C:</tt> I2C HS_CLK Register */
+    __IO uint32_t timeout;              /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */
+    __IO uint32_t slave_addr;           /**< <tt>\b 0x44:</tt> I2C SLAVE_ADDR Register */
+    __IO uint32_t dma;                  /**< <tt>\b 0x48:</tt> I2C DMA Register */
+} mxc_i2c_regs_t;
+
+/* Register offsets for module I2C */
+/**
+ * @ingroup    i2c_registers
+ * @defgroup   I2C_Register_Offsets Register Offsets
+ * @brief      I2C Peripheral Register Offsets from the I2C Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_I2C_CTRL                     ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_I2C_STATUS                   ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_I2C_INT_FL0                  ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_I2C_INT_EN0                  ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_I2C_INT_FL1                  ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_I2C_INT_EN1                  ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_I2C_FIFO_LEN                 ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_I2C_RX_CTRL0                 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */ 
+ #define MXC_R_I2C_RX_CTRL1                 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */ 
+ #define MXC_R_I2C_TX_CTRL0                 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_I2C_TX_CTRL1                 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */ 
+ #define MXC_R_I2C_FIFO                     ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */ 
+ #define MXC_R_I2C_MASTER_CTRL              ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */ 
+ #define MXC_R_I2C_CLK_LO                   ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */ 
+ #define MXC_R_I2C_CLK_HI                   ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */ 
+ #define MXC_R_I2C_HS_CLK                   ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */ 
+ #define MXC_R_I2C_TIMEOUT                  ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */ 
+ #define MXC_R_I2C_SLAVE_ADDR               ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> 0x0044</tt> */ 
+ #define MXC_R_I2C_DMA                      ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */ 
+/**@} end of group i2c_registers */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_CTRL I2C_CTRL
+ * @brief    Control Register0.
+ * @{
+ */
+ #define MXC_F_I2C_CTRL_I2C_EN_POS                      0 /**< CTRL_I2C_EN Position */
+ #define MXC_F_I2C_CTRL_I2C_EN                          ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */
+ #define MXC_V_I2C_CTRL_I2C_EN_DIS                      ((uint32_t)0x0UL) /**< CTRL_I2C_EN_DIS Value */
+ #define MXC_S_I2C_CTRL_I2C_EN_DIS                      (MXC_V_I2C_CTRL_I2C_EN_DIS << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_DIS Setting */
+ #define MXC_V_I2C_CTRL_I2C_EN_EN                       ((uint32_t)0x1UL) /**< CTRL_I2C_EN_EN Value */
+ #define MXC_S_I2C_CTRL_I2C_EN_EN                       (MXC_V_I2C_CTRL_I2C_EN_EN << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_EN Setting */
+
+ #define MXC_F_I2C_CTRL_MST_POS                         1 /**< CTRL_MST Position */
+ #define MXC_F_I2C_CTRL_MST                             ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */
+ #define MXC_V_I2C_CTRL_MST_SLAVE_MODE                  ((uint32_t)0x0UL) /**< CTRL_MST_SLAVE_MODE Value */
+ #define MXC_S_I2C_CTRL_MST_SLAVE_MODE                  (MXC_V_I2C_CTRL_MST_SLAVE_MODE << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_SLAVE_MODE Setting */
+ #define MXC_V_I2C_CTRL_MST_MASTER_MODE                 ((uint32_t)0x1UL) /**< CTRL_MST_MASTER_MODE Value */
+ #define MXC_S_I2C_CTRL_MST_MASTER_MODE                 (MXC_V_I2C_CTRL_MST_MASTER_MODE << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_MASTER_MODE Setting */
+
+ #define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS               2 /**< CTRL_GEN_CALL_ADDR Position */
+ #define MXC_F_I2C_CTRL_GEN_CALL_ADDR                   ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR Mask */
+ #define MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS               ((uint32_t)0x0UL) /**< CTRL_GEN_CALL_ADDR_DIS Value */
+ #define MXC_S_I2C_CTRL_GEN_CALL_ADDR_DIS               (MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_DIS Setting */
+ #define MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN                ((uint32_t)0x1UL) /**< CTRL_GEN_CALL_ADDR_EN Value */
+ #define MXC_S_I2C_CTRL_GEN_CALL_ADDR_EN                (MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_EN Setting */
+
+ #define MXC_F_I2C_CTRL_RX_MODE_POS                     3 /**< CTRL_RX_MODE Position */
+ #define MXC_F_I2C_CTRL_RX_MODE                         ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */
+ #define MXC_V_I2C_CTRL_RX_MODE_DIS                     ((uint32_t)0x0UL) /**< CTRL_RX_MODE_DIS Value */
+ #define MXC_S_I2C_CTRL_RX_MODE_DIS                     (MXC_V_I2C_CTRL_RX_MODE_DIS << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_DIS Setting */
+ #define MXC_V_I2C_CTRL_RX_MODE_EN                      ((uint32_t)0x1UL) /**< CTRL_RX_MODE_EN Value */
+ #define MXC_S_I2C_CTRL_RX_MODE_EN                      (MXC_V_I2C_CTRL_RX_MODE_EN << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_EN Setting */
+
+ #define MXC_F_I2C_CTRL_RX_MODE_ACK_POS                 4 /**< CTRL_RX_MODE_ACK Position */
+ #define MXC_F_I2C_CTRL_RX_MODE_ACK                     ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK Mask */
+ #define MXC_V_I2C_CTRL_RX_MODE_ACK_ACK                 ((uint32_t)0x0UL) /**< CTRL_RX_MODE_ACK_ACK Value */
+ #define MXC_S_I2C_CTRL_RX_MODE_ACK_ACK                 (MXC_V_I2C_CTRL_RX_MODE_ACK_ACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_ACK Setting */
+ #define MXC_V_I2C_CTRL_RX_MODE_ACK_NACK                ((uint32_t)0x1UL) /**< CTRL_RX_MODE_ACK_NACK Value */
+ #define MXC_S_I2C_CTRL_RX_MODE_ACK_NACK                (MXC_V_I2C_CTRL_RX_MODE_ACK_NACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_NACK Setting */
+
+ #define MXC_F_I2C_CTRL_SCL_OUT_POS                     6 /**< CTRL_SCL_OUT Position */
+ #define MXC_F_I2C_CTRL_SCL_OUT                         ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */
+ #define MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW           ((uint32_t)0x0UL) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Value */
+ #define MXC_S_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW           (MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Setting */
+ #define MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL             ((uint32_t)0x1UL) /**< CTRL_SCL_OUT_RELEASE_SCL Value */
+ #define MXC_S_I2C_CTRL_SCL_OUT_RELEASE_SCL             (MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_RELEASE_SCL Setting */
+
+ #define MXC_F_I2C_CTRL_SDA_OUT_POS                     7 /**< CTRL_SDA_OUT Position */
+ #define MXC_F_I2C_CTRL_SDA_OUT                         ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */
+ #define MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW           ((uint32_t)0x0UL) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Value */
+ #define MXC_S_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW           (MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Setting */
+ #define MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA             ((uint32_t)0x1UL) /**< CTRL_SDA_OUT_RELEASE_SDA Value */
+ #define MXC_S_I2C_CTRL_SDA_OUT_RELEASE_SDA             (MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_RELEASE_SDA Setting */
+
+ #define MXC_F_I2C_CTRL_SCL_POS                         8 /**< CTRL_SCL Position */
+ #define MXC_F_I2C_CTRL_SCL                             ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */
+
+ #define MXC_F_I2C_CTRL_SDA_POS                         9 /**< CTRL_SDA Position */
+ #define MXC_F_I2C_CTRL_SDA                             ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */
+
+ #define MXC_F_I2C_CTRL_SW_OUT_EN_POS                   10 /**< CTRL_SW_OUT_EN Position */
+ #define MXC_F_I2C_CTRL_SW_OUT_EN                       ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */
+ #define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE       ((uint32_t)0x0UL) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Value */
+ #define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE       (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Setting */
+ #define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE        ((uint32_t)0x1UL) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Value */
+ #define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE        (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Setting */
+
+ #define MXC_F_I2C_CTRL_READ_POS                        11 /**< CTRL_READ Position */
+ #define MXC_F_I2C_CTRL_READ                            ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */
+ #define MXC_V_I2C_CTRL_READ_WRITE                      ((uint32_t)0x0UL) /**< CTRL_READ_WRITE Value */
+ #define MXC_S_I2C_CTRL_READ_WRITE                      (MXC_V_I2C_CTRL_READ_WRITE << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_WRITE Setting */
+ #define MXC_V_I2C_CTRL_READ_READ                       ((uint32_t)0x1UL) /**< CTRL_READ_READ Value */
+ #define MXC_S_I2C_CTRL_READ_READ                       (MXC_V_I2C_CTRL_READ_READ << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_READ Setting */
+
+ #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS          12 /**< CTRL_SCL_CLK_STRECH_DIS Position */
+ #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS              ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) /**< CTRL_SCL_CLK_STRECH_DIS Mask */
+ #define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN           ((uint32_t)0x0UL) /**< CTRL_SCL_CLK_STRECH_DIS_EN Value */
+ #define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_EN           (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< CTRL_SCL_CLK_STRECH_DIS_EN Setting */
+ #define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS          ((uint32_t)0x1UL) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Value */
+ #define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS          (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Setting */
+
+ #define MXC_F_I2C_CTRL_SCL_PP_MODE_POS                 13 /**< CTRL_SCL_PP_MODE Position */
+ #define MXC_F_I2C_CTRL_SCL_PP_MODE                     ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE Mask */
+ #define MXC_V_I2C_CTRL_SCL_PP_MODE_DIS                 ((uint32_t)0x0UL) /**< CTRL_SCL_PP_MODE_DIS Value */
+ #define MXC_S_I2C_CTRL_SCL_PP_MODE_DIS                 (MXC_V_I2C_CTRL_SCL_PP_MODE_DIS << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_DIS Setting */
+ #define MXC_V_I2C_CTRL_SCL_PP_MODE_EN                  ((uint32_t)0x1UL) /**< CTRL_SCL_PP_MODE_EN Value */
+ #define MXC_S_I2C_CTRL_SCL_PP_MODE_EN                  (MXC_V_I2C_CTRL_SCL_PP_MODE_EN << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_EN Setting */
+
+ #define MXC_F_I2C_CTRL_HS_MODE_POS                     15 /**< CTRL_HS_MODE Position */
+ #define MXC_F_I2C_CTRL_HS_MODE                         ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_MODE_POS)) /**< CTRL_HS_MODE Mask */
+ #define MXC_V_I2C_CTRL_HS_MODE_DIS                     ((uint32_t)0x0UL) /**< CTRL_HS_MODE_DIS Value */
+ #define MXC_S_I2C_CTRL_HS_MODE_DIS                     (MXC_V_I2C_CTRL_HS_MODE_DIS << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_DIS Setting */
+ #define MXC_V_I2C_CTRL_HS_MODE_EN                      ((uint32_t)0x1UL) /**< CTRL_HS_MODE_EN Value */
+ #define MXC_S_I2C_CTRL_HS_MODE_EN                      (MXC_V_I2C_CTRL_HS_MODE_EN << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_EN Setting */
+
+/**@} end of group I2C_CTRL_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_STATUS I2C_STATUS
+ * @brief    Status Register.
+ * @{
+ */
+ #define MXC_F_I2C_STATUS_BUS_POS                       0 /**< STATUS_BUS Position */
+ #define MXC_F_I2C_STATUS_BUS                           ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask */
+ #define MXC_V_I2C_STATUS_BUS_IDLE                      ((uint32_t)0x0UL) /**< STATUS_BUS_IDLE Value */
+ #define MXC_S_I2C_STATUS_BUS_IDLE                      (MXC_V_I2C_STATUS_BUS_IDLE << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_IDLE Setting */
+ #define MXC_V_I2C_STATUS_BUS_BUSY                      ((uint32_t)0x1UL) /**< STATUS_BUS_BUSY Value */
+ #define MXC_S_I2C_STATUS_BUS_BUSY                      (MXC_V_I2C_STATUS_BUS_BUSY << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_BUSY Setting */
+
+ #define MXC_F_I2C_STATUS_RX_EMPTY_POS                  1 /**< STATUS_RX_EMPTY Position */
+ #define MXC_F_I2C_STATUS_RX_EMPTY                      ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */
+ #define MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY            ((uint32_t)0x0UL) /**< STATUS_RX_EMPTY_NOT_EMPTY Value */
+ #define MXC_S_I2C_STATUS_RX_EMPTY_NOT_EMPTY            (MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_NOT_EMPTY Setting */
+ #define MXC_V_I2C_STATUS_RX_EMPTY_EMPTY                ((uint32_t)0x1UL) /**< STATUS_RX_EMPTY_EMPTY Value */
+ #define MXC_S_I2C_STATUS_RX_EMPTY_EMPTY                (MXC_V_I2C_STATUS_RX_EMPTY_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_EMPTY Setting */
+
+ #define MXC_F_I2C_STATUS_RX_FULL_POS                   2 /**< STATUS_RX_FULL Position */
+ #define MXC_F_I2C_STATUS_RX_FULL                       ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
+ #define MXC_V_I2C_STATUS_RX_FULL_NOT_FULL              ((uint32_t)0x0UL) /**< STATUS_RX_FULL_NOT_FULL Value */
+ #define MXC_S_I2C_STATUS_RX_FULL_NOT_FULL              (MXC_V_I2C_STATUS_RX_FULL_NOT_FULL << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_NOT_FULL Setting */
+ #define MXC_V_I2C_STATUS_RX_FULL_FULL                  ((uint32_t)0x1UL) /**< STATUS_RX_FULL_FULL Value */
+ #define MXC_S_I2C_STATUS_RX_FULL_FULL                  (MXC_V_I2C_STATUS_RX_FULL_FULL << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_FULL Setting */
+
+ #define MXC_F_I2C_STATUS_TX_EMPTY_POS                  3 /**< STATUS_TX_EMPTY Position */
+ #define MXC_F_I2C_STATUS_TX_EMPTY                      ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */
+ #define MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY            ((uint32_t)0x0UL) /**< STATUS_TX_EMPTY_NOT_EMPTY Value */
+ #define MXC_S_I2C_STATUS_TX_EMPTY_NOT_EMPTY            (MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_NOT_EMPTY Setting */
+ #define MXC_V_I2C_STATUS_TX_EMPTY_EMPTY                ((uint32_t)0x1UL) /**< STATUS_TX_EMPTY_EMPTY Value */
+ #define MXC_S_I2C_STATUS_TX_EMPTY_EMPTY                (MXC_V_I2C_STATUS_TX_EMPTY_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_EMPTY Setting */
+
+ #define MXC_F_I2C_STATUS_TX_FULL_POS                   4 /**< STATUS_TX_FULL Position */
+ #define MXC_F_I2C_STATUS_TX_FULL                       ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
+ #define MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY             ((uint32_t)0x0UL) /**< STATUS_TX_FULL_NOT_EMPTY Value */
+ #define MXC_S_I2C_STATUS_TX_FULL_NOT_EMPTY             (MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_NOT_EMPTY Setting */
+ #define MXC_V_I2C_STATUS_TX_FULL_EMPTY                 ((uint32_t)0x1UL) /**< STATUS_TX_FULL_EMPTY Value */
+ #define MXC_S_I2C_STATUS_TX_FULL_EMPTY                 (MXC_V_I2C_STATUS_TX_FULL_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_EMPTY Setting */
+
+ #define MXC_F_I2C_STATUS_CLK_MODE_POS                  5 /**< STATUS_CLK_MODE Position */
+ #define MXC_F_I2C_STATUS_CLK_MODE                      ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE Mask */
+ #define MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK ((uint32_t)0x0UL) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Value */
+ #define MXC_S_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK (MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Setting */
+ #define MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK ((uint32_t)0x1UL) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Value */
+ #define MXC_S_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK (MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Setting */
+
+ #define MXC_F_I2C_STATUS_STATUS_POS                    8 /**< STATUS_STATUS Position */
+ #define MXC_F_I2C_STATUS_STATUS                        ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */
+ #define MXC_V_I2C_STATUS_STATUS_IDLE                   ((uint32_t)0x0UL) /**< STATUS_STATUS_IDLE Value */
+ #define MXC_S_I2C_STATUS_STATUS_IDLE                   (MXC_V_I2C_STATUS_STATUS_IDLE << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_IDLE Setting */
+ #define MXC_V_I2C_STATUS_STATUS_MTX_ADDR               ((uint32_t)0x1UL) /**< STATUS_STATUS_MTX_ADDR Value */
+ #define MXC_S_I2C_STATUS_STATUS_MTX_ADDR               (MXC_V_I2C_STATUS_STATUS_MTX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_ADDR Setting */
+ #define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK           ((uint32_t)0x2UL) /**< STATUS_STATUS_MRX_ADDR_ACK Value */
+ #define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK           (MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_ADDR_ACK Setting */
+ #define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR            ((uint32_t)0x3UL) /**< STATUS_STATUS_MTX_EX_ADDR Value */
+ #define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR            (MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_EX_ADDR Setting */
+ #define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR            ((uint32_t)0x4UL) /**< STATUS_STATUS_MRX_EX_ADDR Value */
+ #define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR            (MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_EX_ADDR Setting */
+ #define MXC_V_I2C_STATUS_STATUS_SRX_ADDR               ((uint32_t)0x5UL) /**< STATUS_STATUS_SRX_ADDR Value */
+ #define MXC_S_I2C_STATUS_STATUS_SRX_ADDR               (MXC_V_I2C_STATUS_STATUS_SRX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_ADDR Setting */
+ #define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK           ((uint32_t)0x6UL) /**< STATUS_STATUS_STX_ADDR_ACK Value */
+ #define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK           (MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_ADDR_ACK Setting */
+ #define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR            ((uint32_t)0x7UL) /**< STATUS_STATUS_SRX_EX_ADDR Value */
+ #define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR            (MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_EX_ADDR Setting */
+ #define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK        ((uint32_t)0x8UL) /**< STATUS_STATUS_STX_EX_ADDR_ACK Value */
+ #define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK        (MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_EX_ADDR_ACK Setting */
+ #define MXC_V_I2C_STATUS_STATUS_TX                     ((uint32_t)0x9UL) /**< STATUS_STATUS_TX Value */
+ #define MXC_S_I2C_STATUS_STATUS_TX                     (MXC_V_I2C_STATUS_STATUS_TX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX Setting */
+ #define MXC_V_I2C_STATUS_STATUS_RX_ACK                 ((uint32_t)0xAUL) /**< STATUS_STATUS_RX_ACK Value */
+ #define MXC_S_I2C_STATUS_STATUS_RX_ACK                 (MXC_V_I2C_STATUS_STATUS_RX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX_ACK Setting */
+ #define MXC_V_I2C_STATUS_STATUS_RX                     ((uint32_t)0xBUL) /**< STATUS_STATUS_RX Value */
+ #define MXC_S_I2C_STATUS_STATUS_RX                     (MXC_V_I2C_STATUS_STATUS_RX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX Setting */
+ #define MXC_V_I2C_STATUS_STATUS_TX_ACK                 ((uint32_t)0xCUL) /**< STATUS_STATUS_TX_ACK Value */
+ #define MXC_S_I2C_STATUS_STATUS_TX_ACK                 (MXC_V_I2C_STATUS_STATUS_TX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX_ACK Setting */
+ #define MXC_V_I2C_STATUS_STATUS_NACK                   ((uint32_t)0xDUL) /**< STATUS_STATUS_NACK Value */
+ #define MXC_S_I2C_STATUS_STATUS_NACK                   (MXC_V_I2C_STATUS_STATUS_NACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_NACK Setting */
+ #define MXC_V_I2C_STATUS_STATUS_BY_ST                  ((uint32_t)0xFUL) /**< STATUS_STATUS_BY_ST Value */
+ #define MXC_S_I2C_STATUS_STATUS_BY_ST                  (MXC_V_I2C_STATUS_STATUS_BY_ST << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_BY_ST Setting */
+
+/**@} end of group I2C_STATUS_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_INT_FL0 I2C_INT_FL0
+ * @brief    Interrupt Status Register.
+ * @{
+ */
+ #define MXC_F_I2C_INT_FL0_DONE_POS                     0 /**< INT_FL0_DONE Position */
+ #define MXC_F_I2C_INT_FL0_DONE                         ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */
+ #define MXC_V_I2C_INT_FL0_DONE_INACTIVE                ((uint32_t)0x0UL) /**< INT_FL0_DONE_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_DONE_INACTIVE                (MXC_V_I2C_INT_FL0_DONE_INACTIVE << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_DONE_PENDING                 ((uint32_t)0x1UL) /**< INT_FL0_DONE_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_DONE_PENDING                 (MXC_V_I2C_INT_FL0_DONE_PENDING << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_RX_MODE_POS                  1 /**< INT_FL0_RX_MODE Position */
+ #define MXC_F_I2C_INT_FL0_RX_MODE                      ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE Mask */
+ #define MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE             ((uint32_t)0x0UL) /**< INT_FL0_RX_MODE_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_RX_MODE_INACTIVE             (MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_RX_MODE_PENDING              ((uint32_t)0x1UL) /**< INT_FL0_RX_MODE_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_RX_MODE_PENDING              (MXC_V_I2C_INT_FL0_RX_MODE_PENDING << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS            2 /**< INT_FL0_GEN_CALL_ADDR Position */
+ #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR                ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**< INT_FL0_GEN_CALL_ADDR Mask */
+ #define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE       ((uint32_t)0x0UL) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE       (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING        ((uint32_t)0x1UL) /**< INT_FL0_GEN_CALL_ADDR_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_PENDING        (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< INT_FL0_GEN_CALL_ADDR_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS               3 /**< INT_FL0_ADDR_MATCH Position */
+ #define MXC_F_I2C_INT_FL0_ADDR_MATCH                   ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH Mask */
+ #define MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE          ((uint32_t)0x0UL) /**< INT_FL0_ADDR_MATCH_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_ADDR_MATCH_INACTIVE          (MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING           ((uint32_t)0x1UL) /**< INT_FL0_ADDR_MATCH_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_ADDR_MATCH_PENDING           (MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_RX_THRESH_POS                4 /**< INT_FL0_RX_THRESH Position */
+ #define MXC_F_I2C_INT_FL0_RX_THRESH                    ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH Mask */
+ #define MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE           ((uint32_t)0x0UL) /**< INT_FL0_RX_THRESH_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_RX_THRESH_INACTIVE           (MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_RX_THRESH_PENDING            ((uint32_t)0x1UL) /**< INT_FL0_RX_THRESH_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_RX_THRESH_PENDING            (MXC_V_I2C_INT_FL0_RX_THRESH_PENDING << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_TX_THRESH_POS                5 /**< INT_FL0_TX_THRESH Position */
+ #define MXC_F_I2C_INT_FL0_TX_THRESH                    ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH Mask */
+ #define MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE           ((uint32_t)0x0UL) /**< INT_FL0_TX_THRESH_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_TX_THRESH_INACTIVE           (MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_TX_THRESH_PENDING            ((uint32_t)0x1UL) /**< INT_FL0_TX_THRESH_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_TX_THRESH_PENDING            (MXC_V_I2C_INT_FL0_TX_THRESH_PENDING << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_STOP_POS                     6 /**< INT_FL0_STOP Position */
+ #define MXC_F_I2C_INT_FL0_STOP                         ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */
+ #define MXC_V_I2C_INT_FL0_STOP_INACTIVE                ((uint32_t)0x0UL) /**< INT_FL0_STOP_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_STOP_INACTIVE                (MXC_V_I2C_INT_FL0_STOP_INACTIVE << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_STOP_PENDING                 ((uint32_t)0x1UL) /**< INT_FL0_STOP_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_STOP_PENDING                 (MXC_V_I2C_INT_FL0_STOP_PENDING << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_ADDR_ACK_POS                 7 /**< INT_FL0_ADDR_ACK Position */
+ #define MXC_F_I2C_INT_FL0_ADDR_ACK                     ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK Mask */
+ #define MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE            ((uint32_t)0x0UL) /**< INT_FL0_ADDR_ACK_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_ADDR_ACK_INACTIVE            (MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING             ((uint32_t)0x1UL) /**< INT_FL0_ADDR_ACK_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_ADDR_ACK_PENDING             (MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_ARB_ER_POS                   8 /**< INT_FL0_ARB_ER Position */
+ #define MXC_F_I2C_INT_FL0_ARB_ER                       ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */
+ #define MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE              ((uint32_t)0x0UL) /**< INT_FL0_ARB_ER_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_ARB_ER_INACTIVE              (MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_ARB_ER_PENDING               ((uint32_t)0x1UL) /**< INT_FL0_ARB_ER_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_ARB_ER_PENDING               (MXC_V_I2C_INT_FL0_ARB_ER_PENDING << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_TO_ER_POS                    9 /**< INT_FL0_TO_ER Position */
+ #define MXC_F_I2C_INT_FL0_TO_ER                        ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */
+ #define MXC_V_I2C_INT_FL0_TO_ER_INACTIVE               ((uint32_t)0x0UL) /**< INT_FL0_TO_ER_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_TO_ER_INACTIVE               (MXC_V_I2C_INT_FL0_TO_ER_INACTIVE << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_TO_ER_PENDING                ((uint32_t)0x1UL) /**< INT_FL0_TO_ER_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_TO_ER_PENDING                (MXC_V_I2C_INT_FL0_TO_ER_PENDING << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS             10 /**< INT_FL0_ADDR_NACK_ER Position */
+ #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER                 ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**< INT_FL0_ADDR_NACK_ER Mask */
+ #define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE        ((uint32_t)0x0UL) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE        (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING         ((uint32_t)0x1UL) /**< INT_FL0_ADDR_NACK_ER_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_PENDING         (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< INT_FL0_ADDR_NACK_ER_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_DATA_ER_POS                  11 /**< INT_FL0_DATA_ER Position */
+ #define MXC_F_I2C_INT_FL0_DATA_ER                      ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER Mask */
+ #define MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE             ((uint32_t)0x0UL) /**< INT_FL0_DATA_ER_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_DATA_ER_INACTIVE             (MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_DATA_ER_PENDING              ((uint32_t)0x1UL) /**< INT_FL0_DATA_ER_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_DATA_ER_PENDING              (MXC_V_I2C_INT_FL0_DATA_ER_PENDING << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS           12 /**< INT_FL0_DO_NOT_RESP_ER Position */
+ #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER               ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**< INT_FL0_DO_NOT_RESP_ER Mask */
+ #define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE      ((uint32_t)0x0UL) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE      (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING       ((uint32_t)0x1UL) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING       (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_START_ER_POS                 13 /**< INT_FL0_START_ER Position */
+ #define MXC_F_I2C_INT_FL0_START_ER                     ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER Mask */
+ #define MXC_V_I2C_INT_FL0_START_ER_INACTIVE            ((uint32_t)0x0UL) /**< INT_FL0_START_ER_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_START_ER_INACTIVE            (MXC_V_I2C_INT_FL0_START_ER_INACTIVE << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_START_ER_PENDING             ((uint32_t)0x1UL) /**< INT_FL0_START_ER_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_START_ER_PENDING             (MXC_V_I2C_INT_FL0_START_ER_PENDING << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_STOP_ER_POS                  14 /**< INT_FL0_STOP_ER Position */
+ #define MXC_F_I2C_INT_FL0_STOP_ER                      ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER Mask */
+ #define MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE             ((uint32_t)0x0UL) /**< INT_FL0_STOP_ER_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL0_STOP_ER_INACTIVE             (MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL0_STOP_ER_PENDING              ((uint32_t)0x1UL) /**< INT_FL0_STOP_ER_PENDING Value */
+ #define MXC_S_I2C_INT_FL0_STOP_ER_PENDING              (MXC_V_I2C_INT_FL0_STOP_ER_PENDING << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS              15 /**< INT_FL0_TX_LOCK_OUT Position */
+ #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT                  ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**< INT_FL0_TX_LOCK_OUT Mask */
+
+/**@} end of group I2C_INT_FL0_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_INT_EN0 I2C_INT_EN0
+ * @brief    Interrupt Enable Register.
+ * @{
+ */
+ #define MXC_F_I2C_INT_EN0_DONE_POS                     0 /**< INT_EN0_DONE Position */
+ #define MXC_F_I2C_INT_EN0_DONE                         ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */
+ #define MXC_V_I2C_INT_EN0_DONE_DIS                     ((uint32_t)0x0UL) /**< INT_EN0_DONE_DIS Value */
+ #define MXC_S_I2C_INT_EN0_DONE_DIS                     (MXC_V_I2C_INT_EN0_DONE_DIS << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_DONE_EN                      ((uint32_t)0x1UL) /**< INT_EN0_DONE_EN Value */
+ #define MXC_S_I2C_INT_EN0_DONE_EN                      (MXC_V_I2C_INT_EN0_DONE_EN << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_RX_MODE_POS                  1 /**< INT_EN0_RX_MODE Position */
+ #define MXC_F_I2C_INT_EN0_RX_MODE                      ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE Mask */
+ #define MXC_V_I2C_INT_EN0_RX_MODE_DIS                  ((uint32_t)0x0UL) /**< INT_EN0_RX_MODE_DIS Value */
+ #define MXC_S_I2C_INT_EN0_RX_MODE_DIS                  (MXC_V_I2C_INT_EN0_RX_MODE_DIS << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_RX_MODE_EN                   ((uint32_t)0x1UL) /**< INT_EN0_RX_MODE_EN Value */
+ #define MXC_S_I2C_INT_EN0_RX_MODE_EN                   (MXC_V_I2C_INT_EN0_RX_MODE_EN << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS            2 /**< INT_EN0_GEN_CTRL_ADDR Position */
+ #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR                ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) /**< INT_EN0_GEN_CTRL_ADDR Mask */
+ #define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS            ((uint32_t)0x0UL) /**< INT_EN0_GEN_CTRL_ADDR_DIS Value */
+ #define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_DIS            (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN             ((uint32_t)0x1UL) /**< INT_EN0_GEN_CTRL_ADDR_EN Value */
+ #define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_EN             (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS               3 /**< INT_EN0_ADDR_MATCH Position */
+ #define MXC_F_I2C_INT_EN0_ADDR_MATCH                   ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH Mask */
+ #define MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS               ((uint32_t)0x0UL) /**< INT_EN0_ADDR_MATCH_DIS Value */
+ #define MXC_S_I2C_INT_EN0_ADDR_MATCH_DIS               (MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_ADDR_MATCH_EN                ((uint32_t)0x1UL) /**< INT_EN0_ADDR_MATCH_EN Value */
+ #define MXC_S_I2C_INT_EN0_ADDR_MATCH_EN                (MXC_V_I2C_INT_EN0_ADDR_MATCH_EN << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_RX_THRESH_POS                4 /**< INT_EN0_RX_THRESH Position */
+ #define MXC_F_I2C_INT_EN0_RX_THRESH                    ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH Mask */
+ #define MXC_V_I2C_INT_EN0_RX_THRESH_DIS                ((uint32_t)0x0UL) /**< INT_EN0_RX_THRESH_DIS Value */
+ #define MXC_S_I2C_INT_EN0_RX_THRESH_DIS                (MXC_V_I2C_INT_EN0_RX_THRESH_DIS << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_RX_THRESH_EN                 ((uint32_t)0x1UL) /**< INT_EN0_RX_THRESH_EN Value */
+ #define MXC_S_I2C_INT_EN0_RX_THRESH_EN                 (MXC_V_I2C_INT_EN0_RX_THRESH_EN << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_TX_THRESH_POS                5 /**< INT_EN0_TX_THRESH Position */
+ #define MXC_F_I2C_INT_EN0_TX_THRESH                    ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH Mask */
+ #define MXC_V_I2C_INT_EN0_TX_THRESH_DIS                ((uint32_t)0x0UL) /**< INT_EN0_TX_THRESH_DIS Value */
+ #define MXC_S_I2C_INT_EN0_TX_THRESH_DIS                (MXC_V_I2C_INT_EN0_TX_THRESH_DIS << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_TX_THRESH_EN                 ((uint32_t)0x1UL) /**< INT_EN0_TX_THRESH_EN Value */
+ #define MXC_S_I2C_INT_EN0_TX_THRESH_EN                 (MXC_V_I2C_INT_EN0_TX_THRESH_EN << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_STOP_POS                     6 /**< INT_EN0_STOP Position */
+ #define MXC_F_I2C_INT_EN0_STOP                         ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */
+ #define MXC_V_I2C_INT_EN0_STOP_DIS                     ((uint32_t)0x0UL) /**< INT_EN0_STOP_DIS Value */
+ #define MXC_S_I2C_INT_EN0_STOP_DIS                     (MXC_V_I2C_INT_EN0_STOP_DIS << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_STOP_EN                      ((uint32_t)0x1UL) /**< INT_EN0_STOP_EN Value */
+ #define MXC_S_I2C_INT_EN0_STOP_EN                      (MXC_V_I2C_INT_EN0_STOP_EN << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_ADDR_ACK_POS                 7 /**< INT_EN0_ADDR_ACK Position */
+ #define MXC_F_I2C_INT_EN0_ADDR_ACK                     ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK Mask */
+ #define MXC_V_I2C_INT_EN0_ADDR_ACK_DIS                 ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ACK_DIS Value */
+ #define MXC_S_I2C_INT_EN0_ADDR_ACK_DIS                 (MXC_V_I2C_INT_EN0_ADDR_ACK_DIS << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_ADDR_ACK_EN                  ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ACK_EN Value */
+ #define MXC_S_I2C_INT_EN0_ADDR_ACK_EN                  (MXC_V_I2C_INT_EN0_ADDR_ACK_EN << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_ARB_ER_POS                   8 /**< INT_EN0_ARB_ER Position */
+ #define MXC_F_I2C_INT_EN0_ARB_ER                       ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */
+ #define MXC_V_I2C_INT_EN0_ARB_ER_DIS                   ((uint32_t)0x0UL) /**< INT_EN0_ARB_ER_DIS Value */
+ #define MXC_S_I2C_INT_EN0_ARB_ER_DIS                   (MXC_V_I2C_INT_EN0_ARB_ER_DIS << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_ARB_ER_EN                    ((uint32_t)0x1UL) /**< INT_EN0_ARB_ER_EN Value */
+ #define MXC_S_I2C_INT_EN0_ARB_ER_EN                    (MXC_V_I2C_INT_EN0_ARB_ER_EN << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_TO_ER_POS                    9 /**< INT_EN0_TO_ER Position */
+ #define MXC_F_I2C_INT_EN0_TO_ER                        ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */
+ #define MXC_V_I2C_INT_EN0_TO_ER_DIS                    ((uint32_t)0x0UL) /**< INT_EN0_TO_ER_DIS Value */
+ #define MXC_S_I2C_INT_EN0_TO_ER_DIS                    (MXC_V_I2C_INT_EN0_TO_ER_DIS << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_TO_ER_EN                     ((uint32_t)0x1UL) /**< INT_EN0_TO_ER_EN Value */
+ #define MXC_S_I2C_INT_EN0_TO_ER_EN                     (MXC_V_I2C_INT_EN0_TO_ER_EN << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_ADDR_ER_POS                  10 /**< INT_EN0_ADDR_ER Position */
+ #define MXC_F_I2C_INT_EN0_ADDR_ER                      ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) /**< INT_EN0_ADDR_ER Mask */
+ #define MXC_V_I2C_INT_EN0_ADDR_ER_DIS                  ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ER_DIS Value */
+ #define MXC_S_I2C_INT_EN0_ADDR_ER_DIS                  (MXC_V_I2C_INT_EN0_ADDR_ER_DIS << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_ADDR_ER_EN                   ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ER_EN Value */
+ #define MXC_S_I2C_INT_EN0_ADDR_ER_EN                   (MXC_V_I2C_INT_EN0_ADDR_ER_EN << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_DATA_ER_POS                  11 /**< INT_EN0_DATA_ER Position */
+ #define MXC_F_I2C_INT_EN0_DATA_ER                      ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER Mask */
+ #define MXC_V_I2C_INT_EN0_DATA_ER_DIS                  ((uint32_t)0x0UL) /**< INT_EN0_DATA_ER_DIS Value */
+ #define MXC_S_I2C_INT_EN0_DATA_ER_DIS                  (MXC_V_I2C_INT_EN0_DATA_ER_DIS << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_DATA_ER_EN                   ((uint32_t)0x1UL) /**< INT_EN0_DATA_ER_EN Value */
+ #define MXC_S_I2C_INT_EN0_DATA_ER_EN                   (MXC_V_I2C_INT_EN0_DATA_ER_EN << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS           12 /**< INT_EN0_DO_NOT_RESP_ER Position */
+ #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER               ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**< INT_EN0_DO_NOT_RESP_ER Mask */
+ #define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS           ((uint32_t)0x0UL) /**< INT_EN0_DO_NOT_RESP_ER_DIS Value */
+ #define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_DIS           (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< INT_EN0_DO_NOT_RESP_ER_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN            ((uint32_t)0x1UL) /**< INT_EN0_DO_NOT_RESP_ER_EN Value */
+ #define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_EN            (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< INT_EN0_DO_NOT_RESP_ER_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_START_ER_POS                 13 /**< INT_EN0_START_ER Position */
+ #define MXC_F_I2C_INT_EN0_START_ER                     ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER Mask */
+ #define MXC_V_I2C_INT_EN0_START_ER_DIS                 ((uint32_t)0x0UL) /**< INT_EN0_START_ER_DIS Value */
+ #define MXC_S_I2C_INT_EN0_START_ER_DIS                 (MXC_V_I2C_INT_EN0_START_ER_DIS << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_START_ER_EN                  ((uint32_t)0x1UL) /**< INT_EN0_START_ER_EN Value */
+ #define MXC_S_I2C_INT_EN0_START_ER_EN                  (MXC_V_I2C_INT_EN0_START_ER_EN << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_STOP_ER_POS                  14 /**< INT_EN0_STOP_ER Position */
+ #define MXC_F_I2C_INT_EN0_STOP_ER                      ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER Mask */
+ #define MXC_V_I2C_INT_EN0_STOP_ER_DIS                  ((uint32_t)0x0UL) /**< INT_EN0_STOP_ER_DIS Value */
+ #define MXC_S_I2C_INT_EN0_STOP_ER_DIS                  (MXC_V_I2C_INT_EN0_STOP_ER_DIS << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_STOP_ER_EN                   ((uint32_t)0x1UL) /**< INT_EN0_STOP_ER_EN Value */
+ #define MXC_S_I2C_INT_EN0_STOP_ER_EN                   (MXC_V_I2C_INT_EN0_STOP_ER_EN << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_EN Setting */
+
+ #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS              15 /**< INT_EN0_TX_LOCK_OUT Position */
+ #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT                  ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**< INT_EN0_TX_LOCK_OUT Mask */
+ #define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS              ((uint32_t)0x0UL) /**< INT_EN0_TX_LOCK_OUT_DIS Value */
+ #define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_DIS              (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_DIS Setting */
+ #define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN               ((uint32_t)0x1UL) /**< INT_EN0_TX_LOCK_OUT_EN Value */
+ #define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_EN               (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_EN Setting */
+
+/**@} end of group I2C_INT_EN0_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_INT_FL1 I2C_INT_FL1
+ * @brief    Interrupt Status Register 1.
+ * @{
+ */
+ #define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS              0 /**< INT_FL1_RX_OVERFLOW Position */
+ #define MXC_F_I2C_INT_FL1_RX_OVERFLOW                  ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**< INT_FL1_RX_OVERFLOW Mask */
+ #define MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE         ((uint32_t)0x0UL) /**< INT_FL1_RX_OVERFLOW_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL1_RX_OVERFLOW_INACTIVE         (MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< INT_FL1_RX_OVERFLOW_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING          ((uint32_t)0x1UL) /**< INT_FL1_RX_OVERFLOW_PENDING Value */
+ #define MXC_S_I2C_INT_FL1_RX_OVERFLOW_PENDING          (MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< INT_FL1_RX_OVERFLOW_PENDING Setting */
+
+ #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS             1 /**< INT_FL1_TX_UNDERFLOW Position */
+ #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW                 ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**< INT_FL1_TX_UNDERFLOW Mask */
+ #define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE        ((uint32_t)0x0UL) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Value */
+ #define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE        (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Setting */
+ #define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING         ((uint32_t)0x1UL) /**< INT_FL1_TX_UNDERFLOW_PENDING Value */
+ #define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_PENDING         (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< INT_FL1_TX_UNDERFLOW_PENDING Setting */
+
+/**@} end of group I2C_INT_FL1_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_INT_EN1 I2C_INT_EN1
+ * @brief    Interrupt Staus Register 1.
+ * @{
+ */
+ #define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS              0 /**< INT_EN1_RX_OVERFLOW Position */
+ #define MXC_F_I2C_INT_EN1_RX_OVERFLOW                  ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**< INT_EN1_RX_OVERFLOW Mask */
+ #define MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS              ((uint32_t)0x0UL) /**< INT_EN1_RX_OVERFLOW_DIS Value */
+ #define MXC_S_I2C_INT_EN1_RX_OVERFLOW_DIS              (MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_DIS Setting */
+ #define MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN               ((uint32_t)0x1UL) /**< INT_EN1_RX_OVERFLOW_EN Value */
+ #define MXC_S_I2C_INT_EN1_RX_OVERFLOW_EN               (MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_EN Setting */
+
+ #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS             1 /**< INT_EN1_TX_UNDERFLOW Position */
+ #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW                 ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**< INT_EN1_TX_UNDERFLOW Mask */
+ #define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS             ((uint32_t)0x0UL) /**< INT_EN1_TX_UNDERFLOW_DIS Value */
+ #define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_DIS             (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_DIS Setting */
+ #define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN              ((uint32_t)0x1UL) /**< INT_EN1_TX_UNDERFLOW_EN Value */
+ #define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_EN              (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_EN Setting */
+
+/**@} end of group I2C_INT_EN1_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_FIFO_LEN I2C_FIFO_LEN
+ * @brief    FIFO Configuration Register.
+ * @{
+ */
+ #define MXC_F_I2C_FIFO_LEN_RX_LEN_POS                  0 /**< FIFO_LEN_RX_LEN Position */
+ #define MXC_F_I2C_FIFO_LEN_RX_LEN                      ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN Mask */
+
+ #define MXC_F_I2C_FIFO_LEN_TX_LEN_POS                  8 /**< FIFO_LEN_TX_LEN Position */
+ #define MXC_F_I2C_FIFO_LEN_TX_LEN                      ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN Mask */
+
+/**@} end of group I2C_FIFO_LEN_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_RX_CTRL0 I2C_RX_CTRL0
+ * @brief    Receive Control Register 0.
+ * @{
+ */
+ #define MXC_F_I2C_RX_CTRL0_DNR_POS                     0 /**< RX_CTRL0_DNR Position */
+ #define MXC_F_I2C_RX_CTRL0_DNR                         ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */
+ #define MXC_V_I2C_RX_CTRL0_DNR_RESPOND                 ((uint32_t)0x0UL) /**< RX_CTRL0_DNR_RESPOND Value */
+ #define MXC_S_I2C_RX_CTRL0_DNR_RESPOND                 (MXC_V_I2C_RX_CTRL0_DNR_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_RESPOND Setting */
+ #define MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY ((uint32_t)0x1UL) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Value */
+ #define MXC_S_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY (MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Setting */
+
+ #define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS                7 /**< RX_CTRL0_RX_FLUSH Position */
+ #define MXC_F_I2C_RX_CTRL0_RX_FLUSH                    ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH Mask */
+ #define MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED        ((uint32_t)0x0UL) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Value */
+ #define MXC_S_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED        (MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Setting */
+ #define MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH              ((uint32_t)0x1UL) /**< RX_CTRL0_RX_FLUSH_FLUSH Value */
+ #define MXC_S_I2C_RX_CTRL0_RX_FLUSH_FLUSH              (MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_FLUSH Setting */
+
+ #define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS               8 /**< RX_CTRL0_RX_THRESH Position */
+ #define MXC_F_I2C_RX_CTRL0_RX_THRESH                   ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH Mask */
+
+/**@} end of group I2C_RX_CTRL0_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_RX_CTRL1 I2C_RX_CTRL1
+ * @brief    Receive Control Register 1.
+ * @{
+ */
+ #define MXC_F_I2C_RX_CTRL1_RX_CNT_POS                  0 /**< RX_CTRL1_RX_CNT Position */
+ #define MXC_F_I2C_RX_CTRL1_RX_CNT                      ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT Mask */
+
+ #define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS                 8 /**< RX_CTRL1_RX_FIFO Position */
+ #define MXC_F_I2C_RX_CTRL1_RX_FIFO                     ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO Mask */
+
+/**@} end of group I2C_RX_CTRL1_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_TX_CTRL0 I2C_TX_CTRL0
+ * @brief    Transmit Control Register 0.
+ * @{
+ */
+ #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS              0 /**< TX_CTRL0_TX_PRELOAD Position */
+ #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD                  ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**< TX_CTRL0_TX_PRELOAD Mask */
+
+ #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS           1 /**< TX_CTRL0_TX_READY_MODE Position */
+ #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE               ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**< TX_CTRL0_TX_READY_MODE Mask */
+ #define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN            ((uint32_t)0x0UL) /**< TX_CTRL0_TX_READY_MODE_EN Value */
+ #define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_EN            (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< TX_CTRL0_TX_READY_MODE_EN Setting */
+ #define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS           ((uint32_t)0x1UL) /**< TX_CTRL0_TX_READY_MODE_DIS Value */
+ #define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_DIS           (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< TX_CTRL0_TX_READY_MODE_DIS Setting */
+
+ #define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS                7 /**< TX_CTRL0_TX_FLUSH Position */
+ #define MXC_F_I2C_TX_CTRL0_TX_FLUSH                    ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH Mask */
+ #define MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED        ((uint32_t)0x0UL) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Value */
+ #define MXC_S_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED        (MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Setting */
+ #define MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH              ((uint32_t)0x1UL) /**< TX_CTRL0_TX_FLUSH_FLUSH Value */
+ #define MXC_S_I2C_TX_CTRL0_TX_FLUSH_FLUSH              (MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_FLUSH Setting */
+
+ #define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS               8 /**< TX_CTRL0_TX_THRESH Position */
+ #define MXC_F_I2C_TX_CTRL0_TX_THRESH                   ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH Mask */
+
+/**@} end of group I2C_TX_CTRL0_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_TX_CTRL1 I2C_TX_CTRL1
+ * @brief    Transmit Control Register 1.
+ * @{
+ */
+ #define MXC_F_I2C_TX_CTRL1_TX_READY_POS                0 /**< TX_CTRL1_TX_READY Position */
+ #define MXC_F_I2C_TX_CTRL1_TX_READY                    ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY Mask */
+
+ #define MXC_F_I2C_TX_CTRL1_TX_LAST_POS                 1 /**< TX_CTRL1_TX_LAST Position */
+ #define MXC_F_I2C_TX_CTRL1_TX_LAST                     ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) /**< TX_CTRL1_TX_LAST Mask */
+ #define MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW        ((uint32_t)0x0UL) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Value */
+ #define MXC_S_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW        (MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Setting */
+ #define MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION     ((uint32_t)0x1UL) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Value */
+ #define MXC_S_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION     (MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Setting */
+
+ #define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS                 8 /**< TX_CTRL1_TX_FIFO Position */
+ #define MXC_F_I2C_TX_CTRL1_TX_FIFO                     ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) /**< TX_CTRL1_TX_FIFO Mask */
+
+/**@} end of group I2C_TX_CTRL1_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_FIFO I2C_FIFO
+ * @brief    Data Register.
+ * @{
+ */
+ #define MXC_F_I2C_FIFO_DATA_POS                        0 /**< FIFO_DATA Position */
+ #define MXC_F_I2C_FIFO_DATA                            ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
+
+/**@} end of group I2C_FIFO_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_MASTER_CTRL I2C_MASTER_CTRL
+ * @brief    Master Control Register.
+ * @{
+ */
+ #define MXC_F_I2C_MASTER_CTRL_START_POS                0 /**< MASTER_CTRL_START Position */
+ #define MXC_F_I2C_MASTER_CTRL_START                    ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START Mask */
+
+ #define MXC_F_I2C_MASTER_CTRL_RESTART_POS              1 /**< MASTER_CTRL_RESTART Position */
+ #define MXC_F_I2C_MASTER_CTRL_RESTART                  ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**< MASTER_CTRL_RESTART Mask */
+
+ #define MXC_F_I2C_MASTER_CTRL_STOP_POS                 2 /**< MASTER_CTRL_STOP Position */
+ #define MXC_F_I2C_MASTER_CTRL_STOP                     ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP Mask */
+
+ #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS           7 /**< MASTER_CTRL_SL_EX_ADDR Position */
+ #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR               ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**< MASTER_CTRL_SL_EX_ADDR Mask */
+ #define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS ((uint32_t)0x0UL) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Value */
+ #define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Setting */
+ #define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS ((uint32_t)0x1UL) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Value */
+ #define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Setting */
+
+ #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS          8 /**< MASTER_CTRL_MASTER_CODE Position */
+ #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE              ((uint32_t)(0x7UL << MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) /**< MASTER_CTRL_MASTER_CODE Mask */
+
+ #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS         11 /**< MASTER_CTRL_SCL_SPEED_UP Position */
+ #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP             ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) /**< MASTER_CTRL_SCL_SPEED_UP Mask */
+ #define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN          ((uint32_t)0x0UL) /**< MASTER_CTRL_SCL_SPEED_UP_EN Value */
+ #define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_EN          (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< MASTER_CTRL_SCL_SPEED_UP_EN Setting */
+ #define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS         ((uint32_t)0x1UL) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Value */
+ #define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS         (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Setting */
+
+/**@} end of group I2C_MASTER_CTRL_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_CLK_LO I2C_CLK_LO
+ * @brief    Clock Low Register.
+ * @{
+ */
+ #define MXC_F_I2C_CLK_LO_CLK_LO_POS                    0 /**< CLK_LO_CLK_LO Position */
+ #define MXC_F_I2C_CLK_LO_CLK_LO                        ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_CLK_LO_POS)) /**< CLK_LO_CLK_LO Mask */
+
+/**@} end of group I2C_CLK_LO_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_CLK_HI I2C_CLK_HI
+ * @brief    Clock high Register.
+ * @{
+ */
+ #define MXC_F_I2C_CLK_HI_CKH_POS                       0 /**< CLK_HI_CKH Position */
+ #define MXC_F_I2C_CLK_HI_CKH                           ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_CKH_POS)) /**< CLK_HI_CKH Mask */
+
+/**@} end of group I2C_CLK_HI_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_HS_CLK I2C_HS_CLK
+ * @brief    HS-Mode Clock Control Register
+ * @{
+ */
+ #define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS                 0 /**< HS_CLK_HS_CLK_LO Position */
+ #define MXC_F_I2C_HS_CLK_HS_CLK_LO                     ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */
+
+ #define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS                 8 /**< HS_CLK_HS_CLK_HI Position */
+ #define MXC_F_I2C_HS_CLK_HS_CLK_HI                     ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */
+
+/**@} end of group I2C_HS_CLK_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_TIMEOUT I2C_TIMEOUT
+ * @brief    Timeout Register
+ * @{
+ */
+ #define MXC_F_I2C_TIMEOUT_TO_POS                       0 /**< TIMEOUT_TO Position */
+ #define MXC_F_I2C_TIMEOUT_TO                           ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */
+
+/**@} end of group I2C_TIMEOUT_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_SLAVE_ADDR I2C_SLAVE_ADDR
+ * @brief    Slave Address Register.
+ * @{
+ */
+ #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS            0 /**< SLAVE_ADDR_SLAVE_ADDR Position */
+ #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR                ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**< SLAVE_ADDR_SLAVE_ADDR Mask */
+
+ #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS        10 /**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */
+ #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS            ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_DIS Mask */
+
+ #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS        11 /**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */
+ #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX            ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_IDX Mask */
+
+ #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS               15 /**< SLAVE_ADDR_EX_ADDR Position */
+ #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR                   ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR Mask */
+ #define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS    ((uint32_t)0x0UL) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Value */
+ #define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS    (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Setting */
+ #define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS   ((uint32_t)0x1UL) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Value */
+ #define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS   (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Setting */
+
+/**@} end of group I2C_SLAVE_ADDR_Register */
+
+/**
+ * @ingroup  i2c_registers
+ * @defgroup I2C_DMA I2C_DMA
+ * @brief    DMA Register.
+ * @{
+ */
+ #define MXC_F_I2C_DMA_TX_EN_POS                        0 /**< DMA_TX_EN Position */
+ #define MXC_F_I2C_DMA_TX_EN                            ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
+ #define MXC_V_I2C_DMA_TX_EN_DIS                        ((uint32_t)0x0UL) /**< DMA_TX_EN_DIS Value */
+ #define MXC_S_I2C_DMA_TX_EN_DIS                        (MXC_V_I2C_DMA_TX_EN_DIS << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_DIS Setting */
+ #define MXC_V_I2C_DMA_TX_EN_EN                         ((uint32_t)0x1UL) /**< DMA_TX_EN_EN Value */
+ #define MXC_S_I2C_DMA_TX_EN_EN                         (MXC_V_I2C_DMA_TX_EN_EN << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_EN Setting */
+
+ #define MXC_F_I2C_DMA_RX_EN_POS                        1 /**< DMA_RX_EN Position */
+ #define MXC_F_I2C_DMA_RX_EN                            ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
+ #define MXC_V_I2C_DMA_RX_EN_DIS                        ((uint32_t)0x0UL) /**< DMA_RX_EN_DIS Value */
+ #define MXC_S_I2C_DMA_RX_EN_DIS                        (MXC_V_I2C_DMA_RX_EN_DIS << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_DIS Setting */
+ #define MXC_V_I2C_DMA_RX_EN_EN                         ((uint32_t)0x1UL) /**< DMA_RX_EN_EN Value */
+ #define MXC_S_I2C_DMA_RX_EN_EN                         (MXC_V_I2C_DMA_RX_EN_EN << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_EN Setting */
+
+/**@} end of group I2C_DMA_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _I2C_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h

@@ -0,0 +1,167 @@
+/**
+ * @file    icc_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _ICC_REGS_H_
+#define _ICC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     icc
+ * @defgroup    icc_registers ICC_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
+ * @details Instruction Cache Controller Registers
+ */
+
+/**
+ * @ingroup icc_registers
+ * Structure type to access the ICC Registers.
+ */
+typedef struct {
+    __I  uint32_t cache_id;             /**< <tt>\b 0x0000:</tt> ICC CACHE_ID Register */
+    __I  uint32_t memcfg;               /**< <tt>\b 0x0004:</tt> ICC MEMCFG Register */
+    __R  uint32_t rsv_0x8_0xff[62];
+    __IO uint32_t cache_ctrl;           /**< <tt>\b 0x0100:</tt> ICC CACHE_CTRL Register */
+    __R  uint32_t rsv_0x104_0x6ff[383];
+    __IO uint32_t invalidate;           /**< <tt>\b 0x0700:</tt> ICC INVALIDATE Register */
+} mxc_icc_regs_t;
+
+/* Register offsets for module ICC */
+/**
+ * @ingroup    icc_registers
+ * @defgroup   ICC_Register_Offsets Register Offsets
+ * @brief      ICC Peripheral Register Offsets from the ICC Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_ICC_CACHE_ID                 ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_ICC_MEMCFG                   ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_ICC_CACHE_CTRL               ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> 0x0100</tt> */ 
+ #define MXC_R_ICC_INVALIDATE               ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> 0x0700</tt> */ 
+/**@} end of group icc_registers */
+
+/**
+ * @ingroup  icc_registers
+ * @defgroup ICC_CACHE_ID ICC_CACHE_ID
+ * @brief    Cache ID Register.
+ * @{
+ */
+ #define MXC_F_ICC_CACHE_ID_RELNUM_POS                  0 /**< CACHE_ID_RELNUM Position */
+ #define MXC_F_ICC_CACHE_ID_RELNUM                      ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */
+
+ #define MXC_F_ICC_CACHE_ID_PARTNUM_POS                 6 /**< CACHE_ID_PARTNUM Position */
+ #define MXC_F_ICC_CACHE_ID_PARTNUM                     ((uint32_t)(0xFUL << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */
+
+ #define MXC_F_ICC_CACHE_ID_CCHID_POS                   10 /**< CACHE_ID_CCHID Position */
+ #define MXC_F_ICC_CACHE_ID_CCHID                       ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
+
+/**@} end of group ICC_CACHE_ID_Register */
+
+/**
+ * @ingroup  icc_registers
+ * @defgroup ICC_MEMCFG ICC_MEMCFG
+ * @brief    Memory Configuration Register.
+ * @{
+ */
+ #define MXC_F_ICC_MEMCFG_CCHSZ_POS                     0 /**< MEMCFG_CCHSZ Position */
+ #define MXC_F_ICC_MEMCFG_CCHSZ                         ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
+
+ #define MXC_F_ICC_MEMCFG_MEMSZ_POS                     16 /**< MEMCFG_MEMSZ Position */
+ #define MXC_F_ICC_MEMCFG_MEMSZ                         ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
+
+/**@} end of group ICC_MEMCFG_Register */
+
+/**
+ * @ingroup  icc_registers
+ * @defgroup ICC_CACHE_CTRL ICC_CACHE_CTRL
+ * @brief    Cache Control and Status Register.
+ * @{
+ */
+ #define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS              0 /**< CACHE_CTRL_CACHE_EN Position */
+ #define MXC_F_ICC_CACHE_CTRL_CACHE_EN                  ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */
+ #define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS              ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */
+ #define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS              (MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS Setting */
+ #define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN               ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */
+ #define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN               (MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN Setting */
+
+ #define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS             16 /**< CACHE_CTRL_CACHE_RDY Position */
+ #define MXC_F_ICC_CACHE_CTRL_CACHE_RDY                 ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */
+ #define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY        ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */
+ #define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY        (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Setting */
+ #define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY           ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */
+ #define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY           (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< CACHE_CTRL_CACHE_RDY_READY Setting */
+
+/**@} end of group ICC_CACHE_CTRL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ICC_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/max32660.h

@@ -0,0 +1,403 @@
+/**
+ * @file    max32660.h
+ * @brief   Device-specific perhiperal header file
+ */
+
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+#ifndef _MAX32660_REGS_H_
+#define _MAX32660_REGS_H_
+
+#ifndef TARGET_NUM
+#define TARGET_NUM  32660
+#endif
+
+#include <stdint.h>
+
+#ifndef  FALSE
+#define  FALSE      (0)
+#endif
+
+#ifndef  TRUE
+#define  TRUE       (1)
+#endif
+
+#if !defined (__GNUC__)
+#define CMSIS_VECTAB_VIRTUAL
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
+#endif /* !__GNUC__ */
+
+/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
+#if defined ( __GNUC__ ) /* GCC */
+#define __weak __attribute__((weak))
+
+#elif defined ( __CC_ARM) /* Keil */
+
+#define inline __inline
+#pragma anon_unions
+
+#endif
+
+typedef enum {
+    NonMaskableInt_IRQn    = -14,
+    HardFault_IRQn         = -13,
+    MemoryManagement_IRQn  = -12,
+    BusFault_IRQn          = -11,
+    UsageFault_IRQn        = -10,
+    SVCall_IRQn            = -5,
+    DebugMonitor_IRQn      = -4,
+    PendSV_IRQn            = -2,
+    SysTick_IRQn           = -1,
+
+    /* Device-specific interrupt sources (external to ARM core)                 */
+    /*                      table entry number                                  */
+    /*                      ||||                                                */
+    /*                      ||||  table offset address                          */
+    /*                      vvvv  vvvvvv                                        */
+
+    PF_IRQn = 0,         /* 0x10  0x0040  16: Power Fail */
+    WDT0_IRQn,           /* 0x11  0x0044  17: Watchdog 0 */
+    RSV00_IRQn,          /* 0x12  0x0048  18: RSV00 */
+    RTC_IRQn,            /* 0x13  0x004C  19: RTC */
+    RSV1_IRQn,           /* 0x14  0x0050  20: RSV1 */
+    TMR0_IRQn,           /* 0x15  0x0054  21: Timer 0 */
+    TMR1_IRQn,           /* 0x16  0x0058  22: Timer 1 */
+    TMR2_IRQn,           /* 0x17  0x005C  23: Timer 2 */
+    RSV02_IRQn,          /* 0x18  0x0060  24: RSV02 */
+    RSV03_IRQn,          /* 0x19  0x0064  25: RSV03 */
+    RSV04_IRQn,          /* 0x1A  0x0068  26: RSV04 */
+    RSV05_IRQn,          /* 0x1B  0x006C  27: RSV05 */
+    RSV06_IRQn,          /* 0x1C  0x0070  28: RSV06 */
+    I2C0_IRQn,           /* 0x1D  0x0074  29: I2C0 */
+    UART0_IRQn,          /* 0x1E  0x0078  30: UART 0 */
+    UART1_IRQn,          /* 0x1F  0x007C  31: UART 1 */
+    SPI17Y_IRQn,         /* 0x20  0x0080  32: SPI17Y */
+    SPIMSS_IRQn,         /* 0x21  0x0084  33: SPIMSS */
+    RSV07_IRQn,          /* 0x22  0x0088  34: RSV07 */
+    RSV08_IRQn,          /* 0x23  0x008C  35: RSV08 */
+    RSV09_IRQn,          /* 0x24  0x0090  36: RSV09 */
+    RSV10_IRQn,          /* 0x25  0x0094  37: RSV10 */
+    RSV11_IRQn,          /* 0x26  0x0098  38: RSV11 */
+    FLC_IRQn,            /* 0x27  0x009C  39: FLC */
+    GPIO0_IRQn,          /* 0x28  0x00A0  40: GPIO0 */
+    RSV12_IRQn,          /* 0x29  0x00A4  41: RSV12 */
+    RSV13_IRQn,          /* 0x2A  0x00A8  42: RSV13 */
+    RSV14_IRQn,          /* 0x2B  0x00AC  43: RSV14 */
+    DMA0_IRQn,           /* 0x2C  0x00B0  44: DMA0 */
+    DMA1_IRQn,           /* 0x2D  0x00B4  45: DMA1 */
+    DMA2_IRQn,           /* 0x2E  0x00B8  46: DMA2 */
+    DMA3_IRQn,           /* 0x2F  0x00BC  47: DMA3 */
+    RSV15_IRQn,          /* 0x30  0x00C0  48: RSV15 */
+    RSV16_IRQn,          /* 0x31  0x00C4  49: RSV16 */
+    RSV17_IRQn,          /* 0x32  0x00C8  50: RSV17 */
+    RSV18_IRQn,          /* 0x33  0x00CC  51: RSV18 */
+    I2C1_IRQn,           /* 0x34  0x00D0  52: I2C1 */
+    RSV19_IRQn,          /* 0x35  0x00D4  53: RSV19 */
+    RSV20_IRQn,          /* 0x36  0x00D8  54: RSV20 */
+    RSV21_IRQn,          /* 0x37  0x00DC  55: RSV21 */
+    RSV22_IRQn,          /* 0x38  0x00E0  56: RSV22 */
+    RSV23_IRQn,          /* 0x39  0x00E4  57: RSV23 */
+    RSV24_IRQn,          /* 0x3A  0x00E8  58: RSV24 */
+    RSV25_IRQn,          /* 0x3B  0x00EC  59: RSV25 */
+    RSV26_IRQn,          /* 0x3C  0x00F0  60: RSV26 */
+    RSV27_IRQn,          /* 0x3D  0x00F4  61: RSV27 */
+    RSV28_IRQn,          /* 0x3E  0x00F8  62: RSV28 */
+    RSV29_IRQn,          /* 0x3F  0x00FC  63: RSV29 */
+    RSV30_IRQn,          /* 0x40  0x0100  64: RSV30 */
+    RSV31_IRQn,          /* 0x41  0x0104  65: RSV31 */
+    RSV32_IRQn,          /* 0x42  0x0108  66: RSV32 */
+    RSV33_IRQn,          /* 0x43  0x010C  67: RSV33 */
+    RSV34_IRQn,          /* 0x44  0x0110  68: RSV34 */
+    RSV35_IRQn,          /* 0x45  0x0114  69: RSV35 */
+    GPIOWAKE_IRQn,       /* 0x46  0x0118  70: GPIO Wakeup */
+    MXC_IRQ_EXT_COUNT,
+} IRQn_Type;
+
+#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* ----------------------  Configuration of the Cortex-M Processor and Core Peripherals  ---------------------- */
+#define __CM4_REV                       0x0100          /*!< Cortex-M4 Core Revision                                */
+#define __MPU_PRESENT                   1               /*!< MPU present or not                                     */
+#define __NVIC_PRIO_BITS                3               /*!< Number of Bits used for Priority Levels                */
+#define __Vendor_SysTickConfig          0               /*!< Set to 1 if different SysTick Config is used           */
+#define __FPU_PRESENT                   1               /*!< FPU present or not                                     */
+
+#include <core_cm4.h>                                   /*!< Cortex-M4 processor and core peripherals               */
+#include "system_max32660.h"                            /*!< System Header                                          */
+
+
+/* ================================================================================ */
+/* ==================       Device Specific Memory Section       ================== */
+/* ================================================================================ */
+
+#define MXC_FLASH_MEM_BASE              0x00000000UL
+#define MXC_FLASH_PAGE_SIZE             0x00002000UL
+#define MXC_FLASH_MEM_SIZE              0x00040000UL
+#define MXC_INFO_MEM_BASE               0x00040000UL
+#define MXC_INFO_MEM_SIZE               0x00001000UL
+#define MXC_SRAM_MEM_BASE               0x20000000UL
+#define MXC_SRAM_MEM_SIZE               0x00018000UL
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+/*
+   Base addresses and configuration settings for all MAX32660 peripheral modules.
+*/
+
+/******************************************************************************/
+/*                                                             Global control */
+#define MXC_BASE_GCR                    ((uint32_t)0x40000000UL)
+#define MXC_GCR                         ((mxc_gcr_regs_t*)MXC_BASE_GCR)
+
+/******************************************************************************/
+/*                                            Non-battery backed SI Registers */
+#define MXC_BASE_SIR                    ((uint32_t)0x40000400UL)
+#define MXC_SIR                         ((mxc_sir_regs_t*)MXC_BASE_SIR)
+
+/******************************************************************************/
+/*                                                                   Watchdog */
+#define MXC_BASE_WDT0                   ((uint32_t)0x40003000UL)
+#define MXC_WDT0                        ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
+
+/******************************************************************************/
+/*                                                            Real Time Clock */
+#define MXC_BASE_RTC                    ((uint32_t)0x40006000UL)
+#define MXC_RTC                         ((mxc_rtc_regs_t*)MXC_BASE_RTC)
+
+/******************************************************************************/
+/*                                                            Power Sequencer */
+#define MXC_BASE_PWRSEQ                 ((uint32_t)0x40006800UL)
+#define MXC_PWRSEQ                      ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
+
+
+/******************************************************************************/
+/*                                                                       GPIO */
+#define MXC_CFG_GPIO_INSTANCES          (1)
+#define MXC_CFG_GPIO_PINS_PORT          (14)
+
+#define MXC_BASE_GPIO0                  ((uint32_t)0x40008000UL)
+#define MXC_GPIO0                       ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
+
+#define MXC_GPIO_GET_IDX(p)             ((p) == MXC_GPIO0 ? 0 :-1)
+
+#define MXC_GPIO_GET_GPIO(i)            ((i) == 0 ? MXC_GPIO0 : 0)
+
+#define MXC_GPIO_GET_IRQ(i)             ((i) == 0 ? GPIO0_IRQn : 0)
+
+/******************************************************************************/
+/*                                                                      Timer */
+#define MXC_CFG_TMR_INSTANCES           (3)
+
+#define MXC_BASE_TMR0                   ((uint32_t)0x40010000UL)
+#define MXC_TMR0                        ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
+#define MXC_BASE_TMR1                   ((uint32_t)0x40011000UL)
+#define MXC_TMR1                        ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
+#define MXC_BASE_TMR2                   ((uint32_t)0x40012000UL)
+#define MXC_TMR2                        ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
+
+#define MXC_TMR_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? TMR0_IRQn :     \
+                                            (i) == 1 ? TMR1_IRQn :             \
+                                            (i) == 2 ? TMR2_IRQn : 0)
+
+#define MXC_TMR_GET_BASE(i)             ((i) == 0 ? MXC_BASE_TMR0 :            \
+                                            (i) == 1 ? MXC_BASE_TMR1 :         \
+                                            (i) == 2 ? MXC_BASE_TMR2 : 0)
+
+#define MXC_TMR_GET_TMR(i)              ((i) == 0 ? MXC_TMR0 :                 \
+                                            (i) == 1 ? MXC_TMR1 :              \
+                                            (i) == 2 ? MXC_TMR2 : 0)
+
+#define MXC_TMR_GET_IDX(p)              ((p) == MXC_TMR0 ? 0 :                 \
+                                            (p) == MXC_TMR1 ? 1 :              \
+                                            (p) == MXC_TMR2 ? 2 : -1)
+
+/******************************************************************************/
+/*                                                                    SPIMSS  */
+
+#define MXC_SPIMSS_INSTANCES            (1)
+#define MXC_SPIMSS_FIFO_DEPTH           (8)
+
+#define MXC_BASE_SPIMSS                ((uint32_t)0x40019000UL)
+#define MXC_SPIMSS                     ((mxc_spimss_regs_t*)MXC_BASE_SPIMSS)
+
+#define MXC_SPIMSS_GET_IDX(p)            ((p) == MXC_SPIMSS ? 0 :  -1)
+#define MXC_SPIMSS_GET_SPI(i)            ((i) == 0 ? MXC_SPIMSS :   0)
+
+/******************************************************************************/
+/*                                                                        I2C */
+#define MXC_I2C_INSTANCES               (2)
+#define MXC_I2C_FIFO_DEPTH              (8)
+
+#define MXC_BASE_I2C0                   ((uint32_t)0x4001D000UL)
+#define MXC_I2C0                        ((mxc_i2c_regs_t*)MXC_BASE_I2C0)
+#define MXC_BASE_I2C1                   ((uint32_t)0x4001E000UL)
+#define MXC_I2C1                        ((mxc_i2c_regs_t*)MXC_BASE_I2C1)
+
+#define MXC_I2C_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? I2C0_IRQn :     \
+                                            (i) == 1 ? I2C1_IRQn : 0)
+
+#define MXC_I2C_GET_BASE(i)             ((i) == 0 ? MXC_BASE_I2C0 :            \
+                                            (i) == 1 ? MXC_BASE_I2C1 : 0)
+
+#define MXC_I2C_GET_I2C(i)              ((i) == 0 ? MXC_I2C0 :                 \
+                                            (i) == 1 ? MXC_I2C1 : 0)
+
+#define MXC_I2C_GET_IDX(p)              ((p) == MXC_I2C0 ? 0 :                 \
+                                            (p) == MXC_I2C1 ? 1 : -1)
+
+/******************************************************************************/
+/*                                                                        DMA */
+#define MXC_DMA_CHANNELS                (4)
+
+#define MXC_BASE_DMA                    ((uint32_t)0x40028000UL)
+#define MXC_DMA                         ((mxc_dma_regs_t*)MXC_BASE_DMA)
+
+/******************************************************************************/
+/*                                                                        FLC */
+#define MXC_BASE_FLC                    ((uint32_t)0x40029000UL)
+#define MXC_FLC                         ((mxc_flc_regs_t*)MXC_BASE_FLC)
+
+/******************************************************************************/
+/*                                                          Instruction Cache */
+#define MXC_BASE_ICC                    ((uint32_t)0x4002A000UL)
+#define MXC_ICC                         ((mxc_icc_regs_t*)MXC_BASE_ICC)
+
+/******************************************************************************/
+/*                                               UART / Serial Port Interface */
+
+#define MXC_UART_INSTANCES              (2)
+#define MXC_UART_FIFO_DEPTH             (8)
+
+#define MXC_BASE_UART0                  ((uint32_t)0x40042000UL)
+#define MXC_UART0                       ((mxc_uart_regs_t*)MXC_BASE_UART0)
+#define MXC_BASE_UART1                  ((uint32_t)0x40043000UL)
+#define MXC_UART1                       ((mxc_uart_regs_t*)MXC_BASE_UART1)
+
+#define MXC_UART_GET_IRQ(i)             (IRQn_Type)((i) == 0 ? UART0_IRQn :    \
+                                            (i) == 1 ? UART1_IRQn : 0)
+
+#define MXC_UART_GET_BASE(i)            ((i) == 0 ? MXC_BASE_UART0 :           \
+                                            (i) == 1 ? MXC_BASE_UART1 : 0)
+
+#define MXC_UART_GET_UART(i)            ((i) == 0 ? MXC_UART0 :                \
+                                            (i) == 1 ? MXC_UART1 : 0)
+
+#define MXC_UART_GET_IDX(p)             ((p) == MXC_UART0 ? 0 :                \
+                                            (p) == MXC_UART1 ? 1 : -1)
+
+/******************************************************************************/
+/*                                                                        SPI */
+
+
+#define MXC_SPI17Y_INSTANCES               (4)
+#define MXC_SPI17Y_SS_INSTANCES            (1)
+#define MXC_SPI17Y_FIFO_DEPTH              (32)
+
+#define MXC_BASE_SPI17Y                   ((uint32_t)0x40046000UL)
+#define MXC_SPI17Y                        ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y)
+
+#define MXC_SPI17Y_GET_IDX(p)               ((p) == MXC_SPI17Y ? 0 :  -1)
+
+#define MXC_SPI17Y_GET_BASE(i)             ((i) == 0 ? MXC_BASE_SPI17Y :  0)
+
+#define MXC_SPI17Y_GET_SPI17Y(i)             ((i) == 0 ? MXC_SPI17Y :   0)
+
+/******************************************************************************/
+/*                                                               Bit Shifting */
+
+#define MXC_F_BIT_0                     (1 << 0)
+#define MXC_F_BIT_1                     (1 << 1)
+#define MXC_F_BIT_2                     (1 << 2)
+#define MXC_F_BIT_3                     (1 << 3)
+#define MXC_F_BIT_4                     (1 << 4)
+#define MXC_F_BIT_5                     (1 << 5)
+#define MXC_F_BIT_6                     (1 << 6)
+#define MXC_F_BIT_7                     (1 << 7)
+#define MXC_F_BIT_8                     (1 << 8)
+#define MXC_F_BIT_9                     (1 << 9)
+#define MXC_F_BIT_10                    (1 << 10)
+#define MXC_F_BIT_11                    (1 << 11)
+#define MXC_F_BIT_12                    (1 << 12)
+#define MXC_F_BIT_13                    (1 << 13)
+#define MXC_F_BIT_14                    (1 << 14)
+#define MXC_F_BIT_15                    (1 << 15)
+#define MXC_F_BIT_16                    (1 << 16)
+#define MXC_F_BIT_17                    (1 << 17)
+#define MXC_F_BIT_18                    (1 << 18)
+#define MXC_F_BIT_19                    (1 << 19)
+#define MXC_F_BIT_20                    (1 << 20)
+#define MXC_F_BIT_21                    (1 << 21)
+#define MXC_F_BIT_22                    (1 << 22)
+#define MXC_F_BIT_23                    (1 << 23)
+#define MXC_F_BIT_24                    (1 << 24)
+#define MXC_F_BIT_25                    (1 << 25)
+#define MXC_F_BIT_26                    (1 << 26)
+#define MXC_F_BIT_27                    (1 << 27)
+#define MXC_F_BIT_28                    (1 << 28)
+#define MXC_F_BIT_29                    (1 << 29)
+#define MXC_F_BIT_30                    (1 << 30)
+#define MXC_F_BIT_31                    (1 << 31)
+
+/******************************************************************************/
+/*                                                               Bit Banding  */
+
+#define BITBAND(reg, bit)               ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
+                                            (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
+
+#define MXC_CLRBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
+#define MXC_SETBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
+#define MXC_GETBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit))
+
+#define MXC_SETFIELD(reg, mask, value)  (reg = (reg & ~mask) | (value & mask))
+
+/******************************************************************************/
+/*                                                                  SCB CPACR */
+
+/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
+#define SCB_CPACR_CP10_Pos              20                              /*!< SCB CPACR: Coprocessor 10 Position */
+#define SCB_CPACR_CP10_Msk              (0x3UL << SCB_CPACR_CP10_Pos)   /*!< SCB CPACR: Coprocessor 10 Mask */
+#define SCB_CPACR_CP11_Pos              22                              /*!< SCB CPACR: Coprocessor 11 Position */
+#define SCB_CPACR_CP11_Msk              (0x3UL << SCB_CPACR_CP11_Pos)   /*!< SCB CPACR: Coprocessor 11 Mask */
+
+#endif  /* _MAX32660_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/max32660.svd

@@ -0,0 +1,10650 @@
+<?xml version='1.0' encoding='utf-8'?>
+<device xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xsi:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
+ <vendor>Maxim Integrated</vendor>
+ <vendorID>Maxim</vendorID>
+ <name>max32660</name>
+ <series>ARMCM4</series>
+ <version>1.0</version>
+ <description>MAX32660 32-bit ARM Cortex-M4 microcontroller with 96KB of system RAM and 256KB of flash memory.</description>
+ <cpu>
+  <name>CM4</name>
+  <revision>r2p1</revision>
+  <endian>little</endian>
+  <mpuPresent>true</mpuPresent>
+  <fpuPresent>true</fpuPresent>
+  <nvicPrioBits>3</nvicPrioBits>
+  <vendorSystickConfig>false</vendorSystickConfig>
+ </cpu>
+ <addressUnitBits>8</addressUnitBits>
+ <width>32</width>
+ <size>0x20</size>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <peripherals>
+  <peripheral>
+   <name>BBFC</name>
+   <description>Battery-Backed Function Control.</description>
+   <baseAddress>0x40005800</baseAddress>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x400</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <registers>
+    <register>
+     <name>BBFCR0</name>
+     <description>Function Control Register 0.</description>
+     <addressOffset>0x00</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>CKPDRV</name>
+       <description>Hyperbus CK Pad Driver Control.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>4</bitWidth>
+      </field>
+      <field>
+       <name>CKNPDRV</name>
+       <description>Hyperbus CKN Pad Driver Control.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>4</bitWidth>
+      </field>
+      <field>
+       <name>RDSDLLEN</name>
+       <description>Hyperbus RDS DLL Power Up Control.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--BBFC Battery-Backed Function Control.-->
+  <peripheral>
+   <name>BBSIR</name>
+   <description>Battery-Backed Registers.</description>
+   <baseAddress>0x40005400</baseAddress>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x400</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <registers>
+    <register>
+     <name>rsv0</name>
+     <description>RFU</description>
+     <addressOffset>0x00</addressOffset>
+    </register>
+    <register>
+     <name>BB_SIR2</name>
+     <description>System Init. Configuration Register 2.</description>
+     <addressOffset>0x08</addressOffset>
+     <access>read-only</access>
+    </register>
+    <register>
+     <name>BB_SIR3</name>
+     <description>System Init. Configuration Register 3.</description>
+     <addressOffset>0x0C</addressOffset>
+     <access>read-only</access>
+    </register>
+   </registers>
+  </peripheral>
+<!--BBSIR Battery-Backed Registers.-->
+  <peripheral>
+   <name>DMA</name>
+   <description>DMA Controller Fully programmable, chaining capable DMA channels.</description>
+   <baseAddress>0x40028000</baseAddress>
+   <size>32</size>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x1000</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <interrupt>
+    <name>DMA0</name>
+    <value>28</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA1</name>
+    <value>29</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA2</name>
+    <value>30</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA3</name>
+    <value>31</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA4</name>
+    <value>68</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA5</name>
+    <value>69</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA6</name>
+    <value>70</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA7</name>
+    <value>71</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA8</name>
+    <value>72</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA9</name>
+    <value>73</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA10</name>
+    <value>74</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA11</name>
+    <value>75</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA12</name>
+    <value>76</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA13</name>
+    <value>77</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA14</name>
+    <value>78</value>
+   </interrupt>
+   <interrupt>
+    <name>DMA15</name>
+    <value>79</value>
+   </interrupt>
+   <registers>
+    <register>
+     <name>CN</name>
+     <description>DMA Control Register.</description>
+     <addressOffset>0x000</addressOffset>
+     <fields>
+      <field>
+       <name>CH0_IEN</name>
+       <description>Channel 0 Interrupt Enable.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field derivedFrom="CH0_IEN">
+       <name>CH1_IEN</name>
+       <description>Channel 1 Interrupt Enable.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field derivedFrom="CH0_IEN">
+       <name>CH2_IEN</name>
+       <description>Channel 2 Interrupt Enable.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field derivedFrom="CH0_IEN">
+       <name>CH3_IEN</name>
+       <description>Channel 3 Interrupt Enable.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INTR</name>
+     <description>DMA Interrupt Register.</description>
+     <addressOffset>0x004</addressOffset>
+     <access>read-only</access>
+     <fields>
+      <field>
+       <name>CH0_IPEND</name>
+       <description>Channel Interrupt.   To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>ch_ipend_enum</name>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No interrupt is pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field derivedFrom="CH0_IPEND">
+       <name>CH1_IPEND</name>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field derivedFrom="CH0_IPEND">
+       <name>CH2_IPEND</name>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field derivedFrom="CH0_IPEND">
+       <name>CH3_IPEND</name>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <cluster>
+     <dim>4</dim>
+     <dimIncrement>4</dimIncrement>
+     <name>CH[%s]</name>
+     <description>DMA Channel registers.</description>
+     <headerStructName>dma_ch</headerStructName>
+     <addressOffset>0x100</addressOffset>
+     <access>read-write</access>
+     <register>
+      <name>CFG</name>
+      <description>DMA Channel Configuration Register.</description>
+      <addressOffset>0x100</addressOffset>
+      <fields>
+       <field>
+        <name>CHEN</name>
+        <description>Channel Enable.  This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.</description>
+        <bitOffset>0</bitOffset>
+        <bitWidth>1</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>dis</name>
+          <description>Disable.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>en</name>
+          <description>Enable.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>RLDEN</name>
+        <description>Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.</description>
+        <bitOffset>1</bitOffset>
+        <bitWidth>1</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>dis</name>
+          <description>Disable.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>en</name>
+          <description>Enable.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>PRI</name>
+        <description>DMA Priority.</description>
+        <bitOffset>2</bitOffset>
+        <bitWidth>2</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>high</name>
+          <description>Highest Priority.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>medHigh</name>
+          <description>Medium High Priority.</description>
+          <value>1</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>medLow</name>
+          <description>Medium Low Priority.</description>
+          <value>2</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>low</name>
+          <description>Lowest Priority.</description>
+          <value>3</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>REQSEL</name>
+        <description>Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.</description>
+        <bitOffset>4</bitOffset>
+        <bitWidth>6</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>MEMTOMEM</name>
+          <description>Memory To Memory</description>
+          <value>0x00</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>SPI0RX</name>
+          <description>SPI0 RX</description>
+          <value>0x01</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>SPI1RX</name>
+          <description>SPI1 RX</description>
+          <value>0x02</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>UART0RX</name>
+          <description>UART0 RX</description>
+          <value>0x04</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>UART1RX</name>
+          <description>UART1 RX</description>
+          <value>0x05</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>I2C0RX</name>
+          <description>I2C0 RX</description>
+          <value>0x07</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>I2C1RX</name>
+          <description>I2C1 RX</description>
+          <value>0x08</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>SPI0TX</name>
+          <description>SPI0 TX</description>
+          <value>0x21</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>SPI1TX</name>
+          <description>SPI1 TX</description>
+          <value>0x22</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>UART0TX</name>
+          <description>UART0 TX</description>
+          <value>0x24</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>UART1TX</name>
+          <description>UART1 TX</description>
+          <value>0x25</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>I2C0TX</name>
+          <description>I2C0 TX</description>
+          <value>0x27</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>I2C1TX</name>
+          <description>I2C1 TX</description>
+          <value>0x28</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>REQWAIT</name>
+        <description>Request Wait Enable.  When enabled, delay timer start until DMA request transitions from active to inactive.</description>
+        <bitOffset>10</bitOffset>
+        <bitWidth>1</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>dis</name>
+          <description>Disable.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>en</name>
+          <description>Enable.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>TOSEL</name>
+        <description>Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.</description>
+        <bitOffset>11</bitOffset>
+        <bitWidth>3</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>to4</name>
+          <description>Timeout of 3 to 4 prescale clocks.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>to8</name>
+          <description>Timeout of 7 to 8 prescale clocks.</description>
+          <value>1</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>to16</name>
+          <description>Timeout of 15 to 16 prescale clocks.</description>
+          <value>2</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>to32</name>
+          <description>Timeout of 31 to 32 prescale clocks.</description>
+          <value>3</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>to64</name>
+          <description>Timeout of 63 to 64 prescale clocks.</description>
+          <value>4</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>to128</name>
+          <description>Timeout of 127 to 128 prescale clocks.</description>
+          <value>5</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>to256</name>
+          <description>Timeout of 255 to 256 prescale clocks.</description>
+          <value>6</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>to512</name>
+          <description>Timeout of 511 to 512 prescale clocks.</description>
+          <value>7</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>PSSEL</name>
+        <description>Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.</description>
+        <bitOffset>14</bitOffset>
+        <bitWidth>2</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>dis</name>
+          <description>Disable timer.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>div256</name>
+          <description>hclk / 256.</description>
+          <value>1</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>div64k</name>
+          <description>hclk / 64k.</description>
+          <value>2</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>div16M</name>
+          <description>hclk / 16M.</description>
+          <value>3</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>SRCWD</name>
+        <description>Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.</description>
+        <bitOffset>16</bitOffset>
+        <bitWidth>2</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>byte</name>
+          <description>Byte.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>halfWord</name>
+          <description>Halfword.</description>
+          <value>1</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>word</name>
+          <description>Word.</description>
+          <value>2</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>SRCINC</name>
+        <description>Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.</description>
+        <bitOffset>18</bitOffset>
+        <bitWidth>1</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>dis</name>
+          <description>Disable.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>en</name>
+          <description>Enable.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>DSTWD</name>
+        <description>Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).</description>
+        <bitOffset>20</bitOffset>
+        <bitWidth>2</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>byte</name>
+          <description>Byte.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>halfWord</name>
+          <description>Halfword.</description>
+          <value>1</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>word</name>
+          <description>Word.</description>
+          <value>2</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>DSTINC</name>
+        <description>Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.</description>
+        <bitOffset>22</bitOffset>
+        <bitWidth>1</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>dis</name>
+          <description>Disable.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>en</name>
+          <description>Enable.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>BRST</name>
+        <description>Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst.  Burst size equals 1 + value stored in this field.</description>
+        <bitOffset>24</bitOffset>
+        <bitWidth>5</bitWidth>
+       </field>
+       <field>
+        <name>CHDIEN</name>
+        <description>Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.</description>
+        <bitOffset>30</bitOffset>
+        <bitWidth>1</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>dis</name>
+          <description>Disable.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>en</name>
+          <description>Enable.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>CTZIEN</name>
+        <description>Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.</description>
+        <bitOffset>31</bitOffset>
+        <bitWidth>1</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>dis</name>
+          <description>Disable.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>en</name>
+          <description>Enable.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+      </fields>
+     </register>
+     <register>
+      <name>ST</name>
+      <description>DMA Channel Status Register.</description>
+      <addressOffset>0x104</addressOffset>
+      <fields>
+       <field>
+        <name>CH_ST</name>
+        <description>Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware,  the DMA_CFG.CHEN bit is also cleared (if not cleared already).</description>
+        <bitOffset>0</bitOffset>
+        <bitWidth>1</bitWidth>
+        <access>read-only</access>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>dis</name>
+          <description>Disable.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>en</name>
+          <description>Enable.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>IPEND</name>
+        <description>Channel Interrupt.</description>
+        <bitOffset>1</bitOffset>
+        <bitWidth>1</bitWidth>
+        <access>read-only</access>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>inactive</name>
+          <description>No interrupt is pending.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>pending</name>
+          <description>An interrupt is pending.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>CTZ_ST</name>
+        <description>Count-to-Zero (CTZ) Status</description>
+        <bitOffset>2</bitOffset>
+        <bitWidth>1</bitWidth>
+        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+        <enumeratedValues>
+         <name>ctz_st_enum_rd</name>
+         <usage>read</usage>
+         <enumeratedValue>
+          <name>noEvent</name>
+          <description>The event has not occurred.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>occurred</name>
+          <description>The event has occurred.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+        <enumeratedValues>
+         <name>ctz_st_enum_wr</name>
+         <usage>write</usage>
+         <enumeratedValue>
+          <name>Clear</name>
+          <description>Clears the interrupt flag</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>RLD_ST</name>
+        <description>Reload Status.</description>
+        <bitOffset>3</bitOffset>
+        <bitWidth>1</bitWidth>
+        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+        <enumeratedValues>
+         <usage>read</usage>
+         <enumeratedValue>
+          <name>noEvent</name>
+          <description>The event has not occurred.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>occurred</name>
+          <description>The event has occurred.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+        <enumeratedValues>
+         <usage>write</usage>
+         <enumeratedValue>
+          <name>Clear</name>
+          <description>Clears the interrupt flag</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>BUS_ERR</name>
+        <description>Bus Error. Indicates that an AHB abort was received and the channel has been disabled.</description>
+        <bitOffset>4</bitOffset>
+        <bitWidth>1</bitWidth>
+        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+        <enumeratedValues>
+         <usage>read</usage>
+         <enumeratedValue>
+          <name>noEvent</name>
+          <description>The event has not occurred.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>occurred</name>
+          <description>The event has occurred.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+        <enumeratedValues>
+         <usage>write</usage>
+         <enumeratedValue>
+          <name>Clear</name>
+          <description>Clears the interrupt flag</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+       <field>
+        <name>TO_ST</name>
+        <description>Time-Out Status.</description>
+        <bitOffset>6</bitOffset>
+        <bitWidth>1</bitWidth>
+        <modifiedWriteValues>oneToClear</modifiedWriteValues>
+        <enumeratedValues>
+         <usage>read</usage>
+         <enumeratedValue>
+          <name>noEvent</name>
+          <description>The event has not occurred.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>occurred</name>
+          <description>The event has occurred.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+        <enumeratedValues>
+         <usage>write</usage>
+         <enumeratedValue>
+          <name>Clear</name>
+          <description>Clears the interrupt flag</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+      </fields>
+     </register>
+     <register>
+      <name>SRC</name>
+      <description>Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.</description>
+      <addressOffset>0x108</addressOffset>
+      <fields>
+       <field>
+        <name>ADDR</name>
+        <bitOffset>0</bitOffset>
+        <bitWidth>32</bitWidth>
+       </field>
+      </fields>
+     </register>
+     <register>
+      <name>DST</name>
+      <description>Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.</description>
+      <addressOffset>0x10C</addressOffset>
+      <fields>
+       <field>
+        <name>ADDR</name>
+        <bitOffset>0</bitOffset>
+        <bitWidth>32</bitWidth>
+       </field>
+      </fields>
+     </register>
+     <register>
+      <name>CNT</name>
+      <description>DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.</description>
+      <addressOffset>0x110</addressOffset>
+      <fields>
+       <field>
+        <name>CNT</name>
+        <description>DMA Counter.</description>
+        <bitOffset>0</bitOffset>
+        <bitWidth>24</bitWidth>
+       </field>
+      </fields>
+     </register>
+     <register>
+      <name>SRC_RLD</name>
+      <description>Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.</description>
+      <addressOffset>0x114</addressOffset>
+      <fields>
+       <field>
+        <name>SRC_RLD</name>
+        <description>Source Address Reload Value.</description>
+        <bitOffset>0</bitOffset>
+        <bitWidth>31</bitWidth>
+       </field>
+      </fields>
+     </register>
+     <register>
+      <name>DST_RLD</name>
+      <description>Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.</description>
+      <addressOffset>0x118</addressOffset>
+      <fields>
+       <field>
+        <name>DST_RLD</name>
+        <description>Destination Address Reload Value.</description>
+        <bitOffset>0</bitOffset>
+        <bitWidth>31</bitWidth>
+       </field>
+      </fields>
+     </register>
+     <register>
+      <name>CNT_RLD</name>
+      <description>DMA Channel Count Reload Register.</description>
+      <addressOffset>0x11C</addressOffset>
+      <fields>
+       <field>
+        <name>CNT_RLD</name>
+        <description>Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.</description>
+        <bitOffset>0</bitOffset>
+        <bitWidth>24</bitWidth>
+       </field>
+       <field>
+        <name>RLDEN</name>
+        <description>Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.</description>
+        <bitOffset>31</bitOffset>
+        <bitWidth>1</bitWidth>
+        <enumeratedValues>
+         <enumeratedValue>
+          <name>dis</name>
+          <description>Disable.</description>
+          <value>0</value>
+         </enumeratedValue>
+         <enumeratedValue>
+          <name>en</name>
+          <description>Enable.</description>
+          <value>1</value>
+         </enumeratedValue>
+        </enumeratedValues>
+       </field>
+      </fields>
+     </register>
+    </cluster>
+   </registers>
+  </peripheral>
+<!--DMA DMA Controller Fully programmable, chaining capable DMA channels.-->
+  <peripheral>
+   <name>FLC</name>
+   <description>Flash Memory Control.</description>
+   <prependToName>FLSH_</prependToName>
+   <baseAddress>0x40029000</baseAddress>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x1000</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <interrupt>
+    <name>Flash_Controller</name>
+    <description>Flash Controller interrupt.</description>
+    <value>23</value>
+   </interrupt>
+   <registers>
+    <register>
+     <name>ADDR</name>
+     <description>Flash Write Address.</description>
+     <addressOffset>0x00</addressOffset>
+     <fields>
+      <field>
+       <name>ADDR</name>
+       <description>Address for next operation.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CLKDIV</name>
+     <description>Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.</description>
+     <addressOffset>0x04</addressOffset>
+     <resetValue>0x00000064</resetValue>
+     <fields>
+      <field>
+       <name>CLKDIV</name>
+       <description>Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>8</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CN</name>
+     <description>Flash Control Register.</description>
+     <addressOffset>0x08</addressOffset>
+     <fields>
+      <field>
+       <name>WR</name>
+       <description>Write.  This bit is automatically cleared after the operation.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>complete</name>
+         <description>No operation/complete.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>start</name>
+         <description>Start operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field derivedFrom="WR">
+       <name>ME</name>
+       <description>Mass Erase.  This bit is automatically cleared after the operation.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field derivedFrom="WR">
+       <name>PGE</name>
+       <description>Page Erase.  This bit is automatically cleared after the operation.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>WDTH</name>
+       <description>Data Width.  This bits selects write data width.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>size128</name>
+         <description>128-bit.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>size32</name>
+         <description>32-bit.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ERASE_CODE</name>
+       <description>Erase Code.  The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>8</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>nop</name>
+         <description>No operation.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>erasePage</name>
+         <description>Enable Page Erase.</description>
+         <value>0x55</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>eraseAll</name>
+         <description>Enable Mass Erase. The debug port must be enabled.</description>
+         <value>0xAA</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>PEND</name>
+       <description>Flash Pending.  When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.</description>
+       <bitOffset>24</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>idle</name>
+         <description>Idle.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>busy</name>
+         <description>Busy.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>LVE</name>
+       <description>Low Voltage Read Enable </description>
+       <bitOffset>25</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <name>lve_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disabled</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enabled</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>BRST</name>
+       <description>Burst Mode Enable.</description>
+       <bitOffset>27</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>disable</name>
+         <description>Disable</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>enable</name>
+         <description>Enable</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>UNLOCK</name>
+       <description>Flash Unlock.  The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.</description>
+       <bitOffset>28</bitOffset>
+       <bitWidth>4</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>unlocked</name>
+         <description>Flash Unlocked</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>locked</name>
+         <description>Flash Locked</description>
+         <value>3</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INTR</name>
+     <description>Flash Interrupt Register.</description>
+     <addressOffset>0x024</addressOffset>
+     <fields>
+      <field>
+       <name>DONE</name>
+       <description>Flash Done Interrupt.  This bit is set to 1 upon Flash write or erase completion.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No interrupt is pending</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>AF</name>
+       <description>Flash Access Fail.  This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noError</name>
+         <description>No Failure.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>error</name>
+         <description>Failure occurs.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>DONEIE</name>
+       <description>Flash Done Interrupt Enable.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>disable</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>enable</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field derivedFrom="DONEIE">
+       <name>AFIE</name>
+       <bitOffset>9</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <dim>4</dim>
+     <dimIncrement>4</dimIncrement>
+     <name>DATA[%s]</name>
+     <description>Flash Write Data.</description>
+     <addressOffset>0x30</addressOffset>
+     <fields>
+      <field>
+       <name>DATA</name>
+       <description>Data next operation.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>ACNTL</name>
+     <description>Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.</description>
+     <addressOffset>0x40</addressOffset>
+     <access>write-only</access>
+     <fields>
+      <field>
+       <name>ACNTL</name>
+       <description>Access control.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--FLC Flash Memory Control.-->
+  <peripheral>
+   <name>GCR</name>
+   <description>Global Control Registers.</description>
+   <baseAddress>0x40000000</baseAddress>
+   <addressBlock>
+    <offset>0</offset>
+    <size>0x400</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <registers>
+    <register>
+     <name>SCON</name>
+     <description>System Control.</description>
+     <addressOffset>0x00</addressOffset>
+     <resetMask>0xFFFFFFFE</resetMask>
+     <fields>
+      <field>
+       <name>SBUSARB</name>
+       <description>System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>2</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>fix</name>
+         <description>Fixed Burst abritration.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>round</name>
+         <description>Round-robin scheme.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>FLASH_PAGE_FLIP</name>
+       <description>Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>normal</name>
+         <description>Physical layout matches logical layout.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>swapped</name>
+         <description>Bottom half mapped to logical top half and vice versa.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>FPU_DIS</name>
+       <description>Floating Point Unit Disable </description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>enable</name>
+         <description>enable Floating point unit</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>disable</name>
+         <description>disable floating point unit </description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>CCACHE_FLUSH</name>
+       <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>normal</name>
+         <description>Normal Code Cache Operation</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>flush</name>
+         <description>Code Caches and CPU instruction buffer are flushed </description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SWD_DIS</name>
+       <description>Serial Wire Debug Disable </description>
+       <bitOffset>14</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>enable</name>
+         <description>Enable JTAG SWD</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>disable</name>
+         <description>Disable JTAG SWD </description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>RSTR0</name>
+     <description>Reset.</description>
+     <addressOffset>0x04</addressOffset>
+     <fields>
+      <field>
+       <name>DMA</name>
+       <description>DMA Reset.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>dma_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>dma_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>WDT</name>
+       <description>Watchdog Timer Reset.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>wdt_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>wdt_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>GPIO0</name>
+       <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>gpio0_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>gpio0_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TIMER0</name>
+       <description>Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>timer0_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>timer0_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TIMER1</name>
+       <description>Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>timer1_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>timer1_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TIMER2</name>
+       <description>Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>timer2_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>timer2_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>UART0</name>
+       <description>UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description>
+       <bitOffset>11</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>uart0_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>uart0_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>UART1</name>
+       <description>UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description>
+       <bitOffset>12</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>uart1_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>uart1_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SPI0</name>
+       <description>SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description>
+       <bitOffset>13</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>spi0_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>spi0_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SPI1</name>
+       <description>SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description>
+       <bitOffset>14</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>spi1_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>xpi1_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>I2C0</name>
+       <description>I2C0 Reset.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>i2c0_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>i2c0_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RTC</name>
+       <description>Real Time Clock Reset.</description>
+       <bitOffset>17</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>rtc_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>rtc_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SRST</name>
+       <description>Soft Reset.Write 1 to perform a Soft Reset. A soft reset performs a Peripheral Reset and also resets the GPIO peripheral but does not reset the CPU or Watchdog Timer.</description>
+       <bitOffset>29</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>srst_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>srst_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>PRST</name>
+       <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description>
+       <bitOffset>30</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>prst_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>prst_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SYSTEM</name>
+       <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description>
+       <bitOffset>31</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>system_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>system_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>Reset_Done</name>
+         <description>Reset Complete</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Busy</name>
+         <description>Reset Busy</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CLKCN</name>
+     <description>Clock Control.</description>
+     <addressOffset>0x08</addressOffset>
+     <resetValue>0x00000008</resetValue>
+     <fields>
+      <field>
+       <name>PSC</name>
+       <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>3</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>div1</name>
+         <description>Divide by 1.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div2</name>
+         <description>Divide by 2.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div4</name>
+         <description>Divide by 4.</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div8</name>
+         <description>Divide by 8.</description>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div16</name>
+         <description>Divide by 16.</description>
+         <value>4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div32</name>
+         <description>Divide by 32.</description>
+         <value>5</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div64</name>
+         <description>Divide by 64.</description>
+         <value>6</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div128</name>
+         <description>Divide by 128.</description>
+         <value>7</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>CLKSEL</name>
+       <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description>
+       <bitOffset>9</bitOffset>
+       <bitWidth>3</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>HIRC</name>
+         <description>The internal 96 MHz oscillator is used for the system clock.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>nanoRing</name>
+         <description>The nano-ring output is used for the system clock.</description>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>hfxIn</name>
+         <description>HFXIN is used for the system clock.</description>
+         <value>6</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>CKRDY</name>
+       <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description>
+       <bitOffset>13</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>busy</name>
+         <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>ready</name>
+         <description>System clock running from CLKSEL clock source.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>X32K_EN</name>
+       <description>32kHz Crystal Oscillator Enable.</description>
+       <bitOffset>17</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Is Disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Is Enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>HIRC_EN</name>
+       <description>60MHz High Frequency Internal Reference Clock Enable.</description>
+       <bitOffset>18</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Is Disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Is Enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>X32K_RDY</name>
+       <description>32kHz Crystal Oscillator Ready</description>
+       <bitOffset>25</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>not</name>
+         <description>Not Ready</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Ready</name>
+         <description>X32K Ready</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>HIRC_RDY</name>
+       <description>60MHz HIRC Ready.</description>
+       <bitOffset>26</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>not</name>
+         <description>Not Ready</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>ready</name>
+         <description>HIRC Ready</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>LIRC8K_RDY</name>
+       <description>8kHz Low Frequency Reference Clock Ready.</description>
+       <bitOffset>29</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>not</name>
+         <description>Not Ready</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>ready</name>
+         <description>Clock Ready</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>PM</name>
+     <description>Power Management.</description>
+     <addressOffset>0x0C</addressOffset>
+     <fields>
+      <field>
+       <name>MODE</name>
+       <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>3</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>active</name>
+         <description>Active Mode.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>shutdown</name>
+         <description>Shutdown Mode.</description>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>backup</name>
+         <description>Backup Mode.</description>
+         <value>4</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>GPIOWKEN</name>
+       <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Wake Up Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Wake Up Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RTCWKEN</name>
+       <description>RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Wake Up Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Wake Up Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>HIRCPD</name>
+       <description>HIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode. </description>
+       <bitOffset>15</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>active</name>
+         <description>Mode is Active.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>deepsleep</name>
+         <description>Powered down in DEEPSLEEP.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>PCKDIV</name>
+     <description>Peripheral Clock Divider.</description>
+     <addressOffset>0x18</addressOffset>
+     <resetValue>0x00000001</resetValue>
+     <fields>
+      <field>
+       <name>AONCD</name>
+       <description>Always-ON(AON) domain CLock Divider. These bits define the AON domain clock divider.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>2</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>div_4</name>
+         <description>PCLK divide by 4.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div_8</name>
+         <description>PCLK divide by 8.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div_16</name>
+         <description>PCLK divide by 16.</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div_32</name>
+         <description>PCLK divide by 32.</description>
+         <value>3</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>PERCKCN0</name>
+     <description>Peripheral Clock Disable.</description>
+     <addressOffset>0x24</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO0D</name>
+       <description>GPIO0 Disable.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>GPIODisable</name>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enable it.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disable it.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>DMAD</name>
+       <description>DMA Disable.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>GPIODisable</name>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enable it.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disable it.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SPI0D</name>
+       <description>SPI 0 Disable.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>GPIODisable</name>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enable it.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disable it.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SPI1D</name>
+       <description>SPI 1 Disable.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>GPIODisable</name>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enable it.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disable it.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>UART0D</name>
+       <description>UART 0 Disable.</description>
+       <bitOffset>9</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>GPIODisable</name>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enable it.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disable it.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>UART1D</name>
+       <description>UART 1 Disable.</description>
+       <bitOffset>10</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>GPIODisable</name>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enable it.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disable it.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>I2C0D</name>
+       <description>I2C 0 Disable.</description>
+       <bitOffset>13</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>GPIODisable</name>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enable it.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disable it.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>T0D</name>
+       <description>Timer 0 Disable.</description>
+       <bitOffset>15</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>GPIODisable</name>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enable it.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disable it.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>T1D</name>
+       <description>Timer 1 Disable.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>GPIODisable</name>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enable it.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disable it.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>T2D</name>
+       <description>Timer 2 Disable.</description>
+       <bitOffset>17</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>GPIODisable</name>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enable it.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disable it.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>I2C1D</name>
+       <description>I2C 1 Disable.</description>
+       <bitOffset>28</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>GPIODisable</name>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enable it.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disable it.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>MEMCKCN</name>
+     <description>Memory Clock Control Register.</description>
+     <addressOffset>0x28</addressOffset>
+     <fields>
+      <field>
+       <name>FWS</name>
+       <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>3</bitWidth>
+      </field>
+      <field>
+       <name>SYSRAM0LS</name>
+       <description>System RAM 0 Light Sleep Mode.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>active</name>
+         <description>Memory is active.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>light_sleep</name>
+         <description>Memory is in Light Sleep mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SYSRAM1LS</name>
+       <description>System RAM 1 Light Sleep Mode.</description>
+       <bitOffset>9</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>active</name>
+         <description>Memory is active.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>light_sleep</name>
+         <description>Memory is in Light Sleep mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SYSRAM2LS</name>
+       <description>System RAM 2 Light Sleep Mode.</description>
+       <bitOffset>10</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>active</name>
+         <description>Memory is active.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>light_sleep</name>
+         <description>Memory is in Light Sleep mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SYSRAM3LS</name>
+       <description>System RAM 3 Light Sleep Mode.</description>
+       <bitOffset>11</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>active</name>
+         <description>Memory is active.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>light_sleep</name>
+         <description>Memory is in Light Sleep mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ICACHELS</name>
+       <description>ICache RAM Light Sleep Mode.</description>
+       <bitOffset>12</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>active</name>
+         <description>Memory is active.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>light_sleep</name>
+         <description>Memory is in Light Sleep mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>MEMZCN</name>
+     <description>Memory Zeroize Control.</description>
+     <addressOffset>0x2C</addressOffset>
+     <fields>
+      <field>
+       <name>SRAM0Z</name>
+       <description>System RAM Block 0.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>nop</name>
+         <description>No operation/complete.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>start</name>
+         <description>Start operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ICACHEZ</name>
+       <description>Instruction Cache.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>nop</name>
+         <description>No operation/complete.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>start</name>
+         <description>Start operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>SCCK</name>
+     <description>Smart Card Clock Control.</description>
+     <addressOffset>0x34</addressOffset>
+     <resetValue>0x00001414</resetValue>
+    </register>
+    <register>
+     <name>MPRI0</name>
+     <description>Master Priority Control Register 0.</description>
+     <addressOffset>0x38</addressOffset>
+     <resetValue>0x00001414</resetValue>
+    </register>
+    <register>
+     <name>MPRI1</name>
+     <description>Mater Priority Control Register 1.</description>
+     <addressOffset>0x3C</addressOffset>
+     <resetValue>0x00001414</resetValue>
+    </register>
+    <register>
+     <name>SYSST</name>
+     <description>System Status Register.</description>
+     <addressOffset>0x40</addressOffset>
+     <fields>
+      <field>
+       <name>ICECLOCK</name>
+       <description>ARM ICE Lock Status.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>unlocked</name>
+         <description>ICE is unlocked.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>locked</name>
+         <description>ICE is locked.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>CODEINTERR</name>
+       <description>Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. </description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>norm</name>
+         <description>Normal Operating Condition.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>code</name>
+         <description>Code Integrity Error.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SCMEMF</name>
+       <description>System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>norm</name>
+         <description>Normal Operating Condition.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>memory</name>
+         <description>Memory Fault.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>RSTR1</name>
+     <description>Reset 1.</description>
+     <addressOffset>0x44</addressOffset>
+     <fields>
+      <field>
+       <name>I2C1</name>
+       <description>I2C1 Reset.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>reset_write</name>
+        <usage>write</usage>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>reset</name>
+         <description>Starts reset operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+       <enumeratedValues>
+        <name>reset_read</name>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>reset_done</name>
+         <description>Reset complete.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>busy</name>
+         <description>Reset in progress.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>PERCKCN1</name>
+     <description>Peripheral Clock Disable.</description>
+     <addressOffset>0x48</addressOffset>
+     <fields>
+      <field>
+       <name>FLCD</name>
+       <description>Secure Flash Controller Disable.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ICACHED</name>
+       <description>ICache Clock Disable. </description>
+       <bitOffset>11</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>EVTEN</name>
+     <description>Event Enable Register.</description>
+     <addressOffset>0x4C</addressOffset>
+     <fields>
+      <field>
+       <name>DMAEVENT</name>
+       <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>RXEVENT</name>
+       <description>Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. </description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>REVISION</name>
+     <description>Revision Register.</description>
+     <addressOffset>0x50</addressOffset>
+     <access>read-only</access>
+     <fields>
+      <field>
+       <name>REVISION</name>
+       <description>Manufacturer Chip Revision. </description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>16</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>SYSSIE</name>
+     <description>System Status Interrupt Enable Register.</description>
+     <addressOffset>0x54</addressOffset>
+     <fields>
+      <field>
+       <name>ICEULIE</name>
+       <description>ARM ICE Unlock Interrupt Enable.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>CIEIE</name>
+       <description>Code Integrity Error Interrupt Enable.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SCMFIE</name>
+       <description>System Cache Memory Fault Interrupt Enable.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--GCR Global Control Registers.-->
+  <peripheral>
+   <name>GPIO0</name>
+   <description>Individual I/O for each GPIO</description>
+   <groupName>GPIO</groupName>
+   <baseAddress>0x40008000</baseAddress>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x1000</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <interrupt>
+    <name>GPIO0</name>
+    <description>GPIO0 interrupt.</description>
+    <value>24</value>
+   </interrupt>
+   <registers>
+    <register>
+     <name>EN</name>
+     <description>GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.</description>
+     <addressOffset>0x00</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_EN</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>alternate</name>
+         <description>Alternate function enabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>GPIO</name>
+         <description>GPIO function is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>EN_SET</name>
+     <description>GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.</description>
+     <addressOffset>0x04</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>EN_CLR</name>
+     <description>GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.</description>
+     <addressOffset>0x08</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>OUT_EN</name>
+     <description>GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.</description>
+     <addressOffset>0x0C</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_OUT_EN</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>GPIO Output Disable</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>GPIO Output Enable</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>OUT_EN_SET</name>
+     <description>GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.</description>
+     <addressOffset>0x10</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>OUT_EN_CLR</name>
+     <description>GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.</description>
+     <addressOffset>0x14</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>OUT</name>
+     <description>GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port.  This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.</description>
+     <addressOffset>0x18</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_OUT</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>low</name>
+         <description>Drive Logic 0 (low) on GPIO output.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>high</name>
+         <description>Drive logic 1 (high) on GPIO output.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>OUT_SET</name>
+     <description>GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.</description>
+     <addressOffset>0x1C</addressOffset>
+     <access>write-only</access>
+     <fields>
+      <field>
+       <name>GPIO_OUT_SET</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <description>No Effect.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>set</name>
+         <description>Set GPIO_OUT bit in this position to '1'</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>OUT_CLR</name>
+     <description>GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.</description>
+     <addressOffset>0x20</addressOffset>
+     <access>write-only</access>
+     <fields>
+      <field>
+       <name>GPIO_OUT_CLR</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>IN</name>
+     <description>GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.</description>
+     <addressOffset>0x24</addressOffset>
+     <access>read-only</access>
+     <fields>
+      <field>
+       <name>GPIO_IN</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_MOD</name>
+     <description>GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.</description>
+     <addressOffset>0x28</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_INT_MOD</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>level</name>
+         <description>Interrupts for this pin are level triggered.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>edge</name>
+         <description>Interrupts for this pin are edge triggered.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_POL</name>
+     <description>GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.</description>
+     <addressOffset>0x2C</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_INT_POL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>falling</name>
+         <description>Interrupts are latched on a falling edge or low level condition for this pin.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>rising</name>
+         <description>Interrupts are latched on a rising edge or high condition for this pin.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_EN</name>
+     <description>GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.</description>
+     <addressOffset>0x34</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_INT_EN</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupts are disabled for this GPIO pin.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupts are enabled for this GPIO pin.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_EN_SET</name>
+     <description>GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.</description>
+     <addressOffset>0x38</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_INT_EN_SET</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <description>No effect.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>set</name>
+         <description>Set GPIO_INT_EN bit in this position to '1'</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_EN_CLR</name>
+     <description>GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.</description>
+     <addressOffset>0x3C</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_INT_EN_CLR</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <description>No Effect.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Clear GPIO_INT_EN bit in this position to '0'</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_STAT</name>
+     <description>GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.</description>
+     <addressOffset>0x40</addressOffset>
+     <access>read-only</access>
+     <fields>
+      <field>
+       <name>GPIO_INT_STAT</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <description>No Interrupt is pending on this GPIO pin.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An Interrupt is pending on this GPIO pin.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_CLR</name>
+     <description>GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.</description>
+     <addressOffset>0x48</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>WAKE_EN</name>
+     <description>GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.</description>
+     <addressOffset>0x4C</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_WAKE_EN</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>PMU wakeup for this GPIO is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>PMU wakeup for this GPIO is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>WAKE_EN_SET</name>
+     <description>GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.</description>
+     <addressOffset>0x50</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>WAKE_EN_CLR</name>
+     <description>GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.</description>
+     <addressOffset>0x54</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_DUAL_EDGE</name>
+     <description>GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.</description>
+     <addressOffset>0x5C</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_INT_DUAL_EDGE</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <description>No Effect.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>PAD_CFG1</name>
+     <description>GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description>
+     <addressOffset>0x60</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_PAD_CFG1</name>
+       <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>impedance</name>
+         <description>High Impedance.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pu</name>
+         <description>Weak pull-up mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pd</name>
+         <description>weak pull-down mode.</description>
+         <value>2</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>PAD_CFG2</name>
+     <description>GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description>
+     <addressOffset>0x64</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_PAD_CFG2</name>
+       <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>impedance</name>
+         <description>High Impedance.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pu</name>
+         <description>Weak pull-up mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pd</name>
+         <description>weak pull-down mode.</description>
+         <value>2</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>EN1</name>
+     <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description>
+     <addressOffset>0x68</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_EN1</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>primary</name>
+         <description>Primary function selected.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>secondary</name>
+         <description>Secondary function selected.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>EN1_SET</name>
+     <description>GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.</description>
+     <addressOffset>0x6C</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>EN1_CLR</name>
+     <description>GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.</description>
+     <addressOffset>0x70</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>EN2</name>
+     <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description>
+     <addressOffset>0x74</addressOffset>
+     <fields>
+      <field>
+       <name>GPIO_EN2</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>primary</name>
+         <description>Primary function selected.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>secondary</name>
+         <description>Secondary function selected.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>EN2_SET</name>
+     <description>GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.</description>
+     <addressOffset>0x78</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>EN2_CLR</name>
+     <description>GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.</description>
+     <addressOffset>0x7C</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>IS</name>
+     <description>Input Hysteresis Enable Register</description>
+     <addressOffset>0xA8</addressOffset>
+    </register>
+    <register>
+     <name>SR</name>
+     <description>Slew Rate Select Register.</description>
+     <addressOffset>0xAC</addressOffset>
+    </register>
+    <register>
+     <name>DS</name>
+     <description>GPIO Drive Strength  Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description>
+     <addressOffset>0xB0</addressOffset>
+     <fields>
+      <field>
+       <name>DS</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>ld</name>
+         <description>GPIO port pin is in low-drive mode.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>hd</name>
+         <description>GPIO port pin is in high-drive mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>DS1</name>
+     <description>GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description>
+     <addressOffset>0xB4</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>PS</name>
+     <description>GPIO Pull Select Mode.</description>
+     <addressOffset>0xB8</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>VSSEL</name>
+     <description>GPIO Voltage Select.</description>
+     <addressOffset>0xC0</addressOffset>
+     <fields>
+      <field>
+       <name>ALL</name>
+       <description>Mask of all of the pins on the port.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--GPIO0 Individual I/O for each GPIO-->
+  <peripheral>
+   <name>I2C0</name>
+   <description>Inter-Integrated Circuit.</description>
+   <groupName>I2C</groupName>
+   <baseAddress>0x4001D000</baseAddress>
+   <size>32</size>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x1000</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <interrupt>
+    <name>I2C0</name>
+    <description>I2C0 IRQ</description>
+    <value>13</value>
+   </interrupt>
+   <registers>
+    <register>
+     <name>CTRL</name>
+     <description>Control Register0.</description>
+     <addressOffset>0x00</addressOffset>
+     <fields>
+      <field>
+       <name>I2C_EN</name>
+       <description>I2C Enable.</description>
+       <bitRange>[0:0]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable I2C.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>enable I2C.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>MST</name>
+       <description>Master Mode Enable.</description>
+       <bitRange>[1:1]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>slave_mode</name>
+         <description>Slave Mode.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>master_mode</name>
+         <description>Master Mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>GEN_CALL_ADDR</name>
+       <description>General Call Address Enable.</description>
+       <bitRange>[2:2]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Ignore Gneral Call Address.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Acknowledge general call address.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_MODE</name>
+       <description>Interactive Receive Mode.</description>
+       <bitRange>[3:3]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable Interactive Receive Mode.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable Interactive Receive Mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_MODE_ACK</name>
+       <description>Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.</description>
+       <bitRange>[4:4]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>ack</name>
+         <description>return ACK (pulling SDA LOW).</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>nack</name>
+         <description>return NACK (leaving SDA HIGH).</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SCL_OUT</name>
+       <description>SCL Output. This bits control SCL output when SWOE =1.</description>
+       <bitRange>[6:6]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>drive_scl_low</name>
+         <description>Drive SCL low. </description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>release_scl</name>
+         <description>Release SCL.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SDA_OUT</name>
+       <description>SDA Output. This bits control SDA output when SWOE = 1. </description>
+       <bitRange>[7:7]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>drive_sda_low</name>
+         <description>Drive SDA low. </description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>release_sda</name>
+         <description>Release SDA.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SCL</name>
+       <description>SCL status. This bit reflects the logic gate of SCL signal. </description>
+       <bitRange>[8:8]</bitRange>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>SDA</name>
+       <description>SDA status. THis bit reflects the logic gate of SDA signal.</description>
+       <bitRange>[9:9]</bitRange>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>SW_OUT_EN</name>
+       <description>Software Output Enable.</description>
+       <bitRange>[10:10]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>outputs_disable</name>
+         <description>I2C Outputs SCLO and SDAO disabled. </description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>outputs_enable</name>
+         <description>I2C Outputs SCLO and SDAO enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>READ</name>
+       <description>Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.</description>
+       <bitRange>[11:11]</bitRange>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>write</name>
+         <description>Write.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>read</name>
+         <description>Read.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SCL_CLK_STRECH_DIS</name>
+       <description>This bit will disable slave clock stretching when set.</description>
+       <bitRange>[12:12]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Slave clock stretching enabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Slave clock stretching disabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SCL_PP_MODE</name>
+       <description>SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. </description>
+       <bitRange>[13:13]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Standard open-drain operation: drive low for 0, Hi-Z for 1</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Non-standard push-pull operation: drive low for 0, drive high for 1</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>HS_MODE</name>
+       <description>Hs-mode Enable.</description>
+       <bitOffset>15</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Hs-mode disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Hs-mode enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>STATUS</name>
+     <description>Status Register.</description>
+     <addressOffset>0x04</addressOffset>
+     <fields>
+      <field>
+       <name>BUS</name>
+       <description>Bus Status.</description>
+       <bitRange>[0:0]</bitRange>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>idle</name>
+         <description>I2C Bus Idle.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>busy</name>
+         <description>I2C Bus Busy.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_EMPTY</name>
+       <description>RX empty.</description>
+       <bitRange>[1:1]</bitRange>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>not_empty</name>
+         <description>Not Empty.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>empty</name>
+         <description>Empty.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_FULL</name>
+       <description>RX Full.</description>
+       <bitRange>[2:2]</bitRange>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>not_full</name>
+         <description>Not Full.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>full</name>
+         <description>Full.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_EMPTY</name>
+       <description>TX Empty.</description>
+       <bitRange>[3:3]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>not_empty</name>
+         <description>Not Empty.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>empty</name>
+         <description>Empty.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_FULL</name>
+       <description>TX Full.</description>
+       <bitRange>[4:4]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>not_empty</name>
+         <description>Not Empty.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>empty</name>
+         <description>Empty.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>CLK_MODE</name>
+       <description>Clock Mode.</description>
+       <bitRange>[5:5]</bitRange>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>not_actively_driving_scl_clock</name>
+         <description>Device not actively driving SCL clock cycles.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>actively_driving_scl_clock</name>
+         <description>Device operating as master and actively driving SCL clock cycles.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>STATUS</name>
+       <description>Controller Status.</description>
+       <bitRange>[11:8]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>idle</name>
+         <description>Controller Idle.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>mtx_addr</name>
+         <description>master Transmit address.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>mrx_addr_ack</name>
+         <description>Master Receive address ACK.</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>mtx_ex_addr</name>
+         <description>Master Transmit extended address.</description>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>mrx_ex_addr</name>
+         <description>Master Receive extended address ACK.</description>
+         <value>4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>srx_addr</name>
+         <description>Slave Receive address.</description>
+         <value>5</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>stx_addr_ack</name>
+         <description>Slave Transmit address ACK.</description>
+         <value>6</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>srx_ex_addr</name>
+         <description>Slave Receive extended address.</description>
+         <value>7</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>stx_ex_addr_ack</name>
+         <description>Slave Transmit extended address ACK.</description>
+         <value>8</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>tx</name>
+         <description>Transmit data (master or slave).</description>
+         <value>9</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>rx_ack</name>
+         <description>Receive data ACK (master or slave).</description>
+         <value>10</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>rx</name>
+         <description>Receive data (master or slave).</description>
+         <value>11</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>tx_ack</name>
+         <description>Transmit data ACK (master or slave).</description>
+         <value>12</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>nack</name>
+         <description>NACK stage (master or slave).</description>
+         <value>13</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>by_st</name>
+         <description>Bystander state (ongoing transaction but not participant- another master addressing another slave).</description>
+         <value>15</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_FL0</name>
+     <description>Interrupt Status Register.</description>
+     <addressOffset>0x08</addressOffset>
+     <fields>
+      <field>
+       <name>DONE</name>
+       <description>Transfer Done Interrupt.</description>
+       <bitRange>[0:0]</bitRange>
+       <enumeratedValues>
+        <name>INT_FL0_Done</name>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_MODE</name>
+       <description>Interactive Receive Interrupt.</description>
+       <bitRange>[1:1]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>GEN_CALL_ADDR</name>
+       <description>Slave General Call Address Match Interrupt.</description>
+       <bitRange>[2:2]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ADDR_MATCH</name>
+       <description>Slave Address Match Interrupt.</description>
+       <bitRange>[3:3]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_THRESH</name>
+       <description>Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.</description>
+       <bitRange>[4:4]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No interrupt is pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending. RX_FIFO equal or more bytes than the threshold.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_THRESH</name>
+       <description>Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.</description>
+       <bitRange>[5:5]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No interrupt is pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>STOP</name>
+       <description>STOP Interrupt.</description>
+       <bitRange>[6:6]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No interrupt is pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ADDR_ACK</name>
+       <description>Address Acknowledge Interrupt.</description>
+       <bitRange>[7:7]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ARB_ER</name>
+       <description>Arbritation error Interrupt.</description>
+       <bitRange>[8:8]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TO_ER</name>
+       <description>timeout Error Interrupt.</description>
+       <bitRange>[9:9]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ADDR_NACK_ER</name>
+       <description>Address NACK Error Interrupt.</description>
+       <bitRange>[10:10]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>DATA_ER</name>
+       <description>Data NACK Error Interrupt.</description>
+       <bitRange>[11:11]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>DO_NOT_RESP_ER</name>
+       <description>Do Not Respond Error Interrupt.</description>
+       <bitRange>[12:12]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>START_ER</name>
+       <description>Start Error Interrupt.</description>
+       <bitRange>[13:13]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>STOP_ER</name>
+       <description>Stop Error Interrupt.</description>
+       <bitRange>[14:14]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_LOCK_OUT</name>
+       <description>Transmit Lock Out Interrupt.</description>
+       <bitRange>[15:15]</bitRange>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_EN0</name>
+     <description>Interrupt Enable Register.</description>
+     <addressOffset>0x0C</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>DONE</name>
+       <description>Transfer Done Interrupt Enable.</description>
+       <bitRange>[0:0]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled when DONE = 1.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_MODE</name>
+       <description>Description not available.</description>
+       <bitRange>[1:1]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled when RX_MODE = 1.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>GEN_CTRL_ADDR</name>
+       <description>Slave mode general call address match received input enable.</description>
+       <bitRange>[2:2]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled when GEN_CTRL_ADDR = 1.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ADDR_MATCH</name>
+       <description>Slave mode incoming address match interrupt.</description>
+       <bitRange>[3:3]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled when ADDR_MATCH = 1.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_THRESH</name>
+       <description>RX FIFO Above Treshold Level Interrupt Enable.</description>
+       <bitRange>[4:4]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_THRESH</name>
+       <description>TX FIFO Below Treshold Level Interrupt Enable.</description>
+       <bitRange>[5:5]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>STOP</name>
+       <description>Stop Interrupt Enable</description>
+       <bitRange>[6:6]</bitRange>
+       <access>read-write</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled when STOP = 1.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ADDR_ACK</name>
+       <description>Received Address ACK from Slave Interrupt.</description>
+       <bitRange>[7:7]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ARB_ER</name>
+       <description>Master Mode Arbitration Lost Interrupt.</description>
+       <bitRange>[8:8]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TO_ER</name>
+       <description>Timeout Error Interrupt Enable.</description>
+       <bitRange>[9:9]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ADDR_ER</name>
+       <description>Master Mode Address NACK Received Interrupt.</description>
+       <bitRange>[10:10]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>DATA_ER</name>
+       <description>Master Mode Data NACK Received Interrupt.</description>
+       <bitRange>[11:11]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>DO_NOT_RESP_ER</name>
+       <description>Slave Mode Do Not Respond Interrupt.</description>
+       <bitRange>[12:12]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>START_ER</name>
+       <description>Out of Sequence START condition detected interrupt.</description>
+       <bitRange>[13:13]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>STOP_ER</name>
+       <description>Out of Sequence STOP condition detected interrupt.</description>
+       <bitRange>[14:14]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_LOCK_OUT</name>
+       <description>TX FIFO Locked Out Interrupt.</description>
+       <bitRange>[15:15]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt enabled when TXLOIE = 1.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_FL1</name>
+     <description>Interrupt Status Register 1.</description>
+     <addressOffset>0x10</addressOffset>
+     <fields>
+      <field>
+       <name>RX_OVERFLOW</name>
+       <description>Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.</description>
+       <bitRange>[0:0]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_UNDERFLOW</name>
+       <description>Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).</description>
+       <bitRange>[1:1]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_EN1</name>
+     <description>Interrupt Staus Register 1.</description>
+     <addressOffset>0x14</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>RX_OVERFLOW</name>
+       <description>Receiver Overflow Interrupt Enable.</description>
+       <bitRange>[0:0]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_UNDERFLOW</name>
+       <description>Transmit Underflow Interrupt Enable.</description>
+       <bitRange>[1:1]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>No Interrupt is Pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>FIFO_LEN</name>
+     <description>FIFO Configuration Register.</description>
+     <addressOffset>0x18</addressOffset>
+     <fields>
+      <field>
+       <name>RX_LEN</name>
+       <description>Receive FIFO Length.</description>
+       <bitRange>[7:0]</bitRange>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>TX_LEN</name>
+       <description>Transmit FIFO Length.</description>
+       <bitRange>[15:8]</bitRange>
+       <access>read-only</access>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>RX_CTRL0</name>
+     <description>Receive Control Register 0.</description>
+     <addressOffset>0x1C</addressOffset>
+     <fields>
+      <field>
+       <name>DNR</name>
+       <description>Do Not Respond.</description>
+       <bitRange>[0:0]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>respond</name>
+         <description>Always respond to address match.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>not_respond_rx_fifo_empty</name>
+         <description>Do not respond to address match when RX_FIFO is not empty.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_FLUSH</name>
+       <description>Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.</description>
+       <bitRange>[7:7]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>not_flushed</name>
+         <description>FIFO not flushed.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>flush</name>
+         <description>Flush RX_FIFO.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_THRESH</name>
+       <description>Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.</description>
+       <bitRange>[11:8]</bitRange>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>RX_CTRL1</name>
+     <description>Receive Control Register 1.</description>
+     <addressOffset>0x20</addressOffset>
+     <fields>
+      <field>
+       <name>RX_CNT</name>
+       <description>Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.</description>
+       <bitRange>[7:0]</bitRange>
+      </field>
+      <field>
+       <name>RX_FIFO</name>
+       <description>Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.</description>
+       <bitRange>[11:8]</bitRange>
+       <access>read-only</access>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>TX_CTRL0</name>
+     <description>Transmit Control Register 0.</description>
+     <addressOffset>0x24</addressOffset>
+     <fields>
+      <field>
+       <name>TX_PRELOAD</name>
+       <description>Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.</description>
+       <bitRange>[0:0]</bitRange>
+      </field>
+      <field>
+       <name>TX_READY_MODE</name>
+       <description>Transmit FIFO Ready Manual Mode.</description>
+       <bitRange>[1:1]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>en</name>
+         <description>HW control of I2CTXRDY enabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>HW control of I2CTXRDY disabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_FLUSH</name>
+       <description>Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.</description>
+       <bitRange>[7:7]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>not_flushed</name>
+         <description>FIFO not flushed.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>flush</name>
+         <description>Flush TX_FIFO.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_THRESH</name>
+       <description>Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.</description>
+       <bitRange>[11:8]</bitRange>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>TX_CTRL1</name>
+     <description>Transmit Control Register 1.</description>
+     <addressOffset>0x28</addressOffset>
+     <fields>
+      <field>
+       <name>TX_READY</name>
+       <description>Transmit FIFO Preload Ready.</description>
+       <bitRange>[0:0]</bitRange>
+      </field>
+      <field>
+       <name>TX_LAST</name>
+       <description>Transmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware).</description>
+       <bitRange>[1:1]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>hold_scl_low</name>
+         <description>Hold SCL low on TX_FIFO empty.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>end_transaction</name>
+         <description>End transaction on TX_FIFO empty.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_FIFO</name>
+       <description>Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.</description>
+       <bitRange>[11:8]</bitRange>
+       <access>read-only</access>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>FIFO</name>
+     <description>Data Register.</description>
+     <addressOffset>0x2C</addressOffset>
+     <fields>
+      <field>
+       <name>DATA</name>
+       <description>Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>8</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>MASTER_CTRL</name>
+     <description>Master Control Register.</description>
+     <addressOffset>0x30</addressOffset>
+     <fields>
+      <field>
+       <name>START</name>
+       <description>Setting this bit to 1 will start a master transfer.</description>
+       <bitRange>[0:0]</bitRange>
+      </field>
+      <field>
+       <name>RESTART</name>
+       <description>Setting this bit to 1 will generate a repeated START.</description>
+       <bitRange>[1:1]</bitRange>
+      </field>
+      <field>
+       <name>STOP</name>
+       <description>Setting this bit to 1 will generate a STOP condition.</description>
+       <bitRange>[2:2]</bitRange>
+      </field>
+      <field>
+       <name>SL_EX_ADDR</name>
+       <description>Slave Extend Address Select.</description>
+       <bitRange>[7:7]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>7_bits_address</name>
+         <description>7-bit address.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>10_bits_address</name>
+         <description>10-bit address.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>MASTER_CODE</name>
+       <description>Master Code. These bits set the Master Code used in Hs-mode operation.</description>
+       <bitRange>[10:8]</bitRange>
+      </field>
+      <field>
+       <name>SCL_SPEED_UP</name>
+       <description>Serial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves.</description>
+       <bitRange>[11:11]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Master monitors SCL state.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>SCL state monitoring disabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CLK_LO</name>
+     <description>Clock Low Register.</description>
+     <addressOffset>0x34</addressOffset>
+     <fields>
+      <field>
+       <name>CLK_LO</name>
+       <description>Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.</description>
+       <bitRange>[8:0]</bitRange>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CLK_HI</name>
+     <description>Clock high Register.</description>
+     <addressOffset>0x38</addressOffset>
+     <fields>
+      <field>
+       <name>CKH</name>
+       <description>Clock High. In master mode, these bits define the SCL high period.</description>
+       <bitRange>[8:0]</bitRange>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>HS_CLK</name>
+     <description>HS-Mode Clock Control Register</description>
+     <addressOffset>0x3C</addressOffset>
+     <fields>
+      <field>
+       <name>HS_CLK_LO</name>
+       <description>Slave Address.</description>
+       <bitRange>[7:0]</bitRange>
+      </field>
+      <field>
+       <name>HS_CLK_HI</name>
+       <description>Slave Address.</description>
+       <bitRange>[15:8]</bitRange>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>TIMEOUT</name>
+     <description>Timeout Register</description>
+     <addressOffset>0x40</addressOffset>
+     <fields>
+      <field>
+       <name>TO</name>
+       <description>Timeout</description>
+       <bitRange>[15:0]</bitRange>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>SLAVE_ADDR</name>
+     <description>Slave Address Register.</description>
+     <addressOffset>0x44</addressOffset>
+     <fields>
+      <field>
+       <name>SLAVE_ADDR</name>
+       <description>Slave Address.</description>
+       <bitRange>[9:0]</bitRange>
+      </field>
+      <field>
+       <name>SLAVE_ADDR_DIS</name>
+       <description>Slave Address DIS.</description>
+       <bitRange>[10:10]</bitRange>
+      </field>
+      <field>
+       <name>SLAVE_ADDR_IDX</name>
+       <description>Slave Address Index.</description>
+       <bitRange>[14:11]</bitRange>
+      </field>
+      <field>
+       <name>EX_ADDR</name>
+       <description>Extended Address Select.</description>
+       <bitRange>[15:15]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>7_bits_address</name>
+         <description>7-bit address.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>10_bits_address</name>
+         <description>10-bit address.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>DMA</name>
+     <description>DMA Register.</description>
+     <addressOffset>0x48</addressOffset>
+     <fields>
+      <field>
+       <name>TX_EN</name>
+       <description>TX channel enable.</description>
+       <bitRange>[0:0]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_EN</name>
+       <description>RX channel enable.</description>
+       <bitRange>[1:1]</bitRange>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--I2C0 Inter-Integrated Circuit.-->
+  <peripheral derivedFrom="I2C0">
+   <name>I2C1</name>
+   <description>Inter-Integrated Circuit. 1</description>
+   <baseAddress>0x4001E000</baseAddress>
+   <interrupt>
+    <name>I2C1</name>
+    <description>I2C1 IRQ</description>
+    <value>36</value>
+   </interrupt>
+  </peripheral>
+<!--I2C1 Inter-Integrated Circuit. 1-->
+  <peripheral>
+   <name>ICC0</name>
+   <description>Instruction Cache Controller Registers</description>
+   <baseAddress>0x4002A000</baseAddress>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x1000</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <registers>
+    <register>
+     <name>CACHE_ID</name>
+     <description>Cache ID Register.</description>
+     <addressOffset>0x0000</addressOffset>
+     <access>read-only</access>
+     <fields>
+      <field>
+       <name>RELNUM</name>
+       <description>Release Number. Identifies the RTL release version.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>6</bitWidth>
+      </field>
+      <field>
+       <name>PARTNUM</name>
+       <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>4</bitWidth>
+      </field>
+      <field>
+       <name>CCHID</name>
+       <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description>
+       <bitOffset>10</bitOffset>
+       <bitWidth>6</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>MEMCFG</name>
+     <description>Memory Configuration Register.</description>
+     <addressOffset>0x0004</addressOffset>
+     <access>read-only</access>
+     <resetValue>0x00080008</resetValue>
+     <fields>
+      <field>
+       <name>CCHSZ</name>
+       <description>Cache Size. Indicates total size in Kbytes of cache.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>16</bitWidth>
+      </field>
+      <field>
+       <name>MEMSZ</name>
+       <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>16</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CACHE_CTRL</name>
+     <description>Cache Control and Status Register.</description>
+     <addressOffset>0x0100</addressOffset>
+     <fields>
+      <field>
+       <name>CACHE_EN</name>
+       <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Cache Enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>CACHE_RDY</name>
+       <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>notReady</name>
+         <description>Not Ready.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>ready</name>
+         <description>Ready.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INVALIDATE</name>
+     <description>Invalidate All Registers.</description>
+     <addressOffset>0x0700</addressOffset>
+     <access>read-write</access>
+    </register>
+   </registers>
+  </peripheral>
+<!--ICC0 Instruction Cache Controller Registers-->
+  <peripheral derivedFrom="ICC0">
+   <name>ICC1</name>
+   <description>Instruction Cache Controller Registers 1</description>
+   <baseAddress>0x4002F000</baseAddress>
+  </peripheral>
+<!--ICC1 Instruction Cache Controller Registers 1-->
+  <peripheral>
+   <name>PWRSEQ</name>
+   <description>Power Sequencer / Low Power Control Register.</description>
+   <baseAddress>0x40006800</baseAddress>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x800</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <registers>
+    <register>
+     <name>LP_CTRL</name>
+     <description>Low Power Control Register.</description>
+     <addressOffset>0x00</addressOffset>
+     <fields>
+      <field>
+       <name>RAMRET_SEL0</name>
+       <description>System RAM 0 Data retention in BACKUP mode. </description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RAMRET_SEL1</name>
+       <description>System RAM 1 Data retention in BACKUP mode. </description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RAMRET_SEL2</name>
+       <description>System RAM 2 Data retention in BACKUP mode. </description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RAMRET_SEL3</name>
+       <description>System RAM 3 Data retention in BACKUP mode. </description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>OVR</name>
+       <description>Operating Voltage Range</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>2</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>0_9V</name>
+         <description>0.9V 24MHz</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>1_0V</name>
+         <description>1.0V 48MHz</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>1_1V</name>
+         <description>1.1V 96MHz</description>
+         <value>2</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VCORE_DET_BYPASS</name>
+       <description>Bypass V CORE External Supply Detection</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>enabled</name>
+         <description>enable</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Disable</name>
+         <description>disable</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RETREG_EN</name>
+       <description>Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. </description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>FAST_WK_EN</name>
+       <description>Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. </description>
+       <bitOffset>10</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>BG_OFF</name>
+       <description>Band Gap Disable for DEEPSLEEP and BACKUP Mode</description>
+       <bitOffset>11</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>on</name>
+         <description>Bandgap is always ON.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>off</name>
+         <description>Bandgap is OFF in DeepSleep mode(default).</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VCORE_POR_DIS</name>
+       <description>V CORE POR Disable for DEEPSLEEP and BACKUP Mode</description>
+       <bitOffset>12</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>LDO_DIS</name>
+       <description>LDO Disable</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable if Bandgap is ON(default)</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VCORE_SVM_DIS</name>
+       <description>V CORE Supply Voltage Monitor Disable</description>
+       <bitOffset>20</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable if Bandgap is ON(default)</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VDDIO_POR_DIS</name>
+       <description>VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods.</description>
+       <bitOffset>25</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>LP_WAKEFL</name>
+     <description>Low Power Mode Wakeup Flags for GPIO0</description>
+     <addressOffset>0x04</addressOffset>
+     <fields>
+      <field>
+       <name>WAKEST</name>
+       <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>14</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>LPWK_EN</name>
+     <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description>
+     <addressOffset>0x08</addressOffset>
+     <fields>
+      <field>
+       <name>WAKEEN</name>
+       <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>14</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>LPMEMSD</name>
+     <description>Low Power Memory Shutdown Control.</description>
+     <addressOffset>0x40</addressOffset>
+     <fields>
+      <field>
+       <name>SRAM0_OFF</name>
+       <description>System RAM block 0 Shut Down.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>normal</name>
+         <description>Normal Operating Mode.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>shutdown</name>
+         <description>Shutdown Mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SRAM1_OFF</name>
+       <description>System RAM block 1 Shut Down.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>normal</name>
+         <description>Normal Operating Mode.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>shutdown</name>
+         <description>Shutdown Mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SRAM2_OFF</name>
+       <description>System RAM block 2 Shut Down.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>normal</name>
+         <description>Normal Operating Mode.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>shutdown</name>
+         <description>Shutdown Mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SRAM3_OFF</name>
+       <description>System RAM block 3 Shut Down.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>normal</name>
+         <description>Normal Operating Mode.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>shutdown</name>
+         <description>Shutdown Mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--PWRSEQ Power Sequencer / Low Power Control Register.-->
+  <peripheral>
+   <name>RTC</name>
+   <description>Real Time Clock and Alarm.</description>
+   <baseAddress>0x40006000</baseAddress>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x400</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <interrupt>
+    <name>RTC</name>
+    <description>RTC interrupt.</description>
+    <value>3</value>
+   </interrupt>
+   <registers>
+    <register>
+     <name>SEC</name>
+     <description>RTC Second Counter. This register contains the 32-bit second counter.</description>
+     <addressOffset>0x00</addressOffset>
+     <resetMask>0x00000000</resetMask>
+    </register>
+    <register>
+     <name>SSEC</name>
+     <description>RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00.</description>
+     <addressOffset>0x04</addressOffset>
+     <resetMask>0x00000000</resetMask>
+     <fields>
+      <field>
+       <name>RTSS</name>
+       <description>RTC Sub-second Counter.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>8</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>RAS</name>
+     <description>Time-of-day Alarm.</description>
+     <addressOffset>0x08</addressOffset>
+     <resetMask>0x00000000</resetMask>
+     <fields>
+      <field>
+       <name>RAS</name>
+       <description>Time-of-day Alarm.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>20</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>RSSA</name>
+     <description>RTC sub-second alarm.  This register contains the reload value for the sub-second alarm.</description>
+     <addressOffset>0x0C</addressOffset>
+     <resetMask>0x00000000</resetMask>
+     <fields>
+      <field>
+       <name>RSSA</name>
+       <description>This register contains the reload value for the sub-second alarm.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CTRL</name>
+     <description>RTC Control Register.</description>
+     <addressOffset>0x10</addressOffset>
+     <resetValue>0x00000008</resetValue>
+     <resetMask>0xFFFFFF38</resetMask>
+     <fields>
+      <field>
+       <name>RTCE</name>
+       <description>Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ADE</name>
+       <description>Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ASE</name>
+       <description>Alarm Sub-second Interrupt Enable.  Change to this bit is effective only after BUSY is cleared from 1 to 0.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>BUSY</name>
+       <description>RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place.  This bit is automatically cleared by hardware.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>idle</name>
+         <description>Idle.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>busy</name>
+         <description>Busy.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RDY</name>
+       <description>RTC Ready. This bit is set to 1 by hardware when the RTC count registers update.  It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>busy</name>
+         <description>Register has not updated.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>ready</name>
+         <description>Ready.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RDYE</name>
+       <description>RTC Ready Interrupt Enable.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ALDF</name>
+       <description>Time-of-Day Alarm Interrupt Flag.  This alarm is qualified as wake-up source to the processor.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>Not active</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Pending</name>
+         <description>Active</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ALSF</name>
+       <description>Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>Not active</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Pending</name>
+         <description>Active</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SQE</name>
+       <description>Square Wave Output Enable.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>Not active</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Pending</name>
+         <description>Active</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>FT</name>
+       <description>Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.</description>
+       <bitOffset>9</bitOffset>
+       <bitWidth>2</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>freq1Hz</name>
+         <description>1 Hz (Compensated).</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>freq512Hz</name>
+         <description>512 Hz (Compensated).</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>freq4KHz</name>
+         <description>4 KHz.</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>clkDiv8</name>
+         <description>RTC Input Clock / 8.</description>
+         <value>3</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>X32KMD</name>
+       <description>32KHz Oscillator Mode.</description>
+       <bitOffset>11</bitOffset>
+       <bitWidth>2</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noiseImmuneMode</name>
+         <description>Always operate in Noise Immune Mode.  Oscillator warm-up required.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>quietMode</name>
+         <description>Always operate in Quiet Mode.  No oscillator warm-up required.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>quietInStopWithWarmup</name>
+         <description>Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry.  Will wait for 32K oscillator warm-up before code execution on Stop Mode exit.</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>quietInStopNoWarmup</name>
+         <description>Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry.  Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit.</description>
+         <value>3</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>WE</name>
+       <description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.</description>
+       <bitOffset>15</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>Not active</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Pending</name>
+         <description>Active</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>TRIM</name>
+     <description>RTC Trim Register.</description>
+     <addressOffset>0x14</addressOffset>
+     <resetMask>0x00000000</resetMask>
+     <fields>
+      <field>
+       <name>TRIM</name>
+       <description>RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>8</bitWidth>
+      </field>
+      <field>
+       <name>VBATTMR</name>
+       <description>VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>24</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>OSCCTRL</name>
+     <description>RTC Oscillator Control Register.</description>
+     <addressOffset>0x18</addressOffset>
+     <resetMask>0x00000000</resetMask>
+     <fields>
+      <field>
+       <name>FLITER_EN</name>
+       <description>RTC Oscillator Filter Enable</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>IBIAS_SEL</name>
+       <description>RTC Oscillator 4X Bias Current Select</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>2X</name>
+         <description>Selects 2X bias current for RTC oscillator</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>4X</name>
+         <description>Selects 4X bias current for RTC oscillator</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>HYST_EN</name>
+       <description>RTC Oscillator Hysteresis Buffer Enable</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>IBIAS_EN</name>
+       <description>RTC Oscillator Bias Current Enable</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>BYPASS</name>
+       <description>RTC Crystal Bypass</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>OUT32K</name>
+       <description>RTC 32kHz Square Wave Output</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--RTC Real Time Clock and Alarm.-->
+  <peripheral>
+   <name>SIR</name>
+   <description>System Initialization Registers.</description>
+   <baseAddress>0x40000400</baseAddress>
+   <access>read-only</access>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x400</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <registers>
+    <register>
+     <name>SISTAT</name>
+     <description>System Initialization Status Register.</description>
+     <addressOffset>0x00</addressOffset>
+     <access>read-only</access>
+     <fields>
+      <field>
+       <name>MAGIC</name>
+       <description>Magic Word Validation.  This bit is set by the system initialization block following power-up.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>magicNotSet</name>
+         <description>Magic word was not set (OTP has not been initialized properly).</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>magicSet</name>
+         <description>Magic word was set (OTP contains valid settings).</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>CRCERR</name>
+       <description>CRC Error Status.  This bit is set by the system initialization block following power-up.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <usage>read</usage>
+        <enumeratedValue>
+         <name>noError</name>
+         <description>No CRC errors occurred during the read of the OTP memory block.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>error</name>
+         <description>A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>ERRADDR</name>
+     <description>Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description>
+     <addressOffset>0x04</addressOffset>
+     <access>read-only</access>
+     <fields>
+      <field>
+       <name>ERRADDR</name>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>FSTAT</name>
+     <description>funcstat register.</description>
+     <addressOffset>0x100</addressOffset>
+     <access>read-only</access>
+     <fields>
+      <field>
+       <name>FPU</name>
+       <description>FPU Function.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>USB</name>
+       <description>USB Device.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ADC</name>
+       <description>10-bit Sigma Delta ADC.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>XIP</name>
+       <description>XiP function.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>PBM</name>
+       <description>PBM function.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>HBC</name>
+       <description>HBC function.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SDHC</name>
+       <description>SDHC function.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SMPHR</name>
+       <description>SMPHR function.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SCACHE</name>
+       <description>System Cache function.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>SFSTAT</name>
+     <description>secfuncstat register.</description>
+     <addressOffset>0x104</addressOffset>
+     <access>read-only</access>
+     <fields>
+      <field>
+       <name>TRNG</name>
+       <description>TRNG function.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>AES</name>
+       <description>AES function.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SHA</name>
+       <description>SHA function.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>MAA</name>
+       <description>MAA function.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>no</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>yes</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--SIR System Initialization Registers.-->
+  <peripheral>
+   <name>SMON</name>
+   <description>The Security Monitor block used to monitor system threat conditions.</description>
+   <baseAddress>0x40004000</baseAddress>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x1000</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <registers>
+    <register>
+     <name>EXTSCN</name>
+     <description>External Sensor Control Register.</description>
+     <addressOffset>0x00</addressOffset>
+     <resetMask>0x3800FFC0</resetMask>
+     <fields>
+      <field>
+       <name>EXTS_EN0</name>
+       <description>External Sensor Enable for input/output pair 0.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTS_EN1</name>
+       <description>External Sensor Enable for input/output pair 1.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTS_EN2</name>
+       <description>External Sensor Enable for input/output pair 2.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTS_EN3</name>
+       <description>External Sensor Enable for input/output pair 3.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTS_EN4</name>
+       <description>External Sensor Enable for input/output pair 4.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTS_EN5</name>
+       <description>External Sensor Enable for input/output pair 5.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTCNT</name>
+       <description>External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>5</bitWidth>
+      </field>
+      <field>
+       <name>EXTFRQ</name>
+       <description>External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair.</description>
+       <bitOffset>21</bitOffset>
+       <bitWidth>3</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>freq2000Hz</name>
+         <description>Div 4 (2000Hz).</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>freq1000Hz</name>
+         <description>Div 8 (1000Hz).</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>freq500Hz</name>
+         <description>Div 16 (500Hz).</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>freq250Hz</name>
+         <description>Div 32 (250Hz).</description>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>freq125Hz</name>
+         <description>Div 64 (125Hz).</description>
+         <value>4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>freq63Hz</name>
+         <description>Div 128 (63Hz).</description>
+         <value>5</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>freq31Hz</name>
+         <description>Div 256 (31Hz).</description>
+         <value>6</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>RFU</name>
+         <description>Reserved. Do not use.</description>
+         <value>7</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>DIVCLK</name>
+       <description>Clock Divide.  These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor.</description>
+       <bitOffset>24</bitOffset>
+       <bitWidth>3</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>div1</name>
+         <description>Divide by 1 (8000 Hz).</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div2</name>
+         <description>Divide by 2 (4000 Hz).</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div4</name>
+         <description>Divide by 4 (2000 Hz).</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div8</name>
+         <description>Divide by 8 (1000 Hz).</description>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div16</name>
+         <description>Divide by 16 (500 Hz).</description>
+         <value>4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div32</name>
+         <description>Divide by 32 (250 Hz).</description>
+         <value>5</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div64</name>
+         <description>Divide by 64 (125 Hz).</description>
+         <value>6</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>BUSY</name>
+       <description>Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain.</description>
+       <bitOffset>30</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>idle</name>
+         <description>Idle.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>busy</name>
+         <description>Update in Progress.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>LOCK</name>
+       <description>Lock Register. Once locked, the EXTSCN register can no longer be modified.  Only a battery disconnect will clear this bit. VBAT powers this register.</description>
+       <bitOffset>31</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>unlocked</name>
+         <description>Unlocked.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>locked</name>
+         <description>Locked.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INTSCN</name>
+     <description>Internal Sensor Control Register.</description>
+     <addressOffset>0x04</addressOffset>
+     <resetMask>0x7F00FFF7</resetMask>
+     <fields>
+      <field>
+       <name>SHIELD_EN</name>
+       <description>Die Shield Enable.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TEMP_EN</name>
+       <description>Temperature Sensor Enable.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VBAT_EN</name>
+       <description>Battery Monitor Enable.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>LOTEMP_SEL</name>
+       <description>Low Temperature Detection Select.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>neg50C</name>
+         <description>-50 degrees C.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>neg30C</name>
+         <description>-30 degrees C.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VCORELOEN</name>
+       <description>VCORE Undervoltage Detect Enable.</description>
+       <bitOffset>18</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VCOREHIEN</name>
+       <description>VCORE Overvoltage Detect Enable.</description>
+       <bitOffset>19</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VDDLOEN</name>
+       <description>VDD Undervoltage Detect Enable.</description>
+       <bitOffset>20</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VDDHIEN</name>
+       <description>VDD Overvoltage Detect Enable.</description>
+       <bitOffset>21</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VGLEN</name>
+       <description>Voltage Glitch Detection Enable.</description>
+       <bitOffset>22</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>LOCK</name>
+       <description>Lock Register. Once locked, the INTSCN register can no longer be modified.  Only a battery disconnect will clear this bit. VBAT powers this register.</description>
+       <bitOffset>31</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>unlocked</name>
+         <description>Unlocked.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>locked</name>
+         <description>Locked.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>SECALM</name>
+     <description>Security Alarm Register.</description>
+     <addressOffset>0x08</addressOffset>
+     <resetValue>0x00000000</resetValue>
+     <resetMask>0x00000000</resetMask>
+     <fields>
+      <field>
+       <name>DRS</name>
+       <description>Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>complete</name>
+         <description>No operation/complete.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>start</name>
+         <description>Start operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>KEYWIPE</name>
+       <description>Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>complete</name>
+         <description>No operation/complete.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>start</name>
+         <description>Start operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SHIELDF</name>
+       <description>Die Shield Flag.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>LOTEMP</name>
+       <description>Low Temperature Detect.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>HITEMP</name>
+       <description>High Temperature Detect.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>BATLO</name>
+       <description>Battery Undervoltage Detect.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>BATHI</name>
+       <description>Battery Overvoltage Detect.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTF</name>
+       <description>External Sensor Flag.   This bit is set to 1 when any of the EXTSTAT bits are set.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VDDLO</name>
+       <description>VDD Undervoltage Detect Flag.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VCORELO</name>
+       <description>VCORE Undervoltage Detect Flag.</description>
+       <bitOffset>9</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VCOREHI</name>
+       <description>VCORE Overvoltage Detect Flag.</description>
+       <bitOffset>10</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VDDHI</name>
+       <description>VDD Overvoltage Flag.</description>
+       <bitOffset>11</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>VGL</name>
+       <description>Voltage Glitch Detection Flag.</description>
+       <bitOffset>12</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSTAT0</name>
+       <description>External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSTAT1</name>
+       <description>External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description>
+       <bitOffset>17</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSTAT2</name>
+       <description>External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description>
+       <bitOffset>18</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSTAT3</name>
+       <description>External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description>
+       <bitOffset>19</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSTAT4</name>
+       <description>External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description>
+       <bitOffset>20</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSTAT5</name>
+       <description>External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description>
+       <bitOffset>21</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSWARN0</name>
+       <description>External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description>
+       <bitOffset>24</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSWARN1</name>
+       <description>External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description>
+       <bitOffset>25</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSWARN2</name>
+       <description>External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description>
+       <bitOffset>26</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSWARN3</name>
+       <description>External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description>
+       <bitOffset>27</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSWARN4</name>
+       <description>External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description>
+       <bitOffset>28</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSWARN5</name>
+       <description>External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description>
+       <bitOffset>29</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>SECDIAG</name>
+     <description>Security Diagnostic Register.</description>
+     <addressOffset>0x0C</addressOffset>
+     <access>read-only</access>
+     <resetValue>0x00000001</resetValue>
+     <resetMask>0xFFC0FE02</resetMask>
+     <fields>
+      <field>
+       <name>BORF</name>
+       <description>Battery-On-Reset Flag. This bit is set once the back up battery is conneted.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SHIELDF</name>
+       <description>Die Shield Flag.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>LOTEMP</name>
+       <description>Low Temperature Detect.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>HITEMP</name>
+       <description>High Temperature Detect.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>BATLO</name>
+       <description>Battery Undervoltage Detect.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>BATHI</name>
+       <description>Battery Overvoltage Detect.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>DYNF</name>
+       <description>Dynamic Sensor Flag.  This bit is set to 1 when any of the EXTSTAT bits are set.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>AESKT</name>
+       <description>AES Key Transfer.  This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>incomplete</name>
+         <description>Key has not been transferred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>complete</name>
+         <description>Key has been transferred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSTAT0</name>
+       <description>External Sensor 0 Detect.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSTAT1</name>
+       <description>External Sensor 1 Detect.</description>
+       <bitOffset>17</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSTAT2</name>
+       <description>External Sensor 2 Detect.</description>
+       <bitOffset>18</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSTAT3</name>
+       <description>External Sensor 3 Detect.</description>
+       <bitOffset>19</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSTAT4</name>
+       <description>External Sensor 4 Detect.</description>
+       <bitOffset>20</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>EXTSTAT5</name>
+       <description>External Sensor 5 Detect.</description>
+       <bitOffset>21</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>DLRTC</name>
+     <description>DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred.</description>
+     <addressOffset>0x10</addressOffset>
+     <access>read-only</access>
+     <resetMask>0x00000000</resetMask>
+     <fields>
+      <field>
+       <name>DLRTC</name>
+       <description>DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>SECST</name>
+     <description>Security Monitor Status Register.</description>
+     <addressOffset>0x34</addressOffset>
+     <access>read-only</access>
+     <fields>
+      <field>
+       <name>EXTSRS</name>
+       <description>External Sensor Control Register Status.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>allowed</name>
+         <description>Access authorized.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>notAllowed</name>
+         <description>Access not authorized.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>INTSRS</name>
+       <description>Internal Sensor Control Register Status.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>allowed</name>
+         <description>Access authorized.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>notAllowed</name>
+         <description>Access not authorized.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SECALRS</name>
+       <description>Security Alarm Register Status.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>allowed</name>
+         <description>Access authorized.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>notAllowed</name>
+         <description>Access not authorized.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--SMON The Security Monitor block used to monitor system threat conditions.-->
+  <peripheral>
+   <name>SPI17Y</name>
+   <description>SPI peripheral.</description>
+   <baseAddress>0x40046000</baseAddress>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x1000</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <interrupt>
+    <name>SPI0</name>
+    <value>16</value>
+   </interrupt>
+   <registers>
+    <register>
+     <name>DATA32</name>
+     <description>Register for reading and writing the FIFO.</description>
+     <addressOffset>0x00</addressOffset>
+     <size>32</size>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>DATA</name>
+       <description>Read to pull from RX FIFO, write to put into TX FIFO.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>32</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <dim>2</dim>
+     <dimIncrement>2</dimIncrement>
+     <name>DATA16[%s]</name>
+     <description>Register for reading and writing the FIFO.</description>
+     <alternateRegister>DATA32</alternateRegister>
+     <addressOffset>0x00</addressOffset>
+     <size>16</size>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>DATA</name>
+       <description>Read to pull from RX FIFO, write to put into TX FIFO.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>16</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <dim>4</dim>
+     <dimIncrement>1</dimIncrement>
+     <name>DATA8[%s]</name>
+     <description>Register for reading and writing the FIFO.</description>
+     <alternateRegister>DATA32</alternateRegister>
+     <addressOffset>0x00</addressOffset>
+     <size>8</size>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>DATA</name>
+       <description>Read to pull from RX FIFO, write to put into TX FIFO.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>8</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CTRL0</name>
+     <description>Register for controlling SPI peripheral.</description>
+     <addressOffset>0x04</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>EN</name>
+       <description>SPI Enable.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>SPI is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>SPI is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>MASTER</name>
+       <description>Master Mode Enable.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>SPI is Slave mode.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>SPI is  Master mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SS_IO</name>
+       <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>output</name>
+         <description>Slave select 0 is output.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>input</name>
+         <description>Slave Select 0 is input, only valid if MMEN=1.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>START</name>
+       <description>Start Transmit.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>start</name>
+         <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SS_CTRL</name>
+       <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>DEASSERT</name>
+         <description>SPI De-asserts Slave Select at the end of a transaction.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>ASSERT</name>
+         <description>SPI leaves Slave Select asserted at the end of a transaction.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SS</name>
+       <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>4</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>SS0</name>
+         <description>SS0 is selected.</description>
+         <value>0x1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SS1</name>
+         <description>SS1 is selected.</description>
+         <value>0x2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SS2</name>
+         <description>SS2 is selected.</description>
+         <value>0x4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SS3</name>
+         <description>SS3 is selected.</description>
+         <value>0x8</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CTRL1</name>
+     <description>Register for controlling SPI peripheral.</description>
+     <addressOffset>0x08</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>TX_NUM_CHAR</name>
+       <description>Nubmer of Characters to transmit.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>16</bitWidth>
+      </field>
+      <field>
+       <name>RX_NUM_CHAR</name>
+       <description>Nubmer of Characters to receive.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>16</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CTRL2</name>
+     <description>Register for controlling SPI peripheral.</description>
+     <addressOffset>0x0C</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>CPHA</name>
+       <description>Clock Phase.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>Rising_Edge</name>
+         <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Falling_Edge</name>
+         <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>CPOL</name>
+       <description>Clock Polarity.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>Normal</name>
+         <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Inverted</name>
+         <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SCLK_INV</name>
+       <description>Reserved - Must Always Be Cleared to 0.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>NUMBITS</name>
+       <description>Number of Bits per character.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>4</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>0</name>
+         <description>16 bits per character.</description>
+         <value>0</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>DATA_WIDTH</name>
+       <description>SPI Data width.</description>
+       <bitOffset>12</bitOffset>
+       <bitWidth>2</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>Mono</name>
+         <description>1 data pin.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Dual</name>
+         <description>2 data pins.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>Quad</name>
+         <description>4 data pins.</description>
+         <value>2</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>THREE_WIRE</name>
+       <description>Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.</description>
+       <bitOffset>15</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Use four wire mode (Mono only).</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Use three wire mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SS_POL</name>
+       <description>Slave Select Polarity, each Slave Select can have unique polarity.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>8</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>SS0_high</name>
+         <description>SS0 active high.</description>
+         <value>0x1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SS1_high</name>
+         <description>SS1 active high.</description>
+         <value>0x2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SS2_high</name>
+         <description>SS2 active high.</description>
+         <value>0x4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SS3_high</name>
+         <description>SS3 active high.</description>
+         <value>0x8</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SRPOL</name>
+       <description>Slave Ready Polarity, each Slave Ready can have unique polarity.</description>
+       <bitOffset>24</bitOffset>
+       <bitWidth>8</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>SR0_high</name>
+         <description>SR0 active high.</description>
+         <value>0x1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SR1_high</name>
+         <description>SR1 active high.</description>
+         <value>0x2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SR2_high</name>
+         <description>SR2 active high.</description>
+         <value>0x4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SR3_high</name>
+         <description>SR3 active high.</description>
+         <value>0x8</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SR4_high</name>
+         <description>SR4 active high.</description>
+         <value>0x10</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SR5_high</name>
+         <description>SR5 active high.</description>
+         <value>0x20</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SR6_high</name>
+         <description>SR6 active high.</description>
+         <value>0x40</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SR7_high</name>
+         <description>SR7 active high.</description>
+         <value>0x80</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>SS_TIME</name>
+     <description>Register for controlling SPI peripheral/Slave Select Timing.</description>
+     <addressOffset>0x10</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>PRE</name>
+       <description>Slave Select Pre delay 1.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>8</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>256</name>
+         <description>256 system clocks between SS active and first serial clock edge.</description>
+         <value>0</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>POST</name>
+       <description>Slave Select Post delay 2.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>8</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>256</name>
+         <description>256 system clocks between last serial clock edge and SS inactive.</description>
+         <value>0</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>INACT</name>
+       <description>Slave Select Inactive delay.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>8</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>256</name>
+         <description>256 system clocks between transactions.</description>
+         <value>0</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CLK_CFG</name>
+     <description>Register for controlling SPI clock rate.</description>
+     <addressOffset>0x14</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>LO</name>
+       <description>Low duty cycle control. In timer mode, reload[7:0].</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>8</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>Dis</name>
+         <description>Duty cycle control of serial clock generation is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>HI</name>
+       <description>High duty cycle control. In timer mode, reload[15:8].</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>8</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>Dis</name>
+         <description>Duty cycle control of serial clock generation is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SCALE</name>
+       <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>4</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>DMA</name>
+     <description>Register for controlling DMA.</description>
+     <addressOffset>0x1C</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>TX_FIFO_LEVEL</name>
+       <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>5</bitWidth>
+      </field>
+      <field>
+       <name>TX_FIFO_EN</name>
+       <description>Transmit FIFO enabled for SPI transactions.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Transmit FIFO is not enabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Transmit FIFO is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_FIFO_CLEAR</name>
+       <description>Clear TX FIFO, clear is accomplished by resetting the read and write
+            pointers. This should be done when FIFO is not being accessed on the SPI side.
+          .</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>CLEAR</name>
+         <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_FIFO_CNT</name>
+       <description>Count of entries in TX FIFO.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>6</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>TX_DMA_EN</name>
+       <description>TX DMA Enable.</description>
+       <bitOffset>15</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>DIS</name>
+         <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>TX DMA requests are enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_FIFO_LEVEL</name>
+       <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>5</bitWidth>
+      </field>
+      <field>
+       <name>RX_FIFO_EN</name>
+       <description>Receive FIFO enabled for SPI transactions.</description>
+       <bitOffset>22</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>DIS</name>
+         <description>Receive FIFO is not enabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Receive FIFO is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_FIFO_CLEAR</name>
+       <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description>
+       <bitOffset>23</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>CLEAR</name>
+         <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_FIFO_CNT</name>
+       <description>Count of entries in RX FIFO.</description>
+       <bitOffset>24</bitOffset>
+       <bitWidth>6</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>RX_DMA_EN</name>
+       <description>RX DMA Enable.</description>
+       <bitOffset>31</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>RX DMA requests are enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_FL</name>
+     <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description>
+     <addressOffset>0x20</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>TX_THRESH</name>
+       <description>TX FIFO Threshold Crossed.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_EMPTY</name>
+       <description>TX FIFO Empty.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_THRESH</name>
+       <description>RX FIFO Threshold Crossed.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_FULL</name>
+       <description>RX FIFO FULL.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SSA</name>
+       <description>Slave Select Asserted.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SSD</name>
+       <description>Slave Select Deasserted.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>FAULT</name>
+       <description>Multi-Master Mode Fault.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ABORT</name>
+       <description>Slave Abort Detected.</description>
+       <bitOffset>9</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>M_DONE</name>
+       <description>Master Done, set when SPI Master has completed any transactions.</description>
+       <bitOffset>11</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_OVR</name>
+       <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description>
+       <bitOffset>12</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_UND</name>
+       <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description>
+       <bitOffset>13</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_OVR</name>
+       <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description>
+       <bitOffset>14</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_UND</name>
+       <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description>
+       <bitOffset>15</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_EN</name>
+     <description>Register for enabling interrupts.</description>
+     <addressOffset>0x24</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>TX_THRESH</name>
+       <description>TX FIFO Threshold interrupt enable.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_EMPTY</name>
+       <description>TX FIFO Empty interrupt enable.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_THRESH</name>
+       <description>RX FIFO Threshold Crossed interrupt enable.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_FULL</name>
+       <description>RX FIFO FULL interrupt enable.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SSA</name>
+       <description>Slave Select Asserted interrupt enable.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SSD</name>
+       <description>Slave Select Deasserted interrupt enable.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>FAULT</name>
+       <description>Multi-Master Mode Fault interrupt enable.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ABORT</name>
+       <description>Slave Abort Detected interrupt enable.</description>
+       <bitOffset>9</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>M_DONE</name>
+       <description>Master Done interrupt enable.</description>
+       <bitOffset>11</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_OVR</name>
+       <description>Transmit FIFO Overrun interrupt enable.</description>
+       <bitOffset>12</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_UND</name>
+       <description>Transmit FIFO Underrun interrupt enable.</description>
+       <bitOffset>13</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_OVR</name>
+       <description>Receive FIFO Overrun interrupt enable.</description>
+       <bitOffset>14</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_UND</name>
+       <description>Receive FIFO Underrun interrupt enable.</description>
+       <bitOffset>15</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Interrupt is disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Interrupt is enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>WAKE_FL</name>
+     <description>Register for wake up flags. All bits in this register are write 1 to clear.</description>
+     <addressOffset>0x28</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>TX_THRESH</name>
+       <description>Wake on TX FIFO Threshold Crossed.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_EMPTY</name>
+       <description>Wake on TX FIFO Empty.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_THRESH</name>
+       <description>Wake on RX FIFO Threshold Crossed.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_FULL</name>
+       <description>Wake on RX FIFO Full.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>clear</name>
+         <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>WAKE_EN</name>
+     <description>Register for wake up enable.</description>
+     <addressOffset>0x2C</addressOffset>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>TX_THRESH</name>
+       <description>Wake on TX FIFO Threshold Crossed Enable.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Wakeup source disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Wakeup source enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_EMPTY</name>
+       <description>Wake on TX FIFO Empty Enable.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Wakeup source disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Wakeup source enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_THRESH</name>
+       <description>Wake on RX FIFO Threshold Crossed Enable.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Wakeup source disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Wakeup source enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_FULL</name>
+       <description>Wake on RX FIFO Full Enable.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Wakeup source disabled.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Wakeup source enabled.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>STAT</name>
+     <description>SPI Status register.</description>
+     <addressOffset>0x30</addressOffset>
+     <access>read-only</access>
+     <fields>
+      <field>
+       <name>BUSY</name>
+       <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>not</name>
+         <description>SPI not active.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>active</name>
+         <description>SPI active.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--SPI17Y SPI peripheral.-->
+  <peripheral>
+   <name>SPIMSS</name>
+   <description>Serial Peripheral Interface.</description>
+   <prependToName>SPIMSS0_</prependToName>
+   <baseAddress>0x40018000</baseAddress>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x1000</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <registers>
+    <register>
+     <name>DATA16</name>
+     <description>SPI 16-bit Data Access</description>
+     <addressOffset>0x00</addressOffset>
+     <size>16</size>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>DATA</name>
+       <description>SPI data.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>16</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <dim>2</dim>
+     <dimIncrement>1</dimIncrement>
+     <name>DATA8[%s]</name>
+     <description>SPI Data 8-bit access</description>
+     <alternateRegister>DATA16</alternateRegister>
+     <addressOffset>0x00</addressOffset>
+     <size>8</size>
+     <access>read-write</access>
+     <fields>
+      <field>
+       <name>DATA</name>
+       <description>SPI data.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>8</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CTRL</name>
+     <description>SPI Control Register.</description>
+     <addressOffset>0x04</addressOffset>
+     <fields>
+      <field>
+       <name>SPIEN</name>
+       <description>SPI Enable.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>dis_en_enum</name>
+        <enumeratedValue>
+         <name>disable</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>enable</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>MMEN</name>
+       <description>SPI Master Mode Enable.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>slv_mst_enum</name>
+        <enumeratedValue>
+         <name>slave</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>master</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>WOR</name>
+       <description>Wired OR (open drain) Enable.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>dis_en_enum</name>
+        <enumeratedValue>
+         <name>disable</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>enable</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>CLKPOL</name>
+       <description>Clock Polarity.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>spi_pol_enum</name>
+        <enumeratedValue>
+         <name>idleLo</name>
+         <description>SCLK idles Low (0) after character transmission/reception.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>idleHi</name>
+         <description>SCLK idles High (1) after character transmission/reception.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>PHASE</name>
+       <description>Phase Select.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>spi_phase_enum</name>
+        <enumeratedValue>
+         <name>activeEdge</name>
+         <description>Transmit on active edge of SCLK.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>inactiveEdge</name>
+         <description>Transmit on inactive edge of SCLK.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>BIRQ</name>
+       <description>Baud Rate Generator Timer Interrupt Request.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>dis_en_enum</name>
+        <enumeratedValue>
+         <name>disable</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>enable</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>STR</name>
+       <description>Start SPI Interrupt.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>start_op_enum</name>
+        <enumeratedValue>
+         <name>complete</name>
+         <description>No operation/complete.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>start</name>
+         <description>Start operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>IRQE</name>
+       <description>Interrupt Request Enable.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>dis_en_enum</name>
+        <enumeratedValue>
+         <name>disable</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>enable</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>STATUS</name>
+     <description>SPI Status Register.</description>
+     <addressOffset>0x08</addressOffset>
+     <resetValue>0x00000001</resetValue>
+     <fields>
+      <field>
+       <name>SLAS</name>
+       <description>Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <name>sel_enum</name>
+        <enumeratedValue>
+         <name>selected</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>notSelected</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TXST</name>
+       <description>Transmit Status.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+       <enumeratedValues>
+        <name>busy_enum</name>
+        <enumeratedValue>
+         <name>idle</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>busy</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TUND</name>
+       <description>Transmit Underrun.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <modifiedWriteValues>oneToClear</modifiedWriteValues>
+       <enumeratedValues>
+        <name>event_flag_enum</name>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ROVR</name>
+       <description>Receive Overrun.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>event_flag_enum</name>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>ABT</name>
+       <description>Slave Mode Transaction Abort.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>event_flag_enum</name>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>COL</name>
+       <description>Collision.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>event_flag_enum</name>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TOVR</name>
+       <description>Transmit Overrun.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>event_flag_enum</name>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>IRQ</name>
+       <description>SPI Interrupt Request.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <modifiedWriteValues>oneToClear</modifiedWriteValues>
+       <enumeratedValues>
+        <name>flag_enum</name>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No interrupt is pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>MOD</name>
+     <description>SPI Mode Register.</description>
+     <addressOffset>0x0C</addressOffset>
+     <fields>
+      <field>
+       <name>SSV</name>
+       <description>Slave Select Value.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>lo_hi_enum</name>
+        <enumeratedValue>
+         <name>lo</name>
+         <description>The SSEL pin will be driven low.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>hi</name>
+         <description>The SSEL pin will be driven high.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SSIO</name>
+       <description>Slave Select I/O.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>input_output_enum</name>
+        <enumeratedValue>
+         <name>input</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>output</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>NUMBITS</name>
+       <bitOffset>2</bitOffset>
+       <bitWidth>4</bitWidth>
+       <enumeratedValues>
+        <name>spi_bits_enum</name>
+        <enumeratedValue>
+         <name>bits16</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits1</name>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits2</name>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits3</name>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits4</name>
+         <value>4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits5</name>
+         <value>5</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits6</name>
+         <value>6</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits7</name>
+         <value>7</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits8</name>
+         <value>8</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits9</name>
+         <value>9</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits10</name>
+         <value>10</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits11</name>
+         <value>11</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits12</name>
+         <value>12</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits13</name>
+         <value>13</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits14</name>
+         <value>14</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>bits15</name>
+         <value>15</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_LJ</name>
+       <description>Transmit Left Justify.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>dis_en_enum</name>
+        <enumeratedValue>
+         <name>disable</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>enable</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SSL1</name>
+       <description>Slave Select 1.  If SPI is enabled and in master mode, the SSEL_1 is driven according to this bit.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>hi_lo_enum</name>
+        <enumeratedValue>
+         <name>hi</name>
+         <description>High.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>lo</name>
+         <description>Low.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SSL2</name>
+       <description>Slave Select 2.  If SPI is enabled and in master mode, the SSEL_2 is driven according to this bit.</description>
+       <bitOffset>9</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>hi_lo_enum</name>
+        <enumeratedValue>
+         <name>hi</name>
+         <description>High.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>lo</name>
+         <description>Low.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>SSL3</name>
+       <description>Slave Select 3.  If SPI is enabled and in master mode, the SSEL_3 is driven according to this bit.</description>
+       <bitOffset>10</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>hi_lo_enum</name>
+        <enumeratedValue>
+         <name>hi</name>
+         <description>High.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>lo</name>
+         <description>Low.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>BRG</name>
+     <description>Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4).</description>
+     <addressOffset>0x14</addressOffset>
+     <resetValue>0x0000FFFF</resetValue>
+     <fields>
+      <field>
+       <name>BRG</name>
+       <description>Baud Rate Reload Value.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>16</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>DMA</name>
+     <description>SPI DMA Register.</description>
+     <addressOffset>0x18</addressOffset>
+     <resetValue>0x00070007</resetValue>
+     <fields>
+      <field>
+       <name>TX_FIFO_LEVEL</name>
+       <description>Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>3</bitWidth>
+       <enumeratedValues>
+        <name>fifo_level_enum</name>
+        <enumeratedValue>
+         <name>entry1</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries2</name>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries3</name>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries4</name>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries5</name>
+         <value>4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries6</name>
+         <value>5</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries7</name>
+         <value>6</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries8</name>
+         <value>7</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_FIFO_CLEAR</name>
+       <description>Transmit FIFO Clear.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>write-only</access>
+       <enumeratedValues>
+        <name>start_op_enum</name>
+        <enumeratedValue>
+         <name>complete</name>
+         <description>No operation/complete.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>start</name>
+         <description>Start operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_FIFO_CNT</name>
+       <description>Transmit FIFO Count.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>4</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>TX_DMA_EN</name>
+       <description>Transmit DMA Enable.</description>
+       <bitOffset>15</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>dis_en_enum</name>
+        <enumeratedValue>
+         <name>disable</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>enable</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_FIFO_LEVEL</name>
+       <description>Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>3</bitWidth>
+       <enumeratedValues>
+        <name>fifo_level_enum</name>
+        <enumeratedValue>
+         <name>entry1</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries2</name>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries3</name>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries4</name>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries5</name>
+         <value>4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries6</name>
+         <value>5</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries7</name>
+         <value>6</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>entries8</name>
+         <value>7</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_FIFO_CLEAR</name>
+       <description>Receive FIFO Clear.</description>
+       <bitOffset>20</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>start_op_enum</name>
+        <enumeratedValue>
+         <name>complete</name>
+         <description>No operation/complete.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>start</name>
+         <description>Start operation.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_FIFO_CNT</name>
+       <description>Receive FIFO Count.</description>
+       <bitOffset>24</bitOffset>
+       <bitWidth>4</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>RX_DMA_EN</name>
+       <description>Receive DMA Enable.</description>
+       <bitOffset>31</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>dis_en_enum</name>
+        <enumeratedValue>
+         <name>disable</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>enable</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>I2S_CTRL</name>
+     <description>I2S Control Register.</description>
+     <addressOffset>0x1C</addressOffset>
+     <fields>
+      <field>
+       <name>I2S_EN</name>
+       <description>I2S Mode Enable.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <name>dis_en_enum</name>
+        <enumeratedValue>
+         <name>disable</name>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>enable</name>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>I2S_MUTE</name>
+       <description>I2S Mute transmit.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>normal</name>
+         <description>Normal Transmit.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>replaced</name>
+         <description>Transmit data is replaced with 0.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>I2S_PAUSE</name>
+       <description>I2S Pause transmit/receive.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>normal</name>
+         <description>Normal Transmit.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>halt</name>
+         <description>Halt transmit and receive FIFO and DMA access, transmit 0's.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>I2S_MONO</name>
+       <description>I2S Monophonic Audio Mode.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>stereophonic</name>
+         <description>Stereophonic audio.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>monophonic</name>
+         <description>Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>I2S_LJ</name>
+       <description>I2S Left Justify.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>normal</name>
+         <description>Normal I2S audio protocol.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>replaced</name>
+         <description>Audio data is synchronized with SSEL.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--SPIMSS Serial Peripheral Interface.-->
+  <peripheral>
+   <name>TMR0</name>
+   <description>32-bit reloadable timer that can be used for timing and event counting.</description>
+   <groupName>Timers</groupName>
+   <baseAddress>0x40010000</baseAddress>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x1000</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <interrupt>
+    <name>TMR0</name>
+    <description>TMR0 IRQ</description>
+    <value>5</value>
+   </interrupt>
+   <registers>
+    <register>
+     <name>CNT</name>
+     <description>Count.  This register stores the current timer count.</description>
+     <addressOffset>0x00</addressOffset>
+     <resetValue>0x00000001</resetValue>
+    </register>
+    <register>
+     <name>CMP</name>
+     <description>Compare.  This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.</description>
+     <addressOffset>0x04</addressOffset>
+     <resetValue>0x0000FFFF</resetValue>
+    </register>
+    <register>
+     <name>PWM</name>
+     <description>PWM.  This register stores the value that is compared to the current timer count.</description>
+     <addressOffset>0x08</addressOffset>
+    </register>
+    <register>
+     <name>INTR</name>
+     <description>Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.</description>
+     <addressOffset>0x0C</addressOffset>
+     <modifiedWriteValues>oneToClear</modifiedWriteValues>
+     <fields>
+      <field>
+       <name>IRQ_CLR</name>
+       <description>Clear Interrupt.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>CN</name>
+     <description>Timer Control Register.</description>
+     <addressOffset>0x10</addressOffset>
+     <fields>
+      <field>
+       <name>TMODE</name>
+       <description>Timer Mode.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>3</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>oneShot</name>
+         <description>One Shot Mode.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>continuous</name>
+         <description>Continuous Mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>counter</name>
+         <description>Counter Mode.</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pwm</name>
+         <description>PWM Mode.</description>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>capture</name>
+         <description>Capture Mode.</description>
+         <value>4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>compare</name>
+         <description>Compare Mode.</description>
+         <value>5</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>gated</name>
+         <description>Gated Mode.</description>
+         <value>6</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>captureCompare</name>
+         <description>Capture/Compare Mode.</description>
+         <value>7</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>PRES</name>
+       <description>Prescaler.  Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>3</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>div1</name>
+         <description>Divide by 1.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div2</name>
+         <description>Divide by 2.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div4</name>
+         <description>Divide by 4.</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div8</name>
+         <description>Divide by 8.</description>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div16</name>
+         <description>Divide by 16.</description>
+         <value>4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div32</name>
+         <description>Divide by 32.</description>
+         <value>5</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div64</name>
+         <description>Divide by 64.</description>
+         <value>6</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>div128</name>
+         <description>Divide by 128.</description>
+         <value>7</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TPOL</name>
+       <description>Timer input/output polarity bit.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>activeHi</name>
+         <description>Active High.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>activeLo</name>
+         <description>Active Low.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TEN</name>
+       <description>Timer Enable.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>PRES3</name>
+       <description>MSB of prescaler value.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>PWMSYNC</name>
+       <description>Timer PWM Synchronization Mode Enable.</description>
+       <bitOffset>9</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>NOLHPOL</name>
+       <description>Timer PWM output 0A polarity bit.</description>
+       <bitOffset>10</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>NOLLPOL</name>
+       <description>Timer PWM output 0A' polarity bit.</description>
+       <bitOffset>11</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>PWMCKBD</name>
+       <description>Timer PWM output 0A Mode Disable.</description>
+       <bitOffset>12</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>0</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>NOLCMP</name>
+     <description>Timer Non-Overlapping Compare Register.</description>
+     <addressOffset>0x14</addressOffset>
+     <fields>
+      <field>
+       <name>NOLLCMP</name>
+       <description>Non-overlapping Low Compare.  The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>8</bitWidth>
+      </field>
+      <field>
+       <name>NOLHCMP</name>
+       <description>Non-overlapping High Compare.  The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>8</bitWidth>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--TMR0 32-bit reloadable timer that can be used for timing and event counting.-->
+  <peripheral derivedFrom="TMR0">
+   <name>TMR1</name>
+   <description>32-bit reloadable timer that can be used for timing and event counting. 1</description>
+   <baseAddress>0x40011000</baseAddress>
+   <interrupt>
+    <name>TMR1</name>
+    <description>TMR1 IRQ</description>
+    <value>6</value>
+   </interrupt>
+  </peripheral>
+<!--TMR1 32-bit reloadable timer that can be used for timing and event counting. 1-->
+  <peripheral derivedFrom="TMR0">
+   <name>TMR2</name>
+   <description>32-bit reloadable timer that can be used for timing and event counting. 2</description>
+   <baseAddress>0x40012000</baseAddress>
+   <interrupt>
+    <name>TMR2</name>
+    <description>TMR2 IRQ</description>
+    <value>7</value>
+   </interrupt>
+  </peripheral>
+<!--TMR2 32-bit reloadable timer that can be used for timing and event counting. 2-->
+  <peripheral>
+   <name>UART0</name>
+   <description>UART</description>
+   <baseAddress>0x40042000</baseAddress>
+   <addressBlock>
+    <offset>0</offset>
+    <size>0x1000</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <interrupt>
+    <name>UART0</name>
+    <description>UART0 IRQ</description>
+    <value>14</value>
+   </interrupt>
+   <registers>
+    <register>
+     <name>CTRL</name>
+     <description>Control Register.</description>
+     <addressOffset>0x00</addressOffset>
+     <size>32</size>
+     <fields>
+      <field>
+       <name>ENABLE</name>
+       <description>UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>UART disabled. FIFOs are flushed. Clock is gated off for power savings. </description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>UART enabled. </description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>PARITY_EN</name>
+       <description>Enable/disable Parity bit (9th character).</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>No Parity </description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Parity enabled as 9th bit</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>PARITY</name>
+       <description>When PARITY_EN=1, selects odd, even, Mark or Space parity.
+            Mark parity = always 1; Space parity = always 0.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>2</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>Even</name>
+         <description>Even parity selected.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>ODD</name>
+         <description>Odd parity selected.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>MARK</name>
+         <description>Mark parity selected.</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>SPACE</name>
+         <description>Space parity selected.</description>
+         <value>3</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>PARMD</name>
+       <description>Selects parity based on 1s or 0s count (when PARITY_EN=1).</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>1</name>
+         <description>Parity calculation is based on number of 1s in frame.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>0</name>
+         <description>Parity calculation is based on number of 0s in frame.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TX_FLUSH</name>
+       <description>Flushes the TX FIFO buffer.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>RX_FLUSH</name>
+       <description>Flushes the RX FIFO buffer.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>BITACC</name>
+       <description>If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>FRAME</name>
+         <description>Frame accuracy.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>BIT</name>
+         <description>Bit accuracy.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>CHAR_SIZE</name>
+       <description>Selects UART character size.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>2</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>5</name>
+         <description>5 bits.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>6</name>
+         <description>6 bits.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>7</name>
+         <description>7 bits.</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>8</name>
+         <description>8 bits.</description>
+         <value>3</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>STOPBITS</name>
+       <description>Selects the number of stop bits that will be generated.</description>
+       <bitOffset>10</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>1</name>
+         <description>1 stop bit.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>1_5</name>
+         <description>1.5 stop bits.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>FLOW_CTRL</name>
+       <description>Enables/disables hardware flow control.</description>
+       <bitOffset>11</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>en</name>
+         <description>HW Flow Control with RTS/CTS enabled</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>HW Flow Control disabled</description>
+         <value>0</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>FLOW_POL</name>
+       <description>RTS/CTS polarity.</description>
+       <bitOffset>12</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>0</name>
+         <description>RTS/CTS asserted is logic 0.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>1</name>
+         <description>RTS/CTS asserted is logic 1.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>NULL_MODEM</name>
+       <description>NULL Modem Support (RTS/CTS and TXD/RXD swap).</description>
+       <bitOffset>13</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>DIS</name>
+         <description>Direct convention.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>EN</name>
+         <description>Null Modem Mode.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>BREAK</name>
+       <description>Break control bit. It causes a break condition to be transmitted to receiving UART.</description>
+       <bitOffset>14</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>DIS</name>
+         <description>Break characters are not generated.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>EN</name>
+         <description>Break characters are sent(all the bits are at '0' including start/parity/stop).</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>CLKSEL</name>
+       <description>Baud Rate Clock Source Select.  Selects the baud rate clock.</description>
+       <bitOffset>15</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>SYSTEM</name>
+         <description>System clock.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>ALTERNATE</name>
+         <description>Alternate 7.3727MHz internal clock.  Useful in low power modes when the system clock is slow.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RX_TO</name>
+       <description>RX Time Out. RX time out interrupt will occur after RXTO Uart
+              characters if RX-FIFO is not empty and RX FIFO has not been read.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>8</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>THRESH_CTRL</name>
+     <description>Threshold Control register.</description>
+     <addressOffset>0x04</addressOffset>
+     <size>32</size>
+     <fields>
+      <field>
+       <name>RX_FIFO_THRESH</name>
+       <description>RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>6</bitWidth>
+      </field>
+      <field>
+       <name>TX_FIFO_THRESH</name>
+       <description>TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>6</bitWidth>
+      </field>
+      <field>
+       <name>RTS_FIFO_THRESH</name>
+       <description>RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>6</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>STATUS</name>
+     <description>Status Register.</description>
+     <addressOffset>0x08</addressOffset>
+     <size>32</size>
+     <access>read-only</access>
+     <fields>
+      <field>
+       <name>TX_BUSY</name>
+       <description>Read-only flag indicating the UART transmit status.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>RX_BUSY</name>
+       <description>Read-only flag indicating the UARTreceiver status.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>PARITY</name>
+       <description>9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>BREAK</name>
+       <description>Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>RX_EMPTY</name>
+       <description>Read-only flag indicating the RX FIFO state.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>RX_FULL</name>
+       <description>Read-only flag indicating the RX FIFO state.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>TX_EMPTY</name>
+       <description>Read-only flag indicating the TX FIFO state.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>TX_FULL</name>
+       <description>Read-only flag indicating the TX FIFO state.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>RX_FIFO_CNT</name>
+       <description>Indicates the number of bytes currently in the RX FIFO.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>6</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>TX_FIFO_CNT</name>
+       <description>Indicates the number of bytes currently in the TX FIFO.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>6</bitWidth>
+       <access>read-only</access>
+      </field>
+      <field>
+       <name>RX_TO</name>
+       <description>RX Timeout status.</description>
+       <bitOffset>24</bitOffset>
+       <bitWidth>1</bitWidth>
+       <access>read-only</access>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_EN</name>
+     <description>Interrupt Enable Register.</description>
+     <addressOffset>0x0C</addressOffset>
+     <size>32</size>
+     <fields>
+      <field>
+       <name>RX_FRAME_ERROR</name>
+       <description>Enable for RX Frame Error Interrupt.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>RX_PARITY_ERROR</name>
+       <description>Enable for RX Parity Error interrupt.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>CTS_CHANGE</name>
+       <description>Enable for CTS signal change interrupt.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>RX_OVERRUN</name>
+       <description>Enable for RX FIFO OVerrun interrupt.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>RX_FIFO_THRESH</name>
+       <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>TX_FIFO_ALMOST_EMPTY</name>
+       <description>Enable for interrupt when TX FIFO has only one byte remaining.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>TX_FIFO_THRESH</name>
+       <description>Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>BREAK</name>
+       <description>Enable for received BREAK character interrupt.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>RX_TIMEOUT</name>
+       <description>Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>LAST_BREAK</name>
+       <description>Enable for Last break character interrupt.</description>
+       <bitOffset>9</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>INT_FL</name>
+     <description>Interrupt Status Flags.</description>
+     <addressOffset>0x10</addressOffset>
+     <size>32</size>
+     <modifiedWriteValues>oneToClear</modifiedWriteValues>
+     <fields>
+      <field>
+       <name>RX_FRAME_ERROR</name>
+       <description>FLAG for RX Frame Error Interrupt.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>RX_PARITY_ERROR</name>
+       <description>FLAG for RX Parity Error interrupt.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>CTS_CHANGE</name>
+       <description>FLAG for CTS signal change interrupt.</description>
+       <bitOffset>2</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>RX_OVERRUN</name>
+       <description>FLAG for RX FIFO Overrun interrupt.</description>
+       <bitOffset>3</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>RX_FIFO_THRESH</name>
+       <description>FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>TX_FIFO_ALMOST_EMPTY</name>
+       <description>FLAG for interrupt when TX FIFO has only one byte remaining.</description>
+       <bitOffset>5</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>TX_FIFO_THRESH</name>
+       <description>FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.</description>
+       <bitOffset>6</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>BREAK</name>
+       <description>FLAG for received BREAK character interrupt.</description>
+       <bitOffset>7</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>RX_TIMEOUT</name>
+       <description>FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+      <field>
+       <name>LAST_BREAK</name>
+       <description>FLAG for Last break character interrupt.</description>
+       <bitOffset>9</bitOffset>
+       <bitWidth>1</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>BAUD0</name>
+     <description>Baud rate register. Integer portion.</description>
+     <addressOffset>0x14</addressOffset>
+     <size>32</size>
+     <fields>
+      <field>
+       <name>IBAUD</name>
+       <description>Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>12</bitWidth>
+      </field>
+      <field>
+       <name>FACTOR</name>
+       <description>FACTOR must be chosen to have IDIV&gt;0. factor used in calculation = 128 &gt;&gt; FACTOR.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>2</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>128</name>
+         <description>Baud Factor 128</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>64</name>
+         <description>Baud Factor 64</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>32</name>
+         <description>Baud Factor 32</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>16</name>
+         <description>Baud Factor 16</description>
+         <value>3</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>BAUD1</name>
+     <description>Baud rate register. Decimal Setting.</description>
+     <addressOffset>0x18</addressOffset>
+     <size>32</size>
+     <fields>
+      <field>
+       <name>DBAUD</name>
+       <description>Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>12</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>FIFO</name>
+     <description>FIFO Data buffer.</description>
+     <addressOffset>0x1C</addressOffset>
+     <size>32</size>
+     <fields>
+      <field>
+       <name>FIFO</name>
+       <description>Load/unload location for TX and RX FIFO buffers.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>8</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>DMA</name>
+     <description>DMA Configuration.</description>
+     <addressOffset>0x20</addressOffset>
+     <size>32</size>
+     <fields>
+      <field>
+       <name>TDMA_EN</name>
+       <description>TX DMA channel enable.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>DMA is disabled </description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>DMA is enabled </description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RXDMA_EN</name>
+       <description>RX DMA channel enable.</description>
+       <bitOffset>1</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>DMA is disabled </description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>DMA is enabled </description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>TXDMA_LEVEL</name>
+       <description>TX threshold for DMA transmission.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>6</bitWidth>
+      </field>
+      <field>
+       <name>RXDMA_LEVEL</name>
+       <description>RX threshold for DMA transmission.</description>
+       <bitOffset>16</bitOffset>
+       <bitWidth>6</bitWidth>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>TX_FIFO</name>
+     <description>Transmit FIFO Status register.</description>
+     <addressOffset>0x24</addressOffset>
+     <size>32</size>
+     <fields>
+      <field>
+       <name>DATA</name>
+       <description>Reading from this field returns the next character available at the
+              output of the TX FIFO (if one is available, otherwise 00h is returned).</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>7</bitWidth>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--UART0 UART-->
+  <peripheral derivedFrom="UART0">
+   <name>UART1</name>
+   <description>UART 1</description>
+   <baseAddress>0x40043000</baseAddress>
+   <interrupt>
+    <name>UART1</name>
+    <description>UART1 IRQ</description>
+    <value>15</value>
+   </interrupt>
+  </peripheral>
+<!--UART1 UART 1-->
+  <peripheral>
+   <name>WDT0</name>
+   <description>Watchdog Timer 0</description>
+   <baseAddress>0x40003000</baseAddress>
+   <addressBlock>
+    <offset>0x00</offset>
+    <size>0x0400</size>
+    <usage>registers</usage>
+   </addressBlock>
+   <interrupt>
+    <name>WDT0</name>
+    <value>1</value>
+   </interrupt>
+   <registers>
+    <register>
+     <name>CTRL</name>
+     <description>Watchdog Timer Control Register.</description>
+     <addressOffset>0x00</addressOffset>
+     <resetMask>0x7FFFF000</resetMask>
+     <fields>
+      <field>
+       <name>INT_PERIOD</name>
+       <description>Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>4</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>wdt2pow31</name>
+         <description>2**31 clock cycles.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow30</name>
+         <description>2**30 clock cycles.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow29</name>
+         <description>2**29 clock cycles.</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow28</name>
+         <description>2**28 clock cycles.</description>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow27</name>
+         <description>2^27 clock cycles.</description>
+         <value>4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow26</name>
+         <description>2**26 clock cycles.</description>
+         <value>5</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow25</name>
+         <description>2**25 clock cycles.</description>
+         <value>6</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow24</name>
+         <description>2**24 clock cycles.</description>
+         <value>7</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow23</name>
+         <description>2**23 clock cycles.</description>
+         <value>8</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow22</name>
+         <description>2**22 clock cycles.</description>
+         <value>9</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow21</name>
+         <description>2**21 clock cycles.</description>
+         <value>10</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow20</name>
+         <description>2**20 clock cycles.</description>
+         <value>11</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow19</name>
+         <description>2**19 clock cycles.</description>
+         <value>12</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow18</name>
+         <description>2**18 clock cycles.</description>
+         <value>13</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow17</name>
+         <description>2**17 clock cycles.</description>
+         <value>14</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow16</name>
+         <description>2**16 clock cycles.</description>
+         <value>15</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RST_PERIOD</name>
+       <description>Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description>
+       <bitOffset>4</bitOffset>
+       <bitWidth>4</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>wdt2pow31</name>
+         <description>2**31 clock cycles.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow30</name>
+         <description>2**30 clock cycles.</description>
+         <value>1</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow29</name>
+         <description>2**29 clock cycles.</description>
+         <value>2</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow28</name>
+         <description>2**28 clock cycles.</description>
+         <value>3</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow27</name>
+         <description>2^27 clock cycles.</description>
+         <value>4</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow26</name>
+         <description>2**26 clock cycles.</description>
+         <value>5</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow25</name>
+         <description>2**25 clock cycles.</description>
+         <value>6</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow24</name>
+         <description>2**24 clock cycles.</description>
+         <value>7</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow23</name>
+         <description>2**23 clock cycles.</description>
+         <value>8</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow22</name>
+         <description>2**22 clock cycles.</description>
+         <value>9</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow21</name>
+         <description>2**21 clock cycles.</description>
+         <value>10</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow20</name>
+         <description>2**20 clock cycles.</description>
+         <value>11</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow19</name>
+         <description>2**19 clock cycles.</description>
+         <value>12</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow18</name>
+         <description>2**18 clock cycles.</description>
+         <value>13</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow17</name>
+         <description>2**17 clock cycles.</description>
+         <value>14</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>wdt2pow16</name>
+         <description>2**16 clock cycles.</description>
+         <value>15</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>WDT_EN</name>
+       <description>Watchdog Timer Enable.</description>
+       <bitOffset>8</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>INT_FLAG</name>
+       <description>Watchdog Timer Interrupt Flag.</description>
+       <bitOffset>9</bitOffset>
+       <bitWidth>1</bitWidth>
+       <modifiedWriteValues>oneToClear</modifiedWriteValues>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>inactive</name>
+         <description>No interrupt is pending.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>pending</name>
+         <description>An interrupt is pending.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>INT_EN</name>
+       <description>Watchdog Timer Interrupt Enable.</description>
+       <bitOffset>10</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RST_EN</name>
+       <description>Watchdog Timer Reset Enable.</description>
+       <bitOffset>11</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>dis</name>
+         <description>Disable.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>en</name>
+         <description>Enable.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+      <field>
+       <name>RST_FLAG</name>
+       <description>Watchdog Timer Reset Flag.</description>
+       <bitOffset>31</bitOffset>
+       <bitWidth>1</bitWidth>
+       <enumeratedValues>
+        <usage>read-write</usage>
+        <enumeratedValue>
+         <name>noEvent</name>
+         <description>The event has not occurred.</description>
+         <value>0</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>occurred</name>
+         <description>The event has occurred.</description>
+         <value>1</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+    <register>
+     <name>RST</name>
+     <description>Watchdog Timer Reset Register.</description>
+     <addressOffset>0x04</addressOffset>
+     <access>write-only</access>
+     <fields>
+      <field>
+       <name>WDT_RST</name>
+       <description>Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled.</description>
+       <bitOffset>0</bitOffset>
+       <bitWidth>8</bitWidth>
+       <enumeratedValues>
+        <enumeratedValue>
+         <name>seq0</name>
+         <description>The first value to be written to reset the WDT.</description>
+         <value>0x000000A5</value>
+        </enumeratedValue>
+        <enumeratedValue>
+         <name>seq1</name>
+         <description>The second value to be written to reset the WDT.</description>
+         <value>0x0000005A</value>
+        </enumeratedValue>
+       </enumeratedValues>
+      </field>
+     </fields>
+    </register>
+   </registers>
+  </peripheral>
+<!--WDT0 Watchdog Timer 0-->
+ </peripherals>
+</device>

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/mxc_device.h

@@ -0,0 +1,72 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+/**
+ * @file    mxc_device.h
+ * @brief   contains device and revision specific definitions
+ */
+ 
+#ifndef _MXC_DEVICE_H_
+#define _MXC_DEVICE_H_
+
+#include "max32660.h"
+
+#ifndef TARGET
+    #error TARGET NOT DEFINED
+#endif
+
+// Create a string definition for the TARGET
+#define STRING_ARG(arg) #arg
+#define STRING_NAME(name) STRING_ARG(name)
+#define TARGET_NAME STRING_NAME(TARGET)
+
+// Define which revisions of the IP we are using
+#ifndef TARGET_REV
+    #error TARGET_REV NOT DEFINED
+#endif
+
+#if(TARGET_REV == 0x4131) 
+    // A1
+    #define MXC_PBM_REV         0
+    #define MXC_TMR_REV         0
+    #define MXC_UART_REV        1
+#else
+
+#error TARGET_REV NOT SUPPORTED
+
+#endif  // if(TARGET_REV == ...) 
+
+#endif  /* _MXC_DEVICE_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h

@@ -0,0 +1,273 @@
+/**
+ * @file    pwrseq_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _PWRSEQ_REGS_H_
+#define _PWRSEQ_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     pwrseq
+ * @defgroup    pwrseq_registers PWRSEQ_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
+ * @details Power Sequencer / Low Power Control Register.
+ */
+
+/**
+ * @ingroup pwrseq_registers
+ * Structure type to access the PWRSEQ Registers.
+ */
+typedef struct {
+    __IO uint32_t lp_ctrl;              /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
+    __IO uint32_t lp_wakefl;            /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
+    __IO uint32_t lpwk_en;              /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
+    __R  uint32_t rsv_0xc_0x3f[13];
+    __IO uint32_t lpmemsd;              /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
+} mxc_pwrseq_regs_t;
+
+/* Register offsets for module PWRSEQ */
+/**
+ * @ingroup    pwrseq_registers
+ * @defgroup   PWRSEQ_Register_Offsets Register Offsets
+ * @brief      PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_PWRSEQ_LP_CTRL               ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_PWRSEQ_LP_WAKEFL             ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_PWRSEQ_LPWK_EN               ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_PWRSEQ_LPMEMSD               ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */ 
+/**@} end of group pwrseq_registers */
+
+/**
+ * @ingroup  pwrseq_registers
+ * @defgroup PWRSEQ_LP_CTRL PWRSEQ_LP_CTRL
+ * @brief    Low Power Control Register.
+ * @{
+ */
+ #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS           0 /**< LP_CTRL_RAMRET_SEL0 Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< LP_CTRL_RAMRET_SEL0 Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS           ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS           (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN            ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN            (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN Setting */
+
+ #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS           1 /**< LP_CTRL_RAMRET_SEL1 Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< LP_CTRL_RAMRET_SEL1 Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS           ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS           (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN            ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN            (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN Setting */
+
+ #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS           2 /**< LP_CTRL_RAMRET_SEL2 Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< LP_CTRL_RAMRET_SEL2 Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS           ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS           (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN            ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN            (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN Setting */
+
+ #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS           3 /**< LP_CTRL_RAMRET_SEL3 Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< LP_CTRL_RAMRET_SEL3 Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS           ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS           (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN            ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN            (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN Setting */
+
+ #define MXC_F_PWRSEQ_LP_CTRL_OVR_POS                   4 /**< LP_CTRL_OVR Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_OVR                       ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V                  ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V                  (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V                  ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V                  (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V                  ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V                  (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */
+
+ #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS      6 /**< LP_CTRL_VCORE_DET_BYPASS Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS          ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< LP_CTRL_VCORE_DET_BYPASS Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED  ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED  (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE  ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE  (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Setting */
+
+ #define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS             8 /**< LP_CTRL_RETREG_EN Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS             ((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS             (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN              ((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN              (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN Setting */
+
+ #define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS            10 /**< LP_CTRL_FAST_WK_EN Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN                ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< LP_CTRL_FAST_WK_EN Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS            ((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS            (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN             ((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN             (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN Setting */
+
+ #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS                11 /**< LP_CTRL_BG_OFF Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON                 ((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON                 (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF                ((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF                (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting */
+
+ #define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS         12 /**< LP_CTRL_VCORE_POR_DIS Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS             ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< LP_CTRL_VCORE_POR_DIS Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS         ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS         (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< LP_CTRL_VCORE_POR_DIS_DIS Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN          ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN          (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< LP_CTRL_VCORE_POR_DIS_EN Setting */
+
+ #define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS               16 /**< LP_CTRL_LDO_DIS Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN                ((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN                (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS               ((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS               (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting */
+
+ #define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS         20 /**< LP_CTRL_VCORE_SVM_DIS Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS             ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< LP_CTRL_VCORE_SVM_DIS Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN          ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN          (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< LP_CTRL_VCORE_SVM_DIS_EN Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS         ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS         (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< LP_CTRL_VCORE_SVM_DIS_DIS Setting */
+
+ #define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS         25 /**< LP_CTRL_VDDIO_POR_DIS Position */
+ #define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS             ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< LP_CTRL_VDDIO_POR_DIS Mask */
+ #define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN          ((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN          (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< LP_CTRL_VDDIO_POR_DIS_EN Setting */
+ #define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS         ((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */
+ #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS         (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< LP_CTRL_VDDIO_POR_DIS_DIS Setting */
+
+/**@} end of group PWRSEQ_LP_CTRL_Register */
+
+/**
+ * @ingroup  pwrseq_registers
+ * @defgroup PWRSEQ_LP_WAKEFL PWRSEQ_LP_WAKEFL
+ * @brief    Low Power Mode Wakeup Flags for GPIO0
+ * @{
+ */
+ #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS              0 /**< LP_WAKEFL_WAKEST Position */
+ #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST                  ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST Mask */
+
+/**@} end of group PWRSEQ_LP_WAKEFL_Register */
+
+/**
+ * @ingroup  pwrseq_registers
+ * @defgroup PWRSEQ_LPWK_EN PWRSEQ_LPWK_EN
+ * @brief    Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup
+ *           functionality for GPIO0.
+ * @{
+ */
+ #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS                0 /**< LPWK_EN_WAKEEN Position */
+ #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN                    ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN Mask */
+
+/**@} end of group PWRSEQ_LPWK_EN_Register */
+
+/**
+ * @ingroup  pwrseq_registers
+ * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD
+ * @brief    Low Power Memory Shutdown Control.
+ * @{
+ */
+ #define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS             0 /**< LPMEMSD_SRAM0_OFF Position */
+ #define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF Mask */
+ #define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL          ((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */
+ #define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL          (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL Setting */
+ #define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN        ((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */
+ #define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN        (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Setting */
+
+ #define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS             1 /**< LPMEMSD_SRAM1_OFF Position */
+ #define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF Mask */
+ #define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL          ((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */
+ #define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL          (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL Setting */
+ #define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN        ((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */
+ #define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN        (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Setting */
+
+ #define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS             2 /**< LPMEMSD_SRAM2_OFF Position */
+ #define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF Mask */
+ #define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL          ((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */
+ #define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL          (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL Setting */
+ #define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN        ((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */
+ #define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN        (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Setting */
+
+ #define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS             3 /**< LPMEMSD_SRAM3_OFF Position */
+ #define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF Mask */
+ #define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL          ((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */
+ #define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL          (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL Setting */
+ #define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN        ((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */
+ #define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN        (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Setting */
+
+/**@} end of group PWRSEQ_LPMEMSD_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _PWRSEQ_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h

@@ -0,0 +1,297 @@
+/**
+ * @file    rtc_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _RTC_REGS_H_
+#define _RTC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     rtc
+ * @defgroup    rtc_registers RTC_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
+ * @details Real Time Clock and Alarm.
+ */
+
+/**
+ * @ingroup rtc_registers
+ * Structure type to access the RTC Registers.
+ */
+typedef struct {
+    __IO uint32_t sec;                  /**< <tt>\b 0x00:</tt> RTC SEC Register */
+    __IO uint32_t ssec;                 /**< <tt>\b 0x04:</tt> RTC SSEC Register */
+    __IO uint32_t ras;                  /**< <tt>\b 0x08:</tt> RTC RAS Register */
+    __IO uint32_t rssa;                 /**< <tt>\b 0x0C:</tt> RTC RSSA Register */
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x10:</tt> RTC CTRL Register */
+    __IO uint32_t trim;                 /**< <tt>\b 0x14:</tt> RTC TRIM Register */
+    __IO uint32_t oscctrl;              /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */
+} mxc_rtc_regs_t;
+
+/* Register offsets for module RTC */
+/**
+ * @ingroup    rtc_registers
+ * @defgroup   RTC_Register_Offsets Register Offsets
+ * @brief      RTC Peripheral Register Offsets from the RTC Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_RTC_SEC                      ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_RTC_SSEC                     ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_RTC_RAS                      ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_RTC_RSSA                     ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_RTC_CTRL                     ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_RTC_TRIM                     ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_RTC_OSCCTRL                  ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */ 
+/**@} end of group rtc_registers */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_SSEC RTC_SSEC
+ * @brief    RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented
+ *           when this register rolls over from 0xFF to 0x00.
+ * @{
+ */
+ #define MXC_F_RTC_SSEC_RTSS_POS                        0 /**< SSEC_RTSS Position */
+ #define MXC_F_RTC_SSEC_RTSS                            ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */
+
+/**@} end of group RTC_SSEC_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_RAS RTC_RAS
+ * @brief    Time-of-day Alarm.
+ * @{
+ */
+ #define MXC_F_RTC_RAS_RAS_POS                          0 /**< RAS_RAS Position */
+ #define MXC_F_RTC_RAS_RAS                              ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */
+
+/**@} end of group RTC_RAS_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_RSSA RTC_RSSA
+ * @brief    RTC sub-second alarm.  This register contains the reload value for the sub-
+ *           second alarm.
+ * @{
+ */
+ #define MXC_F_RTC_RSSA_RSSA_POS                        0 /**< RSSA_RSSA Position */
+ #define MXC_F_RTC_RSSA_RSSA                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */
+
+/**@} end of group RTC_RSSA_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_CTRL RTC_CTRL
+ * @brief    RTC Control Register.
+ * @{
+ */
+ #define MXC_F_RTC_CTRL_RTCE_POS                        0 /**< CTRL_RTCE Position */
+ #define MXC_F_RTC_CTRL_RTCE                            ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */
+ #define MXC_V_RTC_CTRL_RTCE_DIS                        ((uint32_t)0x0UL) /**< CTRL_RTCE_DIS Value */
+ #define MXC_S_RTC_CTRL_RTCE_DIS                        (MXC_V_RTC_CTRL_RTCE_DIS << MXC_F_RTC_CTRL_RTCE_POS) /**< CTRL_RTCE_DIS Setting */
+ #define MXC_V_RTC_CTRL_RTCE_EN                         ((uint32_t)0x1UL) /**< CTRL_RTCE_EN Value */
+ #define MXC_S_RTC_CTRL_RTCE_EN                         (MXC_V_RTC_CTRL_RTCE_EN << MXC_F_RTC_CTRL_RTCE_POS) /**< CTRL_RTCE_EN Setting */
+
+ #define MXC_F_RTC_CTRL_ADE_POS                         1 /**< CTRL_ADE Position */
+ #define MXC_F_RTC_CTRL_ADE                             ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */
+ #define MXC_V_RTC_CTRL_ADE_DIS                         ((uint32_t)0x0UL) /**< CTRL_ADE_DIS Value */
+ #define MXC_S_RTC_CTRL_ADE_DIS                         (MXC_V_RTC_CTRL_ADE_DIS << MXC_F_RTC_CTRL_ADE_POS) /**< CTRL_ADE_DIS Setting */
+ #define MXC_V_RTC_CTRL_ADE_EN                          ((uint32_t)0x1UL) /**< CTRL_ADE_EN Value */
+ #define MXC_S_RTC_CTRL_ADE_EN                          (MXC_V_RTC_CTRL_ADE_EN << MXC_F_RTC_CTRL_ADE_POS) /**< CTRL_ADE_EN Setting */
+
+ #define MXC_F_RTC_CTRL_ASE_POS                         2 /**< CTRL_ASE Position */
+ #define MXC_F_RTC_CTRL_ASE                             ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */
+ #define MXC_V_RTC_CTRL_ASE_DIS                         ((uint32_t)0x0UL) /**< CTRL_ASE_DIS Value */
+ #define MXC_S_RTC_CTRL_ASE_DIS                         (MXC_V_RTC_CTRL_ASE_DIS << MXC_F_RTC_CTRL_ASE_POS) /**< CTRL_ASE_DIS Setting */
+ #define MXC_V_RTC_CTRL_ASE_EN                          ((uint32_t)0x1UL) /**< CTRL_ASE_EN Value */
+ #define MXC_S_RTC_CTRL_ASE_EN                          (MXC_V_RTC_CTRL_ASE_EN << MXC_F_RTC_CTRL_ASE_POS) /**< CTRL_ASE_EN Setting */
+
+ #define MXC_F_RTC_CTRL_BUSY_POS                        3 /**< CTRL_BUSY Position */
+ #define MXC_F_RTC_CTRL_BUSY                            ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
+ #define MXC_V_RTC_CTRL_BUSY_IDLE                       ((uint32_t)0x0UL) /**< CTRL_BUSY_IDLE Value */
+ #define MXC_S_RTC_CTRL_BUSY_IDLE                       (MXC_V_RTC_CTRL_BUSY_IDLE << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_IDLE Setting */
+ #define MXC_V_RTC_CTRL_BUSY_BUSY                       ((uint32_t)0x1UL) /**< CTRL_BUSY_BUSY Value */
+ #define MXC_S_RTC_CTRL_BUSY_BUSY                       (MXC_V_RTC_CTRL_BUSY_BUSY << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_BUSY Setting */
+
+ #define MXC_F_RTC_CTRL_RDY_POS                         4 /**< CTRL_RDY Position */
+ #define MXC_F_RTC_CTRL_RDY                             ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
+ #define MXC_V_RTC_CTRL_RDY_BUSY                        ((uint32_t)0x0UL) /**< CTRL_RDY_BUSY Value */
+ #define MXC_S_RTC_CTRL_RDY_BUSY                        (MXC_V_RTC_CTRL_RDY_BUSY << MXC_F_RTC_CTRL_RDY_POS) /**< CTRL_RDY_BUSY Setting */
+ #define MXC_V_RTC_CTRL_RDY_READY                       ((uint32_t)0x1UL) /**< CTRL_RDY_READY Value */
+ #define MXC_S_RTC_CTRL_RDY_READY                       (MXC_V_RTC_CTRL_RDY_READY << MXC_F_RTC_CTRL_RDY_POS) /**< CTRL_RDY_READY Setting */
+
+ #define MXC_F_RTC_CTRL_RDYE_POS                        5 /**< CTRL_RDYE Position */
+ #define MXC_F_RTC_CTRL_RDYE                            ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */
+ #define MXC_V_RTC_CTRL_RDYE_DIS                        ((uint32_t)0x0UL) /**< CTRL_RDYE_DIS Value */
+ #define MXC_S_RTC_CTRL_RDYE_DIS                        (MXC_V_RTC_CTRL_RDYE_DIS << MXC_F_RTC_CTRL_RDYE_POS) /**< CTRL_RDYE_DIS Setting */
+ #define MXC_V_RTC_CTRL_RDYE_EN                         ((uint32_t)0x1UL) /**< CTRL_RDYE_EN Value */
+ #define MXC_S_RTC_CTRL_RDYE_EN                         (MXC_V_RTC_CTRL_RDYE_EN << MXC_F_RTC_CTRL_RDYE_POS) /**< CTRL_RDYE_EN Setting */
+
+ #define MXC_F_RTC_CTRL_ALDF_POS                        6 /**< CTRL_ALDF Position */
+ #define MXC_F_RTC_CTRL_ALDF                            ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */
+ #define MXC_V_RTC_CTRL_ALDF_INACTIVE                   ((uint32_t)0x0UL) /**< CTRL_ALDF_INACTIVE Value */
+ #define MXC_S_RTC_CTRL_ALDF_INACTIVE                   (MXC_V_RTC_CTRL_ALDF_INACTIVE << MXC_F_RTC_CTRL_ALDF_POS) /**< CTRL_ALDF_INACTIVE Setting */
+ #define MXC_V_RTC_CTRL_ALDF_PENDING                    ((uint32_t)0x1UL) /**< CTRL_ALDF_PENDING Value */
+ #define MXC_S_RTC_CTRL_ALDF_PENDING                    (MXC_V_RTC_CTRL_ALDF_PENDING << MXC_F_RTC_CTRL_ALDF_POS) /**< CTRL_ALDF_PENDING Setting */
+
+ #define MXC_F_RTC_CTRL_ALSF_POS                        7 /**< CTRL_ALSF Position */
+ #define MXC_F_RTC_CTRL_ALSF                            ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */
+ #define MXC_V_RTC_CTRL_ALSF_INACTIVE                   ((uint32_t)0x0UL) /**< CTRL_ALSF_INACTIVE Value */
+ #define MXC_S_RTC_CTRL_ALSF_INACTIVE                   (MXC_V_RTC_CTRL_ALSF_INACTIVE << MXC_F_RTC_CTRL_ALSF_POS) /**< CTRL_ALSF_INACTIVE Setting */
+ #define MXC_V_RTC_CTRL_ALSF_PENDING                    ((uint32_t)0x1UL) /**< CTRL_ALSF_PENDING Value */
+ #define MXC_S_RTC_CTRL_ALSF_PENDING                    (MXC_V_RTC_CTRL_ALSF_PENDING << MXC_F_RTC_CTRL_ALSF_POS) /**< CTRL_ALSF_PENDING Setting */
+
+ #define MXC_F_RTC_CTRL_SQE_POS                         8 /**< CTRL_SQE Position */
+ #define MXC_F_RTC_CTRL_SQE                             ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */
+ #define MXC_V_RTC_CTRL_SQE_INACTIVE                    ((uint32_t)0x0UL) /**< CTRL_SQE_INACTIVE Value */
+ #define MXC_S_RTC_CTRL_SQE_INACTIVE                    (MXC_V_RTC_CTRL_SQE_INACTIVE << MXC_F_RTC_CTRL_SQE_POS) /**< CTRL_SQE_INACTIVE Setting */
+ #define MXC_V_RTC_CTRL_SQE_PENDING                     ((uint32_t)0x1UL) /**< CTRL_SQE_PENDING Value */
+ #define MXC_S_RTC_CTRL_SQE_PENDING                     (MXC_V_RTC_CTRL_SQE_PENDING << MXC_F_RTC_CTRL_SQE_POS) /**< CTRL_SQE_PENDING Setting */
+
+ #define MXC_F_RTC_CTRL_FT_POS                          9 /**< CTRL_FT Position */
+ #define MXC_F_RTC_CTRL_FT                              ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */
+ #define MXC_V_RTC_CTRL_FT_FREQ1HZ                      ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */
+ #define MXC_S_RTC_CTRL_FT_FREQ1HZ                      (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */
+ #define MXC_V_RTC_CTRL_FT_FREQ512HZ                    ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */
+ #define MXC_S_RTC_CTRL_FT_FREQ512HZ                    (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */
+ #define MXC_V_RTC_CTRL_FT_FREQ4KHZ                     ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */
+ #define MXC_S_RTC_CTRL_FT_FREQ4KHZ                     (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */
+ #define MXC_V_RTC_CTRL_FT_CLKDIV8                      ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */
+ #define MXC_S_RTC_CTRL_FT_CLKDIV8                      (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */
+
+ #define MXC_F_RTC_CTRL_X32KMD_POS                      11 /**< CTRL_X32KMD Position */
+ #define MXC_F_RTC_CTRL_X32KMD                          ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */
+ #define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE          ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */
+ #define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE          (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */
+ #define MXC_V_RTC_CTRL_X32KMD_QUIETMODE                ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */
+ #define MXC_S_RTC_CTRL_X32KMD_QUIETMODE                (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */
+ #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP    ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */
+ #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP    (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */
+ #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP      ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */
+ #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP      (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */
+
+ #define MXC_F_RTC_CTRL_WE_POS                          15 /**< CTRL_WE Position */
+ #define MXC_F_RTC_CTRL_WE                              ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */
+ #define MXC_V_RTC_CTRL_WE_INACTIVE                     ((uint32_t)0x0UL) /**< CTRL_WE_INACTIVE Value */
+ #define MXC_S_RTC_CTRL_WE_INACTIVE                     (MXC_V_RTC_CTRL_WE_INACTIVE << MXC_F_RTC_CTRL_WE_POS) /**< CTRL_WE_INACTIVE Setting */
+ #define MXC_V_RTC_CTRL_WE_PENDING                      ((uint32_t)0x1UL) /**< CTRL_WE_PENDING Value */
+ #define MXC_S_RTC_CTRL_WE_PENDING                      (MXC_V_RTC_CTRL_WE_PENDING << MXC_F_RTC_CTRL_WE_POS) /**< CTRL_WE_PENDING Setting */
+
+/**@} end of group RTC_CTRL_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_TRIM RTC_TRIM
+ * @brief    RTC Trim Register.
+ * @{
+ */
+ #define MXC_F_RTC_TRIM_TRIM_POS                        0 /**< TRIM_TRIM Position */
+ #define MXC_F_RTC_TRIM_TRIM                            ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */
+
+ #define MXC_F_RTC_TRIM_VBATTMR_POS                     8 /**< TRIM_VBATTMR Position */
+ #define MXC_F_RTC_TRIM_VBATTMR                         ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */
+
+/**@} end of group RTC_TRIM_Register */
+
+/**
+ * @ingroup  rtc_registers
+ * @defgroup RTC_OSCCTRL RTC_OSCCTRL
+ * @brief    RTC Oscillator Control Register.
+ * @{
+ */
+ #define MXC_F_RTC_OSCCTRL_FLITER_EN_POS                0 /**< OSCCTRL_FLITER_EN Position */
+ #define MXC_F_RTC_OSCCTRL_FLITER_EN                    ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */
+
+ #define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS                1 /**< OSCCTRL_IBIAS_SEL Position */
+ #define MXC_F_RTC_OSCCTRL_IBIAS_SEL                    ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */
+ #define MXC_V_RTC_OSCCTRL_IBIAS_SEL_2X                 ((uint32_t)0x0UL) /**< OSCCTRL_IBIAS_SEL_2X Value */
+ #define MXC_S_RTC_OSCCTRL_IBIAS_SEL_2X                 (MXC_V_RTC_OSCCTRL_IBIAS_SEL_2X << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS) /**< OSCCTRL_IBIAS_SEL_2X Setting */
+ #define MXC_V_RTC_OSCCTRL_IBIAS_SEL_4X                 ((uint32_t)0x1UL) /**< OSCCTRL_IBIAS_SEL_4X Value */
+ #define MXC_S_RTC_OSCCTRL_IBIAS_SEL_4X                 (MXC_V_RTC_OSCCTRL_IBIAS_SEL_4X << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS) /**< OSCCTRL_IBIAS_SEL_4X Setting */
+
+ #define MXC_F_RTC_OSCCTRL_HYST_EN_POS                  2 /**< OSCCTRL_HYST_EN Position */
+ #define MXC_F_RTC_OSCCTRL_HYST_EN                      ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */
+
+ #define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS                 3 /**< OSCCTRL_IBIAS_EN Position */
+ #define MXC_F_RTC_OSCCTRL_IBIAS_EN                     ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */
+
+ #define MXC_F_RTC_OSCCTRL_BYPASS_POS                   4 /**< OSCCTRL_BYPASS Position */
+ #define MXC_F_RTC_OSCCTRL_BYPASS                       ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */
+
+ #define MXC_F_RTC_OSCCTRL_OUT32K_POS                   5 /**< OSCCTRL_OUT32K Position */
+ #define MXC_F_RTC_OSCCTRL_OUT32K                       ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */
+
+/**@} end of group RTC_OSCCTRL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTC_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h

@@ -0,0 +1,255 @@
+/**
+ * @file    sir_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _SIR_REGS_H_
+#define _SIR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     sir
+ * @defgroup    sir_registers SIR_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
+ * @details System Initialization Registers.
+ */
+
+/**
+ * @ingroup sir_registers
+ * Structure type to access the SIR Registers.
+ */
+typedef struct {
+    __I  uint32_t sistat;               /**< <tt>\b 0x00:</tt> SIR SISTAT Register */
+    __I  uint32_t erraddr;              /**< <tt>\b 0x04:</tt> SIR ERRADDR Register */
+    __R  uint32_t rsv_0x8_0xff[62];
+    __I  uint32_t fstat;                /**< <tt>\b 0x100:</tt> SIR FSTAT Register */
+    __I  uint32_t sfstat;               /**< <tt>\b 0x104:</tt> SIR SFSTAT Register */
+} mxc_sir_regs_t;
+
+/* Register offsets for module SIR */
+/**
+ * @ingroup    sir_registers
+ * @defgroup   SIR_Register_Offsets Register Offsets
+ * @brief      SIR Peripheral Register Offsets from the SIR Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_SIR_SISTAT                   ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_SIR_ERRADDR                  ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_SIR_FSTAT                    ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: <tt> 0x0100</tt> */ 
+ #define MXC_R_SIR_SFSTAT                   ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: <tt> 0x0104</tt> */ 
+/**@} end of group sir_registers */
+
+/**
+ * @ingroup  sir_registers
+ * @defgroup SIR_SISTAT SIR_SISTAT
+ * @brief    System Initialization Status Register.
+ * @{
+ */
+ #define MXC_F_SIR_SISTAT_MAGIC_POS                     0 /**< SISTAT_MAGIC Position */
+ #define MXC_F_SIR_SISTAT_MAGIC                         ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_MAGIC_POS)) /**< SISTAT_MAGIC Mask */
+ #define MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET             ((uint32_t)0x0UL) /**< SISTAT_MAGIC_MAGICNOTSET Value */
+ #define MXC_S_SIR_SISTAT_MAGIC_MAGICNOTSET             (MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICNOTSET Setting */
+ #define MXC_V_SIR_SISTAT_MAGIC_MAGICSET                ((uint32_t)0x1UL) /**< SISTAT_MAGIC_MAGICSET Value */
+ #define MXC_S_SIR_SISTAT_MAGIC_MAGICSET                (MXC_V_SIR_SISTAT_MAGIC_MAGICSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICSET Setting */
+
+ #define MXC_F_SIR_SISTAT_CRCERR_POS                    1 /**< SISTAT_CRCERR Position */
+ #define MXC_F_SIR_SISTAT_CRCERR                        ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_CRCERR_POS)) /**< SISTAT_CRCERR Mask */
+ #define MXC_V_SIR_SISTAT_CRCERR_NOERROR                ((uint32_t)0x0UL) /**< SISTAT_CRCERR_NOERROR Value */
+ #define MXC_S_SIR_SISTAT_CRCERR_NOERROR                (MXC_V_SIR_SISTAT_CRCERR_NOERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_NOERROR Setting */
+ #define MXC_V_SIR_SISTAT_CRCERR_ERROR                  ((uint32_t)0x1UL) /**< SISTAT_CRCERR_ERROR Value */
+ #define MXC_S_SIR_SISTAT_CRCERR_ERROR                  (MXC_V_SIR_SISTAT_CRCERR_ERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_ERROR Setting */
+
+/**@} end of group SIR_SISTAT_Register */
+
+/**
+ * @ingroup  sir_registers
+ * @defgroup SIR_ERRADDR SIR_ERRADDR
+ * @brief    Read-only field set by the SIB block if a CRC error occurs during the read of
+ *           the OTP memory. Contains the failing address in OTP memory (when CRCERR equals
+ *           1).
+ * @{
+ */
+ #define MXC_F_SIR_ERRADDR_ERRADDR_POS                  0 /**< ERRADDR_ERRADDR Position */
+ #define MXC_F_SIR_ERRADDR_ERRADDR                      ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ERRADDR_ERRADDR_POS)) /**< ERRADDR_ERRADDR Mask */
+
+/**@} end of group SIR_ERRADDR_Register */
+
+/**
+ * @ingroup  sir_registers
+ * @defgroup SIR_FSTAT SIR_FSTAT
+ * @brief    funcstat register.
+ * @{
+ */
+ #define MXC_F_SIR_FSTAT_FPU_POS                        0 /**< FSTAT_FPU Position */
+ #define MXC_F_SIR_FSTAT_FPU                            ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_FPU_POS)) /**< FSTAT_FPU Mask */
+ #define MXC_V_SIR_FSTAT_FPU_NO                         ((uint32_t)0x0UL) /**< FSTAT_FPU_NO Value */
+ #define MXC_S_SIR_FSTAT_FPU_NO                         (MXC_V_SIR_FSTAT_FPU_NO << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_NO Setting */
+ #define MXC_V_SIR_FSTAT_FPU_YES                        ((uint32_t)0x1UL) /**< FSTAT_FPU_YES Value */
+ #define MXC_S_SIR_FSTAT_FPU_YES                        (MXC_V_SIR_FSTAT_FPU_YES << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_YES Setting */
+
+ #define MXC_F_SIR_FSTAT_USB_POS                        1 /**< FSTAT_USB Position */
+ #define MXC_F_SIR_FSTAT_USB                            ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_USB_POS)) /**< FSTAT_USB Mask */
+ #define MXC_V_SIR_FSTAT_USB_NO                         ((uint32_t)0x0UL) /**< FSTAT_USB_NO Value */
+ #define MXC_S_SIR_FSTAT_USB_NO                         (MXC_V_SIR_FSTAT_USB_NO << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_NO Setting */
+ #define MXC_V_SIR_FSTAT_USB_YES                        ((uint32_t)0x1UL) /**< FSTAT_USB_YES Value */
+ #define MXC_S_SIR_FSTAT_USB_YES                        (MXC_V_SIR_FSTAT_USB_YES << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_YES Setting */
+
+ #define MXC_F_SIR_FSTAT_ADC_POS                        2 /**< FSTAT_ADC Position */
+ #define MXC_F_SIR_FSTAT_ADC                            ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC_POS)) /**< FSTAT_ADC Mask */
+ #define MXC_V_SIR_FSTAT_ADC_NO                         ((uint32_t)0x0UL) /**< FSTAT_ADC_NO Value */
+ #define MXC_S_SIR_FSTAT_ADC_NO                         (MXC_V_SIR_FSTAT_ADC_NO << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_NO Setting */
+ #define MXC_V_SIR_FSTAT_ADC_YES                        ((uint32_t)0x1UL) /**< FSTAT_ADC_YES Value */
+ #define MXC_S_SIR_FSTAT_ADC_YES                        (MXC_V_SIR_FSTAT_ADC_YES << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_YES Setting */
+
+ #define MXC_F_SIR_FSTAT_XIP_POS                        3 /**< FSTAT_XIP Position */
+ #define MXC_F_SIR_FSTAT_XIP                            ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_XIP_POS)) /**< FSTAT_XIP Mask */
+ #define MXC_V_SIR_FSTAT_XIP_NO                         ((uint32_t)0x0UL) /**< FSTAT_XIP_NO Value */
+ #define MXC_S_SIR_FSTAT_XIP_NO                         (MXC_V_SIR_FSTAT_XIP_NO << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_NO Setting */
+ #define MXC_V_SIR_FSTAT_XIP_YES                        ((uint32_t)0x1UL) /**< FSTAT_XIP_YES Value */
+ #define MXC_S_SIR_FSTAT_XIP_YES                        (MXC_V_SIR_FSTAT_XIP_YES << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_YES Setting */
+
+ #define MXC_F_SIR_FSTAT_PBM_POS                        4 /**< FSTAT_PBM Position */
+ #define MXC_F_SIR_FSTAT_PBM                            ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_PBM_POS)) /**< FSTAT_PBM Mask */
+ #define MXC_V_SIR_FSTAT_PBM_NO                         ((uint32_t)0x0UL) /**< FSTAT_PBM_NO Value */
+ #define MXC_S_SIR_FSTAT_PBM_NO                         (MXC_V_SIR_FSTAT_PBM_NO << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_NO Setting */
+ #define MXC_V_SIR_FSTAT_PBM_YES                        ((uint32_t)0x1UL) /**< FSTAT_PBM_YES Value */
+ #define MXC_S_SIR_FSTAT_PBM_YES                        (MXC_V_SIR_FSTAT_PBM_YES << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_YES Setting */
+
+ #define MXC_F_SIR_FSTAT_HBC_POS                        5 /**< FSTAT_HBC Position */
+ #define MXC_F_SIR_FSTAT_HBC                            ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_HBC_POS)) /**< FSTAT_HBC Mask */
+ #define MXC_V_SIR_FSTAT_HBC_NO                         ((uint32_t)0x0UL) /**< FSTAT_HBC_NO Value */
+ #define MXC_S_SIR_FSTAT_HBC_NO                         (MXC_V_SIR_FSTAT_HBC_NO << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_NO Setting */
+ #define MXC_V_SIR_FSTAT_HBC_YES                        ((uint32_t)0x1UL) /**< FSTAT_HBC_YES Value */
+ #define MXC_S_SIR_FSTAT_HBC_YES                        (MXC_V_SIR_FSTAT_HBC_YES << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_YES Setting */
+
+ #define MXC_F_SIR_FSTAT_SDHC_POS                       6 /**< FSTAT_SDHC Position */
+ #define MXC_F_SIR_FSTAT_SDHC                           ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SDHC_POS)) /**< FSTAT_SDHC Mask */
+ #define MXC_V_SIR_FSTAT_SDHC_NO                        ((uint32_t)0x0UL) /**< FSTAT_SDHC_NO Value */
+ #define MXC_S_SIR_FSTAT_SDHC_NO                        (MXC_V_SIR_FSTAT_SDHC_NO << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_NO Setting */
+ #define MXC_V_SIR_FSTAT_SDHC_YES                       ((uint32_t)0x1UL) /**< FSTAT_SDHC_YES Value */
+ #define MXC_S_SIR_FSTAT_SDHC_YES                       (MXC_V_SIR_FSTAT_SDHC_YES << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_YES Setting */
+
+ #define MXC_F_SIR_FSTAT_SMPHR_POS                      7 /**< FSTAT_SMPHR Position */
+ #define MXC_F_SIR_FSTAT_SMPHR                          ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SMPHR_POS)) /**< FSTAT_SMPHR Mask */
+ #define MXC_V_SIR_FSTAT_SMPHR_NO                       ((uint32_t)0x0UL) /**< FSTAT_SMPHR_NO Value */
+ #define MXC_S_SIR_FSTAT_SMPHR_NO                       (MXC_V_SIR_FSTAT_SMPHR_NO << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_NO Setting */
+ #define MXC_V_SIR_FSTAT_SMPHR_YES                      ((uint32_t)0x1UL) /**< FSTAT_SMPHR_YES Value */
+ #define MXC_S_SIR_FSTAT_SMPHR_YES                      (MXC_V_SIR_FSTAT_SMPHR_YES << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_YES Setting */
+
+ #define MXC_F_SIR_FSTAT_SCACHE_POS                     8 /**< FSTAT_SCACHE Position */
+ #define MXC_F_SIR_FSTAT_SCACHE                         ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SCACHE_POS)) /**< FSTAT_SCACHE Mask */
+ #define MXC_V_SIR_FSTAT_SCACHE_NO                      ((uint32_t)0x0UL) /**< FSTAT_SCACHE_NO Value */
+ #define MXC_S_SIR_FSTAT_SCACHE_NO                      (MXC_V_SIR_FSTAT_SCACHE_NO << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_NO Setting */
+ #define MXC_V_SIR_FSTAT_SCACHE_YES                     ((uint32_t)0x1UL) /**< FSTAT_SCACHE_YES Value */
+ #define MXC_S_SIR_FSTAT_SCACHE_YES                     (MXC_V_SIR_FSTAT_SCACHE_YES << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_YES Setting */
+
+/**@} end of group SIR_FSTAT_Register */
+
+/**
+ * @ingroup  sir_registers
+ * @defgroup SIR_SFSTAT SIR_SFSTAT
+ * @brief    secfuncstat register.
+ * @{
+ */
+ #define MXC_F_SIR_SFSTAT_TRNG_POS                      2 /**< SFSTAT_TRNG Position */
+ #define MXC_F_SIR_SFSTAT_TRNG                          ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_TRNG_POS)) /**< SFSTAT_TRNG Mask */
+ #define MXC_V_SIR_SFSTAT_TRNG_NO                       ((uint32_t)0x0UL) /**< SFSTAT_TRNG_NO Value */
+ #define MXC_S_SIR_SFSTAT_TRNG_NO                       (MXC_V_SIR_SFSTAT_TRNG_NO << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_NO Setting */
+ #define MXC_V_SIR_SFSTAT_TRNG_YES                      ((uint32_t)0x1UL) /**< SFSTAT_TRNG_YES Value */
+ #define MXC_S_SIR_SFSTAT_TRNG_YES                      (MXC_V_SIR_SFSTAT_TRNG_YES << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_YES Setting */
+
+ #define MXC_F_SIR_SFSTAT_AES_POS                       3 /**< SFSTAT_AES Position */
+ #define MXC_F_SIR_SFSTAT_AES                           ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_AES_POS)) /**< SFSTAT_AES Mask */
+ #define MXC_V_SIR_SFSTAT_AES_NO                        ((uint32_t)0x0UL) /**< SFSTAT_AES_NO Value */
+ #define MXC_S_SIR_SFSTAT_AES_NO                        (MXC_V_SIR_SFSTAT_AES_NO << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_NO Setting */
+ #define MXC_V_SIR_SFSTAT_AES_YES                       ((uint32_t)0x1UL) /**< SFSTAT_AES_YES Value */
+ #define MXC_S_SIR_SFSTAT_AES_YES                       (MXC_V_SIR_SFSTAT_AES_YES << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_YES Setting */
+
+ #define MXC_F_SIR_SFSTAT_SHA_POS                       4 /**< SFSTAT_SHA Position */
+ #define MXC_F_SIR_SFSTAT_SHA                           ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SHA_POS)) /**< SFSTAT_SHA Mask */
+ #define MXC_V_SIR_SFSTAT_SHA_NO                        ((uint32_t)0x0UL) /**< SFSTAT_SHA_NO Value */
+ #define MXC_S_SIR_SFSTAT_SHA_NO                        (MXC_V_SIR_SFSTAT_SHA_NO << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_NO Setting */
+ #define MXC_V_SIR_SFSTAT_SHA_YES                       ((uint32_t)0x1UL) /**< SFSTAT_SHA_YES Value */
+ #define MXC_S_SIR_SFSTAT_SHA_YES                       (MXC_V_SIR_SFSTAT_SHA_YES << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_YES Setting */
+
+ #define MXC_F_SIR_SFSTAT_MAA_POS                       5 /**< SFSTAT_MAA Position */
+ #define MXC_F_SIR_SFSTAT_MAA                           ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_MAA_POS)) /**< SFSTAT_MAA Mask */
+ #define MXC_V_SIR_SFSTAT_MAA_NO                        ((uint32_t)0x0UL) /**< SFSTAT_MAA_NO Value */
+ #define MXC_S_SIR_SFSTAT_MAA_NO                        (MXC_V_SIR_SFSTAT_MAA_NO << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_NO Setting */
+ #define MXC_V_SIR_SFSTAT_MAA_YES                       ((uint32_t)0x1UL) /**< SFSTAT_MAA_YES Value */
+ #define MXC_S_SIR_SFSTAT_MAA_YES                       (MXC_V_SIR_SFSTAT_MAA_YES << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_YES Setting */
+
+/**@} end of group SIR_SFSTAT_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SIR_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/smon_regs.h

@@ -0,0 +1,628 @@
+/**
+ * @file    smon_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the SMON Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _SMON_REGS_H_
+#define _SMON_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     smon
+ * @defgroup    smon_registers SMON_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the SMON Peripheral Module.
+ * @details The Security Monitor block used to monitor system threat conditions.
+ */
+
+/**
+ * @ingroup smon_registers
+ * Structure type to access the SMON Registers.
+ */
+typedef struct {
+    __IO uint32_t extscn;               /**< <tt>\b 0x00:</tt> SMON EXTSCN Register */
+    __IO uint32_t intscn;               /**< <tt>\b 0x04:</tt> SMON INTSCN Register */
+    __IO uint32_t secalm;               /**< <tt>\b 0x08:</tt> SMON SECALM Register */
+    __I  uint32_t secdiag;              /**< <tt>\b 0x0C:</tt> SMON SECDIAG Register */
+    __I  uint32_t dlrtc;                /**< <tt>\b 0x10:</tt> SMON DLRTC Register */
+    __R  uint32_t rsv_0x14_0x33[8];
+    __I  uint32_t secst;                /**< <tt>\b 0x34:</tt> SMON SECST Register */
+} mxc_smon_regs_t;
+
+/* Register offsets for module SMON */
+/**
+ * @ingroup    smon_registers
+ * @defgroup   SMON_Register_Offsets Register Offsets
+ * @brief      SMON Peripheral Register Offsets from the SMON Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_SMON_EXTSCN                  ((uint32_t)0x00000000UL) /**< Offset from SMON Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_SMON_INTSCN                  ((uint32_t)0x00000004UL) /**< Offset from SMON Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_SMON_SECALM                  ((uint32_t)0x00000008UL) /**< Offset from SMON Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_SMON_SECDIAG                 ((uint32_t)0x0000000CUL) /**< Offset from SMON Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_SMON_DLRTC                   ((uint32_t)0x00000010UL) /**< Offset from SMON Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_SMON_SECST                   ((uint32_t)0x00000034UL) /**< Offset from SMON Base Address: <tt> 0x0034</tt> */ 
+/**@} end of group smon_registers */
+
+/**
+ * @ingroup  smon_registers
+ * @defgroup SMON_EXTSCN SMON_EXTSCN
+ * @brief    External Sensor Control Register.
+ * @{
+ */
+ #define MXC_F_SMON_EXTSCN_EXTS_EN0_POS                 0 /**< EXTSCN_EXTS_EN0 Position */
+ #define MXC_F_SMON_EXTSCN_EXTS_EN0                     ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN0_POS)) /**< EXTSCN_EXTS_EN0 Mask */
+ #define MXC_V_SMON_EXTSCN_EXTS_EN0_DIS                 ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN0_DIS Value */
+ #define MXC_S_SMON_EXTSCN_EXTS_EN0_DIS                 (MXC_V_SMON_EXTSCN_EXTS_EN0_DIS << MXC_F_SMON_EXTSCN_EXTS_EN0_POS) /**< EXTSCN_EXTS_EN0_DIS Setting */
+ #define MXC_V_SMON_EXTSCN_EXTS_EN0_EN                  ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN0_EN Value */
+ #define MXC_S_SMON_EXTSCN_EXTS_EN0_EN                  (MXC_V_SMON_EXTSCN_EXTS_EN0_EN << MXC_F_SMON_EXTSCN_EXTS_EN0_POS) /**< EXTSCN_EXTS_EN0_EN Setting */
+
+ #define MXC_F_SMON_EXTSCN_EXTS_EN1_POS                 1 /**< EXTSCN_EXTS_EN1 Position */
+ #define MXC_F_SMON_EXTSCN_EXTS_EN1                     ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN1_POS)) /**< EXTSCN_EXTS_EN1 Mask */
+ #define MXC_V_SMON_EXTSCN_EXTS_EN1_DIS                 ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN1_DIS Value */
+ #define MXC_S_SMON_EXTSCN_EXTS_EN1_DIS                 (MXC_V_SMON_EXTSCN_EXTS_EN1_DIS << MXC_F_SMON_EXTSCN_EXTS_EN1_POS) /**< EXTSCN_EXTS_EN1_DIS Setting */
+ #define MXC_V_SMON_EXTSCN_EXTS_EN1_EN                  ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN1_EN Value */
+ #define MXC_S_SMON_EXTSCN_EXTS_EN1_EN                  (MXC_V_SMON_EXTSCN_EXTS_EN1_EN << MXC_F_SMON_EXTSCN_EXTS_EN1_POS) /**< EXTSCN_EXTS_EN1_EN Setting */
+
+ #define MXC_F_SMON_EXTSCN_EXTS_EN2_POS                 2 /**< EXTSCN_EXTS_EN2 Position */
+ #define MXC_F_SMON_EXTSCN_EXTS_EN2                     ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN2_POS)) /**< EXTSCN_EXTS_EN2 Mask */
+ #define MXC_V_SMON_EXTSCN_EXTS_EN2_DIS                 ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN2_DIS Value */
+ #define MXC_S_SMON_EXTSCN_EXTS_EN2_DIS                 (MXC_V_SMON_EXTSCN_EXTS_EN2_DIS << MXC_F_SMON_EXTSCN_EXTS_EN2_POS) /**< EXTSCN_EXTS_EN2_DIS Setting */
+ #define MXC_V_SMON_EXTSCN_EXTS_EN2_EN                  ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN2_EN Value */
+ #define MXC_S_SMON_EXTSCN_EXTS_EN2_EN                  (MXC_V_SMON_EXTSCN_EXTS_EN2_EN << MXC_F_SMON_EXTSCN_EXTS_EN2_POS) /**< EXTSCN_EXTS_EN2_EN Setting */
+
+ #define MXC_F_SMON_EXTSCN_EXTS_EN3_POS                 3 /**< EXTSCN_EXTS_EN3 Position */
+ #define MXC_F_SMON_EXTSCN_EXTS_EN3                     ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN3_POS)) /**< EXTSCN_EXTS_EN3 Mask */
+ #define MXC_V_SMON_EXTSCN_EXTS_EN3_DIS                 ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN3_DIS Value */
+ #define MXC_S_SMON_EXTSCN_EXTS_EN3_DIS                 (MXC_V_SMON_EXTSCN_EXTS_EN3_DIS << MXC_F_SMON_EXTSCN_EXTS_EN3_POS) /**< EXTSCN_EXTS_EN3_DIS Setting */
+ #define MXC_V_SMON_EXTSCN_EXTS_EN3_EN                  ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN3_EN Value */
+ #define MXC_S_SMON_EXTSCN_EXTS_EN3_EN                  (MXC_V_SMON_EXTSCN_EXTS_EN3_EN << MXC_F_SMON_EXTSCN_EXTS_EN3_POS) /**< EXTSCN_EXTS_EN3_EN Setting */
+
+ #define MXC_F_SMON_EXTSCN_EXTS_EN4_POS                 4 /**< EXTSCN_EXTS_EN4 Position */
+ #define MXC_F_SMON_EXTSCN_EXTS_EN4                     ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN4_POS)) /**< EXTSCN_EXTS_EN4 Mask */
+ #define MXC_V_SMON_EXTSCN_EXTS_EN4_DIS                 ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN4_DIS Value */
+ #define MXC_S_SMON_EXTSCN_EXTS_EN4_DIS                 (MXC_V_SMON_EXTSCN_EXTS_EN4_DIS << MXC_F_SMON_EXTSCN_EXTS_EN4_POS) /**< EXTSCN_EXTS_EN4_DIS Setting */
+ #define MXC_V_SMON_EXTSCN_EXTS_EN4_EN                  ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN4_EN Value */
+ #define MXC_S_SMON_EXTSCN_EXTS_EN4_EN                  (MXC_V_SMON_EXTSCN_EXTS_EN4_EN << MXC_F_SMON_EXTSCN_EXTS_EN4_POS) /**< EXTSCN_EXTS_EN4_EN Setting */
+
+ #define MXC_F_SMON_EXTSCN_EXTS_EN5_POS                 5 /**< EXTSCN_EXTS_EN5 Position */
+ #define MXC_F_SMON_EXTSCN_EXTS_EN5                     ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN5_POS)) /**< EXTSCN_EXTS_EN5 Mask */
+ #define MXC_V_SMON_EXTSCN_EXTS_EN5_DIS                 ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN5_DIS Value */
+ #define MXC_S_SMON_EXTSCN_EXTS_EN5_DIS                 (MXC_V_SMON_EXTSCN_EXTS_EN5_DIS << MXC_F_SMON_EXTSCN_EXTS_EN5_POS) /**< EXTSCN_EXTS_EN5_DIS Setting */
+ #define MXC_V_SMON_EXTSCN_EXTS_EN5_EN                  ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN5_EN Value */
+ #define MXC_S_SMON_EXTSCN_EXTS_EN5_EN                  (MXC_V_SMON_EXTSCN_EXTS_EN5_EN << MXC_F_SMON_EXTSCN_EXTS_EN5_POS) /**< EXTSCN_EXTS_EN5_EN Setting */
+
+ #define MXC_F_SMON_EXTSCN_EXTCNT_POS                   16 /**< EXTSCN_EXTCNT Position */
+ #define MXC_F_SMON_EXTSCN_EXTCNT                       ((uint32_t)(0x1FUL << MXC_F_SMON_EXTSCN_EXTCNT_POS)) /**< EXTSCN_EXTCNT Mask */
+
+ #define MXC_F_SMON_EXTSCN_EXTFRQ_POS                   21 /**< EXTSCN_EXTFRQ Position */
+ #define MXC_F_SMON_EXTSCN_EXTFRQ                       ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_EXTFRQ_POS)) /**< EXTSCN_EXTFRQ Mask */
+ #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ            ((uint32_t)0x0UL) /**< EXTSCN_EXTFRQ_FREQ2000HZ Value */
+ #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ2000HZ            (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ2000HZ Setting */
+ #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ            ((uint32_t)0x1UL) /**< EXTSCN_EXTFRQ_FREQ1000HZ Value */
+ #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ1000HZ            (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ1000HZ Setting */
+ #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ             ((uint32_t)0x2UL) /**< EXTSCN_EXTFRQ_FREQ500HZ Value */
+ #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ500HZ             (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ500HZ Setting */
+ #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ             ((uint32_t)0x3UL) /**< EXTSCN_EXTFRQ_FREQ250HZ Value */
+ #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ250HZ             (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ250HZ Setting */
+ #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ             ((uint32_t)0x4UL) /**< EXTSCN_EXTFRQ_FREQ125HZ Value */
+ #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ125HZ             (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ125HZ Setting */
+ #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ              ((uint32_t)0x5UL) /**< EXTSCN_EXTFRQ_FREQ63HZ Value */
+ #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ63HZ              (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ63HZ Setting */
+ #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ              ((uint32_t)0x6UL) /**< EXTSCN_EXTFRQ_FREQ31HZ Value */
+ #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ31HZ              (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ31HZ Setting */
+ #define MXC_V_SMON_EXTSCN_EXTFRQ_RFU                   ((uint32_t)0x7UL) /**< EXTSCN_EXTFRQ_RFU Value */
+ #define MXC_S_SMON_EXTSCN_EXTFRQ_RFU                   (MXC_V_SMON_EXTSCN_EXTFRQ_RFU << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_RFU Setting */
+
+ #define MXC_F_SMON_EXTSCN_DIVCLK_POS                   24 /**< EXTSCN_DIVCLK Position */
+ #define MXC_F_SMON_EXTSCN_DIVCLK                       ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_DIVCLK_POS)) /**< EXTSCN_DIVCLK Mask */
+ #define MXC_V_SMON_EXTSCN_DIVCLK_DIV1                  ((uint32_t)0x0UL) /**< EXTSCN_DIVCLK_DIV1 Value */
+ #define MXC_S_SMON_EXTSCN_DIVCLK_DIV1                  (MXC_V_SMON_EXTSCN_DIVCLK_DIV1 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV1 Setting */
+ #define MXC_V_SMON_EXTSCN_DIVCLK_DIV2                  ((uint32_t)0x1UL) /**< EXTSCN_DIVCLK_DIV2 Value */
+ #define MXC_S_SMON_EXTSCN_DIVCLK_DIV2                  (MXC_V_SMON_EXTSCN_DIVCLK_DIV2 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV2 Setting */
+ #define MXC_V_SMON_EXTSCN_DIVCLK_DIV4                  ((uint32_t)0x2UL) /**< EXTSCN_DIVCLK_DIV4 Value */
+ #define MXC_S_SMON_EXTSCN_DIVCLK_DIV4                  (MXC_V_SMON_EXTSCN_DIVCLK_DIV4 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV4 Setting */
+ #define MXC_V_SMON_EXTSCN_DIVCLK_DIV8                  ((uint32_t)0x3UL) /**< EXTSCN_DIVCLK_DIV8 Value */
+ #define MXC_S_SMON_EXTSCN_DIVCLK_DIV8                  (MXC_V_SMON_EXTSCN_DIVCLK_DIV8 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV8 Setting */
+ #define MXC_V_SMON_EXTSCN_DIVCLK_DIV16                 ((uint32_t)0x4UL) /**< EXTSCN_DIVCLK_DIV16 Value */
+ #define MXC_S_SMON_EXTSCN_DIVCLK_DIV16                 (MXC_V_SMON_EXTSCN_DIVCLK_DIV16 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV16 Setting */
+ #define MXC_V_SMON_EXTSCN_DIVCLK_DIV32                 ((uint32_t)0x5UL) /**< EXTSCN_DIVCLK_DIV32 Value */
+ #define MXC_S_SMON_EXTSCN_DIVCLK_DIV32                 (MXC_V_SMON_EXTSCN_DIVCLK_DIV32 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV32 Setting */
+ #define MXC_V_SMON_EXTSCN_DIVCLK_DIV64                 ((uint32_t)0x6UL) /**< EXTSCN_DIVCLK_DIV64 Value */
+ #define MXC_S_SMON_EXTSCN_DIVCLK_DIV64                 (MXC_V_SMON_EXTSCN_DIVCLK_DIV64 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV64 Setting */
+
+ #define MXC_F_SMON_EXTSCN_BUSY_POS                     30 /**< EXTSCN_BUSY Position */
+ #define MXC_F_SMON_EXTSCN_BUSY                         ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_BUSY_POS)) /**< EXTSCN_BUSY Mask */
+ #define MXC_V_SMON_EXTSCN_BUSY_IDLE                    ((uint32_t)0x0UL) /**< EXTSCN_BUSY_IDLE Value */
+ #define MXC_S_SMON_EXTSCN_BUSY_IDLE                    (MXC_V_SMON_EXTSCN_BUSY_IDLE << MXC_F_SMON_EXTSCN_BUSY_POS) /**< EXTSCN_BUSY_IDLE Setting */
+ #define MXC_V_SMON_EXTSCN_BUSY_BUSY                    ((uint32_t)0x1UL) /**< EXTSCN_BUSY_BUSY Value */
+ #define MXC_S_SMON_EXTSCN_BUSY_BUSY                    (MXC_V_SMON_EXTSCN_BUSY_BUSY << MXC_F_SMON_EXTSCN_BUSY_POS) /**< EXTSCN_BUSY_BUSY Setting */
+
+ #define MXC_F_SMON_EXTSCN_LOCK_POS                     31 /**< EXTSCN_LOCK Position */
+ #define MXC_F_SMON_EXTSCN_LOCK                         ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_LOCK_POS)) /**< EXTSCN_LOCK Mask */
+ #define MXC_V_SMON_EXTSCN_LOCK_UNLOCKED                ((uint32_t)0x0UL) /**< EXTSCN_LOCK_UNLOCKED Value */
+ #define MXC_S_SMON_EXTSCN_LOCK_UNLOCKED                (MXC_V_SMON_EXTSCN_LOCK_UNLOCKED << MXC_F_SMON_EXTSCN_LOCK_POS) /**< EXTSCN_LOCK_UNLOCKED Setting */
+ #define MXC_V_SMON_EXTSCN_LOCK_LOCKED                  ((uint32_t)0x1UL) /**< EXTSCN_LOCK_LOCKED Value */
+ #define MXC_S_SMON_EXTSCN_LOCK_LOCKED                  (MXC_V_SMON_EXTSCN_LOCK_LOCKED << MXC_F_SMON_EXTSCN_LOCK_POS) /**< EXTSCN_LOCK_LOCKED Setting */
+
+/**@} end of group SMON_EXTSCN_Register */
+
+/**
+ * @ingroup  smon_registers
+ * @defgroup SMON_INTSCN SMON_INTSCN
+ * @brief    Internal Sensor Control Register.
+ * @{
+ */
+ #define MXC_F_SMON_INTSCN_SHIELD_EN_POS                0 /**< INTSCN_SHIELD_EN Position */
+ #define MXC_F_SMON_INTSCN_SHIELD_EN                    ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_SHIELD_EN_POS)) /**< INTSCN_SHIELD_EN Mask */
+ #define MXC_V_SMON_INTSCN_SHIELD_EN_DIS                ((uint32_t)0x0UL) /**< INTSCN_SHIELD_EN_DIS Value */
+ #define MXC_S_SMON_INTSCN_SHIELD_EN_DIS                (MXC_V_SMON_INTSCN_SHIELD_EN_DIS << MXC_F_SMON_INTSCN_SHIELD_EN_POS) /**< INTSCN_SHIELD_EN_DIS Setting */
+ #define MXC_V_SMON_INTSCN_SHIELD_EN_EN                 ((uint32_t)0x1UL) /**< INTSCN_SHIELD_EN_EN Value */
+ #define MXC_S_SMON_INTSCN_SHIELD_EN_EN                 (MXC_V_SMON_INTSCN_SHIELD_EN_EN << MXC_F_SMON_INTSCN_SHIELD_EN_POS) /**< INTSCN_SHIELD_EN_EN Setting */
+
+ #define MXC_F_SMON_INTSCN_TEMP_EN_POS                  1 /**< INTSCN_TEMP_EN Position */
+ #define MXC_F_SMON_INTSCN_TEMP_EN                      ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_TEMP_EN_POS)) /**< INTSCN_TEMP_EN Mask */
+ #define MXC_V_SMON_INTSCN_TEMP_EN_DIS                  ((uint32_t)0x0UL) /**< INTSCN_TEMP_EN_DIS Value */
+ #define MXC_S_SMON_INTSCN_TEMP_EN_DIS                  (MXC_V_SMON_INTSCN_TEMP_EN_DIS << MXC_F_SMON_INTSCN_TEMP_EN_POS) /**< INTSCN_TEMP_EN_DIS Setting */
+ #define MXC_V_SMON_INTSCN_TEMP_EN_EN                   ((uint32_t)0x1UL) /**< INTSCN_TEMP_EN_EN Value */
+ #define MXC_S_SMON_INTSCN_TEMP_EN_EN                   (MXC_V_SMON_INTSCN_TEMP_EN_EN << MXC_F_SMON_INTSCN_TEMP_EN_POS) /**< INTSCN_TEMP_EN_EN Setting */
+
+ #define MXC_F_SMON_INTSCN_VBAT_EN_POS                  2 /**< INTSCN_VBAT_EN Position */
+ #define MXC_F_SMON_INTSCN_VBAT_EN                      ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VBAT_EN_POS)) /**< INTSCN_VBAT_EN Mask */
+ #define MXC_V_SMON_INTSCN_VBAT_EN_DIS                  ((uint32_t)0x0UL) /**< INTSCN_VBAT_EN_DIS Value */
+ #define MXC_S_SMON_INTSCN_VBAT_EN_DIS                  (MXC_V_SMON_INTSCN_VBAT_EN_DIS << MXC_F_SMON_INTSCN_VBAT_EN_POS) /**< INTSCN_VBAT_EN_DIS Setting */
+ #define MXC_V_SMON_INTSCN_VBAT_EN_EN                   ((uint32_t)0x1UL) /**< INTSCN_VBAT_EN_EN Value */
+ #define MXC_S_SMON_INTSCN_VBAT_EN_EN                   (MXC_V_SMON_INTSCN_VBAT_EN_EN << MXC_F_SMON_INTSCN_VBAT_EN_POS) /**< INTSCN_VBAT_EN_EN Setting */
+
+ #define MXC_F_SMON_INTSCN_LOTEMP_SEL_POS               16 /**< INTSCN_LOTEMP_SEL Position */
+ #define MXC_F_SMON_INTSCN_LOTEMP_SEL                   ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS)) /**< INTSCN_LOTEMP_SEL Mask */
+ #define MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG50C            ((uint32_t)0x0UL) /**< INTSCN_LOTEMP_SEL_NEG50C Value */
+ #define MXC_S_SMON_INTSCN_LOTEMP_SEL_NEG50C            (MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG50C << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS) /**< INTSCN_LOTEMP_SEL_NEG50C Setting */
+ #define MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG30C            ((uint32_t)0x1UL) /**< INTSCN_LOTEMP_SEL_NEG30C Value */
+ #define MXC_S_SMON_INTSCN_LOTEMP_SEL_NEG30C            (MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG30C << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS) /**< INTSCN_LOTEMP_SEL_NEG30C Setting */
+
+ #define MXC_F_SMON_INTSCN_VCORELOEN_POS                18 /**< INTSCN_VCORELOEN Position */
+ #define MXC_F_SMON_INTSCN_VCORELOEN                    ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCORELOEN_POS)) /**< INTSCN_VCORELOEN Mask */
+ #define MXC_V_SMON_INTSCN_VCORELOEN_DIS                ((uint32_t)0x0UL) /**< INTSCN_VCORELOEN_DIS Value */
+ #define MXC_S_SMON_INTSCN_VCORELOEN_DIS                (MXC_V_SMON_INTSCN_VCORELOEN_DIS << MXC_F_SMON_INTSCN_VCORELOEN_POS) /**< INTSCN_VCORELOEN_DIS Setting */
+ #define MXC_V_SMON_INTSCN_VCORELOEN_EN                 ((uint32_t)0x1UL) /**< INTSCN_VCORELOEN_EN Value */
+ #define MXC_S_SMON_INTSCN_VCORELOEN_EN                 (MXC_V_SMON_INTSCN_VCORELOEN_EN << MXC_F_SMON_INTSCN_VCORELOEN_POS) /**< INTSCN_VCORELOEN_EN Setting */
+
+ #define MXC_F_SMON_INTSCN_VCOREHIEN_POS                19 /**< INTSCN_VCOREHIEN Position */
+ #define MXC_F_SMON_INTSCN_VCOREHIEN                    ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCOREHIEN_POS)) /**< INTSCN_VCOREHIEN Mask */
+ #define MXC_V_SMON_INTSCN_VCOREHIEN_DIS                ((uint32_t)0x0UL) /**< INTSCN_VCOREHIEN_DIS Value */
+ #define MXC_S_SMON_INTSCN_VCOREHIEN_DIS                (MXC_V_SMON_INTSCN_VCOREHIEN_DIS << MXC_F_SMON_INTSCN_VCOREHIEN_POS) /**< INTSCN_VCOREHIEN_DIS Setting */
+ #define MXC_V_SMON_INTSCN_VCOREHIEN_EN                 ((uint32_t)0x1UL) /**< INTSCN_VCOREHIEN_EN Value */
+ #define MXC_S_SMON_INTSCN_VCOREHIEN_EN                 (MXC_V_SMON_INTSCN_VCOREHIEN_EN << MXC_F_SMON_INTSCN_VCOREHIEN_POS) /**< INTSCN_VCOREHIEN_EN Setting */
+
+ #define MXC_F_SMON_INTSCN_VDDLOEN_POS                  20 /**< INTSCN_VDDLOEN Position */
+ #define MXC_F_SMON_INTSCN_VDDLOEN                      ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDLOEN_POS)) /**< INTSCN_VDDLOEN Mask */
+ #define MXC_V_SMON_INTSCN_VDDLOEN_DIS                  ((uint32_t)0x0UL) /**< INTSCN_VDDLOEN_DIS Value */
+ #define MXC_S_SMON_INTSCN_VDDLOEN_DIS                  (MXC_V_SMON_INTSCN_VDDLOEN_DIS << MXC_F_SMON_INTSCN_VDDLOEN_POS) /**< INTSCN_VDDLOEN_DIS Setting */
+ #define MXC_V_SMON_INTSCN_VDDLOEN_EN                   ((uint32_t)0x1UL) /**< INTSCN_VDDLOEN_EN Value */
+ #define MXC_S_SMON_INTSCN_VDDLOEN_EN                   (MXC_V_SMON_INTSCN_VDDLOEN_EN << MXC_F_SMON_INTSCN_VDDLOEN_POS) /**< INTSCN_VDDLOEN_EN Setting */
+
+ #define MXC_F_SMON_INTSCN_VDDHIEN_POS                  21 /**< INTSCN_VDDHIEN Position */
+ #define MXC_F_SMON_INTSCN_VDDHIEN                      ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDHIEN_POS)) /**< INTSCN_VDDHIEN Mask */
+ #define MXC_V_SMON_INTSCN_VDDHIEN_DIS                  ((uint32_t)0x0UL) /**< INTSCN_VDDHIEN_DIS Value */
+ #define MXC_S_SMON_INTSCN_VDDHIEN_DIS                  (MXC_V_SMON_INTSCN_VDDHIEN_DIS << MXC_F_SMON_INTSCN_VDDHIEN_POS) /**< INTSCN_VDDHIEN_DIS Setting */
+ #define MXC_V_SMON_INTSCN_VDDHIEN_EN                   ((uint32_t)0x1UL) /**< INTSCN_VDDHIEN_EN Value */
+ #define MXC_S_SMON_INTSCN_VDDHIEN_EN                   (MXC_V_SMON_INTSCN_VDDHIEN_EN << MXC_F_SMON_INTSCN_VDDHIEN_POS) /**< INTSCN_VDDHIEN_EN Setting */
+
+ #define MXC_F_SMON_INTSCN_VGLEN_POS                    22 /**< INTSCN_VGLEN Position */
+ #define MXC_F_SMON_INTSCN_VGLEN                        ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VGLEN_POS)) /**< INTSCN_VGLEN Mask */
+ #define MXC_V_SMON_INTSCN_VGLEN_DIS                    ((uint32_t)0x0UL) /**< INTSCN_VGLEN_DIS Value */
+ #define MXC_S_SMON_INTSCN_VGLEN_DIS                    (MXC_V_SMON_INTSCN_VGLEN_DIS << MXC_F_SMON_INTSCN_VGLEN_POS) /**< INTSCN_VGLEN_DIS Setting */
+ #define MXC_V_SMON_INTSCN_VGLEN_EN                     ((uint32_t)0x1UL) /**< INTSCN_VGLEN_EN Value */
+ #define MXC_S_SMON_INTSCN_VGLEN_EN                     (MXC_V_SMON_INTSCN_VGLEN_EN << MXC_F_SMON_INTSCN_VGLEN_POS) /**< INTSCN_VGLEN_EN Setting */
+
+ #define MXC_F_SMON_INTSCN_LOCK_POS                     31 /**< INTSCN_LOCK Position */
+ #define MXC_F_SMON_INTSCN_LOCK                         ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOCK_POS)) /**< INTSCN_LOCK Mask */
+ #define MXC_V_SMON_INTSCN_LOCK_UNLOCKED                ((uint32_t)0x0UL) /**< INTSCN_LOCK_UNLOCKED Value */
+ #define MXC_S_SMON_INTSCN_LOCK_UNLOCKED                (MXC_V_SMON_INTSCN_LOCK_UNLOCKED << MXC_F_SMON_INTSCN_LOCK_POS) /**< INTSCN_LOCK_UNLOCKED Setting */
+ #define MXC_V_SMON_INTSCN_LOCK_LOCKED                  ((uint32_t)0x1UL) /**< INTSCN_LOCK_LOCKED Value */
+ #define MXC_S_SMON_INTSCN_LOCK_LOCKED                  (MXC_V_SMON_INTSCN_LOCK_LOCKED << MXC_F_SMON_INTSCN_LOCK_POS) /**< INTSCN_LOCK_LOCKED Setting */
+
+/**@} end of group SMON_INTSCN_Register */
+
+/**
+ * @ingroup  smon_registers
+ * @defgroup SMON_SECALM SMON_SECALM
+ * @brief    Security Alarm Register.
+ * @{
+ */
+ #define MXC_F_SMON_SECALM_DRS_POS                      0 /**< SECALM_DRS Position */
+ #define MXC_F_SMON_SECALM_DRS                          ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_DRS_POS)) /**< SECALM_DRS Mask */
+ #define MXC_V_SMON_SECALM_DRS_COMPLETE                 ((uint32_t)0x0UL) /**< SECALM_DRS_COMPLETE Value */
+ #define MXC_S_SMON_SECALM_DRS_COMPLETE                 (MXC_V_SMON_SECALM_DRS_COMPLETE << MXC_F_SMON_SECALM_DRS_POS) /**< SECALM_DRS_COMPLETE Setting */
+ #define MXC_V_SMON_SECALM_DRS_START                    ((uint32_t)0x1UL) /**< SECALM_DRS_START Value */
+ #define MXC_S_SMON_SECALM_DRS_START                    (MXC_V_SMON_SECALM_DRS_START << MXC_F_SMON_SECALM_DRS_POS) /**< SECALM_DRS_START Setting */
+
+ #define MXC_F_SMON_SECALM_KEYWIPE_POS                  1 /**< SECALM_KEYWIPE Position */
+ #define MXC_F_SMON_SECALM_KEYWIPE                      ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_KEYWIPE_POS)) /**< SECALM_KEYWIPE Mask */
+ #define MXC_V_SMON_SECALM_KEYWIPE_COMPLETE             ((uint32_t)0x0UL) /**< SECALM_KEYWIPE_COMPLETE Value */
+ #define MXC_S_SMON_SECALM_KEYWIPE_COMPLETE             (MXC_V_SMON_SECALM_KEYWIPE_COMPLETE << MXC_F_SMON_SECALM_KEYWIPE_POS) /**< SECALM_KEYWIPE_COMPLETE Setting */
+ #define MXC_V_SMON_SECALM_KEYWIPE_START                ((uint32_t)0x1UL) /**< SECALM_KEYWIPE_START Value */
+ #define MXC_S_SMON_SECALM_KEYWIPE_START                (MXC_V_SMON_SECALM_KEYWIPE_START << MXC_F_SMON_SECALM_KEYWIPE_POS) /**< SECALM_KEYWIPE_START Setting */
+
+ #define MXC_F_SMON_SECALM_SHIELDF_POS                  2 /**< SECALM_SHIELDF Position */
+ #define MXC_F_SMON_SECALM_SHIELDF                      ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_SHIELDF_POS)) /**< SECALM_SHIELDF Mask */
+ #define MXC_V_SMON_SECALM_SHIELDF_NOEVENT              ((uint32_t)0x0UL) /**< SECALM_SHIELDF_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_SHIELDF_NOEVENT              (MXC_V_SMON_SECALM_SHIELDF_NOEVENT << MXC_F_SMON_SECALM_SHIELDF_POS) /**< SECALM_SHIELDF_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_SHIELDF_OCCURRED             ((uint32_t)0x1UL) /**< SECALM_SHIELDF_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_SHIELDF_OCCURRED             (MXC_V_SMON_SECALM_SHIELDF_OCCURRED << MXC_F_SMON_SECALM_SHIELDF_POS) /**< SECALM_SHIELDF_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_LOTEMP_POS                   3 /**< SECALM_LOTEMP Position */
+ #define MXC_F_SMON_SECALM_LOTEMP                       ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_LOTEMP_POS)) /**< SECALM_LOTEMP Mask */
+ #define MXC_V_SMON_SECALM_LOTEMP_NOEVENT               ((uint32_t)0x0UL) /**< SECALM_LOTEMP_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_LOTEMP_NOEVENT               (MXC_V_SMON_SECALM_LOTEMP_NOEVENT << MXC_F_SMON_SECALM_LOTEMP_POS) /**< SECALM_LOTEMP_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_LOTEMP_OCCURRED              ((uint32_t)0x1UL) /**< SECALM_LOTEMP_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_LOTEMP_OCCURRED              (MXC_V_SMON_SECALM_LOTEMP_OCCURRED << MXC_F_SMON_SECALM_LOTEMP_POS) /**< SECALM_LOTEMP_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_HITEMP_POS                   4 /**< SECALM_HITEMP Position */
+ #define MXC_F_SMON_SECALM_HITEMP                       ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_HITEMP_POS)) /**< SECALM_HITEMP Mask */
+ #define MXC_V_SMON_SECALM_HITEMP_NOEVENT               ((uint32_t)0x0UL) /**< SECALM_HITEMP_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_HITEMP_NOEVENT               (MXC_V_SMON_SECALM_HITEMP_NOEVENT << MXC_F_SMON_SECALM_HITEMP_POS) /**< SECALM_HITEMP_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_HITEMP_OCCURRED              ((uint32_t)0x1UL) /**< SECALM_HITEMP_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_HITEMP_OCCURRED              (MXC_V_SMON_SECALM_HITEMP_OCCURRED << MXC_F_SMON_SECALM_HITEMP_POS) /**< SECALM_HITEMP_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_BATLO_POS                    5 /**< SECALM_BATLO Position */
+ #define MXC_F_SMON_SECALM_BATLO                        ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATLO_POS)) /**< SECALM_BATLO Mask */
+ #define MXC_V_SMON_SECALM_BATLO_NOEVENT                ((uint32_t)0x0UL) /**< SECALM_BATLO_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_BATLO_NOEVENT                (MXC_V_SMON_SECALM_BATLO_NOEVENT << MXC_F_SMON_SECALM_BATLO_POS) /**< SECALM_BATLO_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_BATLO_OCCURRED               ((uint32_t)0x1UL) /**< SECALM_BATLO_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_BATLO_OCCURRED               (MXC_V_SMON_SECALM_BATLO_OCCURRED << MXC_F_SMON_SECALM_BATLO_POS) /**< SECALM_BATLO_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_BATHI_POS                    6 /**< SECALM_BATHI Position */
+ #define MXC_F_SMON_SECALM_BATHI                        ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATHI_POS)) /**< SECALM_BATHI Mask */
+ #define MXC_V_SMON_SECALM_BATHI_NOEVENT                ((uint32_t)0x0UL) /**< SECALM_BATHI_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_BATHI_NOEVENT                (MXC_V_SMON_SECALM_BATHI_NOEVENT << MXC_F_SMON_SECALM_BATHI_POS) /**< SECALM_BATHI_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_BATHI_OCCURRED               ((uint32_t)0x1UL) /**< SECALM_BATHI_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_BATHI_OCCURRED               (MXC_V_SMON_SECALM_BATHI_OCCURRED << MXC_F_SMON_SECALM_BATHI_POS) /**< SECALM_BATHI_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTF_POS                     7 /**< SECALM_EXTF Position */
+ #define MXC_F_SMON_SECALM_EXTF                         ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTF_POS)) /**< SECALM_EXTF Mask */
+ #define MXC_V_SMON_SECALM_EXTF_NOEVENT                 ((uint32_t)0x0UL) /**< SECALM_EXTF_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTF_NOEVENT                 (MXC_V_SMON_SECALM_EXTF_NOEVENT << MXC_F_SMON_SECALM_EXTF_POS) /**< SECALM_EXTF_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTF_OCCURRED                ((uint32_t)0x1UL) /**< SECALM_EXTF_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTF_OCCURRED                (MXC_V_SMON_SECALM_EXTF_OCCURRED << MXC_F_SMON_SECALM_EXTF_POS) /**< SECALM_EXTF_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_VDDLO_POS                    8 /**< SECALM_VDDLO Position */
+ #define MXC_F_SMON_SECALM_VDDLO                        ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDLO_POS)) /**< SECALM_VDDLO Mask */
+ #define MXC_V_SMON_SECALM_VDDLO_NOEVENT                ((uint32_t)0x0UL) /**< SECALM_VDDLO_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_VDDLO_NOEVENT                (MXC_V_SMON_SECALM_VDDLO_NOEVENT << MXC_F_SMON_SECALM_VDDLO_POS) /**< SECALM_VDDLO_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_VDDLO_OCCURRED               ((uint32_t)0x1UL) /**< SECALM_VDDLO_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_VDDLO_OCCURRED               (MXC_V_SMON_SECALM_VDDLO_OCCURRED << MXC_F_SMON_SECALM_VDDLO_POS) /**< SECALM_VDDLO_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_VCORELO_POS                  9 /**< SECALM_VCORELO Position */
+ #define MXC_F_SMON_SECALM_VCORELO                      ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCORELO_POS)) /**< SECALM_VCORELO Mask */
+ #define MXC_V_SMON_SECALM_VCORELO_NOEVENT              ((uint32_t)0x0UL) /**< SECALM_VCORELO_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_VCORELO_NOEVENT              (MXC_V_SMON_SECALM_VCORELO_NOEVENT << MXC_F_SMON_SECALM_VCORELO_POS) /**< SECALM_VCORELO_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_VCORELO_OCCURRED             ((uint32_t)0x1UL) /**< SECALM_VCORELO_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_VCORELO_OCCURRED             (MXC_V_SMON_SECALM_VCORELO_OCCURRED << MXC_F_SMON_SECALM_VCORELO_POS) /**< SECALM_VCORELO_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_VCOREHI_POS                  10 /**< SECALM_VCOREHI Position */
+ #define MXC_F_SMON_SECALM_VCOREHI                      ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCOREHI_POS)) /**< SECALM_VCOREHI Mask */
+ #define MXC_V_SMON_SECALM_VCOREHI_NOEVENT              ((uint32_t)0x0UL) /**< SECALM_VCOREHI_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_VCOREHI_NOEVENT              (MXC_V_SMON_SECALM_VCOREHI_NOEVENT << MXC_F_SMON_SECALM_VCOREHI_POS) /**< SECALM_VCOREHI_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_VCOREHI_OCCURRED             ((uint32_t)0x1UL) /**< SECALM_VCOREHI_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_VCOREHI_OCCURRED             (MXC_V_SMON_SECALM_VCOREHI_OCCURRED << MXC_F_SMON_SECALM_VCOREHI_POS) /**< SECALM_VCOREHI_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_VDDHI_POS                    11 /**< SECALM_VDDHI Position */
+ #define MXC_F_SMON_SECALM_VDDHI                        ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDHI_POS)) /**< SECALM_VDDHI Mask */
+ #define MXC_V_SMON_SECALM_VDDHI_NOEVENT                ((uint32_t)0x0UL) /**< SECALM_VDDHI_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_VDDHI_NOEVENT                (MXC_V_SMON_SECALM_VDDHI_NOEVENT << MXC_F_SMON_SECALM_VDDHI_POS) /**< SECALM_VDDHI_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_VDDHI_OCCURRED               ((uint32_t)0x1UL) /**< SECALM_VDDHI_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_VDDHI_OCCURRED               (MXC_V_SMON_SECALM_VDDHI_OCCURRED << MXC_F_SMON_SECALM_VDDHI_POS) /**< SECALM_VDDHI_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_VGL_POS                      12 /**< SECALM_VGL Position */
+ #define MXC_F_SMON_SECALM_VGL                          ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VGL_POS)) /**< SECALM_VGL Mask */
+ #define MXC_V_SMON_SECALM_VGL_NOEVENT                  ((uint32_t)0x0UL) /**< SECALM_VGL_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_VGL_NOEVENT                  (MXC_V_SMON_SECALM_VGL_NOEVENT << MXC_F_SMON_SECALM_VGL_POS) /**< SECALM_VGL_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_VGL_OCCURRED                 ((uint32_t)0x1UL) /**< SECALM_VGL_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_VGL_OCCURRED                 (MXC_V_SMON_SECALM_VGL_OCCURRED << MXC_F_SMON_SECALM_VGL_POS) /**< SECALM_VGL_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTSTAT0_POS                 16 /**< SECALM_EXTSTAT0 Position */
+ #define MXC_F_SMON_SECALM_EXTSTAT0                     ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT0_POS)) /**< SECALM_EXTSTAT0 Mask */
+ #define MXC_V_SMON_SECALM_EXTSTAT0_NOEVENT             ((uint32_t)0x0UL) /**< SECALM_EXTSTAT0_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTSTAT0_NOEVENT             (MXC_V_SMON_SECALM_EXTSTAT0_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT0_POS) /**< SECALM_EXTSTAT0_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTSTAT0_OCCURRED            ((uint32_t)0x1UL) /**< SECALM_EXTSTAT0_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTSTAT0_OCCURRED            (MXC_V_SMON_SECALM_EXTSTAT0_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT0_POS) /**< SECALM_EXTSTAT0_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTSTAT1_POS                 17 /**< SECALM_EXTSTAT1 Position */
+ #define MXC_F_SMON_SECALM_EXTSTAT1                     ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT1_POS)) /**< SECALM_EXTSTAT1 Mask */
+ #define MXC_V_SMON_SECALM_EXTSTAT1_NOEVENT             ((uint32_t)0x0UL) /**< SECALM_EXTSTAT1_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTSTAT1_NOEVENT             (MXC_V_SMON_SECALM_EXTSTAT1_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT1_POS) /**< SECALM_EXTSTAT1_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTSTAT1_OCCURRED            ((uint32_t)0x1UL) /**< SECALM_EXTSTAT1_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTSTAT1_OCCURRED            (MXC_V_SMON_SECALM_EXTSTAT1_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT1_POS) /**< SECALM_EXTSTAT1_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTSTAT2_POS                 18 /**< SECALM_EXTSTAT2 Position */
+ #define MXC_F_SMON_SECALM_EXTSTAT2                     ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT2_POS)) /**< SECALM_EXTSTAT2 Mask */
+ #define MXC_V_SMON_SECALM_EXTSTAT2_NOEVENT             ((uint32_t)0x0UL) /**< SECALM_EXTSTAT2_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTSTAT2_NOEVENT             (MXC_V_SMON_SECALM_EXTSTAT2_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT2_POS) /**< SECALM_EXTSTAT2_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTSTAT2_OCCURRED            ((uint32_t)0x1UL) /**< SECALM_EXTSTAT2_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTSTAT2_OCCURRED            (MXC_V_SMON_SECALM_EXTSTAT2_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT2_POS) /**< SECALM_EXTSTAT2_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTSTAT3_POS                 19 /**< SECALM_EXTSTAT3 Position */
+ #define MXC_F_SMON_SECALM_EXTSTAT3                     ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT3_POS)) /**< SECALM_EXTSTAT3 Mask */
+ #define MXC_V_SMON_SECALM_EXTSTAT3_NOEVENT             ((uint32_t)0x0UL) /**< SECALM_EXTSTAT3_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTSTAT3_NOEVENT             (MXC_V_SMON_SECALM_EXTSTAT3_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT3_POS) /**< SECALM_EXTSTAT3_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTSTAT3_OCCURRED            ((uint32_t)0x1UL) /**< SECALM_EXTSTAT3_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTSTAT3_OCCURRED            (MXC_V_SMON_SECALM_EXTSTAT3_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT3_POS) /**< SECALM_EXTSTAT3_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTSTAT4_POS                 20 /**< SECALM_EXTSTAT4 Position */
+ #define MXC_F_SMON_SECALM_EXTSTAT4                     ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT4_POS)) /**< SECALM_EXTSTAT4 Mask */
+ #define MXC_V_SMON_SECALM_EXTSTAT4_NOEVENT             ((uint32_t)0x0UL) /**< SECALM_EXTSTAT4_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTSTAT4_NOEVENT             (MXC_V_SMON_SECALM_EXTSTAT4_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT4_POS) /**< SECALM_EXTSTAT4_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTSTAT4_OCCURRED            ((uint32_t)0x1UL) /**< SECALM_EXTSTAT4_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTSTAT4_OCCURRED            (MXC_V_SMON_SECALM_EXTSTAT4_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT4_POS) /**< SECALM_EXTSTAT4_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTSTAT5_POS                 21 /**< SECALM_EXTSTAT5 Position */
+ #define MXC_F_SMON_SECALM_EXTSTAT5                     ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT5_POS)) /**< SECALM_EXTSTAT5 Mask */
+ #define MXC_V_SMON_SECALM_EXTSTAT5_NOEVENT             ((uint32_t)0x0UL) /**< SECALM_EXTSTAT5_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTSTAT5_NOEVENT             (MXC_V_SMON_SECALM_EXTSTAT5_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT5_POS) /**< SECALM_EXTSTAT5_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTSTAT5_OCCURRED            ((uint32_t)0x1UL) /**< SECALM_EXTSTAT5_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTSTAT5_OCCURRED            (MXC_V_SMON_SECALM_EXTSTAT5_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT5_POS) /**< SECALM_EXTSTAT5_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTSWARN0_POS                24 /**< SECALM_EXTSWARN0 Position */
+ #define MXC_F_SMON_SECALM_EXTSWARN0                    ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN0_POS)) /**< SECALM_EXTSWARN0 Mask */
+ #define MXC_V_SMON_SECALM_EXTSWARN0_NOEVENT            ((uint32_t)0x0UL) /**< SECALM_EXTSWARN0_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTSWARN0_NOEVENT            (MXC_V_SMON_SECALM_EXTSWARN0_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN0_POS) /**< SECALM_EXTSWARN0_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTSWARN0_OCCURRED           ((uint32_t)0x1UL) /**< SECALM_EXTSWARN0_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTSWARN0_OCCURRED           (MXC_V_SMON_SECALM_EXTSWARN0_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN0_POS) /**< SECALM_EXTSWARN0_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTSWARN1_POS                25 /**< SECALM_EXTSWARN1 Position */
+ #define MXC_F_SMON_SECALM_EXTSWARN1                    ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN1_POS)) /**< SECALM_EXTSWARN1 Mask */
+ #define MXC_V_SMON_SECALM_EXTSWARN1_NOEVENT            ((uint32_t)0x0UL) /**< SECALM_EXTSWARN1_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTSWARN1_NOEVENT            (MXC_V_SMON_SECALM_EXTSWARN1_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN1_POS) /**< SECALM_EXTSWARN1_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTSWARN1_OCCURRED           ((uint32_t)0x1UL) /**< SECALM_EXTSWARN1_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTSWARN1_OCCURRED           (MXC_V_SMON_SECALM_EXTSWARN1_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN1_POS) /**< SECALM_EXTSWARN1_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTSWARN2_POS                26 /**< SECALM_EXTSWARN2 Position */
+ #define MXC_F_SMON_SECALM_EXTSWARN2                    ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN2_POS)) /**< SECALM_EXTSWARN2 Mask */
+ #define MXC_V_SMON_SECALM_EXTSWARN2_NOEVENT            ((uint32_t)0x0UL) /**< SECALM_EXTSWARN2_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTSWARN2_NOEVENT            (MXC_V_SMON_SECALM_EXTSWARN2_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN2_POS) /**< SECALM_EXTSWARN2_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTSWARN2_OCCURRED           ((uint32_t)0x1UL) /**< SECALM_EXTSWARN2_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTSWARN2_OCCURRED           (MXC_V_SMON_SECALM_EXTSWARN2_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN2_POS) /**< SECALM_EXTSWARN2_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTSWARN3_POS                27 /**< SECALM_EXTSWARN3 Position */
+ #define MXC_F_SMON_SECALM_EXTSWARN3                    ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN3_POS)) /**< SECALM_EXTSWARN3 Mask */
+ #define MXC_V_SMON_SECALM_EXTSWARN3_NOEVENT            ((uint32_t)0x0UL) /**< SECALM_EXTSWARN3_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTSWARN3_NOEVENT            (MXC_V_SMON_SECALM_EXTSWARN3_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN3_POS) /**< SECALM_EXTSWARN3_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTSWARN3_OCCURRED           ((uint32_t)0x1UL) /**< SECALM_EXTSWARN3_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTSWARN3_OCCURRED           (MXC_V_SMON_SECALM_EXTSWARN3_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN3_POS) /**< SECALM_EXTSWARN3_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTSWARN4_POS                28 /**< SECALM_EXTSWARN4 Position */
+ #define MXC_F_SMON_SECALM_EXTSWARN4                    ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN4_POS)) /**< SECALM_EXTSWARN4 Mask */
+ #define MXC_V_SMON_SECALM_EXTSWARN4_NOEVENT            ((uint32_t)0x0UL) /**< SECALM_EXTSWARN4_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTSWARN4_NOEVENT            (MXC_V_SMON_SECALM_EXTSWARN4_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN4_POS) /**< SECALM_EXTSWARN4_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTSWARN4_OCCURRED           ((uint32_t)0x1UL) /**< SECALM_EXTSWARN4_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTSWARN4_OCCURRED           (MXC_V_SMON_SECALM_EXTSWARN4_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN4_POS) /**< SECALM_EXTSWARN4_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECALM_EXTSWARN5_POS                29 /**< SECALM_EXTSWARN5 Position */
+ #define MXC_F_SMON_SECALM_EXTSWARN5                    ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN5_POS)) /**< SECALM_EXTSWARN5 Mask */
+ #define MXC_V_SMON_SECALM_EXTSWARN5_NOEVENT            ((uint32_t)0x0UL) /**< SECALM_EXTSWARN5_NOEVENT Value */
+ #define MXC_S_SMON_SECALM_EXTSWARN5_NOEVENT            (MXC_V_SMON_SECALM_EXTSWARN5_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN5_POS) /**< SECALM_EXTSWARN5_NOEVENT Setting */
+ #define MXC_V_SMON_SECALM_EXTSWARN5_OCCURRED           ((uint32_t)0x1UL) /**< SECALM_EXTSWARN5_OCCURRED Value */
+ #define MXC_S_SMON_SECALM_EXTSWARN5_OCCURRED           (MXC_V_SMON_SECALM_EXTSWARN5_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN5_POS) /**< SECALM_EXTSWARN5_OCCURRED Setting */
+
+/**@} end of group SMON_SECALM_Register */
+
+/**
+ * @ingroup  smon_registers
+ * @defgroup SMON_SECDIAG SMON_SECDIAG
+ * @brief    Security Diagnostic Register.
+ * @{
+ */
+ #define MXC_F_SMON_SECDIAG_BORF_POS                    0 /**< SECDIAG_BORF Position */
+ #define MXC_F_SMON_SECDIAG_BORF                        ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BORF_POS)) /**< SECDIAG_BORF Mask */
+ #define MXC_V_SMON_SECDIAG_BORF_NOEVENT                ((uint32_t)0x0UL) /**< SECDIAG_BORF_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_BORF_NOEVENT                (MXC_V_SMON_SECDIAG_BORF_NOEVENT << MXC_F_SMON_SECDIAG_BORF_POS) /**< SECDIAG_BORF_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_BORF_OCCURRED               ((uint32_t)0x1UL) /**< SECDIAG_BORF_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_BORF_OCCURRED               (MXC_V_SMON_SECDIAG_BORF_OCCURRED << MXC_F_SMON_SECDIAG_BORF_POS) /**< SECDIAG_BORF_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECDIAG_SHIELDF_POS                 2 /**< SECDIAG_SHIELDF Position */
+ #define MXC_F_SMON_SECDIAG_SHIELDF                     ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_SHIELDF_POS)) /**< SECDIAG_SHIELDF Mask */
+ #define MXC_V_SMON_SECDIAG_SHIELDF_NOEVENT             ((uint32_t)0x0UL) /**< SECDIAG_SHIELDF_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_SHIELDF_NOEVENT             (MXC_V_SMON_SECDIAG_SHIELDF_NOEVENT << MXC_F_SMON_SECDIAG_SHIELDF_POS) /**< SECDIAG_SHIELDF_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_SHIELDF_OCCURRED            ((uint32_t)0x1UL) /**< SECDIAG_SHIELDF_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_SHIELDF_OCCURRED            (MXC_V_SMON_SECDIAG_SHIELDF_OCCURRED << MXC_F_SMON_SECDIAG_SHIELDF_POS) /**< SECDIAG_SHIELDF_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECDIAG_LOTEMP_POS                  3 /**< SECDIAG_LOTEMP Position */
+ #define MXC_F_SMON_SECDIAG_LOTEMP                      ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_LOTEMP_POS)) /**< SECDIAG_LOTEMP Mask */
+ #define MXC_V_SMON_SECDIAG_LOTEMP_NOEVENT              ((uint32_t)0x0UL) /**< SECDIAG_LOTEMP_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_LOTEMP_NOEVENT              (MXC_V_SMON_SECDIAG_LOTEMP_NOEVENT << MXC_F_SMON_SECDIAG_LOTEMP_POS) /**< SECDIAG_LOTEMP_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_LOTEMP_OCCURRED             ((uint32_t)0x1UL) /**< SECDIAG_LOTEMP_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_LOTEMP_OCCURRED             (MXC_V_SMON_SECDIAG_LOTEMP_OCCURRED << MXC_F_SMON_SECDIAG_LOTEMP_POS) /**< SECDIAG_LOTEMP_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECDIAG_HITEMP_POS                  4 /**< SECDIAG_HITEMP Position */
+ #define MXC_F_SMON_SECDIAG_HITEMP                      ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_HITEMP_POS)) /**< SECDIAG_HITEMP Mask */
+ #define MXC_V_SMON_SECDIAG_HITEMP_NOEVENT              ((uint32_t)0x0UL) /**< SECDIAG_HITEMP_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_HITEMP_NOEVENT              (MXC_V_SMON_SECDIAG_HITEMP_NOEVENT << MXC_F_SMON_SECDIAG_HITEMP_POS) /**< SECDIAG_HITEMP_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_HITEMP_OCCURRED             ((uint32_t)0x1UL) /**< SECDIAG_HITEMP_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_HITEMP_OCCURRED             (MXC_V_SMON_SECDIAG_HITEMP_OCCURRED << MXC_F_SMON_SECDIAG_HITEMP_POS) /**< SECDIAG_HITEMP_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECDIAG_BATLO_POS                   5 /**< SECDIAG_BATLO Position */
+ #define MXC_F_SMON_SECDIAG_BATLO                       ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATLO_POS)) /**< SECDIAG_BATLO Mask */
+ #define MXC_V_SMON_SECDIAG_BATLO_NOEVENT               ((uint32_t)0x0UL) /**< SECDIAG_BATLO_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_BATLO_NOEVENT               (MXC_V_SMON_SECDIAG_BATLO_NOEVENT << MXC_F_SMON_SECDIAG_BATLO_POS) /**< SECDIAG_BATLO_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_BATLO_OCCURRED              ((uint32_t)0x1UL) /**< SECDIAG_BATLO_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_BATLO_OCCURRED              (MXC_V_SMON_SECDIAG_BATLO_OCCURRED << MXC_F_SMON_SECDIAG_BATLO_POS) /**< SECDIAG_BATLO_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECDIAG_BATHI_POS                   6 /**< SECDIAG_BATHI Position */
+ #define MXC_F_SMON_SECDIAG_BATHI                       ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATHI_POS)) /**< SECDIAG_BATHI Mask */
+ #define MXC_V_SMON_SECDIAG_BATHI_NOEVENT               ((uint32_t)0x0UL) /**< SECDIAG_BATHI_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_BATHI_NOEVENT               (MXC_V_SMON_SECDIAG_BATHI_NOEVENT << MXC_F_SMON_SECDIAG_BATHI_POS) /**< SECDIAG_BATHI_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_BATHI_OCCURRED              ((uint32_t)0x1UL) /**< SECDIAG_BATHI_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_BATHI_OCCURRED              (MXC_V_SMON_SECDIAG_BATHI_OCCURRED << MXC_F_SMON_SECDIAG_BATHI_POS) /**< SECDIAG_BATHI_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECDIAG_DYNF_POS                    7 /**< SECDIAG_DYNF Position */
+ #define MXC_F_SMON_SECDIAG_DYNF                        ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_DYNF_POS)) /**< SECDIAG_DYNF Mask */
+ #define MXC_V_SMON_SECDIAG_DYNF_NOEVENT                ((uint32_t)0x0UL) /**< SECDIAG_DYNF_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_DYNF_NOEVENT                (MXC_V_SMON_SECDIAG_DYNF_NOEVENT << MXC_F_SMON_SECDIAG_DYNF_POS) /**< SECDIAG_DYNF_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_DYNF_OCCURRED               ((uint32_t)0x1UL) /**< SECDIAG_DYNF_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_DYNF_OCCURRED               (MXC_V_SMON_SECDIAG_DYNF_OCCURRED << MXC_F_SMON_SECDIAG_DYNF_POS) /**< SECDIAG_DYNF_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECDIAG_AESKT_POS                   8 /**< SECDIAG_AESKT Position */
+ #define MXC_F_SMON_SECDIAG_AESKT                       ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESKT_POS)) /**< SECDIAG_AESKT Mask */
+ #define MXC_V_SMON_SECDIAG_AESKT_INCOMPLETE            ((uint32_t)0x0UL) /**< SECDIAG_AESKT_INCOMPLETE Value */
+ #define MXC_S_SMON_SECDIAG_AESKT_INCOMPLETE            (MXC_V_SMON_SECDIAG_AESKT_INCOMPLETE << MXC_F_SMON_SECDIAG_AESKT_POS) /**< SECDIAG_AESKT_INCOMPLETE Setting */
+ #define MXC_V_SMON_SECDIAG_AESKT_COMPLETE              ((uint32_t)0x1UL) /**< SECDIAG_AESKT_COMPLETE Value */
+ #define MXC_S_SMON_SECDIAG_AESKT_COMPLETE              (MXC_V_SMON_SECDIAG_AESKT_COMPLETE << MXC_F_SMON_SECDIAG_AESKT_POS) /**< SECDIAG_AESKT_COMPLETE Setting */
+
+ #define MXC_F_SMON_SECDIAG_EXTSTAT0_POS                16 /**< SECDIAG_EXTSTAT0 Position */
+ #define MXC_F_SMON_SECDIAG_EXTSTAT0                    ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT0_POS)) /**< SECDIAG_EXTSTAT0 Mask */
+ #define MXC_V_SMON_SECDIAG_EXTSTAT0_NOEVENT            ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT0_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_EXTSTAT0_NOEVENT            (MXC_V_SMON_SECDIAG_EXTSTAT0_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT0_POS) /**< SECDIAG_EXTSTAT0_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_EXTSTAT0_OCCURRED           ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT0_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_EXTSTAT0_OCCURRED           (MXC_V_SMON_SECDIAG_EXTSTAT0_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT0_POS) /**< SECDIAG_EXTSTAT0_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECDIAG_EXTSTAT1_POS                17 /**< SECDIAG_EXTSTAT1 Position */
+ #define MXC_F_SMON_SECDIAG_EXTSTAT1                    ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT1_POS)) /**< SECDIAG_EXTSTAT1 Mask */
+ #define MXC_V_SMON_SECDIAG_EXTSTAT1_NOEVENT            ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT1_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_EXTSTAT1_NOEVENT            (MXC_V_SMON_SECDIAG_EXTSTAT1_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT1_POS) /**< SECDIAG_EXTSTAT1_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_EXTSTAT1_OCCURRED           ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT1_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_EXTSTAT1_OCCURRED           (MXC_V_SMON_SECDIAG_EXTSTAT1_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT1_POS) /**< SECDIAG_EXTSTAT1_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECDIAG_EXTSTAT2_POS                18 /**< SECDIAG_EXTSTAT2 Position */
+ #define MXC_F_SMON_SECDIAG_EXTSTAT2                    ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT2_POS)) /**< SECDIAG_EXTSTAT2 Mask */
+ #define MXC_V_SMON_SECDIAG_EXTSTAT2_NOEVENT            ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT2_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_EXTSTAT2_NOEVENT            (MXC_V_SMON_SECDIAG_EXTSTAT2_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT2_POS) /**< SECDIAG_EXTSTAT2_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_EXTSTAT2_OCCURRED           ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT2_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_EXTSTAT2_OCCURRED           (MXC_V_SMON_SECDIAG_EXTSTAT2_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT2_POS) /**< SECDIAG_EXTSTAT2_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECDIAG_EXTSTAT3_POS                19 /**< SECDIAG_EXTSTAT3 Position */
+ #define MXC_F_SMON_SECDIAG_EXTSTAT3                    ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT3_POS)) /**< SECDIAG_EXTSTAT3 Mask */
+ #define MXC_V_SMON_SECDIAG_EXTSTAT3_NOEVENT            ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT3_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_EXTSTAT3_NOEVENT            (MXC_V_SMON_SECDIAG_EXTSTAT3_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT3_POS) /**< SECDIAG_EXTSTAT3_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_EXTSTAT3_OCCURRED           ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT3_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_EXTSTAT3_OCCURRED           (MXC_V_SMON_SECDIAG_EXTSTAT3_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT3_POS) /**< SECDIAG_EXTSTAT3_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECDIAG_EXTSTAT4_POS                20 /**< SECDIAG_EXTSTAT4 Position */
+ #define MXC_F_SMON_SECDIAG_EXTSTAT4                    ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT4_POS)) /**< SECDIAG_EXTSTAT4 Mask */
+ #define MXC_V_SMON_SECDIAG_EXTSTAT4_NOEVENT            ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT4_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_EXTSTAT4_NOEVENT            (MXC_V_SMON_SECDIAG_EXTSTAT4_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT4_POS) /**< SECDIAG_EXTSTAT4_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_EXTSTAT4_OCCURRED           ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT4_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_EXTSTAT4_OCCURRED           (MXC_V_SMON_SECDIAG_EXTSTAT4_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT4_POS) /**< SECDIAG_EXTSTAT4_OCCURRED Setting */
+
+ #define MXC_F_SMON_SECDIAG_EXTSTAT5_POS                21 /**< SECDIAG_EXTSTAT5 Position */
+ #define MXC_F_SMON_SECDIAG_EXTSTAT5                    ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT5_POS)) /**< SECDIAG_EXTSTAT5 Mask */
+ #define MXC_V_SMON_SECDIAG_EXTSTAT5_NOEVENT            ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT5_NOEVENT Value */
+ #define MXC_S_SMON_SECDIAG_EXTSTAT5_NOEVENT            (MXC_V_SMON_SECDIAG_EXTSTAT5_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT5_POS) /**< SECDIAG_EXTSTAT5_NOEVENT Setting */
+ #define MXC_V_SMON_SECDIAG_EXTSTAT5_OCCURRED           ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT5_OCCURRED Value */
+ #define MXC_S_SMON_SECDIAG_EXTSTAT5_OCCURRED           (MXC_V_SMON_SECDIAG_EXTSTAT5_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT5_POS) /**< SECDIAG_EXTSTAT5_OCCURRED Setting */
+
+/**@} end of group SMON_SECDIAG_Register */
+
+/**
+ * @ingroup  smon_registers
+ * @defgroup SMON_DLRTC SMON_DLRTC
+ * @brief    DRS Log RTC Value. This register contains the 32 bit value in the RTC second
+ *           register when the last DRS event occurred.
+ * @{
+ */
+ #define MXC_F_SMON_DLRTC_DLRTC_POS                     0 /**< DLRTC_DLRTC Position */
+ #define MXC_F_SMON_DLRTC_DLRTC                         ((uint32_t)(0xFFFFFFFFUL << MXC_F_SMON_DLRTC_DLRTC_POS)) /**< DLRTC_DLRTC Mask */
+
+/**@} end of group SMON_DLRTC_Register */
+
+/**
+ * @ingroup  smon_registers
+ * @defgroup SMON_SECST SMON_SECST
+ * @brief    Security Monitor Status Register.
+ * @{
+ */
+ #define MXC_F_SMON_SECST_EXTSRS_POS                    0 /**< SECST_EXTSRS Position */
+ #define MXC_F_SMON_SECST_EXTSRS                        ((uint32_t)(0x1UL << MXC_F_SMON_SECST_EXTSRS_POS)) /**< SECST_EXTSRS Mask */
+ #define MXC_V_SMON_SECST_EXTSRS_ALLOWED                ((uint32_t)0x0UL) /**< SECST_EXTSRS_ALLOWED Value */
+ #define MXC_S_SMON_SECST_EXTSRS_ALLOWED                (MXC_V_SMON_SECST_EXTSRS_ALLOWED << MXC_F_SMON_SECST_EXTSRS_POS) /**< SECST_EXTSRS_ALLOWED Setting */
+ #define MXC_V_SMON_SECST_EXTSRS_NOTALLOWED             ((uint32_t)0x1UL) /**< SECST_EXTSRS_NOTALLOWED Value */
+ #define MXC_S_SMON_SECST_EXTSRS_NOTALLOWED             (MXC_V_SMON_SECST_EXTSRS_NOTALLOWED << MXC_F_SMON_SECST_EXTSRS_POS) /**< SECST_EXTSRS_NOTALLOWED Setting */
+
+ #define MXC_F_SMON_SECST_INTSRS_POS                    1 /**< SECST_INTSRS Position */
+ #define MXC_F_SMON_SECST_INTSRS                        ((uint32_t)(0x1UL << MXC_F_SMON_SECST_INTSRS_POS)) /**< SECST_INTSRS Mask */
+ #define MXC_V_SMON_SECST_INTSRS_ALLOWED                ((uint32_t)0x0UL) /**< SECST_INTSRS_ALLOWED Value */
+ #define MXC_S_SMON_SECST_INTSRS_ALLOWED                (MXC_V_SMON_SECST_INTSRS_ALLOWED << MXC_F_SMON_SECST_INTSRS_POS) /**< SECST_INTSRS_ALLOWED Setting */
+ #define MXC_V_SMON_SECST_INTSRS_NOTALLOWED             ((uint32_t)0x1UL) /**< SECST_INTSRS_NOTALLOWED Value */
+ #define MXC_S_SMON_SECST_INTSRS_NOTALLOWED             (MXC_V_SMON_SECST_INTSRS_NOTALLOWED << MXC_F_SMON_SECST_INTSRS_POS) /**< SECST_INTSRS_NOTALLOWED Setting */
+
+ #define MXC_F_SMON_SECST_SECALRS_POS                   2 /**< SECST_SECALRS Position */
+ #define MXC_F_SMON_SECST_SECALRS                       ((uint32_t)(0x1UL << MXC_F_SMON_SECST_SECALRS_POS)) /**< SECST_SECALRS Mask */
+ #define MXC_V_SMON_SECST_SECALRS_ALLOWED               ((uint32_t)0x0UL) /**< SECST_SECALRS_ALLOWED Value */
+ #define MXC_S_SMON_SECST_SECALRS_ALLOWED               (MXC_V_SMON_SECST_SECALRS_ALLOWED << MXC_F_SMON_SECST_SECALRS_POS) /**< SECST_SECALRS_ALLOWED Setting */
+ #define MXC_V_SMON_SECST_SECALRS_NOTALLOWED            ((uint32_t)0x1UL) /**< SECST_SECALRS_NOTALLOWED Value */
+ #define MXC_S_SMON_SECST_SECALRS_NOTALLOWED            (MXC_V_SMON_SECST_SECALRS_NOTALLOWED << MXC_F_SMON_SECST_SECALRS_POS) /**< SECST_SECALRS_NOTALLOWED Setting */
+
+/**@} end of group SMON_SECST_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SMON_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/spi17y_regs.h

@@ -0,0 +1,664 @@
+/**
+ * @file    spi17y_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _SPI17Y_REGS_H_
+#define _SPI17Y_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     spi17y
+ * @defgroup    spi17y_registers SPI17Y_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module.
+ * @details SPI peripheral.
+ */
+
+/**
+ * @ingroup spi17y_registers
+ * Structure type to access the SPI17Y Registers.
+ */
+typedef struct {
+  union{
+    __IO uint32_t data32;               /**< <tt>\b 0x00:</tt> SPI17Y DATA32 Register */
+    __IO uint16_t data16[2];            /**< <tt>\b 0x00:</tt> SPI17Y DATA16 Register */
+    __IO uint8_t  data8[4];             /**< <tt>\b 0x00:</tt> SPI17Y DATA8 Register */
+  };
+    __IO uint32_t ctrl0;                /**< <tt>\b 0x04:</tt> SPI17Y CTRL0 Register */
+    __IO uint32_t ctrl1;                /**< <tt>\b 0x08:</tt> SPI17Y CTRL1 Register */
+    __IO uint32_t ctrl2;                /**< <tt>\b 0x0C:</tt> SPI17Y CTRL2 Register */
+    __IO uint32_t ss_time;              /**< <tt>\b 0x10:</tt> SPI17Y SS_TIME Register */
+    __IO uint32_t clk_cfg;              /**< <tt>\b 0x14:</tt> SPI17Y CLK_CFG Register */
+    __R  uint32_t rsv_0x18;
+    __IO uint32_t dma;                  /**< <tt>\b 0x1C:</tt> SPI17Y DMA Register */
+    __IO uint32_t int_fl;               /**< <tt>\b 0x20:</tt> SPI17Y INT_FL Register */
+    __IO uint32_t int_en;               /**< <tt>\b 0x24:</tt> SPI17Y INT_EN Register */
+    __IO uint32_t wake_fl;              /**< <tt>\b 0x28:</tt> SPI17Y WAKE_FL Register */
+    __IO uint32_t wake_en;              /**< <tt>\b 0x2C:</tt> SPI17Y WAKE_EN Register */
+    __I  uint32_t stat;                 /**< <tt>\b 0x30:</tt> SPI17Y STAT Register */
+} mxc_spi17y_regs_t;
+
+/* Register offsets for module SPI17Y */
+/**
+ * @ingroup    spi17y_registers
+ * @defgroup   SPI17Y_Register_Offsets Register Offsets
+ * @brief      SPI17Y Peripheral Register Offsets from the SPI17Y Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_SPI17Y_DATA32                ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_SPI17Y_DATA16                ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_SPI17Y_DATA8                 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_SPI17Y_CTRL0                 ((uint32_t)0x00000004UL) /**< Offset from SPI17Y Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_SPI17Y_CTRL1                 ((uint32_t)0x00000008UL) /**< Offset from SPI17Y Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_SPI17Y_CTRL2                 ((uint32_t)0x0000000CUL) /**< Offset from SPI17Y Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_SPI17Y_SS_TIME               ((uint32_t)0x00000010UL) /**< Offset from SPI17Y Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_SPI17Y_CLK_CFG               ((uint32_t)0x00000014UL) /**< Offset from SPI17Y Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_SPI17Y_DMA                   ((uint32_t)0x0000001CUL) /**< Offset from SPI17Y Base Address: <tt> 0x001C</tt> */ 
+ #define MXC_R_SPI17Y_INT_FL                ((uint32_t)0x00000020UL) /**< Offset from SPI17Y Base Address: <tt> 0x0020</tt> */ 
+ #define MXC_R_SPI17Y_INT_EN                ((uint32_t)0x00000024UL) /**< Offset from SPI17Y Base Address: <tt> 0x0024</tt> */ 
+ #define MXC_R_SPI17Y_WAKE_FL               ((uint32_t)0x00000028UL) /**< Offset from SPI17Y Base Address: <tt> 0x0028</tt> */ 
+ #define MXC_R_SPI17Y_WAKE_EN               ((uint32_t)0x0000002CUL) /**< Offset from SPI17Y Base Address: <tt> 0x002C</tt> */ 
+ #define MXC_R_SPI17Y_STAT                  ((uint32_t)0x00000030UL) /**< Offset from SPI17Y Base Address: <tt> 0x0030</tt> */ 
+/**@} end of group spi17y_registers */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_DATA32 SPI17Y_DATA32
+ * @brief    Register for reading and writing the FIFO.
+ * @{
+ */
+ #define MXC_F_SPI17Y_DATA32_DATA_POS                   0 /**< DATA32_DATA Position */
+ #define MXC_F_SPI17Y_DATA32_DATA                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI17Y_DATA32_DATA_POS)) /**< DATA32_DATA Mask */
+
+/**@} end of group SPI17Y_DATA32_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_DATA16 SPI17Y_DATA16
+ * @brief    Register for reading and writing the FIFO.
+ * @{
+ */
+ #define MXC_F_SPI17Y_DATA16_DATA_POS                   0 /**< DATA16_DATA Position */
+ #define MXC_F_SPI17Y_DATA16_DATA                       ((uint16_t)(0xFFFFUL << MXC_F_SPI17Y_DATA16_DATA_POS)) /**< DATA16_DATA Mask */
+
+/**@} end of group SPI17Y_DATA16_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_DATA8 SPI17Y_DATA8
+ * @brief    Register for reading and writing the FIFO.
+ * @{
+ */
+ #define MXC_F_SPI17Y_DATA8_DATA_POS                    0 /**< DATA8_DATA Position */
+ #define MXC_F_SPI17Y_DATA8_DATA                        ((uint8_t)(0xFFUL << MXC_F_SPI17Y_DATA8_DATA_POS)) /**< DATA8_DATA Mask */
+
+/**@} end of group SPI17Y_DATA8_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_CTRL0 SPI17Y_CTRL0
+ * @brief    Register for controlling SPI peripheral.
+ * @{
+ */
+ #define MXC_F_SPI17Y_CTRL0_EN_POS                      0 /**< CTRL0_EN Position */
+ #define MXC_F_SPI17Y_CTRL0_EN                          ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_EN_POS)) /**< CTRL0_EN Mask */
+ #define MXC_V_SPI17Y_CTRL0_EN_DIS                      ((uint32_t)0x0UL) /**< CTRL0_EN_DIS Value */
+ #define MXC_S_SPI17Y_CTRL0_EN_DIS                      (MXC_V_SPI17Y_CTRL0_EN_DIS << MXC_F_SPI17Y_CTRL0_EN_POS) /**< CTRL0_EN_DIS Setting */
+ #define MXC_V_SPI17Y_CTRL0_EN_EN                       ((uint32_t)0x1UL) /**< CTRL0_EN_EN Value */
+ #define MXC_S_SPI17Y_CTRL0_EN_EN                       (MXC_V_SPI17Y_CTRL0_EN_EN << MXC_F_SPI17Y_CTRL0_EN_POS) /**< CTRL0_EN_EN Setting */
+
+ #define MXC_F_SPI17Y_CTRL0_MASTER_POS                  1 /**< CTRL0_MASTER Position */
+ #define MXC_F_SPI17Y_CTRL0_MASTER                      ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_MASTER_POS)) /**< CTRL0_MASTER Mask */
+ #define MXC_V_SPI17Y_CTRL0_MASTER_DIS                  ((uint32_t)0x0UL) /**< CTRL0_MASTER_DIS Value */
+ #define MXC_S_SPI17Y_CTRL0_MASTER_DIS                  (MXC_V_SPI17Y_CTRL0_MASTER_DIS << MXC_F_SPI17Y_CTRL0_MASTER_POS) /**< CTRL0_MASTER_DIS Setting */
+ #define MXC_V_SPI17Y_CTRL0_MASTER_EN                   ((uint32_t)0x1UL) /**< CTRL0_MASTER_EN Value */
+ #define MXC_S_SPI17Y_CTRL0_MASTER_EN                   (MXC_V_SPI17Y_CTRL0_MASTER_EN << MXC_F_SPI17Y_CTRL0_MASTER_POS) /**< CTRL0_MASTER_EN Setting */
+
+ #define MXC_F_SPI17Y_CTRL0_SS_IO_POS                   4 /**< CTRL0_SS_IO Position */
+ #define MXC_F_SPI17Y_CTRL0_SS_IO                       ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */
+ #define MXC_V_SPI17Y_CTRL0_SS_IO_OUTPUT                ((uint32_t)0x0UL) /**< CTRL0_SS_IO_OUTPUT Value */
+ #define MXC_S_SPI17Y_CTRL0_SS_IO_OUTPUT                (MXC_V_SPI17Y_CTRL0_SS_IO_OUTPUT << MXC_F_SPI17Y_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_OUTPUT Setting */
+ #define MXC_V_SPI17Y_CTRL0_SS_IO_INPUT                 ((uint32_t)0x1UL) /**< CTRL0_SS_IO_INPUT Value */
+ #define MXC_S_SPI17Y_CTRL0_SS_IO_INPUT                 (MXC_V_SPI17Y_CTRL0_SS_IO_INPUT << MXC_F_SPI17Y_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_INPUT Setting */
+
+ #define MXC_F_SPI17Y_CTRL0_START_POS                   5 /**< CTRL0_START Position */
+ #define MXC_F_SPI17Y_CTRL0_START                       ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_START_POS)) /**< CTRL0_START Mask */
+ #define MXC_V_SPI17Y_CTRL0_START_START                 ((uint32_t)0x1UL) /**< CTRL0_START_START Value */
+ #define MXC_S_SPI17Y_CTRL0_START_START                 (MXC_V_SPI17Y_CTRL0_START_START << MXC_F_SPI17Y_CTRL0_START_POS) /**< CTRL0_START_START Setting */
+
+ #define MXC_F_SPI17Y_CTRL0_SS_CTRL_POS                 8 /**< CTRL0_SS_CTRL Position */
+ #define MXC_F_SPI17Y_CTRL0_SS_CTRL                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */
+ #define MXC_V_SPI17Y_CTRL0_SS_CTRL_DEASSERT            ((uint32_t)0x0UL) /**< CTRL0_SS_CTRL_DEASSERT Value */
+ #define MXC_S_SPI17Y_CTRL0_SS_CTRL_DEASSERT            (MXC_V_SPI17Y_CTRL0_SS_CTRL_DEASSERT << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_DEASSERT Setting */
+ #define MXC_V_SPI17Y_CTRL0_SS_CTRL_ASSERT              ((uint32_t)0x1UL) /**< CTRL0_SS_CTRL_ASSERT Value */
+ #define MXC_S_SPI17Y_CTRL0_SS_CTRL_ASSERT              (MXC_V_SPI17Y_CTRL0_SS_CTRL_ASSERT << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_ASSERT Setting */
+
+ #define MXC_F_SPI17Y_CTRL0_SS_POS                      16 /**< CTRL0_SS Position */
+ #define MXC_F_SPI17Y_CTRL0_SS                          ((uint32_t)(0xFUL << MXC_F_SPI17Y_CTRL0_SS_POS)) /**< CTRL0_SS Mask */
+ #define MXC_V_SPI17Y_CTRL0_SS_SS0                      ((uint32_t)0x1UL) /**< CTRL0_SS_SS0 Value */
+ #define MXC_S_SPI17Y_CTRL0_SS_SS0                      (MXC_V_SPI17Y_CTRL0_SS_SS0 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS0 Setting */
+ #define MXC_V_SPI17Y_CTRL0_SS_SS1                      ((uint32_t)0x2UL) /**< CTRL0_SS_SS1 Value */
+ #define MXC_S_SPI17Y_CTRL0_SS_SS1                      (MXC_V_SPI17Y_CTRL0_SS_SS1 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS1 Setting */
+ #define MXC_V_SPI17Y_CTRL0_SS_SS2                      ((uint32_t)0x4UL) /**< CTRL0_SS_SS2 Value */
+ #define MXC_S_SPI17Y_CTRL0_SS_SS2                      (MXC_V_SPI17Y_CTRL0_SS_SS2 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS2 Setting */
+ #define MXC_V_SPI17Y_CTRL0_SS_SS3                      ((uint32_t)0x8UL) /**< CTRL0_SS_SS3 Value */
+ #define MXC_S_SPI17Y_CTRL0_SS_SS3                      (MXC_V_SPI17Y_CTRL0_SS_SS3 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS3 Setting */
+
+/**@} end of group SPI17Y_CTRL0_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_CTRL1 SPI17Y_CTRL1
+ * @brief    Register for controlling SPI peripheral.
+ * @{
+ */
+ #define MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS             0 /**< CTRL1_TX_NUM_CHAR Position */
+ #define MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR                 ((uint32_t)(0xFFFFUL << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */
+
+ #define MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS             16 /**< CTRL1_RX_NUM_CHAR Position */
+ #define MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR                 ((uint32_t)(0xFFFFUL << MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */
+
+/**@} end of group SPI17Y_CTRL1_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_CTRL2 SPI17Y_CTRL2
+ * @brief    Register for controlling SPI peripheral.
+ * @{
+ */
+ #define MXC_F_SPI17Y_CTRL2_CPHA_POS                    0 /**< CTRL2_CPHA Position */
+ #define MXC_F_SPI17Y_CTRL2_CPHA                        ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_CPHA_POS)) /**< CTRL2_CPHA Mask */
+ #define MXC_V_SPI17Y_CTRL2_CPHA_RISING_EDGE            ((uint32_t)0x0UL) /**< CTRL2_CPHA_RISING_EDGE Value */
+ #define MXC_S_SPI17Y_CTRL2_CPHA_RISING_EDGE            (MXC_V_SPI17Y_CTRL2_CPHA_RISING_EDGE << MXC_F_SPI17Y_CTRL2_CPHA_POS) /**< CTRL2_CPHA_RISING_EDGE Setting */
+ #define MXC_V_SPI17Y_CTRL2_CPHA_FALLING_EDGE           ((uint32_t)0x1UL) /**< CTRL2_CPHA_FALLING_EDGE Value */
+ #define MXC_S_SPI17Y_CTRL2_CPHA_FALLING_EDGE           (MXC_V_SPI17Y_CTRL2_CPHA_FALLING_EDGE << MXC_F_SPI17Y_CTRL2_CPHA_POS) /**< CTRL2_CPHA_FALLING_EDGE Setting */
+
+ #define MXC_F_SPI17Y_CTRL2_CPOL_POS                    1 /**< CTRL2_CPOL Position */
+ #define MXC_F_SPI17Y_CTRL2_CPOL                        ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_CPOL_POS)) /**< CTRL2_CPOL Mask */
+ #define MXC_V_SPI17Y_CTRL2_CPOL_NORMAL                 ((uint32_t)0x0UL) /**< CTRL2_CPOL_NORMAL Value */
+ #define MXC_S_SPI17Y_CTRL2_CPOL_NORMAL                 (MXC_V_SPI17Y_CTRL2_CPOL_NORMAL << MXC_F_SPI17Y_CTRL2_CPOL_POS) /**< CTRL2_CPOL_NORMAL Setting */
+ #define MXC_V_SPI17Y_CTRL2_CPOL_INVERTED               ((uint32_t)0x1UL) /**< CTRL2_CPOL_INVERTED Value */
+ #define MXC_S_SPI17Y_CTRL2_CPOL_INVERTED               (MXC_V_SPI17Y_CTRL2_CPOL_INVERTED << MXC_F_SPI17Y_CTRL2_CPOL_POS) /**< CTRL2_CPOL_INVERTED Setting */
+
+ #define MXC_F_SPI17Y_CTRL2_SCLK_INV_POS                4 /**< CTRL2_SCLK_INV Position */
+ #define MXC_F_SPI17Y_CTRL2_SCLK_INV                    ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_SCLK_INV_POS)) /**< CTRL2_SCLK_INV Mask */
+
+ #define MXC_F_SPI17Y_CTRL2_NUMBITS_POS                 8 /**< CTRL2_NUMBITS Position */
+ #define MXC_F_SPI17Y_CTRL2_NUMBITS                     ((uint32_t)(0xFUL << MXC_F_SPI17Y_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */
+ #define MXC_V_SPI17Y_CTRL2_NUMBITS_0                   ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */
+ #define MXC_S_SPI17Y_CTRL2_NUMBITS_0                   (MXC_V_SPI17Y_CTRL2_NUMBITS_0 << MXC_F_SPI17Y_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */
+
+ #define MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS              12 /**< CTRL2_DATA_WIDTH Position */
+ #define MXC_F_SPI17Y_CTRL2_DATA_WIDTH                  ((uint32_t)(0x3UL << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */
+ #define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_MONO             ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */
+ #define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_MONO             (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */
+ #define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_DUAL             ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */
+ #define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_DUAL             (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */
+ #define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_QUAD             ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */
+ #define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_QUAD             (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */
+
+ #define MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS              15 /**< CTRL2_THREE_WIRE Position */
+ #define MXC_F_SPI17Y_CTRL2_THREE_WIRE                  ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */
+ #define MXC_V_SPI17Y_CTRL2_THREE_WIRE_DIS              ((uint32_t)0x0UL) /**< CTRL2_THREE_WIRE_DIS Value */
+ #define MXC_S_SPI17Y_CTRL2_THREE_WIRE_DIS              (MXC_V_SPI17Y_CTRL2_THREE_WIRE_DIS << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_DIS Setting */
+ #define MXC_V_SPI17Y_CTRL2_THREE_WIRE_EN               ((uint32_t)0x1UL) /**< CTRL2_THREE_WIRE_EN Value */
+ #define MXC_S_SPI17Y_CTRL2_THREE_WIRE_EN               (MXC_V_SPI17Y_CTRL2_THREE_WIRE_EN << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_EN Setting */
+
+ #define MXC_F_SPI17Y_CTRL2_SS_POL_POS                  16 /**< CTRL2_SS_POL Position */
+ #define MXC_F_SPI17Y_CTRL2_SS_POL                      ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */
+ #define MXC_V_SPI17Y_CTRL2_SS_POL_SS0_HIGH             ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */
+ #define MXC_S_SPI17Y_CTRL2_SS_POL_SS0_HIGH             (MXC_V_SPI17Y_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */
+ #define MXC_V_SPI17Y_CTRL2_SS_POL_SS1_HIGH             ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */
+ #define MXC_S_SPI17Y_CTRL2_SS_POL_SS1_HIGH             (MXC_V_SPI17Y_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */
+ #define MXC_V_SPI17Y_CTRL2_SS_POL_SS2_HIGH             ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */
+ #define MXC_S_SPI17Y_CTRL2_SS_POL_SS2_HIGH             (MXC_V_SPI17Y_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */
+ #define MXC_V_SPI17Y_CTRL2_SS_POL_SS3_HIGH             ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */
+ #define MXC_S_SPI17Y_CTRL2_SS_POL_SS3_HIGH             (MXC_V_SPI17Y_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */
+
+ #define MXC_F_SPI17Y_CTRL2_SRPOL_POS                   24 /**< CTRL2_SRPOL Position */
+ #define MXC_F_SPI17Y_CTRL2_SRPOL                       ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CTRL2_SRPOL_POS)) /**< CTRL2_SRPOL Mask */
+ #define MXC_V_SPI17Y_CTRL2_SRPOL_SR0_HIGH              ((uint32_t)0x1UL) /**< CTRL2_SRPOL_SR0_HIGH Value */
+ #define MXC_S_SPI17Y_CTRL2_SRPOL_SR0_HIGH              (MXC_V_SPI17Y_CTRL2_SRPOL_SR0_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR0_HIGH Setting */
+ #define MXC_V_SPI17Y_CTRL2_SRPOL_SR1_HIGH              ((uint32_t)0x2UL) /**< CTRL2_SRPOL_SR1_HIGH Value */
+ #define MXC_S_SPI17Y_CTRL2_SRPOL_SR1_HIGH              (MXC_V_SPI17Y_CTRL2_SRPOL_SR1_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR1_HIGH Setting */
+ #define MXC_V_SPI17Y_CTRL2_SRPOL_SR2_HIGH              ((uint32_t)0x4UL) /**< CTRL2_SRPOL_SR2_HIGH Value */
+ #define MXC_S_SPI17Y_CTRL2_SRPOL_SR2_HIGH              (MXC_V_SPI17Y_CTRL2_SRPOL_SR2_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR2_HIGH Setting */
+ #define MXC_V_SPI17Y_CTRL2_SRPOL_SR3_HIGH              ((uint32_t)0x8UL) /**< CTRL2_SRPOL_SR3_HIGH Value */
+ #define MXC_S_SPI17Y_CTRL2_SRPOL_SR3_HIGH              (MXC_V_SPI17Y_CTRL2_SRPOL_SR3_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR3_HIGH Setting */
+ #define MXC_V_SPI17Y_CTRL2_SRPOL_SR4_HIGH              ((uint32_t)0x10UL) /**< CTRL2_SRPOL_SR4_HIGH Value */
+ #define MXC_S_SPI17Y_CTRL2_SRPOL_SR4_HIGH              (MXC_V_SPI17Y_CTRL2_SRPOL_SR4_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR4_HIGH Setting */
+ #define MXC_V_SPI17Y_CTRL2_SRPOL_SR5_HIGH              ((uint32_t)0x20UL) /**< CTRL2_SRPOL_SR5_HIGH Value */
+ #define MXC_S_SPI17Y_CTRL2_SRPOL_SR5_HIGH              (MXC_V_SPI17Y_CTRL2_SRPOL_SR5_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR5_HIGH Setting */
+ #define MXC_V_SPI17Y_CTRL2_SRPOL_SR6_HIGH              ((uint32_t)0x40UL) /**< CTRL2_SRPOL_SR6_HIGH Value */
+ #define MXC_S_SPI17Y_CTRL2_SRPOL_SR6_HIGH              (MXC_V_SPI17Y_CTRL2_SRPOL_SR6_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR6_HIGH Setting */
+ #define MXC_V_SPI17Y_CTRL2_SRPOL_SR7_HIGH              ((uint32_t)0x80UL) /**< CTRL2_SRPOL_SR7_HIGH Value */
+ #define MXC_S_SPI17Y_CTRL2_SRPOL_SR7_HIGH              (MXC_V_SPI17Y_CTRL2_SRPOL_SR7_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR7_HIGH Setting */
+
+/**@} end of group SPI17Y_CTRL2_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_SS_TIME SPI17Y_SS_TIME
+ * @brief    Register for controlling SPI peripheral/Slave Select Timing.
+ * @{
+ */
+ #define MXC_F_SPI17Y_SS_TIME_PRE_POS                   0 /**< SS_TIME_PRE Position */
+ #define MXC_F_SPI17Y_SS_TIME_PRE                       ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_PRE_POS)) /**< SS_TIME_PRE Mask */
+ #define MXC_V_SPI17Y_SS_TIME_PRE_256                   ((uint32_t)0x0UL) /**< SS_TIME_PRE_256 Value */
+ #define MXC_S_SPI17Y_SS_TIME_PRE_256                   (MXC_V_SPI17Y_SS_TIME_PRE_256 << MXC_F_SPI17Y_SS_TIME_PRE_POS) /**< SS_TIME_PRE_256 Setting */
+
+ #define MXC_F_SPI17Y_SS_TIME_POST_POS                  8 /**< SS_TIME_POST Position */
+ #define MXC_F_SPI17Y_SS_TIME_POST                      ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_POST_POS)) /**< SS_TIME_POST Mask */
+ #define MXC_V_SPI17Y_SS_TIME_POST_256                  ((uint32_t)0x0UL) /**< SS_TIME_POST_256 Value */
+ #define MXC_S_SPI17Y_SS_TIME_POST_256                  (MXC_V_SPI17Y_SS_TIME_POST_256 << MXC_F_SPI17Y_SS_TIME_POST_POS) /**< SS_TIME_POST_256 Setting */
+
+ #define MXC_F_SPI17Y_SS_TIME_INACT_POS                 16 /**< SS_TIME_INACT Position */
+ #define MXC_F_SPI17Y_SS_TIME_INACT                     ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_INACT_POS)) /**< SS_TIME_INACT Mask */
+ #define MXC_V_SPI17Y_SS_TIME_INACT_256                 ((uint32_t)0x0UL) /**< SS_TIME_INACT_256 Value */
+ #define MXC_S_SPI17Y_SS_TIME_INACT_256                 (MXC_V_SPI17Y_SS_TIME_INACT_256 << MXC_F_SPI17Y_SS_TIME_INACT_POS) /**< SS_TIME_INACT_256 Setting */
+
+/**@} end of group SPI17Y_SS_TIME_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_CLK_CFG SPI17Y_CLK_CFG
+ * @brief    Register for controlling SPI clock rate.
+ * @{
+ */
+ #define MXC_F_SPI17Y_CLK_CFG_LO_POS                    0 /**< CLK_CFG_LO Position */
+ #define MXC_F_SPI17Y_CLK_CFG_LO                        ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */
+ #define MXC_V_SPI17Y_CLK_CFG_LO_DIS                    ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */
+ #define MXC_S_SPI17Y_CLK_CFG_LO_DIS                    (MXC_V_SPI17Y_CLK_CFG_LO_DIS << MXC_F_SPI17Y_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */
+
+ #define MXC_F_SPI17Y_CLK_CFG_HI_POS                    8 /**< CLK_CFG_HI Position */
+ #define MXC_F_SPI17Y_CLK_CFG_HI                        ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */
+ #define MXC_V_SPI17Y_CLK_CFG_HI_DIS                    ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */
+ #define MXC_S_SPI17Y_CLK_CFG_HI_DIS                    (MXC_V_SPI17Y_CLK_CFG_HI_DIS << MXC_F_SPI17Y_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */
+
+ #define MXC_F_SPI17Y_CLK_CFG_SCALE_POS                 16 /**< CLK_CFG_SCALE Position */
+ #define MXC_F_SPI17Y_CLK_CFG_SCALE                     ((uint32_t)(0xFUL << MXC_F_SPI17Y_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */
+
+/**@} end of group SPI17Y_CLK_CFG_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_DMA SPI17Y_DMA
+ * @brief    Register for controlling DMA.
+ * @{
+ */
+ #define MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS             0 /**< DMA_TX_FIFO_LEVEL Position */
+ #define MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL                 ((uint32_t)(0x1FUL << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */
+
+ #define MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS                6 /**< DMA_TX_FIFO_EN Position */
+ #define MXC_F_SPI17Y_DMA_TX_FIFO_EN                    ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */
+ #define MXC_V_SPI17Y_DMA_TX_FIFO_EN_DIS                ((uint32_t)0x0UL) /**< DMA_TX_FIFO_EN_DIS Value */
+ #define MXC_S_SPI17Y_DMA_TX_FIFO_EN_DIS                (MXC_V_SPI17Y_DMA_TX_FIFO_EN_DIS << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_DIS Setting */
+ #define MXC_V_SPI17Y_DMA_TX_FIFO_EN_EN                 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_EN_EN Value */
+ #define MXC_S_SPI17Y_DMA_TX_FIFO_EN_EN                 (MXC_V_SPI17Y_DMA_TX_FIFO_EN_EN << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_EN Setting */
+
+ #define MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS             7 /**< DMA_TX_FIFO_CLEAR Position */
+ #define MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR                 ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */
+ #define MXC_V_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR           ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_CLEAR Value */
+ #define MXC_S_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR           (MXC_V_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR << MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS               8 /**< DMA_TX_FIFO_CNT Position */
+ #define MXC_F_SPI17Y_DMA_TX_FIFO_CNT                   ((uint32_t)(0x3FUL << MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
+
+ #define MXC_F_SPI17Y_DMA_TX_DMA_EN_POS                 15 /**< DMA_TX_DMA_EN Position */
+ #define MXC_F_SPI17Y_DMA_TX_DMA_EN                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
+ #define MXC_V_SPI17Y_DMA_TX_DMA_EN_DIS                 ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DIS Value */
+ #define MXC_S_SPI17Y_DMA_TX_DMA_EN_DIS                 (MXC_V_SPI17Y_DMA_TX_DMA_EN_DIS << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DIS Setting */
+ #define MXC_V_SPI17Y_DMA_TX_DMA_EN_EN                  ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_EN Value */
+ #define MXC_S_SPI17Y_DMA_TX_DMA_EN_EN                  (MXC_V_SPI17Y_DMA_TX_DMA_EN_EN << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_EN Setting */
+
+ #define MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS             16 /**< DMA_RX_FIFO_LEVEL Position */
+ #define MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL                 ((uint32_t)(0x1FUL << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */
+
+ #define MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS                22 /**< DMA_RX_FIFO_EN Position */
+ #define MXC_F_SPI17Y_DMA_RX_FIFO_EN                    ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */
+ #define MXC_V_SPI17Y_DMA_RX_FIFO_EN_DIS                ((uint32_t)0x0UL) /**< DMA_RX_FIFO_EN_DIS Value */
+ #define MXC_S_SPI17Y_DMA_RX_FIFO_EN_DIS                (MXC_V_SPI17Y_DMA_RX_FIFO_EN_DIS << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_DIS Setting */
+ #define MXC_V_SPI17Y_DMA_RX_FIFO_EN_EN                 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_EN_EN Value */
+ #define MXC_S_SPI17Y_DMA_RX_FIFO_EN_EN                 (MXC_V_SPI17Y_DMA_RX_FIFO_EN_EN << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_EN Setting */
+
+ #define MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS             23 /**< DMA_RX_FIFO_CLEAR Position */
+ #define MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR                 ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */
+ #define MXC_V_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR           ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_CLEAR Value */
+ #define MXC_S_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR           (MXC_V_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR << MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS               24 /**< DMA_RX_FIFO_CNT Position */
+ #define MXC_F_SPI17Y_DMA_RX_FIFO_CNT                   ((uint32_t)(0x3FUL << MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
+
+ #define MXC_F_SPI17Y_DMA_RX_DMA_EN_POS                 31 /**< DMA_RX_DMA_EN Position */
+ #define MXC_F_SPI17Y_DMA_RX_DMA_EN                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
+ #define MXC_V_SPI17Y_DMA_RX_DMA_EN_DIS                 ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DIS Value */
+ #define MXC_S_SPI17Y_DMA_RX_DMA_EN_DIS                 (MXC_V_SPI17Y_DMA_RX_DMA_EN_DIS << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DIS Setting */
+ #define MXC_V_SPI17Y_DMA_RX_DMA_EN_EN                  ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_EN Value */
+ #define MXC_S_SPI17Y_DMA_RX_DMA_EN_EN                  (MXC_V_SPI17Y_DMA_RX_DMA_EN_EN << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_EN Setting */
+
+/**@} end of group SPI17Y_DMA_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_INT_FL SPI17Y_INT_FL
+ * @brief    Register for reading and clearing interrupt flags. All bits are write 1 to
+ *           clear.
+ * @{
+ */
+ #define MXC_F_SPI17Y_INT_FL_TX_THRESH_POS              0 /**< INT_FL_TX_THRESH Position */
+ #define MXC_F_SPI17Y_INT_FL_TX_THRESH                  ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS)) /**< INT_FL_TX_THRESH Mask */
+ #define MXC_V_SPI17Y_INT_FL_TX_THRESH_CLEAR            ((uint32_t)0x1UL) /**< INT_FL_TX_THRESH_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_TX_THRESH_CLEAR            (MXC_V_SPI17Y_INT_FL_TX_THRESH_CLEAR << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS) /**< INT_FL_TX_THRESH_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS               1 /**< INT_FL_TX_EMPTY Position */
+ #define MXC_F_SPI17Y_INT_FL_TX_EMPTY                   ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */
+ #define MXC_V_SPI17Y_INT_FL_TX_EMPTY_CLEAR             ((uint32_t)0x1UL) /**< INT_FL_TX_EMPTY_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_TX_EMPTY_CLEAR             (MXC_V_SPI17Y_INT_FL_TX_EMPTY_CLEAR << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS) /**< INT_FL_TX_EMPTY_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_INT_FL_RX_THRESH_POS              2 /**< INT_FL_RX_THRESH Position */
+ #define MXC_F_SPI17Y_INT_FL_RX_THRESH                  ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS)) /**< INT_FL_RX_THRESH Mask */
+ #define MXC_V_SPI17Y_INT_FL_RX_THRESH_CLEAR            ((uint32_t)0x1UL) /**< INT_FL_RX_THRESH_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_RX_THRESH_CLEAR            (MXC_V_SPI17Y_INT_FL_RX_THRESH_CLEAR << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS) /**< INT_FL_RX_THRESH_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_INT_FL_RX_FULL_POS                3 /**< INT_FL_RX_FULL Position */
+ #define MXC_F_SPI17Y_INT_FL_RX_FULL                    ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */
+ #define MXC_V_SPI17Y_INT_FL_RX_FULL_CLEAR              ((uint32_t)0x1UL) /**< INT_FL_RX_FULL_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_RX_FULL_CLEAR              (MXC_V_SPI17Y_INT_FL_RX_FULL_CLEAR << MXC_F_SPI17Y_INT_FL_RX_FULL_POS) /**< INT_FL_RX_FULL_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_INT_FL_SSA_POS                    4 /**< INT_FL_SSA Position */
+ #define MXC_F_SPI17Y_INT_FL_SSA                        ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */
+ #define MXC_V_SPI17Y_INT_FL_SSA_CLEAR                  ((uint32_t)0x1UL) /**< INT_FL_SSA_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_SSA_CLEAR                  (MXC_V_SPI17Y_INT_FL_SSA_CLEAR << MXC_F_SPI17Y_INT_FL_SSA_POS) /**< INT_FL_SSA_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_INT_FL_SSD_POS                    5 /**< INT_FL_SSD Position */
+ #define MXC_F_SPI17Y_INT_FL_SSD                        ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */
+ #define MXC_V_SPI17Y_INT_FL_SSD_CLEAR                  ((uint32_t)0x1UL) /**< INT_FL_SSD_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_SSD_CLEAR                  (MXC_V_SPI17Y_INT_FL_SSD_CLEAR << MXC_F_SPI17Y_INT_FL_SSD_POS) /**< INT_FL_SSD_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_INT_FL_FAULT_POS                  8 /**< INT_FL_FAULT Position */
+ #define MXC_F_SPI17Y_INT_FL_FAULT                      ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_FAULT_POS)) /**< INT_FL_FAULT Mask */
+ #define MXC_V_SPI17Y_INT_FL_FAULT_CLEAR                ((uint32_t)0x1UL) /**< INT_FL_FAULT_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_FAULT_CLEAR                (MXC_V_SPI17Y_INT_FL_FAULT_CLEAR << MXC_F_SPI17Y_INT_FL_FAULT_POS) /**< INT_FL_FAULT_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_INT_FL_ABORT_POS                  9 /**< INT_FL_ABORT Position */
+ #define MXC_F_SPI17Y_INT_FL_ABORT                      ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */
+ #define MXC_V_SPI17Y_INT_FL_ABORT_CLEAR                ((uint32_t)0x1UL) /**< INT_FL_ABORT_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_ABORT_CLEAR                (MXC_V_SPI17Y_INT_FL_ABORT_CLEAR << MXC_F_SPI17Y_INT_FL_ABORT_POS) /**< INT_FL_ABORT_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_INT_FL_M_DONE_POS                 11 /**< INT_FL_M_DONE Position */
+ #define MXC_F_SPI17Y_INT_FL_M_DONE                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */
+ #define MXC_V_SPI17Y_INT_FL_M_DONE_CLEAR               ((uint32_t)0x1UL) /**< INT_FL_M_DONE_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_M_DONE_CLEAR               (MXC_V_SPI17Y_INT_FL_M_DONE_CLEAR << MXC_F_SPI17Y_INT_FL_M_DONE_POS) /**< INT_FL_M_DONE_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_INT_FL_TX_OVR_POS                 12 /**< INT_FL_TX_OVR Position */
+ #define MXC_F_SPI17Y_INT_FL_TX_OVR                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */
+ #define MXC_V_SPI17Y_INT_FL_TX_OVR_CLEAR               ((uint32_t)0x1UL) /**< INT_FL_TX_OVR_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_TX_OVR_CLEAR               (MXC_V_SPI17Y_INT_FL_TX_OVR_CLEAR << MXC_F_SPI17Y_INT_FL_TX_OVR_POS) /**< INT_FL_TX_OVR_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_INT_FL_TX_UND_POS                 13 /**< INT_FL_TX_UND Position */
+ #define MXC_F_SPI17Y_INT_FL_TX_UND                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */
+ #define MXC_V_SPI17Y_INT_FL_TX_UND_CLEAR               ((uint32_t)0x1UL) /**< INT_FL_TX_UND_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_TX_UND_CLEAR               (MXC_V_SPI17Y_INT_FL_TX_UND_CLEAR << MXC_F_SPI17Y_INT_FL_TX_UND_POS) /**< INT_FL_TX_UND_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_INT_FL_RX_OVR_POS                 14 /**< INT_FL_RX_OVR Position */
+ #define MXC_F_SPI17Y_INT_FL_RX_OVR                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */
+ #define MXC_V_SPI17Y_INT_FL_RX_OVR_CLEAR               ((uint32_t)0x1UL) /**< INT_FL_RX_OVR_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_RX_OVR_CLEAR               (MXC_V_SPI17Y_INT_FL_RX_OVR_CLEAR << MXC_F_SPI17Y_INT_FL_RX_OVR_POS) /**< INT_FL_RX_OVR_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_INT_FL_RX_UND_POS                 15 /**< INT_FL_RX_UND Position */
+ #define MXC_F_SPI17Y_INT_FL_RX_UND                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */
+ #define MXC_V_SPI17Y_INT_FL_RX_UND_CLEAR               ((uint32_t)0x1UL) /**< INT_FL_RX_UND_CLEAR Value */
+ #define MXC_S_SPI17Y_INT_FL_RX_UND_CLEAR               (MXC_V_SPI17Y_INT_FL_RX_UND_CLEAR << MXC_F_SPI17Y_INT_FL_RX_UND_POS) /**< INT_FL_RX_UND_CLEAR Setting */
+
+/**@} end of group SPI17Y_INT_FL_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_INT_EN SPI17Y_INT_EN
+ * @brief    Register for enabling interrupts.
+ * @{
+ */
+ #define MXC_F_SPI17Y_INT_EN_TX_THRESH_POS              0 /**< INT_EN_TX_THRESH Position */
+ #define MXC_F_SPI17Y_INT_EN_TX_THRESH                  ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS)) /**< INT_EN_TX_THRESH Mask */
+ #define MXC_V_SPI17Y_INT_EN_TX_THRESH_DIS              ((uint32_t)0x0UL) /**< INT_EN_TX_THRESH_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_TX_THRESH_DIS              (MXC_V_SPI17Y_INT_EN_TX_THRESH_DIS << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS) /**< INT_EN_TX_THRESH_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_TX_THRESH_EN               ((uint32_t)0x1UL) /**< INT_EN_TX_THRESH_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_TX_THRESH_EN               (MXC_V_SPI17Y_INT_EN_TX_THRESH_EN << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS) /**< INT_EN_TX_THRESH_EN Setting */
+
+ #define MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS               1 /**< INT_EN_TX_EMPTY Position */
+ #define MXC_F_SPI17Y_INT_EN_TX_EMPTY                   ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */
+ #define MXC_V_SPI17Y_INT_EN_TX_EMPTY_DIS               ((uint32_t)0x0UL) /**< INT_EN_TX_EMPTY_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_TX_EMPTY_DIS               (MXC_V_SPI17Y_INT_EN_TX_EMPTY_DIS << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_TX_EMPTY_EN                ((uint32_t)0x1UL) /**< INT_EN_TX_EMPTY_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_TX_EMPTY_EN                (MXC_V_SPI17Y_INT_EN_TX_EMPTY_EN << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_EN Setting */
+
+ #define MXC_F_SPI17Y_INT_EN_RX_THRESH_POS              2 /**< INT_EN_RX_THRESH Position */
+ #define MXC_F_SPI17Y_INT_EN_RX_THRESH                  ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS)) /**< INT_EN_RX_THRESH Mask */
+ #define MXC_V_SPI17Y_INT_EN_RX_THRESH_DIS              ((uint32_t)0x0UL) /**< INT_EN_RX_THRESH_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_RX_THRESH_DIS              (MXC_V_SPI17Y_INT_EN_RX_THRESH_DIS << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS) /**< INT_EN_RX_THRESH_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_RX_THRESH_EN               ((uint32_t)0x1UL) /**< INT_EN_RX_THRESH_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_RX_THRESH_EN               (MXC_V_SPI17Y_INT_EN_RX_THRESH_EN << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS) /**< INT_EN_RX_THRESH_EN Setting */
+
+ #define MXC_F_SPI17Y_INT_EN_RX_FULL_POS                3 /**< INT_EN_RX_FULL Position */
+ #define MXC_F_SPI17Y_INT_EN_RX_FULL                    ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */
+ #define MXC_V_SPI17Y_INT_EN_RX_FULL_DIS                ((uint32_t)0x0UL) /**< INT_EN_RX_FULL_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_RX_FULL_DIS                (MXC_V_SPI17Y_INT_EN_RX_FULL_DIS << MXC_F_SPI17Y_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_RX_FULL_EN                 ((uint32_t)0x1UL) /**< INT_EN_RX_FULL_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_RX_FULL_EN                 (MXC_V_SPI17Y_INT_EN_RX_FULL_EN << MXC_F_SPI17Y_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_EN Setting */
+
+ #define MXC_F_SPI17Y_INT_EN_SSA_POS                    4 /**< INT_EN_SSA Position */
+ #define MXC_F_SPI17Y_INT_EN_SSA                        ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */
+ #define MXC_V_SPI17Y_INT_EN_SSA_DIS                    ((uint32_t)0x0UL) /**< INT_EN_SSA_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_SSA_DIS                    (MXC_V_SPI17Y_INT_EN_SSA_DIS << MXC_F_SPI17Y_INT_EN_SSA_POS) /**< INT_EN_SSA_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_SSA_EN                     ((uint32_t)0x1UL) /**< INT_EN_SSA_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_SSA_EN                     (MXC_V_SPI17Y_INT_EN_SSA_EN << MXC_F_SPI17Y_INT_EN_SSA_POS) /**< INT_EN_SSA_EN Setting */
+
+ #define MXC_F_SPI17Y_INT_EN_SSD_POS                    5 /**< INT_EN_SSD Position */
+ #define MXC_F_SPI17Y_INT_EN_SSD                        ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */
+ #define MXC_V_SPI17Y_INT_EN_SSD_DIS                    ((uint32_t)0x0UL) /**< INT_EN_SSD_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_SSD_DIS                    (MXC_V_SPI17Y_INT_EN_SSD_DIS << MXC_F_SPI17Y_INT_EN_SSD_POS) /**< INT_EN_SSD_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_SSD_EN                     ((uint32_t)0x1UL) /**< INT_EN_SSD_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_SSD_EN                     (MXC_V_SPI17Y_INT_EN_SSD_EN << MXC_F_SPI17Y_INT_EN_SSD_POS) /**< INT_EN_SSD_EN Setting */
+
+ #define MXC_F_SPI17Y_INT_EN_FAULT_POS                  8 /**< INT_EN_FAULT Position */
+ #define MXC_F_SPI17Y_INT_EN_FAULT                      ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */
+ #define MXC_V_SPI17Y_INT_EN_FAULT_DIS                  ((uint32_t)0x0UL) /**< INT_EN_FAULT_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_FAULT_DIS                  (MXC_V_SPI17Y_INT_EN_FAULT_DIS << MXC_F_SPI17Y_INT_EN_FAULT_POS) /**< INT_EN_FAULT_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_FAULT_EN                   ((uint32_t)0x1UL) /**< INT_EN_FAULT_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_FAULT_EN                   (MXC_V_SPI17Y_INT_EN_FAULT_EN << MXC_F_SPI17Y_INT_EN_FAULT_POS) /**< INT_EN_FAULT_EN Setting */
+
+ #define MXC_F_SPI17Y_INT_EN_ABORT_POS                  9 /**< INT_EN_ABORT Position */
+ #define MXC_F_SPI17Y_INT_EN_ABORT                      ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */
+ #define MXC_V_SPI17Y_INT_EN_ABORT_DIS                  ((uint32_t)0x0UL) /**< INT_EN_ABORT_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_ABORT_DIS                  (MXC_V_SPI17Y_INT_EN_ABORT_DIS << MXC_F_SPI17Y_INT_EN_ABORT_POS) /**< INT_EN_ABORT_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_ABORT_EN                   ((uint32_t)0x1UL) /**< INT_EN_ABORT_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_ABORT_EN                   (MXC_V_SPI17Y_INT_EN_ABORT_EN << MXC_F_SPI17Y_INT_EN_ABORT_POS) /**< INT_EN_ABORT_EN Setting */
+
+ #define MXC_F_SPI17Y_INT_EN_M_DONE_POS                 11 /**< INT_EN_M_DONE Position */
+ #define MXC_F_SPI17Y_INT_EN_M_DONE                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */
+ #define MXC_V_SPI17Y_INT_EN_M_DONE_DIS                 ((uint32_t)0x0UL) /**< INT_EN_M_DONE_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_M_DONE_DIS                 (MXC_V_SPI17Y_INT_EN_M_DONE_DIS << MXC_F_SPI17Y_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_M_DONE_EN                  ((uint32_t)0x1UL) /**< INT_EN_M_DONE_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_M_DONE_EN                  (MXC_V_SPI17Y_INT_EN_M_DONE_EN << MXC_F_SPI17Y_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_EN Setting */
+
+ #define MXC_F_SPI17Y_INT_EN_TX_OVR_POS                 12 /**< INT_EN_TX_OVR Position */
+ #define MXC_F_SPI17Y_INT_EN_TX_OVR                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */
+ #define MXC_V_SPI17Y_INT_EN_TX_OVR_DIS                 ((uint32_t)0x0UL) /**< INT_EN_TX_OVR_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_TX_OVR_DIS                 (MXC_V_SPI17Y_INT_EN_TX_OVR_DIS << MXC_F_SPI17Y_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_TX_OVR_EN                  ((uint32_t)0x1UL) /**< INT_EN_TX_OVR_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_TX_OVR_EN                  (MXC_V_SPI17Y_INT_EN_TX_OVR_EN << MXC_F_SPI17Y_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_EN Setting */
+
+ #define MXC_F_SPI17Y_INT_EN_TX_UND_POS                 13 /**< INT_EN_TX_UND Position */
+ #define MXC_F_SPI17Y_INT_EN_TX_UND                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */
+ #define MXC_V_SPI17Y_INT_EN_TX_UND_DIS                 ((uint32_t)0x0UL) /**< INT_EN_TX_UND_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_TX_UND_DIS                 (MXC_V_SPI17Y_INT_EN_TX_UND_DIS << MXC_F_SPI17Y_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_TX_UND_EN                  ((uint32_t)0x1UL) /**< INT_EN_TX_UND_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_TX_UND_EN                  (MXC_V_SPI17Y_INT_EN_TX_UND_EN << MXC_F_SPI17Y_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_EN Setting */
+
+ #define MXC_F_SPI17Y_INT_EN_RX_OVR_POS                 14 /**< INT_EN_RX_OVR Position */
+ #define MXC_F_SPI17Y_INT_EN_RX_OVR                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */
+ #define MXC_V_SPI17Y_INT_EN_RX_OVR_DIS                 ((uint32_t)0x0UL) /**< INT_EN_RX_OVR_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_RX_OVR_DIS                 (MXC_V_SPI17Y_INT_EN_RX_OVR_DIS << MXC_F_SPI17Y_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_RX_OVR_EN                  ((uint32_t)0x1UL) /**< INT_EN_RX_OVR_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_RX_OVR_EN                  (MXC_V_SPI17Y_INT_EN_RX_OVR_EN << MXC_F_SPI17Y_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_EN Setting */
+
+ #define MXC_F_SPI17Y_INT_EN_RX_UND_POS                 15 /**< INT_EN_RX_UND Position */
+ #define MXC_F_SPI17Y_INT_EN_RX_UND                     ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */
+ #define MXC_V_SPI17Y_INT_EN_RX_UND_DIS                 ((uint32_t)0x0UL) /**< INT_EN_RX_UND_DIS Value */
+ #define MXC_S_SPI17Y_INT_EN_RX_UND_DIS                 (MXC_V_SPI17Y_INT_EN_RX_UND_DIS << MXC_F_SPI17Y_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_DIS Setting */
+ #define MXC_V_SPI17Y_INT_EN_RX_UND_EN                  ((uint32_t)0x1UL) /**< INT_EN_RX_UND_EN Value */
+ #define MXC_S_SPI17Y_INT_EN_RX_UND_EN                  (MXC_V_SPI17Y_INT_EN_RX_UND_EN << MXC_F_SPI17Y_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_EN Setting */
+
+/**@} end of group SPI17Y_INT_EN_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_WAKE_FL SPI17Y_WAKE_FL
+ * @brief    Register for wake up flags. All bits in this register are write 1 to clear.
+ * @{
+ */
+ #define MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS             0 /**< WAKE_FL_TX_THRESH Position */
+ #define MXC_F_SPI17Y_WAKE_FL_TX_THRESH                 ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS)) /**< WAKE_FL_TX_THRESH Mask */
+ #define MXC_V_SPI17Y_WAKE_FL_TX_THRESH_CLEAR           ((uint32_t)0x1UL) /**< WAKE_FL_TX_THRESH_CLEAR Value */
+ #define MXC_S_SPI17Y_WAKE_FL_TX_THRESH_CLEAR           (MXC_V_SPI17Y_WAKE_FL_TX_THRESH_CLEAR << MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS) /**< WAKE_FL_TX_THRESH_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS              1 /**< WAKE_FL_TX_EMPTY Position */
+ #define MXC_F_SPI17Y_WAKE_FL_TX_EMPTY                  ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */
+ #define MXC_V_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR            ((uint32_t)0x1UL) /**< WAKE_FL_TX_EMPTY_CLEAR Value */
+ #define MXC_S_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR            (MXC_V_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR << MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS) /**< WAKE_FL_TX_EMPTY_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS             2 /**< WAKE_FL_RX_THRESH Position */
+ #define MXC_F_SPI17Y_WAKE_FL_RX_THRESH                 ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS)) /**< WAKE_FL_RX_THRESH Mask */
+ #define MXC_V_SPI17Y_WAKE_FL_RX_THRESH_CLEAR           ((uint32_t)0x1UL) /**< WAKE_FL_RX_THRESH_CLEAR Value */
+ #define MXC_S_SPI17Y_WAKE_FL_RX_THRESH_CLEAR           (MXC_V_SPI17Y_WAKE_FL_RX_THRESH_CLEAR << MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS) /**< WAKE_FL_RX_THRESH_CLEAR Setting */
+
+ #define MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS               3 /**< WAKE_FL_RX_FULL Position */
+ #define MXC_F_SPI17Y_WAKE_FL_RX_FULL                   ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */
+ #define MXC_V_SPI17Y_WAKE_FL_RX_FULL_CLEAR             ((uint32_t)0x1UL) /**< WAKE_FL_RX_FULL_CLEAR Value */
+ #define MXC_S_SPI17Y_WAKE_FL_RX_FULL_CLEAR             (MXC_V_SPI17Y_WAKE_FL_RX_FULL_CLEAR << MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS) /**< WAKE_FL_RX_FULL_CLEAR Setting */
+
+/**@} end of group SPI17Y_WAKE_FL_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_WAKE_EN SPI17Y_WAKE_EN
+ * @brief    Register for wake up enable.
+ * @{
+ */
+ #define MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS             0 /**< WAKE_EN_TX_THRESH Position */
+ #define MXC_F_SPI17Y_WAKE_EN_TX_THRESH                 ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS)) /**< WAKE_EN_TX_THRESH Mask */
+ #define MXC_V_SPI17Y_WAKE_EN_TX_THRESH_DIS             ((uint32_t)0x0UL) /**< WAKE_EN_TX_THRESH_DIS Value */
+ #define MXC_S_SPI17Y_WAKE_EN_TX_THRESH_DIS             (MXC_V_SPI17Y_WAKE_EN_TX_THRESH_DIS << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS) /**< WAKE_EN_TX_THRESH_DIS Setting */
+ #define MXC_V_SPI17Y_WAKE_EN_TX_THRESH_EN              ((uint32_t)0x1UL) /**< WAKE_EN_TX_THRESH_EN Value */
+ #define MXC_S_SPI17Y_WAKE_EN_TX_THRESH_EN              (MXC_V_SPI17Y_WAKE_EN_TX_THRESH_EN << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS) /**< WAKE_EN_TX_THRESH_EN Setting */
+
+ #define MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS              1 /**< WAKE_EN_TX_EMPTY Position */
+ #define MXC_F_SPI17Y_WAKE_EN_TX_EMPTY                  ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */
+ #define MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_DIS              ((uint32_t)0x0UL) /**< WAKE_EN_TX_EMPTY_DIS Value */
+ #define MXC_S_SPI17Y_WAKE_EN_TX_EMPTY_DIS              (MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_DIS << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_DIS Setting */
+ #define MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_EN               ((uint32_t)0x1UL) /**< WAKE_EN_TX_EMPTY_EN Value */
+ #define MXC_S_SPI17Y_WAKE_EN_TX_EMPTY_EN               (MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_EN << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_EN Setting */
+
+ #define MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS             2 /**< WAKE_EN_RX_THRESH Position */
+ #define MXC_F_SPI17Y_WAKE_EN_RX_THRESH                 ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS)) /**< WAKE_EN_RX_THRESH Mask */
+ #define MXC_V_SPI17Y_WAKE_EN_RX_THRESH_DIS             ((uint32_t)0x0UL) /**< WAKE_EN_RX_THRESH_DIS Value */
+ #define MXC_S_SPI17Y_WAKE_EN_RX_THRESH_DIS             (MXC_V_SPI17Y_WAKE_EN_RX_THRESH_DIS << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS) /**< WAKE_EN_RX_THRESH_DIS Setting */
+ #define MXC_V_SPI17Y_WAKE_EN_RX_THRESH_EN              ((uint32_t)0x1UL) /**< WAKE_EN_RX_THRESH_EN Value */
+ #define MXC_S_SPI17Y_WAKE_EN_RX_THRESH_EN              (MXC_V_SPI17Y_WAKE_EN_RX_THRESH_EN << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS) /**< WAKE_EN_RX_THRESH_EN Setting */
+
+ #define MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS               3 /**< WAKE_EN_RX_FULL Position */
+ #define MXC_F_SPI17Y_WAKE_EN_RX_FULL                   ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */
+ #define MXC_V_SPI17Y_WAKE_EN_RX_FULL_DIS               ((uint32_t)0x0UL) /**< WAKE_EN_RX_FULL_DIS Value */
+ #define MXC_S_SPI17Y_WAKE_EN_RX_FULL_DIS               (MXC_V_SPI17Y_WAKE_EN_RX_FULL_DIS << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_DIS Setting */
+ #define MXC_V_SPI17Y_WAKE_EN_RX_FULL_EN                ((uint32_t)0x1UL) /**< WAKE_EN_RX_FULL_EN Value */
+ #define MXC_S_SPI17Y_WAKE_EN_RX_FULL_EN                (MXC_V_SPI17Y_WAKE_EN_RX_FULL_EN << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_EN Setting */
+
+/**@} end of group SPI17Y_WAKE_EN_Register */
+
+/**
+ * @ingroup  spi17y_registers
+ * @defgroup SPI17Y_STAT SPI17Y_STAT
+ * @brief    SPI Status register.
+ * @{
+ */
+ #define MXC_F_SPI17Y_STAT_BUSY_POS                     0 /**< STAT_BUSY Position */
+ #define MXC_F_SPI17Y_STAT_BUSY                         ((uint32_t)(0x1UL << MXC_F_SPI17Y_STAT_BUSY_POS)) /**< STAT_BUSY Mask */
+ #define MXC_V_SPI17Y_STAT_BUSY_NOT                     ((uint32_t)0x0UL) /**< STAT_BUSY_NOT Value */
+ #define MXC_S_SPI17Y_STAT_BUSY_NOT                     (MXC_V_SPI17Y_STAT_BUSY_NOT << MXC_F_SPI17Y_STAT_BUSY_POS) /**< STAT_BUSY_NOT Setting */
+ #define MXC_V_SPI17Y_STAT_BUSY_ACTIVE                  ((uint32_t)0x1UL) /**< STAT_BUSY_ACTIVE Value */
+ #define MXC_S_SPI17Y_STAT_BUSY_ACTIVE                  (MXC_V_SPI17Y_STAT_BUSY_ACTIVE << MXC_F_SPI17Y_STAT_BUSY_POS) /**< STAT_BUSY_ACTIVE Setting */
+
+/**@} end of group SPI17Y_STAT_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SPI17Y_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h

@@ -0,0 +1,496 @@
+/**
+ * @file    spimss_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _SPIMSS_REGS_H_
+#define _SPIMSS_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     spimss
+ * @defgroup    spimss_registers SPIMSS_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
+ * @details Serial Peripheral Interface.
+ */
+
+/**
+ * @ingroup spimss_registers
+ * Structure type to access the SPIMSS Registers.
+ */
+typedef struct {
+  union{
+    __IO uint16_t data16;               /**< <tt>\b 0x00:</tt> SPIMSS DATA16 Register */
+    __IO uint8_t  data8[2];             /**< <tt>\b 0x00:</tt> SPIMSS DATA8 Register */
+  };
+    __R  uint16_t rsv_0x2;
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x04:</tt> SPIMSS CTRL Register */
+    __IO uint32_t status;               /**< <tt>\b 0x08:</tt> SPIMSS STATUS Register */
+    __IO uint32_t mod;                  /**< <tt>\b 0x0C:</tt> SPIMSS MOD Register */
+    __R  uint32_t rsv_0x10;
+    __IO uint32_t brg;                  /**< <tt>\b 0x14:</tt> SPIMSS BRG Register */
+    __IO uint32_t dma;                  /**< <tt>\b 0x18:</tt> SPIMSS DMA Register */
+    __IO uint32_t i2s_ctrl;             /**< <tt>\b 0x1C:</tt> SPIMSS I2S_CTRL Register */
+} mxc_spimss_regs_t;
+
+/* Register offsets for module SPIMSS */
+/**
+ * @ingroup    spimss_registers
+ * @defgroup   SPIMSS_Register_Offsets Register Offsets
+ * @brief      SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_SPIMSS_DATA16                ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_SPIMSS_DATA8                 ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_SPIMSS_CTRL                  ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_SPIMSS_STATUS                ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_SPIMSS_MOD                   ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_SPIMSS_BRG                   ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_SPIMSS_DMA                   ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_SPIMSS_I2S_CTRL              ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: <tt> 0x001C</tt> */ 
+/**@} end of group spimss_registers */
+
+/**
+ * @ingroup  spimss_registers
+ * @defgroup SPIMSS_DATA16 SPIMSS_DATA16
+ * @brief    SPI 16-bit Data Access
+ * @{
+ */
+ #define MXC_F_SPIMSS_DATA16_DATA_POS                   0 /**< DATA16_DATA Position */
+ #define MXC_F_SPIMSS_DATA16_DATA                       ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_DATA16_DATA_POS)) /**< DATA16_DATA Mask */
+
+/**@} end of group SPIMSS_DATA16_Register */
+
+/**
+ * @ingroup  spimss_registers
+ * @defgroup SPIMSS_DATA8 SPIMSS_DATA8
+ * @brief    SPI Data 8-bit access
+ * @{
+ */
+ #define MXC_F_SPIMSS_DATA8_DATA_POS                    0 /**< DATA8_DATA Position */
+ #define MXC_F_SPIMSS_DATA8_DATA                        ((uint8_t)(0xFFUL << MXC_F_SPIMSS_DATA8_DATA_POS)) /**< DATA8_DATA Mask */
+
+/**@} end of group SPIMSS_DATA8_Register */
+
+/**
+ * @ingroup  spimss_registers
+ * @defgroup SPIMSS_CTRL SPIMSS_CTRL
+ * @brief    SPI Control Register.
+ * @{
+ */
+ #define MXC_F_SPIMSS_CTRL_SPIEN_POS                    0 /**< CTRL_SPIEN Position */
+ #define MXC_F_SPIMSS_CTRL_SPIEN                        ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_SPIEN_POS)) /**< CTRL_SPIEN Mask */
+ #define MXC_V_SPIMSS_CTRL_SPIEN_DISABLE                ((uint32_t)0x0UL) /**< CTRL_SPIEN_DISABLE Value */
+ #define MXC_S_SPIMSS_CTRL_SPIEN_DISABLE                (MXC_V_SPIMSS_CTRL_SPIEN_DISABLE << MXC_F_SPIMSS_CTRL_SPIEN_POS) /**< CTRL_SPIEN_DISABLE Setting */
+ #define MXC_V_SPIMSS_CTRL_SPIEN_ENABLE                 ((uint32_t)0x1UL) /**< CTRL_SPIEN_ENABLE Value */
+ #define MXC_S_SPIMSS_CTRL_SPIEN_ENABLE                 (MXC_V_SPIMSS_CTRL_SPIEN_ENABLE << MXC_F_SPIMSS_CTRL_SPIEN_POS) /**< CTRL_SPIEN_ENABLE Setting */
+
+ #define MXC_F_SPIMSS_CTRL_MMEN_POS                     1 /**< CTRL_MMEN Position */
+ #define MXC_F_SPIMSS_CTRL_MMEN                         ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */
+ #define MXC_V_SPIMSS_CTRL_MMEN_SLAVE                   ((uint32_t)0x0UL) /**< CTRL_MMEN_SLAVE Value */
+ #define MXC_S_SPIMSS_CTRL_MMEN_SLAVE                   (MXC_V_SPIMSS_CTRL_MMEN_SLAVE << MXC_F_SPIMSS_CTRL_MMEN_POS) /**< CTRL_MMEN_SLAVE Setting */
+ #define MXC_V_SPIMSS_CTRL_MMEN_MASTER                  ((uint32_t)0x1UL) /**< CTRL_MMEN_MASTER Value */
+ #define MXC_S_SPIMSS_CTRL_MMEN_MASTER                  (MXC_V_SPIMSS_CTRL_MMEN_MASTER << MXC_F_SPIMSS_CTRL_MMEN_POS) /**< CTRL_MMEN_MASTER Setting */
+
+ #define MXC_F_SPIMSS_CTRL_WOR_POS                      2 /**< CTRL_WOR Position */
+ #define MXC_F_SPIMSS_CTRL_WOR                          ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_WOR_POS)) /**< CTRL_WOR Mask */
+ #define MXC_V_SPIMSS_CTRL_WOR_DISABLE                  ((uint32_t)0x0UL) /**< CTRL_WOR_DISABLE Value */
+ #define MXC_S_SPIMSS_CTRL_WOR_DISABLE                  (MXC_V_SPIMSS_CTRL_WOR_DISABLE << MXC_F_SPIMSS_CTRL_WOR_POS) /**< CTRL_WOR_DISABLE Setting */
+ #define MXC_V_SPIMSS_CTRL_WOR_ENABLE                   ((uint32_t)0x1UL) /**< CTRL_WOR_ENABLE Value */
+ #define MXC_S_SPIMSS_CTRL_WOR_ENABLE                   (MXC_V_SPIMSS_CTRL_WOR_ENABLE << MXC_F_SPIMSS_CTRL_WOR_POS) /**< CTRL_WOR_ENABLE Setting */
+
+ #define MXC_F_SPIMSS_CTRL_CLKPOL_POS                   3 /**< CTRL_CLKPOL Position */
+ #define MXC_F_SPIMSS_CTRL_CLKPOL                       ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */
+ #define MXC_V_SPIMSS_CTRL_CLKPOL_IDLELO                ((uint32_t)0x0UL) /**< CTRL_CLKPOL_IDLELO Value */
+ #define MXC_S_SPIMSS_CTRL_CLKPOL_IDLELO                (MXC_V_SPIMSS_CTRL_CLKPOL_IDLELO << MXC_F_SPIMSS_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLELO Setting */
+ #define MXC_V_SPIMSS_CTRL_CLKPOL_IDLEHI                ((uint32_t)0x1UL) /**< CTRL_CLKPOL_IDLEHI Value */
+ #define MXC_S_SPIMSS_CTRL_CLKPOL_IDLEHI                (MXC_V_SPIMSS_CTRL_CLKPOL_IDLEHI << MXC_F_SPIMSS_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLEHI Setting */
+
+ #define MXC_F_SPIMSS_CTRL_PHASE_POS                    4 /**< CTRL_PHASE Position */
+ #define MXC_F_SPIMSS_CTRL_PHASE                        ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */
+ #define MXC_V_SPIMSS_CTRL_PHASE_ACTIVEEDGE             ((uint32_t)0x0UL) /**< CTRL_PHASE_ACTIVEEDGE Value */
+ #define MXC_S_SPIMSS_CTRL_PHASE_ACTIVEEDGE             (MXC_V_SPIMSS_CTRL_PHASE_ACTIVEEDGE << MXC_F_SPIMSS_CTRL_PHASE_POS) /**< CTRL_PHASE_ACTIVEEDGE Setting */
+ #define MXC_V_SPIMSS_CTRL_PHASE_INACTIVEEDGE           ((uint32_t)0x1UL) /**< CTRL_PHASE_INACTIVEEDGE Value */
+ #define MXC_S_SPIMSS_CTRL_PHASE_INACTIVEEDGE           (MXC_V_SPIMSS_CTRL_PHASE_INACTIVEEDGE << MXC_F_SPIMSS_CTRL_PHASE_POS) /**< CTRL_PHASE_INACTIVEEDGE Setting */
+
+ #define MXC_F_SPIMSS_CTRL_BIRQ_POS                     5 /**< CTRL_BIRQ Position */
+ #define MXC_F_SPIMSS_CTRL_BIRQ                         ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */
+ #define MXC_V_SPIMSS_CTRL_BIRQ_DISABLE                 ((uint32_t)0x0UL) /**< CTRL_BIRQ_DISABLE Value */
+ #define MXC_S_SPIMSS_CTRL_BIRQ_DISABLE                 (MXC_V_SPIMSS_CTRL_BIRQ_DISABLE << MXC_F_SPIMSS_CTRL_BIRQ_POS) /**< CTRL_BIRQ_DISABLE Setting */
+ #define MXC_V_SPIMSS_CTRL_BIRQ_ENABLE                  ((uint32_t)0x1UL) /**< CTRL_BIRQ_ENABLE Value */
+ #define MXC_S_SPIMSS_CTRL_BIRQ_ENABLE                  (MXC_V_SPIMSS_CTRL_BIRQ_ENABLE << MXC_F_SPIMSS_CTRL_BIRQ_POS) /**< CTRL_BIRQ_ENABLE Setting */
+
+ #define MXC_F_SPIMSS_CTRL_STR_POS                      6 /**< CTRL_STR Position */
+ #define MXC_F_SPIMSS_CTRL_STR                          ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS)) /**< CTRL_STR Mask */
+ #define MXC_V_SPIMSS_CTRL_STR_COMPLETE                 ((uint32_t)0x0UL) /**< CTRL_STR_COMPLETE Value */
+ #define MXC_S_SPIMSS_CTRL_STR_COMPLETE                 (MXC_V_SPIMSS_CTRL_STR_COMPLETE << MXC_F_SPIMSS_CTRL_STR_POS) /**< CTRL_STR_COMPLETE Setting */
+ #define MXC_V_SPIMSS_CTRL_STR_START                    ((uint32_t)0x1UL) /**< CTRL_STR_START Value */
+ #define MXC_S_SPIMSS_CTRL_STR_START                    (MXC_V_SPIMSS_CTRL_STR_START << MXC_F_SPIMSS_CTRL_STR_POS) /**< CTRL_STR_START Setting */
+
+ #define MXC_F_SPIMSS_CTRL_IRQE_POS                     7 /**< CTRL_IRQE Position */
+ #define MXC_F_SPIMSS_CTRL_IRQE                         ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */
+ #define MXC_V_SPIMSS_CTRL_IRQE_DISABLE                 ((uint32_t)0x0UL) /**< CTRL_IRQE_DISABLE Value */
+ #define MXC_S_SPIMSS_CTRL_IRQE_DISABLE                 (MXC_V_SPIMSS_CTRL_IRQE_DISABLE << MXC_F_SPIMSS_CTRL_IRQE_POS) /**< CTRL_IRQE_DISABLE Setting */
+ #define MXC_V_SPIMSS_CTRL_IRQE_ENABLE                  ((uint32_t)0x1UL) /**< CTRL_IRQE_ENABLE Value */
+ #define MXC_S_SPIMSS_CTRL_IRQE_ENABLE                  (MXC_V_SPIMSS_CTRL_IRQE_ENABLE << MXC_F_SPIMSS_CTRL_IRQE_POS) /**< CTRL_IRQE_ENABLE Setting */
+
+/**@} end of group SPIMSS_CTRL_Register */
+
+/**
+ * @ingroup  spimss_registers
+ * @defgroup SPIMSS_STATUS SPIMSS_STATUS
+ * @brief    SPI Status Register.
+ * @{
+ */
+ #define MXC_F_SPIMSS_STATUS_SLAS_POS                   0 /**< STATUS_SLAS Position */
+ #define MXC_F_SPIMSS_STATUS_SLAS                       ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_SLAS_POS)) /**< STATUS_SLAS Mask */
+ #define MXC_V_SPIMSS_STATUS_SLAS_SELECTED              ((uint32_t)0x0UL) /**< STATUS_SLAS_SELECTED Value */
+ #define MXC_S_SPIMSS_STATUS_SLAS_SELECTED              (MXC_V_SPIMSS_STATUS_SLAS_SELECTED << MXC_F_SPIMSS_STATUS_SLAS_POS) /**< STATUS_SLAS_SELECTED Setting */
+ #define MXC_V_SPIMSS_STATUS_SLAS_NOTSELECTED           ((uint32_t)0x1UL) /**< STATUS_SLAS_NOTSELECTED Value */
+ #define MXC_S_SPIMSS_STATUS_SLAS_NOTSELECTED           (MXC_V_SPIMSS_STATUS_SLAS_NOTSELECTED << MXC_F_SPIMSS_STATUS_SLAS_POS) /**< STATUS_SLAS_NOTSELECTED Setting */
+
+ #define MXC_F_SPIMSS_STATUS_TXST_POS                   1 /**< STATUS_TXST Position */
+ #define MXC_F_SPIMSS_STATUS_TXST                       ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TXST_POS)) /**< STATUS_TXST Mask */
+ #define MXC_V_SPIMSS_STATUS_TXST_IDLE                  ((uint32_t)0x0UL) /**< STATUS_TXST_IDLE Value */
+ #define MXC_S_SPIMSS_STATUS_TXST_IDLE                  (MXC_V_SPIMSS_STATUS_TXST_IDLE << MXC_F_SPIMSS_STATUS_TXST_POS) /**< STATUS_TXST_IDLE Setting */
+ #define MXC_V_SPIMSS_STATUS_TXST_BUSY                  ((uint32_t)0x1UL) /**< STATUS_TXST_BUSY Value */
+ #define MXC_S_SPIMSS_STATUS_TXST_BUSY                  (MXC_V_SPIMSS_STATUS_TXST_BUSY << MXC_F_SPIMSS_STATUS_TXST_POS) /**< STATUS_TXST_BUSY Setting */
+
+ #define MXC_F_SPIMSS_STATUS_TUND_POS                   2 /**< STATUS_TUND Position */
+ #define MXC_F_SPIMSS_STATUS_TUND                       ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TUND_POS)) /**< STATUS_TUND Mask */
+ #define MXC_V_SPIMSS_STATUS_TUND_NOEVENT               ((uint32_t)0x0UL) /**< STATUS_TUND_NOEVENT Value */
+ #define MXC_S_SPIMSS_STATUS_TUND_NOEVENT               (MXC_V_SPIMSS_STATUS_TUND_NOEVENT << MXC_F_SPIMSS_STATUS_TUND_POS) /**< STATUS_TUND_NOEVENT Setting */
+ #define MXC_V_SPIMSS_STATUS_TUND_OCCURRED              ((uint32_t)0x1UL) /**< STATUS_TUND_OCCURRED Value */
+ #define MXC_S_SPIMSS_STATUS_TUND_OCCURRED              (MXC_V_SPIMSS_STATUS_TUND_OCCURRED << MXC_F_SPIMSS_STATUS_TUND_POS) /**< STATUS_TUND_OCCURRED Setting */
+
+ #define MXC_F_SPIMSS_STATUS_ROVR_POS                   3 /**< STATUS_ROVR Position */
+ #define MXC_F_SPIMSS_STATUS_ROVR                       ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_ROVR_POS)) /**< STATUS_ROVR Mask */
+ #define MXC_V_SPIMSS_STATUS_ROVR_NOEVENT               ((uint32_t)0x0UL) /**< STATUS_ROVR_NOEVENT Value */
+ #define MXC_S_SPIMSS_STATUS_ROVR_NOEVENT               (MXC_V_SPIMSS_STATUS_ROVR_NOEVENT << MXC_F_SPIMSS_STATUS_ROVR_POS) /**< STATUS_ROVR_NOEVENT Setting */
+ #define MXC_V_SPIMSS_STATUS_ROVR_OCCURRED              ((uint32_t)0x1UL) /**< STATUS_ROVR_OCCURRED Value */
+ #define MXC_S_SPIMSS_STATUS_ROVR_OCCURRED              (MXC_V_SPIMSS_STATUS_ROVR_OCCURRED << MXC_F_SPIMSS_STATUS_ROVR_POS) /**< STATUS_ROVR_OCCURRED Setting */
+
+ #define MXC_F_SPIMSS_STATUS_ABT_POS                    4 /**< STATUS_ABT Position */
+ #define MXC_F_SPIMSS_STATUS_ABT                        ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_ABT_POS)) /**< STATUS_ABT Mask */
+ #define MXC_V_SPIMSS_STATUS_ABT_NOEVENT                ((uint32_t)0x0UL) /**< STATUS_ABT_NOEVENT Value */
+ #define MXC_S_SPIMSS_STATUS_ABT_NOEVENT                (MXC_V_SPIMSS_STATUS_ABT_NOEVENT << MXC_F_SPIMSS_STATUS_ABT_POS) /**< STATUS_ABT_NOEVENT Setting */
+ #define MXC_V_SPIMSS_STATUS_ABT_OCCURRED               ((uint32_t)0x1UL) /**< STATUS_ABT_OCCURRED Value */
+ #define MXC_S_SPIMSS_STATUS_ABT_OCCURRED               (MXC_V_SPIMSS_STATUS_ABT_OCCURRED << MXC_F_SPIMSS_STATUS_ABT_POS) /**< STATUS_ABT_OCCURRED Setting */
+
+ #define MXC_F_SPIMSS_STATUS_COL_POS                    5 /**< STATUS_COL Position */
+ #define MXC_F_SPIMSS_STATUS_COL                        ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_COL_POS)) /**< STATUS_COL Mask */
+ #define MXC_V_SPIMSS_STATUS_COL_NOEVENT                ((uint32_t)0x0UL) /**< STATUS_COL_NOEVENT Value */
+ #define MXC_S_SPIMSS_STATUS_COL_NOEVENT                (MXC_V_SPIMSS_STATUS_COL_NOEVENT << MXC_F_SPIMSS_STATUS_COL_POS) /**< STATUS_COL_NOEVENT Setting */
+ #define MXC_V_SPIMSS_STATUS_COL_OCCURRED               ((uint32_t)0x1UL) /**< STATUS_COL_OCCURRED Value */
+ #define MXC_S_SPIMSS_STATUS_COL_OCCURRED               (MXC_V_SPIMSS_STATUS_COL_OCCURRED << MXC_F_SPIMSS_STATUS_COL_POS) /**< STATUS_COL_OCCURRED Setting */
+
+ #define MXC_F_SPIMSS_STATUS_TOVR_POS                   6 /**< STATUS_TOVR Position */
+ #define MXC_F_SPIMSS_STATUS_TOVR                       ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TOVR_POS)) /**< STATUS_TOVR Mask */
+ #define MXC_V_SPIMSS_STATUS_TOVR_NOEVENT               ((uint32_t)0x0UL) /**< STATUS_TOVR_NOEVENT Value */
+ #define MXC_S_SPIMSS_STATUS_TOVR_NOEVENT               (MXC_V_SPIMSS_STATUS_TOVR_NOEVENT << MXC_F_SPIMSS_STATUS_TOVR_POS) /**< STATUS_TOVR_NOEVENT Setting */
+ #define MXC_V_SPIMSS_STATUS_TOVR_OCCURRED              ((uint32_t)0x1UL) /**< STATUS_TOVR_OCCURRED Value */
+ #define MXC_S_SPIMSS_STATUS_TOVR_OCCURRED              (MXC_V_SPIMSS_STATUS_TOVR_OCCURRED << MXC_F_SPIMSS_STATUS_TOVR_POS) /**< STATUS_TOVR_OCCURRED Setting */
+
+ #define MXC_F_SPIMSS_STATUS_IRQ_POS                    7 /**< STATUS_IRQ Position */
+ #define MXC_F_SPIMSS_STATUS_IRQ                        ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_IRQ_POS)) /**< STATUS_IRQ Mask */
+ #define MXC_V_SPIMSS_STATUS_IRQ_INACTIVE               ((uint32_t)0x0UL) /**< STATUS_IRQ_INACTIVE Value */
+ #define MXC_S_SPIMSS_STATUS_IRQ_INACTIVE               (MXC_V_SPIMSS_STATUS_IRQ_INACTIVE << MXC_F_SPIMSS_STATUS_IRQ_POS) /**< STATUS_IRQ_INACTIVE Setting */
+ #define MXC_V_SPIMSS_STATUS_IRQ_PENDING                ((uint32_t)0x1UL) /**< STATUS_IRQ_PENDING Value */
+ #define MXC_S_SPIMSS_STATUS_IRQ_PENDING                (MXC_V_SPIMSS_STATUS_IRQ_PENDING << MXC_F_SPIMSS_STATUS_IRQ_POS) /**< STATUS_IRQ_PENDING Setting */
+
+/**@} end of group SPIMSS_STATUS_Register */
+
+/**
+ * @ingroup  spimss_registers
+ * @defgroup SPIMSS_MOD SPIMSS_MOD
+ * @brief    SPI Mode Register.
+ * @{
+ */
+ #define MXC_F_SPIMSS_MOD_SSV_POS                       0 /**< MOD_SSV Position */
+ #define MXC_F_SPIMSS_MOD_SSV                           ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSV_POS)) /**< MOD_SSV Mask */
+ #define MXC_V_SPIMSS_MOD_SSV_LO                        ((uint32_t)0x0UL) /**< MOD_SSV_LO Value */
+ #define MXC_S_SPIMSS_MOD_SSV_LO                        (MXC_V_SPIMSS_MOD_SSV_LO << MXC_F_SPIMSS_MOD_SSV_POS) /**< MOD_SSV_LO Setting */
+ #define MXC_V_SPIMSS_MOD_SSV_HI                        ((uint32_t)0x1UL) /**< MOD_SSV_HI Value */
+ #define MXC_S_SPIMSS_MOD_SSV_HI                        (MXC_V_SPIMSS_MOD_SSV_HI << MXC_F_SPIMSS_MOD_SSV_POS) /**< MOD_SSV_HI Setting */
+
+ #define MXC_F_SPIMSS_MOD_SSIO_POS                      1 /**< MOD_SSIO Position */
+ #define MXC_F_SPIMSS_MOD_SSIO                          ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSIO_POS)) /**< MOD_SSIO Mask */
+ #define MXC_V_SPIMSS_MOD_SSIO_INPUT                    ((uint32_t)0x0UL) /**< MOD_SSIO_INPUT Value */
+ #define MXC_S_SPIMSS_MOD_SSIO_INPUT                    (MXC_V_SPIMSS_MOD_SSIO_INPUT << MXC_F_SPIMSS_MOD_SSIO_POS) /**< MOD_SSIO_INPUT Setting */
+ #define MXC_V_SPIMSS_MOD_SSIO_OUTPUT                   ((uint32_t)0x1UL) /**< MOD_SSIO_OUTPUT Value */
+ #define MXC_S_SPIMSS_MOD_SSIO_OUTPUT                   (MXC_V_SPIMSS_MOD_SSIO_OUTPUT << MXC_F_SPIMSS_MOD_SSIO_POS) /**< MOD_SSIO_OUTPUT Setting */
+
+ #define MXC_F_SPIMSS_MOD_NUMBITS_POS                   2 /**< MOD_NUMBITS Position */
+ #define MXC_F_SPIMSS_MOD_NUMBITS                       ((uint32_t)(0xFUL << MXC_F_SPIMSS_MOD_NUMBITS_POS)) /**< MOD_NUMBITS Mask */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS16                ((uint32_t)0x0UL) /**< MOD_NUMBITS_BITS16 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS16                (MXC_V_SPIMSS_MOD_NUMBITS_BITS16 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS16 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS1                 ((uint32_t)0x1UL) /**< MOD_NUMBITS_BITS1 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS1                 (MXC_V_SPIMSS_MOD_NUMBITS_BITS1 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS1 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS2                 ((uint32_t)0x2UL) /**< MOD_NUMBITS_BITS2 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS2                 (MXC_V_SPIMSS_MOD_NUMBITS_BITS2 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS2 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS3                 ((uint32_t)0x3UL) /**< MOD_NUMBITS_BITS3 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS3                 (MXC_V_SPIMSS_MOD_NUMBITS_BITS3 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS3 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS4                 ((uint32_t)0x4UL) /**< MOD_NUMBITS_BITS4 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS4                 (MXC_V_SPIMSS_MOD_NUMBITS_BITS4 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS4 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS5                 ((uint32_t)0x5UL) /**< MOD_NUMBITS_BITS5 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS5                 (MXC_V_SPIMSS_MOD_NUMBITS_BITS5 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS5 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS6                 ((uint32_t)0x6UL) /**< MOD_NUMBITS_BITS6 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS6                 (MXC_V_SPIMSS_MOD_NUMBITS_BITS6 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS6 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS7                 ((uint32_t)0x7UL) /**< MOD_NUMBITS_BITS7 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS7                 (MXC_V_SPIMSS_MOD_NUMBITS_BITS7 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS7 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS8                 ((uint32_t)0x8UL) /**< MOD_NUMBITS_BITS8 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS8                 (MXC_V_SPIMSS_MOD_NUMBITS_BITS8 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS8 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS9                 ((uint32_t)0x9UL) /**< MOD_NUMBITS_BITS9 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS9                 (MXC_V_SPIMSS_MOD_NUMBITS_BITS9 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS9 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS10                ((uint32_t)0xAUL) /**< MOD_NUMBITS_BITS10 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS10                (MXC_V_SPIMSS_MOD_NUMBITS_BITS10 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS10 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS11                ((uint32_t)0xBUL) /**< MOD_NUMBITS_BITS11 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS11                (MXC_V_SPIMSS_MOD_NUMBITS_BITS11 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS11 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS12                ((uint32_t)0xCUL) /**< MOD_NUMBITS_BITS12 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS12                (MXC_V_SPIMSS_MOD_NUMBITS_BITS12 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS12 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS13                ((uint32_t)0xDUL) /**< MOD_NUMBITS_BITS13 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS13                (MXC_V_SPIMSS_MOD_NUMBITS_BITS13 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS13 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS14                ((uint32_t)0xEUL) /**< MOD_NUMBITS_BITS14 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS14                (MXC_V_SPIMSS_MOD_NUMBITS_BITS14 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS14 Setting */
+ #define MXC_V_SPIMSS_MOD_NUMBITS_BITS15                ((uint32_t)0xFUL) /**< MOD_NUMBITS_BITS15 Value */
+ #define MXC_S_SPIMSS_MOD_NUMBITS_BITS15                (MXC_V_SPIMSS_MOD_NUMBITS_BITS15 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS15 Setting */
+
+ #define MXC_F_SPIMSS_MOD_TX_LJ_POS                     7 /**< MOD_TX_LJ Position */
+ #define MXC_F_SPIMSS_MOD_TX_LJ                         ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_TX_LJ_POS)) /**< MOD_TX_LJ Mask */
+ #define MXC_V_SPIMSS_MOD_TX_LJ_DISABLE                 ((uint32_t)0x0UL) /**< MOD_TX_LJ_DISABLE Value */
+ #define MXC_S_SPIMSS_MOD_TX_LJ_DISABLE                 (MXC_V_SPIMSS_MOD_TX_LJ_DISABLE << MXC_F_SPIMSS_MOD_TX_LJ_POS) /**< MOD_TX_LJ_DISABLE Setting */
+ #define MXC_V_SPIMSS_MOD_TX_LJ_ENABLE                  ((uint32_t)0x1UL) /**< MOD_TX_LJ_ENABLE Value */
+ #define MXC_S_SPIMSS_MOD_TX_LJ_ENABLE                  (MXC_V_SPIMSS_MOD_TX_LJ_ENABLE << MXC_F_SPIMSS_MOD_TX_LJ_POS) /**< MOD_TX_LJ_ENABLE Setting */
+
+ #define MXC_F_SPIMSS_MOD_SSL1_POS                      8 /**< MOD_SSL1 Position */
+ #define MXC_F_SPIMSS_MOD_SSL1                          ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL1_POS)) /**< MOD_SSL1 Mask */
+ #define MXC_V_SPIMSS_MOD_SSL1_HI                       ((uint32_t)0x0UL) /**< MOD_SSL1_HI Value */
+ #define MXC_S_SPIMSS_MOD_SSL1_HI                       (MXC_V_SPIMSS_MOD_SSL1_HI << MXC_F_SPIMSS_MOD_SSL1_POS) /**< MOD_SSL1_HI Setting */
+ #define MXC_V_SPIMSS_MOD_SSL1_LO                       ((uint32_t)0x1UL) /**< MOD_SSL1_LO Value */
+ #define MXC_S_SPIMSS_MOD_SSL1_LO                       (MXC_V_SPIMSS_MOD_SSL1_LO << MXC_F_SPIMSS_MOD_SSL1_POS) /**< MOD_SSL1_LO Setting */
+
+ #define MXC_F_SPIMSS_MOD_SSL2_POS                      9 /**< MOD_SSL2 Position */
+ #define MXC_F_SPIMSS_MOD_SSL2                          ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL2_POS)) /**< MOD_SSL2 Mask */
+ #define MXC_V_SPIMSS_MOD_SSL2_HI                       ((uint32_t)0x0UL) /**< MOD_SSL2_HI Value */
+ #define MXC_S_SPIMSS_MOD_SSL2_HI                       (MXC_V_SPIMSS_MOD_SSL2_HI << MXC_F_SPIMSS_MOD_SSL2_POS) /**< MOD_SSL2_HI Setting */
+ #define MXC_V_SPIMSS_MOD_SSL2_LO                       ((uint32_t)0x1UL) /**< MOD_SSL2_LO Value */
+ #define MXC_S_SPIMSS_MOD_SSL2_LO                       (MXC_V_SPIMSS_MOD_SSL2_LO << MXC_F_SPIMSS_MOD_SSL2_POS) /**< MOD_SSL2_LO Setting */
+
+ #define MXC_F_SPIMSS_MOD_SSL3_POS                      10 /**< MOD_SSL3 Position */
+ #define MXC_F_SPIMSS_MOD_SSL3                          ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL3_POS)) /**< MOD_SSL3 Mask */
+ #define MXC_V_SPIMSS_MOD_SSL3_HI                       ((uint32_t)0x0UL) /**< MOD_SSL3_HI Value */
+ #define MXC_S_SPIMSS_MOD_SSL3_HI                       (MXC_V_SPIMSS_MOD_SSL3_HI << MXC_F_SPIMSS_MOD_SSL3_POS) /**< MOD_SSL3_HI Setting */
+ #define MXC_V_SPIMSS_MOD_SSL3_LO                       ((uint32_t)0x1UL) /**< MOD_SSL3_LO Value */
+ #define MXC_S_SPIMSS_MOD_SSL3_LO                       (MXC_V_SPIMSS_MOD_SSL3_LO << MXC_F_SPIMSS_MOD_SSL3_POS) /**< MOD_SSL3_LO Setting */
+
+/**@} end of group SPIMSS_MOD_Register */
+
+/**
+ * @ingroup  spimss_registers
+ * @defgroup SPIMSS_BRG SPIMSS_BRG
+ * @brief    Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for
+ *           the SPI Baud Rate Generator. The reload value must be greater than or equal to
+ *           0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by
+ *           4).
+ * @{
+ */
+ #define MXC_F_SPIMSS_BRG_BRG_POS                       0 /**< BRG_BRG Position */
+ #define MXC_F_SPIMSS_BRG_BRG                           ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_BRG_POS)) /**< BRG_BRG Mask */
+
+/**@} end of group SPIMSS_BRG_Register */
+
+/**
+ * @ingroup  spimss_registers
+ * @defgroup SPIMSS_DMA SPIMSS_DMA
+ * @brief    SPI DMA Register.
+ * @{
+ */
+ #define MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS             0 /**< DMA_TX_FIFO_LEVEL Position */
+ #define MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL                 ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */
+ #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1          ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LEVEL_ENTRY1 Value */
+ #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1          (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRY1 Setting */
+ #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2        ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES2 Value */
+ #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2        (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES2 Setting */
+ #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3        ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES3 Value */
+ #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3        (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES3 Setting */
+ #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4        ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES4 Value */
+ #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4        (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES4 Setting */
+ #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5        ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES5 Value */
+ #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5        (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES5 Setting */
+ #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6        ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES6 Value */
+ #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6        (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES6 Setting */
+ #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7        ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES7 Value */
+ #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7        (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES7 Setting */
+ #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8        ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES8 Value */
+ #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8        (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES8 Setting */
+
+ #define MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS             4 /**< DMA_TX_FIFO_CLEAR Position */
+ #define MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR                 ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */
+ #define MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE        ((uint32_t)0x0UL) /**< DMA_TX_FIFO_CLEAR_COMPLETE Value */
+ #define MXC_S_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE        (MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_COMPLETE Setting */
+ #define MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_START           ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_START Value */
+ #define MXC_S_SPIMSS_DMA_TX_FIFO_CLEAR_START           (MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_START << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_START Setting */
+
+ #define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS               8 /**< DMA_TX_FIFO_CNT Position */
+ #define MXC_F_SPIMSS_DMA_TX_FIFO_CNT                   ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
+
+ #define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS                 15 /**< DMA_TX_DMA_EN Position */
+ #define MXC_F_SPIMSS_DMA_TX_DMA_EN                     ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
+ #define MXC_V_SPIMSS_DMA_TX_DMA_EN_DISABLE             ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DISABLE Value */
+ #define MXC_S_SPIMSS_DMA_TX_DMA_EN_DISABLE             (MXC_V_SPIMSS_DMA_TX_DMA_EN_DISABLE << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DISABLE Setting */
+ #define MXC_V_SPIMSS_DMA_TX_DMA_EN_ENABLE              ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_ENABLE Value */
+ #define MXC_S_SPIMSS_DMA_TX_DMA_EN_ENABLE              (MXC_V_SPIMSS_DMA_TX_DMA_EN_ENABLE << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_ENABLE Setting */
+
+ #define MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS             16 /**< DMA_RX_FIFO_LEVEL Position */
+ #define MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL                 ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */
+ #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1          ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LEVEL_ENTRY1 Value */
+ #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1          (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRY1 Setting */
+ #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2        ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES2 Value */
+ #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2        (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES2 Setting */
+ #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3        ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES3 Value */
+ #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3        (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES3 Setting */
+ #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4        ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES4 Value */
+ #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4        (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES4 Setting */
+ #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5        ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES5 Value */
+ #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5        (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES5 Setting */
+ #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6        ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES6 Value */
+ #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6        (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES6 Setting */
+ #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7        ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES7 Value */
+ #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7        (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES7 Setting */
+ #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8        ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES8 Value */
+ #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8        (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES8 Setting */
+
+ #define MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS             20 /**< DMA_RX_FIFO_CLEAR Position */
+ #define MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR                 ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */
+ #define MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE        ((uint32_t)0x0UL) /**< DMA_RX_FIFO_CLEAR_COMPLETE Value */
+ #define MXC_S_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE        (MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_COMPLETE Setting */
+ #define MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_START           ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_START Value */
+ #define MXC_S_SPIMSS_DMA_RX_FIFO_CLEAR_START           (MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_START << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_START Setting */
+
+ #define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS               24 /**< DMA_RX_FIFO_CNT Position */
+ #define MXC_F_SPIMSS_DMA_RX_FIFO_CNT                   ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
+
+ #define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS                 31 /**< DMA_RX_DMA_EN Position */
+ #define MXC_F_SPIMSS_DMA_RX_DMA_EN                     ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
+ #define MXC_V_SPIMSS_DMA_RX_DMA_EN_DISABLE             ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DISABLE Value */
+ #define MXC_S_SPIMSS_DMA_RX_DMA_EN_DISABLE             (MXC_V_SPIMSS_DMA_RX_DMA_EN_DISABLE << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DISABLE Setting */
+ #define MXC_V_SPIMSS_DMA_RX_DMA_EN_ENABLE              ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_ENABLE Value */
+ #define MXC_S_SPIMSS_DMA_RX_DMA_EN_ENABLE              (MXC_V_SPIMSS_DMA_RX_DMA_EN_ENABLE << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_ENABLE Setting */
+
+/**@} end of group SPIMSS_DMA_Register */
+
+/**
+ * @ingroup  spimss_registers
+ * @defgroup SPIMSS_I2S_CTRL SPIMSS_I2S_CTRL
+ * @brief    I2S Control Register.
+ * @{
+ */
+ #define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS               0 /**< I2S_CTRL_I2S_EN Position */
+ #define MXC_F_SPIMSS_I2S_CTRL_I2S_EN                   ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */
+ #define MXC_V_SPIMSS_I2S_CTRL_I2S_EN_DISABLE           ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_EN_DISABLE Value */
+ #define MXC_S_SPIMSS_I2S_CTRL_I2S_EN_DISABLE           (MXC_V_SPIMSS_I2S_CTRL_I2S_EN_DISABLE << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_DISABLE Setting */
+ #define MXC_V_SPIMSS_I2S_CTRL_I2S_EN_ENABLE            ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_EN_ENABLE Value */
+ #define MXC_S_SPIMSS_I2S_CTRL_I2S_EN_ENABLE            (MXC_V_SPIMSS_I2S_CTRL_I2S_EN_ENABLE << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_ENABLE Setting */
+
+ #define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS             1 /**< I2S_CTRL_I2S_MUTE Position */
+ #define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE                 ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */
+ #define MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL          ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MUTE_NORMAL Value */
+ #define MXC_S_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL          (MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_NORMAL Setting */
+ #define MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED        ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MUTE_REPLACED Value */
+ #define MXC_S_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED        (MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_REPLACED Setting */
+
+ #define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS            2 /**< I2S_CTRL_I2S_PAUSE Position */
+ #define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE                ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */
+ #define MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL         ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_PAUSE_NORMAL Value */
+ #define MXC_S_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL         (MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_NORMAL Setting */
+ #define MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT           ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_PAUSE_HALT Value */
+ #define MXC_S_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT           (MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_HALT Setting */
+
+ #define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS             3 /**< I2S_CTRL_I2S_MONO Position */
+ #define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO                 ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */
+ #define MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC    ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Value */
+ #define MXC_S_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC    (MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Setting */
+ #define MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC      ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Value */
+ #define MXC_S_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC      (MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Setting */
+
+ #define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS               4 /**< I2S_CTRL_I2S_LJ Position */
+ #define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ                   ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */
+ #define MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL            ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_LJ_NORMAL Value */
+ #define MXC_S_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL            (MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_NORMAL Setting */
+ #define MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED          ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_LJ_REPLACED Value */
+ #define MXC_S_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED          (MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_REPLACED Setting */
+
+/**@} end of group SPIMSS_I2S_CTRL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SPIMSS_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h

@@ -0,0 +1,93 @@
+/**
+ * @file    system_max32660.h
+ * @brief   System-specific header file
+ */
+
+
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+#ifndef _SYSTEM_MAX32660_H_
+#define _SYSTEM_MAX32660_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+
+#ifndef HFX_FREQ
+#define HFX_FREQ                32768
+#endif
+
+#ifndef NANORING_FREQ
+#define NANORING_FREQ           8000
+#endif
+
+#ifndef HIRC96_FREQ
+#define HIRC96_FREQ             96000000
+#endif
+
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */
+#ifndef PeripheralClock
+#define         PeripheralClock     (SystemCoreClock /2)    /*!< Peripheral Clock Frequency */
+#endif
+
+/*
+ * Initialize the system
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/*
+ * Update SystemCoreClock variable
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_MAX32660_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h

@@ -0,0 +1,233 @@
+/**
+ * @file    tmr_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _TMR_REGS_H_
+#define _TMR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     tmr
+ * @defgroup    tmr_registers TMR_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
+ * @details 32-bit reloadable timer that can be used for timing and event counting.
+ */
+
+/**
+ * @ingroup tmr_registers
+ * Structure type to access the TMR Registers.
+ */
+typedef struct {
+    __IO uint32_t cnt;                  /**< <tt>\b 0x00:</tt> TMR CNT Register */
+    __IO uint32_t cmp;                  /**< <tt>\b 0x04:</tt> TMR CMP Register */
+    __IO uint32_t pwm;                  /**< <tt>\b 0x08:</tt> TMR PWM Register */
+    __IO uint32_t intr;                 /**< <tt>\b 0x0C:</tt> TMR INTR Register */
+    __IO uint32_t cn;                   /**< <tt>\b 0x10:</tt> TMR CN Register */
+    __IO uint32_t nolcmp;               /**< <tt>\b 0x14:</tt> TMR NOLCMP Register */
+} mxc_tmr_regs_t;
+
+/* Register offsets for module TMR */
+/**
+ * @ingroup    tmr_registers
+ * @defgroup   TMR_Register_Offsets Register Offsets
+ * @brief      TMR Peripheral Register Offsets from the TMR Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_TMR_CNT                      ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_TMR_CMP                      ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_TMR_PWM                      ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_TMR_INTR                     ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_TMR_CN                       ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_TMR_NOLCMP                   ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> 0x0014</tt> */ 
+/**@} end of group tmr_registers */
+
+/**
+ * @ingroup  tmr_registers
+ * @defgroup TMR_INTR TMR_INTR
+ * @brief    Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the
+ *           associated interrupt.
+ * @{
+ */
+ #define MXC_F_TMR_INTR_IRQ_CLR_POS                     0 /**< INTR_IRQ_CLR Position */
+ #define MXC_F_TMR_INTR_IRQ_CLR                         ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */
+
+/**@} end of group TMR_INTR_Register */
+
+/**
+ * @ingroup  tmr_registers
+ * @defgroup TMR_CN TMR_CN
+ * @brief    Timer Control Register.
+ * @{
+ */
+ #define MXC_F_TMR_CN_TMODE_POS                         0 /**< CN_TMODE Position */
+ #define MXC_F_TMR_CN_TMODE                             ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */
+ #define MXC_V_TMR_CN_TMODE_ONESHOT                     ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */
+ #define MXC_S_TMR_CN_TMODE_ONESHOT                     (MXC_V_TMR_CN_TMODE_ONESHOT << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */
+ #define MXC_V_TMR_CN_TMODE_CONTINUOUS                  ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */
+ #define MXC_S_TMR_CN_TMODE_CONTINUOUS                  (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */
+ #define MXC_V_TMR_CN_TMODE_COUNTER                     ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */
+ #define MXC_S_TMR_CN_TMODE_COUNTER                     (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */
+ #define MXC_V_TMR_CN_TMODE_PWM                         ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */
+ #define MXC_S_TMR_CN_TMODE_PWM                         (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */
+ #define MXC_V_TMR_CN_TMODE_CAPTURE                     ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */
+ #define MXC_S_TMR_CN_TMODE_CAPTURE                     (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */
+ #define MXC_V_TMR_CN_TMODE_COMPARE                     ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */
+ #define MXC_S_TMR_CN_TMODE_COMPARE                     (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */
+ #define MXC_V_TMR_CN_TMODE_GATED                       ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */
+ #define MXC_S_TMR_CN_TMODE_GATED                       (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
+ #define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE              ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */
+ #define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE              (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */
+
+ #define MXC_F_TMR_CN_PRES_POS                          3 /**< CN_PRES Position */
+ #define MXC_F_TMR_CN_PRES                              ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */
+ #define MXC_V_TMR_CN_PRES_DIV1                         ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */
+ #define MXC_S_TMR_CN_PRES_DIV1                         (MXC_V_TMR_CN_PRES_DIV1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */
+ #define MXC_V_TMR_CN_PRES_DIV2                         ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */
+ #define MXC_S_TMR_CN_PRES_DIV2                         (MXC_V_TMR_CN_PRES_DIV2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */
+ #define MXC_V_TMR_CN_PRES_DIV4                         ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */
+ #define MXC_S_TMR_CN_PRES_DIV4                         (MXC_V_TMR_CN_PRES_DIV4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */
+ #define MXC_V_TMR_CN_PRES_DIV8                         ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */
+ #define MXC_S_TMR_CN_PRES_DIV8                         (MXC_V_TMR_CN_PRES_DIV8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */
+ #define MXC_V_TMR_CN_PRES_DIV16                        ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */
+ #define MXC_S_TMR_CN_PRES_DIV16                        (MXC_V_TMR_CN_PRES_DIV16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */
+ #define MXC_V_TMR_CN_PRES_DIV32                        ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */
+ #define MXC_S_TMR_CN_PRES_DIV32                        (MXC_V_TMR_CN_PRES_DIV32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */
+ #define MXC_V_TMR_CN_PRES_DIV64                        ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */
+ #define MXC_S_TMR_CN_PRES_DIV64                        (MXC_V_TMR_CN_PRES_DIV64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */
+ #define MXC_V_TMR_CN_PRES_DIV128                       ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value */
+ #define MXC_S_TMR_CN_PRES_DIV128                       (MXC_V_TMR_CN_PRES_DIV128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */
+
+ #define MXC_F_TMR_CN_TPOL_POS                          6 /**< CN_TPOL Position */
+ #define MXC_F_TMR_CN_TPOL                              ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */
+ #define MXC_V_TMR_CN_TPOL_ACTIVEHI                     ((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */
+ #define MXC_S_TMR_CN_TPOL_ACTIVEHI                     (MXC_V_TMR_CN_TPOL_ACTIVEHI << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */
+ #define MXC_V_TMR_CN_TPOL_ACTIVELO                     ((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */
+ #define MXC_S_TMR_CN_TPOL_ACTIVELO                     (MXC_V_TMR_CN_TPOL_ACTIVELO << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */
+
+ #define MXC_F_TMR_CN_TEN_POS                           7 /**< CN_TEN Position */
+ #define MXC_F_TMR_CN_TEN                               ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */
+ #define MXC_V_TMR_CN_TEN_DIS                           ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */
+ #define MXC_S_TMR_CN_TEN_DIS                           (MXC_V_TMR_CN_TEN_DIS << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting */
+ #define MXC_V_TMR_CN_TEN_EN                            ((uint32_t)0x1UL) /**< CN_TEN_EN Value */
+ #define MXC_S_TMR_CN_TEN_EN                            (MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting */
+
+ #define MXC_F_TMR_CN_PRES3_POS                         8 /**< CN_PRES3 Position */
+ #define MXC_F_TMR_CN_PRES3                             ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */
+
+ #define MXC_F_TMR_CN_PWMSYNC_POS                       9 /**< CN_PWMSYNC Position */
+ #define MXC_F_TMR_CN_PWMSYNC                           ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */
+ #define MXC_V_TMR_CN_PWMSYNC_DIS                       ((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value */
+ #define MXC_S_TMR_CN_PWMSYNC_DIS                       (MXC_V_TMR_CN_PWMSYNC_DIS << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_DIS Setting */
+ #define MXC_V_TMR_CN_PWMSYNC_EN                        ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */
+ #define MXC_S_TMR_CN_PWMSYNC_EN                        (MXC_V_TMR_CN_PWMSYNC_EN << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */
+
+ #define MXC_F_TMR_CN_NOLHPOL_POS                       10 /**< CN_NOLHPOL Position */
+ #define MXC_F_TMR_CN_NOLHPOL                           ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */
+ #define MXC_V_TMR_CN_NOLHPOL_DIS                       ((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value */
+ #define MXC_S_TMR_CN_NOLHPOL_DIS                       (MXC_V_TMR_CN_NOLHPOL_DIS << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_DIS Setting */
+ #define MXC_V_TMR_CN_NOLHPOL_EN                        ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */
+ #define MXC_S_TMR_CN_NOLHPOL_EN                        (MXC_V_TMR_CN_NOLHPOL_EN << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */
+
+ #define MXC_F_TMR_CN_NOLLPOL_POS                       11 /**< CN_NOLLPOL Position */
+ #define MXC_F_TMR_CN_NOLLPOL                           ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */
+ #define MXC_V_TMR_CN_NOLLPOL_DIS                       ((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value */
+ #define MXC_S_TMR_CN_NOLLPOL_DIS                       (MXC_V_TMR_CN_NOLLPOL_DIS << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_DIS Setting */
+ #define MXC_V_TMR_CN_NOLLPOL_EN                        ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */
+ #define MXC_S_TMR_CN_NOLLPOL_EN                        (MXC_V_TMR_CN_NOLLPOL_EN << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */
+
+ #define MXC_F_TMR_CN_PWMCKBD_POS                       12 /**< CN_PWMCKBD Position */
+ #define MXC_F_TMR_CN_PWMCKBD                           ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */
+ #define MXC_V_TMR_CN_PWMCKBD_DIS                       ((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value */
+ #define MXC_S_TMR_CN_PWMCKBD_DIS                       (MXC_V_TMR_CN_PWMCKBD_DIS << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_DIS Setting */
+ #define MXC_V_TMR_CN_PWMCKBD_EN                        ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */
+ #define MXC_S_TMR_CN_PWMCKBD_EN                        (MXC_V_TMR_CN_PWMCKBD_EN << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */
+
+/**@} end of group TMR_CN_Register */
+
+/**
+ * @ingroup  tmr_registers
+ * @defgroup TMR_NOLCMP TMR_NOLCMP
+ * @brief    Timer Non-Overlapping Compare Register.
+ * @{
+ */
+ #define MXC_F_TMR_NOLCMP_NOLLCMP_POS                   0 /**< NOLCMP_NOLLCMP Position */
+ #define MXC_F_TMR_NOLCMP_NOLLCMP                       ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */
+
+ #define MXC_F_TMR_NOLCMP_NOLHCMP_POS                   8 /**< NOLCMP_NOLHCMP Position */
+ #define MXC_F_TMR_NOLCMP_NOLHCMP                       ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */
+
+/**@} end of group TMR_NOLCMP_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TMR_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h

@@ -0,0 +1,450 @@
+/**
+ * @file    uart_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _UART_REGS_H_
+#define _UART_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     uart
+ * @defgroup    uart_registers UART_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
+ * @details UART
+ */
+
+/**
+ * @ingroup uart_registers
+ * Structure type to access the UART Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x00:</tt> UART CTRL Register */
+    __IO uint32_t thresh_ctrl;          /**< <tt>\b 0x04:</tt> UART THRESH_CTRL Register */
+    __I  uint32_t status;               /**< <tt>\b 0x08:</tt> UART STATUS Register */
+    __IO uint32_t int_en;               /**< <tt>\b 0x0C:</tt> UART INT_EN Register */
+    __IO uint32_t int_fl;               /**< <tt>\b 0x10:</tt> UART INT_FL Register */
+    __IO uint32_t baud0;                /**< <tt>\b 0x14:</tt> UART BAUD0 Register */
+    __IO uint32_t baud1;                /**< <tt>\b 0x18:</tt> UART BAUD1 Register */
+    __IO uint32_t fifo;                 /**< <tt>\b 0x1C:</tt> UART FIFO Register */
+    __IO uint32_t dma;                  /**< <tt>\b 0x20:</tt> UART DMA Register */
+    __IO uint32_t tx_fifo;              /**< <tt>\b 0x24:</tt> UART TX_FIFO Register */
+} mxc_uart_regs_t;
+
+/* Register offsets for module UART */
+/**
+ * @ingroup    uart_registers
+ * @defgroup   UART_Register_Offsets Register Offsets
+ * @brief      UART Peripheral Register Offsets from the UART Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_UART_CTRL                    ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_UART_THRESH_CTRL             ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */ 
+ #define MXC_R_UART_STATUS                  ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */ 
+ #define MXC_R_UART_INT_EN                  ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */ 
+ #define MXC_R_UART_INT_FL                  ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */ 
+ #define MXC_R_UART_BAUD0                   ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */ 
+ #define MXC_R_UART_BAUD1                   ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */ 
+ #define MXC_R_UART_FIFO                    ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */ 
+ #define MXC_R_UART_DMA                     ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */ 
+ #define MXC_R_UART_TX_FIFO                 ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> 0x0024</tt> */ 
+/**@} end of group uart_registers */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_CTRL UART_CTRL
+ * @brief    Control Register.
+ * @{
+ */
+ #define MXC_F_UART_CTRL_ENABLE_POS                     0 /**< CTRL_ENABLE Position */
+ #define MXC_F_UART_CTRL_ENABLE                         ((uint32_t)(0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */
+ #define MXC_V_UART_CTRL_ENABLE_DIS                     ((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */
+ #define MXC_S_UART_CTRL_ENABLE_DIS                     (MXC_V_UART_CTRL_ENABLE_DIS << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */
+ #define MXC_V_UART_CTRL_ENABLE_EN                      ((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value */
+ #define MXC_S_UART_CTRL_ENABLE_EN                      (MXC_V_UART_CTRL_ENABLE_EN << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */
+
+ #define MXC_F_UART_CTRL_PARITY_EN_POS                  1 /**< CTRL_PARITY_EN Position */
+ #define MXC_F_UART_CTRL_PARITY_EN                      ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */
+ #define MXC_V_UART_CTRL_PARITY_EN_DIS                  ((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */
+ #define MXC_S_UART_CTRL_PARITY_EN_DIS                  (MXC_V_UART_CTRL_PARITY_EN_DIS << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */
+ #define MXC_V_UART_CTRL_PARITY_EN_EN                   ((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */
+ #define MXC_S_UART_CTRL_PARITY_EN_EN                   (MXC_V_UART_CTRL_PARITY_EN_EN << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */
+
+ #define MXC_F_UART_CTRL_PARITY_POS                     2 /**< CTRL_PARITY Position */
+ #define MXC_F_UART_CTRL_PARITY                         ((uint32_t)(0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */
+ #define MXC_V_UART_CTRL_PARITY_EVEN                    ((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */
+ #define MXC_S_UART_CTRL_PARITY_EVEN                    (MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */
+ #define MXC_V_UART_CTRL_PARITY_ODD                     ((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */
+ #define MXC_S_UART_CTRL_PARITY_ODD                     (MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */
+ #define MXC_V_UART_CTRL_PARITY_MARK                    ((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */
+ #define MXC_S_UART_CTRL_PARITY_MARK                    (MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */
+ #define MXC_V_UART_CTRL_PARITY_SPACE                   ((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */
+ #define MXC_S_UART_CTRL_PARITY_SPACE                   (MXC_V_UART_CTRL_PARITY_SPACE << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */
+
+ #define MXC_F_UART_CTRL_PARMD_POS                      4 /**< CTRL_PARMD Position */
+ #define MXC_F_UART_CTRL_PARMD                          ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask */
+ #define MXC_V_UART_CTRL_PARMD_1                        ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */
+ #define MXC_S_UART_CTRL_PARMD_1                        (MXC_V_UART_CTRL_PARMD_1 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_1 Setting */
+ #define MXC_V_UART_CTRL_PARMD_0                        ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */
+ #define MXC_S_UART_CTRL_PARMD_0                        (MXC_V_UART_CTRL_PARMD_0 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */
+
+ #define MXC_F_UART_CTRL_TX_FLUSH_POS                   5 /**< CTRL_TX_FLUSH Position */
+ #define MXC_F_UART_CTRL_TX_FLUSH                       ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */
+
+ #define MXC_F_UART_CTRL_RX_FLUSH_POS                   6 /**< CTRL_RX_FLUSH Position */
+ #define MXC_F_UART_CTRL_RX_FLUSH                       ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */
+
+ #define MXC_F_UART_CTRL_BITACC_POS                     7 /**< CTRL_BITACC Position */
+ #define MXC_F_UART_CTRL_BITACC                         ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */
+ #define MXC_V_UART_CTRL_BITACC_FRAME                   ((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */
+ #define MXC_S_UART_CTRL_BITACC_FRAME                   (MXC_V_UART_CTRL_BITACC_FRAME << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */
+ #define MXC_V_UART_CTRL_BITACC_BIT                     ((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */
+ #define MXC_S_UART_CTRL_BITACC_BIT                     (MXC_V_UART_CTRL_BITACC_BIT << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */
+
+ #define MXC_F_UART_CTRL_CHAR_SIZE_POS                  8 /**< CTRL_CHAR_SIZE Position */
+ #define MXC_F_UART_CTRL_CHAR_SIZE                      ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */
+ #define MXC_V_UART_CTRL_CHAR_SIZE_5                    ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */
+ #define MXC_S_UART_CTRL_CHAR_SIZE_5                    (MXC_V_UART_CTRL_CHAR_SIZE_5 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */
+ #define MXC_V_UART_CTRL_CHAR_SIZE_6                    ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */
+ #define MXC_S_UART_CTRL_CHAR_SIZE_6                    (MXC_V_UART_CTRL_CHAR_SIZE_6 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */
+ #define MXC_V_UART_CTRL_CHAR_SIZE_7                    ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */
+ #define MXC_S_UART_CTRL_CHAR_SIZE_7                    (MXC_V_UART_CTRL_CHAR_SIZE_7 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */
+ #define MXC_V_UART_CTRL_CHAR_SIZE_8                    ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */
+ #define MXC_S_UART_CTRL_CHAR_SIZE_8                    (MXC_V_UART_CTRL_CHAR_SIZE_8 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */
+
+ #define MXC_F_UART_CTRL_STOPBITS_POS                   10 /**< CTRL_STOPBITS Position */
+ #define MXC_F_UART_CTRL_STOPBITS                       ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */
+ #define MXC_V_UART_CTRL_STOPBITS_1                     ((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */
+ #define MXC_S_UART_CTRL_STOPBITS_1                     (MXC_V_UART_CTRL_STOPBITS_1 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */
+ #define MXC_V_UART_CTRL_STOPBITS_1_5                   ((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */
+ #define MXC_S_UART_CTRL_STOPBITS_1_5                   (MXC_V_UART_CTRL_STOPBITS_1_5 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */
+
+ #define MXC_F_UART_CTRL_FLOW_CTRL_POS                  11 /**< CTRL_FLOW_CTRL Position */
+ #define MXC_F_UART_CTRL_FLOW_CTRL                      ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */
+ #define MXC_V_UART_CTRL_FLOW_CTRL_EN                   ((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */
+ #define MXC_S_UART_CTRL_FLOW_CTRL_EN                   (MXC_V_UART_CTRL_FLOW_CTRL_EN << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */
+ #define MXC_V_UART_CTRL_FLOW_CTRL_DIS                  ((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */
+ #define MXC_S_UART_CTRL_FLOW_CTRL_DIS                  (MXC_V_UART_CTRL_FLOW_CTRL_DIS << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */
+
+ #define MXC_F_UART_CTRL_FLOW_POL_POS                   12 /**< CTRL_FLOW_POL Position */
+ #define MXC_F_UART_CTRL_FLOW_POL                       ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */
+ #define MXC_V_UART_CTRL_FLOW_POL_0                     ((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */
+ #define MXC_S_UART_CTRL_FLOW_POL_0                     (MXC_V_UART_CTRL_FLOW_POL_0 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */
+ #define MXC_V_UART_CTRL_FLOW_POL_1                     ((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */
+ #define MXC_S_UART_CTRL_FLOW_POL_1                     (MXC_V_UART_CTRL_FLOW_POL_1 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */
+
+ #define MXC_F_UART_CTRL_NULL_MODEM_POS                 13 /**< CTRL_NULL_MODEM Position */
+ #define MXC_F_UART_CTRL_NULL_MODEM                     ((uint32_t)(0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM Mask */
+ #define MXC_V_UART_CTRL_NULL_MODEM_DIS                 ((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */
+ #define MXC_S_UART_CTRL_NULL_MODEM_DIS                 (MXC_V_UART_CTRL_NULL_MODEM_DIS << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting */
+ #define MXC_V_UART_CTRL_NULL_MODEM_EN                  ((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */
+ #define MXC_S_UART_CTRL_NULL_MODEM_EN                  (MXC_V_UART_CTRL_NULL_MODEM_EN << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */
+
+ #define MXC_F_UART_CTRL_BREAK_POS                      14 /**< CTRL_BREAK Position */
+ #define MXC_F_UART_CTRL_BREAK                          ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask */
+ #define MXC_V_UART_CTRL_BREAK_DIS                      ((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value */
+ #define MXC_S_UART_CTRL_BREAK_DIS                      (MXC_V_UART_CTRL_BREAK_DIS << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */
+ #define MXC_V_UART_CTRL_BREAK_EN                       ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */
+ #define MXC_S_UART_CTRL_BREAK_EN                       (MXC_V_UART_CTRL_BREAK_EN << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */
+
+ #define MXC_F_UART_CTRL_CLKSEL_POS                     15 /**< CTRL_CLKSEL Position */
+ #define MXC_F_UART_CTRL_CLKSEL                         ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */
+ #define MXC_V_UART_CTRL_CLKSEL_SYSTEM                  ((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */
+ #define MXC_S_UART_CTRL_CLKSEL_SYSTEM                  (MXC_V_UART_CTRL_CLKSEL_SYSTEM << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */
+ #define MXC_V_UART_CTRL_CLKSEL_ALTERNATE               ((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */
+ #define MXC_S_UART_CTRL_CLKSEL_ALTERNATE               (MXC_V_UART_CTRL_CLKSEL_ALTERNATE << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */
+
+ #define MXC_F_UART_CTRL_RX_TO_POS                      16 /**< CTRL_RX_TO Position */
+ #define MXC_F_UART_CTRL_RX_TO                          ((uint32_t)(0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */
+
+/**@} end of group UART_CTRL_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_THRESH_CTRL UART_THRESH_CTRL
+ * @brief    Threshold Control register.
+ * @{
+ */
+ #define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS      0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */
+ #define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH          ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**< THRESH_CTRL_RX_FIFO_THRESH Mask */
+
+ #define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS      8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */
+ #define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH          ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**< THRESH_CTRL_TX_FIFO_THRESH Mask */
+
+ #define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS     16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */
+ #define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH         ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**< THRESH_CTRL_RTS_FIFO_THRESH Mask */
+
+/**@} end of group UART_THRESH_CTRL_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_STATUS UART_STATUS
+ * @brief    Status Register.
+ * @{
+ */
+ #define MXC_F_UART_STATUS_TX_BUSY_POS                  0 /**< STATUS_TX_BUSY Position */
+ #define MXC_F_UART_STATUS_TX_BUSY                      ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */
+
+ #define MXC_F_UART_STATUS_RX_BUSY_POS                  1 /**< STATUS_RX_BUSY Position */
+ #define MXC_F_UART_STATUS_RX_BUSY                      ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */
+
+ #define MXC_F_UART_STATUS_PARITY_POS                   2 /**< STATUS_PARITY Position */
+ #define MXC_F_UART_STATUS_PARITY                       ((uint32_t)(0x1UL << MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */
+
+ #define MXC_F_UART_STATUS_BREAK_POS                    3 /**< STATUS_BREAK Position */
+ #define MXC_F_UART_STATUS_BREAK                        ((uint32_t)(0x1UL << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */
+
+ #define MXC_F_UART_STATUS_RX_EMPTY_POS                 4 /**< STATUS_RX_EMPTY Position */
+ #define MXC_F_UART_STATUS_RX_EMPTY                     ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */
+
+ #define MXC_F_UART_STATUS_RX_FULL_POS                  5 /**< STATUS_RX_FULL Position */
+ #define MXC_F_UART_STATUS_RX_FULL                      ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
+
+ #define MXC_F_UART_STATUS_TX_EMPTY_POS                 6 /**< STATUS_TX_EMPTY Position */
+ #define MXC_F_UART_STATUS_TX_EMPTY                     ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */
+
+ #define MXC_F_UART_STATUS_TX_FULL_POS                  7 /**< STATUS_TX_FULL Position */
+ #define MXC_F_UART_STATUS_TX_FULL                      ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
+
+ #define MXC_F_UART_STATUS_RX_FIFO_CNT_POS              8 /**< STATUS_RX_FIFO_CNT Position */
+ #define MXC_F_UART_STATUS_RX_FIFO_CNT                  ((uint32_t)(0x3FUL << MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT Mask */
+
+ #define MXC_F_UART_STATUS_TX_FIFO_CNT_POS              16 /**< STATUS_TX_FIFO_CNT Position */
+ #define MXC_F_UART_STATUS_TX_FIFO_CNT                  ((uint32_t)(0x3FUL << MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT Mask */
+
+ #define MXC_F_UART_STATUS_RX_TO_POS                    24 /**< STATUS_RX_TO Position */
+ #define MXC_F_UART_STATUS_RX_TO                        ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */
+
+/**@} end of group UART_STATUS_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_INT_EN UART_INT_EN
+ * @brief    Interrupt Enable Register.
+ * @{
+ */
+ #define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS           0 /**< INT_EN_RX_FRAME_ERROR Position */
+ #define MXC_F_UART_INT_EN_RX_FRAME_ERROR               ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */
+
+ #define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS          1 /**< INT_EN_RX_PARITY_ERROR Position */
+ #define MXC_F_UART_INT_EN_RX_PARITY_ERROR              ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */
+
+ #define MXC_F_UART_INT_EN_CTS_CHANGE_POS               2 /**< INT_EN_CTS_CHANGE Position */
+ #define MXC_F_UART_INT_EN_CTS_CHANGE                   ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE Mask */
+
+ #define MXC_F_UART_INT_EN_RX_OVERRUN_POS               3 /**< INT_EN_RX_OVERRUN Position */
+ #define MXC_F_UART_INT_EN_RX_OVERRUN                   ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */
+
+ #define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS           4 /**< INT_EN_RX_FIFO_THRESH Position */
+ #define MXC_F_UART_INT_EN_RX_FIFO_THRESH               ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**< INT_EN_RX_FIFO_THRESH Mask */
+
+ #define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS     5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */
+ #define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY         ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_EN_TX_FIFO_ALMOST_EMPTY Mask */
+
+ #define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS           6 /**< INT_EN_TX_FIFO_THRESH Position */
+ #define MXC_F_UART_INT_EN_TX_FIFO_THRESH               ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**< INT_EN_TX_FIFO_THRESH Mask */
+
+ #define MXC_F_UART_INT_EN_BREAK_POS                    7 /**< INT_EN_BREAK Position */
+ #define MXC_F_UART_INT_EN_BREAK                        ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */
+
+ #define MXC_F_UART_INT_EN_RX_TIMEOUT_POS               8 /**< INT_EN_RX_TIMEOUT Position */
+ #define MXC_F_UART_INT_EN_RX_TIMEOUT                   ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT Mask */
+
+ #define MXC_F_UART_INT_EN_LAST_BREAK_POS               9 /**< INT_EN_LAST_BREAK Position */
+ #define MXC_F_UART_INT_EN_LAST_BREAK                   ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */
+
+/**@} end of group UART_INT_EN_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_INT_FL UART_INT_FL
+ * @brief    Interrupt Status Flags.
+ * @{
+ */
+ #define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS           0 /**< INT_FL_RX_FRAME_ERROR Position */
+ #define MXC_F_UART_INT_FL_RX_FRAME_ERROR               ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**< INT_FL_RX_FRAME_ERROR Mask */
+
+ #define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS          1 /**< INT_FL_RX_PARITY_ERROR Position */
+ #define MXC_F_UART_INT_FL_RX_PARITY_ERROR              ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**< INT_FL_RX_PARITY_ERROR Mask */
+
+ #define MXC_F_UART_INT_FL_CTS_CHANGE_POS               2 /**< INT_FL_CTS_CHANGE Position */
+ #define MXC_F_UART_INT_FL_CTS_CHANGE                   ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE Mask */
+
+ #define MXC_F_UART_INT_FL_RX_OVERRUN_POS               3 /**< INT_FL_RX_OVERRUN Position */
+ #define MXC_F_UART_INT_FL_RX_OVERRUN                   ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN Mask */
+
+ #define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS           4 /**< INT_FL_RX_FIFO_THRESH Position */
+ #define MXC_F_UART_INT_FL_RX_FIFO_THRESH               ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**< INT_FL_RX_FIFO_THRESH Mask */
+
+ #define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS     5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */
+ #define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY         ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_FL_TX_FIFO_ALMOST_EMPTY Mask */
+
+ #define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS           6 /**< INT_FL_TX_FIFO_THRESH Position */
+ #define MXC_F_UART_INT_FL_TX_FIFO_THRESH               ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**< INT_FL_TX_FIFO_THRESH Mask */
+
+ #define MXC_F_UART_INT_FL_BREAK_POS                    7 /**< INT_FL_BREAK Position */
+ #define MXC_F_UART_INT_FL_BREAK                        ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */
+
+ #define MXC_F_UART_INT_FL_RX_TIMEOUT_POS               8 /**< INT_FL_RX_TIMEOUT Position */
+ #define MXC_F_UART_INT_FL_RX_TIMEOUT                   ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT Mask */
+
+ #define MXC_F_UART_INT_FL_LAST_BREAK_POS               9 /**< INT_FL_LAST_BREAK Position */
+ #define MXC_F_UART_INT_FL_LAST_BREAK                   ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */
+
+/**@} end of group UART_INT_FL_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_BAUD0 UART_BAUD0
+ * @brief    Baud rate register. Integer portion.
+ * @{
+ */
+ #define MXC_F_UART_BAUD0_IBAUD_POS                     0 /**< BAUD0_IBAUD Position */
+ #define MXC_F_UART_BAUD0_IBAUD                         ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */
+
+ #define MXC_F_UART_BAUD0_FACTOR_POS                    16 /**< BAUD0_FACTOR Position */
+ #define MXC_F_UART_BAUD0_FACTOR                        ((uint32_t)(0x3UL << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */
+ #define MXC_V_UART_BAUD0_FACTOR_128                    ((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */
+ #define MXC_S_UART_BAUD0_FACTOR_128                    (MXC_V_UART_BAUD0_FACTOR_128 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */
+ #define MXC_V_UART_BAUD0_FACTOR_64                     ((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */
+ #define MXC_S_UART_BAUD0_FACTOR_64                     (MXC_V_UART_BAUD0_FACTOR_64 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */
+ #define MXC_V_UART_BAUD0_FACTOR_32                     ((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */
+ #define MXC_S_UART_BAUD0_FACTOR_32                     (MXC_V_UART_BAUD0_FACTOR_32 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */
+ #define MXC_V_UART_BAUD0_FACTOR_16                     ((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */
+ #define MXC_S_UART_BAUD0_FACTOR_16                     (MXC_V_UART_BAUD0_FACTOR_16 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */
+
+/**@} end of group UART_BAUD0_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_BAUD1 UART_BAUD1
+ * @brief    Baud rate register. Decimal Setting.
+ * @{
+ */
+ #define MXC_F_UART_BAUD1_DBAUD_POS                     0 /**< BAUD1_DBAUD Position */
+ #define MXC_F_UART_BAUD1_DBAUD                         ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */
+
+/**@} end of group UART_BAUD1_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_FIFO UART_FIFO
+ * @brief    FIFO Data buffer.
+ * @{
+ */
+ #define MXC_F_UART_FIFO_FIFO_POS                       0 /**< FIFO_FIFO Position */
+ #define MXC_F_UART_FIFO_FIFO                           ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */
+
+/**@} end of group UART_FIFO_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_DMA UART_DMA
+ * @brief    DMA Configuration.
+ * @{
+ */
+ #define MXC_F_UART_DMA_TDMA_EN_POS                     0 /**< DMA_TDMA_EN Position */
+ #define MXC_F_UART_DMA_TDMA_EN                         ((uint32_t)(0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */
+ #define MXC_V_UART_DMA_TDMA_EN_DIS                     ((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */
+ #define MXC_S_UART_DMA_TDMA_EN_DIS                     (MXC_V_UART_DMA_TDMA_EN_DIS << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */
+ #define MXC_V_UART_DMA_TDMA_EN_EN                      ((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value */
+ #define MXC_S_UART_DMA_TDMA_EN_EN                      (MXC_V_UART_DMA_TDMA_EN_EN << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */
+
+ #define MXC_F_UART_DMA_RXDMA_EN_POS                    1 /**< DMA_RXDMA_EN Position */
+ #define MXC_F_UART_DMA_RXDMA_EN                        ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */
+ #define MXC_V_UART_DMA_RXDMA_EN_DIS                    ((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */
+ #define MXC_S_UART_DMA_RXDMA_EN_DIS                    (MXC_V_UART_DMA_RXDMA_EN_DIS << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */
+ #define MXC_V_UART_DMA_RXDMA_EN_EN                     ((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */
+ #define MXC_S_UART_DMA_RXDMA_EN_EN                     (MXC_V_UART_DMA_RXDMA_EN_EN << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */
+
+ #define MXC_F_UART_DMA_TXDMA_LEVEL_POS                 8 /**< DMA_TXDMA_LEVEL Position */
+ #define MXC_F_UART_DMA_TXDMA_LEVEL                     ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL Mask */
+
+ #define MXC_F_UART_DMA_RXDMA_LEVEL_POS                 16 /**< DMA_RXDMA_LEVEL Position */
+ #define MXC_F_UART_DMA_RXDMA_LEVEL                     ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL Mask */
+
+/**@} end of group UART_DMA_Register */
+
+/**
+ * @ingroup  uart_registers
+ * @defgroup UART_TX_FIFO UART_TX_FIFO
+ * @brief    Transmit FIFO Status register.
+ * @{
+ */
+ #define MXC_F_UART_TX_FIFO_DATA_POS                    0 /**< TX_FIFO_DATA Position */
+ #define MXC_F_UART_TX_FIFO_DATA                        ((uint32_t)(0x7FUL << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */
+
+/**@} end of group UART_TX_FIFO_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _UART_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h

@@ -0,0 +1,236 @@
+/**
+ * @file    wdt_regs.h
+ * @brief   Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _WDT_REGS_H_
+#define _WDT_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ 
+#if defined (__ICCARM__)
+  #pragma system_include
+#endif
+ 
+#if defined (__CC_ARM)
+  #pragma anon_unions
+#endif
+/// @cond
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I  volatile const
+#endif
+#ifndef __O
+#define __O  volatile
+#endif
+#ifndef __R
+#define __R  volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     wdt
+ * @defgroup    wdt_registers WDT_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
+ * @details Watchdog Timer 0
+ */
+
+/**
+ * @ingroup wdt_registers
+ * Structure type to access the WDT Registers.
+ */
+typedef struct {
+    __IO uint32_t ctrl;                 /**< <tt>\b 0x00:</tt> WDT CTRL Register */
+    __O  uint32_t rst;                  /**< <tt>\b 0x04:</tt> WDT RST Register */
+} mxc_wdt_regs_t;
+
+/* Register offsets for module WDT */
+/**
+ * @ingroup    wdt_registers
+ * @defgroup   WDT_Register_Offsets Register Offsets
+ * @brief      WDT Peripheral Register Offsets from the WDT Base Peripheral Address. 
+ * @{
+ */
+ #define MXC_R_WDT_CTRL                     ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> 0x0000</tt> */ 
+ #define MXC_R_WDT_RST                      ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> 0x0004</tt> */ 
+/**@} end of group wdt_registers */
+
+/**
+ * @ingroup  wdt_registers
+ * @defgroup WDT_CTRL WDT_CTRL
+ * @brief    Watchdog Timer Control Register.
+ * @{
+ */
+ #define MXC_F_WDT_CTRL_INT_PERIOD_POS                  0 /**< CTRL_INT_PERIOD Position */
+ #define MXC_F_WDT_CTRL_INT_PERIOD                      ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31            ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30            ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29            ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28            ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27            ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26            ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25            ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24            ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23            ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22            ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21            ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20            ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19            ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18            ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17            ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */
+ #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16            ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */
+ #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16            (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */
+
+ #define MXC_F_WDT_CTRL_RST_PERIOD_POS                  4 /**< CTRL_RST_PERIOD Position */
+ #define MXC_F_WDT_CTRL_RST_PERIOD                      ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31            ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30            ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29            ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28            ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27            ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26            ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25            ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24            ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23            ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22            ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21            ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20            ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19            ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18            ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17            ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */
+ #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16            ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */
+ #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16            (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */
+
+ #define MXC_F_WDT_CTRL_WDT_EN_POS                      8 /**< CTRL_WDT_EN Position */
+ #define MXC_F_WDT_CTRL_WDT_EN                          ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */
+ #define MXC_V_WDT_CTRL_WDT_EN_DIS                      ((uint32_t)0x0UL) /**< CTRL_WDT_EN_DIS Value */
+ #define MXC_S_WDT_CTRL_WDT_EN_DIS                      (MXC_V_WDT_CTRL_WDT_EN_DIS << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_DIS Setting */
+ #define MXC_V_WDT_CTRL_WDT_EN_EN                       ((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value */
+ #define MXC_S_WDT_CTRL_WDT_EN_EN                       (MXC_V_WDT_CTRL_WDT_EN_EN << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_EN Setting */
+
+ #define MXC_F_WDT_CTRL_INT_FLAG_POS                    9 /**< CTRL_INT_FLAG Position */
+ #define MXC_F_WDT_CTRL_INT_FLAG                        ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */
+ #define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE               ((uint32_t)0x0UL) /**< CTRL_INT_FLAG_INACTIVE Value */
+ #define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE               (MXC_V_WDT_CTRL_INT_FLAG_INACTIVE << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting */
+ #define MXC_V_WDT_CTRL_INT_FLAG_PENDING                ((uint32_t)0x1UL) /**< CTRL_INT_FLAG_PENDING Value */
+ #define MXC_S_WDT_CTRL_INT_FLAG_PENDING                (MXC_V_WDT_CTRL_INT_FLAG_PENDING << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_PENDING Setting */
+
+ #define MXC_F_WDT_CTRL_INT_EN_POS                      10 /**< CTRL_INT_EN Position */
+ #define MXC_F_WDT_CTRL_INT_EN                          ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */
+ #define MXC_V_WDT_CTRL_INT_EN_DIS                      ((uint32_t)0x0UL) /**< CTRL_INT_EN_DIS Value */
+ #define MXC_S_WDT_CTRL_INT_EN_DIS                      (MXC_V_WDT_CTRL_INT_EN_DIS << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_DIS Setting */
+ #define MXC_V_WDT_CTRL_INT_EN_EN                       ((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value */
+ #define MXC_S_WDT_CTRL_INT_EN_EN                       (MXC_V_WDT_CTRL_INT_EN_EN << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_EN Setting */
+
+ #define MXC_F_WDT_CTRL_RST_EN_POS                      11 /**< CTRL_RST_EN Position */
+ #define MXC_F_WDT_CTRL_RST_EN                          ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */
+ #define MXC_V_WDT_CTRL_RST_EN_DIS                      ((uint32_t)0x0UL) /**< CTRL_RST_EN_DIS Value */
+ #define MXC_S_WDT_CTRL_RST_EN_DIS                      (MXC_V_WDT_CTRL_RST_EN_DIS << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_DIS Setting */
+ #define MXC_V_WDT_CTRL_RST_EN_EN                       ((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value */
+ #define MXC_S_WDT_CTRL_RST_EN_EN                       (MXC_V_WDT_CTRL_RST_EN_EN << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_EN Setting */
+
+ #define MXC_F_WDT_CTRL_RST_FLAG_POS                    31 /**< CTRL_RST_FLAG Position */
+ #define MXC_F_WDT_CTRL_RST_FLAG                        ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */
+ #define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT                ((uint32_t)0x0UL) /**< CTRL_RST_FLAG_NOEVENT Value */
+ #define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT                (MXC_V_WDT_CTRL_RST_FLAG_NOEVENT << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_NOEVENT Setting */
+ #define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED               ((uint32_t)0x1UL) /**< CTRL_RST_FLAG_OCCURRED Value */
+ #define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED               (MXC_V_WDT_CTRL_RST_FLAG_OCCURRED << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting */
+
+/**@} end of group WDT_CTRL_Register */
+
+/**
+ * @ingroup  wdt_registers
+ * @defgroup WDT_RST WDT_RST
+ * @brief    Watchdog Timer Reset Register.
+ * @{
+ */
+ #define MXC_F_WDT_RST_WDT_RST_POS                      0 /**< RST_WDT_RST Position */
+ #define MXC_F_WDT_RST_WDT_RST                          ((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */
+ #define MXC_V_WDT_RST_WDT_RST_SEQ0                     ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */
+ #define MXC_S_WDT_RST_WDT_RST_SEQ0                     (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */
+ #define MXC_V_WDT_RST_WDT_RST_SEQ1                     ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */
+ #define MXC_S_WDT_RST_WDT_RST_SEQ1                     (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */
+
+/**@} end of group WDT_RST_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WDT_REGS_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/ARM/startup_max32660.s

@@ -0,0 +1,373 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ ; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ ;
+ ; Permission is hereby granted, free of charge, to any person obtaining a
+ ; copy of this software and associated documentation files (the "Software"),
+ ; to deal in the Software without restriction, including without limitation
+ ; the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ ; and/or sell copies of the Software, and to permit persons to whom the
+ ; Software is furnished to do so, subject to the following conditions:
+ ;
+ ; The above copyright notice and this permission notice shall be included
+ ; in all copies or substantial portions of the Software.
+ ;
+ ; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ ; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ ; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ ; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ ; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ ; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ ; OTHER DEALINGS IN THE SOFTWARE.
+ ;
+ ; Except as contained in this notice, the name of Maxim Integrated
+ ; Products, Inc. shall not be used except as stated in the Maxim Integrated
+ ; Products, Inc. Branding Policy.
+ ;
+ ; The mere transfer of this software does not imply any licenses
+ ; of trade secrets, proprietary technology, copyrights, patents,
+ ; trademarks, maskwork rights, or any other form of intellectual
+ ; property whatsoever. Maxim Integrated Products, Inc. retains all
+ ; ownership rights.
+ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; To map FreeRTOS function names to their CMSIS equivalents add following lines to FreeRTOSConfig.h
+; #define vPortSVCHandler SVC_Handler
+; #define xPortPendSVHandler PendSV_Handler
+; #define xPortSysTickHandler SysTick_Handler
+; *------- <<< Use Configuration Wizard in Context Menu to Modify Stack Size and Heap Size. >>> ----
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00001000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    ; Name used with Keil Configuration Wizard and Keil MicroLib
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+                EXPORT  __isr_vector
+                IMPORT  SysTick_Handler
+
+__isr_vector    DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; Device-specific Interrupts
+                DCD     PF_IRQHandler             ; 0x10  0x0040  16: Power Fail
+                DCD     WDT0_IRQHandler           ; 0x11  0x0044  17: Watchdog 0
+                DCD     RSV00_IRQHandler          ; 0x12  0x0048  18: RSV00
+                DCD     RTC_IRQHandler            ; 0x13  0x004C  19: RTC
+                DCD     RSV01_IRQHandler          ; 0x14  0x0050  20: RSV1
+                DCD     TMR0_IRQHandler           ; 0x15  0x0054  21: Timer 0
+                DCD     TMR1_IRQHandler           ; 0x16  0x0058  22: Timer 1
+                DCD     TMR2_IRQHandler           ; 0x17  0x005C  23: Timer 2
+                DCD     RSV02_IRQHandler          ; 0x18  0x0060  24: RSV02
+                DCD     RSV03_IRQHandler          ; 0x19  0x0064  25: RSV03
+                DCD     RSV04_IRQHandler          ; 0x1A  0x0068  26: RSV04
+                DCD     RSV05_IRQHandler          ; 0x1B  0x006C  27: RSV05
+                DCD     RSV06_IRQHandler          ; 0x1C  0x0070  28: RSV06
+                DCD     I2C0_IRQHandler           ; 0x1D  0x0074  29: I2C0
+                DCD     UART0_IRQHandler          ; 0x1E  0x0078  30: UART 0
+                DCD     UART1_IRQHandler          ; 0x1F  0x007C  31: UART 1
+                DCD     SPI0_IRQHandler           ; 0x20  0x0080  32: SPIY17
+                DCD     SPI1_IRQHandler           ; 0x21  0x0084  33: SPIMSS
+                DCD     RSV07_IRQHandler          ; 0x22  0x0088  34: RSV07
+                DCD     RSV08_IRQHandler          ; 0x23  0x008C  35: RSV08
+                DCD     RSV09_IRQHandler          ; 0x24  0x0090  36: RSV09
+                DCD     RSV10_IRQHandler          ; 0x25  0x0094  37: RSV10
+                DCD     RSV11_IRQHandler          ; 0x26  0x0098  38: RSV11
+                DCD     FLC_IRQHandler            ; 0x27  0x009C  39: FLC
+                DCD     GPIO0_IRQHandler          ; 0x28  0x00A0  40: GPIO0
+                DCD     RSV12_IRQHandler          ; 0x29  0x00A4  41: RSV12
+                DCD     RSV13_IRQHandler          ; 0x2A  0x00A8  42: RSV13
+                DCD     RSV14_IRQHandler          ; 0x2B  0x00AC  43: RSV14
+                DCD     DMA0_IRQHandler           ; 0x2C  0x00B0  44: DMA0
+                DCD     DMA1_IRQHandler           ; 0x2D  0x00B4  45: DMA1
+                DCD     DMA2_IRQHandler           ; 0x2E  0x00B8  46: DMA2
+                DCD     DMA3_IRQHandler           ; 0x2F  0x00BC  47: DMA3
+                DCD     RSV15_IRQHandler          ; 0x30  0x00C0  48: RSV15
+                DCD     RSV16_IRQHandler          ; 0x31  0x00C4  49: RSV16
+                DCD     RSV17_IRQHandler          ; 0x32  0x00C8  50: RSV17
+                DCD     RSV18_IRQHandler          ; 0x33  0x00CC  51: RSV18
+                DCD     I2C1_IRQHandler           ; 0x34  0x00D0  52: I2C1
+                DCD     RSV19_IRQHandler          ; 0x35  0x00D4  53: RSV19
+                DCD     RSV20_IRQHandler          ; 0x36  0x00D8  54: RSV20
+                DCD     RSV21_IRQHandler          ; 0x37  0x00DC  55: RSV21
+                DCD     RSV22_IRQHandler          ; 0x38  0x00E0  56: RSV22
+                DCD     RSV23_IRQHandler          ; 0x39  0x00E4  57: RSV23
+                DCD     RSV24_IRQHandler          ; 0x3A  0x00E8  58: RSV24
+                DCD     RSV25_IRQHandler          ; 0x3B  0x00EC  59: RSV25
+                DCD     RSV26_IRQHandler          ; 0x3C  0x00F0  60: RSV26
+                DCD     RSV27_IRQHandler          ; 0x3D  0x00F4  61: RSV27
+                DCD     RSV28_IRQHandler          ; 0x3E  0x00F8  62: RSV28
+                DCD     RSV29_IRQHandler          ; 0x3F  0x00FC  63: RSV29
+                DCD     RSV30_IRQHandler          ; 0x40  0x0100  64: RSV30
+                DCD     RSV31_IRQHandler          ; 0x41  0x0104  65: RSV31
+                DCD     RSV32_IRQHandler          ; 0x42  0x0108  66: RSV32
+                DCD     RSV33_IRQHandler          ; 0x43  0x010C  67: RSV33
+                DCD     RSV34_IRQHandler          ; 0x44  0x0110  68: RSV34
+                DCD     RSV35_IRQHandler          ; 0x45  0x0114  69: RSV35
+                DCD     GPIOWAKE_IRQHandler       ; 0x46  0x0118  70: GPIO Wakeup
+__isr_vector_end
+
+__isr_vector_size       EQU  __isr_vector_end - __isr_vector
+__Vectors       EQU     __isr_vector
+__Vectors_End   EQU     __isr_vector_end
+__Vectors_Size  EQU     __isr_vector_size
+
+                AREA    |.text|, CODE, READONLY
+
+Reset_Handler   PROC
+                EXPORT Reset_Handler                    [WEAK]
+                IMPORT PreInit
+                ;IMPORT SystemInit
+                IMPORT __main
+                LDR     R0, =PreInit            ; Call to PreInit (prior to RAM initialization)
+                BLX     R0
+                LDR     R0, =__main             ; SystemInit() is called from post scatter memory initialization in function  $Sub$$__main_after_scatterload - system_max32660.c
+                BX      R0
+__SPIN
+                WFI
+                BL __SPIN
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler             [WEAK]
+                B       .
+                ENDP
+
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler       [WEAK]
+                B       .
+                ENDP
+
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler       [WEAK]
+                B       .
+                ENDP
+
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler        [WEAK]
+                B       .
+                ENDP
+
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler      [WEAK]
+                B       .
+                ENDP
+
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler             [WEAK]
+                B       .
+                ENDP
+
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler        [WEAK]
+                B       .
+                ENDP
+
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler          [WEAK]
+                B       .
+                ENDP
+Default_Handler\
+                PROC
+                ; MAX32660 Device-specific Interrupts
+                EXPORT PF_IRQHandler            [WEAK] ;  0x10  0x0040  16: Power Fail
+                EXPORT WDT0_IRQHandler          [WEAK] ;  0x11  0x0044  17: Watchdog 0
+                EXPORT RSV00_IRQHandler         [WEAK] ;  0x12  0x0048  18: RSV00
+                EXPORT RTC_IRQHandler           [WEAK] ;  0x13  0x004C  19: RTC
+                EXPORT RSV01_IRQHandler         [WEAK] ;  0x14  0x0050  20: RSV01
+                EXPORT TMR0_IRQHandler          [WEAK] ;  0x15  0x0054  21: Timer 0
+                EXPORT TMR1_IRQHandler          [WEAK] ;  0x16  0x0058  22: Timer 1
+                EXPORT TMR2_IRQHandler          [WEAK] ;  0x17  0x005C  23: Timer 2
+                EXPORT RSV02_IRQHandler         [WEAK] ;  0x18  0x0060  24: RSV02
+                EXPORT RSV03_IRQHandler         [WEAK] ;  0x19  0x0064  25: RSV03
+                EXPORT RSV04_IRQHandler         [WEAK] ;  0x1A  0x0068  26: RSV04
+                EXPORT RSV05_IRQHandler         [WEAK] ;  0x1B  0x006C  27: RSV05
+                EXPORT RSV06_IRQHandler         [WEAK] ;  0x1C  0x0070  28: RSV06
+                EXPORT I2C0_IRQHandler          [WEAK] ;  0x1D  0x0074  29: I2C0
+                EXPORT UART0_IRQHandler         [WEAK] ;  0x1E  0x0078  30: UART 0
+                EXPORT UART1_IRQHandler         [WEAK] ;  0x1F  0x007C  31: UART 1
+                EXPORT SPI0_IRQHandler          [WEAK] ;  0x20  0x0080  32: SPIY17
+                EXPORT SPI1_IRQHandler          [WEAK] ;  0x21  0x0084  33: SPIMSS
+                EXPORT RSV07_IRQHandler         [WEAK] ;  0x22  0x0088  34: RSV07
+                EXPORT RSV08_IRQHandler         [WEAK] ;  0x23  0x008C  35: RSV08
+                EXPORT RSV09_IRQHandler         [WEAK] ;  0x24  0x0090  36: RSV09
+                EXPORT RSV10_IRQHandler         [WEAK] ;  0x25  0x0094  37: RSV10
+                EXPORT RSV11_IRQHandler         [WEAK] ;  0x26  0x0098  38: RSV11
+                EXPORT FLC_IRQHandler           [WEAK] ;  0x27  0x009C  39: FLC
+                EXPORT GPIO0_IRQHandler         [WEAK] ;  0x28  0x00A0  40: GPIO0
+                EXPORT RSV12_IRQHandler         [WEAK] ;  0x29  0x00A4  41: RSV12
+                EXPORT RSV13_IRQHandler         [WEAK] ;  0x2A  0x00A8  42: RSV13
+                EXPORT RSV14_IRQHandler         [WEAK] ;  0x2B  0x00AC  43: RSV14
+                EXPORT DMA0_IRQHandler          [WEAK] ;  0x2C  0x00B0  44: DMA0
+                EXPORT DMA1_IRQHandler          [WEAK] ;  0x2D  0x00B4  45: DMA1
+                EXPORT DMA2_IRQHandler          [WEAK] ;  0x2E  0x00B8  46: DMA2
+                EXPORT DMA3_IRQHandler          [WEAK] ;  0x2F  0x00BC  47: DMA3
+                EXPORT RSV15_IRQHandler         [WEAK] ;  0x30  0x00C0  48: RSV15
+                EXPORT RSV16_IRQHandler         [WEAK] ;  0x31  0x00C4  49: RSV16
+                EXPORT RSV17_IRQHandler         [WEAK] ;  0x32  0x00C8  50: RSV17
+                EXPORT RSV18_IRQHandler         [WEAK] ;  0x33  0x00CC  51: RSV18
+                EXPORT I2C1_IRQHandler          [WEAK] ;  0x34  0x00D0  52: I2C1
+                EXPORT RSV19_IRQHandler         [WEAK] ;  0x35  0x00D4  53: RSV19
+                EXPORT RSV20_IRQHandler         [WEAK] ;  0x36  0x00D8  54: RSV20
+                EXPORT RSV21_IRQHandler         [WEAK] ;  0x37  0x00DC  55: RSV21
+                EXPORT RSV22_IRQHandler         [WEAK] ;  0x38  0x00E0  56: RSV22
+                EXPORT RSV23_IRQHandler         [WEAK] ;  0x39  0x00E4  57: RSV23
+                EXPORT RSV24_IRQHandler         [WEAK] ;  0x3A  0x00E8  58: RSV24
+                EXPORT RSV25_IRQHandler         [WEAK] ;  0x3B  0x00EC  59: RSV25
+                EXPORT RSV26_IRQHandler         [WEAK] ;  0x3C  0x00F0  60: RSV26
+                EXPORT RSV27_IRQHandler         [WEAK] ;  0x3D  0x00F4  61: RSV27
+                EXPORT RSV28_IRQHandler         [WEAK] ;  0x3E  0x00F8  62: RSV28
+                EXPORT RSV29_IRQHandler         [WEAK] ;  0x3F  0x00FC  63: RSV29
+                EXPORT RSV30_IRQHandler         [WEAK] ;  0x40  0x0100  64: RSV30
+                EXPORT RSV31_IRQHandler         [WEAK] ;  0x41  0x0104  65: RSV31
+                EXPORT RSV32_IRQHandler         [WEAK] ;  0x42  0x0108  66: RSV32
+                EXPORT RSV33_IRQHandler         [WEAK] ;  0x43  0x010C  67: RSV33
+                EXPORT RSV34_IRQHandler         [WEAK] ;  0x44  0x0110  68: RSV34
+                EXPORT RSV35_IRQHandler         [WEAK] ;  0x45  0x0114  69: RSV35
+                EXPORT GPIOWAKE_IRQHandler      [WEAK] ;  0x46  0x0118  70: GPIO Wakeup
+
+;*******************************************************************************
+; Default handler implementations
+;*******************************************************************************
+PF_IRQHandler                                   ;  0x10  0x0040  16: Power Fail
+WDT0_IRQHandler                                 ;  0x11  0x0044  17: Watchdog 0
+RSV00_IRQHandler                                ;  0x12  0x0048  18: RSV00
+RTC_IRQHandler                                  ;  0x13  0x004C  19: RTC
+RSV01_IRQHandler                                ;  0x14  0x0050  20: RSV01
+TMR0_IRQHandler                                 ;  0x15  0x0054  21: Timer 0
+TMR1_IRQHandler                                 ;  0x16  0x0058  22: Timer 1
+TMR2_IRQHandler                                 ;  0x17  0x005C  23: Timer 2
+RSV02_IRQHandler                                ;  0x18  0x0060  24: RSV02
+RSV03_IRQHandler                                ;  0x19  0x0064  25: RSV03
+RSV04_IRQHandler                                ;  0x1A  0x0068  26: RSV04
+RSV05_IRQHandler                                ;  0x1B  0x006C  27: RSV05
+RSV06_IRQHandler                                ;  0x1C  0x0070  28: RSV06
+I2C0_IRQHandler                                 ;  0x1D  0x0074  29: I2C0
+UART0_IRQHandler                                ;  0x1E  0x0078  30: UART 0
+UART1_IRQHandler                                ;  0x1F  0x007C  31: UART 1
+SPI0_IRQHandler                                 ;  0x20  0x0080  32: SPI0
+SPI1_IRQHandler                                 ;  0x21  0x0084  33: SPI1
+RSV07_IRQHandler                                ;  0x22  0x0088  34: RSV07
+RSV08_IRQHandler                                ;  0x23  0x008C  35: RSV08
+RSV09_IRQHandler                                ;  0x24  0x0090  36: RSV09
+RSV10_IRQHandler                                ;  0x25  0x0094  37: RSV10
+RSV11_IRQHandler                                ;  0x26  0x0098  38: RSV11
+FLC_IRQHandler                                  ;  0x27  0x009C  39: FLC
+GPIO0_IRQHandler                                ;  0x28  0x00A0  40: GPIO0
+RSV12_IRQHandler                                ;  0x29  0x00A4  41: RSV12
+RSV13_IRQHandler                                ;  0x2A  0x00A8  42: RSV13
+RSV14_IRQHandler                                ;  0x2B  0x00AC  43: RSV14
+DMA0_IRQHandler                                 ;  0x2C  0x00B0  44: DMA0
+DMA1_IRQHandler                                 ;  0x2D  0x00B4  45: DMA1
+DMA2_IRQHandler                                 ;  0x2E  0x00B8  46: DMA2
+DMA3_IRQHandler                                 ;  0x2F  0x00BC  47: DMA3
+RSV15_IRQHandler                                ;  0x30  0x00C0  48: RSV15
+RSV16_IRQHandler                                ;  0x31  0x00C4  49: RSV16
+RSV17_IRQHandler                                ;  0x32  0x00C8  50: RSV17
+RSV18_IRQHandler                                ;  0x33  0x00CC  51: RSV18
+I2C1_IRQHandler                                 ;  0x34  0x00D0  52: I2C1
+RSV19_IRQHandler                                ;  0x35  0x00D4  53: RSV19
+RSV20_IRQHandler                                ;  0x36  0x00D8  54: RSV20
+RSV21_IRQHandler                                ;  0x37  0x00DC  55: RSV21
+RSV22_IRQHandler                                ;  0x38  0x00E0  56: RSV22
+RSV23_IRQHandler                                ;  0x39  0x00E4  57: RSV23
+RSV24_IRQHandler                                ;  0x3A  0x00E8  58: RSV24
+RSV25_IRQHandler                                ;  0x3B  0x00EC  59: RSV25
+RSV26_IRQHandler                                ;  0x3C  0x00F0  60: RSV26
+RSV27_IRQHandler                                ;  0x3D  0x00F4  61: RSV27
+RSV28_IRQHandler                                ;  0x3E  0x00F8  62: RSV28
+RSV29_IRQHandler                                ;  0x3F  0x00FC  63: RSV29
+RSV30_IRQHandler                                ;  0x40  0x0100  64: RSV30
+RSV31_IRQHandler                                ;  0x41  0x0104  65: RSV31
+RSV32_IRQHandler                                ;  0x42  0x0108  66: RSV32
+RSV33_IRQHandler                                ;  0x43  0x010C  67: RSV33
+RSV34_IRQHandler                                ;  0x44  0x0110  68: RSV34
+RSV35_IRQHandler                                ;  0x45  0x0114  69: RSV35
+GPIOWAKE_IRQHandler                             ;  0x46  0x0118  70: GPIO Wakeup
+
+                B       .
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap\
+                PROC
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, = (Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+                END
+
+;;;;;;;;;;;;;;;;;;;;;;;;;
+;; End of file.
+;;;;;;;;;;;;;;;;;;;;;;;;;

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/gcc.mk

@@ -0,0 +1,391 @@
+################################################################################
+ # Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ #
+ # Permission is hereby granted, free of charge, to any person obtaining a
+ # copy of this software and associated documentation files (the "Software"),
+ # to deal in the Software without restriction, including without limitation
+ # the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ # and/or sell copies of the Software, and to permit persons to whom the
+ # Software is furnished to do so, subject to the following conditions:
+ #
+ # The above copyright notice and this permission notice shall be included
+ # in all copies or substantial portions of the Software.
+ #
+ # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ # IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ # OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ # OTHER DEALINGS IN THE SOFTWARE.
+ #
+ # Except as contained in this notice, the name of Maxim Integrated
+ # Products, Inc. shall not be used except as stated in the Maxim Integrated
+ # Products, Inc. Branding Policy.
+ #
+ # The mere transfer of this software does not imply any licenses
+ # of trade secrets, proprietary technology, copyrights, patents,
+ # trademarks, maskwork rights, or any other form of intellectual
+ # property whatsoever. Maxim Integrated Products, Inc. retains all
+ # ownership rights.
+ #
+ # $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ 
+ # $Revision: 40072 $
+ #
+ ###############################################################################
+
+# The build directory
+ifeq "$(BUILD_DIR)" ""
+BUILD_DIR=$(CURDIR)/build
+endif
+
+# Create output object file names
+SRCS_NOPATH := $(foreach NAME,$(SRCS),$(basename $(notdir $(NAME))).c)
+OBJS_NOPATH := $(SRCS_NOPATH:.c=.o)
+OBJS        := $(OBJS_NOPATH:%.o=$(BUILD_DIR)/%.o)
+
+################################################################################
+# Goals
+
+# The default goal, which causes the example to be built.
+.DEFAULT_GOAL :=
+.PHONY: all
+all: mkbuildir
+all: ${BUILD_DIR}/${PROJECT}.elf
+
+# Goal to build for release without debug
+.PHONY: release
+release: mkbuildir
+release: ${BUILD_DIR}/${PROJECT}.elf
+release: ${BUILD_DIR}/${PROJECT}.srec
+release: ${BUILD_DIR}/${PROJECT}.hex
+release: ${BUILD_DIR}/${PROJECT}.bin
+release: ${BUILD_DIR}/${PROJECT}.dasm
+
+# The goal to build as a library
+.PHONY: lib
+lib: mkbuildir
+lib: ${BUILD_DIR}/${PROJECT}.a
+
+# The goal to create the target directory.
+.PHONY: mkbuildir
+mkbuildir:
+	@mkdir -p ${BUILD_DIR}
+
+# The goal to clean out all the build products.
+.PHONY: clean
+clean:
+	@rm -rf ${BUILD_DIR} ${wildcard *~}
+
+${BUILD_DIR}/${PROJECT}.elf: ${LIBS} ${OBJS} ${LINKERFILE}
+${BUILD_DIR}/${PROJECT}.a: ${OBJS}
+
+# Create a goal to exercise the library build dependencies
+.PHONY: FORCE
+FORCE:
+
+# Include the automatically generated dependency files.
+ifneq (${MAKECMDGOALS},clean)
+-include ${wildcard ${BUILD_DIR}/*.d} __dummy__
+endif
+
+################################################################################
+# Get the operating system name.  If this is Cygwin, the .d files will be
+# munged to convert c: into /cygdrive/c so that "make" will be happy with the
+# auto-generated dependencies. Also if this is Cygwin, file paths for ARM GCC
+# will be converted from /cygdrive/c to C:.
+################################################################################
+ifneq ($(findstring CYGWIN, ${shell uname -s}), )
+CYGWIN=True
+endif
+
+# Get the prefix for the tools to use.
+ifeq "$(TOOL_DIR)" ""
+PREFIX=arm-none-eabi
+else
+PREFIX=$(TOOL_DIR)/arm-none-eabi
+endif
+
+# The command for calling the compiler.
+CC=${PREFIX}-gcc
+CXX=${PREFIX}-g++
+
+# Discover if we are using GCC > 4.8.0
+GCCVERSIONGTEQ4 := $(shell expr `gcc -dumpversion | cut -f1 -d.` \> 4)
+ifeq "$(GCCVERSIONGTEQ4)" "0"
+GCCVERSIONGTEQ4 := $(shell expr `gcc -dumpversion | cut -f1 -d.` \>= 4)
+ifeq "$(GCCVERSIONGTEQ4)" "1"
+GCCVERSIONGTEQ4 := $(shell expr `gcc -dumpversion | cut -f2 -d.` \>= 8)
+endif
+
+endif
+
+# The flags passed to the assembler.
+AFLAGS=-mthumb         \
+       -mcpu=cortex-m4 \
+       -MD
+ifneq "$(HEAP_SIZE)" ""
+AFLAGS+=-D__HEAP_SIZE=$(HEAP_SIZE)
+endif
+ifneq "$(STACK_SIZE)" ""
+AFLAGS+=-D__STACK_SIZE=$(STACK_SIZE)
+endif
+AFLAGS+=$(PROJ_AFLAGS)
+
+ifeq "$(MXC_OPTIMIZE_CFLAGS)" ""
+# Default is optimize for size
+MXC_OPTIMIZE_CFLAGS = -Os   
+endif
+
+# The flags passed to the compiler.
+# fno-isolate-erroneous-paths-dereference disables the check for pointers with the value of 0
+#  add this below when arm-none-eabi-gcc version is past 4.8 -fno-isolate-erroneous-paths-dereference                                \
+
+CFLAGS=-mthumb                                                                 \
+       -mcpu=cortex-m4                                                         \
+       -mfloat-abi=hard                                                        \
+       -mfpu=fpv4-sp-d16                                                       \
+       -Wa,-mimplicit-it=thumb                                                 \
+       $(MXC_OPTIMIZE_CFLAGS)                                                  \
+       -fsingle-precision-constant                                             \
+       -ffunction-sections                                                     \
+       -fdata-sections                                                         \
+       -MD                                                                     \
+       -Wall                                                                   \
+       -Wdouble-promotion													   \
+       -Wno-format                                                             \
+       -c
+
+# The flags passed to the C++ compiler.
+CXXFLAGS= \
+	-mthumb					\
+	-mcpu=cortex-m4				\
+	-mfloat-abi=hard			\
+	-mfpu=fpv4-sp-d16			\
+	-Wa,-mimplicit-it=thumb			\
+	$(MXC_OPTIMIZE_CFLAGS)			\
+	-ffunction-sections			\
+	-fdata-sections				\
+	-MD					\
+	-Wall					\
+	-Wno-format				\
+	-fno-rtti				\
+	-fno-exceptions				\
+	-std=c++11				\
+	-c
+
+# On GCC version > 4.8.0 use the -fno-isolate-erroneous-paths-dereference flag
+ifeq "$(GCCVERSIONGTEQ4)" "1"
+CFLAGS += -fno-isolate-erroneous-paths-dereference
+endif
+
+ifneq "$(TARGET)" ""
+# Turn TARGET into a number for use within source files (e.g. MAX32650 -> 32650)
+CFLAGS+=-DTARGET=$(shell echo $(TARGET) | tr -d '[:alpha:]')
+CXXFLAGS+=-DTARGET=$(shell echo $(TARGET) | tr -d '[:alpha:]')
+endif
+
+ifneq "$(TARGET_REV)" ""
+CFLAGS+=-DTARGET_REV=$(TARGET_REV)
+CXXFLAGS+=-DTARGET_REV=$(TARGET_REV)
+endif
+
+# Exclude debug for 'release' builds
+ifneq (${MAKECMDGOALS},release)
+ifneq (${DEBUG},0)
+CFLAGS+=-g3 -ggdb -DDEBUG
+endif
+endif
+
+CFLAGS+=$(PROJ_CFLAGS)
+CXXFLAGS+=$(PROJ_CFLAGS)
+
+# The command for calling the library archiver.
+AR=${PREFIX}-ar
+
+# The command for calling the linker.
+LD=${PREFIX}-gcc
+
+# The flags passed to the linker.
+LDFLAGS=-mthumb                                                                \
+        -mcpu=cortex-m4                                                        \
+        -mfloat-abi=hard                                                       \
+        -mfpu=fpv4-sp-d16                                                      \
+        -Xlinker --gc-sections                                                 \
+	-Xlinker -Map -Xlinker ${BUILD_DIR}/$(PROJECT).map
+LDFLAGS+=$(PROJ_LDFLAGS)
+
+# Include math library
+STD_LIBS=-lc -lm
+
+# Determine if any C++ files are in the project sources, and add libraries as appropriate
+ifneq "$(findstring cpp, ${SRCS})" ""
+STD_LIBS+=-lsupc++ -lstdc++
+endif
+
+# Finally, resolve any newlib system calls with libnosys
+STD_LIBS+=-lnosys
+
+PROJ_LIBS:=$(addprefix -l, $(PROJ_LIBS))
+
+# The command for extracting images from the linked executables.
+OBJCOPY=${PREFIX}-objcopy
+OBJDUMP=${PREFIX}-objdump
+
+ifeq "$(CYGWIN)" "True"
+fixpath=$(shell echo $(1) | sed -r 's/\/cygdrive\/([A-Na-n])/\U\1:/g' )
+else
+fixpath=$(1)
+endif
+
+# Add the include file paths to AFLAGS and CFLAGS.
+AFLAGS+=${patsubst %,-I%,$(call fixpath,$(IPATH))}
+CFLAGS+=${patsubst %,-I%,$(call fixpath,$(IPATH))}
+CXXFLAGS+=${patsubst %,-I%,$(call fixpath,$(IPATH))}
+LDFLAGS+=${patsubst %,-L%,$(call fixpath,$(LIBPATH))}
+
+################################################################################
+# The rule for building the object file from each C source file.
+${BUILD_DIR}/%.o: %.c
+	@if [ 'x${ECLIPSE}' != x ]; 																			\
+	then 																									\
+		echo ${CC} ${CFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<}) | sed 's/-I\/\(.\)\//-I\1:\//g' ; \
+	elif [ 'x${VERBOSE}' != x ];                                               								\
+	then 																									\
+	    echo ${CC} ${CFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<});     								\
+	else                                                                       								\
+	    echo "  CC    ${<}";                                                   								\
+	fi
+	@${CC} ${CFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<})
+ifeq "$(CYGWIN)" "True"
+	@sed -i -r -e 's/([A-Na-n]):/\/cygdrive\/\L\1/g' -e 's/\\([A-Za-z])/\/\1/g' ${@:.o=.d}
+endif
+
+# The rule to build an object file from a C++ source file
+${BUILD_DIR}/%.o: %.cpp
+	@if [ 'x${ECLIPSE}' != x ]; 																			\
+	then 																									\
+		echo ${CXX} ${CXXFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<}) | sed 's/-I\/\(.\)\//-I\1:\//g' ; \
+	elif [ 'x${VERBOSE}' != x ];                                               								\
+	then 																									\
+	    echo ${CXX} ${CXXFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<});     								\
+	else                                                                       								\
+	    echo "  CXX    ${<}";                                                   								\
+	fi
+	@${CXX} ${CXXFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<})
+ifeq "$(CYGWIN)" "True"
+	@sed -i -r -e 's/([A-Na-n]):/\/cygdrive\/\L\1/g' -e 's/\\([A-Za-z])/\/\1/g' ${@:.o=.d}
+endif
+
+# The rule for building the object file from each assembly source file.
+${BUILD_DIR}/%.o: %.S
+	@if [ 'x${VERBOSE}' = x ];                                                   \
+	 then                                                                        \
+	     echo "  AS    ${<}";                                                    \
+	 else                                                                        \
+	     echo ${CC} ${AFLAGS} -o $(call fixpath,${@}) -c $(call fixpath,${<});   \
+	 fi
+	@${CC} ${AFLAGS} -o $(call fixpath,${@}) -c $(call fixpath,${<})
+ifeq "$(CYGWIN)" "True"
+	@sed -i -r -e 's/([A-Na-n]):/\/cygdrive\/\L\1/g' -e 's/\\([A-Za-z])/\/\1/g' ${@:.o=.d}
+endif
+
+# The rule for creating an object library.
+${BUILD_DIR}/%.a:
+	@if [ 'x${VERBOSE}' = x ];                                                   \
+	 then                                                                        \
+	     echo "  AR    ${@}";                                                    \
+	 else                                                                        \
+	     echo ${AR} -cr $(call fixpath,${@}) $(call fixpath,${^});               \
+	 fi
+	@${AR} -cr $(call fixpath,${@}) $(call fixpath,${^})
+
+# The rule for linking the application.
+${BUILD_DIR}/%.elf:
+	@if [ 'x${VERBOSE}' = x ];                                                   \
+	 then                                                                        \
+	     echo "  LD    ${@} ${LNK_SCP}";                                         \
+	 else                                                                        \
+	     echo ${LD} -T $(call fixpath,${LINKERFILE})                             \
+	          --entry ${ENTRY}                                                   \
+	          $(call fixpath,${LDFLAGS})                                         \
+	          -o $(call fixpath,${@})                                            \
+	          $(call fixpath,$(filter %.o, ${^}))                                \
+	          -Xlinker --start-group                                             \
+	          $(call fixpath,$(filter %.a, ${^}))                                \
+	          ${PROJ_LIBS}                                                       \
+	          ${STD_LIBS}                                                        \
+	          -Xlinker --end-group;                                              \
+	 fi;                                                                         \
+	${LD} -T $(call fixpath,${LINKERFILE})                                       \
+	      --entry ${ENTRY}                                                       \
+	      $(call fixpath,${LDFLAGS})                                             \
+	      -o $(call fixpath,${@})                                                \
+	      $(call fixpath,$(filter %.o, ${^}))                                    \
+	      -Xlinker --start-group                                                 \
+	      $(call fixpath,$(filter %.a, ${^}))                                    \
+	      ${PROJ_LIBS}                                                           \
+	      ${STD_LIBS}                                                            \
+	      -Xlinker --end-group
+
+# Create S-Record output file
+%.srec: %.elf
+	@if [ 'x${VERBOSE}' = x ];                                                   \
+	 then                                                                        \
+	     echo "Creating ${@}";                                                   \
+	 else                                                                        \
+	     echo ${OBJCOPY} -O srec $(call fixpath,${<}) $(call fixpath,${@});      \
+	 fi
+	@$(OBJCOPY) -O srec $< $(call fixpath,${@})
+
+# Create Intex Hex output file
+%.hex: %.elf
+	@if [ 'x${VERBOSE}' = x ];                                                   \
+	 then                                                                        \
+	     echo "Creating ${@}";                                                   \
+	 else                                                                        \
+	     echo ${OBJCOPY} -O ihex $(call fixpath,${<}) $(call fixpath,${@});      \
+	 fi
+	@$(OBJCOPY) -O ihex $< $(call fixpath,${@})
+
+# Create binary output file
+%.bin: %.elf
+	@if [ 'x${VERBOSE}' = x ];                                                   \
+	 then                                                                        \
+	     echo "Creating ${@}";                                                   \
+	 else                                                                        \
+	     echo ${OBJCOPY} -O binary $(call fixpath,${<}) $(call fixpath,${@});    \
+	 fi
+	@$(OBJCOPY) -O binary $< $(call fixpath,${@})
+
+# Create disassembly file
+%.dasm: %.elf
+	@if [ 'x${VERBOSE}' = x ];                                                   \
+	 then                                                                        \
+	     echo "Creating ${@}";                                                   \
+	 else                                                                        \
+	     echo $(OBJDUMP) -S $(call fixpath,${<}) $(call fixpath,${@});        \
+	 fi
+	@$(OBJDUMP) -S $< > $(call fixpath,${@})
+
+################################################################################
+.PHONY: debug
+debug:
+	@echo CYGWIN = ${CYGWIN}
+	@echo
+	@echo BUILD_DIR = ${BUILD_DIR}
+	@echo
+	@echo SRCS = ${SRCS}
+	@echo
+	@echo SRCS_NOPATH = ${SRCS_NOPATH}
+	@echo
+	@echo OBJS_NOPATH = ${OBJS_NOPATH}
+	@echo
+	@echo OBJS = ${OBJS}
+	@echo
+	@echo LIBS = ${LIBS}
+	@echo
+	@echo VPATH = ${VPATH}
+	@echo
+	@echo IPATH = ${IPATH}
+

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660.ld

@@ -0,0 +1,131 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ 
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+MEMORY {
+    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+SECTIONS {
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        *(.text*)    /* program code */
+        *(.rodata*)  /* read-only data: "const" */
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > FLASH
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx*)
+        __exidx_end = .;
+    } > FLASH
+
+    .data :
+    {
+        _data = ALIGN(., 4);
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+        *(.spix_config*)    /* SPIX configuration functions need to be run from SRAM */
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        _edata = ALIGN(., 4);
+    } > SRAM AT>FLASH
+    __load_data = LOADADDR(.data);
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialzed global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM
+
+    .heap (COPY):
+    {
+        . = ALIGN(4);
+        *(.heap*)
+        __HeapLimit = ABSOLUTE(__StackLimit);
+    } > SRAM
+
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660.mk

@@ -0,0 +1,83 @@
+################################################################################
+ # Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ #
+ # Permission is hereby granted, free of charge, to any person obtaining a
+ # copy of this software and associated documentation files (the "Software"),
+ # to deal in the Software without restriction, including without limitation
+ # the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ # and/or sell copies of the Software, and to permit persons to whom the
+ # Software is furnished to do so, subject to the following conditions:
+ #
+ # The above copyright notice and this permission notice shall be included
+ # in all copies or substantial portions of the Software.
+ #
+ # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ # IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ # OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ # OTHER DEALINGS IN THE SOFTWARE.
+ #
+ # Except as contained in this notice, the name of Maxim Integrated
+ # Products, Inc. shall not be used except as stated in the Maxim Integrated
+ # Products, Inc. Branding Policy.
+ #
+ # The mere transfer of this software does not imply any licenses
+ # of trade secrets, proprietary technology, copyrights, patents,
+ # trademarks, maskwork rights, or any other form of intellectual
+ # property whatsoever. Maxim Integrated Products, Inc. retains all
+ # ownership rights.
+ #
+ # $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ 
+ # $Revision: 40072 $
+ #
+ ###############################################################################
+
+ifeq "$(CMSIS_ROOT)" ""
+$(error CMSIS_ROOT must be specified)
+endif
+
+# The build directory
+ifeq "$(BUILD_DIR)" ""
+BUILD_DIR=$(CURDIR)/build
+endif
+
+ifeq "$(STARTUPFILE)" ""
+STARTUPFILE=startup_max32660.S
+endif
+
+ifeq "$(LINKERFILE)" ""
+LINKERFILE=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Source/GCC/max32660.ld
+endif
+
+ifeq "$(ENTRY)" ""
+ENTRY=Reset_Handler
+endif
+
+# Default TARGET_REVISION
+# "A1" in ASCII
+ifeq "$(TARGET_REV)" ""
+TARGET_REV=0x4131
+endif
+
+# Add target specific CMSIS source files
+ifneq (${MAKECMDGOALS},lib)
+SRCS += ${STARTUPFILE}
+SRCS += heap.c
+SRCS += system_max32660.c
+endif
+
+# Add target specific CMSIS source directories
+VPATH+=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Source/GCC
+VPATH+=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Source
+
+# Add target specific CMSIS include directories
+IPATH+=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Include
+IPATH+=$(CMSIS_ROOT)/Include
+
+# Add directory with linker include file
+LIBPATH+=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Source/GCC
+
+# Include the rules and goals for building
+include $(CMSIS_ROOT)/Device/Maxim/MAX32660/Source/GCC/gcc.mk

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_emulator.ld

@@ -0,0 +1,131 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ 
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+MEMORY {
+    FLASH (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000
+}
+
+SECTIONS {
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        *(.text*)    /* program code */
+        *(.rodata*)  /* read-only data: "const" */
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > FLASH
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx*)
+        __exidx_end = .;
+    } > FLASH
+
+    .data :
+    {
+        _data = ALIGN(., 4);
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+        *(.spix_config*)    /* SPIX configuration functions need to be run from SRAM */
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        _edata = ALIGN(., 4);
+    } > SRAM AT>FLASH
+    __load_data = LOADADDR(.data);
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialzed global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM
+
+    .heap (COPY):
+    {
+        . = ALIGN(4);
+        *(.heap*)
+        __HeapLimit = ABSOLUTE(__StackLimit);
+    } > SRAM
+
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_emulator_ram.ld

@@ -0,0 +1,132 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ 
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+MEMORY {
+    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000
+}
+
+SECTIONS {
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        *(.text*)    /* program code */
+        *(.rodata*)  /* read-only data: "const" */
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > SRAM
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx*)
+        __exidx_end = .;
+    } > SRAM
+
+    .data :
+    {
+        _data = ALIGN(., 4);
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+        *(.spix_config*)    /* SPIX configuration functions need to be run from SRAM */
+        *(.flashprog*)      /* Flash program */
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        _edata = ALIGN(., 4);
+    } > SRAM AT>SRAM
+    __load_data = LOADADDR(.data);
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialzed global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM
+
+    .heap (COPY):
+    {
+        . = ALIGN(4);
+        *(.heap*)
+        __HeapLimit = ABSOLUTE(__StackLimit);
+    } > SRAM
+
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_ram.ld

@@ -0,0 +1,132 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ 
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+MEMORY {
+    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000
+}
+
+SECTIONS {
+    .text :
+    {
+        _text = .;
+        KEEP(*(.isr_vector))
+        *(.text*)    /* program code */
+        *(.rodata*)  /* read-only data: "const" */
+        *(.flashprog*)  /* Flash program */
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > SRAM
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx*)
+        __exidx_end = .;
+    } > SRAM
+
+    .data :
+    {
+        _data = ALIGN(., 4);
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+        *(.spix_config*)    /* SPIX configuration functions need to be run from SRAM */
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        _edata = ALIGN(., 4);
+    } > SRAM AT>SRAM
+    __load_data = LOADADDR(.data);
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialzed global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM
+
+    .heap (COPY):
+    {
+        . = ALIGN(4);
+        *(.heap*)
+        __HeapLimit = ABSOLUTE(__StackLimit);
+    } > SRAM
+
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_sbl.ld

@@ -0,0 +1,271 @@
+/*******************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ 
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+MEMORY {
+    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* 256kB "FLASH" */
+	SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000
+}
+
+OUTPUT_FORMAT ("elf32-littlearm")
+ENTRY(Reset_Handler)
+EXTERN(__start_c main __stack __section_end_heap)
+
+SECTIONS {
+
+    /* SRAM start/stop addresses used during startup (PreInit(), preinit.S) to initialize ECCEN register
+     * and initial Error correcting state. (SEC-DED) */
+    __sram_ecc_initialize_start = ORIGIN(SRAM);
+    __sram_ecc_initialize_stop = (ORIGIN(SRAM) + LENGTH(SRAM));
+
+    .text : ALIGN(0x100)
+    {
+        _text = .;
+		__section_load_nvic = .;
+		KEEP(*(.isr_vector))
+		__section_load_nvic_end = .;
+        
+        KEEP(*startup*(.text))
+        *(.text*) /* program code */
+        *(.flashprog*) /* Flash program */
+        KEEP(*(.init))
+        KEEP(*(.fini))
+        *(.rodata*)  /* read-only data: "const" */
+		KEEP(*(.iota_rom_params))
+
+        /* C++ Exception handling */
+        KEEP(*(.eh_frame*))
+        _etext = .;
+    } > FLASH
+
+  __section_nvic_size = __section_load_nvic_end - __section_load_nvic;
+  __section_nvic_start = ORIGIN(SRAM);
+  __section_nvic_end = __section_nvic_start + __section_nvic_size;
+
+    /* it's used for C++ exception handling      */
+    /* we need to keep this to avoid overlapping */
+    .ARM.exidx :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx*)
+        __exidx_end = .;
+    } > FLASH
+
+    .data __section_nvic_end : ALIGN(0x10)
+    {
+        _data = ALIGN(., 4);
+        *(.data*)           /*read-write initialized data: initialized global variable*/
+        *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */
+
+        /* These array sections are used by __libc_init_array to call static C++ constructors */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        _edata = ALIGN(., 4);
+        __section_end_data = .;
+
+    } > SRAM AT>FLASH
+    __load_data = LOADADDR(.data);
+
+	/** Info block/OTP reserved area */
+  	__virtual_otp_size = 0x400;
+  	__virtual_end_otp = ORIGIN(FLASH) + LENGTH(FLASH);
+  	__virtual_start_otp = __virtual_end_otp - __virtual_otp_size;
+
+
+	/** Free area to program application */
+  	__virtual_start_iota = ALIGN(__load_data,0x10);
+  	__virtual_end_iota = __virtual_start_otp;
+  	__virtual_iota_size = __virtual_end_iota - __virtual_start_iota;
+
+  /** Work buffer */
+  .iota_work __virtual_start_iota :
+  {
+  	. += __virtual_iota_size;
+  }
+
+  /** OTP area */
+  .iota_otp __virtual_start_otp :
+  {
+  	. += __virtual_otp_size;
+  }
+
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _bss = .;
+        *(.bss*)     /*read-write zero initialized data: uninitialzed global variable*/
+        *(COMMON)
+        _ebss = ALIGN(., 4);
+    } > SRAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+
+	/* Stack and Heap */
+  	.heap (NOLOAD) : ALIGN(0x80)
+  	{
+	    __section_start_heap = .;
+		*(.heap*)
+    	__section_end_heap = .;
+
+  	} > SRAM
+
+  	__section_start_heap_va = __section_start_heap;
+  	__section_end_heap_va = __section_start_heap_va + SIZEOF(.heap);
+
+  	.stack __section_end_heap : ALIGN(0x80)
+  	{
+	  	__section_start_stack = .;
+	    *(.stack*)
+	    _stack = .;
+	    __section_end_stack = .;
+
+  	} > SRAM
+  	__stack_va = __stack;
+
+    PROVIDE(__stack = _stack);
+
+ /* ======================================================================== */
+  /** RAM for STP and SCP **/
+  __section_protocol_ram_end = (ORIGIN(SRAM) + LENGTH(SRAM));
+  __region_end_ram = (ORIGIN(SRAM) + LENGTH(SRAM));
+
+  /** Cryptography work buffer */
+  .iota_work.sh __section_end_stack : ALIGN(0x10)
+  {
+  	KEEP(*(.iota_work.sh))
+  } >SRAM=0
+
+  __iota_work_sh_start = LOADADDR(.iota_work.sh);
+  __iota_work_sh_end = LOADADDR(.iota_work.sh) + SIZEOF(.iota_work.sh);
+  __iota_work_sh_size = SIZEOF(.iota_work.sh);
+
+  /** Configuration Management work buffer */
+  .iota_work.cm __iota_work_sh_end : ALIGN(0x10)
+  {
+  	KEEP(*(.iota_work.cm))
+  } >SRAM=0
+
+  __iota_work_cm_start = LOADADDR(.iota_work.cm);
+  __iota_work_cm_end = LOADADDR(.iota_work.cm) + SIZEOF(.iota_work.cm);
+  __iota_work_cm_size = SIZEOF(.iota_work.cm);
+
+  /** RCE Signature check work buffer */
+  .iota_work.rce __iota_work_cm_end : ALIGN(0x10)
+  {
+	KEEP(*(.iota_work.rce))
+
+  } >SRAM=0
+
+	__iota_work_rce_start = LOADADDR(.iota_work.rce);
+	__iota_work_rce_end = LOADADDR(.iota_work.rce) + SIZEOF(.iota_work.rce);
+	__iota_work_rce_size = SIZEOF(.iota_work.rce);
+
+  /* ======================================================================== */
+
+  /** STP Application, SCP Applet memory areas */
+  .protocol_ram.stack __iota_work_rce_end : ALIGN(0x10)
+  {
+    __section_protocol_start = .;
+  	/** Stack dedicated to STP/SCP application matter if needed */
+   	__section_start_stp_stack = .;
+   	KEEP(*(.protocol_ram.stack))
+	/* . += __stack_size_stp;*/
+	__stack_stp = .;
+
+  } >SRAM
+	__section_end_stp_stack = .;
+
+  .protocol_ram.bss __section_end_stp_stack : ALIGN(0x10)
+  {
+    *stp_*(.bss .bss.* .gnu.linkonce.b.*)
+
+  } >SRAM
+
+  __section_start_bss_stp = LOADADDR(.protocol_ram.bss);
+  __section_end_bss_stp = LOADADDR(.protocol_ram.bss) + SIZEOF(.protocol_ram.bss);
+  __section_bss_stp_size = SIZEOF(.protocol_ram.bss);
+
+  .protocol_ram __section_end_bss_stp : ALIGN(0x10)
+  {
+	/** Code part */
+    KEEP(*stp_*(.data .data.* .gnu.linkonce.d.*))
+    KEEP(*(.protocol_ram))
+
+  } >SRAM
+  __section_protocol_end = ALIGN(0x10);
+  __scp_applet_area_size = __section_protocol_ram_end - __section_protocol_end;
+
+  /** Lasting free internal SRAM space */
+  .iota_scp_applet __section_protocol_end : ALIGN(0x10)
+  {
+    __scp_applet_start = .;
+    . += __scp_applet_area_size;
+    __scp_applet_end = .;
+
+  } >SRAM
+
+  __section_scp_start = LOADADDR(.protocol_ram);
+  __section_scp_stop = LOADADDR(.iota_scp_applet) + SIZEOF(.iota_scp_applet);
+
+  __section_bss_size_stp = __section_end_bss_stp - __section_start_bss_stp;
+  __section_stp_size = SIZEOF(.protocol_ram.stack) + SIZEOF(.protocol_ram.bss) + SIZEOF(.protocol_ram);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
+}

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S

@@ -0,0 +1,314 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ 
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+    .syntax unified
+    .arch armv7-m
+
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0x00001000
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x00000C00
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .if    Heap_Size
+    .space    Heap_Size
+    .endif
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+
+
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    MemManage_Handler     /* MPU Fault Handler */
+    .long    BusFault_Handler      /* Bus Fault Handler */
+    .long    UsageFault_Handler    /* Usage Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    DebugMon_Handler      /* Debug Monitor Handler */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+    /* Device-specific Interrupts */
+    .long PF_IRQHandler             /* 0x10  0x0040  16: Power Fail */
+    .long WDT0_IRQHandler           /* 0x11  0x0044  17: Watchdog 0 */
+    .long RSV00_IRQHandler          /* 0x12  0x0048  18: RSV00 */
+    .long RTC_IRQHandler            /* 0x13  0x004C  19: RTC */
+    .long RSV1_IRQHandler           /* 0x14  0x0050  20: RSV1 */
+    .long TMR0_IRQHandler           /* 0x15  0x0054  21: Timer 0 */
+    .long TMR1_IRQHandler           /* 0x16  0x0058  22: Timer 1 */
+    .long TMR2_IRQHandler           /* 0x17  0x005C  23: Timer 2 */
+    .long RSV02_IRQHandler          /* 0x18  0x0060  24: RSV02 */
+    .long RSV03_IRQHandler          /* 0x19  0x0064  25: RSV03 */
+    .long RSV04_IRQHandler          /* 0x1A  0x0068  26: RSV04 */
+    .long RSV05_IRQHandler          /* 0x1B  0x006C  27: RSV05 */
+    .long RSV06_IRQHandler          /* 0x1C  0x0070  28: RSV06 */
+    .long I2C0_IRQHandler           /* 0x1D  0x0074  29: I2C0 */
+    .long UART0_IRQHandler          /* 0x1E  0x0078  30: UART 0 */
+    .long UART1_IRQHandler          /* 0x1F  0x007C  31: UART 1 */
+    .long SPI0_IRQHandler           /* 0x20  0x0080  32: SPIY17 */
+    .long SPI1_IRQHandler           /* 0x21  0x0084  33: SPIMSS */
+    .long RSV07_IRQHandler          /* 0x22  0x0088  34: RSV07 */
+    .long RSV08_IRQHandler          /* 0x23  0x008C  35: RSV08 */
+    .long RSV09_IRQHandler          /* 0x24  0x0090  36: RSV09 */
+    .long RSV10_IRQHandler          /* 0x25  0x0094  37: RSV10 */
+    .long RSV11_IRQHandler          /* 0x26  0x0098  38: RSV11 */
+    .long FLC_IRQHandler            /* 0x27  0x009C  39: FLC */
+    .long GPIO0_IRQHandler          /* 0x28  0x00A0  40: GPIO0 */
+    .long RSV12_IRQHandler          /* 0x29  0x00A4  41: RSV12 */
+    .long RSV13_IRQHandler          /* 0x2A  0x00A8  42: RSV13 */
+    .long RSV14_IRQHandler          /* 0x2B  0x00AC  43: RSV14 */
+    .long DMA0_IRQHandler           /* 0x2C  0x00B0  44: DMA0 */
+    .long DMA1_IRQHandler           /* 0x2D  0x00B4  45: DMA1 */
+    .long DMA2_IRQHandler           /* 0x2E  0x00B8  46: DMA2 */
+    .long DMA3_IRQHandler           /* 0x2F  0x00BC  47: DMA3 */
+    .long RSV15_IRQHandler          /* 0x30  0x00C0  48: RSV15 */
+    .long RSV16_IRQHandler          /* 0x31  0x00C4  49: RSV16 */
+    .long RSV17_IRQHandler          /* 0x32  0x00C8  50: RSV17 */
+    .long RSV18_IRQHandler          /* 0x33  0x00CC  51: RSV18 */
+    .long I2C1_IRQHandler           /* 0x34  0x00D0  52: I2C1 */
+    .long RSV19_IRQHandler          /* 0x35  0x00D4  53: RSV19 */
+    .long RSV20_IRQHandler          /* 0x36  0x00D8  54: RSV20 */
+    .long RSV21_IRQHandler          /* 0x37  0x00DC  55: RSV21 */
+    .long RSV22_IRQHandler          /* 0x38  0x00E0  56: RSV22 */
+    .long RSV23_IRQHandler          /* 0x39  0x00E4  57: RSV23 */
+    .long RSV24_IRQHandler          /* 0x3A  0x00E8  58: RSV24 */
+    .long RSV25_IRQHandler          /* 0x3B  0x00EC  59: RSV25 */
+    .long RSV26_IRQHandler          /* 0x3C  0x00F0  60: RSV26 */
+    .long RSV27_IRQHandler          /* 0x3D  0x00F4  61: RSV27 */
+    .long RSV28_IRQHandler          /* 0x3E  0x00F8  62: RSV28 */
+    .long RSV29_IRQHandler          /* 0x3F  0x00FC  63: RSV29 */
+    .long RSV30_IRQHandler          /* 0x40  0x0100  64: RSV30 */
+    .long RSV31_IRQHandler          /* 0x41  0x0104  65: RSV31 */
+    .long RSV32_IRQHandler          /* 0x42  0x0108  66: RSV32 */
+    .long RSV33_IRQHandler          /* 0x43  0x010C  67: RSV33 */
+    .long RSV34_IRQHandler          /* 0x44  0x0110  68: RSV34 */
+    .long RSV35_IRQHandler          /* 0x45  0x0114  69: RSV35 */
+    .long GPIOWAKE_IRQHandler       /* 0x46  0x0118  70: GPIO Wakeup */
+    .text 	
+    .thumb
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    ldr r0, =__StackTop
+    mov sp, r0
+
+    /* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */
+    ldr     r0, =PreInit
+    blx     r0
+    cbnz    r0, .SKIPRAMINIT
+
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __load_data: Where data sections are saved.
+ *      _data /_edata: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__load_data
+    ldr    r2, =_data
+    ldr    r3, =_edata
+
+#if 0
+/* Here are two copies of loop implemenations. First one favors code size
+ * and the second one favors performance. Default uses the first one.
+ * Change to "#if 0" to use the second one */
+.LC0:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .LC0
+#else
+    subs    r3, r2
+    ble    .LC1
+.LC0:
+    subs    r3, #4
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    bgt    .LC0
+.LC1:
+#endif
+
+/*
+ *     Loop to zero out BSS section, which uses following symbols
+ *     in linker script:
+ *      _bss  : start of BSS section. Must align to 4
+ *      _ebss : end of BSS section. Must align to 4
+ */
+    ldr r1, =_bss
+    ldr r2, =_ebss
+
+    movs    r0, 0
+.LC2:
+    cmp     r1, r2
+    itt    lt
+    strlt   r0, [r1], #4
+    blt    .LC2
+
+.SKIPRAMINIT:
+
+    /* Perform system initialization after RAM initialization */
+    ldr     r0, =SystemInit
+    blx     r0
+
+    /* This must be called to walk the constructor array for static C++ objects */
+    /* Note: The linker file must have .data symbols for __X_array_start and __X_array_end */
+    /*        where X is {preinit, init, fini}                                             */
+    ldr     r0, =__libc_init_array
+    blx     r0  
+
+    /* Transfer control to users main program */
+    ldr     r0, =main
+    blx     r0 
+
+.SPIN:
+    /* spin if main ever returns. */
+    bl .SPIN
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_irq_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    /* SysTick_Handler is defined in mxc_delay.c */
+    def_irq_handler    Default_Handler
+
+    /* Device-specific Interrupts */
+    def_irq_handler PF_IRQHandler             /* 0x10  0x0040  16: Power Fail */
+    def_irq_handler WDT0_IRQHandler           /* 0x11  0x0044  17: Watchdog 0 */
+    def_irq_handler RSV00_IRQHandler          /* 0x12  0x0048  18: RSV00 */
+    def_irq_handler RTC_IRQHandler            /* 0x13  0x004C  19: RTC */
+    def_irq_handler RSV1_IRQHandler           /* 0x14  0x0050  20: RSV1 */
+    def_irq_handler TMR0_IRQHandler           /* 0x15  0x0054  21: Timer 0 */
+    def_irq_handler TMR1_IRQHandler           /* 0x16  0x0058  22: Timer 1 */
+    def_irq_handler TMR2_IRQHandler           /* 0x17  0x005C  23: Timer 2 */
+    def_irq_handler RSV02_IRQHandler          /* 0x18  0x0060  24: RSV02 */
+    def_irq_handler RSV03_IRQHandler          /* 0x19  0x0064  25: RSV03 */
+    def_irq_handler RSV04_IRQHandler          /* 0x1A  0x0068  26: RSV04 */
+    def_irq_handler RSV05_IRQHandler          /* 0x1B  0x006C  27: RSV05 */
+    def_irq_handler RSV06_IRQHandler          /* 0x1C  0x0070  28: RSV06 */
+    def_irq_handler I2C0_IRQHandler           /* 0x1D  0x0074  29: I2C0 */
+    def_irq_handler UART0_IRQHandler          /* 0x1E  0x0078  30: UART 0 */
+    def_irq_handler UART1_IRQHandler          /* 0x1F  0x007C  31: UART 1 */
+    def_irq_handler SPI0_IRQHandler           /* 0x20  0x0080  32: SPIY17 */
+    def_irq_handler SPI1_IRQHandler           /* 0x21  0x0084  33: SPIMSS */
+    def_irq_handler RSV07_IRQHandler          /* 0x22  0x0088  34: RSV07 */
+    def_irq_handler RSV08_IRQHandler          /* 0x23  0x008C  35: RSV08 */
+    def_irq_handler RSV09_IRQHandler          /* 0x24  0x0090  36: RSV09 */
+    def_irq_handler RSV10_IRQHandler          /* 0x25  0x0094  37: RSV10 */
+    def_irq_handler RSV11_IRQHandler          /* 0x26  0x0098  38: RSV11 */
+    def_irq_handler FLC_IRQHandler            /* 0x27  0x009C  39: FLC */
+    def_irq_handler GPIO0_IRQHandler          /* 0x28  0x00A0  40: GPIO0 */
+    def_irq_handler RSV12_IRQHandler          /* 0x29  0x00A4  41: RSV12 */
+    def_irq_handler RSV13_IRQHandler          /* 0x2A  0x00A8  42: RSV13 */
+    def_irq_handler RSV14_IRQHandler          /* 0x2B  0x00AC  43: RSV14 */
+    def_irq_handler DMA0_IRQHandler           /* 0x2C  0x00B0  44: DMA0 */
+    def_irq_handler DMA1_IRQHandler           /* 0x2D  0x00B4  45: DMA1 */
+    def_irq_handler DMA2_IRQHandler           /* 0x2E  0x00B8  46: DMA2 */
+    def_irq_handler DMA3_IRQHandler           /* 0x2F  0x00BC  47: DMA3 */
+    def_irq_handler RSV15_IRQHandler          /* 0x30  0x00C0  48: RSV15 */
+    def_irq_handler RSV16_IRQHandler          /* 0x31  0x00C4  49: RSV16 */
+    def_irq_handler RSV17_IRQHandler          /* 0x32  0x00C8  50: RSV17 */
+    def_irq_handler RSV18_IRQHandler          /* 0x33  0x00CC  51: RSV18 */
+    def_irq_handler I2C1_IRQHandler           /* 0x34  0x00D0  52: I2C1 */
+    def_irq_handler RSV19_IRQHandler          /* 0x35  0x00D4  53: RSV19 */
+    def_irq_handler RSV20_IRQHandler          /* 0x36  0x00D8  54: RSV20 */
+    def_irq_handler RSV21_IRQHandler          /* 0x37  0x00DC  55: RSV21 */
+    def_irq_handler RSV22_IRQHandler          /* 0x38  0x00E0  56: RSV22 */
+    def_irq_handler RSV23_IRQHandler          /* 0x39  0x00E4  57: RSV23 */
+    def_irq_handler RSV24_IRQHandler          /* 0x3A  0x00E8  58: RSV24 */
+    def_irq_handler RSV25_IRQHandler          /* 0x3B  0x00EC  59: RSV25 */
+    def_irq_handler RSV26_IRQHandler          /* 0x3C  0x00F0  60: RSV26 */
+    def_irq_handler RSV27_IRQHandler          /* 0x3D  0x00F4  61: RSV27 */
+    def_irq_handler RSV28_IRQHandler          /* 0x3E  0x00F8  62: RSV28 */
+    def_irq_handler RSV29_IRQHandler          /* 0x3F  0x00FC  63: RSV29 */
+    def_irq_handler RSV30_IRQHandler          /* 0x40  0x0100  64: RSV30 */
+    def_irq_handler RSV31_IRQHandler          /* 0x41  0x0104  65: RSV31 */
+    def_irq_handler RSV32_IRQHandler          /* 0x42  0x0108  66: RSV32 */
+    def_irq_handler RSV33_IRQHandler          /* 0x43  0x010C  67: RSV33 */
+    def_irq_handler RSV34_IRQHandler          /* 0x44  0x0110  68: RSV34 */
+    def_irq_handler RSV35_IRQHandler          /* 0x45  0x0114  69: RSV35 */
+    def_irq_handler GPIOWAKE_IRQHandler       /* 0x46  0x0118  70: GPIO Wakeup */
+
+    .end

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/cmain.s

@@ -0,0 +1,79 @@
+/**************************************************
+ *
+ * Part two of the system initialization code, contains C-level
+ * initialization, thumb-2 only variant.
+ *
+ * Copyright 2006 IAR Systems. All rights reserved.
+ *
+ * $Revision: 36818 $
+ *
+ **************************************************/
+
+
+; --------------------------------------------------
+; Module ?cmain, C-level initialization.
+;
+
+
+        SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2)
+        SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2)
+
+        SECTION .text:CODE:NOROOT(2)
+
+        PUBLIC  __cmain
+        ;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world...
+        PUBLIC  ?main
+        EXTWEAK __iar_data_init3
+        EXTWEAK __iar_argc_argv
+        EXTERN  __low_level_init
+        EXTERN  __call_ctors
+        EXTERN  SystemInit
+        EXTERN  main
+        EXTERN  exit
+
+        THUMB
+__cmain:
+?main:
+
+; Initialize segments.
+; __segment_init and __low_level_init are assumed to use the same
+; instruction set and to be reachable by BL from the ICODE segment
+; (it is safest to link them in segment ICODE).
+
+        FUNCALL __cmain, __low_level_init
+        bl      __low_level_init
+        cmp     r0,#0
+        beq     ?l1
+
+        FUNCALL __cmain, __iar_data_init3
+        bl      __iar_data_init3
+
+?l1:
+        REQUIRE ?l3
+
+        SECTION .text:CODE:NOROOT(2)
+
+        PUBLIC  _main
+        PUBLIC  _call_main
+        THUMB
+
+__iar_init$$done:                       ; Copy initialization is done
+
+?l3:
+_call_main:
+; Static Initialization is complete. Call the SystemInit function to
+; set up the device and system.
+        FUNCALL __cmain, SystemInit
+        BL      SystemInit
+        MOVS    r0,#0                   ;  No parameters
+
+        FUNCALL __cmain, __iar_argc_argv
+        BL      __iar_argc_argv         ; Maybe setup command line
+
+        FUNCALL __cmain, main
+        BL      main
+_main:
+        FUNCALL __cmain, exit
+        BL      exit
+
+        END

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/low_level_init.c

@@ -0,0 +1,50 @@
+/* *************************************************
+ *
+ * This module contains the function `__low_level_init', a function
+ * that is called before the `main' function of the program.  Normally
+ * low-level initializations - such as setting the prefered interrupt
+ * level or setting the watchdog - can be performed here.
+ *
+ * Note that this function is called before the data segments are
+ * initialized, this means that this function cannot rely on the
+ * values of global or static variables.
+ *
+ * When this function returns zero, the startup code will inhibit the
+ * initialization of the data segments. The result is faster startup,
+ * the drawback is that neither global nor static data will be
+ * initialized.
+ *
+ * Copyright 1999-2004 IAR Systems. All rights reserved.
+ *
+ * $Revision: 36818 $
+ *
+ ************************************************* */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int PreInit(void);
+
+#pragma language=extended
+
+__interwork int __low_level_init(void);
+
+__interwork int __low_level_init(void)
+{
+    /*====================================*/
+    /*  Initialize hardware.              */
+    /*  AND                               */
+    /* Choose if segment initialization   */
+    /* should be done or not.             */
+    /* Return: 0 to omit seg_init         */
+    /*         1 to run seg_init          */
+    /*====================================*/
+    return !PreInit(); // See system_max32660.c
+}
+
+#pragma language=default
+
+#ifdef __cplusplus
+}
+#endif

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/IAR/startup_max32660.s

@@ -0,0 +1,480 @@
+;*******************************************************************************
+;* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+;*
+;* Permission is hereby granted, free of charge, to any person obtaining a
+;* copy of this software and associated documentation files (the "Software"),
+;* to deal in the Software without restriction, including without limitation
+;* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+;* and/or sell copies of the Software, and to permit persons to whom the
+;* Software is furnished to do so, subject to the following conditions:
+;*
+;* The above copyright notice and this permission notice shall be included
+;* in all copies or substantial portions of the Software.
+;*
+;* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+;* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+;* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+;* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+;* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+;* OTHER DEALINGS IN THE SOFTWARE.
+;*
+;* Except as contained in this notice, the name of Maxim Integrated
+;* Products, Inc. shall not be used except as stated in the Maxim Integrated
+;* Products, Inc. Branding Policy.
+;*
+;* The mere transfer of this software does not imply any licenses
+;* of trade secrets, proprietary technology, copyrights, patents,
+;* trademarks, maskwork rights, or any other form of intellectual
+;* property whatsoever. Maxim Integrated Products, Inc. retains all
+;* ownership rights.
+;*
+;* Description        : MAX32660 device vector table for IAR EWARM toolchain.
+;*                      - Sets the initial SP
+;*                      - Sets the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address, all set as PUBWEAK. User may override any ISR
+;*                        defined as PUBWEAK.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+    MODULE  ?cstartup
+
+    ;; Forward declaration of sections.
+    SECTION CSTACK:DATA:NOROOT(3)
+
+    SECTION .intvec:CODE:NOROOT(2)
+
+    EXTERN  __iar_program_start
+    ; EXTERN  SystemInit
+    PUBLIC  __vector_table
+    PUBLIC  __isr_vector
+    PUBLIC  __vector_table_modify
+    PUBLIC  __Vectors
+    PUBLIC  __Vectors_End
+    PUBLIC  __Vectors_Size
+
+    DATA
+__vector_table
+__isr_vector
+    DCD     sfe(CSTACK)
+    DCD     Reset_Handler               ; Reset Handler
+
+    DCD     NMI_Handler                 ; NMI Handler
+    DCD     HardFault_Handler           ; Hard Fault Handler
+    DCD     MemManage_Handler           ; MPU Fault Handler
+    DCD     BusFault_Handler            ; Bus Fault Handler
+    DCD     UsageFault_Handler          ; Usage Fault Handler
+__vector_table_modify
+    DCD     0                           ; Reserved
+    DCD     0                           ; Reserved
+    DCD     0                           ; Reserved
+    DCD     0                           ; Reserved
+    DCD     SVC_Handler                 ; SVCall Handler
+    DCD     DebugMon_Handler            ; Debug Monitor Handler
+    DCD     0                           ; Reserved
+    DCD     PendSV_Handler              ; PendSV Handler
+    DCD     SysTick_Handler             ; SysTick Handler
+
+    ; MAX32660 Device-specific Interrupts
+    DCD     PF_IRQHandler               ; /* 0x10  0x0040  16: Power Fail */
+    DCD     WDT0_IRQHandler             ; /* 0x11  0x0044  17: Watchdog 0 */
+    DCD     RSV00_IRQHandler            ; /* 0x12  0x0048  18: RSV00 */
+    DCD     RTC_IRQHandler              ; /* 0x13  0x004C  19: RTC */
+    DCD     RSV1_IRQHandler             ; /* 0x14  0x0050  20: RSV1 */
+    DCD     TMR0_IRQHandler             ; /* 0x15  0x0054  21: Timer 0 */
+    DCD     TMR1_IRQHandler             ; /* 0x16  0x0058  22: Timer 1 */
+    DCD     TMR2_IRQHandler             ; /* 0x17  0x005C  23: Timer 2 */
+    DCD     RSV02_IRQHandler            ; /* 0x18  0x0060  24: RSV02 */
+    DCD     RSV03_IRQHandler            ; /* 0x19  0x0064  25: RSV03 */
+    DCD     RSV04_IRQHandler            ; /* 0x1A  0x0068  26: RSV04 */
+    DCD     RSV05_IRQHandler            ; /* 0x1B  0x006C  27: RSV05 */
+    DCD     RSV06_IRQHandler            ; /* 0x1C  0x0070  28: RSV06 */
+    DCD     I2C0_IRQHandler             ; /* 0x1D  0x0074  29: I2C0 */
+    DCD     UART0_IRQHandler            ; /* 0x1E  0x0078  30: UART 0 */
+    DCD     UART1_IRQHandler            ; /* 0x1F  0x007C  31: UART 1 */
+    DCD     SPI0_IRQHandler             ; /* 0x20  0x0080  32: SPI0 */
+    DCD     SPI1_IRQHandler             ; /* 0x21  0x0084  33: SPI1 */
+    DCD     RSV07_IRQHandler            ; /* 0x22  0x0088  34: RSV07 */
+    DCD     RSV08_IRQHandler            ; /* 0x23  0x008C  35: RSV08 */
+    DCD     RSV09_IRQHandler            ; /* 0x24  0x0090  36: RSV09 */
+    DCD     RSV10_IRQHandler            ; /* 0x25  0x0094  37: RSV10 */
+    DCD     RSV11_IRQHandler            ; /* 0x26  0x0098  38: RSV11 */
+    DCD     FLC_IRQHandler              ; /* 0x27  0x009C  39: FLC */
+    DCD     GPIO0_IRQHandler            ; /* 0x28  0x00A0  40: GPIO0 */
+    DCD     RSV12_IRQHandler            ; /* 0x29  0x00A4  41: RSV12 */
+    DCD     RSV13_IRQHandler            ; /* 0x2A  0x00A8  42: RSV13 */
+    DCD     RSV14_IRQHandler            ; /* 0x2B  0x00AC  43: RSV14 */
+    DCD     DMA0_IRQHandler             ; /* 0x2C  0x00B0  44: DMA0 */
+    DCD     DMA1_IRQHandler             ; /* 0x2D  0x00B4  45: DMA1 */
+    DCD     DMA2_IRQHandler             ; /* 0x2E  0x00B8  46: DMA2 */
+    DCD     DMA3_IRQHandler             ; /* 0x2F  0x00BC  47: DMA3 */
+    DCD     RSV15_IRQHandler            ; /* 0x30  0x00C0  48: RSV15 */
+    DCD     RSV16_IRQHandler            ; /* 0x31  0x00C4  49: RSV16 */
+    DCD     RSV17_IRQHandler            ; /* 0x32  0x00C8  50: RSV17 */
+    DCD     RSV18_IRQHandler            ; /* 0x33  0x00CC  51: RSV18 */
+    DCD     I2C1_IRQHandler             ; /* 0x34  0x00D0  52: I2C1 */
+    DCD     RSV19_IRQHandler            ; /* 0x35  0x00D4  53: RSV19 */
+    DCD     RSV20_IRQHandler            ; /* 0x36  0x00D8  54: RSV20 */
+    DCD     RSV21_IRQHandler            ; /* 0x37  0x00DC  55: RSV21 */
+    DCD     RSV22_IRQHandler            ; /* 0x38  0x00E0  56: RSV22 */
+    DCD     RSV23_IRQHandler            ; /* 0x39  0x00E4  57: RSV23 */
+    DCD     RSV24_IRQHandler            ; /* 0x3A  0x00E8  58: RSV24 */
+    DCD     RSV25_IRQHandler            ; /* 0x3B  0x00EC  59: RSV25 */
+    DCD     RSV26_IRQHandler            ; /* 0x3C  0x00F0  60: RSV26 */
+    DCD     RSV27_IRQHandler            ; /* 0x3D  0x00F4  61: RSV27 */
+    DCD     RSV28_IRQHandler            ; /* 0x3E  0x00F8  62: RSV28 */
+    DCD     RSV29_IRQHandler            ; /* 0x3F  0x00FC  63: RSV29 */
+    DCD     RSV30_IRQHandler            ; /* 0x40  0x0100  64: RSV30 */
+    DCD     RSV31_IRQHandler            ; /* 0x41  0x0104  65: RSV31 */
+    DCD     RSV32_IRQHandler            ; /* 0x42  0x0108  66: RSV32 */
+    DCD     RSV33_IRQHandler            ; /* 0x43  0x010C  67: RSV33 */
+    DCD     RSV34_IRQHandler            ; /* 0x44  0x0110  68: RSV34 */
+    DCD     RSV35_IRQHandler            ; /* 0x45  0x0114  69: RSV35 */
+    DCD     GPIOWAKE_IRQHandler         ; /* 0x46  0x0118  70: GPIO Wakeup */
+    ; Continue this pattern when vectors are eventually assigned by hardware
+
+__Vectors_End
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+
+
+    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+    THUMB
+    PUBWEAK Reset_Handler
+    SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        ; IAR: PreInit is called from low_level_init.c
+        ; IAR: SystemInit is called from cmain.s
+        LDR        R0, =__iar_program_start
+        BX         R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+; SysTick Handler is defined in mxc_delay.c
+;         PUBWEAK SysTick_Handler
+;         SECTION .text:CODE:REORDER:NOROOT(1)
+; SysTick_Handler
+;         B SysTick_Handler
+
+        PUBWEAK PF_IRQHandler             ; /* 0x10  0x0040  16: Power Fail */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PF_IRQHandler
+        B PF_IRQHandler
+
+        PUBWEAK WDT0_IRQHandler           ; /* 0x11  0x0044  17: Watchdog 0 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WDT0_IRQHandler
+        B WDT0_IRQHandler
+
+        PUBWEAK RSV00_IRQHandler          ; /* 0x12  0x0048  18: RSV00 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV00_IRQHandler
+        B RSV00_IRQHandler
+
+        PUBWEAK RTC_IRQHandler            ; /* 0x13  0x004C  19: RTC */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK RSV1_IRQHandler           ; /* 0x14  0x0050  20: RSV1 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV1_IRQHandler
+        B RSV1_IRQHandler
+
+        PUBWEAK TMR0_IRQHandler           ; /* 0x15  0x0054  21: Timer 0 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR0_IRQHandler
+        B TMR0_IRQHandler
+
+        PUBWEAK TMR1_IRQHandler           ; /* 0x16  0x0058  22: Timer 1 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_IRQHandler
+        B TMR1_IRQHandler
+
+        PUBWEAK TMR2_IRQHandler           ; /* 0x17  0x005C  23: Timer 2 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TMR2_IRQHandler
+        B TMR2_IRQHandler
+
+        PUBWEAK RSV02_IRQHandler          ; /* 0x18  0x0060  24: RSV02 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV02_IRQHandler
+        B RSV02_IRQHandler
+
+        PUBWEAK RSV03_IRQHandler          ; /* 0x19  0x0064  25: RSV03 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV03_IRQHandler
+        B RSV03_IRQHandler
+
+        PUBWEAK RSV04_IRQHandler          ; /* 0x1A  0x0068  26: RSV04 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV04_IRQHandler
+        B RSV04_IRQHandler
+
+        PUBWEAK RSV05_IRQHandler          ; /* 0x1B  0x006C  27: RSV05 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV05_IRQHandler
+        B RSV05_IRQHandler
+
+        PUBWEAK RSV06_IRQHandler          ; /* 0x1C  0x0070  28: RSV06 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV06_IRQHandler
+        B RSV06_IRQHandler
+
+        PUBWEAK I2C0_IRQHandler           ; /* 0x1D  0x0074  29: I2C0 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C0_IRQHandler
+        B I2C0_IRQHandler
+
+        PUBWEAK UART0_IRQHandler          ; /* 0x1E  0x0078  30: UART 0 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+        B UART0_IRQHandler
+
+        PUBWEAK UART1_IRQHandler          ; /* 0x1F  0x007C  31: UART 1 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART1_IRQHandler
+        B UART1_IRQHandler
+
+        PUBWEAK SPI0_IRQHandler           ; /* 0x20  0x0080  32: SPI0 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI0_IRQHandler
+        B SPI0_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler           ; /* 0x21  0x0084  33: SPI1 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK RSV07_IRQHandler          ; /* 0x22  0x0088  34: RSV07 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV07_IRQHandler
+        B RSV07_IRQHandler
+
+        PUBWEAK RSV08_IRQHandler          ; /* 0x23  0x008C  35: RSV08 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV08_IRQHandler
+        B RSV08_IRQHandler
+
+        PUBWEAK RSV09_IRQHandler          ; /* 0x24  0x0090  36: RSV09 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV09_IRQHandler
+        B RSV09_IRQHandler
+
+        PUBWEAK RSV10_IRQHandler          ; /* 0x25  0x0094  37: RSV10 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV10_IRQHandler
+        B RSV10_IRQHandler
+
+        PUBWEAK RSV11_IRQHandler          ; /* 0x26  0x0098  38: RSV11 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV11_IRQHandler
+        B RSV11_IRQHandler
+
+        PUBWEAK FLC_IRQHandler            ; /* 0x27  0x009C  39: FLC */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FLC_IRQHandler
+        B FLC_IRQHandler
+
+        PUBWEAK GPIO0_IRQHandler          ; /* 0x28  0x00A0  40: GPIO0 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO0_IRQHandler
+        B GPIO0_IRQHandler
+
+        PUBWEAK RSV12_IRQHandler          ; /* 0x29  0x00A4  41: RSV12 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV12_IRQHandler
+        B RSV12_IRQHandler
+
+        PUBWEAK RSV13_IRQHandler          ; /* 0x2A  0x00A8  42: RSV13 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV13_IRQHandler
+        B RSV13_IRQHandler
+
+        PUBWEAK RSV14_IRQHandler          ; /* 0x2B  0x00AC  43: RSV14 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV14_IRQHandler
+        B RSV14_IRQHandler
+
+        PUBWEAK DMA0_IRQHandler           ; /* 0x2C  0x00B0  44: DMA0 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA0_IRQHandler
+        B DMA0_IRQHandler
+
+        PUBWEAK DMA1_IRQHandler           ; /* 0x2D  0x00B4  45: DMA1 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_IRQHandler
+        B DMA1_IRQHandler
+
+        PUBWEAK DMA2_IRQHandler           ; /* 0x2E  0x00B8  46: DMA2 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_IRQHandler
+        B DMA2_IRQHandler
+
+        PUBWEAK DMA3_IRQHandler           ; /* 0x2F  0x00BC  47: DMA3 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA3_IRQHandler
+        B DMA3_IRQHandler
+
+        PUBWEAK RSV15_IRQHandler          ; /* 0x30  0x00C0  48: RSV15 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV15_IRQHandler
+        B RSV15_IRQHandler
+
+        PUBWEAK RSV16_IRQHandler          ; /* 0x31  0x00C4  49: RSV16 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV16_IRQHandler
+        B RSV16_IRQHandler
+
+        PUBWEAK RSV17_IRQHandler          ; /* 0x32  0x00C8  50: RSV17 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV17_IRQHandler
+        B RSV17_IRQHandler
+
+        PUBWEAK RSV18_IRQHandler          ; /* 0x33  0x00CC  51: RSV18 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV18_IRQHandler
+        B RSV18_IRQHandler
+
+        PUBWEAK I2C1_IRQHandler           ; /* 0x34  0x00D0  52: I2C1 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+
+        PUBWEAK RSV19_IRQHandler          ; /* 0x35  0x00D4  53: RSV19 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV19_IRQHandler
+        B RSV19_IRQHandler
+
+        PUBWEAK RSV20_IRQHandler          ; /* 0x36  0x00D8  54: RSV20 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV20_IRQHandler
+        B RSV20_IRQHandler
+
+        PUBWEAK RSV21_IRQHandler          ; /* 0x37  0x00DC  55: RSV21 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV21_IRQHandler
+        B RSV21_IRQHandler
+
+        PUBWEAK RSV22_IRQHandler          ; /* 0x38  0x00E0  56: RSV22 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV22_IRQHandler
+        B RSV22_IRQHandler
+
+        PUBWEAK RSV23_IRQHandler          ; /* 0x39  0x00E4  57: RSV23 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV23_IRQHandler
+        B RSV23_IRQHandler
+
+        PUBWEAK RSV24_IRQHandler          ; /* 0x3A  0x00E8  58: RSV24 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV24_IRQHandler
+        B RSV24_IRQHandler
+
+        PUBWEAK RSV25_IRQHandler          ; /* 0x3B  0x00EC  59: RSV25 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV25_IRQHandler
+        B RSV25_IRQHandler
+
+        PUBWEAK RSV26_IRQHandler          ; /* 0x3C  0x00F0  60: RSV26 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV26_IRQHandler
+        B RSV26_IRQHandler
+
+        PUBWEAK RSV27_IRQHandler          ; /* 0x3D  0x00F4  61: RSV27 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV27_IRQHandler
+        B RSV27_IRQHandler
+
+        PUBWEAK RSV28_IRQHandler          ; /* 0x3E  0x00F8  62: RSV28 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV28_IRQHandler
+        B RSV28_IRQHandler
+
+        PUBWEAK RSV29_IRQHandler          ; /* 0x3F  0x00FC  63: RSV29 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV29_IRQHandler
+        B RSV29_IRQHandler
+
+        PUBWEAK RSV30_IRQHandler          ; /* 0x40  0x0100  64: RSV30 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV30_IRQHandler
+        B RSV30_IRQHandler
+
+        PUBWEAK RSV31_IRQHandler          ; /* 0x41  0x0104  65: RSV31 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV31_IRQHandler
+        B RSV31_IRQHandler
+
+        PUBWEAK RSV32_IRQHandler          ; /* 0x42  0x0108  66: RSV32 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV32_IRQHandler
+        B RSV32_IRQHandler
+
+        PUBWEAK RSV33_IRQHandler          ; /* 0x43  0x010C  67: RSV33 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV33_IRQHandler
+        B RSV33_IRQHandler
+
+        PUBWEAK RSV34_IRQHandler          ; /* 0x44  0x0110  68: RSV34 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV34_IRQHandler
+        B RSV34_IRQHandler
+
+        PUBWEAK RSV35_IRQHandler          ; /* 0x45  0x0114  69: RSV35 */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RSV35_IRQHandler
+        B RSV35_IRQHandler
+
+        PUBWEAK GPIOWAKE_IRQHandler       ; /* 0x46  0x0118  70: GPIO Wakeup */
+        SECTION .text:CODE:REORDER:NOROOT(1)
+GPIOWAKE_IRQHandler
+        B GPIOWAKE_IRQHandler
+
+
+        END

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/heap.c

@@ -0,0 +1,77 @@
+ /**
+ * @file    heap.c
+ * @brief   System level setup help
+ */
+ 
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+ 
+/* **** Includes **** */ 
+#include <stdint.h>
+#include <errno.h>
+#include <unistd.h>
+
+/**
+ * @brief  sbrk
+ * @detail Increase program data space
+ * @detail Malloc and related functions depend on this
+ */
+ 
+/* **** declarations **** */
+static char *heap_end = 0;
+extern unsigned int __HeapBase;
+extern unsigned int __HeapLimit;
+
+/* **** functions **** */
+caddr_t _sbrk(int incr)
+{
+    char *prev_heap_end;
+
+    if (heap_end == 0) {
+        heap_end = (caddr_t)&__HeapBase;
+    }
+    prev_heap_end = heap_end;
+
+    if ((unsigned int)(heap_end + incr) > (unsigned int)&__HeapLimit) {
+        errno = ENOMEM;
+        return  (caddr_t) -1;
+    }
+
+    heap_end += incr;
+
+    return (caddr_t) prev_heap_end;
+}
+

bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c

@@ -0,0 +1,167 @@
+/**
+ * @file       system_max32660.c
+ * @brief      System-level initialization implementation file
+ */
+
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ ******************************************************************************/
+
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "max32660.h"
+#include "gcr_regs.h"
+#include "pwrseq_regs.h"
+#include "tmr_regs.h"
+#include "wdt_regs.h"
+#include "mxc_sys.h"
+
+extern void (* const __isr_vector[])(void);
+uint32_t SystemCoreClock = HIRC96_FREQ;
+
+__weak void SystemCoreClockUpdate(void)
+{
+    uint32_t base_freq, div, clk_src,ovr;
+
+    // Get the clock source and frequency
+    clk_src = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_CLKSEL);
+    
+    if (clk_src == MXC_S_GCR_CLKCN_CLKSEL_HFXIN) {
+        base_freq = HFX_FREQ;
+    } else {
+	if (clk_src == MXC_S_GCR_CLKCN_CLKSEL_NANORING) {
+	    base_freq = NANORING_FREQ;
+	} else {
+	    ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
+	    if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
+		base_freq = HIRC96_FREQ/4;
+	    } else {
+		if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
+		    base_freq = HIRC96_FREQ/2;
+		} else {
+		    base_freq = HIRC96_FREQ;
+		}
+	    }
+	}
+    }
+
+    // Get the clock divider
+    div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS;
+
+    SystemCoreClock = base_freq >> div;
+}
+
+/* This function is called before C runtime initialization and can be
+ * implemented by the application for early initializations. If a value other
+ * than '0' is returned, the C runtime initialization will be skipped.
+ *
+ * You may over-ride this function in your program by defining a custom
+ *  PreInit(), but care should be taken to reproduce the initilization steps
+ *  or a non-functional system may result.
+ */
+__weak int PreInit(void)
+{
+    /* Do nothing */
+    return 0;
+}
+
+/* This function can be implemented by the application to initialize the board */
+__weak int Board_Init(void)
+{
+    /* Do nothing */
+    return 0;
+}
+
+/* This function is called just before control is transferred to main().
+ *
+ * You may over-ride this function in your program by defining a custom
+ *  SystemInit(), but care should be taken to reproduce the initialization
+ *  steps or a non-functional system may result.
+ */
+__weak void SystemInit(void)
+{
+    /* Configure the interrupt controller to use the application vector table in */
+    /* the application space */
+    /* IAR & Keil must set vector table after all memory initialization. */
+    SCB->VTOR = (unsigned long)__isr_vector;
+
+    MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN;  /* Turn off watchdog. Application can re-enable as needed. */
+
+    /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
+    /* Grant full access, per "Table B3-24 CPACR bit assignments". */
+    /* DDI0403D "ARMv7-M Architecture Reference Manual" */
+    SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
+    __DSB();
+    __ISB();
+
+    /* Switch system clock to HIRC */
+    SYS_Clock_Select(SYS_CLOCK_HIRC, MXC_TMR0);
+
+    /* Disable clocks to peripherals by default to reduce power */
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_DMA);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_SPI17Y);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_SPIMSS);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_UART0);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_UART1);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C0);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_T0);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_T1);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_T2);
+    SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C1);
+    
+    Board_Init();
+}
+
+#if defined ( __CC_ARM )
+/* Global variable initialization does not occur until post scatterload in Keil tools.*/
+
+/* External function called after our post scatterload function implementation. */
+extern void $Super$$__main_after_scatterload(void);
+
+/**
+ * @brief   Initialization function for SystemCoreClock and Board_Init.
+ * @details $Sub$$__main_after_scatterload is called during system startup in the Keil
+ *          toolset. Global variable and static variable space must be set up by the compiler
+ *          prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init
+ *          require global memory for variable storage and are called from this function in
+ *          the Keil tool chain.
+ */
+void $Sub$$__main_after_scatterload(void)
+{
+    SystemInit();
+    $Super$$__main_after_scatterload();
+}
+#endif /* __CC_ARM */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/dma.h

@@ -0,0 +1,317 @@
+/**
+ * @file
+ * @brief   Direct Memory Access (DMA) driver function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-07-01 11:06:19 -0500 (Mon, 01 Jul 2019) $
+ * $Revision: 44383 $
+ *
+ *************************************************************************** */
+
+#ifndef _DMA_H_
+#define _DMA_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "dma_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup dma Direct Memory Access (DMA)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * Enumeration for the DMA Channel's priority level.
+ */
+typedef enum {
+    DMA_PRIO_HIGH = MXC_S_DMA_CFG_PRI_HIGH,         /**< High Priority */
+    DMA_PRIO_MEDHIGH = MXC_S_DMA_CFG_PRI_MEDHIGH,   /**< Medium High Priority */
+    DMA_PRIO_MEDLOW = MXC_S_DMA_CFG_PRI_MEDLOW,     /**< Medium Low Priority */
+    DMA_PRIO_LOW = MXC_S_DMA_CFG_PRI_LOW,           /**< Low Priority */
+} dma_priority_t;
+
+/** @brief DMA request select */
+typedef enum {
+    DMA_REQSEL_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM,        /**< Memory to Memory DMA Request Selection */
+    DMA_REQSEL_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX,            /**< SPI0 Receive DMA Request Selection */
+    DMA_REQSEL_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX,            /**< SPI1 Receive DMA Request Selection */
+    DMA_REQSEL_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX,          /**< UART0 Receive DMA Request Selection */
+    DMA_REQSEL_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX,          /**< UART1 Receive DMA Request Selection */
+    DMA_REQSEL_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX,            /**< I2C0 Receive DMA Request Selection */
+    DMA_REQSEL_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX,            /**< I2C1 Receive DMA Request Selection */
+    DMA_REQSEL_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX,            /**< SPI0 Transmit DMA Request Selection */
+    DMA_REQSEL_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX,            /**< SPI1 Transmit DMA Request Selection */
+    DMA_REQSEL_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX,          /**< UART0 Transmit DMA Request Selection */
+    DMA_REQSEL_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX,          /**< UART1 Transmit DMA Request Selection */
+    DMA_REQSEL_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX,            /**< I2C0 Transmit DMA Request Selection */
+    DMA_REQSEL_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX,            /**< I2C1 Transmit DMA Request Selection */
+} dma_reqsel_t;
+
+/** @brief Enumeration for the DMA prescaler */
+typedef enum {
+    DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS,     /**< Prescaler disabled */
+    DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256,   /**< Divide by 256 */
+    DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K,   /**< Divide by 65,536 */
+    DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M,   /**< Divide by 16,777,216 */
+} dma_prescale_t;
+
+/** @brief Enumeration for the DMA timeout value */
+typedef enum {
+    DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4,        /**< DMA timeout of 4 clocks */
+    DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8,        /**< DMA timeout of 8 clocks */
+    DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16,      /**< DMA timeout of 16 clocks */
+    DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32,      /**< DMA timeout of 32 clocks */
+    DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64,      /**< DMA timeout of 64 clocks */
+    DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128,    /**< DMA timeout of 128 clocks */
+    DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256,    /**< DMA timeout of 256 clocks */
+    DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512,    /**< DMA timeout of 512 clocks */
+} dma_timeout_t;
+
+/** @brief DMA transfer data width */
+typedef enum {
+    /* Using the '_V_' define instead of the '_S_' since these same values will be used to 
+       specify the DSTWD also.  The API functions will shift the value the correct amount 
+       prior to writing the cfg register. */
+    DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE,          /**< DMA transfer in bytes */
+    DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD,  /**< DMA transfer in 16-bit half-words */
+    DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD,          /**< DMA transfer in 32-bit words */
+} dma_width_t;
+
+/** @brief Convenience defines for options */
+#define DMA_FALSE 0 /**< Define for passing 0 to DMA functions */
+#define DMA_TRUE  1 /**< Define for passing 1 to DMA functions */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Initialize DMA resources
+ * @details    This initialization is required before using the DMA driver functions.
+ * @return     #E_NO_ERROR if successful
+ */
+int DMA_Init(void);
+
+
+/**
+ * @brief      Request DMA channel
+ * @details    Returns a handle to the first free DMA channel, which can be used via API calls
+ *             or direct access to channel registers using the DMA_GetCHRegs(int ch) function.
+ * @return     Non-negative channel handle (inclusive of zero).
+ * @return     #E_NONE_AVAIL    All channels in use.
+ * @return     #E_BAD_STATE     DMA is not initialized, call DMA_Init() first.
+ * @return     #E_BUSY          DMA is currently busy (locked), try again later.
+ */
+int DMA_AcquireChannel(void);
+
+/**
+ * @brief      Release DMA channel
+ * @details    Stops any DMA operation on the channel and returns it to the pool of free channels.
+ *
+ * @param          ch   channel handle to release
+ *
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
+ */
+int DMA_ReleaseChannel(int ch);
+
+/**
+ * @brief      Configure the DMA channel
+ * @details    Configures the channel, which was previously requested by DMA_Getchannel()
+ *
+ * @param      ch           The channel to configure
+ * @param      prio         The channel's priority
+ * @param      reqsel       Select the DMA request line
+ * @param      reqwait_en   The enable delay before request
+ * @param      tosel        The transfer timer timeout select
+ * @param      pssel        The transfer timer prescale select
+ * @param      srcwd        The size of the read transactions
+ * @param      srcinc_en    Enable auto-increment source pointer
+ * @param      dstwd        The size of write transactions
+ * @param      dstinc_en    Enable auto-increment destination pointer
+ * @param      burst_size   The number of bytes transferred in one transaction
+ * @param      chdis_inten  The channel disable interrupt enable
+ * @param      ctz_inten    The count-to-zero interrupt enable
+ *
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_ConfigChannel(int ch,
+                      dma_priority_t prio,
+                      dma_reqsel_t reqsel, unsigned int reqwait_en,
+                      dma_timeout_t tosel, dma_prescale_t pssel,
+                      dma_width_t srcwd, unsigned int srcinc_en,
+                      dma_width_t dstwd, unsigned int dstinc_en,
+                      unsigned int burst_size, unsigned int chdis_inten,
+                      unsigned int ctz_inten);
+
+/**
+ * @brief      Set channel source, destination, and count for transfer
+ * @param      ch   channel handle
+ * @param      src_addr  source address (*)
+ * @param      dst_addr  destination address (*)
+ * @param      count  number of bytes to transfer
+ * @details    This function is used to set the source and destination addresses and the number
+ *             of bytes to transfer using the channel, @p ch.
+ * @note       Unless the channel request select is #DMA_REQSEL_MEMTOMEM,
+ *             either src_addr or dst_addr will be ignored by the DMA engine.
+ *             In these cases, the address is a don't-care. See the User's
+ *             Guide for more information.
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_SetSrcDstCnt(int ch,
+                     void *src_addr,
+                     void *dst_addr,
+                     unsigned int count);
+
+/**
+ * @brief      Set channel reload values
+ * @param      ch   channel handle
+ * @param      src_addr_reload  source address
+ * @param      dst_addr_reload  destination address
+ * @param      count_reload  number of bytes to transfer
+ * @details    This function will set the values which will be loaded after the
+ *             channel count register reaches zero. After enabling, call with
+ *             count_reload set to zero to disable reload.
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_SetReload(int ch,
+                  void *src_addr_reload,
+                  void *dst_addr_reload,
+                  unsigned int count_reload);
+
+/**
+ * @brief      Set channel interrupt callback
+ * @param      ch        channel handle
+ * @param      callback  Pointer to a function to call when the channel
+ *                       interrupt flag is set and interrupts are enabled or
+ *                       when DMA is shutdown by the driver.
+ * @details    Configures the channel interrupt callback. The @p callback
+ *             function is called for two conditions:
+ *               -# When the channel's interrupt flag is set and DMA interrupts
+ *                  are enabled.
+ *               -# If the driver calls the DMA_Shutdown() function. The
+ *                  callback function prototype is:
+ * @code
+ *             void callback_fn(int ch, int reason);
+ * @endcode
+ *             @p ch indicates the channel that generated the callback, @p
+ *             reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN
+ *             if the DMA is being shutdown.
+ *
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_SetCallback(int ch, void (*callback)(int, int));
+
+/**
+ * @brief      Enable channel interrupt
+ * @param      ch   channel handle
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_EnableInterrupt(int ch);
+
+/**
+ * @brief      Disable channel interrupt
+ * @param      ch   channel handle
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_DisableInterrupt(int ch);
+
+/**
+ * @brief Read channel interrupt flags
+ * @param      ch channel handle
+ * @param      fl flags to get
+ * @return    #E_BAD_PARAM if an unused or invalid channel handle
+ * @return    #E_NO_ERROR otherwise
+ */
+int DMA_GetFlags(int ch, unsigned int *fl);
+
+/**
+ * @brief      Clear channel interrupt flags
+ * @param      ch   channel handle
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_ClearFlags(int ch);
+
+/**
+ * @brief      Start transfer
+ * @param      ch   channel handle
+ * @details    Start the DMA channel transfer, assumes that DMA_SetSrcDstCnt() has been called beforehand.
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_Start(int ch);
+
+/**
+ * @brief      Stop DMA transfer, irrespective of status (complete or in-progress)
+ * @param      ch   channel handle
+ * @return     #E_BAD_PARAM if an unused or invalid channel handle
+ * @return     #E_NO_ERROR otherwise
+ */
+int DMA_Stop(int ch);
+
+/**
+ * @brief      Get a pointer to the DMA channel registers
+ * @param      ch   channel handle
+ * @details    If direct access to DMA channel registers is required, this
+ *             function can be used on a channel handle returned by DMA_AcquireChannel().
+ * @return     NULL if an unused or invalid channel handle, or a valid pointer otherwise
+ */
+mxc_dma_ch_regs_t *DMA_GetCHRegs(int ch);
+
+/**
+ * @brief      Interrupt handler function
+ * @param      ch   channel handle
+ * @details    Call this function as the ISR for each DMA channel under driver control.
+ *             Interrupt flags for channel ch will be automatically cleared before return.
+ * @return     NULL if an unused or invalid channel handle, or a valid pointer otherwise
+ */
+void DMA_Handler(int ch);
+
+/**@} end of group dma */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DMA_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/flc.h

@@ -0,0 +1,200 @@
+/**
+ * @file
+ * @brief      Flash Controler driver.
+ * @details    This driver can be used to operate on the embedded flash memory.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-06-05 16:53:29 -0500 (Wed, 05 Jun 2019) $
+ * $Revision: 43696 $
+ *
+ *************************************************************************** */
+
+#ifndef _FLC_H_
+#define _FLC_H_
+
+/* **** Includes **** */
+#include "flc_regs.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup flc Flash Controller
+ * @ingroup periphlibs
+ * @{
+ */
+
+/***** Definitions *****/
+
+/// Bit mask that can be used to find the starting address of a page in flash
+#define MXC_FLASH_PAGE_MASK         ~(MXC_FLASH_PAGE_SIZE - 1)
+
+/// Calculate the address of a page in flash from the page number
+#define MXC_FLASH_PAGE_ADDR(page)   (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
+
+/***** Function Prototypes *****/
+
+/**
+ * @brief      Initializes the flash controller for erase/write operations
+ * @param      sys_cfg      Reserved for future use.  Use NULL as this parameter's value.  
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int FLC_Init(const sys_cfg_flc_t *sys_cfg);
+  
+/**
+ * @brief      Checks if Flash controller is busy.
+ * @details    Reading or executing from flash is not possible if flash is busy
+ *             with an erase or write operation.
+ * @return     If non-zero, flash operation is in progress
+ */
+int FLC_Busy(void);
+  
+/**
+ * @brief      Erases the entire flash array.
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int FLC_MassErase(void);
+
+/**
+ * @brief      Erases the page of flash at the specified address.
+ * @param      address  Any address within the page to erase.
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int FLC_PageErase(uint32_t address);
+
+/**
+ * @brief      Page erase from start to end address.
+ * @note       All data within the selected pages will be erased.
+ * @param      start  Any address within the first page to erase.
+ * @param      end    Any address within the last page to erase.
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int FLC_Erase(uint32_t start, uint32_t end);
+
+/**
+ * @brief      Erase from start to end address.  Restoring any flash page contents outside the given range.
+ * @param      start    Starting address to erase, inclusive.
+ * @param      end      Ending address to erase, exclusive.
+ * @param      buffer   Data buffer to restore data in beginning and ending pages.
+ * @param      length   Length of given buffer.
+ * 
+ * @note       Buffer should be appropriate size to store all of the data remaining in the 
+ * first and last pages. length should be greater than or equal to 
+ * (start % MXC_FLASH_PAGE_SIZE) and ((MXC_FLASH_PAGE_SIZE - (end % MXC_FLASH_PAGE_SIZE)) % MXC_FLASH_PAGE_SIZE).
+ * 
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int FLC_BufferErase(uint32_t start, uint32_t end, uint8_t *buffer, unsigned length);
+
+/**
+ * @brief      Writes the specified 32-bit value to flash.
+ * @param      address  32-bit aligned address in flash to write.
+ * @param      data     value to be written to flash.
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int FLC_Write32(uint32_t address, uint32_t data);
+
+/**
+ * @brief      Writes the specified 128-bits of data to flash.
+ * @param      address  128-bit aligned address in flash to write.
+ * @param      data     pointer to data to be written to flash.
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int FLC_Write128(uint32_t address, uint32_t *data);
+
+/**
+ * @brief      Writes data to flash.
+ * @param      address  Address in flash to start writing from.
+ * @param      length   Number of bytes to be written.
+ * @param      buffer   Pointer to data to be written to flash.
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int FLC_Write(uint32_t address, uint32_t length, uint8_t *buffer);
+
+/**
+ * @brief      Enable flash interrupts
+ * @param      mask   Interrupts to enable
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int FLC_EnableInt(uint32_t mask);
+
+/**
+ * @brief      Disable flash interrupts
+ * @param      mask   Interrupts to disable
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int FLC_DisableInt(uint32_t mask);
+
+/**
+ * @brief      Retrieve flash interrupt flags
+ * @return     Mask of active flags.
+ */
+int FLC_GetFlags(void);
+
+/**
+ * @brief      Clear flash interrupt flags
+ * @note       Provide the bit position to clear, even if the flag is write-0-to-clear
+ * @param      mask Mask of flags to clear
+ * @return     #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int FLC_ClearFlags(uint32_t mask);
+
+/**
+ * @brief      Unlock info block
+ *
+ * @return     #E_NO_ERROR If function is successful.
+ */
+int FLC_UnlockInfoBlock(void);
+
+/**
+ * @brief      Lock info block
+ *
+ * @return     #E_NO_ERROR If function is successful.
+ */
+int FLC_LockInfoBlock(void);
+/**@} end of group flc */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLC_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/gpio.h

@@ -0,0 +1,295 @@
+/**
+ * @file    gpio.h
+ * @brief   General-Purpose Input/Output (GPIO) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+/* **** Includes **** */
+#include "gpio_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup gpio General-Purpose Input/Output (GPIO)
+ * @ingroup periphlibs
+ * @{
+ */
+
+/* **** Definitions **** */
+/**
+ * @defgroup gpio_port_pin Port and Pin Definitions
+ * @ingroup gpio
+ * @{
+ * @defgroup gpio_port Port Definitions
+ * @ingroup gpio_port_pin
+ * @{
+ */
+#define PORT_0      ((uint32_t)(0UL))             /**< Port 0  Define*/
+#define PORT_1      ((uint32_t)(1UL))             /**< Port 1  Define*/
+#define PORT_2      ((uint32_t)(2UL))             /**< Port 2  Define*/
+#define PORT_3      ((uint32_t)(3UL))             /**< Port 3  Define*/
+#define PORT_4      ((uint32_t)(4UL))             /**< Port 4  Define*/
+/**@} end of gpio_port group*/
+/**
+ * @defgroup gpio_pin Pin Definitions
+ * @ingroup gpio_port_pin
+ * @{
+ */
+#define PIN_0       ((uint32_t)(1UL << 0))       /**< Pin 0 Define */
+#define PIN_1       ((uint32_t)(1UL << 1))       /**< Pin 1 Define */
+#define PIN_2       ((uint32_t)(1UL << 2))       /**< Pin 2 Define */
+#define PIN_3       ((uint32_t)(1UL << 3))       /**< Pin 3 Define */
+#define PIN_4       ((uint32_t)(1UL << 4))       /**< Pin 4 Define */
+#define PIN_5       ((uint32_t)(1UL << 5))       /**< Pin 5 Define */
+#define PIN_6       ((uint32_t)(1UL << 6))       /**< Pin 6 Define */
+#define PIN_7       ((uint32_t)(1UL << 7))       /**< Pin 7 Define */
+#define PIN_8       ((uint32_t)(1UL << 8))       /**< Pin 8 Define */
+#define PIN_9       ((uint32_t)(1UL << 9))       /**< Pin 9 Define */
+#define PIN_10      ((uint32_t)(1UL << 10))       /**< Pin 10 Define */
+#define PIN_11      ((uint32_t)(1UL << 11))       /**< Pin 11 Define */
+#define PIN_12      ((uint32_t)(1UL << 12))       /**< Pin 12 Define */
+#define PIN_13      ((uint32_t)(1UL << 13))       /**< Pin 13 Define */
+#define PIN_14      ((uint32_t)(1UL << 14))       /**< Pin 14 Define */
+#define PIN_15      ((uint32_t)(1UL << 15))       /**< Pin 15 Define */
+#define PIN_16      ((uint32_t)(1UL << 16))       /**< Pin 16 Define */
+#define PIN_17      ((uint32_t)(1UL << 17))       /**< Pin 17 Define */
+#define PIN_18      ((uint32_t)(1UL << 18))       /**< Pin 18 Define */
+#define PIN_19      ((uint32_t)(1UL << 19))       /**< Pin 19 Define */
+#define PIN_20      ((uint32_t)(1UL << 20))       /**< Pin 20 Define */
+#define PIN_21      ((uint32_t)(1UL << 21))       /**< Pin 21 Define */
+#define PIN_22      ((uint32_t)(1UL << 22))       /**< Pin 22 Define */
+#define PIN_23      ((uint32_t)(1UL << 23))       /**< Pin 23 Define */
+#define PIN_24      ((uint32_t)(1UL << 24))       /**< Pin 24 Define */
+#define PIN_25      ((uint32_t)(1UL << 25))       /**< Pin 25 Define */
+#define PIN_26      ((uint32_t)(1UL << 26))       /**< Pin 26 Define */
+#define PIN_27      ((uint32_t)(1UL << 27))       /**< Pin 27 Define */
+#define PIN_28      ((uint32_t)(1UL << 28))       /**< Pin 28 Define */
+#define PIN_29      ((uint32_t)(1UL << 29))       /**< Pin 29 Define */
+#define PIN_30      ((uint32_t)(1UL << 30))       /**< Pin 30 Define */
+#define PIN_31      ((uint32_t)(1UL << 31))       /**< Pin 31 Define */
+/**@} end of gpio_pin group */
+/**@} end of gpio_port_pin group */
+
+/**
+ * Enumeration type for the GPIO Function Type
+ */
+typedef enum {
+    GPIO_FUNC_IN,       /**< GPIO Input */
+    GPIO_FUNC_OUT,      /**< GPIO Output */
+    GPIO_FUNC_ALT1,     /**< Alternate Function Selection */
+    GPIO_FUNC_ALT2,     /**< Alternate Function Selection */
+    GPIO_FUNC_ALT3,     /**< Alternate Function Selection */
+    GPIO_FUNC_ALT4,     /**< Alternate Function Selection */
+} gpio_func_t;
+
+/**
+ * Enumeration type for the type of GPIO pad on a given pin.
+ */
+typedef enum {
+    GPIO_PAD_NONE,          /**< No pull-up or pull-down */
+    GPIO_PAD_PULL_UP,       /**< Set pad to weak pull-up */
+    GPIO_PAD_PULL_DOWN,     /**< Set pad to weak pull-down */
+} gpio_pad_t;
+
+/**
+ * Structure type for configuring a GPIO port.
+ */
+typedef struct {
+    uint32_t port;          /**< Index of GPIO port */
+    uint32_t mask;          /**< Pin mask (multiple pins may be set) */
+    gpio_func_t func;       /**< Function type */
+    gpio_pad_t pad;         /**< Pad type */
+} gpio_cfg_t;
+
+/**
+ * Enumeration type for the interrupt modes.
+ */
+typedef enum {
+  GPIO_INT_LEVEL = 0,   /**< Interrupt is level sensitive */
+  GPIO_INT_EDGE = 1     /**< Interrupt is edge sensitive */
+} gpio_int_mode_t;
+
+/**
+ * Enumeration type for the interrupt polarity.
+ */
+typedef enum {
+  GPIO_INT_FALLING = 0,                 /**< Interrupt triggers on falling edge */
+  GPIO_INT_HIGH = GPIO_INT_FALLING,     /**< Interrupt triggers when level is high */
+  GPIO_INT_RISING,                      /**< Interrupt triggers on rising edge */
+  GPIO_INT_LOW = GPIO_INT_RISING,       /**< Interrupt triggers when level is low */
+  GPIO_INT_BOTH                         /**< Interrupt triggers on either edge */
+} gpio_int_pol_t;
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Initialize GPIO.
+ * @return     #E_NO_ERROR if everything is successful.
+ */
+int GPIO_Init(void);
+
+/**
+ * @brief      Configure GPIO pin(s).
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ * @return     #E_NO_ERROR if everything is successful.
+ */
+int GPIO_Config(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Gets the pin(s) input state.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ * @return     The requested pin state.
+ */
+uint32_t GPIO_InGet(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Sets the pin(s) to a high level output.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ *
+ */
+void GPIO_OutSet(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Clears the pin(s) to a low level output.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ *
+ */
+void GPIO_OutClr(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Gets the pin(s) output state.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ *
+ * @return     The state of the requested pin.
+ *
+ */
+uint32_t GPIO_OutGet(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Write the pin(s) to a desired output level.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ * @param      val   Desired output level of the pin(s). This will be masked
+ *                   with the configuration mask.
+ */
+void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val);
+
+/**
+ * @brief      Toggles the the pin(s) output level.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ *
+ */
+void GPIO_OutToggle(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Configure GPIO interrupt(s)
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ * @param      mode  Requested interrupt mode.
+ * @param      pol   Requested interrupt polarity.
+ * @return     #E_NO_ERROR if everything is successful.
+ */
+int GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode, gpio_int_pol_t pol);
+
+/**
+ * @brief      Enables the specified GPIO interrupt
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ *
+ */
+void GPIO_IntEnable(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Disables the specified GPIO interrupt.
+ * @param      cfg   Pointer to configuration structure describing the pin.
+ */
+void GPIO_IntDisable(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Gets the interrupt(s) status on a GPIO pin.
+ * @param      cfg   Pointer to configuration structure describing the pin
+ *                   for which the status is being requested.
+ * @return     The requested interrupt status.
+ */
+uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Clears the interrupt(s) status on a GPIO pin.
+ * @param      cfg   Pointer to configuration structure describing the pin
+ *                   to clear the interrupt state of.
+ */
+void GPIO_IntClr(const gpio_cfg_t *cfg);
+
+/**
+ * @brief      Type alias for a GPIO callback function with prototype:
+ * @code
+    void callback_fn(void *cbdata);
+ * @endcode
+ * @param      cbdata  A void pointer to the data type as registered when
+ *                     GPIO_RegisterCallback() was called.
+ */
+typedef void (*gpio_callback_fn)(void *cbdata);
+
+/**
+ * @brief      Registers a callback for the interrupt on a given port and pin.
+ * @param      cfg       Pointer to configuration structure describing the pin
+ * @param      callback  A pointer to a function of type \c #gpio_callback_fn.
+ * @param      cbdata    The parameter to be passed to the callback function, #gpio_callback_fn, when an interrupt occurs.
+ *
+ */
+void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn callback, void *cbdata);
+
+/**
+ * @brief      GPIO IRQ Handler. @note If a callback is registered for a given
+ *             interrupt, the callback function will be called.
+ *
+ * @param      port number of the port that generated the interrupt service routine.
+ *
+ */
+void GPIO_Handler(unsigned int port);
+
+/**@} end of group gpio */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GPIO_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/i2c.h

@@ -0,0 +1,250 @@
+/**
+ * @file    i2c.h
+ * @brief   Inter-integrated circuit (I2C) communications interface driver.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2019-06-28 09:42:42 -0500 (Fri, 28 Jun 2019) $
+ * $Revision: 44330 $
+ *
+ *************************************************************************** */
+
+#ifndef _I2C_H_
+#define _I2C_H_
+
+#include <stdint.h>
+#include "i2c_regs.h"
+#include "mxc_sys.h"
+
+/**
+ * @defgroup i2c I2C
+ * @ingroup periphlibs
+ * @{
+ */
+
+/***** Definitions *****/
+
+/// @brief I2C Speed Modes
+typedef enum {
+    I2C_STD_MODE        = 100000,       //!< 100KHz Bus Speed 
+    I2C_FAST_MODE       = 400000,       //!< 400KHz Bus Speed 
+    I2C_FASTPLUS_MODE   = 1000000,      //!< 1MHz   Bus Speed
+    I2C_HS_MODE         = 3400000       //!< 3.4MHz Bus Speed 
+} i2c_speed_t;
+
+//State for Master
+typedef enum {
+    I2C_STATE_READING = 0,
+    I2C_STATE_WRITING = 1
+} i2c_state_t;
+
+// @brief Enable/Disable TXFIFO Autoflush mode
+typedef enum {
+    I2C_AUTOFLUSH_ENABLE   = 0,
+    I2C_AUTOFLUSH_DISABLE  = 1 
+} i2c_autoflush_disable_t;
+
+// @brief I2C Transaction request.
+typedef struct i2c_req i2c_req_t;
+struct i2c_req {
+
+    uint8_t addr;                  /**< @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
+                                     *     Only supports 7-bit addressing. LSb of the given address
+                                     *     will be used as the read/write bit, the @p addr <b>will 
+                                     *     not be shifted</b>. Used for <em>both master</em> and 
+                                     *     @em slave transactions. @endparblock
+                                     */
+    const uint8_t *tx_data;          ///< Data for mater write/slave read.
+    uint8_t *rx_data;                ///< Data for master read/slave write.
+    unsigned tx_len;                 ///< Length of tx data.
+    unsigned rx_len;                 ///< Length of rx.
+    unsigned tx_num;                 ///< Number of tx bytes sent.
+    unsigned rx_num;                 ///< Number of rx bytes sent.
+    i2c_state_t state;               ///< Read or Write.
+
+    /**
+     * @details     0 to send a stop bit at the end of the transaction, 
+                    otherwise send a restart. Only used in master trasnactions.
+     */
+    int restart;                   /**< @parblock Restart or stop bit indicator. 
+                                     *    @arg 0 to send a stop bit at the end of the transaction
+                                     *    @arg Non-zero to send a restart at end of the transaction
+                                     *    @note Only used for Master transactions.
+                                     *    @endparblock
+                                     */ 
+    i2c_autoflush_disable_t sw_autoflush_disable;       ///< Enable/Disable autoflush.
+
+    /**
+     * @brief   Callback for asynchronous request.
+     * @param   i2c_req_t*  Pointer to the transaction request.
+     * @param   int         Error code.
+     */
+    void (*callback)(i2c_req_t*, int);
+};
+
+/***** Function Prototypes *****/
+
+/**
+ * @brief   Initialize and enable I2C.
+ * @param      i2c     Pointer to I2C peripheral registers.
+ * @param      i2cspeed desired speed (I2C mode)
+ * @param      sys_cfg System configuration object
+ * @returns \c #E_NO_ERROR if everything is successful, 
+ *             @ref MXC_Error_Codes if an error occurred.
+ */
+int I2C_Init(mxc_i2c_regs_t * i2c, i2c_speed_t i2cspeed, const sys_cfg_i2c_t* sys_cfg);
+
+/**
+ * @brief   Shutdown I2C module.
+ * @param   i2c    Pointer to the I2C registers.
+ * @returns #E_NO_ERROR I2C shutdown successfully, @ref MXC_Error_Codes "error" if
+ *             unsuccessful.
+ */
+int I2C_Shutdown(mxc_i2c_regs_t *i2c);
+
+/**
+ * @brief   Master write data. Will block until transaction is complete.
+ * @param   i2c         Pointer to I2C regs.
+ * @param   addr        @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
+ *                          Only supports 7-bit addressing. LSb of the given address
+ *                          will be used as the read/write bit, the \p addr <b>will 
+ *                          not be shifted</b>. Used for <em>both master</em> and 
+ *                          @em slave transactions.    @endparblock                                 
+ * @param   data        Data to be written.
+ * @param   len         Number of bytes to Write.
+ * @param   restart     0 to send a stop bit at the end of the transaction, 
+                        otherwise send a restart.
+ * @returns Bytes transacted if everything is successful, 
+ *              @ref MXC_Error_Codes if an error occurred.
+ */
+int I2C_MasterWrite(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* data, int len, int restart);
+
+/**
+ * @brief   Master read data. Will block until transaction is complete.
+ * @param   i2c         Pointer to I2C regs.
+ * @param   addr        @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
+ *                          Only supports 7-bit addressing. LSb of the given address
+ *                          will be used as the read/write bit, the @p addr <b>will 
+ *                          not be shifted</b>. Used for <em>both master</em> and 
+ *                          @em slave transactions.  @endparblock
+ * @param   data        Data to be written.
+ * @param   len         Number of bytes to Write.
+ * @param   restart     0 to send a stop bit at the end of the transaction, 
+                        otherwise send a restart.
+ * @returns Bytes transacted if everything is successful, @ref MXC_Error_Codes if an error occurred.
+ */
+int I2C_MasterRead(mxc_i2c_regs_t *i2c, uint8_t addr, uint8_t* data, int len, int restart);
+
+/**
+ * @brief   Slave read data. Will block until transaction is complete.
+ * @param   i2c         Pointer to I2C regs.
+ * @param   addr        @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
+ *                          Only supports 7-bit addressing. LSb of the given address
+ *                          will be used as the read/write bit, the @p addr <b>will 
+ *                          not be shifted</b>. Used for <em>both master</em> and 
+ *                          @em slave transactions.  @endparblock
+ * @param   read_data   Buffer that the master will read from.
+ * @param   read_len    Number of bytes the master can read.
+ * @param   write_data  Buffer that the master will write to.
+ * @param   write_len   Number of bytes the master can write.
+ * @param   tx_num      Number of bytes transmitted by the slave.
+ * @param   rx_num      Number of bytes received by the slave.
+ * @param   sw_autoflush_disable      TX Autoflush enabled by default.Set this bit to disable autoflush manually.
+ * @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred.
+ */
+int I2C_Slave(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* read_data, 
+              int read_len, uint8_t* write_data, int write_len, int* tx_num, 
+              int* rx_num, i2c_autoflush_disable_t sw_autoflush_disable);
+
+/**
+ * @brief   Master Read and Write Asynchronous.
+ * @param   i2c         Pointer to I2C regs.
+ * @param   req         Request for an I2C transaction.
+ * @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred.
+ */
+int I2C_MasterAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req);
+
+/**
+ * @brief   Slave Read and Write Asynchronous.
+ * @param   i2c         Pointer to I2C regs.
+ * @param   req         Request for an I2C transaction.
+ * @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred.
+ */
+int I2C_SlaveAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req);
+/**
+ * @brief   I2C interrupt handler.
+ * @details This function should be called by the application from the interrupt
+ *          handler if I2C interrupts are enabled. Alternately, this function
+ *          can be periodically called by the application if I2C interrupts are
+ *          disabled.
+ * @param   i2c         Base address of the I2C module.
+ */
+void I2C_Handler(mxc_i2c_regs_t *i2c);
+
+/**
+ * @brief   Drain all of the data in the RXFIFO.
+ * @param   i2c     Pointer to I2C regs.
+ */
+void I2C_DrainRX(mxc_i2c_regs_t *i2c);
+
+/**
+ * @brief   Drain all of the data in the TXFIFO.
+ * @param   i2c     Pointer to I2C regs.
+ */
+void I2C_DrainTX(mxc_i2c_regs_t *i2c);
+
+/**
+ * @brief   Abort Async request based on the request you want to abort.
+ * @param   req     Pointer to I2C Transaction.
+ */
+int I2C_AbortAsync(i2c_req_t *req);
+
+/**
+ * @brief      Enable and Set Timeout 
+ *
+ * @param      i2c   pointer to I2C regs
+ * @param[in]  us    micro seconds to delay
+ *
+ * @return     E_NO_ERROR or E_BAD_PARAM if delay is to long.
+ */
+int I2C_SetTimeout(mxc_i2c_regs_t *i2c, int us);
+
+/**
+ * @brief      clear and disable timeout
+ *
+ * @param      i2c   pointer to I2C regs
+ */
+void I2C_ClearTimeout(mxc_i2c_regs_t *i2c);
+
+/**@} end of group i2c */
+#endif /* _I2C_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/i2s.h

@@ -0,0 +1,179 @@
+/**
+ * @file    i2s.h
+ * @brief   I2S (Inter-Integrated Sound) driver function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ *************************************************************************** */
+
+#ifndef _I2S_H_
+#define _I2S_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "dma.h"
+#include "spimss_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup i2s Inter-Integrated Sound (I2S)
+ * @ingroup spi
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/** @brief I2S audio directions */
+typedef enum {
+    AUDIO_OUT = 1,
+    AUDIO_IN = 2,
+} i2s_direction_t;
+
+/** @brief I2S Configuration Struct */
+typedef struct {
+    uint8_t                     left_justify;
+    uint8_t                     mono_audio;
+    i2s_direction_t             audio_direction;
+    unsigned int                sample_rate;
+    unsigned int                start_immediately;
+    void                        *dma_src_addr;
+    void                        *dma_dst_addr;
+    unsigned int                dma_cnt;
+    unsigned int                dma_reload_en;
+} i2s_cfg_t;
+  
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Initialize I2S resources 
+ * @param      cfg          I2S Configuration Struct
+ * @param      dma_ctz_cb   Optional function to be called when the DMA completes 
+                            a transfer. Set to NULL if unused.
+ * @param      sys_cfg_i2s  System configuration object
+ * @details    This initialization is required before using the I2S driver functions.
+ * @return   \c #E_NO_ERROR if successful
+ */
+int I2S_Init(const i2s_cfg_t *cfg, void (*dma_ctz_cb)(int, int), const sys_cfg_i2s_t* sys_cfg_i2s);
+
+/**
+ * @brief      Release I2S
+ * @details    De-configures the I2S protocol and stops DMA request
+ * @return   \c #E_BAD_PARAM if DMA cannot be stopped, #E_NO_ERROR otherwise
+ */  
+int I2S_Shutdown(void);
+
+/**
+ * @brief      Mute I2S Output
+ * @details    Sets I2S data to zero, continues sending clock and accessing DMA
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_Mute(void);
+
+/**
+ * @brief      Unmute I2S Output
+ * @details    Restores I2S data
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_Unmute(void);
+
+/**
+ * @brief      Pause I2S Output
+ * @details    Similar to mute, but stops FIFO and DMA access, clocks continue
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_Pause(void);
+
+/**
+ * @brief      Unpause I2S Output
+ * @details    Similar to mute, but restarts FIFO and DMA access
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_Unpause(void);
+
+/**
+ * @brief      Stops I2S Output
+ * @details    Similar to pause, but also halts clock
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_Stop(void);
+
+/**
+ * @brief      Starts I2S Output
+ * @details    Starts I2S Output, automatically called by configure if requested
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_Start(void);
+
+/**
+ * @brief      Clears DMA Interrupt Flags
+ * @details    Clears the DMA Interrupt flags, should be called at the end of a dma_ctz_cb
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_DMA_ClearFlags(void);
+
+/**
+ * @brief      Set DMA Addr (Source or Dest) and bytes to transfer
+ * @param      src_addr The address to read data from (Audio Out)
+ * @param      dst_addr The address to write data to (Audio In)    
+ * @param      count    The length of the transfer in bytes
+ * @details    Sets the address to read/write data in memory and the length of
+ *             the transfer. The unused addr parameter is ignored.
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count);
+
+/**
+ * @brief      Sets the DMA reload address and count
+ * @param      src_addr The address to read data from (Audio Out)
+ * @param      dst_addr The address to write data to (Audio In)    
+ * @param      count    The length of the transfer in bytes
+ * @details    If DMA reload is enabled, when the DMA has transfered $count bytes
+ *             (a CTZ event occurs) the src, dst, and count registers will be 
+ *             set to these. The DMA reload flag clears after a reload occurs.
+ * @return   \c #E_NO_ERROR
+ */  
+int I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count);
+/**@} end of group i2s */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _I2S_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/icc.h

@@ -0,0 +1,97 @@
+/**
+ * @file    icc.h
+ * @brief   Instruction Controller Cache(ICC) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
+ * $Revision: 40072 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _ICC_H_
+#define _ICC_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+#include "icc_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup icc Internal Cache Controller (ICC)
+ * @ingroup periphlibs
+ * @{
+ */ 
+
+/**
+ * @brief Enumeration type for the Cache ID Register
+ */
+typedef enum {
+    ICC_CACHE_ID_RELNUM,	// Identifies the RTL release version
+    ICC_CACHE_ID_PARTNUM,	// Specifies the value of C_ID Port Number
+    ICC_CACHE_ID_CCHID		// Specifies the value of Cache ID
+} icc_cache_id_t;
+
+/**
+ * @brief	Reads the data from the Cache Id Register.
+ * @param	cid	Enumeration type for Cache Id Register.
+ * @retval	Returns the contents of Cache Id Register. 
+ */
+int ICC_ID(icc_cache_id_t cid);
+
+/**
+ * @brief	Enable the instruction cache controller.
+ */
+void ICC_Enable(void);
+
+/**
+ * @brief	Disable the instruction cache controller.
+ */
+void ICC_Disable(void);
+
+/**
+ * @brief	Flush the instruction cache controller.
+ */
+void ICC_Flush(void);
+
+/**@} end of group icc */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ICC_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/lp.h

@@ -0,0 +1,341 @@
+/**
+ * @file    lp.h
+ * @brief   Low power function prototypes and data types.
+ */
+
+
+/* ****************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-09-26 08:48:30 -0500 (Wed, 26 Sep 2018) $
+ * $Revision: 38105 $
+ *
+ *************************************************************************** */
+ 
+// Define to prevent redundant inclusion 
+#ifndef _LP_H_
+#define _LP_H_
+
+/***** Includes *****/
+#include "gpio.h"
+#include "pwrseq_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */
+typedef enum {
+    LP_OVR_0_9       = MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V,         /**< Reset DMA */
+    LP_OVR_1_0       = MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V,         /**< Reset DMA */
+    LP_OVR_1_1       = MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V,         /**< Reset DMA */
+} lp_ovr_t;
+
+/**
+ * @brief 	   Clears the low power wakeup flags
+ */	
+void LP_ClearWakeStatus(void);
+
+/**
+ * @brief      Enables power to RAM addresses 0x20010000-0x20017FFF.
+ */
+void LP_EnableSRAM3(void);
+
+/**
+ * @brief      Enables power to RAM addresses 0x20008000-0x2000FFFF.
+ */
+void LP_EnableSRAM2(void);
+
+/**
+ * @brief      Enables power to RAM addresses 0x20004000-0x20007FFF.
+ */
+void LP_EnableSRAM1(void);
+
+/**
+ * @brief      Enables power to RAM addresses 0x20000000-0x20003FFF.
+ */
+void LP_EnableSRAM0(void);
+
+/**
+ * @brief      Disables power to RAM addresses 0x20010000-0x20017FFF. The contents of the RAM are destroyed.
+ */
+void LP_DisableSRAM3(void);
+
+/**
+ * @brief      Disables power to RAM addresses 0x20008000-0x2000FFFF. The contents of the RAM are destroyed.
+ */
+void LP_DisableSRAM2(void);
+
+/**
+ * @brief      Disables power to RAM addresses 0x20004000-0x20007FFF. The contents of the RAM are destroyed.
+ */
+void LP_DisableSRAM1(void);
+
+/**
+ * @brief      Disables power to RAM addresses 0x20000000-0x20003FFF. The contents of the RAM are destroyed.
+ */
+void LP_DisableSRAM0(void);
+
+/**
+ * @brief      Places the instruction cache in light sleep mode. Data will be unavailable for read/write operations but will be retained.
+ */
+void LP_EnableICacheLightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20010000 to 0x20017FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
+ */
+void LP_EnableSysRAM3LightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20008000 to 0x2000FFFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
+ */
+void LP_EnableSysRAM2LightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20004000 to 0x20007FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
+ */
+void LP_EnableSysRAM1LightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20000000 to 0x20003FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
+ */
+void LP_EnableSysRAM0LightSleep(void);
+
+/**
+ * @brief      Places the instruction cache in active mode.
+ */
+void LP_DisableICacheLightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20010000 to 0x20017FFF of the RAM in active mode.
+ */
+void LP_DisableSysRAM3LightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20008000 to 0x2000FFFF of the RAM in active mode.
+ */
+void LP_DisableSysRAM2LightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20004000 to 0x20007FFF of the RAM in active mode.
+ */
+void LP_DisableSysRAM1LightSleep(void);
+
+/**
+ * @brief      Places addresses 0x20000000 to 0x20003FFF of the RAM in active mode.
+ */
+void LP_DisableSysRAM0LightSleep(void);
+
+/**
+ * @brief      Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.  
+ *             Call this function multiple times to enable pins on multiple ports.  This function does not configure
+ *             the GPIO pins nor does it setup their interrupt functionality.
+ * @param      wu_pins      The port and pins to configure as wakeup sources.  Only the gpio and mask fields of the
+ *                          structure are used.  The func and pad fields are ignored.
+ */
+void LP_EnableGPIOWakeup(const gpio_cfg_t *wu_pins);
+
+/**
+ * @brief      Disables the selected GPIO port and its selected pins as a wake up source.  
+ *             Call this function multiple times to disable pins on multiple ports.
+ * @param      wu_pins      The port and pins to disable as wakeup sources.  Only the gpio and mask fields of the
+ *                          structure are used.  The func and pad fields are ignored.
+ */
+void LP_DisableGPIOWakeup(const gpio_cfg_t *wu_pins);
+
+/**
+ * @brief      Enables the RTC alarm to wake up the device from any low power mode.  
+ */
+void LP_EnableRTCAlarmWakeup(void);
+
+/**
+ * @brief      Disables the RTC alarm from waking up the device.  
+ */
+void LP_DisableRTCAlarmWakeup(void);
+
+/**
+ * @brief      Places the device into SLEEP mode.  This function returns once any interrupt occurs. 
+ * @note 	   LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
+ */
+void LP_EnterSleepMode(void);
+
+/**
+ * @brief      Places the device into DEEPSLEEP mode.  This function returns once an RTC or external interrupt occur. 
+ * @note      LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
+*/
+void LP_EnterDeepSleepMode(void);
+
+/**
+ * @brief      Places the device into BACKUP mode.  CPU state is not maintained in this mode, so this function never returns.  
+ *             Instead, the device will restart once an RTC or external interrupt occur. 
+ * @note       LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
+ */
+void LP_EnterBackupMode(void);
+
+/**
+ * @brief      Places the device into Shutdown mode.  CPU state is not maintained in this mode, so this function never returns.  
+ *             Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur. 
+ */
+void LP_EnterShutDownMode(void);
+
+/**
+ * @brief      Set operating voltage and change the clock to match the new voltage. 
+ * @param	   system reset configuration struct
+ */
+void LP_SetOperatingVoltage(lp_ovr_t ovr);
+
+/**
+ * @brief      Enables Data Retention to RAM addresses 0x20000000-0x20003FFF.
+ */
+void LP_EnableSRamRet0(void);
+
+/**
+ * @brief      Disables Data Retention to RAM addresses 0x20000000-0x20003FFF. 
+ */
+void LP_DisableSRamRet0(void);
+
+/**
+ * @brief      Enables Data Retention to RAM addresses 0x20004000-0x20007FFF.
+ */
+void LP_EnableSRamRet1(void);
+
+/**
+ * @brief      Disables Data Retention to RAM addresses 0x20004000-0x20007FFF.
+ */
+void LP_DisableSRamRet1(void);
+
+/**
+ * @brief      Enables Data Retention to RAM addresses 0x20008000-0x2000FFFF.
+ */
+void LP_EnableSRamRet2(void);
+
+/**
+ * @brief      Disables Data Retention to RAM addresses 0x20008000-0x2000FFFF.
+ */
+void LP_DisableSRamRet2(void);
+
+/**
+ * @brief      Enables Data Retention to RAM addresses 0x20010000-0x20017FFF.
+ */
+void LP_EnableSRamRet3(void);
+
+/**
+ * @brief      Disables Data Retention to RAM addresses 0x20010000-0x20017FFF.
+ */
+void LP_DisableSRamRet3(void);
+
+/**
+ * @brief      Enables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time.
+ */
+void LP_EnableBlockDetect(void);
+
+/**
+ * @brief      Disables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time
+ */
+void LP_DisableBlockDetect(void);
+
+/**
+ * @brief      RAM Retention Regulator Enable for BACKUP Mode
+ */
+void LP_EnableRamRetReg(void);
+
+/**
+ * @brief      RAM Retention Regulator Disabels for BACKUP Mode
+ */
+void LP_DisableRamRetReg(void);
+
+/**
+ * @brief      Enables Fast wake up from deepsleep 
+ */
+void LP_EnableFastWk(void);
+
+/**
+ * @brief      Disables Fast wake up from deepsleep
+ */
+void LP_DisableFastWk(void);
+
+/**
+ * @brief      Turns on band gap during deepsleep and backup mode. 
+ */
+void LP_EnableBandGap(void);
+
+/**
+ * @brief      Turns off band gap during deepsleep and backup mode.
+ */
+void LP_DisableBandGap(void);
+
+/**
+ * @brief     Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
+ */
+void LP_EnableVCorePORSignal(void);
+
+/**
+ * @brief     Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode 
+ */
+void LP_DisableVCorePORSignal(void);
+
+/**
+ * @brief     Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
+ */
+void LP_EnableLDO(void);
+
+/**
+ * @brief     Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode 
+ */
+void LP_DisableLDO(void);
+
+/**
+ * @brief     Enables V CORE Supply Voltage Monitor 
+ */
+void LP_EnableVCoreSVM(void);
+
+/**
+ * @brief     Disables V CORE Supply Voltage Monitor 
+ */
+void LP_DisableVCoreSVM(void);
+
+
+/**
+ * @brief     Enables VDDIO Power-On-Reset Monitor 
+ */
+void LP_EnableVDDIOPorMonitor(void);
+
+/**
+ * @brief     Disables VDDIO Power-On-Reset Monitor  
+ */
+void LP_DisableVDDIOPorMonitor(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LP_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/mxc_assert.h

@@ -0,0 +1,113 @@
+/**
+ * @file
+ * @brief      Assertion checks for debugging.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $ 
+ * $Revision: 36818 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_ASSERT_H_
+#define _MXC_ASSERT_H_
+
+/* **** Includes **** */
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup    syscfg
+ * @defgroup   mxc_assertions Assertion Checks for Debugging
+ * @brief      Assertion checks for debugging.
+ * @{
+ */ 
+/* **** Definitions **** */
+/**
+ * @note       To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ *             defined. 
+ */
+///@cond
+#ifdef MXC_ASSERT_ENABLE
+/**
+ * Macro that checks the expression for true and generates an assertion.
+ * @note       To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ *             defined.
+ */
+#define MXC_ASSERT(expr)                                \
+if (!(expr))                                            \
+{                                                       \
+    mxc_assert(#expr, __FILE__, __LINE__);              \
+}
+/**
+ * Macro that generates an assertion with the message "FAIL".
+ * @note       To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ *             defined.
+ */
+#define MXC_ASSERT_FAIL() mxc_assert("FAIL", __FILE__, __LINE__);
+#else
+#define MXC_ASSERT(expr)
+#define MXC_ASSERT_FAIL()
+#endif
+///@endcond
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief      Assert an error when the given expression fails during debugging.
+ * @param      expr  String with the expression that failed the assertion.
+ * @param      file  File containing the failed assertion.
+ * @param      line  Line number for the failed assertion.
+ * @note       This is defined as a weak function and can be overridden at the
+ *             application layer to print the debugging information. 
+ *             @code 
+ *             printf("%s, file: %s, line %d\n", expr, file, line);
+ *             @endcode
+ * @note       To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ *             defined. 
+ */
+void mxc_assert(const char *expr, const char *file, int line);
+
+/**@} end of group MXC_Assertions*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_ASSERT_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/mxc_config.h

@@ -0,0 +1,53 @@
+/**
+ * @file       mxc_config.h
+ * @brief      Top-level include file for device configuration.
+ */
+ 
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
+ * $Revision: 36818 $
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_CONFIG_H
+#define _MXC_CONFIG_H
+
+#if !defined __GNUC__
+#include "RTE_Components.h"
+#endif /* not __GNUC__ */
+
+#include "mxc_device.h"
+#include "mxc_errors.h"
+#include "mxc_pins.h"
+
+#endif /* _CONFIG_H */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/mxc_delay.h

@@ -0,0 +1,124 @@
+/**
+ * @file
+ * @brief    Asynchronous delay routines based on the SysTick Timer.
+*/
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-11-05 09:52:05 -0600 (Mon, 05 Nov 2018) $ 
+ * $Revision: 38934 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _DELAY_H_
+#define _DELAY_H_
+
+/**
+ * @defgroup    MXC_delay Delay Utility Functions 
+ * @ingroup     devicelibs 
+ * @brief       Asynchronous delay routines based on the SysTick Timer
+ * @{
+ */ 
+
+/***** Definitions *****/
+/**
+ * Macro used to specify a microsecond timing parameter in seconds.
+ * \code
+ * x = SEC(3) // 3 seconds -> x = 3,000,000 
+ * \endcode
+ */
+#define MXC_DELAY_SEC(s)            (((unsigned long)s) * 1000000UL)  
+/**
+ * Macro used to specify a microsecond timing parameter in milliseconds.
+ * \code
+ * x = MSEC(3) // 3ms -> x = 3,000
+ * \endcode
+ */
+#define MXC_DELAY_MSEC(ms)          (ms * 1000UL)
+/**
+ * Macro used to specify a microsecond timing parameter.
+ * \code
+ * x = USEC(3) // 3us -> x = 3
+ * \endcode
+ */
+#define MXC_DELAY_USEC(us)          (us)
+
+/***** Function Prototypes *****/
+
+/**
+ * @brief      Blocks and delays for the specified number of microseconds.
+ * @details    Uses the SysTick to create the requested delay. If the SysTick is
+ *             running, the current settings will be used. If the SysTick is not
+ *             running, it will be started.
+ * @param      us    microseconds to delay
+ * @return     #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int mxc_delay(unsigned long us);
+
+/**
+ * @brief      Starts a non-blocking delay for the specified number of
+ *             microseconds.
+ * @details    Uses the SysTick to time the requested delay. If the SysTick is
+ *             running, the current settings will be used. If the SysTick is not
+ *             running, it will be started.
+ * @note       mxc_delay_handler() must be called from the SysTick interrupt service
+ *             routine or at a rate greater than the SysTick overflow rate.
+ * @param      us    microseconds to delay
+ * @return     #E_NO_ERROR if no errors, #E_BUSY if currently servicing another
+ *             delay request.
+ */
+int mxc_delay_start(unsigned long us);
+
+/**
+ * @brief      Returns the status of a non-blocking delay request
+ * @pre        Start the asynchronous delay by calling mxc_delay_start().
+ * @return     #E_BUSY until the requested delay time has expired.
+ */
+int mxc_delay_check(void);
+
+/**
+ * @brief      Stops an asynchronous delay previously started.
+ * @pre        Start the asynchronous delay by calling mxc_delay_start().
+ */
+void mxc_delay_stop(void);
+
+/**
+ * @brief      Processes the delay interrupt.
+ * @details    This function must be called from the SysTick IRQ or polled at a
+ *             rate greater than the SysTick overflow rate.
+ */
+void mxc_delay_handler(void);
+
+/**@} end of group MXC_delay */
+
+#endif /* _DELAY_H_ */

bsp/maxim/libraries/MAX32660PeriphDriver/Include/mxc_errors.h

@@ -0,0 +1,94 @@
+/**
+ * @file
+ * @brief    List of common error return codes for Maxim Integrated libraries. 
+*/
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $ 
+ * $Revision: 36818 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_ERRORS_H_
+#define _MXC_ERRORS_H_
+
+/**
+ * @ingroup syscfg
+ * @defgroup MXC_Error_Codes Error Codes
+ * @brief      A list of common error codes used by the API.
+ * @note       A Negative Error Convention is used to avoid conflict with
+ *             positive, Non-Error, returns. 
+ * @{
+ */ 
+
+/** No Error */
+#define		E_NO_ERROR		0
+/** No Error, success */
+#define		E_SUCCESS		0
+/** Pointer is NULL */ 
+#define		E_NULL_PTR		-1
+/** No such device */
+#define		E_NO_DEVICE		-2
+/** Parameter not acceptable */
+#define		E_BAD_PARAM		-3
+/** Value not valid or allowed */
+#define		E_INVALID		-4
+/** Module not initialized */
+#define		E_UNINITIALIZED	-5
+/** Busy now, try again later */
+#define		E_BUSY			-6
+/** Operation not allowed in current state */
+#define		E_BAD_STATE		-7
+/** Generic error */
+#define		E_UNKNOWN		-8
+/** General communications error */
+#define		E_COMM_ERR		-9
+/** Operation timed out */
+#define		E_TIME_OUT		-10
+/** Expected response did not occur */
+#define		E_NO_RESPONSE	-11
+/** Operations resulted in unexpected overflow */
+#define		E_OVERFLOW		-12
+/** Operations resulted in unexpected underflow */
+#define     E_UNDERFLOW     -13
+/** Data or resource not available at this time */
+#define		E_NONE_AVAIL	-14
+/** Event was shutdown */
+#define		E_SHUTDOWN		-15
+/** Event was aborted */
+#define     E_ABORT         -16
+/** The requested operation is not supported */
+#define		E_NOT_SUPPORTED	-17
+/**@} end of MXC_Error_Codes group */
+ 
+#endif /* _MXC_ERRORS_H_ */