drv_spi.c 7.3 KB

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  1. /*
  2. * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2019-03-19 wangyq the first version
  9. * 2019-11-01 wangyq update libraries
  10. */
  11. #include <rtthread.h>
  12. #include <rtdevice.h>
  13. #include <string.h>
  14. #include <rthw.h>
  15. #include "board.h"
  16. #include "drv_spi.h"
  17. #include <ald_spi.h>
  18. #include <ald_gpio.h>
  19. #include <ald_cmu.h>
  20. #ifdef RT_USING_SPI
  21. #define SPITIMEOUT 0x0FFF
  22. rt_err_t spi_configure(struct rt_spi_device *device,
  23. struct rt_spi_configuration *cfg)
  24. {
  25. spi_handle_t *hspi;
  26. hspi = (spi_handle_t *)device->bus->parent.user_data;
  27. /* config spi mode */
  28. if (cfg->mode & RT_SPI_SLAVE)
  29. {
  30. hspi->init.mode = SPI_MODE_SLAVER;
  31. }
  32. else
  33. {
  34. hspi->init.mode = SPI_MODE_MASTER;
  35. }
  36. if (cfg->mode & RT_SPI_3WIRE)
  37. {
  38. hspi->init.dir = SPI_DIRECTION_1LINE;
  39. }
  40. else
  41. {
  42. hspi->init.dir = SPI_DIRECTION_2LINES;
  43. }
  44. if (cfg->data_width == 8)
  45. {
  46. hspi->init.data_size = SPI_DATA_SIZE_8;
  47. }
  48. else if (cfg->data_width == 16)
  49. {
  50. hspi->init.data_size = SPI_DATA_SIZE_16;
  51. }
  52. if (cfg->mode & RT_SPI_CPHA)
  53. {
  54. hspi->init.phase = SPI_CPHA_SECOND;
  55. }
  56. else
  57. {
  58. hspi->init.phase = SPI_CPHA_FIRST;
  59. }
  60. if (cfg->mode & RT_SPI_CPOL)
  61. {
  62. hspi->init.polarity = SPI_CPOL_HIGH;
  63. }
  64. else
  65. {
  66. hspi->init.polarity = SPI_CPOL_LOW;
  67. }
  68. if (cfg->mode & RT_SPI_NO_CS)
  69. {
  70. hspi->init.ss_en = DISABLE;
  71. }
  72. else
  73. {
  74. hspi->init.ss_en = ENABLE;
  75. }
  76. /* config spi clock */
  77. if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 2)
  78. {
  79. /* pclk1 max speed 48MHz, spi master max speed 10MHz */
  80. if (ald_cmu_get_pclk1_clock() / 2 <= 10000000)
  81. {
  82. hspi->init.baud = SPI_BAUD_2;
  83. }
  84. else if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
  85. {
  86. hspi->init.baud = SPI_BAUD_4;
  87. }
  88. else
  89. {
  90. hspi->init.baud = SPI_BAUD_8;
  91. }
  92. }
  93. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 4)
  94. {
  95. /* pclk1 max speed 48MHz, spi master max speed 10MHz */
  96. if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
  97. {
  98. hspi->init.baud = SPI_BAUD_4;
  99. }
  100. else
  101. {
  102. hspi->init.baud = SPI_BAUD_8;
  103. }
  104. }
  105. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 8)
  106. {
  107. hspi->init.baud = SPI_BAUD_8;
  108. }
  109. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 16)
  110. {
  111. hspi->init.baud = SPI_BAUD_16;
  112. }
  113. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 32)
  114. {
  115. hspi->init.baud = SPI_BAUD_32;
  116. }
  117. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 64)
  118. {
  119. hspi->init.baud = SPI_BAUD_64;
  120. }
  121. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 128)
  122. {
  123. hspi->init.baud = SPI_BAUD_128;
  124. }
  125. else
  126. {
  127. hspi->init.baud = SPI_BAUD_256;
  128. }
  129. ald_spi_init(hspi);
  130. return RT_EOK;
  131. }
  132. static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  133. {
  134. rt_err_t res;
  135. spi_handle_t *hspi;
  136. struct es32f0_hw_spi_cs *cs;
  137. RT_ASSERT(device != RT_NULL);
  138. RT_ASSERT(device->bus != RT_NULL);
  139. RT_ASSERT(device->bus->parent.user_data != RT_NULL);
  140. RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
  141. hspi = (spi_handle_t *)device->bus->parent.user_data;
  142. cs = device->parent.user_data;
  143. /* only send data */
  144. if (message->recv_buf == RT_NULL)
  145. {
  146. if (message->cs_take)
  147. {
  148. rt_pin_write(cs->pin, 0);
  149. }
  150. res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
  151. if (message->cs_release)
  152. {
  153. rt_pin_write(cs->pin, 1);
  154. }
  155. if (res != RT_EOK)
  156. return RT_ERROR;
  157. }
  158. /* only receive data */
  159. if (message->send_buf == RT_NULL)
  160. {
  161. if (message->cs_take)
  162. {
  163. rt_pin_write(cs->pin, 0);
  164. }
  165. res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
  166. if (message->cs_release)
  167. {
  168. rt_pin_write(cs->pin, 1);
  169. }
  170. if (res != RT_EOK)
  171. return RT_ERROR;
  172. }
  173. /* send & receive */
  174. else
  175. {
  176. if (message->cs_take)
  177. {
  178. rt_pin_write(cs->pin, 0);
  179. }
  180. res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
  181. (rt_int32_t)message->length, SPITIMEOUT);
  182. if (message->cs_release)
  183. {
  184. rt_pin_write(cs->pin, 1);
  185. }
  186. if (res != RT_EOK)
  187. return RT_ERROR;
  188. }
  189. return message->length;
  190. }
  191. const struct rt_spi_ops es32f0_spi_ops =
  192. {
  193. spi_configure,
  194. spixfer,
  195. };
  196. static struct rt_spi_bus _spi_bus0, _spi_bus1;
  197. static spi_handle_t _spi0, _spi1;
  198. int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
  199. {
  200. struct rt_spi_bus *spi_bus;
  201. spi_handle_t *spi;
  202. gpio_init_t gpio_instruct;
  203. if (SPIx == SPI0)
  204. {
  205. _spi0.perh = SPI0;
  206. spi_bus = &_spi_bus0;
  207. spi = &_spi0;
  208. /* SPI0 gpio init */
  209. gpio_instruct.mode = GPIO_MODE_OUTPUT;
  210. gpio_instruct.odos = GPIO_PUSH_PULL;
  211. gpio_instruct.func = GPIO_FUNC_4;
  212. gpio_instruct.type = GPIO_TYPE_CMOS;
  213. gpio_instruct.flt = GPIO_FILTER_DISABLE;
  214. /* PB3->SPI0_SCK, PB5->SPI0_MOSI */
  215. ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
  216. /* PB4->SPI0_MISO */
  217. gpio_instruct.mode = GPIO_MODE_INPUT;
  218. ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
  219. }
  220. else if (SPIx == SPI1)
  221. {
  222. _spi1.perh = SPI1;
  223. spi_bus = &_spi_bus1;
  224. spi = &_spi1;
  225. /* SPI1 gpio init */
  226. gpio_instruct.mode = GPIO_MODE_OUTPUT;
  227. gpio_instruct.odos = GPIO_PUSH_PULL;
  228. gpio_instruct.func = GPIO_FUNC_4;
  229. gpio_instruct.type = GPIO_TYPE_CMOS;
  230. gpio_instruct.flt = GPIO_FILTER_DISABLE;
  231. /* PB13->SPI1_SCK, PB15->SPI1_MOSI */
  232. ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct);
  233. /* PB14->SPI1_MISO */
  234. gpio_instruct.mode = GPIO_MODE_INPUT;
  235. ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct);
  236. }
  237. else
  238. {
  239. return -1;
  240. }
  241. spi_bus->parent.user_data = spi;
  242. return rt_spi_bus_register(spi_bus, name, &es32f0_spi_ops);
  243. }
  244. rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name)
  245. {
  246. /* define spi Instance */
  247. struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  248. RT_ASSERT(spi_device != RT_NULL);
  249. struct es32f0_hw_spi_cs *cs_pin = (struct es32f0_hw_spi_cs *)rt_malloc(sizeof(struct es32f0_hw_spi_cs));
  250. RT_ASSERT(cs_pin != RT_NULL);
  251. cs_pin->pin = pin;
  252. rt_pin_mode(pin, PIN_MODE_OUTPUT);
  253. rt_pin_write(pin, 1);
  254. return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
  255. }
  256. int rt_hw_spi_init(void)
  257. {
  258. int result = 0;
  259. #ifdef BSP_USING_SPI0
  260. result = es32f0_spi_register_bus(SPI0, "spi0");
  261. #endif
  262. #ifdef BSP_USING_SPI1
  263. result = es32f0_spi_register_bus(SPI1, "spi1");
  264. #endif
  265. return result;
  266. }
  267. INIT_BOARD_EXPORT(rt_hw_spi_init);
  268. #endif