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@@ -1,382 +1,381 @@
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-/**************************************************************************/
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-/*!
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- @file dcd_lpc43xx.c
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- @author hathach (tinyusb.org)
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-
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- @section LICENSE
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-
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- Software License Agreement (BSD License)
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-
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- Copyright (c) 2013, hathach (tinyusb.org)
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- All rights reserved.
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-
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- Redistribution and use in source and binary forms, with or without
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- modification, are permitted provided that the following conditions are met:
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- 1. Redistributions of source code must retain the above copyright
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- notice, this list of conditions and the following disclaimer.
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- 2. Redistributions in binary form must reproduce the above copyright
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- notice, this list of conditions and the following disclaimer in the
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- documentation and/or other materials provided with the distribution.
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- 3. Neither the name of the copyright holders nor the
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- names of its contributors may be used to endorse or promote products
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- derived from this software without specific prior written permission.
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-
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- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
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- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
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- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-
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- This file is part of the tinyusb stack.
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-*/
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-/**************************************************************************/
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-
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-#include "tusb_option.h"
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-
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-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_LPC43XX
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-
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-//--------------------------------------------------------------------+
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-// INCLUDE
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-//--------------------------------------------------------------------+
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-#include "common/tusb_common.h"
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-#include "tusb_hal.h"
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-
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-#include "device/dcd.h"
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-#include "dcd_lpc43xx.h"
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-
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-#include "chip.h"
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-
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-//--------------------------------------------------------------------+
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-// MACRO CONSTANT TYPEDEF
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-//--------------------------------------------------------------------+
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-typedef struct {
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- dcd_qhd_t qhd[DCD_QHD_MAX] ATTR_ALIGNED(64); ///< Must be at 2K alignment
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- dcd_qtd_t qtd[DCD_QTD_MAX] ATTR_ALIGNED(32);
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-}dcd_data_t;
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-
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-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
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-CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data0;
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-#endif
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-
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-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
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-CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data1;
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-#endif
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-
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-static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
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-
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-static dcd_data_t* const dcd_data_ptr[2] =
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-{
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-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
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- &dcd_data0,
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-#else
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- NULL,
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-#endif
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-
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-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
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- &dcd_data1
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-#else
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- NULL
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-#endif
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-};
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-
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-//--------------------------------------------------------------------+
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-// CONTROLLER API
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-//--------------------------------------------------------------------+
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-void dcd_connect(uint8_t rhport)
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-{
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- LPC_USB[rhport]->USBCMD_D |= BIT_(0);
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-}
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-
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-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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-{
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- LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | BIT_(24);
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-}
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-
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-void dcd_set_config(uint8_t rhport, uint8_t config_num)
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-{
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- // nothing to do
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-}
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-
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-/// follows LPC43xx User Manual 23.10.3
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-static void bus_reset(uint8_t rhport)
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-{
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- LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
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-
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- // The reset value for all endpoint types is the control endpoint. If one endpoint
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- // direction is enabled and the paired endpoint of opposite direction is disabled, then the
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- // endpoint type of the unused direction must bechanged from the control type to any other
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- // type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
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- // for the data PID tracking on the active endpoint.
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-
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- // USB0 has 5 but USB1 only has 3 non-control endpoints
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- for( int i=1; i < (rhport ? 6 : 4); i++)
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- {
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- lpc_usb->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
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- }
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-
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- //------------- Clear All Registers -------------//
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- lpc_usb->ENDPTNAK = lpc_usb->ENDPTNAK;
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- lpc_usb->ENDPTNAKEN = 0;
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- lpc_usb->USBSTS_D = lpc_usb->USBSTS_D;
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- lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;
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- lpc_usb->ENDPTCOMPLETE = lpc_usb->ENDPTCOMPLETE;
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-
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- while (lpc_usb->ENDPTPRIME);
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- lpc_usb->ENDPTFLUSH = 0xFFFFFFFF;
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- while (lpc_usb->ENDPTFLUSH);
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-
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- // read reset bit in portsc
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-
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- //------------- Queue Head & Queue TD -------------//
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- dcd_data_t* p_dcd = dcd_data_ptr[rhport];
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-
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- tu_memclr(p_dcd, sizeof(dcd_data_t));
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-
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- //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
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- p_dcd->qhd[0].zero_length_termination = p_dcd->qhd[1].zero_length_termination = 1;
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- p_dcd->qhd[0].max_package_size = p_dcd->qhd[1].max_package_size = CFG_TUD_ENDOINT0_SIZE;
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- p_dcd->qhd[0].qtd_overlay.next = p_dcd->qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
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-
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- p_dcd->qhd[0].int_on_setup = 1; // OUT only
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-}
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-
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-bool dcd_init(uint8_t rhport)
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-{
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- LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
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- dcd_data_t* p_dcd = dcd_data_ptr[rhport];
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-
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- tu_memclr(p_dcd, sizeof(dcd_data_t));
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-
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- lpc_usb->ENDPOINTLISTADDR = (uint32_t) p_dcd->qhd; // Endpoint List Address has to be 2K alignment
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- lpc_usb->USBSTS_D = lpc_usb->USBSTS_D;
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- lpc_usb->USBINTR_D = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
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-
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- lpc_usb->USBCMD_D &= ~0x00FF0000; // Interrupt Threshold Interval = 0
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- lpc_usb->USBCMD_D |= BIT_(0); // connect
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-
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- // enable interrupt
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- NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
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-
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- return true;
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-}
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-
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-//--------------------------------------------------------------------+
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-// HELPER
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-//--------------------------------------------------------------------+
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-// index to bit position in register
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-static inline uint8_t ep_idx2bit(uint8_t ep_idx)
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-{
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- return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
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-}
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-
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-static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
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-{
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- tu_memclr(p_qtd, sizeof(dcd_qtd_t));
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-
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- p_qtd->next = QTD_NEXT_INVALID;
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- p_qtd->active = 1;
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- p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
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-
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- if (data_ptr != NULL)
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- {
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- p_qtd->buffer[0] = (uint32_t) data_ptr;
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- for(uint8_t i=1; i<5; i++)
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- {
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- p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
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- }
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- }
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-}
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-
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-//--------------------------------------------------------------------+
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-// DCD Endpoint Port
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-//--------------------------------------------------------------------+
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-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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-{
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- uint8_t const epnum = edpt_number(ep_addr);
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- uint8_t const dir = edpt_dir(ep_addr);
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-
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- if ( epnum == 0)
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- {
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- // Stall both Control IN and OUT
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- LPC_USB[rhport]->ENDPTCTRL[epnum] |= ( (ENDPTCTRL_MASK_STALL << 16) || (ENDPTCTRL_MASK_STALL << 0) );
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- }else
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- {
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- LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (dir ? 16 : 0);
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- }
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-}
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-
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-bool dcd_edpt_stalled (uint8_t rhport, uint8_t ep_addr)
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-{
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- uint8_t const epnum = edpt_number(ep_addr);
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- uint8_t const dir = edpt_dir(ep_addr);
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-
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- return LPC_USB[rhport]->ENDPTCTRL[epnum] & (ENDPTCTRL_MASK_STALL << (dir ? 16 : 0));
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-}
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-
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-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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-{
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- uint8_t const epnum = edpt_number(ep_addr);
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- uint8_t const dir = edpt_dir(ep_addr);
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-
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- // data toggle also need to be reset
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- LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ( dir ? 16 : 0 );
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- LPC_USB[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ( dir ? 16 : 0));
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-}
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-
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-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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-{
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- // TODO USB1 only has 4 non-control enpoint (USB0 has 5)
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- // TODO not support ISO yet
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- TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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-
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- uint8_t const epnum = edpt_number(p_endpoint_desc->bEndpointAddress);
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- uint8_t const dir = edpt_dir(p_endpoint_desc->bEndpointAddress);
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- uint8_t const ep_idx = 2*epnum + dir;
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-
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- //------------- Prepare Queue Head -------------//
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- dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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- tu_memclr(p_qhd, sizeof(dcd_qhd_t));
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-
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- p_qhd->zero_length_termination = 1;
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- p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
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- p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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-
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- // Enable EP Control
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- LPC_USB[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
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-
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- return true;
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-}
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-
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-bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
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-{
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- uint8_t const epnum = edpt_number(ep_addr);
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- uint8_t const dir = edpt_dir(ep_addr);
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- uint8_t const ep_idx = 2*epnum + dir;
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-
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- dcd_qhd_t const * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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- dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
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-
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- return p_qtd->active;
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-// return !p_qhd->qtd_overlay.halted && p_qhd->qtd_overlay.active;
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-}
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-
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-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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-{
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- uint8_t const epnum = edpt_number(ep_addr);
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- uint8_t const dir = edpt_dir(ep_addr);
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- uint8_t const ep_idx = 2*epnum + dir;
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-
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- if ( epnum == 0 )
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- {
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- // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
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- // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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- while(LPC_USB[rhport]->ENDPTSETUPSTAT & BIT_(0)) {}
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- }
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-
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- dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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- dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
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-
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- //------------- Prepare qtd -------------//
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- qtd_init(p_qtd, buffer, total_bytes);
|
|
|
|
|
- p_qtd->int_on_complete = true;
|
|
|
|
|
- p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
|
|
|
|
|
-
|
|
|
|
|
- // start transfer
|
|
|
|
|
- LPC_USB[rhport]->ENDPTPRIME = BIT_( ep_idx2bit(ep_idx) ) ;
|
|
|
|
|
-
|
|
|
|
|
- return true;
|
|
|
|
|
-}
|
|
|
|
|
-
|
|
|
|
|
-//--------------------------------------------------------------------+
|
|
|
|
|
-// ISR
|
|
|
|
|
-//--------------------------------------------------------------------+
|
|
|
|
|
-void hal_dcd_isr(uint8_t rhport)
|
|
|
|
|
-{
|
|
|
|
|
- LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
|
|
|
|
|
-
|
|
|
|
|
- uint32_t const int_enable = lpc_usb->USBINTR_D;
|
|
|
|
|
- uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
|
|
|
|
|
- lpc_usb->USBSTS_D = int_status; // Acknowledge handled interrupt
|
|
|
|
|
-
|
|
|
|
|
- if (int_status == 0) return;// disabled interrupt sources
|
|
|
|
|
-
|
|
|
|
|
-
|
|
|
|
|
- if (int_status & INT_MASK_RESET)
|
|
|
|
|
- {
|
|
|
|
|
- bus_reset(rhport);
|
|
|
|
|
- dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
|
|
|
|
|
- }
|
|
|
|
|
-
|
|
|
|
|
- if (int_status & INT_MASK_SUSPEND)
|
|
|
|
|
- {
|
|
|
|
|
- if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
|
|
|
|
|
- {
|
|
|
|
|
- // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
|
|
|
|
|
- if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
|
|
|
|
|
- {
|
|
|
|
|
- dcd_event_bus_signal(rhport, DCD_EVENT_SUSPENDED, true);
|
|
|
|
|
- }
|
|
|
|
|
- }
|
|
|
|
|
- }
|
|
|
|
|
-
|
|
|
|
|
- // TODO disconnection does not generate interrupt !!!!!!
|
|
|
|
|
-// if (int_status & INT_MASK_PORT_CHANGE)
|
|
|
|
|
-// {
|
|
|
|
|
-// if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
|
|
|
|
|
-// {
|
|
|
|
|
-// dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
|
|
|
|
|
-// dcd_event_handler(&event, true);
|
|
|
|
|
-// }
|
|
|
|
|
-// }
|
|
|
|
|
-
|
|
|
|
|
- if (int_status & INT_MASK_USB)
|
|
|
|
|
- {
|
|
|
|
|
- uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
|
|
|
|
|
- lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
|
|
|
|
|
-
|
|
|
|
|
- dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
|
|
|
|
|
-
|
|
|
|
|
- if (lpc_usb->ENDPTSETUPSTAT)
|
|
|
|
|
- {
|
|
|
|
|
- //------------- Set up Received -------------//
|
|
|
|
|
- // 23.10.10.2 Operational model for setup transfers
|
|
|
|
|
- lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
|
|
|
|
|
-
|
|
|
|
|
- dcd_event_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request, true);
|
|
|
|
|
- }
|
|
|
|
|
-
|
|
|
|
|
- if ( edpt_complete )
|
|
|
|
|
- {
|
|
|
|
|
- for(uint8_t ep_idx = 0; ep_idx < DCD_QHD_MAX; ep_idx++)
|
|
|
|
|
- {
|
|
|
|
|
- if ( BIT_TEST_(edpt_complete, ep_idx2bit(ep_idx)) )
|
|
|
|
|
- {
|
|
|
|
|
- // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
|
|
|
|
|
- dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
|
|
|
|
|
- dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
|
|
|
|
|
-
|
|
|
|
|
- uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED :
|
|
|
|
|
- ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
|
|
|
|
|
-
|
|
|
|
|
- uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
|
|
|
|
|
- dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
|
|
|
|
|
- }
|
|
|
|
|
- }
|
|
|
|
|
- }
|
|
|
|
|
- }
|
|
|
|
|
-
|
|
|
|
|
- if (int_status & INT_MASK_SOF)
|
|
|
|
|
- {
|
|
|
|
|
- dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
|
|
|
|
|
- }
|
|
|
|
|
-
|
|
|
|
|
- if (int_status & INT_MASK_NAK) {}
|
|
|
|
|
- if (int_status & INT_MASK_ERROR) TU_ASSERT(false, );
|
|
|
|
|
-}
|
|
|
|
|
-
|
|
|
|
|
-#endif
|
|
|
|
|
|
|
+/**************************************************************************/
|
|
|
|
|
+/*!
|
|
|
|
|
+ @file dcd_lpc43xx.c
|
|
|
|
|
+ @author hathach (tinyusb.org)
|
|
|
|
|
+
|
|
|
|
|
+ @section LICENSE
|
|
|
|
|
+
|
|
|
|
|
+ Software License Agreement (BSD License)
|
|
|
|
|
+
|
|
|
|
|
+ Copyright (c) 2013, hathach (tinyusb.org)
|
|
|
|
|
+ All rights reserved.
|
|
|
|
|
+
|
|
|
|
|
+ Redistribution and use in source and binary forms, with or without
|
|
|
|
|
+ modification, are permitted provided that the following conditions are met:
|
|
|
|
|
+ 1. Redistributions of source code must retain the above copyright
|
|
|
|
|
+ notice, this list of conditions and the following disclaimer.
|
|
|
|
|
+ 2. Redistributions in binary form must reproduce the above copyright
|
|
|
|
|
+ notice, this list of conditions and the following disclaimer in the
|
|
|
|
|
+ documentation and/or other materials provided with the distribution.
|
|
|
|
|
+ 3. Neither the name of the copyright holders nor the
|
|
|
|
|
+ names of its contributors may be used to endorse or promote products
|
|
|
|
|
+ derived from this software without specific prior written permission.
|
|
|
|
|
+
|
|
|
|
|
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
|
|
|
|
|
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
|
|
|
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
|
|
|
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
|
|
|
|
|
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
|
|
|
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
|
|
|
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
|
|
|
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
|
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
|
|
|
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
|
+
|
|
|
|
|
+ This file is part of the tinyusb stack.
|
|
|
|
|
+*/
|
|
|
|
|
+/**************************************************************************/
|
|
|
|
|
+
|
|
|
|
|
+#include "tusb_option.h"
|
|
|
|
|
+
|
|
|
|
|
+#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_LPC43XX
|
|
|
|
|
+
|
|
|
|
|
+//--------------------------------------------------------------------+
|
|
|
|
|
+// INCLUDE
|
|
|
|
|
+//--------------------------------------------------------------------+
|
|
|
|
|
+#include "common/tusb_common.h"
|
|
|
|
|
+#include "tusb_hal.h"
|
|
|
|
|
+
|
|
|
|
|
+#include "device/dcd.h"
|
|
|
|
|
+#include "dcd_lpc43xx.h"
|
|
|
|
|
+
|
|
|
|
|
+#include "chip.h"
|
|
|
|
|
+
|
|
|
|
|
+//--------------------------------------------------------------------+
|
|
|
|
|
+// MACRO CONSTANT TYPEDEF
|
|
|
|
|
+//--------------------------------------------------------------------+
|
|
|
|
|
+typedef struct {
|
|
|
|
|
+ dcd_qhd_t qhd[DCD_QHD_MAX] ATTR_ALIGNED(64); ///< Must be at 2K alignment
|
|
|
|
|
+ dcd_qtd_t qtd[DCD_QTD_MAX] ATTR_ALIGNED(32);
|
|
|
|
|
+}dcd_data_t;
|
|
|
|
|
+
|
|
|
|
|
+#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
|
|
|
|
|
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data0;
|
|
|
|
|
+#endif
|
|
|
|
|
+
|
|
|
|
|
+#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
|
|
|
|
|
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data1;
|
|
|
|
|
+#endif
|
|
|
|
|
+
|
|
|
|
|
+static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
|
|
|
|
|
+
|
|
|
|
|
+static dcd_data_t* const dcd_data_ptr[2] =
|
|
|
|
|
+{
|
|
|
|
|
+#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
|
|
|
|
|
+ &dcd_data0,
|
|
|
|
|
+#else
|
|
|
|
|
+ NULL,
|
|
|
|
|
+#endif
|
|
|
|
|
+
|
|
|
|
|
+#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
|
|
|
|
|
+ &dcd_data1
|
|
|
|
|
+#else
|
|
|
|
|
+ NULL
|
|
|
|
|
+#endif
|
|
|
|
|
+};
|
|
|
|
|
+
|
|
|
|
|
+//--------------------------------------------------------------------+
|
|
|
|
|
+// CONTROLLER API
|
|
|
|
|
+//--------------------------------------------------------------------+
|
|
|
|
|
+void dcd_connect(uint8_t rhport)
|
|
|
|
|
+{
|
|
|
|
|
+ LPC_USB[rhport]->USBCMD_D |= BIT_(0);
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
|
|
|
|
|
+{
|
|
|
|
|
+ LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | BIT_(24);
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
|
|
|
|
|
+{
|
|
|
|
|
+ // nothing to do
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+/// follows LPC43xx User Manual 23.10.3
|
|
|
|
|
+static void bus_reset(uint8_t rhport)
|
|
|
|
|
+{
|
|
|
|
|
+ LPC_USBHS_T* lpc_usb = LPC_USB[rhport];
|
|
|
|
|
+
|
|
|
|
|
+ // The reset value for all endpoint types is the control endpoint. If one endpoint
|
|
|
|
|
+ // direction is enabled and the paired endpoint of opposite direction is disabled, then the
|
|
|
|
|
+ // endpoint type of the unused direction must bechanged from the control type to any other
|
|
|
|
|
+ // type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
|
|
|
|
|
+ // for the data PID tracking on the active endpoint.
|
|
|
|
|
+
|
|
|
|
|
+ // USB0 has 5 but USB1 only has 3 non-control endpoints
|
|
|
|
|
+ for( int i=1; i < (rhport ? 6 : 4); i++)
|
|
|
|
|
+ {
|
|
|
|
|
+ lpc_usb->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ //------------- Clear All Registers -------------//
|
|
|
|
|
+ lpc_usb->ENDPTNAK = lpc_usb->ENDPTNAK;
|
|
|
|
|
+ lpc_usb->ENDPTNAKEN = 0;
|
|
|
|
|
+ lpc_usb->USBSTS_D = lpc_usb->USBSTS_D;
|
|
|
|
|
+ lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;
|
|
|
|
|
+ lpc_usb->ENDPTCOMPLETE = lpc_usb->ENDPTCOMPLETE;
|
|
|
|
|
+
|
|
|
|
|
+ while (lpc_usb->ENDPTPRIME);
|
|
|
|
|
+ lpc_usb->ENDPTFLUSH = 0xFFFFFFFF;
|
|
|
|
|
+ while (lpc_usb->ENDPTFLUSH);
|
|
|
|
|
+
|
|
|
|
|
+ // read reset bit in portsc
|
|
|
|
|
+
|
|
|
|
|
+ //------------- Queue Head & Queue TD -------------//
|
|
|
|
|
+ dcd_data_t* p_dcd = dcd_data_ptr[rhport];
|
|
|
|
|
+ tu_memclr(p_dcd, sizeof(dcd_data_t));
|
|
|
|
|
+
|
|
|
|
|
+ //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
|
|
|
|
|
+ p_dcd->qhd[0].zero_length_termination = p_dcd->qhd[1].zero_length_termination = 1;
|
|
|
|
|
+ p_dcd->qhd[0].max_package_size = p_dcd->qhd[1].max_package_size = CFG_TUD_ENDOINT0_SIZE;
|
|
|
|
|
+ p_dcd->qhd[0].qtd_overlay.next = p_dcd->qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
|
|
|
|
|
+
|
|
|
|
|
+ p_dcd->qhd[0].int_on_setup = 1; // OUT only
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+bool dcd_init(uint8_t rhport)
|
|
|
|
|
+{
|
|
|
|
|
+ LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
|
|
|
|
|
+ dcd_data_t* p_dcd = dcd_data_ptr[rhport];
|
|
|
|
|
+
|
|
|
|
|
+ tu_memclr(p_dcd, sizeof(dcd_data_t));
|
|
|
|
|
+
|
|
|
|
|
+ lpc_usb->ENDPOINTLISTADDR = (uint32_t) p_dcd->qhd; // Endpoint List Address has to be 2K alignment
|
|
|
|
|
+ lpc_usb->USBSTS_D = lpc_usb->USBSTS_D;
|
|
|
|
|
+ lpc_usb->USBINTR_D = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
|
|
|
|
|
+
|
|
|
|
|
+ lpc_usb->USBCMD_D &= ~0x00FF0000; // Interrupt Threshold Interval = 0
|
|
|
|
|
+ lpc_usb->USBCMD_D |= BIT_(0); // connect
|
|
|
|
|
+
|
|
|
|
|
+ // enable interrupt
|
|
|
|
|
+ NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
|
|
|
|
|
+
|
|
|
|
|
+ return true;
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+//--------------------------------------------------------------------+
|
|
|
|
|
+// HELPER
|
|
|
|
|
+//--------------------------------------------------------------------+
|
|
|
|
|
+// index to bit position in register
|
|
|
|
|
+static inline uint8_t ep_idx2bit(uint8_t ep_idx)
|
|
|
|
|
+{
|
|
|
|
|
+ return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
|
|
|
|
|
+{
|
|
|
|
|
+ tu_memclr(p_qtd, sizeof(dcd_qtd_t));
|
|
|
|
|
+
|
|
|
|
|
+ p_qtd->next = QTD_NEXT_INVALID;
|
|
|
|
|
+ p_qtd->active = 1;
|
|
|
|
|
+ p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
|
|
|
|
|
+
|
|
|
|
|
+ if (data_ptr != NULL)
|
|
|
|
|
+ {
|
|
|
|
|
+ p_qtd->buffer[0] = (uint32_t) data_ptr;
|
|
|
|
|
+ for(uint8_t i=1; i<5; i++)
|
|
|
|
|
+ {
|
|
|
|
|
+ p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
|
|
|
|
|
+ }
|
|
|
|
|
+ }
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+//--------------------------------------------------------------------+
|
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+// DCD Endpoint Port
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+//--------------------------------------------------------------------+
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+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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+{
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+ uint8_t const epnum = edpt_number(ep_addr);
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+ uint8_t const dir = edpt_dir(ep_addr);
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+
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+ if ( epnum == 0)
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+ {
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+ // Stall both Control IN and OUT
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+ LPC_USB[rhport]->ENDPTCTRL[epnum] |= ( (ENDPTCTRL_MASK_STALL << 16) || (ENDPTCTRL_MASK_STALL << 0) );
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+ }else
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+ {
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+ LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (dir ? 16 : 0);
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+ }
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+}
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+
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+bool dcd_edpt_stalled (uint8_t rhport, uint8_t ep_addr)
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+{
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+ uint8_t const epnum = edpt_number(ep_addr);
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+ uint8_t const dir = edpt_dir(ep_addr);
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+
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+ return LPC_USB[rhport]->ENDPTCTRL[epnum] & (ENDPTCTRL_MASK_STALL << (dir ? 16 : 0));
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+}
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+
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+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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+{
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+ uint8_t const epnum = edpt_number(ep_addr);
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+ uint8_t const dir = edpt_dir(ep_addr);
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+
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+ // data toggle also need to be reset
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+ LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ( dir ? 16 : 0 );
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+ LPC_USB[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ( dir ? 16 : 0));
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+}
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+
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+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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+{
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+ // TODO USB1 only has 4 non-control enpoint (USB0 has 5)
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+ // TODO not support ISO yet
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+ TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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+
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+ uint8_t const epnum = edpt_number(p_endpoint_desc->bEndpointAddress);
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+ uint8_t const dir = edpt_dir(p_endpoint_desc->bEndpointAddress);
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+ uint8_t const ep_idx = 2*epnum + dir;
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+
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+ //------------- Prepare Queue Head -------------//
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+ dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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+ tu_memclr(p_qhd, sizeof(dcd_qhd_t));
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+
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+ p_qhd->zero_length_termination = 1;
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+ p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size;
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+ p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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+
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+ // Enable EP Control
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+ LPC_USB[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
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+
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+ return true;
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+}
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+
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+bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
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+{
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+ uint8_t const epnum = edpt_number(ep_addr);
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+ uint8_t const dir = edpt_dir(ep_addr);
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+ uint8_t const ep_idx = 2*epnum + dir;
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+
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+ dcd_qhd_t const * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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+ dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
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+
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+ return p_qtd->active;
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+// return !p_qhd->qtd_overlay.halted && p_qhd->qtd_overlay.active;
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+}
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+
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+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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+{
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+ uint8_t const epnum = edpt_number(ep_addr);
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+ uint8_t const dir = edpt_dir(ep_addr);
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+ uint8_t const ep_idx = 2*epnum + dir;
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+
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+ if ( epnum == 0 )
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+ {
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+ // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
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+ // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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+ while(LPC_USB[rhport]->ENDPTSETUPSTAT & BIT_(0)) {}
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+ }
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+
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+ dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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+ dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
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+
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+ //------------- Prepare qtd -------------//
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+ qtd_init(p_qtd, buffer, total_bytes);
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+ p_qtd->int_on_complete = true;
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+ p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
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+
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+ // start transfer
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+ LPC_USB[rhport]->ENDPTPRIME = BIT_( ep_idx2bit(ep_idx) ) ;
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+
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+ return true;
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+}
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+
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+//--------------------------------------------------------------------+
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+// ISR
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+//--------------------------------------------------------------------+
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+void hal_dcd_isr(uint8_t rhport)
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+{
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+ LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
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+
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+ uint32_t const int_enable = lpc_usb->USBINTR_D;
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+ uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
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+ lpc_usb->USBSTS_D = int_status; // Acknowledge handled interrupt
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+
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+ if (int_status == 0) return;// disabled interrupt sources
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+
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+
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+ if (int_status & INT_MASK_RESET)
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+ {
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+ bus_reset(rhport);
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+ dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
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+ }
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+
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+ if (int_status & INT_MASK_SUSPEND)
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+ {
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+ if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
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+ {
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+ // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
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+ if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
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+ {
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+ dcd_event_bus_signal(rhport, DCD_EVENT_SUSPENDED, true);
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+ }
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+ }
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+ }
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+
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+ // TODO disconnection does not generate interrupt !!!!!!
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+// if (int_status & INT_MASK_PORT_CHANGE)
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+// {
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+// if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
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+// {
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+// dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
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+// dcd_event_handler(&event, true);
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+// }
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+// }
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+
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+ if (int_status & INT_MASK_USB)
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+ {
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+ uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
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+ lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
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+
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+ dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
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+
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+ if (lpc_usb->ENDPTSETUPSTAT)
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+ {
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+ //------------- Set up Received -------------//
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+ // 23.10.10.2 Operational model for setup transfers
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+ lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
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+
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+ dcd_event_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request, true);
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+ }
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+
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+ if ( edpt_complete )
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+ {
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+ for(uint8_t ep_idx = 0; ep_idx < DCD_QHD_MAX; ep_idx++)
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+ {
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+ if ( BIT_TEST_(edpt_complete, ep_idx2bit(ep_idx)) )
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+ {
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+ // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
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+ dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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+ dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
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+
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+ uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED :
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+ ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
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+
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+ uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
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+ dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
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+ }
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+ }
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+ }
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+ }
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+
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+ if (int_status & INT_MASK_SOF)
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+ {
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+ dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
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+ }
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+
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+ if (int_status & INT_MASK_NAK) {}
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+ if (int_status & INT_MASK_ERROR) TU_ASSERT(false, );
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+}
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+
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+#endif
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