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@@ -183,6 +183,11 @@ static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr)
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return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? 1 : 0);
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}
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+static inline uint8_t edpt_phy2addr(uint8_t ep_idx)
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+{
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+ return (ep_idx/2) | ( ep_idx & 0x01 ? TUSB_DIR_DEV_TO_HOST_MASK : 0 );
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+}
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+
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static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
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{
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return physical_endpoint/2;
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@@ -273,11 +278,12 @@ static inline volatile uint32_t * get_reg_control_addr(uint8_t port, uint8_t phy
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return &(LPC_USB[port]->ENDPTCTRL0) + edpt_phy2log(physical_endpoint);
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}
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-void tusb_dcd_edpt_stall(edpt_hdl_t edpt_hdl)
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+void tusb_dcd_edpt_stall(uint8_t port, uint8_t edpt_addr)
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{
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- volatile uint32_t * reg_control = get_reg_control_addr(edpt_hdl.port, edpt_hdl.index);
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+ uint8_t ep_idx = edpt_addr2phy(edpt_addr);
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+ volatile uint32_t * reg_control = get_reg_control_addr(port, ep_idx);
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- (*reg_control) |= ENDPTCTRL_MASK_STALL << (edpt_hdl.index & 0x01 ? 16 : 0);
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+ (*reg_control) |= ENDPTCTRL_MASK_STALL << (ep_idx & 0x01 ? 16 : 0);
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}
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void tusb_dcd_edpt_clear_stall(uint8_t port, uint8_t edpt_addr)
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@@ -289,7 +295,7 @@ void tusb_dcd_edpt_clear_stall(uint8_t port, uint8_t edpt_addr)
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(*reg_control) &= ~(ENDPTCTRL_MASK_STALL << ((edpt_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? 16 : 0));
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}
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-bool tusb_dcd_edpt_open(uint8_t port, tusb_descriptor_endpoint_t const * p_endpoint_desc, edpt_hdl_t* eh)
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+bool tusb_dcd_edpt_open(uint8_t port, tusb_descriptor_endpoint_t const * p_endpoint_desc)
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{
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// TODO USB1 only has 4 non-control enpoint (USB0 has 5)
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// TODO not support ISO yet
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@@ -315,28 +321,26 @@ bool tusb_dcd_edpt_open(uint8_t port, tusb_descriptor_endpoint_t const * p_endpo
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(*reg_control) |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
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- eh->port = port;
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- eh->index = ep_idx;
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-
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return true;
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}
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-bool tusb_dcd_edpt_busy(edpt_hdl_t edpt_hdl)
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+bool tusb_dcd_edpt_busy(uint8_t port, uint8_t edpt_addr)
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{
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- dcd_qhd_t const * p_qhd = &dcd_data_ptr[edpt_hdl.port]->qhd[edpt_hdl.index];
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+ uint8_t ep_idx = edpt_addr2phy(edpt_addr);
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+ dcd_qhd_t const * p_qhd = &dcd_data_ptr[port]->qhd[ep_idx];
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return p_qhd->list_qtd_idx[0] != 0; // qtd list is not empty
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// return !p_qhd->qtd_overlay.halted && p_qhd->qtd_overlay.active;
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}
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// add only, controller virtually cannot know
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-static tusb_error_t pipe_add_xfer(edpt_hdl_t edpt_hdl, void * buffer, uint16_t total_bytes, bool int_on_complete)
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+static tusb_error_t pipe_add_xfer(uint8_t port, uint8_t ed_idx, void * buffer, uint16_t total_bytes, bool int_on_complete)
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{
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- uint8_t qtd_idx = qtd_find_free(edpt_hdl.port);
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+ uint8_t qtd_idx = qtd_find_free(port);
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ASSERT(qtd_idx != 0, TUSB_ERROR_DCD_NOT_ENOUGH_QTD);
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- dcd_data_t* p_dcd = dcd_data_ptr[edpt_hdl.port];
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- dcd_qhd_t * p_qhd = &p_dcd->qhd[edpt_hdl.index];
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+ dcd_data_t* p_dcd = dcd_data_ptr[port];
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+ dcd_qhd_t * p_qhd = &p_dcd->qhd[ed_idx];
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dcd_qtd_t * p_qtd = &p_dcd->qtd[qtd_idx];
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//------------- Find free slot in qhd's array list -------------//
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@@ -358,21 +362,24 @@ static tusb_error_t pipe_add_xfer(edpt_hdl_t edpt_hdl, void * buffer, uint16_t t
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return TUSB_ERROR_NONE;
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}
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-tusb_error_t tusb_dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
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+tusb_error_t tusb_dcd_edpt_queue_xfer(uint8_t port, uint8_t edpt_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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- return pipe_add_xfer( edpt_hdl, buffer, total_bytes, false);
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+ uint8_t ep_idx = edpt_addr2phy(edpt_addr);
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+ return pipe_add_xfer(port, ep_idx, buffer, total_bytes, false);
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}
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-tusb_error_t tusb_dcd_edpt_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete)
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+tusb_error_t tusb_dcd_edpt_xfer(uint8_t port, uint8_t edpt_addr, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete)
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{
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- ASSERT_STATUS ( pipe_add_xfer(edpt_hdl, buffer, total_bytes, int_on_complete) );
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+ uint8_t ep_idx = edpt_addr2phy(edpt_addr);
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- dcd_qhd_t* p_qhd = &dcd_data_ptr[edpt_hdl.port]->qhd[ edpt_hdl.index ];
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- dcd_qtd_t* p_qtd = &dcd_data_ptr[edpt_hdl.port]->qtd[ p_qhd->list_qtd_idx[0] ];
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+ ASSERT_STATUS ( pipe_add_xfer(port, ep_idx, buffer, total_bytes, int_on_complete) );
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+
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+ dcd_qhd_t* p_qhd = &dcd_data_ptr[port]->qhd[ ep_idx ];
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+ dcd_qtd_t* p_qtd = &dcd_data_ptr[port]->qtd[ p_qhd->list_qtd_idx[0] ];
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p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // attach head QTD to QHD start transferring
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- LPC_USB[edpt_hdl.port]->ENDPTPRIME = BIT_( edpt_phy2pos(edpt_hdl.index) ) ;
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+ LPC_USB[port]->ENDPTPRIME = BIT_( edpt_phy2pos(ep_idx) ) ;
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return TUSB_ERROR_NONE;
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}
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@@ -386,12 +393,6 @@ void xfer_complete_isr(uint8_t port, uint32_t reg_complete)
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{ // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
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dcd_qhd_t * p_qhd = &dcd_data_ptr[port]->qhd[ep_idx];
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- edpt_hdl_t edpt_hdl =
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- {
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- .port = port,
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- .index = ep_idx,
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- };
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-
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// retire all QTDs in array list, up to 1st still-active QTD
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while( p_qhd->list_qtd_idx[0] != 0 )
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{
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@@ -407,7 +408,9 @@ void xfer_complete_isr(uint8_t port, uint32_t reg_complete)
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if (p_qtd->int_on_complete)
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{
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bool succeeded = ( p_qtd->xact_err || p_qtd->halted || p_qtd->buffer_err ) ? false : true;
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- tusb_dcd_xfer_complete(edpt_hdl, p_qtd->expected_bytes - p_qtd->total_bytes, succeeded); // only number of bytes in the IOC qtd
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+
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+ uint8_t edpt_addr = edpt_phy2addr(ep_idx);
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+ tusb_dcd_xfer_complete(port, edpt_addr, p_qtd->expected_bytes - p_qtd->total_bytes, succeeded); // only number of bytes in the IOC qtd
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}
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}
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}
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@@ -476,14 +479,8 @@ void hal_dcd_isr(uint8_t port)
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if ( p_qtd->int_on_complete )
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{
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- edpt_hdl_t edpt_hdl =
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- {
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- .port = port,
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- .index = 0,
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- };
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bool succeeded = ( p_qtd->xact_err || p_qtd->halted || p_qtd->buffer_err ) ? false : true;
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-
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- tusb_dcd_xfer_complete(edpt_hdl, 0, succeeded); // TODO xferred bytes for control xfer is not needed yet !!!!
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+ tusb_dcd_xfer_complete(port, 0, 0, succeeded); // TODO xferred bytes for control xfer is not needed yet !!!!
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}
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}
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}
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