CoreValidation: Fixed CoreA issues and warnings.

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/RTE/Device/ARMCA5/mmu_ARMCA5.c

@@ -100,7 +100,7 @@
 //Descriptors should place all memory in domain 0
 
 #include "ARMCA5.h"
-
+#include "mem_ARMCA5.h"
 
 // L2 table pointers
 //----------------------------------------
@@ -166,13 +166,9 @@ void MMU_CreateTranslationTable(void)
      *
      */
 
-    //Define Image
-    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
-    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
-    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
-
-    //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
-    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, __TTB_BASE, 1, Sect_Normal);
 
     //--------------------- PERIPHERALS -------------------
     MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE0    , 64, Sect_Device_RO);

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/RTE/Device/ARMCA7/mmu_ARMCA7.c

@@ -100,7 +100,7 @@
 //Descriptors should place all memory in domain 0
 
 #include "ARMCA7.h"
-
+#include "mem_ARMCA7.h"
 
 // L2 table pointers
 //----------------------------------------
@@ -166,13 +166,9 @@ void MMU_CreateTranslationTable(void)
      *
      */
 
-    //Define Image
-    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
-    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
-    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
-
-    //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
-    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, __TTB_BASE, 1, Sect_Normal);
 
     //--------------------- PERIPHERALS -------------------
     MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_FLASH_BASE0    , 64, Sect_Device_RO);

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/GCC/RTE/Device/ARMCA9/mmu_ARMCA9.c

@@ -100,7 +100,7 @@
 //Descriptors should place all memory in domain 0
 
 #include "ARMCA9.h"
-
+#include "mem_ARMCA9.h"
 
 // L2 table pointers
 //----------------------------------------
@@ -166,13 +166,9 @@ void MMU_CreateTranslationTable(void)
      *
      */
 
-    //Define Image
-    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
-    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
-    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
-
-    //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
-    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, __TTB_BASE, 1, Sect_Normal);
 
     //--------------------- PERIPHERALS -------------------
     MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A9_MP_FLASH_BASE0    , 64, Sect_Device_RO);

CMSIS/CoreValidation/Source/CV_CoreAFunc.c

@@ -33,15 +33,19 @@ void TC_CoreAFunc_FPSCR(void) {
   __set_FPSCR(fpscr);
 
   ASSERT_TRUE(fpscr == __get_FPSCR());
+  ASSERT_TRUE((f3 < 5.781f) && (f3 > 5.780f));
 }
 
 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
 #if defined(__CC_ARM)
 #define __SUBS(Rd, Rm, Rn) __ASM("SUBS " # Rd ", " # Rm ", " # Rn)
 #define __ADDS(Rd, Rm, Rn) __ASM("ADDS " # Rd ", " # Rm ", " # Rn)
+#elif defined( __GNUC__ ) && defined(__thumb__)
+#define __SUBS(Rd, Rm, Rn) __ASM("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#define __ADDS(Rd, Rm, Rn) __ASM("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
 #else
-#define __SUBS(Rd, Rm, Rn) __ASM("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc")
-#define __ADDS(Rd, Rm, Rn) __ASM("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc")
+#define __SUBS(Rd, Rm, Rn) __ASM("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#define __ADDS(Rd, Rm, Rn) __ASM("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
 #endif
 
 void TC_CoreAFunc_CPSR(void) {