Merge pull request #1 from margguo/update_to_6.80d

update jlink to 6.80d

Devices/Altera/Cyclone_V/Altera_Cyclone_V.JLinkScript

@@ -1,30 +0,0 @@
-/*********************************************************************
-*               (c) SEGGER Microcontroller GmbH & Co. KG             *
-*                        The Embedded Experts                        *
-*                           www.segger.com                           *
-**********************************************************************
-
--------------------------- END-OF-HEADER -----------------------------
-
-File    : Altera_Cyclone_V.JLinkScript
-Purpose : Script file for Cyclone V series devices
-Literature:
-  [1]  J-Link User Guide
-
-Additional information:
-  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
-*/
-
-/*********************************************************************
-*
-*       ConfigTargetSettings
-*/
-int ConfigTargetSettings(void) {
-  //
-  // For the Cyclone V device to work with J-Link the Core type needs to be set manually.
-  //
-  CPU = CORTEX_A9;
-  return 0;
-}
-
-/*************************** end of file ****************************/

Devices/AnalogDevices/ADSP-CM41/CM41x_M4.JLinkScript

@@ -1,204 +0,0 @@
-// Reset script for ADSP-CM41x, Cortex-M4 core.
-// Copyright (c) 2016 Analog Devices, Inc. All Rights Reserved.
-//
-// This script is for use with Segger JLink Lite emulators, to
-// connect to the Cortex-M4 core of the ADSP-CM41x processor.
-//
-// When the processor's security is enabled, debugger access is
-// disabled until secure keys are provided. If using custom key
-// values instead of the default key values, modify the values
-// passed by this script.
-// Note that there TWO sets of locations to change in this script 
-// - one for JTAG connections, and one for SWD connections.
-
-int GetScriptVersion(void) {
-  //
-  // Make sure that J-Link DLL does not ignore InitTraget() from script file
-  // Return values for Analog Devices:
-  //   <  100: Perform DLL internal connect sequence
-  //   >= 100: Perform InitTarget() from script file
-  //
-  return 100;                   
-}
-
-void ResetTarget(void) {
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0xe0002008);
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x8001031b);   // don't vector flash
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0xe000200c);
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x800102f7);   // don't vector uart
-  SYS_Sleep(300);
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0xe0002000);
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x00000007);   // enable fpb patch 0+1
-  SYS_Sleep(300);
-
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0xe000ed0c);
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x05fa0004);   // reset
-
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0xe000edf0);
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0xa05f0001);   // enable debug
-  SYS_Sleep(300);
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0xe000edf0);
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0xa05f0003);   // halt
-
-  Report("CM41x_M4.JLinkScript-v1.0.0.0: Resetting and halting Cortex-M4 core.");
-}
-
-
-/*********************************************************************
-*
-*       _InitTargetSWD
-*
-**********************************************************************/
-int _InitTargetSWD(void) {
-  CPU                = CORTEX_M4;
-  JTAG_AllowTAPReset = 0;
-
-  // reset the board
-
-  Report("CM41x_M4.JLinkScript-v1.0.0.0: SWD connection");
-  JTAG_ResetPin=0;
-  SYS_Sleep(300);
-  JTAG_ResetPin=1;
-  SYS_Sleep(300);
-
-  Report("CM41x_M4.JLinkScript-v1.0.0.0: SWD: send secure keys");
-
-  JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0x50000031);  // Set SYSPWRUPREQ and DBGPWRUPREQ and overrun detection
-  JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 24) | (0 << 4));      // Select AHB-AP bank 0 (data read/write registers)
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, 0x23000042);
-
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0x40017050);                  // SDBGKEYCOMP0	
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x11111111);                  // Replace 0x11111111 with your value
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0x40017054);                  // SDBGKEYCOMP1	
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x22222222);                  // Replace 0x22222222 with your value
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0x40017058);                  // SDBGKEYCOMP2	
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x33333333);                  // Replace 0x33333333 with your value
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0x4001705c);                  // SDBGKEYCOMP3	
-  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x44444444);                  // Replace 0x44444444 with your value
-  return 0;
-}
-
-/*********************************************************************
-*
-*       _InitTargetJTAG
-*
-**********************************************************************/
-int _InitTargetJTAG(void) {
-  int TAPCIdCode;
-  int DPIdCode;
-  int BitPos;
-  int TryAgain;
-  Report("CM41x_M4.JLinkScript-v1.0.0.0: JTAG connection");
-
-  TryAgain = 0;
-Reconnect:
-  JTAG_Reset();                           // Perform TAP reset and J-Link JTAG auto-detection
-  if (JTAG_TotalIRLen != 5) {
-    if (TryAgain == 0) {
-      //
-      // Toggle reset and retry the connect sequence
-      //
-      Report("CM41x_M4.JLinkScript-v1.0.0.0: ADI TAPC not found (IRLen mismatch). Performing recovery sequence");
-      JTAG_ResetPin = 0;
-      SYS_Sleep(300);
-      JTAG_ResetPin = 1;
-      SYS_Sleep(300);
-      TryAgain = 1;
-      goto Reconnect;
-    }
-    Report1("CM41x_M4.JLinkScript-v1.0.0.0: ADI TAPC not found (IRLen mismatch), Found: ", JTAG_TotalIRLen);
-    return -1;
-  }
-  //
-  // Configure JTAG chain
-  //
-  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=5");          // Does not hurt to configure the JTAG chain if SWD is used, as these params are simply not used for SWD
-  //
-  // Check TAPC device ID
-  //
-  JTAG_WriteIR(0x2); // IDCODE instruction for TAPC device
-  BitPos = JTAG_WriteDR(0x00000000, 32);
-  TAPCIdCode = JTAG_GetU32(BitPos);
-  if ((TAPCIdCode & 0x0FFFFFFF) != 0x0280b0cb) {    // Highest nibble holds version information, so it can not be used for verification.
-    Report1("CM41x_M4.JLinkScript-v1.0.0.0: Can not find TAPC (IDCODE mismatch). Expected 0x0280b0cb, found: ", TAPCIdCode & 0x0FFFFFFF);
-    return -1;
-  }
-  //
-  // Send 128-bit unlock key to device
-  //
-  Report("CM41x_M4.JLinkScript-v1.0.0.0: JTAG: Send secure keys");
-  JTAG_WriteIR(0xA);  
-  JTAG_StartDR();
-  JTAG_WriteDRCont(0x11111111, 32);  // SDBKEY 0: Replace 0x11111111 with your value
-  JTAG_WriteDRCont(0x22222222, 32);  // SDBKEY 1: Replace 0x22222222 with your value
-  JTAG_WriteDRCont(0x33333333, 32);  // SDBKEY 2: Replace 0x33333333 with your value
-  JTAG_WriteDREnd(0x44444444, 32);   // SDBKEY 3: Replace 0x44444444 with your value
-  JTAG_WriteClocks(1);               // Make sure that we go through Idle state in TAP controller
-  // set bit 0 in JTAG_CTL
-  // This adds the M4 and M0 to the chain
-  // New chain layout:
-  // #0 M0 (closest to TDO)
-  // #1 M4
-  // #2 TAPC
-  //  
-  JTAG_WriteIR(5);
-  BitPos = JTAG_WriteDR(0x5, 0x8);
-  //
-  // Select M4 TAP to communicate with
-  // Get DAP-Id
-  // Set DLL variables for further debugging
-  //
-  JTAG_AllowTAPReset = 0;
-  JLINK_CORESIGHT_Configure("IRPre=4;DRPre=1;IRPost=5;DRPost=1;IRLenDevice=4; PerformTIFInit=0");          // Does not hurt to configure the JTAG chain if SWD is used, as these params are simply not used for SWD
-  CPU=CORTEX_M4;
-  Report("CM41x_M4.JLinkScript-v1.0.0.0: starting Cortex-M4 core");
-  JTAG_WriteIR(0xE);
-  BitPos = JTAG_WriteDR(0x00000000, 32);
-  DPIdCode = JTAG_GetU32(BitPos);
-  if (((DPIdCode & 0xFFFFFFFF) != 0x4BA00477)) {
-    Report1("CM41x_M4.JLinkScript-v1.0.0.0: Can not find Cortex-M4 (IDCODE mismatch). Expected 0x4BA00477, found: ", DPIdCode);
-    return -1;
-  } else {
-    Report ("CM41x_M4.JLinkScript-v1.0.0.0: Found Cortex-M4");
-    //
-    // Set Device Ids (needed by DLL in case JTAG is used)
-    //
-    JTAG_SetDeviceId(0, 0x0BA00000);   // M0
-    Report ("CM41x_M4.JLinkScript-v1.0.0.0: set device id 0");
-    JTAG_SetDeviceId(1, DPIdCode);     // M4
-    Report ("CM41x_M4.JLinkScript-v1.0.0.0: set device id 1");
-    JTAG_SetDeviceId(2, TAPCIdCode);   // TAPC
-    Report ("CM41x_M4.JLinkScript-v1.0.0.0: set device id 2");
-  }
-  return 0;
-}
-
-void InitTarget(void) {
-  int r;
-  int Speed;
-
-  Report("*********************************");
-  Report("* CM41x_M4.JLinkScript-v1.0.0.0 *");
-  Report("*********************************"); 
-  //
-  // Remember original target interface speed and set new one
-  //
-  Speed       = JTAG_Speed;
-  JTAG_Speed  = 0x1000;
-  //
-  // Perform target interface specific connect sequence
-  //
-  if (MAIN_ActiveTIF == JLINK_TIF_JTAG) {
-    r = _InitTargetJTAG();
-  } else {
-    r = _InitTargetSWD();
-  }
-  //
-  // Restore original target interface speed settings
-  //
-  JTAG_Speed = Speed;
-  return r;
-}
-
-
-

Devices/Cypress/PSoC6/CY8C6xx7_CM0p.JLinkScript

@@ -0,0 +1,30 @@
+int ConfigTargetSettings(void) {
+  //
+  // Mark a specific memory region as memory type illegal
+  // in order to make sure that the software is not allowed to access these regions
+  // 
+  // Note: This does not work for J-Flash tool
+  //
+
+  // Exclude SFLASH regions
+  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+
+  // Exclude Cy Metadata
+  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+}
+
+void InitTarget(void) {
+  Report("********************************************");
+  Report("InitTarget for PSoC6 Cortex-M0+ script");
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // SYSAP
+  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M0+ core
+  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M4 core
+  CORESIGHT_IndexAHBAPToUse = 1;
+  CPU=CORTEX_M0;
+  JLINK_ExecCommand("SetETBIsPresent = 1");
+  Report("********************************************");
+}

Devices/Cypress/PSoC6/CY8C6xx7_CM0p_tm_xA.JLinkScript

@@ -0,0 +1,326 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : CY8C6xxx_CM0p_tm_xA.JLinkScript
+Purpose : J-Link script file for Cypress PSoC6A-BLE2 devices (CY8C6xx6 and CY8C6xx7)
+Literature:
+  [1]  J-Link User Guide
+
+Additional information:
+  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
+*/
+
+/*********************************************************************
+*
+*       Constants (similar to defines)
+*
+**********************************************************************
+*/
+
+__constant U32 _ACCESS_DP                        = 0;
+__constant U32 _ACCESS_AP                        = 1;
+__constant U32 _DHCSR_ADDR                       = 0xE000EDF0; // Debug Halting Control and Status Register
+__constant U32 _DEMCR_ADDR                       = 0xE000EDFC; // Debug Exception and Monitor Control Register
+__constant U32 _DCRDR_ADDR                       = 0xE000EDF8; // Debug Core Register Data Register
+__constant U32 _DCRSR_ADDR                       = 0xE000EDF4; // Debug Core Register Selector Register
+__constant U32 _DAP_ACC_32BIT_NO_AUTO_INC        = (1 << 29) | (1 << 25) | (1 << 24) | (0 << 4) | (2 << 0);
+__constant U32 _CPUSS_CM0_VTBASE                 = 0x402102B0; // Vector table base address for CM0+ core (CPUSS_CM0_VECTOR_TABLE_BASE reg.)
+__constant U32 _CPUSS_CMX_VTBASE_ERR_MSK         = 0xFFFFFF00; // Set by boot code if flash is empty or secure application
+
+/*********************************************************************
+*
+*       Static data
+*
+**********************************************************************
+*/
+
+const U8 _aData_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x9E, 0xE7,                                            // Switching sequence STM32
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x00, 0x00                                             // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
+};
+
+const U8 _aDir_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF
+};
+
+U8 _aDataOut[18];                                  // Needs to be big enough to hold data for longest sequence
+
+/*********************************************************************
+*
+*       Local functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       _PerformChipAcquisitionSeq()
+*
+*  Function description
+*    Performs the Cypress PSoC6-specific chip acquisition sequence.
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
+*/
+int _PerformChipAcquisitionSeq(void) {
+  U32 v;
+  U32 OrgTIFSpeed;
+  int t;
+  int tDelta;
+  //
+  // Perform Cypress PSoC 6 chip acquisition sequence
+  // This is the recommended connection sequence, to make sure that we can gain control over the device again, even if there is bad code running on it
+  //   nRESET == LOW
+  //   nRESET == HIGH
+  //   xx us (Wait for reset release)
+  //   xx us (wait for secure boot code to finish)
+  //   JTAGToSWDSwitching()
+  //   Set TST_CTRL
+  //   Device waits for app. 1500 us to receive the switching sequence + set TST_CTRL before it starts the user application
+  //
+  // We do not wait any fixed delay after reset release.
+  // We just output the switching sequence and try to read the SW-DP Id. This is repeated, until successful.
+  // This is done because the whole chip acquisition sequence is very time critical
+  //
+  //
+  // Make sure that J-Link is using a high target interface speed,
+  // so we can meet the timing requirements for "chip acquisition sequence"
+  // Might be necessary for some IDEs that select a very slow interface speed by default and do not allow to change this
+  //
+  OrgTIFSpeed = JLINK_JTAG_Speed;
+  JLINK_JTAG_Speed = 4000;
+  //
+  // Preconfigure some CoreSight settings as time is not critical at this point
+  // E.g. by default, when executing DAP API calls from within the firmware, J-Link will do a retry of the DAP transfer for some interfaces, if we got an invalid response from the DAP
+  // As this costs valuable time here, we temporarily disable this behavior and restore it at the end of the call
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=0;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Reset device, so it will wait for "device acquisition sequence"
+  //
+  JLINK_JTAG_ResetPin = 0;  // nRESET == LOW
+  JLINK_SYS_Sleep(10);      // Make sure that device recognizes the reset
+  JLINK_JTAG_ResetPin = 1;  // nRESET == HIGH
+  //
+  // Wait until device becomes responsive
+  //
+  t = JLINK_GetTime();
+  do {
+    JLINK_SWD_ReadWriteBits(&_aData_SeqSwitchToSWD[0], &_aDir_SeqSwitchToSWD[0], &_aDataOut[0], 18 * 8);
+    v = 0;
+    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_IDCODE, 0, &v);
+    v &= 0x0F000FFF;
+    if (v == 0x0B000477) {                      // DAP is responsive?
+      break;
+    }
+    tDelta = JLINK_GetTime() - t;
+  } while (tDelta < 1000);                        // Timeout reached?
+  //
+  // Put device into test mode, so it does not start the user application
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0, 0x50000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, 0x00000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, 0x00000002);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, 0x40260100);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 0x80000000);  
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, 0, &v);   // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  //
+  // Restore CORESIGHT settings (See beginning of this function call for more info)
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=1;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Restore original TIF speed
+  //
+  JLINK_JTAG_Speed = OrgTIFSpeed;
+  return 0;
+}
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       ConfigTargetSettings()
+*
+*  Function description
+*    Called before InitTarget(). Maninly used to set some global DLL variables to customize the normal connect procedure.
+*    For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
+*    that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
+*    May also be used to specify the device name in case debugger does not pass it to the DLL.
+*
+*  Notes
+*    (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
+*    (2) Should only set some global DLL variables
+*/
+int ConfigTargetSettings(void) {
+  Report("*****************************************************************");
+  Report("JLinkScript: Start 'ConfigTargetSettings' for PSoC6xxx Cortex-M0+");
+
+  //
+  // The PSoC 6 has the following APs:
+  // AP[0]  SYS-AP (used for chip acquisition sequence)
+  // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
+  // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
+  //
+  JLINK_CORESIGHT_AddAP(0, CORESIGHT_CUSTOM_AP);
+  JLINK_CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_IndexAHBAPToUse = 1; // AP-Index of AHB-AP to use for communication with core
+  CPU=CORTEX_M0;
+
+//  //
+//  // Mark a specific memory region as memory type illegal
+//  // in order to make sure that the software is not allowed to access these regions
+//  // Note: This does not work for J-Flash tool
+//  //
+//  // Exclude SFLASH regions
+//  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+//  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+//  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+//  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+//  // Exclude Cy Metadata
+//  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+//  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+
+  Report("*****************************************************************");
+  return 0;
+}
+
+/*********************************************************************
+*
+*       ResetTarget()
+*
+*  Function description
+*    Replaces selected reset strategy of J-Link software.
+*    No matter what reset type is selected, if this function is present, it will be called instead of the selected reset strategy
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
+*    (2) May use MEM_ API functions
+*/
+__probe int ResetTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  U32 iAPBank;
+  U32 iAP;
+  U32 v;
+  U32 vtBase;
+  U32 resetAddr;
+  //
+  // Perform standard chip acquisition sequence which also includes a reset
+  //
+  _PerformChipAcquisitionSeq();   // Requires __probe attribute for caller
+  //
+  // Make sure that the CPU is halted. See (1)
+  // No rush here, as chip acquisition sequence makes sure that user application is not started
+  //
+  // DAP has already been powered-up etc. by _PerformChipAcquisitionSeq(), so no need to configure CoreSight here again
+  //
+  JLINK_SYS_Sleep(5);   // Give BTL some time to enter WFI
+  iAPBank = 0;
+  iAP = 1;    // AHB-AP for M0
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, _ACCESS_DP, (iAP << 24) | (iAPBank << 4));
+  //
+  // Reset of PSoC6 also resets debug logic, so we need to restore some registers
+  // Luckily, we need to touch most of these registers anyhow, to halt the core
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, _ACCESS_AP, _DAP_ACC_32BIT_NO_AUTO_INC);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DHCSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0xA05F0003);  // Key + C_DEBUGEN + C_HALT
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DEMCR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, (1 << 24));   // TRCENA
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, _ACCESS_DP, &v);          // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  JLINK_SYS_Sleep(2);  // Give CPU some time to handle halt request (should not be necessary, but as user-initiated reset is not really a time critical operation that happens rarely, it does not hurt)
+
+  //
+  // Check CPUSS_CM0_VECTOR_TABLE_BASE. Zero or error code there means that the Flash is empty or TOC is corrupted.
+  // In this case boot code jumps to infinite loop in ROM.
+  // This case is sufficient condition for programming, but has no sense for debugging
+  // Otherwise, application exist, so need to set correct PC/SP for debugging
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _CPUSS_CM0_VTBASE);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &vtBase);
+  vtBase &= _CPUSS_CMX_VTBASE_ERR_MSK;
+  
+  if (vtBase != 0 && vtBase != _CPUSS_CMX_VTBASE_ERR_MSK) {
+
+    // Get address at reset vector
+    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, vtBase + 4);
+    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &resetAddr);
+    if (resetAddr != 0) {
+  
+      // Set PC with address at reset
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, resetAddr);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x0001000F);  
+    
+      // Get address at vector table & set SP
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, vtBase);
+      JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010011);  
+    
+      //Read xPSR register, set the thumb bit, and restore modified value to xPSR register
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00000010);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);  
+      v |= 0x01000000;
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010010);  
+	}
+  }
+  return 0;
+}
+
+/*********************************************************************
+*
+*       InitTarget()
+*
+*  Function description
+*    If present, called right before performing generic connect sequence.
+*    Usually used for targets which need a special connect sequence.
+*    E.g.: TI devices with ICEPick TAP on them where core TAP needs to be enabled via specific ICEPick sequences first
+*
+*  Return value
+*    >= 0:  O.K.
+*     < 0:  Error
+*
+*  Notes
+*    (1) Must not use high-level API functions like JLINK_MEM_ etc.
+*    (2) For target interface JTAG, this device has to setup the JTAG chain + JTAG TAP Ids.
+*    (3) This function is called before J-Link performed any communication with the device
+*    (4) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+*/
+__probe int InitTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  _PerformChipAcquisitionSeq();  // Requires __probe attribute for caller
+  JLINK_ExecCommand("SetETBIsPresent = 1");
+  return 0;
+}
+
+/*************************** end of file ****************************/

Devices/Cypress/PSoC6/CY8C6xx7_CM0p_tm_xx.JLinkScript

@@ -0,0 +1,308 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : CY8C6xxx_CM0p_tm.JLinkScript
+Purpose : J-Link script file for Cypress PSoC 6 series
+Literature:
+  [1]  J-Link User Guide
+
+Additional information:
+  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
+*/
+
+/*********************************************************************
+*
+*       Constants (similar to defines)
+*
+**********************************************************************
+*/
+
+__constant U32 _ACCESS_DP                        = 0;
+__constant U32 _ACCESS_AP                        = 1;
+__constant U32 _DHCSR_ADDR                       = 0xE000EDF0; // Debug Halting Control and Status Register
+__constant U32 _DEMCR_ADDR                       = 0xE000EDFC; // Debug Exception and Monitor Control Register
+__constant U32 _DCRDR_ADDR                       = 0xE000EDF8; // Debug Core Register Data Register
+__constant U32 _DCRSR_ADDR                       = 0xE000EDF4; // Debug Core Register Selector Register
+__constant U32 _DAP_ACC_32BIT_NO_AUTO_INC        = (1 << 29) | (1 << 25) | (1 << 24) | (0 << 4) | (2 << 0);
+__constant U32 _VECTOR_ADDR                      = 0x10000000; // Vector table for M0+ application
+
+
+/*********************************************************************
+*
+*       Static data
+*
+**********************************************************************
+*/
+
+const U8 _aData_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x9E, 0xE7,                                            // Switching sequence STM32
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x00, 0x00                                             // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
+};
+
+const U8 _aDir_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF
+};
+
+U8 _aDataOut[18];                                  // Needs to be big enough to hold data for longest sequence
+
+/*********************************************************************
+*
+*       Local functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       _PerformChipAcquisitionSeq()
+*
+*  Function description
+*    Performs the Cypress PSoC6-specific chip acquisition sequence.
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
+*/
+int _PerformChipAcquisitionSeq(void) {
+  U32 v;
+  U32 OrgTIFSpeed;
+  int t;
+  int tDelta;
+  //
+  // Perform Cypress PSoC 6 chip acquisition sequence
+  // This is the recommended connection sequence, to make sure that we can gain control over the device again, even if there is bad code running on it
+  //   nRESET == LOW
+  //   nRESET == HIGH
+  //   xx us (Wait for reset release)
+  //   xx us (wait for secure boot code to finish)
+  //   JTAGToSWDSwitching()
+  //   Set TST_CTRL
+  //   Device waits for app. 1500 us to receive the switching sequence + set TST_CTRL before it starts the user application
+  //
+  // We do not wait any fixed delay after reset release.
+  // We just output the switching sequence and try to read the SW-DP Id. This is repeated, until successful.
+  // This is done because the whole chip acquisition sequence is very time critical
+  //
+  //
+  // Make sure that J-Link is using a high target interface speed,
+  // so we can meet the timing requirements for "chip acquisition sequence"
+  // Might be necessary for some IDEs that select a very slow interface speed by default and do not allow to change this
+  //
+  OrgTIFSpeed = JLINK_JTAG_Speed;
+  JLINK_JTAG_Speed = 4000;
+  //
+  // Preconfigure some CoreSight settings as time is not critical at this point
+  // E.g. by default, when executing DAP API calls from within the firmware, J-Link will do a retry of the DAP transfer for some interfaces, if we got an invalid response from the DAP
+  // As this costs valuable time here, we temporarily disable this behavior and restore it at the end of the call
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=0;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Reset device, so it will wait for "device acquisition sequence"
+  //
+  JLINK_JTAG_ResetPin = 0;  // nRESET == LOW
+  JLINK_SYS_Sleep(10);      // Make sure that device recognizes the reset
+  JLINK_JTAG_ResetPin = 1;  // nRESET == HIGH
+  //
+  // Wait until device becomes responsive
+  //
+  t = JLINK_GetTime();
+  do {
+    JLINK_SWD_ReadWriteBits(&_aData_SeqSwitchToSWD[0], &_aDir_SeqSwitchToSWD[0], &_aDataOut[0], 18 * 8);
+    v = 0;
+    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_IDCODE, 0, &v);
+    v &= 0x0F000FFF;
+    if (v == 0x0B000477) {                      // DAP is responsive?
+      break;
+    }
+    tDelta = JLINK_GetTime() - t;
+  } while (tDelta < 50);                        // Timeout reached?
+  //
+  // Put device into test mode, so it does not start the user application
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0, 0x50000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, 0x00000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, 0x00000002);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, 0x40260100);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 0x80000000);  
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, 0, &v);   // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  //
+  // Restore CORESIGHT settings (See beginning of this function call for more info)
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=1;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Restore original TIF speed
+  //
+  JLINK_JTAG_Speed = OrgTIFSpeed;
+  return 0;
+}
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       ConfigTargetSettings()
+*
+*  Function description
+*    Called before InitTarget(). Maninly used to set some global DLL variables to customize the normal connect procedure.
+*    For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
+*    that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
+*    May also be used to specify the device name in case debugger does not pass it to the DLL.
+*
+*  Notes
+*    (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
+*    (2) Should only set some global DLL variables
+*/
+int ConfigTargetSettings(void) {
+  Report("*****************************************************************");
+  Report("JLinkScript: Start 'ConfigTargetSettings' for PSoC6xxx Cortex-M0+");
+
+  //
+  // The PSoC 6 has the following APs:
+  // AP[0]  SYS-AP (used for chip acquisition sequence)
+  // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
+  // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
+  //
+  JLINK_CORESIGHT_AddAP(0, CORESIGHT_CUSTOM_AP);
+  JLINK_CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_IndexAHBAPToUse = 1; // AP-Index of AHB-AP to use for communication with core
+  CPU=CORTEX_M0;
+
+//  //
+//  // Mark a specific memory region as memory type illegal
+//  // in order to make sure that the software is not allowed to access these regions
+//  // Note: This does not work for J-Flash tool
+//  //
+//  // Exclude SFLASH regions
+//  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+//  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+//  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+//  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+//  // Exclude Cy Metadata
+//  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+//  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+
+  Report("*****************************************************************");
+  return 0;
+}
+
+/*********************************************************************
+*
+*       ResetTarget()
+*
+*  Function description
+*    Replaces selected reset strategy of J-Link software.
+*    No matter what reset type is selected, if this function is present, it will be called instead of the selected reset strategy
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
+*    (2) May use MEM_ API functions
+*/
+__probe int ResetTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  U32 iAPBank;
+  U32 iAP;
+  U32 v;
+  //
+  // Perform standard chip acquisition sequence which also includes a reset
+  //
+  _PerformChipAcquisitionSeq();   // Requires __probe attribute for caller
+  //
+  // Make sure that the CPU is halted. See (1)
+  // No rush here, as chip acquisition sequence makes sure that user application is not started
+  //
+  // DAP has already been powered-up etc. by _PerformChipAcquisitionSeq(), so no need to configure CoreSight here again
+  //
+  JLINK_SYS_Sleep(5);   // Give BTL some time to enter WFI
+  iAPBank = 0;
+  iAP = 1;    // AHB-AP for M0
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, _ACCESS_DP, (iAP << 24) | (iAPBank << 4));
+  //
+  // Reset of PSoC6 also resets debug logic, so we need to restore some registers
+  // Luckily, we need to touch most of these registers anyhow, to halt the core
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, _ACCESS_AP, _DAP_ACC_32BIT_NO_AUTO_INC);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DHCSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0xA05F0003);  // Key + C_DEBUGEN + C_HALT
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DEMCR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, (1 << 24));   // TRCENA
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, _ACCESS_DP, &v);          // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  JLINK_SYS_Sleep(2);  // Give CPU some time to handle halt request (should not be necessary, but as user-initiated reset is not really a time critical operation that happens rarely, it does not hurt)
+
+  // Get address at reset vector & set PC
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _VECTOR_ADDR + 4);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x0001000F);  
+
+  // Get address at vector table & set SP
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _VECTOR_ADDR);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010011);  
+
+  //Read xPSR register, set the thumb bit, and restore modified value to xPSR register
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00000010);  
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);  
+  v |= 0x01000000;
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010010);  
+  
+  return 0;
+}
+
+/*********************************************************************
+*
+*       InitTarget()
+*
+*  Function description
+*    If present, called right before performing generic connect sequence.
+*    Usually used for targets which need a special connect sequence.
+*    E.g.: TI devices with ICEPick TAP on them where core TAP needs to be enabled via specific ICEPick sequences first
+*
+*  Return value
+*    >= 0:  O.K.
+*     < 0:  Error
+*
+*  Notes
+*    (1) Must not use high-level API functions like JLINK_MEM_ etc.
+*    (2) For target interface JTAG, this device has to setup the JTAG chain + JTAG TAP Ids.
+*    (3) This function is called before J-Link performed any communication with the device
+*    (4) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+*/
+__probe int InitTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  _PerformChipAcquisitionSeq();  // Requires __probe attribute for caller
+  JLINK_ExecCommand("SetETBIsPresent = 1");
+  return 0;
+}
+
+/*************************** end of file ****************************/

Devices/Cypress/PSoC6/CY8C6xx7_CM4.JLinkScript

@@ -0,0 +1,290 @@
+/*********************************************************************
+*
+*       Constants (similar to defines)
+*
+**********************************************************************
+*/
+
+/*----------------- Pin mapping for the TRACE signals ----------------
+  Copy 0
+    P6_4  DS #5   cpuss.swj_swo_tdo     (SWO DATA)
+    P7_0  ACT #14 cpuss.trace_clock     (ETM/SWO TRACECLK)
+    P9_3  ACT #15 cpuss.trace_data[0]:0 (ETM TRACEDATA[0])
+    P9_2  ACT #15 cpuss.trace_data[1]:0 (ETM TRACEDATA[1])
+    P9_1  ACT #15 cpuss.trace_data[2]:0 (ETM TRACEDATA[2])
+    P9_0  ACT #15 cpuss.trace_data[3]:0 (ETM TRACEDATA[3])
+  Copy 1
+    P10_3 ACT #15 cpuss.trace_data[0]:1 (ETM TRACEDATA[0])
+    P10_2 ACT #15 cpuss.trace_data[1]:1 (ETM TRACEDATA[1])
+    P10_1 ACT #15 cpuss.trace_data[2]:1 (ETM TRACEDATA[2])
+    P10_0 ACT #15 cpuss.trace_data[3]:1 (ETM TRACEDATA[3])
+  Copy 2
+    P7_7  ACT #15 cpuss.trace_data[0]:2 (ETM TRACEDATA[0])
+    P7_6  ACT #15 cpuss.trace_data[1]:2 (ETM TRACEDATA[1])
+    P7_5  ACT #15 cpuss.trace_data[2]:2 (ETM TRACEDATA[2])
+    P7_4  ACT #15 cpuss.trace_data[3]:2 (ETM TRACEDATA[3])
+  See 'Multiple Alternate Functions' table in device datasheet.
+
+  Examples:
+  1) CY8CKIT-062-WIFI-BT Pioneer Kit, J12:
+     TCLK => P7_0, TD0 => P9_3, TD1 => P7_6, TD2 => P7_5, TD3 => P7_4  
+*/
+
+/* Global variables */
+U32 _IS_TRACE_CONFIGURED = 0x0;
+
+/* Trace clock setup registers */
+__constant U32 _PERI_CLOCK_CTL54_ADDR       = 0x40010CD8; // Clock control register for cpuss.clock_trace_in
+__constant U32 _PERI_CLOCK_CTL_DIV_SEL_MASK = 0x0000000F; // PERI_CLOCK_CTL.DIV_SEL
+__constant U32 _PERI_DIV_8_CTL0_ADDR        = 0x40010800; // Divider control (for 8.0 divider)
+__constant U32 _PERI_DIV_CMD_ADDR           = 0x40010400; // Divider command
+__constant U32 _PERI_DIV_CMD_ENABLE_MASK    = 0x80000000; // ENABLE field in PERI_DIV_CMD
+__constant U32 _PERI_DIV_CMD_DISABLE_MASK   = 0x40000000; // DISABLE field in PERI_DIV_CMD
+__constant U32 _PERI_DIV_CMD_PA_SEL_ROL     = 0x00000008; // PA_TYPE_SEL + PA_DIV_SEL fields offset in PERI_DIV_CMD
+__constant U32 _PERI_DIV_PA_SEL_MASK        = 0x000000FF; // PA_TYPE_SEL + PA_DIV_SEL fields mask (size)
+/* Trace pins setup registers */
+__constant U32 _HSIOM_PRT7_PORT_SEL0        = 0x40310070; // Port 7 selection 0
+__constant U32 _HSIOM_PRT9_PORT_SEL0        = 0x40310090; // Port 9 selection 0
+__constant U32 _HSIOM_PRT10_PORT_SEL0       = 0x403100A0; // Port 10 selection 0
+__constant U32 _GPIO_PRT7_CFG               = 0x403203A8; // Port 7 configuration
+__constant U32 _GPIO_PRT9_CFG               = 0x403204A8; // Port 9 configuration
+__constant U32 _GPIO_PRT10_CFG              = 0x40320528; // Port 10 configuration
+__constant U32 _GPIO_PRT7_CFG_OUT           = 0x403203B0; // Port 7 output buffer configuration
+__constant U32 _GPIO_PRT9_CFG_OUT           = 0x403204B0; // Port 9 output buffer configuration
+__constant U32 _GPIO_PRT10_CFG_OUT          = 0x40320530; // Port 10 output buffer configuration
+__constant U32 _PRT_IO_SEL_MASK             = 0x1F; // Mask for IO[pin]_SEL field in HSIOM_PRT[port]_PORT_SEL[0/1] register
+__constant U32 _PRT_DRIVE_MODE_MASK         = 0xF;  // Mask for IN_EN[pin] & DRIVE_MODE[pin] fields in GPIO_PRT[port]_CFG register
+__constant U32 _PRT_SLOW_MASK               = 0x1;  // Mask for SLOW[pin] field in GPIO_PRT[port]_CFG_OUT register
+__constant U32 _PRT_DRIVE_SEL_MASK          = 0x3;  // Mask for DRIVE_SEL[pin] field in GPIO_PRT[port]_CFG_OUT register
+
+/*********************************************************************
+*
+*       Local functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+* _SetupTraceClock() - Selects TPIU Clock divider for ETM Trace.
+*/
+int _SetupTraceClock(void) {	
+  U32 ClockCtlVal;
+  U32 ClockDivCtlVal;
+  U32 ClockDivSel;
+  U32 ClockDivVal;
+  U32 ClockDivCmd;
+  U32 TRACE_CLOCK_CTL_ADDR;
+  U32 TRACE_CLOCK_DIV_CTL_ADDR;
+  U32 TRACE_CLOCK_DIV_CMD_ADDR;
+  
+  TRACE_CLOCK_CTL_ADDR     = _PERI_CLOCK_CTL54_ADDR;
+  TRACE_CLOCK_DIV_CTL_ADDR = _PERI_DIV_8_CTL0_ADDR;
+  TRACE_CLOCK_DIV_CMD_ADDR = _PERI_DIV_CMD_ADDR;
+
+  ClockDivSel = (7 & _PERI_CLOCK_CTL_DIV_SEL_MASK); // Peripheral clock divider index to use for trace clock
+  ClockDivVal = (0 & _PERI_DIV_PA_SEL_MASK);        // Peripheral clock divider value for trace clock
+                                                    // Actual divider is (1+ClockDivVal)
+
+  ClockCtlVal = JLINK_MEM_ReadU32(TRACE_CLOCK_CTL_ADDR);
+  ClockDivCtlVal = JLINK_MEM_ReadU32(TRACE_CLOCK_DIV_CTL_ADDR + (ClockDivSel*4));
+  if((ClockCtlVal != ClockDivSel) || (ClockDivCtlVal != ((ClockDivVal << _PERI_DIV_CMD_PA_SEL_ROL) | 0x1))){
+    JLINK_SYS_Report("JLinkScript/Trace: Setup TPIU clock");
+    //
+    // Select TPIU Clock divider
+    //
+    
+    // DISABLE 8.0 DIV in PERI_DIV_CMD:
+    ClockDivCmd = _PERI_DIV_CMD_DISABLE_MASK | (_PERI_DIV_PA_SEL_MASK << _PERI_DIV_CMD_PA_SEL_ROL) | ClockDivSel;
+    JLINK_MEM_WriteU32(TRACE_CLOCK_DIV_CMD_ADDR, ClockDivCmd);
+    // Use selected divider (8.0) for cpuss.clock_trace_in
+    JLINK_MEM_WriteU32(TRACE_CLOCK_CTL_ADDR, ClockDivSel);
+    // Set 8.0 DIV = ClockDivVal
+    JLINK_MEM_WriteU32((TRACE_CLOCK_DIV_CTL_ADDR+(ClockDivSel*4)), (ClockDivVal << 8));
+    // ENABLE 8.0 DIV 
+    ClockDivCmd = _PERI_DIV_CMD_ENABLE_MASK | (_PERI_DIV_PA_SEL_MASK << _PERI_DIV_CMD_PA_SEL_ROL) | ClockDivSel;
+    JLINK_MEM_WriteU32(TRACE_CLOCK_DIV_CMD_ADDR, ClockDivCmd);
+  }
+
+  return 0;  
+}
+
+/*********************************************************************
+*
+* _SetupTracePin() - Configures Trace Pin.
+* Parameters:
+*   pin:                  Pin number
+*   hsiomPrtPortSel0Addr: HSIOM_PRT[port]_PORT_SEL0 register address
+*   ioSelVal:             IO[pin]_SEL field value (connection) for HSIOM_PRT[port]_PORT_SEL register
+*   gpioPrtCfgAddr:       GPIO_PRT[port]_CFG register address
+*   gpioPrtCfgOutAddr:    GPIO_PRT[port]_CFG_OUT register address
+*/
+int _SetupTracePin(U32 pin,
+                   U32 hsiomPrtPortSel0Addr, U32 ioSelVal,
+                   U32 gpioPrtCfgAddr,
+                   U32 gpioPrtCfgOutAddr) {	
+  U32 reg0;
+  U32 reg1;
+  U32 offset;
+  U32 hsiomRegAddr; // Address of HSIOM_PRT[port]_PORT_SEL0 or HSIOM_PRT[port]_PORT_SEL1
+  U32 pMode;        // pin drive mode
+  U32 pSlew;        // pin slew rate
+  U32 pStrange;     // pin drive strange
+  
+  //
+  // Select pin route connection in HSIOM_PRT[port]_PORT_SEL[0/1] register
+  // See HSIOM_PRT0_PORT_SEL0 in registers TRM for the bit-field map of HSIOM_PRT[port]_PORT_SEL0 registers
+  // See HSIOM_PRT2_PORT_SEL1 in registers TRM for the bit-field map of HSIOM_PRT[port]_PORT_SEL1 registers
+  if (pin < 4) { /* Pin[0-3] selection is in HSIOM_PRT[port]_PORT_SEL0 register */
+    hsiomRegAddr = hsiomPrtPortSel0Addr; // Use HSIOM_PRT[port]_PORT_SEL0
+    offset = pin * 8; // Offset of the IO[pin]_SEL field for required pin number,
+                      // where 8 = 5 bits for IO[pin]_SEL field + 3 not used bits
+  }
+  else { /* Pin[4-7] selection is in HSIOM_PRT[port]_PORT_SEL1 register */
+    hsiomRegAddr = hsiomPrtPortSel0Addr + 4; // Use HSIOM_PRT[port]_PORT_SEL1
+    offset = (pin - 4) * 8; // Offset of the IO[pin]_SEL field for required pin number,
+                            // where 8 = 5 bits for IO[pin]_SEL field + 3 not used bits
+  }
+  reg0 = JLINK_MEM_ReadU32(hsiomRegAddr);
+  reg1 = reg0;
+  reg1 &= ~(_PRT_IO_SEL_MASK << offset); // Clear IO[pin]_SEL field
+  reg1 |=  (ioSelVal         << offset); // Set field value
+  if (reg0 |= reg1) {
+    JLINK_MEM_WriteU32(hsiomRegAddr, reg1);
+  }
+  
+  //
+  // Disable input buffer and set drive mode in GPIO_PRT[port]_CFG register
+  // See GPIO_PRT2_CFG in registers TRM for the bit-field map:
+  pMode = 6;      // DRIVE_MODE[pin]:
+                  //  0: HIGHZ:         Output buffer is off creating a high impedance input (default)
+                  //  1: RESERVED:      This mode is reserved and should not be used
+                  //  2: PULLUP:        Resistive pull up
+                  //  3: PULLDOWN:      Resistive pull down
+                  //  4: OD_DRIVESLOW:  Open drain, drives low
+                  //  5: OD_DRIVESHIGH: Open drain, drives high
+                  //  6: STRONG:        Strong D_OUTput buffer
+                  //  7: PULLUP_DOWN:   Pull up or pull down
+  reg0 = JLINK_MEM_ReadU32(gpioPrtCfgAddr);
+  reg1 = reg0;
+  offset = pin * 4; // Offset of the DRIVE_MODE[pin] field for required pin number,
+                    // where 4 = 3 bits for DRIVE_MODE[pin] + 1 bit for IN_EN fields
+  reg1 &= ~(_PRT_DRIVE_MODE_MASK << offset); // Clear IN_EN[pin] and DRIVE_MODE[pin] fields
+  reg1 |=  (pMode                << offset); // Set DRIVE_MODE[pin] field value
+  if (reg0 |= reg1) {
+    JLINK_MEM_WriteU32(gpioPrtCfgAddr, reg1);
+  }
+  
+  //
+  // Set slew rate and drive strength in GPIO_PRT[port]_CFG_OUT register
+  // See GPIO_PRT2_CFG_OUT in registers TRM for the bit-field map:
+  pSlew = 0x0;    // SLOW[pin]:  
+                  //  0 - Fast slew rate (default)
+                  //  1 - Slow slew rate
+  pStrange = 0x3; // DRIVE_SEL[pin]:  
+                  //  0 - FULL_DRIVE:        Full drive strength: GPIO drives current at its max rated spec.
+                  //  1 - ONE_HALF_DRIVE:    1/2 drive strength: GPIO drives current at 1/2 of its max rated spec (default)
+                  //  2 - ONE_QUARTER_DRIVE: 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
+                  //  3 - ONE_EIGHTH_DRIVE:  1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
+  reg0 = JLINK_MEM_ReadU32(gpioPrtCfgOutAddr);
+  reg1 = reg0;
+  offset = pin;
+  reg1 &= ~(_PRT_SLOW_MASK << offset); // Clear SLOW[pin] field
+  reg1 |=  (pSlew          << offset); // Set field value
+  offset = 16 + pin * 2;               // Offset of the DRIVE_SEL[pin] field for required pin number,
+                                       // where '16' is the offset of DRIVE_SEL[pin] for pin 0 and '2' is the size of DRIVE_SEL[pin]
+  reg1 &= ~(_PRT_DRIVE_SEL_MASK << offset); // Clear DRIVE_SEL[pin] field
+  reg1 |=  (pStrange            << offset); // Set field value
+  if (reg0 |= reg1) {
+    JLINK_MEM_WriteU32(gpioPrtCfgOutAddr, reg1);
+  }
+  
+  return 0;
+}
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+
+int ConfigTargetSettings(void) {
+  //
+  // Mark a specific memory region as memory type illegal
+  // in order to make sure that the software is not allowed to access these regions
+  // 
+  // Note: This does not work for J-Flash tool
+  //
+
+  // Exclude SFLASH regions
+  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+
+  // Exclude Cy Metadata
+  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+}
+
+void InitTarget(void) {
+  Report("JLinkScript/InitTarget: CORESIGHT setup");
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // SYSAP
+  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M0+ core
+  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M4 core
+  CORESIGHT_IndexAHBAPToUse = 2;
+  CPU=CORTEX_M4;
+}
+
+/*********************************************************************
+*
+*       OnTraceStart()
+*
+*  Function description
+*    If present, called right before trace is started.
+*    Used to initialize MCU specific trace related things like configuring the trace pins for alternate function.
+*
+*  Return value
+*    >= 0:  O.K.
+*     < 0:  Error
+*
+*  Notes
+*    (1) May use high-level API functions like JLINK_MEM_ etc.
+*    (2) Should not call JLINK_TARGET_Halt(). Can rely on target being halted when entering this function
+*/
+int OnTraceStart(void) {
+  U32 PortWidth;
+  U32 IO_SEL_ACT14;
+  U32 IO_SEL_ACT15;
+  //U32 IO_SEL_DS5;
+
+  if (_IS_TRACE_CONFIGURED) {
+	  return 0;
+  }
+
+  // Adjust sampling point of trace pin (Optional: not needed for this cpu)
+  // JLINK_ExecCommand("TraceSampleAdjust TD=2000");   
+  
+  // Setup peripheral clocks for tracing
+  _SetupTraceClock();     
+  
+  // Setup pins for tracing: TCLK > P7_0, TD0 > P9_3, TD1 > P7_6, TD2 > P7_5, TD3 > P7_4
+  PortWidth = JLINK_TRACE_PortWidth;      
+  JLINK_SYS_Report("JLinkScript/Trace: Setup clock and data pins");
+  IO_SEL_ACT14 = 0x1A; // Connection route for 'cpuss.trace_clock' signal (P7_0)
+  IO_SEL_ACT15 = 0x1B; // Connection route for 'cpuss.trace_data[0-3]' signals (P7, P9 and P10)
+  //IO_SEL_DS5 =   0x1D; // Connection route for 'cpuss.swj_swo_tdo' signal (P6_4)
+
+  _SetupTracePin( /*P7_0*/ 0, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT14, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);
+  _SetupTracePin( /*P9_3*/ 3, _HSIOM_PRT9_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT9_CFG, _GPIO_PRT9_CFG_OUT);
+  _SetupTracePin( /*P7_6*/ 6, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);  
+  if (PortWidth > 2) {
+    _SetupTracePin( /*P7_5*/ 5, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);  
+    _SetupTracePin( /*P7_4*/ 4, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);  
+  }
+  
+  _IS_TRACE_CONFIGURED = 1;
+  return 0;
+}
+

Devices/Cypress/PSoC6/CY8C6xxA_CM0p.JLinkScript

@@ -0,0 +1,30 @@
+int ConfigTargetSettings(void) {
+  //
+  // Mark a specific memory region as memory type illegal
+  // in order to make sure that the software is not allowed to access these regions
+  // 
+  // Note: This does not work for J-Flash tool
+  //
+
+  // Exclude SFLASH regions
+  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+
+  // Exclude Cy Metadata
+  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+}
+
+void InitTarget(void) {
+  Report("********************************************");
+  Report("InitTarget for PSoC6 Cortex-M0+ script");
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // SYSAP
+  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M0+ core
+  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M4 core
+  CORESIGHT_IndexAHBAPToUse = 1;
+  CPU=CORTEX_M0;
+  JLINK_ExecCommand("SetETBIsPresent = 1");
+  Report("********************************************");
+}

Devices/Cypress/PSoC6/CY8C6xxA_CM0p_tm.JLinkScript

@@ -0,0 +1,326 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : CY8C6xxA_CM0p_tm.JLinkScript
+Purpose : J-Link script file for Cypress PSoC6A-2M/512K devices (CY8C6xxA and CY8C6xx5)
+Literature:
+  [1]  J-Link User Guide
+
+Additional information:
+  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
+*/
+
+/*********************************************************************
+*
+*       Constants (similar to defines)
+*
+**********************************************************************
+*/
+
+__constant U32 _ACCESS_DP                        = 0;
+__constant U32 _ACCESS_AP                        = 1;
+__constant U32 _DHCSR_ADDR                       = 0xE000EDF0; // Debug Halting Control and Status Register
+__constant U32 _DEMCR_ADDR                       = 0xE000EDFC; // Debug Exception and Monitor Control Register
+__constant U32 _DCRDR_ADDR                       = 0xE000EDF8; // Debug Core Register Data Register
+__constant U32 _DCRSR_ADDR                       = 0xE000EDF4; // Debug Core Register Selector Register
+__constant U32 _DAP_ACC_32BIT_NO_AUTO_INC        = (1 << 29) | (1 << 25) | (1 << 24) | (0 << 4) | (2 << 0);
+__constant U32 _CPUSS_CM0_VTBASE                 = 0x40201120; // Vector table base address for CM0+ core (CPUSS_CM0_VECTOR_TABLE_BASE reg.)
+__constant U32 _CPUSS_CMX_VTBASE_ERR_MSK         = 0xFFFFFF00; // Set by boot code if flash is empty or secure application
+
+/*********************************************************************
+*
+*       Static data
+*
+**********************************************************************
+*/
+
+const U8 _aData_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x9E, 0xE7,                                            // Switching sequence STM32
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x00, 0x00                                             // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
+};
+
+const U8 _aDir_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF
+};
+
+U8 _aDataOut[18];                                  // Needs to be big enough to hold data for longest sequence
+
+/*********************************************************************
+*
+*       Local functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       _PerformChipAcquisitionSeq()
+*
+*  Function description
+*    Performs the Cypress PSoC6-specific chip acquisition sequence.
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
+*/
+int _PerformChipAcquisitionSeq(void) {
+  U32 v;
+  U32 OrgTIFSpeed;
+  int t;
+  int tDelta;
+  //
+  // Perform Cypress PSoC 6 chip acquisition sequence
+  // This is the recommended connection sequence, to make sure that we can gain control over the device again, even if there is bad code running on it
+  //   nRESET == LOW
+  //   nRESET == HIGH
+  //   xx us (Wait for reset release)
+  //   xx us (wait for secure boot code to finish)
+  //   JTAGToSWDSwitching()
+  //   Set TST_CTRL
+  //   Device waits for app. 1500 us to receive the switching sequence + set TST_CTRL before it starts the user application
+  //
+  // We do not wait any fixed delay after reset release.
+  // We just output the switching sequence and try to read the SW-DP Id. This is repeated, until successful.
+  // This is done because the whole chip acquisition sequence is very time critical
+  //
+  //
+  // Make sure that J-Link is using a high target interface speed,
+  // so we can meet the timing requirements for "chip acquisition sequence"
+  // Might be necessary for some IDEs that select a very slow interface speed by default and do not allow to change this
+  //
+  OrgTIFSpeed = JLINK_JTAG_Speed;
+  JLINK_JTAG_Speed = 4000;
+  //
+  // Preconfigure some CoreSight settings as time is not critical at this point
+  // E.g. by default, when executing DAP API calls from within the firmware, J-Link will do a retry of the DAP transfer for some interfaces, if we got an invalid response from the DAP
+  // As this costs valuable time here, we temporarily disable this behavior and restore it at the end of the call
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=0;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Reset device, so it will wait for "device acquisition sequence"
+  //
+  JLINK_JTAG_ResetPin = 0;  // nRESET == LOW
+  JLINK_SYS_Sleep(10);      // Make sure that device recognizes the reset
+  JLINK_JTAG_ResetPin = 1;  // nRESET == HIGH
+  //
+  // Wait until device becomes responsive
+  //
+  t = JLINK_GetTime();
+  do {
+    JLINK_SWD_ReadWriteBits(&_aData_SeqSwitchToSWD[0], &_aDir_SeqSwitchToSWD[0], &_aDataOut[0], 18 * 8);
+    v = 0;
+    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_IDCODE, 0, &v);
+    v &= 0x0F000FFF;
+    if (v == 0x0B000477) {                      // DAP is responsive?
+      break;
+    }
+    tDelta = JLINK_GetTime() - t;
+  } while (tDelta < 1000);                        // Timeout reached?
+  //
+  // Put device into test mode, so it does not start the user application
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0, 0x50000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, 0x00000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, 0x00000002);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, 0x40260100);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 0x80000000);  
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, 0, &v);   // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  //
+  // Restore CORESIGHT settings (See beginning of this function call for more info)
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=1;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Restore original TIF speed
+  //
+  JLINK_JTAG_Speed = OrgTIFSpeed;
+  return 0;
+}
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       ConfigTargetSettings()
+*
+*  Function description
+*    Called before InitTarget(). Maninly used to set some global DLL variables to customize the normal connect procedure.
+*    For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
+*    that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
+*    May also be used to specify the device name in case debugger does not pass it to the DLL.
+*
+*  Notes
+*    (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
+*    (2) Should only set some global DLL variables
+*/
+int ConfigTargetSettings(void) {
+  Report("*****************************************************************");
+  Report("JLinkScript: Start 'ConfigTargetSettings' for PSoC6xxA Cortex-M0+");
+
+  //
+  // The PSoC 6 has the following APs:
+  // AP[0]  SYS-AP (used for chip acquisition sequence)
+  // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
+  // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
+  //
+  JLINK_CORESIGHT_AddAP(0, CORESIGHT_CUSTOM_AP);
+  JLINK_CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_IndexAHBAPToUse = 1; // AP-Index of AHB-AP to use for communication with core
+  CPU=CORTEX_M0;
+
+//  //
+//  // Mark a specific memory region as memory type illegal
+//  // in order to make sure that the software is not allowed to access these regions
+//  // Note: This does not work for J-Flash tool
+//  //
+//  // Exclude SFLASH regions
+//  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+//  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+//  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+//  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+//  // Exclude Cy Metadata
+//  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+//  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+
+  Report("*****************************************************************");
+  return 0;
+}
+
+/*********************************************************************
+*
+*       ResetTarget()
+*
+*  Function description
+*    Replaces selected reset strategy of J-Link software.
+*    No matter what reset type is selected, if this function is present, it will be called instead of the selected reset strategy
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
+*    (2) May use MEM_ API functions
+*/
+__probe int ResetTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  U32 iAPBank;
+  U32 iAP;
+  U32 v;
+  U32 vtBase;
+  U32 resetAddr;
+  //
+  // Perform standard chip acquisition sequence which also includes a reset
+  //
+  _PerformChipAcquisitionSeq();   // Requires __probe attribute for caller
+  //
+  // Make sure that the CPU is halted. See (1)
+  // No rush here, as chip acquisition sequence makes sure that user application is not started
+  //
+  // DAP has already been powered-up etc. by _PerformChipAcquisitionSeq(), so no need to configure CoreSight here again
+  //
+  JLINK_SYS_Sleep(5);   // Give BTL some time to enter WFI
+  iAPBank = 0;
+  iAP = 1;    // AHB-AP for M0
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, _ACCESS_DP, (iAP << 24) | (iAPBank << 4));
+  //
+  // Reset of PSoC6 also resets debug logic, so we need to restore some registers
+  // Luckily, we need to touch most of these registers anyhow, to halt the core
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, _ACCESS_AP, _DAP_ACC_32BIT_NO_AUTO_INC);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DHCSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0xA05F0003);  // Key + C_DEBUGEN + C_HALT
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DEMCR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, (1 << 24));   // TRCENA
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, _ACCESS_DP, &v);          // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  JLINK_SYS_Sleep(2);  // Give CPU some time to handle halt request (should not be necessary, but as user-initiated reset is not really a time critical operation that happens rarely, it does not hurt)
+
+  //
+  // Check CPUSS_CM0_VECTOR_TABLE_BASE. Zero or error code there means that the Flash is empty or TOC is corrupted.
+  // In this case boot code jumps to infinite loop in ROM.
+  // This case is sufficient condition for programming, but has no sense for debugging
+  // Otherwise, application exist, so need to set correct PC/SP for debugging
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _CPUSS_CM0_VTBASE);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &vtBase);
+  vtBase &= _CPUSS_CMX_VTBASE_ERR_MSK;
+  
+  if (vtBase != 0 && vtBase != _CPUSS_CMX_VTBASE_ERR_MSK) {
+
+    // Get address at reset vector
+    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, vtBase + 4);
+    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &resetAddr);
+    if (resetAddr != 0) {
+  
+      // Set PC with address at reset
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, resetAddr);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x0001000F);  
+    
+      // Get address at vector table & set SP
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, vtBase);
+      JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010011);  
+    
+      //Read xPSR register, set the thumb bit, and restore modified value to xPSR register
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00000010);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);  
+      v |= 0x01000000;
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010010);  
+	}
+  }
+  return 0;
+}
+
+/*********************************************************************
+*
+*       InitTarget()
+*
+*  Function description
+*    If present, called right before performing generic connect sequence.
+*    Usually used for targets which need a special connect sequence.
+*    E.g.: TI devices with ICEPick TAP on them where core TAP needs to be enabled via specific ICEPick sequences first
+*
+*  Return value
+*    >= 0:  O.K.
+*     < 0:  Error
+*
+*  Notes
+*    (1) Must not use high-level API functions like JLINK_MEM_ etc.
+*    (2) For target interface JTAG, this device has to setup the JTAG chain + JTAG TAP Ids.
+*    (3) This function is called before J-Link performed any communication with the device
+*    (4) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+*/
+__probe int InitTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  _PerformChipAcquisitionSeq();  // Requires __probe attribute for caller
+  JLINK_ExecCommand("SetETBIsPresent = 1");
+  return 0;
+}
+
+/*************************** end of file ****************************/

Devices/Cypress/PSoC6/CY8C6xxA_CM0p_tm_xA.JLinkScript

@@ -0,0 +1,327 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : CY8C6xxx_CM0p_tm.JLinkScript
+Purpose : J-Link script file for Cypress PSoC 6 series
+Literature:
+  [1]  J-Link User Guide
+
+Additional information:
+  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
+*/
+
+/*********************************************************************
+*
+*       Constants (similar to defines)
+*
+**********************************************************************
+*/
+
+__constant U32 _ACCESS_DP                        = 0;
+__constant U32 _ACCESS_AP                        = 1;
+__constant U32 _DHCSR_ADDR                       = 0xE000EDF0; // Debug Halting Control and Status Register
+__constant U32 _DEMCR_ADDR                       = 0xE000EDFC; // Debug Exception and Monitor Control Register
+__constant U32 _DCRDR_ADDR                       = 0xE000EDF8; // Debug Core Register Data Register
+__constant U32 _DCRSR_ADDR                       = 0xE000EDF4; // Debug Core Register Selector Register
+__constant U32 _DAP_ACC_32BIT_NO_AUTO_INC        = (1 << 29) | (1 << 25) | (1 << 24) | (0 << 4) | (2 << 0);
+__constant U32 _CPUSS_CM0_VTBASE                 = 0x40201120; // Vector table base address for CM0+ core (CPUSS_CM0_VECTOR_TABLE_BASE reg.)
+__constant U32 _CPUSS_CMX_VTBASE_ERR_MSK         = 0xFFFFFF00; // Set by boot code if flash is empty or secure application
+
+/*********************************************************************
+*
+*       Static data
+*
+**********************************************************************
+*/
+
+const U8 _aData_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x9E, 0xE7,                                            // Switching sequence STM32
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x00, 0x00                                             // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
+};
+
+const U8 _aDir_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF
+};
+
+U8 _aDataOut[18];                                  // Needs to be big enough to hold data for longest sequence
+
+/*********************************************************************
+*
+*       Local functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       _PerformChipAcquisitionSeq()
+*
+*  Function description
+*    Performs the Cypress PSoC6-specific chip acquisition sequence.
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
+*/
+int _PerformChipAcquisitionSeq(void) {
+  U32 v;
+  U32 OrgTIFSpeed;
+  int t;
+  int tDelta;
+  //
+  // Perform Cypress PSoC 6 chip acquisition sequence
+  // This is the recommended connection sequence, to make sure that we can gain control over the device again, even if there is bad code running on it
+  //   nRESET == LOW
+  //   nRESET == HIGH
+  //   xx us (Wait for reset release)
+  //   xx us (wait for secure boot code to finish)
+  //   JTAGToSWDSwitching()
+  //   Set TST_CTRL
+  //   Device waits for app. 1500 us to receive the switching sequence + set TST_CTRL before it starts the user application
+  //
+  // We do not wait any fixed delay after reset release.
+  // We just output the switching sequence and try to read the SW-DP Id. This is repeated, until successful.
+  // This is done because the whole chip acquisition sequence is very time critical
+  //
+  //
+  // Make sure that J-Link is using a high target interface speed,
+  // so we can meet the timing requirements for "chip acquisition sequence"
+  // Might be necessary for some IDEs that select a very slow interface speed by default and do not allow to change this
+  //
+  OrgTIFSpeed = JLINK_JTAG_Speed;
+  JLINK_JTAG_Speed = 4000;
+  //
+  // Preconfigure some CoreSight settings as time is not critical at this point
+  // E.g. by default, when executing DAP API calls from within the firmware, J-Link will do a retry of the DAP transfer for some interfaces, if we got an invalid response from the DAP
+  // As this costs valuable time here, we temporarily disable this behavior and restore it at the end of the call
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=0;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Reset device, so it will wait for "device acquisition sequence"
+  //
+  JLINK_JTAG_ResetPin = 0;  // nRESET == LOW
+  JLINK_SYS_Sleep(10);      // Make sure that device recognizes the reset
+  JLINK_JTAG_ResetPin = 1;  // nRESET == HIGH
+  //
+  // Wait until device becomes responsive
+  //
+  t = JLINK_GetTime();
+  do {
+    JLINK_SWD_ReadWriteBits(&_aData_SeqSwitchToSWD[0], &_aDir_SeqSwitchToSWD[0], &_aDataOut[0], 18 * 8);
+    v = 0;
+    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_IDCODE, 0, &v);
+    v &= 0x0F000FFF;
+    if (v == 0x0B000477) {                      // DAP is responsive?
+      break;
+    }
+    tDelta = JLINK_GetTime() - t;
+  } while (tDelta < 1000);                        // Timeout reached?
+  //
+  // Put device into test mode, so it does not start the user application
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0, 0x50000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, 0x00000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, 0x00000002);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, 0x40260100);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 0x80000000);  
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, 0, &v);   // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  //
+  // Restore CORESIGHT settings (See beginning of this function call for more info)
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=1;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Restore original TIF speed
+  //
+  JLINK_JTAG_Speed = OrgTIFSpeed;
+  return 0;
+}
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       ConfigTargetSettings()
+*
+*  Function description
+*    Called before InitTarget(). Maninly used to set some global DLL variables to customize the normal connect procedure.
+*    For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
+*    that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
+*    May also be used to specify the device name in case debugger does not pass it to the DLL.
+*
+*  Notes
+*    (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
+*    (2) Should only set some global DLL variables
+*/
+int ConfigTargetSettings(void) {
+  Report("*****************************************************************");
+  Report("JLinkScript: Start 'ConfigTargetSettings' for PSoC6xxx Cortex-M0+");
+
+  //
+  // The PSoC 6 has the following APs:
+  // AP[0]  SYS-AP (used for chip acquisition sequence)
+  // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
+  // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
+  //
+  JLINK_CORESIGHT_AddAP(0, CORESIGHT_CUSTOM_AP);
+  JLINK_CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_IndexAHBAPToUse = 1; // AP-Index of AHB-AP to use for communication with core
+  CPU=CORTEX_M0;
+
+//  //
+//  // Mark a specific memory region as memory type illegal
+//  // in order to make sure that the software is not allowed to access these regions
+//  // Note: This does not work for J-Flash tool
+//  //
+//  // Exclude SFLASH regions
+//  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+//  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+//  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+//  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+//  // Exclude Cy Metadata
+//  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+//  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+//  // Exclude eFuse
+//  JLINK_ExecCommand("map region 0x90700000-0x907FFFFF XI");
+
+  Report("*****************************************************************");
+  return 0;
+}
+
+/*********************************************************************
+*
+*       ResetTarget()
+*
+*  Function description
+*    Replaces selected reset strategy of J-Link software.
+*    No matter what reset type is selected, if this function is present, it will be called instead of the selected reset strategy
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
+*    (2) May use MEM_ API functions
+*/
+__probe int ResetTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  U32 iAPBank;
+  U32 iAP;
+  U32 v;
+  U32 vtBase;
+  U32 resetAddr;
+  //
+  // Perform standard chip acquisition sequence which also includes a reset
+  //
+  _PerformChipAcquisitionSeq();   // Requires __probe attribute for caller
+  //
+  // Make sure that the CPU is halted. See (1)
+  // No rush here, as chip acquisition sequence makes sure that user application is not started
+  //
+  // DAP has already been powered-up etc. by _PerformChipAcquisitionSeq(), so no need to configure CoreSight here again
+  //
+  JLINK_SYS_Sleep(5);   // Give BTL some time to enter WFI
+  iAPBank = 0;
+  iAP = 1;    // AHB-AP for M0
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, _ACCESS_DP, (iAP << 24) | (iAPBank << 4));
+  //
+  // Reset of PSoC6 also resets debug logic, so we need to restore some registers
+  // Luckily, we need to touch most of these registers anyhow, to halt the core
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, _ACCESS_AP, _DAP_ACC_32BIT_NO_AUTO_INC);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DHCSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0xA05F0003);  // Key + C_DEBUGEN + C_HALT
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DEMCR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, (1 << 24));   // TRCENA
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, _ACCESS_DP, &v);          // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  JLINK_SYS_Sleep(2);  // Give CPU some time to handle halt request (should not be necessary, but as user-initiated reset is not really a time critical operation that happens rarely, it does not hurt)
+
+  //
+  // Check CPUSS_CM0_VECTOR_TABLE_BASE. Zero or error code there means that the Flash is empty or TOC is corrupted.
+  // In this case boot code jumps to infinite loop in ROM.
+  // This case is sufficient condition for programming, but has no sense for debugging
+  // Otherwise, application exist, so need to set correct PC/SP for debugging
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _CPUSS_CM0_VTBASE);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &vtBase);
+  vtBase &= _CPUSS_CMX_VTBASE_ERR_MSK;
+  
+  if (vtBase != 0 && vtBase != _CPUSS_CMX_VTBASE_ERR_MSK) {
+
+    // Get address at reset vector
+    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, vtBase + 4);
+    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &resetAddr);
+    if (resetAddr != 0) {
+  
+      // Set PC with address at reset
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, resetAddr);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x0001000F);  
+    
+      // Get address at vector table & set SP
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, vtBase);
+      JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010011);  
+    
+      //Read xPSR register, set the thumb bit, and restore modified value to xPSR register
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00000010);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);  
+      v |= 0x01000000;
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010010);  
+	}
+  }
+  return 0;
+}
+
+/*********************************************************************
+*
+*       InitTarget()
+*
+*  Function description
+*    If present, called right before performing generic connect sequence.
+*    Usually used for targets which need a special connect sequence.
+*    E.g.: TI devices with ICEPick TAP on them where core TAP needs to be enabled via specific ICEPick sequences first
+*
+*  Return value
+*    >= 0:  O.K.
+*     < 0:  Error
+*
+*  Notes
+*    (1) Must not use high-level API functions like JLINK_MEM_ etc.
+*    (2) For target interface JTAG, this device has to setup the JTAG chain + JTAG TAP Ids.
+*    (3) This function is called before J-Link performed any communication with the device
+*    (4) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+*/
+__probe int InitTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  _PerformChipAcquisitionSeq();  // Requires __probe attribute for caller
+  return 0;
+}
+
+/*************************** end of file ****************************/

Devices/Cypress/PSoC6/CY8C6xxA_CM0p_tm_xx.JLinkScript

@@ -0,0 +1,309 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : CY8C6xxx_CM0p_tm.JLinkScript
+Purpose : J-Link script file for Cypress PSoC 6 series
+Literature:
+  [1]  J-Link User Guide
+
+Additional information:
+  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
+*/
+
+/*********************************************************************
+*
+*       Constants (similar to defines)
+*
+**********************************************************************
+*/
+
+__constant U32 _ACCESS_DP                        = 0;
+__constant U32 _ACCESS_AP                        = 1;
+__constant U32 _DHCSR_ADDR                       = 0xE000EDF0; // Debug Halting Control and Status Register
+__constant U32 _DEMCR_ADDR                       = 0xE000EDFC; // Debug Exception and Monitor Control Register
+__constant U32 _DCRDR_ADDR                       = 0xE000EDF8; // Debug Core Register Data Register
+__constant U32 _DCRSR_ADDR                       = 0xE000EDF4; // Debug Core Register Selector Register
+__constant U32 _DAP_ACC_32BIT_NO_AUTO_INC        = (1 << 29) | (1 << 25) | (1 << 24) | (0 << 4) | (2 << 0);
+__constant U32 _VECTOR_ADDR                      = 0x10000000; // Vector table for M0+ application
+
+
+/*********************************************************************
+*
+*       Static data
+*
+**********************************************************************
+*/
+
+const U8 _aData_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x9E, 0xE7,                                            // Switching sequence STM32
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x00, 0x00                                             // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
+};
+
+const U8 _aDir_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF
+};
+
+U8 _aDataOut[18];                                  // Needs to be big enough to hold data for longest sequence
+
+/*********************************************************************
+*
+*       Local functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       _PerformChipAcquisitionSeq()
+*
+*  Function description
+*    Performs the Cypress PSoC6-specific chip acquisition sequence.
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
+*/
+int _PerformChipAcquisitionSeq(void) {
+  U32 v;
+  U32 OrgTIFSpeed;
+  int t;
+  int tDelta;
+  //
+  // Perform Cypress PSoC 6 chip acquisition sequence
+  // This is the recommended connection sequence, to make sure that we can gain control over the device again, even if there is bad code running on it
+  //   nRESET == LOW
+  //   nRESET == HIGH
+  //   xx us (Wait for reset release)
+  //   xx us (wait for secure boot code to finish)
+  //   JTAGToSWDSwitching()
+  //   Set TST_CTRL
+  //   Device waits for app. 1500 us to receive the switching sequence + set TST_CTRL before it starts the user application
+  //
+  // We do not wait any fixed delay after reset release.
+  // We just output the switching sequence and try to read the SW-DP Id. This is repeated, until successful.
+  // This is done because the whole chip acquisition sequence is very time critical
+  //
+  //
+  // Make sure that J-Link is using a high target interface speed,
+  // so we can meet the timing requirements for "chip acquisition sequence"
+  // Might be necessary for some IDEs that select a very slow interface speed by default and do not allow to change this
+  //
+  OrgTIFSpeed = JLINK_JTAG_Speed;
+  JLINK_JTAG_Speed = 4000;
+  //
+  // Preconfigure some CoreSight settings as time is not critical at this point
+  // E.g. by default, when executing DAP API calls from within the firmware, J-Link will do a retry of the DAP transfer for some interfaces, if we got an invalid response from the DAP
+  // As this costs valuable time here, we temporarily disable this behavior and restore it at the end of the call
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=0;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Reset device, so it will wait for "device acquisition sequence"
+  //
+  JLINK_JTAG_ResetPin = 0;  // nRESET == LOW
+  JLINK_SYS_Sleep(10);      // Make sure that device recognizes the reset
+  JLINK_JTAG_ResetPin = 1;  // nRESET == HIGH
+  //
+  // Wait until device becomes responsive
+  //
+  t = JLINK_GetTime();
+  do {
+    JLINK_SWD_ReadWriteBits(&_aData_SeqSwitchToSWD[0], &_aDir_SeqSwitchToSWD[0], &_aDataOut[0], 18 * 8);
+    v = 0;
+    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_IDCODE, 0, &v);
+    v &= 0x0F000FFF;
+    if (v == 0x0B000477) {                      // DAP is responsive?
+      break;
+    }
+    tDelta = JLINK_GetTime() - t;
+  } while (tDelta < 50);                        // Timeout reached?
+  //
+  // Put device into test mode, so it does not start the user application
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0, 0x50000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, 0x00000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, 0x00000002);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, 0x40260100);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 0x80000000);  
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, 0, &v);   // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  //
+  // Restore CORESIGHT settings (See beginning of this function call for more info)
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=1;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Restore original TIF speed
+  //
+  JLINK_JTAG_Speed = OrgTIFSpeed;
+  return 0;
+}
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       ConfigTargetSettings()
+*
+*  Function description
+*    Called before InitTarget(). Maninly used to set some global DLL variables to customize the normal connect procedure.
+*    For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
+*    that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
+*    May also be used to specify the device name in case debugger does not pass it to the DLL.
+*
+*  Notes
+*    (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
+*    (2) Should only set some global DLL variables
+*/
+int ConfigTargetSettings(void) {
+  Report("*****************************************************************");
+  Report("JLinkScript: Start 'ConfigTargetSettings' for PSoC6xxx Cortex-M0+");
+
+  //
+  // The PSoC 6 has the following APs:
+  // AP[0]  SYS-AP (used for chip acquisition sequence)
+  // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
+  // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
+  //
+  JLINK_CORESIGHT_AddAP(0, CORESIGHT_CUSTOM_AP);
+  JLINK_CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_IndexAHBAPToUse = 1; // AP-Index of AHB-AP to use for communication with core
+  CPU=CORTEX_M0;
+
+//  //
+//  // Mark a specific memory region as memory type illegal
+//  // in order to make sure that the software is not allowed to access these regions
+//  // Note: This does not work for J-Flash tool
+//  //
+//  // Exclude SFLASH regions
+//  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+//  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+//  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+//  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+//  // Exclude Cy Metadata
+//  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+//  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+//  // Exclude eFuse
+//  JLINK_ExecCommand("map region 0x90700000-0x907FFFFF XI");
+
+  Report("*****************************************************************");
+  return 0;
+}
+
+/*********************************************************************
+*
+*       ResetTarget()
+*
+*  Function description
+*    Replaces selected reset strategy of J-Link software.
+*    No matter what reset type is selected, if this function is present, it will be called instead of the selected reset strategy
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
+*    (2) May use MEM_ API functions
+*/
+__probe int ResetTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  U32 iAPBank;
+  U32 iAP;
+  U32 v;
+  //
+  // Perform standard chip acquisition sequence which also includes a reset
+  //
+  _PerformChipAcquisitionSeq();   // Requires __probe attribute for caller
+  //
+  // Make sure that the CPU is halted. See (1)
+  // No rush here, as chip acquisition sequence makes sure that user application is not started
+  //
+  // DAP has already been powered-up etc. by _PerformChipAcquisitionSeq(), so no need to configure CoreSight here again
+  //
+  JLINK_SYS_Sleep(5);   // Give BTL some time to enter WFI
+  iAPBank = 0;
+  iAP = 1;    // AHB-AP for M0
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, _ACCESS_DP, (iAP << 24) | (iAPBank << 4));
+  //
+  // Reset of PSoC6 also resets debug logic, so we need to restore some registers
+  // Luckily, we need to touch most of these registers anyhow, to halt the core
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, _ACCESS_AP, _DAP_ACC_32BIT_NO_AUTO_INC);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DHCSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0xA05F0003);  // Key + C_DEBUGEN + C_HALT
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DEMCR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, (1 << 24));   // TRCENA
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, _ACCESS_DP, &v);          // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  JLINK_SYS_Sleep(2);  // Give CPU some time to handle halt request (should not be necessary, but as user-initiated reset is not really a time critical operation that happens rarely, it does not hurt)
+
+  // Get address at reset vector & set PC
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _VECTOR_ADDR + 4);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x0001000F);  
+
+  // Get address at vector table & set SP
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _VECTOR_ADDR);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010011);  
+
+  //Read xPSR register, set the thumb bit, and restore modified value to xPSR register
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00000010);  
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);  
+  v |= 0x01000000;
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010010);  
+  
+  return 0;
+}
+
+/*********************************************************************
+*
+*       InitTarget()
+*
+*  Function description
+*    If present, called right before performing generic connect sequence.
+*    Usually used for targets which need a special connect sequence.
+*    E.g.: TI devices with ICEPick TAP on them where core TAP needs to be enabled via specific ICEPick sequences first
+*
+*  Return value
+*    >= 0:  O.K.
+*     < 0:  Error
+*
+*  Notes
+*    (1) Must not use high-level API functions like JLINK_MEM_ etc.
+*    (2) For target interface JTAG, this device has to setup the JTAG chain + JTAG TAP Ids.
+*    (3) This function is called before J-Link performed any communication with the device
+*    (4) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+*/
+__probe int InitTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  _PerformChipAcquisitionSeq();  // Requires __probe attribute for caller
+  return 0;
+}
+
+/*************************** end of file ****************************/

Devices/Cypress/PSoC6/CY8C6xxA_CM4.JLinkScript

@@ -0,0 +1,290 @@
+/*********************************************************************
+*
+*       Constants (similar to defines)
+*
+**********************************************************************
+*/
+
+/*----------------- Pin mapping for the TRACE signals ----------------
+  Copy 0
+    P6_4  DS #5   cpuss.swj_swo_tdo     (SWO DATA)
+    P7_0  ACT #14 cpuss.trace_clock     (ETM/SWO TRACECLK)
+    P9_3  ACT #15 cpuss.trace_data[0]:0 (ETM TRACEDATA[0])
+    P9_2  ACT #15 cpuss.trace_data[1]:0 (ETM TRACEDATA[1])
+    P9_1  ACT #15 cpuss.trace_data[2]:0 (ETM TRACEDATA[2])
+    P9_0  ACT #15 cpuss.trace_data[3]:0 (ETM TRACEDATA[3])
+  Copy 1
+    P10_3 ACT #15 cpuss.trace_data[0]:1 (ETM TRACEDATA[0])
+    P10_2 ACT #15 cpuss.trace_data[1]:1 (ETM TRACEDATA[1])
+    P10_1 ACT #15 cpuss.trace_data[2]:1 (ETM TRACEDATA[2])
+    P10_0 ACT #15 cpuss.trace_data[3]:1 (ETM TRACEDATA[3])
+  Copy 2
+    P7_7  ACT #15 cpuss.trace_data[0]:2 (ETM TRACEDATA[0])
+    P7_6  ACT #15 cpuss.trace_data[1]:2 (ETM TRACEDATA[1])
+    P7_5  ACT #15 cpuss.trace_data[2]:2 (ETM TRACEDATA[2])
+    P7_4  ACT #15 cpuss.trace_data[3]:2 (ETM TRACEDATA[3])
+  See 'Multiple Alternate Functions' table in device datasheet.
+
+  Examples:
+  1) CY8CKIT-062-WIFI-BT Pioneer Kit, J12:
+     TCLK => P7_0, TD0 => P9_3, TD1 => P7_6, TD2 => P7_5, TD3 => P7_4  
+*/
+
+/* Global variables */
+U32 _IS_TRACE_CONFIGURED = 0x0;
+
+/* Trace clock setup registers */
+__constant U32 _PERI_CLOCK_CTL50_ADDR       = 0x40000CC8; // Clock control register for cpuss.clock_trace_in
+__constant U32 _PERI_CLOCK_CTL_DIV_SEL_MASK = 0x0000000F; // PERI_CLOCK_CTL.DIV_SEL
+__constant U32 _PERI_DIV_8_CTL0_ADDR        = 0x40001000; // Divider control (for 8.0 divider)
+__constant U32 _PERI_DIV_CMD_ADDR           = 0x40000400; // Divider command
+__constant U32 _PERI_DIV_CMD_ENABLE_MASK    = 0x80000000; // ENABLE field in PERI_DIV_CMD
+__constant U32 _PERI_DIV_CMD_DISABLE_MASK   = 0x40000000; // DISABLE field in PERI_DIV_CMD
+__constant U32 _PERI_DIV_CMD_PA_SEL_ROL     = 0x00000010; // PA_TYPE_SEL + PA_DIV_SEL fields offset in PERI_DIV_CMD
+__constant U32 _PERI_DIV_PA_SEL_MASK        = 0x000003FF; // PA_TYPE_SEL + PA_DIV_SEL fields mask (size)
+/* Trace pins setup registers */
+__constant U32 _HSIOM_PRT7_PORT_SEL0        = 0x40300070; // Port 7 selection 0
+__constant U32 _HSIOM_PRT9_PORT_SEL0        = 0x40300090; // Port 9 selection 0
+__constant U32 _HSIOM_PRT10_PORT_SEL0       = 0x403000A0; // Port 10 selection 0
+__constant U32 _GPIO_PRT7_CFG               = 0x403103C4; // Port 7 configuration
+__constant U32 _GPIO_PRT9_CFG               = 0x403104C4; // Port 9 configuration
+__constant U32 _GPIO_PRT10_CFG              = 0x40310544; // Port 10 configuration
+__constant U32 _GPIO_PRT7_CFG_OUT           = 0x403103CC; // Port 7 output buffer configuration
+__constant U32 _GPIO_PRT9_CFG_OUT           = 0x403104CC; // Port 9 output buffer configuration
+__constant U32 _GPIO_PRT10_CFG_OUT          = 0x4031054C; // Port 10 output buffer configuration
+__constant U32 _PRT_IO_SEL_MASK             = 0x1F; // Mask for IO[pin]_SEL field in HSIOM_PRT[port]_PORT_SEL[0/1] register
+__constant U32 _PRT_DRIVE_MODE_MASK         = 0xF;  // Mask for IN_EN[pin] & DRIVE_MODE[pin] fields in GPIO_PRT[port]_CFG register
+__constant U32 _PRT_SLOW_MASK               = 0x1;  // Mask for SLOW[pin] field in GPIO_PRT[port]_CFG_OUT register
+__constant U32 _PRT_DRIVE_SEL_MASK          = 0x3;  // Mask for DRIVE_SEL[pin] field in GPIO_PRT[port]_CFG_OUT register
+
+/*********************************************************************
+*
+*       Local functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+* _SetupTraceClock() - Selects TPIU Clock divider for ETM Trace.
+*/
+int _SetupTraceClock(void) {	
+  U32 ClockCtlVal;
+  U32 ClockDivCtlVal;
+  U32 ClockDivSel;
+  U32 ClockDivVal;
+  U32 ClockDivCmd;
+  U32 TRACE_CLOCK_CTL_ADDR;
+  U32 TRACE_CLOCK_DIV_CTL_ADDR;
+  U32 TRACE_CLOCK_DIV_CMD_ADDR;
+  
+  TRACE_CLOCK_CTL_ADDR     = _PERI_CLOCK_CTL50_ADDR;
+  TRACE_CLOCK_DIV_CTL_ADDR = _PERI_DIV_8_CTL0_ADDR;
+  TRACE_CLOCK_DIV_CMD_ADDR = _PERI_DIV_CMD_ADDR;
+
+  ClockDivSel = (7 & _PERI_CLOCK_CTL_DIV_SEL_MASK); // Peripheral clock divider index to use for trace clock
+  ClockDivVal = (0 & _PERI_DIV_PA_SEL_MASK);        // Peripheral clock divider value for trace clock
+                                                    // Actual divider is (1+ClockDivVal)
+
+  ClockCtlVal = JLINK_MEM_ReadU32(TRACE_CLOCK_CTL_ADDR);
+  ClockDivCtlVal = JLINK_MEM_ReadU32(TRACE_CLOCK_DIV_CTL_ADDR + (ClockDivSel*4));
+  if((ClockCtlVal != ClockDivSel) || (ClockDivCtlVal != ((ClockDivVal << _PERI_DIV_CMD_PA_SEL_ROL) | 0x1))){
+    JLINK_SYS_Report("JLinkScript/Trace: Setup TPIU clock");
+    //
+    // Select TPIU Clock divider
+    //
+    
+    // DISABLE 8.0 DIV in PERI_DIV_CMD:
+    ClockDivCmd = _PERI_DIV_CMD_DISABLE_MASK | (_PERI_DIV_PA_SEL_MASK << _PERI_DIV_CMD_PA_SEL_ROL) | ClockDivSel;
+    JLINK_MEM_WriteU32(TRACE_CLOCK_DIV_CMD_ADDR, ClockDivCmd);
+    // Use selected divider (8.0) for cpuss.clock_trace_in
+    JLINK_MEM_WriteU32(TRACE_CLOCK_CTL_ADDR, ClockDivSel);
+    // Set 8.0 DIV = ClockDivVal
+    JLINK_MEM_WriteU32((TRACE_CLOCK_DIV_CTL_ADDR+(ClockDivSel*4)), (ClockDivVal << 8));
+    // ENABLE 8.0 DIV 
+    ClockDivCmd = _PERI_DIV_CMD_ENABLE_MASK | (_PERI_DIV_PA_SEL_MASK << _PERI_DIV_CMD_PA_SEL_ROL) | ClockDivSel;
+    JLINK_MEM_WriteU32(TRACE_CLOCK_DIV_CMD_ADDR, ClockDivCmd);
+  }
+
+  return 0;  
+}
+
+/*********************************************************************
+*
+* _SetupTracePin() - Configures Trace Pin.
+* Parameters:
+*   pin:                  Pin number
+*   hsiomPrtPortSel0Addr: HSIOM_PRT[port]_PORT_SEL0 register address
+*   ioSelVal:             IO[pin]_SEL field value (connection) for HSIOM_PRT[port]_PORT_SEL register
+*   gpioPrtCfgAddr:       GPIO_PRT[port]_CFG register address
+*   gpioPrtCfgOutAddr:    GPIO_PRT[port]_CFG_OUT register address
+*/
+int _SetupTracePin(U32 pin,
+                   U32 hsiomPrtPortSel0Addr, U32 ioSelVal,
+                   U32 gpioPrtCfgAddr,
+                   U32 gpioPrtCfgOutAddr) {	
+  U32 reg0;
+  U32 reg1;
+  U32 offset;
+  U32 hsiomRegAddr; // Address of HSIOM_PRT[port]_PORT_SEL0 or HSIOM_PRT[port]_PORT_SEL1
+  U32 pMode;        // pin drive mode
+  U32 pSlew;        // pin slew rate
+  U32 pStrange;     // pin drive strange
+  
+  //
+  // Select pin route connection in HSIOM_PRT[port]_PORT_SEL[0/1] register
+  // See HSIOM_PRT0_PORT_SEL0 in registers TRM for the bit-field map of HSIOM_PRT[port]_PORT_SEL0 registers
+  // See HSIOM_PRT2_PORT_SEL1 in registers TRM for the bit-field map of HSIOM_PRT[port]_PORT_SEL1 registers
+  if (pin < 4) { /* Pin[0-3] selection is in HSIOM_PRT[port]_PORT_SEL0 register */
+    hsiomRegAddr = hsiomPrtPortSel0Addr; // Use HSIOM_PRT[port]_PORT_SEL0
+    offset = pin * 8; // Offset of the IO[pin]_SEL field for required pin number,
+                      // where 8 = 5 bits for IO[pin]_SEL field + 3 not used bits
+  }
+  else { /* Pin[4-7] selection is in HSIOM_PRT[port]_PORT_SEL1 register */
+    hsiomRegAddr = hsiomPrtPortSel0Addr + 4; // Use HSIOM_PRT[port]_PORT_SEL1
+    offset = (pin - 4) * 8; // Offset of the IO[pin]_SEL field for required pin number,
+                            // where 8 = 5 bits for IO[pin]_SEL field + 3 not used bits
+  }
+  reg0 = JLINK_MEM_ReadU32(hsiomRegAddr);
+  reg1 = reg0;
+  reg1 &= ~(_PRT_IO_SEL_MASK << offset); // Clear IO[pin]_SEL field
+  reg1 |=  (ioSelVal         << offset); // Set field value
+  if (reg0 |= reg1) {
+    JLINK_MEM_WriteU32(hsiomRegAddr, reg1);
+  }
+  
+  //
+  // Disable input buffer and set drive mode in GPIO_PRT[port]_CFG register
+  // See GPIO_PRT2_CFG in registers TRM for the bit-field map:
+  pMode = 6;      // DRIVE_MODE[pin]:
+                  //  0: HIGHZ:         Output buffer is off creating a high impedance input (default)
+                  //  1: RESERVED:      This mode is reserved and should not be used
+                  //  2: PULLUP:        Resistive pull up
+                  //  3: PULLDOWN:      Resistive pull down
+                  //  4: OD_DRIVESLOW:  Open drain, drives low
+                  //  5: OD_DRIVESHIGH: Open drain, drives high
+                  //  6: STRONG:        Strong D_OUTput buffer
+                  //  7: PULLUP_DOWN:   Pull up or pull down
+  reg0 = JLINK_MEM_ReadU32(gpioPrtCfgAddr);
+  reg1 = reg0;
+  offset = pin * 4; // Offset of the DRIVE_MODE[pin] field for required pin number,
+                    // where 4 = 3 bits for DRIVE_MODE[pin] + 1 bit for IN_EN fields
+  reg1 &= ~(_PRT_DRIVE_MODE_MASK << offset); // Clear IN_EN[pin] and DRIVE_MODE[pin] fields
+  reg1 |=  (pMode                << offset); // Set DRIVE_MODE[pin] field value
+  if (reg0 |= reg1) {
+    JLINK_MEM_WriteU32(gpioPrtCfgAddr, reg1);
+  }
+  
+  //
+  // Set slew rate and drive strength in GPIO_PRT[port]_CFG_OUT register
+  // See GPIO_PRT2_CFG_OUT in registers TRM for the bit-field map:
+  pSlew = 0x0;    // SLOW[pin]:  
+                  //  0 - Fast slew rate (default)
+                  //  1 - Slow slew rate
+  pStrange = 0x3; // DRIVE_SEL[pin]:  
+                  //  0 - FULL_DRIVE:        Full drive strength: GPIO drives current at its max rated spec.
+                  //  1 - ONE_HALF_DRIVE:    1/2 drive strength: GPIO drives current at 1/2 of its max rated spec (default)
+                  //  2 - ONE_QUARTER_DRIVE: 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
+                  //  3 - ONE_EIGHTH_DRIVE:  1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
+  reg0 = JLINK_MEM_ReadU32(gpioPrtCfgOutAddr);
+  reg1 = reg0;
+  offset = pin;
+  reg1 &= ~(_PRT_SLOW_MASK << offset); // Clear SLOW[pin] field
+  reg1 |=  (pSlew          << offset); // Set field value
+  offset = 16 + pin * 2;               // Offset of the DRIVE_SEL[pin] field for required pin number,
+                                       // where '16' is the offset of DRIVE_SEL[pin] for pin 0 and '2' is the size of DRIVE_SEL[pin]
+  reg1 &= ~(_PRT_DRIVE_SEL_MASK << offset); // Clear DRIVE_SEL[pin] field
+  reg1 |=  (pStrange            << offset); // Set field value
+  if (reg0 |= reg1) {
+    JLINK_MEM_WriteU32(gpioPrtCfgOutAddr, reg1);
+  }
+  
+  return 0;
+}
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+
+int ConfigTargetSettings(void) {
+  //
+  // Mark a specific memory region as memory type illegal
+  // in order to make sure that the software is not allowed to access these regions
+  // 
+  // Note: This does not work for J-Flash tool
+  //
+
+  // Exclude SFLASH regions
+  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+
+  // Exclude Cy Metadata
+  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+}
+
+void InitTarget(void) {
+  Report("JLinkScript/InitTarget: CORESIGHT setup");
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // SYSAP
+  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M0+ core
+  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M4 core
+  CORESIGHT_IndexAHBAPToUse = 2;
+  CPU=CORTEX_M4;
+}
+
+/*********************************************************************
+*
+*       OnTraceStart()
+*
+*  Function description
+*    If present, called right before trace is started.
+*    Used to initialize MCU specific trace related things like configuring the trace pins for alternate function.
+*
+*  Return value
+*    >= 0:  O.K.
+*     < 0:  Error
+*
+*  Notes
+*    (1) May use high-level API functions like JLINK_MEM_ etc.
+*    (2) Should not call JLINK_TARGET_Halt(). Can rely on target being halted when entering this function
+*/
+int OnTraceStart(void) {
+  U32 PortWidth;
+  U32 IO_SEL_ACT14;
+  U32 IO_SEL_ACT15;
+  //U32 IO_SEL_DS5;
+
+  if (_IS_TRACE_CONFIGURED) {
+	  return 0;
+  }
+
+  // Adjust sampling point of trace pin (Optional: not needed for this cpu)
+  // JLINK_ExecCommand("TraceSampleAdjust TD=2000");   
+  
+  // Setup peripheral clocks for tracing
+  _SetupTraceClock();     
+  
+  // Setup pins for tracing: TCLK > P7_0, TD0 > P9_3, TD1 > P7_6, TD2 > P7_5, TD3 > P7_4
+  PortWidth = JLINK_TRACE_PortWidth;      
+  JLINK_SYS_Report("JLinkScript/Trace: Setup clock and data pins");
+  IO_SEL_ACT14 = 0x1A; // Connection route for 'cpuss.trace_clock' signal (P7_0)
+  IO_SEL_ACT15 = 0x1B; // Connection route for 'cpuss.trace_data[0-3]' signals (P7, P9 and P10)
+  //IO_SEL_DS5 =   0x1D; // Connection route for 'cpuss.swj_swo_tdo' signal (P6_4)
+
+  _SetupTracePin( /*P7_0*/ 0, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT14, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);
+  _SetupTracePin( /*P9_3*/ 3, _HSIOM_PRT9_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT9_CFG, _GPIO_PRT9_CFG_OUT);
+  _SetupTracePin( /*P7_6*/ 6, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);  
+  if (PortWidth > 2) {
+    _SetupTracePin( /*P7_5*/ 5, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);  
+    _SetupTracePin( /*P7_4*/ 4, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);  
+  }
+  
+  _IS_TRACE_CONFIGURED = 1;
+  return 0;
+}
+

Devices/Cypress/PSoC6/version.dat

@@ -0,0 +1 @@
+2.2.0.87

Devices/NXP/LPC5411x/LPC5411x_M0.JLinkScript

@@ -1,32 +0,0 @@
-/*********************************************************************
-*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
-*                        The Embedded Experts                        *
-*                           www.segger.com                           *
-**********************************************************************
-
--------------------------- END-OF-HEADER -----------------------------
-
-File    : LPC5411x_M0.JLinkScript
-Purpose : Script file for NXP LPC5411 series that has a Cortex-M4 and Cortex-M0+ in it.
-          This script connects to the M0+
-Literature:
-  [1]  J-Link User Guide
-
-Additional information:
-  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
-*/
-
-
-/*********************************************************************
-*
-*       InitTarget
-*/
-void InitTarget(void) {
-  //
-  // Set AP register layout
-  // Usually only needed if core is not accessible via the first AHB-AP / APB-AP found
-  //
-  JLINK_CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);              // AHB-AP (Cortex-M4)
-  JLINK_CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);              // AHB-AP (Cortex-M0+)
-  CORESIGHT_IndexAHBAPToUse = 1;
-}

Devices/NXP/iMX7ULP/NXP_iMX7ULP_CortexM4.JLinkScript

@@ -24,9 +24,9 @@ void ResetTarget(void) {
 *       InitTarget
 */
 void InitTarget(void) { 
-  Report("***************************************************");
-  Report("J-Link script: iMX7ULP Cortex-M4 core J-Link script");
-  Report("***************************************************");
+  JLINK_SYS_Report("***************************************************");
+  JLINK_SYS_Report("J-Link script: iMX7ULP Cortex-M4 core J-Link script");
+  JLINK_SYS_Report("***************************************************");
   JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
   CPU = CORTEX_M4;                                                              // Pre-select that we have a Cortex-M4 connected
   JTAG_AllowTAPReset = 0;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
@@ -53,4 +53,10 @@ void SetupTarget(void) {
   //  Map alias area of M4 core for flash to 0x04000000 instead of 0xC0000000 as in certain circumstances the 0xC0000000 is not initialized
   //
   JLINK_ExecCommand("map add 0xC0000000-0xC7FFFFFF A FLASH 0x04000000 0x07FFFFFF");
+  //
+  // The MPU causes problems during flash download
+  // This fix has been requested by NXP
+  //
+  JLINK_SYS_Report("Disabling Cortex-M4 MPU ...");
+  MEM_WriteU32(0xE000ED94, 0x00000000);
 }

Devices/NXP/iMX8M/NXP_iMX8M_Connect_CortexM4.JLinkScript

@@ -0,0 +1,97 @@
+/*********************************************************************
+*               (c) SEGGER Microcontroller GmbH & Co. KG             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  //
+  // This device requires a special reset as default reset does not work for this device.
+  // TBD
+  //
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) {
+  int v;
+  int Ctrl;
+  int CSGPR_ADDR;
+  int DP_REG_CTRL_STAT;
+  int DP_REG_SELECT;
+  int AHBAP_REG_CTRL;
+  int AHBAP_REG_ADDR;
+  int AHBAP_REG_DATA;
+
+  DP_REG_CTRL_STAT = 1;
+  DP_REG_SELECT    = 2;
+  AHBAP_REG_CTRL   = 0;
+  AHBAP_REG_ADDR   = 1;
+  AHBAP_REG_DATA   = 3;
+
+  Report("***************************************************");
+  Report("J-Link script: iMX8M Quad Cortex-M4 J-Link script");
+  Report("***************************************************");
+  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
+  CPU = CORTEX_M4;                                                              // Pre-select that we have a Cortex-M4 connected
+  JTAG_AllowTAPReset = 0;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
+
+  //
+  // Power-up complete DAP
+  //
+  Ctrl = 0
+       | (1 << 30)    // System power-up
+       | (1 << 28)    // Debug popwer-up
+       | (1 << 5)     // Clear STICKYERR
+       ;
+  JLINK_CORESIGHT_WriteDP(DP_REG_CTRL_STAT, Ctrl);
+
+  //
+  // Select AHB-AP and configure it
+  //
+  JLINK_CORESIGHT_WriteDP(DP_REG_SELECT, (0 << 4) | (0 << 24));
+  Ctrl =  0
+      | (2 << 0)    // AP-access size. Fixed to 2: 32-bit
+      | (1 << 4)    // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
+      | (1 << 31)   // Enable software access to the Debug APB bus.
+      ;
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_CTRL, Ctrl);
+
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, 0x007E0000);
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, 0x20008000);
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, 0x007E0004);
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, 0x1FFE0009);
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, 0x007E0008);
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, 0xE7FEE7FE);
+
+  //
+  // Manually configure which APs are present on the CoreSight device
+  //
+  JTAG_SetDeviceId(0, 0x5BA00477);  // 4-bits IRLen
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // AXI-AP
+  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);  // APB-AP for CA53
+  CORESIGHT_AddAP(2, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(3, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(4, CORESIGHT_AHB_AP);  // AHB-AP
+
+  CORESIGHT_IndexAHBAPToUse = 4;
+}
+
+/*********************************************************************
+*
+*       SetupTarget
+*/
+void SetupTarget(void)
+{
+  JLINK_MEM_WriteU32(0x3039000C, 0x000000A8);
+  JLINK_MEM_WriteU32(0x3039000C, 0x000000AA);
+}

Devices/NXP/iMX8M/Readme_NXP.txt

@@ -0,0 +1,2 @@
+The NXP devices support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via NXP only.
+For support, please get in contact with NXP directly: https://www.nxp.com/support/support:SUPPORTHOME

Devices/NXP/iMX8MM/NXP_iMX8M_Connect_CortexM4.JLinkScript

@@ -0,0 +1,97 @@
+/*********************************************************************
+*               (c) SEGGER Microcontroller GmbH & Co. KG             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  //
+  // This device requires a special reset as default reset does not work for this device.
+  // TBD
+  //
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) {
+  int v;
+  int Ctrl;
+  int CSGPR_ADDR;
+  int DP_REG_CTRL_STAT;
+  int DP_REG_SELECT;
+  int AHBAP_REG_CTRL;
+  int AHBAP_REG_ADDR;
+  int AHBAP_REG_DATA;
+
+  DP_REG_CTRL_STAT = 1;
+  DP_REG_SELECT    = 2;
+  AHBAP_REG_CTRL   = 0;
+  AHBAP_REG_ADDR   = 1;
+  AHBAP_REG_DATA   = 3;
+
+  Report("***************************************************");
+  Report("J-Link script: iMX8M Mini Cortex-M4 J-Link script");
+  Report("***************************************************");
+  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
+  CPU = CORTEX_M4;                                                              // Pre-select that we have a Cortex-M4 connected
+  JTAG_AllowTAPReset = 0;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
+
+  //
+  // Power-up complete DAP
+  //
+  Ctrl = 0
+       | (1 << 30)    // System power-up
+       | (1 << 28)    // Debug popwer-up
+       | (1 << 5)     // Clear STICKYERR
+       ;
+  JLINK_CORESIGHT_WriteDP(DP_REG_CTRL_STAT, Ctrl);
+
+  //
+  // Select AHB-AP and configure it
+  //
+  JLINK_CORESIGHT_WriteDP(DP_REG_SELECT, (0 << 4) | (0 << 24));
+  Ctrl =  0
+      | (2 << 0)    // AP-access size. Fixed to 2: 32-bit
+      | (1 << 4)    // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
+      | (1 << 31)   // Enable software access to the Debug APB bus.
+      ;
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_CTRL, Ctrl);
+
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, 0x007E0000);
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, 0x20008000);
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, 0x007E0004);
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, 0x1FFE0009);
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, 0x007E0008);
+  JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, 0xE7FEE7FE);
+
+  //
+  // Manually configure which APs are present on the CoreSight device
+  //
+  JTAG_SetDeviceId(0, 0x5BA00477);  // 4-bits IRLen
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // AXI-AP
+  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);  // APB-AP for CA53
+  CORESIGHT_AddAP(2, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(3, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(4, CORESIGHT_AHB_AP);  // AHB-AP
+
+  CORESIGHT_IndexAHBAPToUse = 4;
+}
+
+/*********************************************************************
+*
+*       SetupTarget
+*/
+void SetupTarget(void)
+{
+  JLINK_MEM_WriteU32(0x3039000C, 0x000000A8);
+  JLINK_MEM_WriteU32(0x3039000C, 0x000000AA);
+}

Devices/NXP/iMX8MM/Readme_NXP.txt

@@ -0,0 +1,2 @@
+The NXP devices support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via NXP only.
+For support, please get in contact with NXP directly: https://www.nxp.com/support/support:SUPPORTHOME

Devices/NXP/iMX8MN/NXP_iMX8M_Connect_CortexM7.JLinkScript

@@ -0,0 +1,69 @@
+/*********************************************************************
+*               (c) SEGGER Microcontroller GmbH & Co. KG             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  //
+  // This device requires a special reset as default reset does not work for this device.
+  // TBD
+  //
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) {
+  // No need to configure debug config here, SEGGER will do auto scan 
+
+  // clear sticky error flag
+  U32 v;
+  // v = _DP_CTRL_STAT_BIT_DBGPWRUPREQ | _DP_CTRL_STAT_BIT_SYSPWRUPREQ | _DP_CTRL_STAT_BIT_STICKYERR; // Clear sticky error flag
+  v = (1<<28) | (1<<30) | (1 << 5);
+  JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, v);
+
+  // Check DAP successful
+  v = JLINK_CORESIGHT_ReadDP(JLINK_CORESIGHT_DP_REG_CTRL_STAT);
+  if (((v >> 28) & 0xF) != 0xF) {
+    return -1;
+  }
+  Report("***************************************************");
+  Report("J-Link script: iMX8M Nano Cortex-M7 J-Link script");
+  Report("***************************************************");
+  // AHB32 Read Register
+  JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (0 << 24));
+  // JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _DAP_ACC_32BIT_NO_AUTO_INC);
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0x3039000C);
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0xAA);
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0x3039000C);
+  v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA);
+  Report1("****** Reset Release with M7_RCR : ", v);
+}
+
+/*********************************************************************
+*
+*       SetupTarget
+*/
+void SetupTarget(void)
+{
+  Report("***************************************************");
+  Report("J-Link script: Prepare Landing Zone");
+  Report("***************************************************");
+  JLINK_MEM_WriteU32(0x7E0000, 0x20020000);
+  JLINK_MEM_WriteU32(0x7E0004, 0x9);
+  JLINK_MEM_WriteU32(0x7E0008, 0xE7FEE7FE);
+
+  Report("***************************************************");
+  Report("J-Link script: Release Wait");
+  Report("***************************************************");
+  JLINK_MEM_WriteU32(0x30340058, 0x0000000);
+}

Devices/NXP/iMX8MN/Readme_NXP.txt

@@ -0,0 +1,2 @@
+The NXP devices support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via NXP only.
+For support, please get in contact with NXP directly: https://www.nxp.com/support/support:SUPPORTHOME

Devices/NXP/iMX8QM/NXP_iMX8QM_Connect_CortexM4_0.JLinkScript

@@ -0,0 +1,114 @@
+/*********************************************************************
+*               (c) SEGGER Microcontroller GmbH & Co. KG             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  //
+  // This device requires a special reset as default reset does not work for this device.
+  // TBD
+  //
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) {
+  int v;
+  int Ctrl;
+  int CSGPR_ADDR;
+  int DP_REG_CTRL_STAT;
+  int DP_REG_SELECT;
+  int APBAP_REG_CTRL;
+  int APBAP_REG_ADDR;
+  int APBAP_REG_DATA;
+
+  CSGPR_ADDR         = 0x80070000;
+  DP_REG_CTRL_STAT   = 1;
+  DP_REG_SELECT      = 2;
+  APBAP_REG_CTRL     = 0;
+  APBAP_REG_ADDR     = 1;
+  APBAP_REG_DATA     = 3;
+
+  Report("***************************************************");
+  Report("J-Link script: iMX8QM Cortex-M4 core0 J-Link script");
+  Report("***************************************************");
+  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
+  CPU = CORTEX_M4;                                                              // Pre-select that we have a Cortex-M4 connected
+  JTAG_AllowTAPReset = 0;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
+
+  //
+  // Power-up complete DAP
+  //
+  Ctrl = 0
+       | (1 << 30)    // System power-up
+       | (1 << 28)    // Debug popwer-up
+       | (1 << 5)     // Clear STICKYERR
+       ;
+  JLINK_CORESIGHT_WriteDP(DP_REG_CTRL_STAT, Ctrl);
+
+  //
+  // Select AHB-AP and configure it
+  //
+  JLINK_CORESIGHT_WriteDP(DP_REG_SELECT, (0 << 4) | (6 << 24));
+  JLINK_CORESIGHT_WriteAP(APBAP_REG_CTRL, (2 << 0) | (1 << 31));
+
+  // Kick off M4_0
+  JLINK_CORESIGHT_WriteAP(APBAP_REG_ADDR, CSGPR_ADDR);
+  v = JLINK_CORESIGHT_ReadAP(APBAP_REG_DATA);
+  v |= 1 << 6;
+  JLINK_CORESIGHT_WriteAP(APBAP_REG_ADDR, CSGPR_ADDR);
+  JLINK_CORESIGHT_WriteAP(APBAP_REG_DATA, v);
+
+  // Wait 100ms to make sure M4_0 wakeup
+  SYS_Sleep(100);
+
+  //
+  // Manually configure which APs are present on the CoreSight device
+  //
+  JTAG_SetDeviceId(0, 0x5BA00477);  // 4-bits IRLen
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // AXI-AP
+  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // SCU-AP
+  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // CM4-0-AP
+  CORESIGHT_AddAP(3, CORESIGHT_AHB_AP);  // CM4-1-AP
+  CORESIGHT_AddAP(4, CORESIGHT_AHB_AP);  // CM0+-AP
+  CORESIGHT_AddAP(6, CORESIGHT_APB_AP);  // APB-AP for CA72/CA53
+
+  CORESIGHT_IndexAHBAPToUse = 2;
+}
+
+/*********************************************************************
+*
+*       SetupTarget
+*/
+void SetupTarget(void)
+{
+  // Configure LMEM Parity/ECC Control Register
+  //
+  // Note: ECC Multi-bit IRQ should be disabled
+  //       prior to list/dump of locations that
+  //       have not been written to avoid vectoring
+  //       to the NMI
+  //
+  // 31:22 RESERVED
+  // 21    Enable Cache Parity IRQ
+  // 20    Enable Cache Parity Report
+  // 19:17 RESERVED
+  // 16    Enable RAM Parity Reporting
+  // 15:10 RESERVED
+  // 9     Enable RAM ECC 1-bit IRQ
+  // 8     Enable RAM ECC 1-bit Report
+  // 7:2   RESERVED
+  // 1     Enable RAM ECC Multi-bit IRQ
+  // 0     Enable RAM ECC Multi-bit
+  JLINK_MEM_WriteU32(0xE0080480, 0x0);
+}

Devices/NXP/iMX8QM/NXP_iMX8QM_Connect_CortexM4_1.JLinkScript

@@ -0,0 +1,114 @@
+/*********************************************************************
+*               (c) SEGGER Microcontroller GmbH & Co. KG             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  //
+  // This device requires a special reset as default reset does not work for this device.
+  // TBD
+  //
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) {
+  int v;
+  int Ctrl;
+  int CSGPR_ADDR;
+  int DP_REG_CTRL_STAT;
+  int DP_REG_SELECT;
+  int APBAP_REG_CTRL;
+  int APBAP_REG_ADDR;
+  int APBAP_REG_DATA;
+
+  CSGPR_ADDR         = 0x80070000;
+  DP_REG_CTRL_STAT   = 1;
+  DP_REG_SELECT      = 2;
+  APBAP_REG_CTRL     = 0;
+  APBAP_REG_ADDR     = 1;
+  APBAP_REG_DATA     = 3;
+
+  Report("***************************************************");
+  Report("J-Link script: iMX8QM Cortex-M4 core1 J-Link script");
+  Report("***************************************************");
+  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
+  CPU = CORTEX_M4;                                                              // Pre-select that we have a Cortex-M4 connected
+  JTAG_AllowTAPReset = 0;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
+
+  //
+  // Power-up complete DAP
+  //
+  Ctrl = 0
+       | (1 << 30)    // System power-up
+       | (1 << 28)    // Debug popwer-up
+       | (1 << 5)     // Clear STICKYERR
+       ;
+  JLINK_CORESIGHT_WriteDP(DP_REG_CTRL_STAT, Ctrl);
+
+  //
+  // Select AHB-AP and configure it
+  //
+  JLINK_CORESIGHT_WriteDP(DP_REG_SELECT, (0 << 4) | (6 << 24));
+  JLINK_CORESIGHT_WriteAP(APBAP_REG_CTRL, (2 << 0) | (1 << 31));
+
+  // Kick off M4_1
+  JLINK_CORESIGHT_WriteAP(APBAP_REG_ADDR, CSGPR_ADDR);
+  v = JLINK_CORESIGHT_ReadAP(APBAP_REG_DATA);
+  v |= 1 << 7;
+  JLINK_CORESIGHT_WriteAP(APBAP_REG_ADDR, CSGPR_ADDR);
+  JLINK_CORESIGHT_WriteAP(APBAP_REG_DATA, v);
+
+  // Wait 100ms to make sure M4_1 wakeup
+  SYS_Sleep(100);
+
+  //
+  // Manually configure which APs are present on the CoreSight device
+  //
+  JTAG_SetDeviceId(0, 0x5BA00477);  // 4-bits IRLen
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // AXI-AP
+  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // SCU-AP
+  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // CM4-0-AP
+  CORESIGHT_AddAP(3, CORESIGHT_AHB_AP);  // CM4-1-AP
+  CORESIGHT_AddAP(4, CORESIGHT_AHB_AP);  // CM0+-AP
+  CORESIGHT_AddAP(6, CORESIGHT_APB_AP);  // APB-AP for CA72/CA53
+
+  CORESIGHT_IndexAHBAPToUse = 3;
+}
+
+/*********************************************************************
+*
+*       SetupTarget
+*/
+void SetupTarget(void)
+{
+  // Configure LMEM Parity/ECC Control Register
+  //
+  // Note: ECC Multi-bit IRQ should be disabled
+  //       prior to list/dump of locations that
+  //       have not been written to avoid vectoring
+  //       to the NMI
+  //
+  // 31:22 RESERVED
+  // 21    Enable Cache Parity IRQ
+  // 20    Enable Cache Parity Report
+  // 19:17 RESERVED
+  // 16    Enable RAM Parity Reporting
+  // 15:10 RESERVED
+  // 9     Enable RAM ECC 1-bit IRQ
+  // 8     Enable RAM ECC 1-bit Report
+  // 7:2   RESERVED
+  // 1     Enable RAM ECC Multi-bit IRQ
+  // 0     Enable RAM ECC Multi-bit
+  JLINK_MEM_WriteU32(0xE0080480, 0x0);
+}

Devices/NXP/iMX8QM/Readme_NXP.txt

@@ -0,0 +1,2 @@
+The NXP devices support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via NXP only.
+For support, please get in contact with NXP directly: https://www.nxp.com/support/support:SUPPORTHOME

Devices/NXP/iMX8QX/NXP_iMX8QX_Connect_CortexM4.JLinkScript

@@ -0,0 +1,113 @@
+/*********************************************************************
+*               (c) SEGGER Microcontroller GmbH & Co. KG             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  //
+  // This device requires a special reset as default reset does not work for this device.
+  // TBD
+  //
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) {
+  int v;
+  int Ctrl;
+  int CSGPR_ADDR;
+  int DP_REG_CTRL_STAT;
+  int DP_REG_SELECT;
+  int APBAP_REG_CTRL;
+  int APBAP_REG_ADDR;
+  int APBAP_REG_DATA;
+
+  CSGPR_ADDR         = 0x80070000;
+  DP_REG_CTRL_STAT   = 1;
+  DP_REG_SELECT      = 2;
+  APBAP_REG_CTRL     = 0;
+  APBAP_REG_ADDR     = 1;
+  APBAP_REG_DATA     = 3;
+
+  Report("***************************************************");
+  Report("J-Link script: iMX8QX Cortex-M4 core0 J-Link script");
+  Report("***************************************************");
+  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
+  CPU = CORTEX_M4;                                                              // Pre-select that we have a Cortex-M4 connected
+  JTAG_AllowTAPReset = 0;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
+
+  //
+  // Power-up complete DAP
+  //
+  Ctrl = 0
+       | (1 << 30)    // System power-up
+       | (1 << 28)    // Debug popwer-up
+       | (1 << 5)     // Clear STICKYERR
+       ;
+  JLINK_CORESIGHT_WriteDP(DP_REG_CTRL_STAT, Ctrl);
+
+  //
+  // Select AHB-AP and configure it
+  //
+  JLINK_CORESIGHT_WriteDP(DP_REG_SELECT, (0 << 4) | (4 << 24));
+  JLINK_CORESIGHT_WriteAP(APBAP_REG_CTRL, (2 << 0) | (1 << 31));
+
+  // Kick off M4_0
+  JLINK_CORESIGHT_WriteAP(APBAP_REG_ADDR, CSGPR_ADDR);
+  v = JLINK_CORESIGHT_ReadAP(APBAP_REG_DATA);
+  v |= 1 << 6;
+  JLINK_CORESIGHT_WriteAP(APBAP_REG_ADDR, CSGPR_ADDR);
+  JLINK_CORESIGHT_WriteAP(APBAP_REG_DATA, v);
+
+  // Wait 100ms to make sure M4_0 wakeup
+  SYS_Sleep(100);
+
+  //
+  // Manually configure which APs are present on the CoreSight device
+  //
+  JTAG_SetDeviceId(0, 0x5BA00477);  // 4-bits IRLen
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // AXI-AP
+  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // SCU-AP
+  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // CM4-0-AP
+  CORESIGHT_AddAP(3, CORESIGHT_AHB_AP);  // CM0+
+  CORESIGHT_AddAP(4, CORESIGHT_APB_AP);  // APB-AP for CA53
+
+  CORESIGHT_IndexAHBAPToUse = 2;
+}
+
+/*********************************************************************
+*
+*       SetupTarget
+*/
+void SetupTarget(void)
+{
+  // Configure LMEM Parity/ECC Control Register
+  //
+  // Note: ECC Multi-bit IRQ should be disabled
+  //       prior to list/dump of locations that
+  //       have not been written to avoid vectoring
+  //       to the NMI
+  //
+  // 31:22 RESERVED
+  // 21    Enable Cache Parity IRQ
+  // 20    Enable Cache Parity Report
+  // 19:17 RESERVED
+  // 16    Enable RAM Parity Reporting
+  // 15:10 RESERVED
+  // 9     Enable RAM ECC 1-bit IRQ
+  // 8     Enable RAM ECC 1-bit Report
+  // 7:2   RESERVED
+  // 1     Enable RAM ECC Multi-bit IRQ
+  // 0     Enable RAM ECC Multi-bit
+  JLINK_MEM_WriteU32(0xE0080480, 0x0);
+}

Devices/NXP/iMX8QX/Readme_NXP.txt

@@ -0,0 +1,2 @@
+The NXP devices support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via NXP only.
+For support, please get in contact with NXP directly: https://www.nxp.com/support/support:SUPPORTHOME