STM32_Prog_DB_0x484.xml 91 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x484</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M33</CPU>
  8. <Name>STM32H5xx</Name>
  9. <Series>STM32H5</Series>
  10. <Description>ARM 32-bit Cortex-M33 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- dual Bank non secure -->
  15. <TZEN reference="0x0"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xC3000000"/> </TZEN>
  16. </Configuration>
  17. <Configuration number="0x1"> <!-- Dual Bank secure -->
  18. <TZEN reference="0x1"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xB4000000"/> </TZEN>
  19. </Configuration>
  20. </Interface>
  21. <!-- Bootloader Interface -->
  22. <Interface name="Bootloader">
  23. <Configuration number="0x2"> <!-- Dual Bank Secure-->
  24. <TZEN reference="0x1"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xB4000000"/> </TZEN>
  25. </Configuration>
  26. <Configuration number="0x3"> <!-- Dual Bank non Secure-->
  27. <TZEN reference="0x0"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xC3000000"/> </TZEN>
  28. </Configuration>
  29. </Interface>
  30. </Configurations>
  31. <!-- Peripherals -->
  32. <Peripherals>
  33. <!-- Embedded SRAM -->
  34. <Peripheral>
  35. <Name>Embedded SRAM</Name>
  36. <Type>Storage</Type>
  37. <Description/>
  38. <ErasedValue>0xFF</ErasedValue>
  39. <Access>RWE</Access>
  40. <!-- 96 KB -->
  41. <Configuration config="0,3">
  42. <Parameters address="0x20000000" name="SRAM" size="0x40000"/>
  43. <Description/>
  44. <Organization>Single</Organization>
  45. <Bank name="Bank 1">
  46. <Field>
  47. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x40000"/>
  48. </Field>
  49. </Bank>
  50. </Configuration>
  51. <Configuration config="1,2">
  52. <Parameters address="0x30000000" name="SRAM" size="0x40000"/>
  53. <Description/>
  54. <Organization>Single</Organization>
  55. <Bank name="Bank 1">
  56. <Field>
  57. <Parameters address="0x30000000" name="SRAM" occurence="0x1" size="0x40000"/>
  58. </Field>
  59. </Bank>
  60. </Configuration>
  61. </Peripheral>
  62. <!-- Embedded Flash -->
  63. <Peripheral>
  64. <Name>Embedded Flash</Name>
  65. <Type>Storage</Type>
  66. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  67. <ErasedValue>0xFF</ErasedValue>
  68. <Access>RWE</Access>
  69. <FlashSize address="0x0BFA07A0" default="0x200000"/>
  70. <Configuration config="0,3"> <!-- dual Bank nn secure -->
  71. <Parameters address="0x08000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  72. <Description/>
  73. <Organization>Dual</Organization>
  74. <Allignement>0x10</Allignement>
  75. <Bank name="Bank 1">
  76. <Field>
  77. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  78. </Field>
  79. </Bank>
  80. <Bank name="Bank 2">
  81. <Field>
  82. <Parameters address="0x08100000" name="sector128" occurence="0x80" size="0x2000"/>
  83. </Field>
  84. </Bank>
  85. </Configuration>
  86. <Configuration config="1,2"> <!-- dual Bank secure -->
  87. <Parameters address="0x0c000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  88. <Description/>
  89. <Organization>Dual</Organization>
  90. <Allignement>0x10</Allignement>
  91. <Bank name="Bank 1">
  92. <Field>
  93. <Parameters address="0x0c000000" name="sector0" occurence="0x80" size="0x2000"/>
  94. </Field>
  95. </Bank>
  96. <Bank name="Bank 2">
  97. <Field>
  98. <Parameters address="0x0c100000" name="sector128" occurence="0x80" size="0x2000"/>
  99. </Field>
  100. </Bank>
  101. </Configuration>
  102. </Peripheral>
  103. <!-- Data EEPROM -->
  104. <Peripheral>
  105. <Name>Data EEPROM</Name>
  106. <Type>Storage</Type>
  107. <Description>The Data EEPROM memory block. It contains user data.</Description>
  108. <ErasedValue>0xFF</ErasedValue>
  109. <Access>RWE</Access>
  110. <!-- Dummy Config Just to avoid crash when TZEN=0 -->
  111. <Configuration config="1,3">
  112. <Parameters address="0x0C000000" name=" 2 Mbyte Data EEPROM" size="0x200000"/>
  113. <Description/>
  114. <Organization>Dual</Organization>
  115. <Allignement>0x4</Allignement>
  116. <Bank name="Bank 1">
  117. <Field>
  118. <Parameters address="0x0C000000" name="sector0" occurence="0x80" size="0x2000"/>
  119. </Field>
  120. </Bank>
  121. <Bank name="Bank 2">
  122. <Field>
  123. <Parameters address="0x0C100000" name="sector128" occurence="0x80" size="0x2000"/>
  124. </Field>
  125. </Bank>
  126. </Configuration>
  127. </Peripheral>
  128. <!-- OTP -->
  129. <Peripheral>
  130. <Name>OTP</Name>
  131. <Type>Storage</Type>
  132. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  133. <ErasedValue>0xFF</ErasedValue>
  134. <Access>RW</Access>
  135. <!-- 512 Bytes single bank -->
  136. <Configuration>
  137. <Parameters address="0x0BFA0000" name=" 512 Bytes Data OTP" size="0x200"/>
  138. <Description/>
  139. <Organization>Single</Organization>
  140. <Allignement>0x4</Allignement>
  141. <Bank name="OTP">
  142. <Field>
  143. <Parameters address="0x0BFA0000" name="OTP" occurence="0x1" size="0x200"/>
  144. </Field>
  145. </Bank>
  146. </Configuration>
  147. </Peripheral>
  148. <!-- Option Bytes -->
  149. <Peripheral>
  150. <Name>Option Bytes</Name>
  151. <Type>Configuration</Type>
  152. <Description/>
  153. <Access>RW</Access>
  154. <Configuration config="0,3">
  155. <Bank interface="JTAG_SWD">
  156. <Parameters address="0x40022050" name="Bank 1" size="0x70"/>
  157. <Category>
  158. <Name>Product state</Name>
  159. <Field>
  160. <Parameters address="0x40022050" name="CUR" size="0x4"/>
  161. <AssignedBits>
  162. <Bit>
  163. <Name>PRODUCT_STATE</Name>
  164. <Description>Life state code.</Description>
  165. <BitOffset>0x8</BitOffset>
  166. <BitWidth>0x8</BitWidth>
  167. <Access>R</Access>
  168. <Values>
  169. <Val value="0xB4">ST-VIRGIN</Val>
  170. <Val value="0x39">ST-OPEN</Val>
  171. <Val value="0x4B">ST-SFI-READY</Val>
  172. <Val value="0xED">ST-ROT-READY</Val>
  173. <Val value="0x17">OEM-provisioning</Val>
  174. <Val value="0x2E">OEM-provisioned</Val>
  175. <Val value="0xC6">TZ-OEM-Closed</Val>
  176. <Val value="0x72">OEM-Closed</Val>
  177. <Val value="0x5C">OEM-Locked</Val>
  178. <Val value="0x9A">OEM-Unconstrained-Debug</Val>
  179. <Val value="0xA3">OEM-NS-Unconstrained-Debug</Val>
  180. </Values>
  181. </Bit>
  182. </AssignedBits>
  183. </Field>
  184. <Field>
  185. <Parameters address="0x40022054" name="PRG" size="0x4"/>
  186. <AssignedBits>
  187. <Bit>
  188. <Name>PRODUCT_STATE</Name>
  189. <Description>Life state code.</Description>
  190. <BitOffset>0x8</BitOffset>
  191. <BitWidth>0x8</BitWidth>
  192. <Access>W</Access>
  193. <Values>
  194. <Val value="0xB4">ST-VIRGIN</Val>
  195. <Val value="0x39">ST-OPEN</Val>
  196. <Val value="0x4B">ST-SFI-READY</Val>
  197. <Val value="0xED">ST-ROT-READY</Val>
  198. <Val value="0x17">OEM-provisioning</Val>
  199. <Val value="0x2E">OEM-provisioned</Val>
  200. <Val value="0xC6">TZ-OEM-Closed</Val>
  201. <Val value="0x72">OEM-Closed</Val>
  202. <Val value="0x5C">OEM-Locked</Val>
  203. <Val value="0x9A">OEM-Unconstrained-Debug</Val>
  204. <Val value="0xA3">OEM-NS-Unconstrained-Debug</Val>
  205. </Values>
  206. </Bit>
  207. </AssignedBits>
  208. </Field>
  209. </Category>
  210. <Category>
  211. <Name>BOR Level</Name>
  212. <Field>
  213. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  214. <AssignedBits>
  215. <Bit>
  216. <Name>BOR_LEV</Name>
  217. <Description>Brownout level option status bit.</Description>
  218. <BitOffset>0x0</BitOffset>
  219. <BitWidth>0x2</BitWidth>
  220. <Access>R</Access>
  221. <Values>
  222. <Val value="0x0">BOR OFF, POR/PDR reset threshold level is applied</Val>
  223. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  224. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  225. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  226. </Values>
  227. </Bit>
  228. </AssignedBits>
  229. </Field>
  230. <Field>
  231. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  232. <AssignedBits>
  233. <Bit>
  234. <Name>BOR_LEV</Name>
  235. <Description>Brownout level option status bit.</Description>
  236. <BitOffset>0x0</BitOffset>
  237. <BitWidth>0x2</BitWidth>
  238. <Access>W</Access>
  239. <Values>
  240. <Val value="0x0">BOR OFF, POR/PDR reset threshold level is applied</Val>
  241. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  242. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  243. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  244. </Values>
  245. </Bit>
  246. </AssignedBits>
  247. </Field>
  248. </Category>
  249. <Category>
  250. <Name>User Configuration</Name>
  251. <Field>
  252. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  253. <AssignedBits>
  254. <Bit>
  255. <Name>VDDIO_HSLV</Name>
  256. <Description>VDD I/O high-speed at low-voltage status bit.</Description>
  257. <BitOffset>0x10</BitOffset>
  258. <BitWidth>0x4</BitWidth>
  259. <Access>R</Access>
  260. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  261. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  262. </Bit>
  263. </AssignedBits>
  264. </Field>
  265. <Field>
  266. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  267. <AssignedBits>
  268. <Bit>
  269. <Name>VDDIO_HSLV</Name>
  270. <Description>VDD I/O high-speed at low-voltage status bit.</Description>
  271. <BitOffset>0x10</BitOffset>
  272. <BitWidth>0x4</BitWidth>
  273. <Access>W</Access>
  274. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  275. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  276. </Bit>
  277. </AssignedBits>
  278. </Field>
  279. <Field>
  280. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  281. <AssignedBits>
  282. <Bit>
  283. <Name>IWDG_STOP</Name>
  284. <Description>Stop mode freeze option status bit.</Description>
  285. <BitOffset>0x14</BitOffset>
  286. <BitWidth>0x1</BitWidth>
  287. <Access>R</Access>
  288. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  289. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  290. </Bit>
  291. </AssignedBits>
  292. </Field>
  293. <Field>
  294. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  295. <AssignedBits>
  296. <Bit>
  297. <Name>IWDG_STOP</Name>
  298. <Description>Stop mode freeze option status bit.</Description>
  299. <BitOffset>0x14</BitOffset>
  300. <BitWidth>0x1</BitWidth>
  301. <Access>W</Access>
  302. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  303. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  304. </Bit>
  305. </AssignedBits>
  306. </Field>
  307. <Field>
  308. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  309. <AssignedBits>
  310. <Bit>
  311. <Name>BOOT_UBE</Name>
  312. <Description>Unique boot entry control, selects either ST or OEM iRoT for secure boot.</Description>
  313. <BitOffset>0x16</BitOffset>
  314. <BitWidth>0x8</BitWidth>
  315. <Access>R</Access>
  316. <Val value="0xB4">OEM-iRoT (system flash) selected</Val>
  317. <Val value="0xC3">ST-iRoT (user flash) selected</Val>
  318. </Bit>
  319. </AssignedBits>
  320. </Field>
  321. <Field>
  322. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  323. <AssignedBits>
  324. <Bit>
  325. <Name>BOOT_UBE</Name>
  326. <Description>Unique boot entry control, selects either ST or OEM iRoT for secure boot.</Description>
  327. <BitOffset>0x16</BitOffset>
  328. <BitWidth>0x8</BitWidth>
  329. <Access>W</Access>
  330. <Val value="0xB4">OEM-iRoT (system flash) selected</Val>
  331. <Val value="0xC3">ST-iRoT (user flash) selected</Val>
  332. </Bit>
  333. </AssignedBits>
  334. </Field>
  335. <Field>
  336. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  337. <AssignedBits>
  338. <Bit>
  339. <Name>SWAP_BANK</Name>
  340. <Description>Bank swapping option status bit.</Description>
  341. <BitOffset>0x1F</BitOffset>
  342. <BitWidth>0x1</BitWidth>
  343. <Access>R</Access>
  344. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  345. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  346. </Bit>
  347. </AssignedBits>
  348. </Field>
  349. <Field>
  350. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  351. <AssignedBits>
  352. <Bit>
  353. <Name>SWAP_BANK</Name>
  354. <Description>Bank swapping option status bit.</Description>
  355. <BitOffset>0x1F</BitOffset>
  356. <BitWidth>0x1</BitWidth>
  357. <Access>W</Access>
  358. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  359. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  360. </Bit>
  361. </AssignedBits>
  362. </Field>
  363. <Field>
  364. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  365. <AssignedBits>
  366. <Bit>
  367. <Name>IWDG_SW</Name>
  368. <Description>IWDG control mode option status bit.</Description>
  369. <BitOffset>0x3</BitOffset>
  370. <BitWidth>0x1</BitWidth>
  371. <Access>R</Access>
  372. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  373. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  374. </Bit>
  375. </AssignedBits>
  376. </Field>
  377. <Field>
  378. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  379. <AssignedBits>
  380. <Bit>
  381. <Name>IWDG_SW</Name>
  382. <Description>IWDG control mode option status bit.</Description>
  383. <BitOffset>0x3</BitOffset>
  384. <BitWidth>0x1</BitWidth>
  385. <Access>W</Access>
  386. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  387. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  388. </Bit>
  389. </AssignedBits>
  390. </Field>
  391. <Field>
  392. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  393. <AssignedBits>
  394. <Bit>
  395. <Name>WWDG_SW</Name>
  396. <Description>IWDG control mode option status bit.</Description>
  397. <BitOffset>0x4</BitOffset>
  398. <BitWidth>0x1</BitWidth>
  399. <Access>R</Access>
  400. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  401. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  402. </Bit>
  403. </AssignedBits>
  404. </Field>
  405. <Field>
  406. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  407. <AssignedBits>
  408. <Bit>
  409. <Name>WWDG_SW</Name>
  410. <Description>IWDG control mode option status bit.</Description>
  411. <BitOffset>0x4</BitOffset>
  412. <BitWidth>0x1</BitWidth>
  413. <Access>W</Access>
  414. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  415. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  416. </Bit>
  417. </AssignedBits>
  418. </Field>
  419. <Field>
  420. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  421. <AssignedBits>
  422. <Bit>
  423. <Name>NRST_SHDWN</Name>
  424. <Description>Core domain Shutdown entry reset option status bit.</Description>
  425. <BitOffset>0x5</BitOffset>
  426. <BitWidth>0x1</BitWidth>
  427. <Access>R</Access>
  428. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  429. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  430. </Bit>
  431. </AssignedBits>
  432. </Field>
  433. <Field>
  434. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  435. <AssignedBits>
  436. <Bit>
  437. <Name>NRST_SHDWN</Name>
  438. <Description>Core domain Shutdown entry reset option status bit.</Description>
  439. <BitOffset>0x5</BitOffset>
  440. <BitWidth>0x1</BitWidth>
  441. <Access>W</Access>
  442. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  443. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  444. </Bit>
  445. </AssignedBits>
  446. </Field>
  447. <Field>
  448. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  449. <AssignedBits>
  450. <Bit>
  451. <Name>NRST_STOP</Name>
  452. <Description>Core domain DStop entry reset option status bit.</Description>
  453. <BitOffset>0x6</BitOffset>
  454. <BitWidth>0x1</BitWidth>
  455. <Access>R</Access>
  456. <Val value="0x0">a reset is generated when entering DStop or DStop2 mode on core domain</Val>
  457. <Val value="0x1">no reset generated when entering DStop or DStop2 mode on core domain</Val>
  458. </Bit>
  459. </AssignedBits>
  460. </Field>
  461. <Field>
  462. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  463. <AssignedBits>
  464. <Bit>
  465. <Name>NRST_STOP</Name>
  466. <Description>Core domain DStop entry reset option status bit.</Description>
  467. <BitOffset>0x6</BitOffset>
  468. <BitWidth>0x1</BitWidth>
  469. <Access>W</Access>
  470. <Val value="0x0">a reset is generated when entering DStop or DStop2 mode on core domain</Val>
  471. <Val value="0x1">no reset generated when entering DStop or DStop2 mode on core domain</Val>
  472. </Bit>
  473. </AssignedBits>
  474. </Field>
  475. <Field>
  476. <Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
  477. <AssignedBits>
  478. <Bit>
  479. <Name>NRST_STDY</Name>
  480. <Description>Core domain Standby entry reset option status bit.</Description>
  481. <BitOffset>0x7</BitOffset>
  482. <BitWidth>0x1</BitWidth>
  483. <Access>R</Access>
  484. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  485. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  486. </Bit>
  487. </AssignedBits>
  488. </Field>
  489. <Field>
  490. <Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
  491. <AssignedBits>
  492. <Bit>
  493. <Name>NRST_STDY</Name>
  494. <Description>Core domain Standby entry reset option status bit.</Description>
  495. <BitOffset>0x7</BitOffset>
  496. <BitWidth>0x1</BitWidth>
  497. <Access>W</Access>
  498. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  499. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  500. </Bit>
  501. </AssignedBits>
  502. </Field>
  503. <Field>
  504. <Parameters address="0x40022058" name="FLASH_SECIPR" size="0x4"/>
  505. <AssignedBits>
  506. <Bit>
  507. <Name>USB_EN</Name>
  508. <Description>USB peripheral enable bit</Description>
  509. <BitOffset>0xE</BitOffset>
  510. <BitWidth>0x1</BitWidth>
  511. <Access>R</Access>
  512. <Values>
  513. <Val value="0x0">USB communication disabled</Val>
  514. <Val value="0x1">USB communication enabled</Val>
  515. </Values>
  516. </Bit>
  517. <Bit>
  518. <Name>HASH_EN</Name>
  519. <Description>HASH SHA IP enable bit.</Description>
  520. <BitOffset>0xD</BitOffset>
  521. <BitWidth>0x1</BitWidth>
  522. <Access>R</Access>
  523. <Values>
  524. <Val value="0x0">HASH feature disabled</Val>
  525. <Val value="0x1">HASH feature enabled</Val>
  526. </Values>
  527. </Bit>
  528. <Bit>
  529. <Name>RNG_EN</Name>
  530. <Description>random number generator IP enable bit</Description>
  531. <BitOffset>0xC</BitOffset>
  532. <BitWidth>0x1</BitWidth>
  533. <Access>R</Access>
  534. <Values>
  535. <Val value="0x0">HASH feature disabled</Val>
  536. <Val value="0x1">HASH feature enabled</Val>
  537. </Values>
  538. </Bit>
  539. <Bit>
  540. <Name>PKA_EN</Name>
  541. <Description>public key cryptography IP enable bit</Description>
  542. <BitOffset>0xB</BitOffset>
  543. <BitWidth>0x1</BitWidth>
  544. <Access>R</Access>
  545. <Values>
  546. <Val value="0x0">HASH feature disabled</Val>
  547. <Val value="0x1">HASH feature enabled</Val>
  548. </Values>
  549. </Bit>
  550. <Bit>
  551. <Name>AES_EN</Name>
  552. <Description/>
  553. <BitOffset>0xA</BitOffset>
  554. <BitWidth>0x1</BitWidth>
  555. <Access>R</Access>
  556. <Values>
  557. <Val value="0x0">HASH feature disabled</Val>
  558. <Val value="0x1">HASH feature enabled</Val>
  559. </Values>
  560. </Bit>
  561. <Bit>
  562. <Name>RSS_OPT</Name>
  563. <Description/>
  564. <BitOffset>0x7</BitOffset>
  565. <BitWidth>0x3</BitWidth>
  566. <Access>R</Access>
  567. <Values>
  568. <!--Val value="0x0">Freeze IWDG counter in stop mode</Val-->
  569. <!--Val value="0x1">IWDG counter active in stop mode</Val-->
  570. </Values>
  571. </Bit>
  572. <Bit>
  573. <Name>FLASH_SIZE</Name>
  574. <Description/>
  575. <BitOffset>0x4</BitOffset>
  576. <BitWidth>0x3</BitWidth>
  577. <Access>R</Access>
  578. <Values>
  579. <Val value="0x0">512kB product</Val>
  580. <Val value="0x1">1MB product</Val>
  581. <Val value="0x2">2MB product</Val>
  582. </Values>
  583. </Bit>
  584. <Bit>
  585. <Name>GFX_EN</Name>
  586. <Description>GFX module option status bit</Description>
  587. <BitOffset>0x3</BitOffset>
  588. <BitWidth>0x1</BitWidth>
  589. <Access>R</Access>
  590. <Values>
  591. <Val value="0x0">GFX disabled</Val>
  592. <Val value="0x1">GFX enabled</Val>
  593. </Values>
  594. </Bit>
  595. <Bit>
  596. <Name>OTFDEC_EN</Name>
  597. <Description>OTFDEC option status bit. Controls on the fly decryption of external memory</Description>
  598. <BitOffset>0x2</BitOffset>
  599. <BitWidth>0x1</BitWidth>
  600. <Access>R</Access>
  601. <Values>
  602. <Val value="0x0">OTFDEC disabled</Val>
  603. <Val value="0x1">OTFDEC enbled</Val>
  604. </Values>
  605. </Bit>
  606. <Bit>
  607. <Name>SAES_EN</Name>
  608. <Description>Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage</Description>
  609. <BitOffset>0x1</BitOffset>
  610. <BitWidth>0x1</BitWidth>
  611. <Access>R</Access>
  612. <Values>
  613. <Val value="0x0">SAES disabled</Val>
  614. <Val value="0x1">SAES enabled</Val>
  615. </Values>
  616. </Bit>
  617. <Bit>
  618. <Name>CAN_EN</Name>
  619. <Description>CAN module control bit</Description>
  620. <BitOffset>0x0</BitOffset>
  621. <BitWidth>0x1</BitWidth>
  622. <Access>R</Access>
  623. <Values>
  624. <Val value="0x0">CAN disabled</Val>
  625. <Val value="0x1">CAN enabled</Val>
  626. </Values>
  627. </Bit>
  628. </AssignedBits>
  629. </Field>
  630. <Field>
  631. <Parameters address="0x4002205C" name="FLASH_SECIPR" size="0x4"/>
  632. <AssignedBits>
  633. <Bit>
  634. <Name>USB_EN</Name>
  635. <Description>USB peripheral enable bit.</Description>
  636. <BitOffset>0xE</BitOffset>
  637. <BitWidth>0x1</BitWidth>
  638. <Access>W</Access>
  639. <Values>
  640. <Val value="0x0">USB communication disabled</Val>
  641. <Val value="0x1">USB communication enabled</Val>
  642. </Values>
  643. </Bit>
  644. <Bit>
  645. <Name>HASH_EN</Name>
  646. <Description>HASH SHA IP enable bit.</Description>
  647. <BitOffset>0xD</BitOffset>
  648. <BitWidth>0x1</BitWidth>
  649. <Access>W</Access>
  650. <Values>
  651. <Val value="0x0">HASH feature disabled</Val>
  652. <Val value="0x1">HASH feature enabled</Val>
  653. </Values>
  654. </Bit>
  655. <Bit>
  656. <Name>RNG_EN</Name>
  657. <Description>random number generator IP enable bit</Description>
  658. <BitOffset>0xC</BitOffset>
  659. <BitWidth>0x1</BitWidth>
  660. <Access>W</Access>
  661. <Values>
  662. <Val value="0x0">HASH feature disabled</Val>
  663. <Val value="0x1">HASH feature enabled</Val>
  664. </Values>
  665. </Bit>
  666. <Bit>
  667. <Name>PKA_EN</Name>
  668. <Description>public key cryptography IP enable bit</Description>
  669. <BitOffset>0xB</BitOffset>
  670. <BitWidth>0x1</BitWidth>
  671. <Access>W</Access>
  672. <Values>
  673. <Val value="0x0">HASH feature disabled</Val>
  674. <Val value="0x1">HASH feature enabled</Val>
  675. </Values>
  676. </Bit>
  677. <Bit>
  678. <Name>AES_EN</Name>
  679. <Description/>
  680. <BitOffset>0xA</BitOffset>
  681. <BitWidth>0x1</BitWidth>
  682. <Access>W</Access>
  683. <Values>
  684. <Val value="0x0">HASH feature disabled</Val>
  685. <Val value="0x1">HASH feature enabled</Val>
  686. </Values>
  687. </Bit>
  688. <Bit>
  689. <Name>RSS_OPT</Name>
  690. <Description/>
  691. <BitOffset>0x7</BitOffset>
  692. <BitWidth>0x3</BitWidth>
  693. <Access>W</Access>
  694. <Values>
  695. <!--Val value="0x0">Freeze IWDG counter in stop mode</Val-->
  696. <!--Val value="0x1">IWDG counter active in stop mode</Val-->
  697. </Values>
  698. </Bit>
  699. <Bit>
  700. <Name>FLASH_SIZE</Name>
  701. <Description/>
  702. <BitOffset>0x4</BitOffset>
  703. <BitWidth>0x3</BitWidth>
  704. <Access>W</Access>
  705. <Values>
  706. <Val value="0x0">512kB product</Val>
  707. <Val value="0x1">1MB product</Val>
  708. <Val value="0x2">2MB product</Val>
  709. </Values>
  710. </Bit>
  711. <Bit>
  712. <Name>GFX_EN</Name>
  713. <Description>GFX module option status bit</Description>
  714. <BitOffset>0x3</BitOffset>
  715. <BitWidth>0x1</BitWidth>
  716. <Access>W</Access>
  717. <Values>
  718. <Val value="0x0">GFX disabled</Val>
  719. <Val value="0x1">GFX enabled</Val>
  720. </Values>
  721. </Bit>
  722. <Bit>
  723. <Name>OTFDEC_EN</Name>
  724. <Description>OTFDEC option status bit. Controls on the fly decryption of external memory</Description>
  725. <BitOffset>0x2</BitOffset>
  726. <BitWidth>0x1</BitWidth>
  727. <Access>W</Access>
  728. <Values>
  729. <Val value="0x0">OTFDEC disabled</Val>
  730. <Val value="0x1">OTFDEC enbled</Val>
  731. </Values>
  732. </Bit>
  733. <Bit>
  734. <Name>SAES_EN</Name>
  735. <Description>Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage</Description>
  736. <BitOffset>0x1</BitOffset>
  737. <BitWidth>0x1</BitWidth>
  738. <Access>W</Access>
  739. <Values>
  740. <Val value="0x0">SAES disabled</Val>
  741. <Val value="0x1">SAES enabled</Val>
  742. </Values>
  743. </Bit>
  744. <Bit>
  745. <Name>CAN_EN</Name>
  746. <Description>CAN module control bit</Description>
  747. <BitOffset>0x0</BitOffset>
  748. <BitWidth>0x1</BitWidth>
  749. <Access>W</Access>
  750. <Values>
  751. <Val value="0x0">CAN disabled</Val>
  752. <Val value="0x1">CAN enabled</Val>
  753. </Values>
  754. </Bit>
  755. </AssignedBits>
  756. </Field>
  757. </Category>
  758. </Bank>
  759. <Bank interface="JTAG_SWD">
  760. <Parameters address="0x40022070" name="Bank 2" size="0x10"/>
  761. <Category>
  762. <Name>User Configuration 2</Name>
  763. <Field>
  764. <Parameters address="0x40022070" name="FLASH_WRP1AR" size="0x4"/>
  765. <AssignedBits>
  766. <Bit>
  767. <Name>TZEN</Name>
  768. <Description>Trust Zone Enable configuration bits</Description>
  769. <BitOffset>0x18</BitOffset>
  770. <BitWidth>0x8</BitWidth>
  771. <Access>R</Access>
  772. <Values>
  773. <Val value="0xC3">Trust zone disabled</Val>
  774. <Val value="0xB4">Trust zone enabled</Val>
  775. </Values>
  776. </Bit>
  777. <Bit>
  778. <Name>HUK_PUF</Name>
  779. <Description>This bit configures the nature and use of the unique key</Description>
  780. <BitOffset>0xF</BitOffset>
  781. <BitWidth>0x1</BitWidth>
  782. <Access>R</Access>
  783. <Values>
  784. <Val value="0x0">The key is treated as HUK</Val>
  785. <Val value="0x1">The key is treated as PUF</Val>
  786. </Values>
  787. </Bit>
  788. <Bit>
  789. <Name>USBPD_DB_DIS</Name>
  790. <Description>USB power delivery configuration option bit</Description>
  791. <BitOffset>0x8</BitOffset>
  792. <BitWidth>0x1</BitWidth>
  793. <Access>R</Access>
  794. <Values>
  795. <Val value="0x0">Disabled</Val>
  796. <Val value="0x1">Enabled</Val>
  797. </Values>
  798. </Bit>
  799. <Bit>
  800. <Name>SRAM2_PAR</Name>
  801. <Description>Parity in SRAM2 region configuration bit</Description>
  802. <BitOffset>0x7</BitOffset>
  803. <BitWidth>0x1</BitWidth>
  804. <Access>R</Access>
  805. <Values>
  806. <Val value="0x0">The key is treated as HUK</Val>
  807. <Val value="0x1">The key is treated as PUF</Val>
  808. </Values>
  809. </Bit>
  810. <Bit>
  811. <Name>SRAM2_ECC</Name>
  812. <Description>ECC in SRAM2 region configuration bit</Description>
  813. <BitOffset>0x6</BitOffset>
  814. <BitWidth>0x1</BitWidth>
  815. <Access>R</Access>
  816. <Values>
  817. <Val value="0x0">Disabled</Val>
  818. <Val value="0x1">Enabled</Val>
  819. </Values>
  820. </Bit>
  821. <Bit>
  822. <Name>SRAM3_ECC</Name>
  823. <Description>ECC in SRAM3 region configuration bit</Description>
  824. <BitOffset>0x5</BitOffset>
  825. <BitWidth>0x1</BitWidth>
  826. <Access>R</Access>
  827. <Values>
  828. <Val value="0x0">Disabled</Val>
  829. <Val value="0x1">Enabled</Val>
  830. </Values>
  831. </Bit>
  832. <Bit>
  833. <Name>BKPRAM_ECC</Name>
  834. <Description>ECC in BKPRAM region configuration bit</Description>
  835. <BitOffset>0x4</BitOffset>
  836. <BitWidth>0x1</BitWidth>
  837. <Access>R</Access>
  838. <Values>
  839. <Val value="0x0">Disabled</Val>
  840. <Val value="0x1">Enabled</Val>
  841. </Values>
  842. </Bit>
  843. <Bit>
  844. <Name>SRAM2_RST</Name>
  845. <Description/>
  846. <BitOffset>0x3</BitOffset>
  847. <BitWidth>0x1</BitWidth>
  848. <Access>R</Access>
  849. <Values>
  850. <Val value="0x0">Disabled</Val>
  851. <Val value="0x1">Enabled</Val>
  852. </Values>
  853. </Bit>
  854. <Bit>
  855. <Name>SRAM1_3_RST</Name>
  856. <Description/>
  857. <BitOffset>0x2</BitOffset>
  858. <BitWidth>0x1</BitWidth>
  859. <Access>R</Access>
  860. <Values>
  861. <Val value="0x0">Disabled</Val>
  862. <Val value="0x1">Enabled</Val>
  863. </Values>
  864. </Bit>
  865. </AssignedBits>
  866. </Field>
  867. <Field>
  868. <Parameters address="0x40022074" name="FLASH_WRP1AR" size="0x4"/>
  869. <AssignedBits>
  870. <Bit>
  871. <Name>TZEN</Name>
  872. <Description>Trust Zone Enable configuration bits</Description>
  873. <BitOffset>0x18</BitOffset>
  874. <BitWidth>0x8</BitWidth>
  875. <Access>W</Access>
  876. <Values>
  877. <Val value="0xC3">Trust zone disabled</Val>
  878. <Val value="0xB4">Trust zone enabled</Val>
  879. </Values>
  880. </Bit>
  881. <Bit>
  882. <Name>HUK_PUF</Name>
  883. <Description>This bit configures the nature and use of the unique key</Description>
  884. <BitOffset>0xF</BitOffset>
  885. <BitWidth>0x1</BitWidth>
  886. <Access>W</Access>
  887. <Values>
  888. <Val value="0x0">The key is treated as HUK</Val>
  889. <Val value="0x1">The key is treated as PUF</Val>
  890. </Values>
  891. </Bit>
  892. <Bit>
  893. <Name>USBPD_DB_DIS</Name>
  894. <Description>USB power delivery configuration option bit</Description>
  895. <BitOffset>0x8</BitOffset>
  896. <BitWidth>0x1</BitWidth>
  897. <Access>W</Access>
  898. <Values>
  899. <Val value="0x0">Disabled</Val>
  900. <Val value="0x1">Enabled</Val>
  901. </Values>
  902. </Bit>
  903. <Bit>
  904. <Name>SRAM2_PAR</Name>
  905. <Description>Parity in SRAM2 region configuration bit</Description>
  906. <BitOffset>0x7</BitOffset>
  907. <BitWidth>0x1</BitWidth>
  908. <Access>W</Access>
  909. <Values>
  910. <Val value="0x0">The key is treated as HUK</Val>
  911. <Val value="0x1">The key is treated as PUF</Val>
  912. </Values>
  913. </Bit>
  914. <Bit>
  915. <Name>SRAM2_ECC</Name>
  916. <Description>ECC in SRAM2 region configuration bit</Description>
  917. <BitOffset>0x6</BitOffset>
  918. <BitWidth>0x1</BitWidth>
  919. <Access>W</Access>
  920. <Values>
  921. <Val value="0x0">Disabled</Val>
  922. <Val value="0x1">Enabled</Val>
  923. </Values>
  924. </Bit>
  925. <Bit>
  926. <Name>SRAM3_ECC</Name>
  927. <Description>ECC in SRAM3 region configuration bit</Description>
  928. <BitOffset>0x5</BitOffset>
  929. <BitWidth>0x1</BitWidth>
  930. <Access>W</Access>
  931. <Values>
  932. <Val value="0x0">Disabled</Val>
  933. <Val value="0x1">Enabled</Val>
  934. </Values>
  935. </Bit>
  936. <Bit>
  937. <Name>BKPRAM_ECC</Name>
  938. <Description>ECC in BKPRAM region configuration bit</Description>
  939. <BitOffset>0x4</BitOffset>
  940. <BitWidth>0x1</BitWidth>
  941. <Access>W</Access>
  942. <Values>
  943. <Val value="0x0">Disabled</Val>
  944. <Val value="0x1">Enabled</Val>
  945. </Values>
  946. </Bit>
  947. <Bit>
  948. <Name>SRAM2_RST</Name>
  949. <Description></Description>
  950. <BitOffset>0x3</BitOffset>
  951. <BitWidth>0x1</BitWidth>
  952. <Access>W</Access>
  953. <Values>
  954. <Val value="0x0">Disabled</Val>
  955. <Val value="0x1">Enabled</Val>
  956. </Values>
  957. </Bit>
  958. <Bit>
  959. <Name>SRAM1_3_RST</Name>
  960. <Description/>
  961. <BitOffset>0x2</BitOffset>
  962. <BitWidth>0x1</BitWidth>
  963. <Access>W</Access>
  964. <Values>
  965. <Val value="0x0">Disabled</Val>
  966. <Val value="0x1">Enabled</Val>
  967. </Values>
  968. </Bit>
  969. </AssignedBits>
  970. </Field>
  971. </Category>
  972. </Bank>
  973. <Bank interface="JTAG_SWD">
  974. <Parameters address="0x40022080" name="Bank 3" size="0x8"/>
  975. <Category>
  976. <Name>Boot Configuration</Name>
  977. <Field>
  978. <Parameters address="0x40022080" name="FLASH_WRP2AR" size="0x4"/>
  979. <AssignedBits>
  980. <Bit>
  981. <Name>BOOT_ADDR_NS</Name>
  982. <Description>Unique Boot Entry Secure Address</Description>
  983. <BitOffset>0x8</BitOffset>
  984. <BitWidth>0x10</BitWidth>
  985. <Access>R</Access>
  986. <Equation multiplier="0x2000" offset="0x08000000"/>
  987. </Bit>
  988. <Bit>
  989. <Name>BOOT_LOCK_NS</Name>
  990. <Description>A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings</Description>
  991. <BitOffset>0x0</BitOffset>
  992. <BitWidth>0x8</BitWidth>
  993. <Access>R</Access>
  994. <Equation multiplier="0x2000" offset="0x08000000"/>
  995. </Bit>
  996. </AssignedBits>
  997. </Field>
  998. <Field>
  999. <Parameters address="0x40022084" name="FLASH_WRP2AR" size="0x4"/>
  1000. <AssignedBits>
  1001. <Bit>
  1002. <Name>BOOT_ADDR_NS</Name>
  1003. <Description>Unique Boot Entry Secure Address</Description>
  1004. <BitOffset>0x8</BitOffset>
  1005. <BitWidth>0x10</BitWidth>
  1006. <Access>W</Access>
  1007. <Equation multiplier="0x2000" offset="0x08000000"/>
  1008. </Bit>
  1009. <Bit>
  1010. <Name>BOOT_LOCK_NS</Name>
  1011. <Description>A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings</Description>
  1012. <BitOffset>0x0</BitOffset>
  1013. <BitWidth>0x8</BitWidth>
  1014. <Access>W</Access>
  1015. <Equation multiplier="0x2000" offset="0x08000000"/>
  1016. </Bit>
  1017. </AssignedBits>
  1018. </Field>
  1019. </Category>
  1020. </Bank>
  1021. <Bank interface="JTAG_SWD">
  1022. <Parameters address="0x400220E8" name="Bank 4" size="0x8"/>
  1023. <Category>
  1024. <Name>Write sector group protection 1</Name>
  1025. <Field>
  1026. <Parameters address="0x400220E8" name="FLASH_WRP2BR" size="0x4"/>
  1027. <AssignedBits>
  1028. <Bit>
  1029. <Name>WRPSGn1</Name>
  1030. <Description>Bank 1 sector group protection option status byte</Description>
  1031. <BitOffset>0x0</BitOffset>
  1032. <BitWidth>0x20</BitWidth>
  1033. <Access>R</Access>
  1034. <Equation multiplier="0x2000" offset="0x08000000"/>
  1035. </Bit>
  1036. </AssignedBits>
  1037. </Field>
  1038. <Field>
  1039. <Parameters address="0x400220EC" name="FLASH_WRP2BR" size="0x4"/>
  1040. <AssignedBits>
  1041. <Bit>
  1042. <Name>WRPSGn1</Name>
  1043. <Description>Bank 1 sector group protection option status byte</Description>
  1044. <BitOffset>0x0</BitOffset>
  1045. <BitWidth>0x20</BitWidth>
  1046. <Access>W</Access>
  1047. <Equation multiplier="0x2000" offset="0x08000000"/>
  1048. </Bit>
  1049. </AssignedBits>
  1050. </Field>
  1051. </Category>
  1052. </Bank>
  1053. <Bank interface="JTAG_SWD">
  1054. <Parameters address="0x400221E8" name="Bank 5" size="0x8"/>
  1055. <Category>
  1056. <Name>Write sector group protection 2</Name>
  1057. <Field>
  1058. <Parameters address="0x400221E8" name="FLASH_WRP2BR" size="0x4"/>
  1059. <AssignedBits>
  1060. <Bit>
  1061. <Name>WRPSGn2</Name>
  1062. <Description>Bank 2 sector group protection option status byte</Description>
  1063. <BitOffset>0x0</BitOffset>
  1064. <BitWidth>0x20</BitWidth>
  1065. <Access>R</Access>
  1066. <Equation multiplier="0x2000" offset="0x08000000"/>
  1067. </Bit>
  1068. </AssignedBits>
  1069. </Field>
  1070. <Field>
  1071. <Parameters address="0x400221E8" name="FLASH_WRP2BR" size="0x4"/>
  1072. <AssignedBits>
  1073. <Bit>
  1074. <Name>WRPSGn2</Name>
  1075. <Description>Bank 2 sector group protection option status byte</Description>
  1076. <BitOffset>0x0</BitOffset>
  1077. <BitWidth>0x20</BitWidth>
  1078. <Access>W</Access>
  1079. <Equation multiplier="0x2000" offset="0x08000000"/>
  1080. </Bit>
  1081. </AssignedBits>
  1082. </Field>
  1083. </Category>
  1084. </Bank>
  1085. <Bank interface="JTAG_SWD">
  1086. <Parameters address="0x40022090" name="Bank 6" size="0x8"/>
  1087. <Category>
  1088. <Name>OTP write protection</Name>
  1089. <Field>
  1090. <Parameters address="0x40022090" name="FLASH_WRP2BR" size="0x4"/>
  1091. <AssignedBits>
  1092. <Bit>
  1093. <Name>LOCKBL</Name>
  1094. <Description>OTP Block Lock</Description>
  1095. <BitOffset>0x0</BitOffset>
  1096. <BitWidth>0x20</BitWidth>
  1097. <Access>R</Access>
  1098. <Equation multiplier="0x2000" offset="0x00000000"/>
  1099. </Bit>
  1100. </AssignedBits>
  1101. </Field>
  1102. <Field>
  1103. <Parameters address="0x40022094" name="FLASH_WRP2BR" size="0x4"/>
  1104. <AssignedBits>
  1105. <Bit>
  1106. <Name>LOCKBL</Name>
  1107. <Description>OTP Block Lock</Description>
  1108. <BitOffset>0x0</BitOffset>
  1109. <BitWidth>0x20</BitWidth>
  1110. <Access>W</Access>
  1111. <Equation multiplier="0x2000" offset="0x00000000"/>
  1112. </Bit>
  1113. </AssignedBits>
  1114. </Field>
  1115. </Category>
  1116. </Bank>
  1117. <Bank interface="JTAG_SWD">
  1118. <Parameters address="0x400220F0" name="Bank 7" size="0x8"/>
  1119. <Category>
  1120. <Name>Flash data sectors</Name>
  1121. <Field>
  1122. <Parameters address="0x400220F0" name="FLASH_WRP2BR" size="0x4"/>
  1123. <AssignedBits>
  1124. <Bit>
  1125. <Name>DATA_EN</Name>
  1126. <Description>Bank1 Flash high-cycle data enable</Description>
  1127. <BitOffset>0xF</BitOffset>
  1128. <BitWidth>0x1</BitWidth>
  1129. <Access>R</Access>
  1130. <Values>
  1131. <Val value="0x0">No Flash high-cycle data area</Val>
  1132. <Val value="0x1">Flash high-cycle data is used</Val>
  1133. </Values>
  1134. </Bit>
  1135. <Bit>
  1136. <Name>DATA_SECTOR_START_1</Name>
  1137. <Description>DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1.</Description>
  1138. <BitOffset>0x0</BitOffset>
  1139. <BitWidth>0x3</BitWidth>
  1140. <Access>R</Access>
  1141. <Equation multiplier="0x1" offset="0x0"/>
  1142. </Bit>
  1143. </AssignedBits>
  1144. </Field>
  1145. <Field>
  1146. <Parameters address="0x400220F4" name="FLASH_WRP2BR" size="0x4"/>
  1147. <AssignedBits>
  1148. <Bit>
  1149. <Name>DATA_EN</Name>
  1150. <Description>Bank1 Flash high-cycle data enable</Description>
  1151. <BitOffset>0xF</BitOffset>
  1152. <BitWidth>0x1</BitWidth>
  1153. <Access>W</Access>
  1154. <Values>
  1155. <Val value="0x0">No Flash high-cycle data area</Val>
  1156. <Val value="0x1">Flash high-cycle data is used</Val>
  1157. </Values>
  1158. </Bit>
  1159. <Bit>
  1160. <Name>DATA_SECTOR_START_1</Name>
  1161. <Description>DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1.</Description>
  1162. <BitOffset>0x0</BitOffset>
  1163. <BitWidth>0x3</BitWidth>
  1164. <Access>W</Access>
  1165. <Equation multiplier="0x1" offset="0x0"/>
  1166. </Bit>
  1167. </AssignedBits>
  1168. </Field>
  1169. </Category>
  1170. </Bank>
  1171. <Bank interface="JTAG_SWD">
  1172. <Parameters address="0x400221F0" name="Bank 8" size="0x8"/>
  1173. <Category>
  1174. <Name>Flash data sectors</Name>
  1175. <Field>
  1176. <Parameters address="0x400221F0" name="FLASH_WRP2BR" size="0x4"/>
  1177. <AssignedBits>
  1178. <Bit>
  1179. <Name>DATA_EN_2</Name>
  1180. <Description>Bank1 Flash high-cycle data enable</Description>
  1181. <BitOffset>0xF</BitOffset>
  1182. <BitWidth>0x1</BitWidth>
  1183. <Access>R</Access>
  1184. <Values>
  1185. <Val value="0x0">No Flash high-cycle data area</Val>
  1186. <Val value="0x1">Flash high-cycle data is used</Val>
  1187. </Values>
  1188. </Bit>
  1189. <Bit>
  1190. <Name>DATA_SECTOR_START_2</Name>
  1191. <Description>DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2.</Description>
  1192. <BitOffset>0x0</BitOffset>
  1193. <BitWidth>0x3</BitWidth>
  1194. <Access>R</Access>
  1195. <Equation multiplier="0x1" offset="0x0"/>
  1196. </Bit>
  1197. </AssignedBits>
  1198. </Field>
  1199. <Field>
  1200. <Parameters address="0x400221F4" name="FLASH_WRP2BR" size="0x4"/>
  1201. <AssignedBits>
  1202. <Bit>
  1203. <Name>DATA_EN_2</Name>
  1204. <Description>Bank1 Flash high-cycle data enable</Description>
  1205. <BitOffset>0xF</BitOffset>
  1206. <BitWidth>0x1</BitWidth>
  1207. <Access>W</Access>
  1208. <Values>
  1209. <Val value="0x0">No Flash high-cycle data area</Val>
  1210. <Val value="0x1">Flash high-cycle data is used</Val>
  1211. </Values>
  1212. </Bit>
  1213. <Bit>
  1214. <Name>DATA_SECTOR_START_2</Name>
  1215. <Description>DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2.</Description>
  1216. <BitOffset>0x0</BitOffset>
  1217. <BitWidth>0x3</BitWidth>
  1218. <Access>W</Access>
  1219. <Equation multiplier="0x1" offset="0x0"/>
  1220. </Bit>
  1221. </AssignedBits>
  1222. </Field>
  1223. </Category>
  1224. </Bank>
  1225. <Bank interface="JTAG_SWD">
  1226. <Parameters address="0x40022060" name="Bank 9" size="0x10"/>
  1227. <Category>
  1228. <Name>Flash EPOCH</Name>
  1229. <Field>
  1230. <Parameters address="0x40022060" name="FLASH_WRP2BR" size="0x4"/>
  1231. <AssignedBits>
  1232. <Bit>
  1233. <Name>NS_EPOCH</Name>
  1234. <Description>Non Volatile Non Secure EPOCH counter</Description>
  1235. <BitOffset>0x0</BitOffset>
  1236. <BitWidth>0x18</BitWidth>
  1237. <Access>R</Access>
  1238. <Equation multiplier="0x1" offset="0x00000001"/>
  1239. </Bit>
  1240. </AssignedBits>
  1241. </Field>
  1242. <Field>
  1243. <Parameters address="0x40022064" name="FLASH_WRP2BR" size="0x4"/>
  1244. <AssignedBits>
  1245. <Bit>
  1246. <Name>NS_EPOCH</Name>
  1247. <Description>Non Volatile Non Secure EPOCH counter</Description>
  1248. <BitOffset>0x0</BitOffset>
  1249. <BitWidth>0x18</BitWidth>
  1250. <Access>W</Access>
  1251. <Equation multiplier="0x1" offset="0x00000001"/>
  1252. </Bit>
  1253. </AssignedBits>
  1254. </Field>
  1255. <Field>
  1256. <Parameters address="0x40022064" name="FLASH_WRP2BR" size="0x4"/>
  1257. <AssignedBits>
  1258. <Bit>
  1259. <Name>SEC_EPOCH</Name>
  1260. <Description>Non Volatile Secure EPOCH counter</Description>
  1261. <BitOffset>0x0</BitOffset>
  1262. <BitWidth>0x18</BitWidth>
  1263. <Access>R</Access>
  1264. <Equation multiplier="0x1" offset="0x00000001"/>
  1265. </Bit>
  1266. </AssignedBits>
  1267. </Field>
  1268. <Field>
  1269. <Parameters address="0x40022068" name="FLASH_WRP2BR" size="0x4"/>
  1270. <AssignedBits>
  1271. <Bit>
  1272. <Name>SEC_EPOCH</Name>
  1273. <Description>Non Volatile Secure EPOCH counter</Description>
  1274. <BitOffset>0x0</BitOffset>
  1275. <BitWidth>0x18</BitWidth>
  1276. <Access>W</Access>
  1277. <Equation multiplier="0x1" offset="0x00000001"/>
  1278. </Bit>
  1279. </AssignedBits>
  1280. </Field>
  1281. </Category>
  1282. </Bank>
  1283. <Bank interface="JTAG_SWD">
  1284. <Parameters address="0x400220F8" name="Bank 10" size="0x8"/>
  1285. <Category>
  1286. <Name>Flash HDP bank 1</Name>
  1287. <Field>
  1288. <Parameters address="0x400220F8" name="FLASH_WRP2BR" size="0x4"/>
  1289. <AssignedBits>
  1290. <Bit>
  1291. <Name>HDP1_STRT</Name>
  1292. <Description>TIL barrier start set in number of 8kb sectors</Description>
  1293. <BitOffset>0x0</BitOffset>
  1294. <BitWidth>0x7</BitWidth>
  1295. <Access>R</Access>
  1296. <Equation multiplier="0x2000" offset="0x00000001"/>
  1297. </Bit>
  1298. <Bit>
  1299. <Name>HDP1_END</Name>
  1300. <Description>TIL barrier end set in number of 8kb sectors</Description>
  1301. <BitOffset>0x10</BitOffset>
  1302. <BitWidth>0x7</BitWidth>
  1303. <Access>R</Access>
  1304. <Equation multiplier="0x2000" offset="0x00000001"/>
  1305. </Bit>
  1306. </AssignedBits>
  1307. </Field>
  1308. <Field>
  1309. <Parameters address="0x400220FC" name="FLASH_WRP2BR" size="0x4"/>
  1310. <AssignedBits>
  1311. <Bit>
  1312. <Name>HDP1_STRT</Name>
  1313. <Description>TIL barrier start set in number of 8kb sectors</Description>
  1314. <BitOffset>0x0</BitOffset>
  1315. <BitWidth>0x7</BitWidth>
  1316. <Access>W</Access>
  1317. <Equation multiplier="0x2000" offset="0x00000001"/>
  1318. </Bit>
  1319. <Bit>
  1320. <Name>HDP1_END</Name>
  1321. <Description>TIL barrier end set in number of 8kb sectors</Description>
  1322. <BitOffset>0x10</BitOffset>
  1323. <BitWidth>0x7</BitWidth>
  1324. <Access>W</Access>
  1325. <Equation multiplier="0x2000" offset="0x00000001"/>
  1326. </Bit>
  1327. </AssignedBits>
  1328. </Field>
  1329. </Category>
  1330. </Bank>
  1331. <Bank interface="JTAG_SWD">
  1332. <Parameters address="0x400221F8" name="Bank 11" size="0x8"/>
  1333. <Category>
  1334. <Name>Flash HDP bank 2</Name>
  1335. <Field>
  1336. <Parameters address="0x400221F8" name="FLASH_WRP2BR" size="0x4"/>
  1337. <AssignedBits>
  1338. <Bit>
  1339. <Name>HDP2_STRT</Name>
  1340. <Description>TIL barrier start set in number of 8kb sectors</Description>
  1341. <BitOffset>0x0</BitOffset>
  1342. <BitWidth>0x7</BitWidth>
  1343. <Access>R</Access>
  1344. <Equation multiplier="0x2000" offset="0x00000001"/>
  1345. </Bit>
  1346. <Bit>
  1347. <Name>HDP2_END</Name>
  1348. <Description>TIL barrier end set in number of 8kb sectors</Description>
  1349. <BitOffset>0x10</BitOffset>
  1350. <BitWidth>0x7</BitWidth>
  1351. <Access>R</Access>
  1352. <Equation multiplier="0x2000" offset="0x00000001"/>
  1353. </Bit>
  1354. </AssignedBits>
  1355. </Field>
  1356. <Field>
  1357. <Parameters address="0x400221FC" name="FLASH_WRP2BR" size="0x4"/>
  1358. <AssignedBits>
  1359. <Bit>
  1360. <Name>HDP2_STRT</Name>
  1361. <Description>TIL barrier start set in number of 8kb sectors</Description>
  1362. <BitOffset>0x0</BitOffset>
  1363. <BitWidth>0x7</BitWidth>
  1364. <Access>W</Access>
  1365. <Equation multiplier="0x2000" offset="0x00000001"/>
  1366. </Bit>
  1367. <Bit>
  1368. <Name>HDP2_END</Name>
  1369. <Description>TIL barrier end set in number of 8kb sectors</Description>
  1370. <BitOffset>0x10</BitOffset>
  1371. <BitWidth>0x7</BitWidth>
  1372. <Access>W</Access>
  1373. <Equation multiplier="0x2000" offset="0x00000001"/>
  1374. </Bit>
  1375. </AssignedBits>
  1376. </Field>
  1377. </Category>
  1378. </Bank>
  1379. </Configuration>
  1380. <Configuration config="1,2">
  1381. <Bank interface="JTAG_SWD">
  1382. <Parameters address="0x50022050" name="Bank 1" size="0x70"/>
  1383. <Category>
  1384. <Name>Product state</Name>
  1385. <Field>
  1386. <Parameters address="0x50022050" name="CUR" size="0x4"/>
  1387. <AssignedBits>
  1388. <Bit>
  1389. <Name>PRODUCT_STATE</Name>
  1390. <Description>Life state code.</Description>
  1391. <BitOffset>0x8</BitOffset>
  1392. <BitWidth>0x8</BitWidth>
  1393. <Access>R</Access>
  1394. <Values>
  1395. <Val value="0xB4">ST-VIRGIN</Val>
  1396. <Val value="0x39">ST-OPEN</Val>
  1397. <Val value="0x4B">ST-SFI-READY</Val>
  1398. <Val value="0xED">ST-ROT-READY</Val>
  1399. <Val value="0x17">OEM-provisioning</Val>
  1400. <Val value="0x2E">OEM-provisioned</Val>
  1401. <Val value="0xC6">TZ-OEM-Closed</Val>
  1402. <Val value="0x72">OEM-Closed</Val>
  1403. <Val value="0x5C">OEM-Locked</Val>
  1404. <Val value="0x9A">OEM-Unconstrained-Debug</Val>
  1405. <Val value="0xA3">OEM-NS-Unconstrained-Debug</Val>
  1406. </Values>
  1407. </Bit>
  1408. </AssignedBits>
  1409. </Field>
  1410. <Field>
  1411. <Parameters address="0x50022054" name="PRG" size="0x4"/>
  1412. <AssignedBits>
  1413. <Bit>
  1414. <Name>PRODUCT_STATE</Name>
  1415. <Description>Life state code.</Description>
  1416. <BitOffset>0x8</BitOffset>
  1417. <BitWidth>0x8</BitWidth>
  1418. <Access>W</Access>
  1419. <Values>
  1420. <Val value="0xB4">ST-VIRGIN</Val>
  1421. <Val value="0x39">ST-OPEN</Val>
  1422. <Val value="0x4B">ST-SFI-READY</Val>
  1423. <Val value="0xED">ST-ROT-READY</Val>
  1424. <Val value="0x17">OEM-provisioning</Val>
  1425. <Val value="0x2E">OEM-provisioned</Val>
  1426. <Val value="0xC6">TZ-OEM-Closed</Val>
  1427. <Val value="0x72">OEM-Closed</Val>
  1428. <Val value="0x5C">OEM-Locked</Val>
  1429. <Val value="0x9A">OEM-Unconstrained-Debug</Val>
  1430. <Val value="0xA3">OEM-NS-Unconstrained-Debug</Val>
  1431. </Values>
  1432. </Bit>
  1433. </AssignedBits>
  1434. </Field>
  1435. </Category>
  1436. <Category>
  1437. <Name>BOR Level</Name>
  1438. <Field>
  1439. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1440. <AssignedBits>
  1441. <Bit>
  1442. <Name>BOR_LEV</Name>
  1443. <Description>Brownout level option status bit.</Description>
  1444. <BitOffset>0x0</BitOffset>
  1445. <BitWidth>0x2</BitWidth>
  1446. <Access>R</Access>
  1447. <Values>
  1448. <Val value="0x0">BOR OFF, POR/PDR reset threshold level is applied</Val>
  1449. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  1450. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  1451. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  1452. </Values>
  1453. </Bit>
  1454. </AssignedBits>
  1455. </Field>
  1456. <Field>
  1457. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1458. <AssignedBits>
  1459. <Bit>
  1460. <Name>BOR_LEV</Name>
  1461. <Description>Brownout level option status bit.</Description>
  1462. <BitOffset>0x0</BitOffset>
  1463. <BitWidth>0x2</BitWidth>
  1464. <Access>W</Access>
  1465. <Values>
  1466. <Val value="0x0">BOR OFF, POR/PDR reset threshold level is applied</Val>
  1467. <Val value="0x1">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
  1468. <Val value="0x2">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
  1469. <Val value="0x3">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
  1470. </Values>
  1471. </Bit>
  1472. </AssignedBits>
  1473. </Field>
  1474. </Category>
  1475. <Category>
  1476. <Name>User Configuration</Name>
  1477. <Field>
  1478. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1479. <AssignedBits>
  1480. <Bit>
  1481. <Name>VDDIO_HSLV</Name>
  1482. <Description>VDD I/O high-speed at low-voltage status bit.</Description>
  1483. <BitOffset>0x10</BitOffset>
  1484. <BitWidth>0x4</BitWidth>
  1485. <Access>R</Access>
  1486. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  1487. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  1488. </Bit>
  1489. </AssignedBits>
  1490. </Field>
  1491. <Field>
  1492. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1493. <AssignedBits>
  1494. <Bit>
  1495. <Name>VDDIO_HSLV</Name>
  1496. <Description>VDD I/O high-speed at low-voltage status bit.</Description>
  1497. <BitOffset>0x10</BitOffset>
  1498. <BitWidth>0x4</BitWidth>
  1499. <Access>W</Access>
  1500. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  1501. <Val value="0x1">VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  1502. </Bit>
  1503. </AssignedBits>
  1504. </Field>
  1505. <Field>
  1506. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1507. <AssignedBits>
  1508. <Bit>
  1509. <Name>IWDG_STOP</Name>
  1510. <Description>Stop mode freeze option status bit.</Description>
  1511. <BitOffset>0x14</BitOffset>
  1512. <BitWidth>0x1</BitWidth>
  1513. <Access>R</Access>
  1514. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  1515. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  1516. </Bit>
  1517. </AssignedBits>
  1518. </Field>
  1519. <Field>
  1520. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1521. <AssignedBits>
  1522. <Bit>
  1523. <Name>IWDG_STOP</Name>
  1524. <Description>Stop mode freeze option status bit.</Description>
  1525. <BitOffset>0x14</BitOffset>
  1526. <BitWidth>0x1</BitWidth>
  1527. <Access>W</Access>
  1528. <Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
  1529. <Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
  1530. </Bit>
  1531. </AssignedBits>
  1532. </Field>
  1533. <Field>
  1534. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1535. <AssignedBits>
  1536. <Bit>
  1537. <Name>BOOT_UBE</Name>
  1538. <Description>Unique boot entry control, selects either ST or OEM iRoT for secure boot.</Description>
  1539. <BitOffset>0x16</BitOffset>
  1540. <BitWidth>0x8</BitWidth>
  1541. <Access>R</Access>
  1542. <Val value="0xB4">OEM-iRoT (system flash) selected</Val>
  1543. <Val value="0xC3">ST-iRoT (user flash) selected</Val>
  1544. </Bit>
  1545. </AssignedBits>
  1546. </Field>
  1547. <Field>
  1548. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1549. <AssignedBits>
  1550. <Bit>
  1551. <Name>BOOT_UBE</Name>
  1552. <Description>Unique boot entry control, selects either ST or OEM iRoT for secure boot.</Description>
  1553. <BitOffset>0x16</BitOffset>
  1554. <BitWidth>0x8</BitWidth>
  1555. <Access>W</Access>
  1556. <Val value="0xB4">OEM-iRoT (system flash) selected</Val>
  1557. <Val value="0xC3">ST-iRoT (user flash) selected</Val>
  1558. </Bit>
  1559. </AssignedBits>
  1560. </Field>
  1561. <Field>
  1562. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1563. <AssignedBits>
  1564. <Bit>
  1565. <Name>SWAP_BANK</Name>
  1566. <Description>Bank swapping option status bit.</Description>
  1567. <BitOffset>0x1F</BitOffset>
  1568. <BitWidth>0x1</BitWidth>
  1569. <Access>R</Access>
  1570. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  1571. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  1572. </Bit>
  1573. </AssignedBits>
  1574. </Field>
  1575. <Field>
  1576. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1577. <AssignedBits>
  1578. <Bit>
  1579. <Name>SWAP_BANK</Name>
  1580. <Description>Bank swapping option status bit.</Description>
  1581. <BitOffset>0x1F</BitOffset>
  1582. <BitWidth>0x1</BitWidth>
  1583. <Access>W</Access>
  1584. <Val value="0x0">bank 1 and bank 2 not swapped</Val>
  1585. <Val value="0x1">bank 1 and bank 2 swapped</Val>
  1586. </Bit>
  1587. </AssignedBits>
  1588. </Field>
  1589. <Field>
  1590. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1591. <AssignedBits>
  1592. <Bit>
  1593. <Name>IWDG_SW</Name>
  1594. <Description>IWDG control mode option status bit.</Description>
  1595. <BitOffset>0x3</BitOffset>
  1596. <BitWidth>0x1</BitWidth>
  1597. <Access>R</Access>
  1598. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  1599. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  1600. </Bit>
  1601. </AssignedBits>
  1602. </Field>
  1603. <Field>
  1604. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1605. <AssignedBits>
  1606. <Bit>
  1607. <Name>IWDG_SW</Name>
  1608. <Description>IWDG control mode option status bit.</Description>
  1609. <BitOffset>0x3</BitOffset>
  1610. <BitWidth>0x1</BitWidth>
  1611. <Access>W</Access>
  1612. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  1613. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  1614. </Bit>
  1615. </AssignedBits>
  1616. </Field>
  1617. <Field>
  1618. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1619. <AssignedBits>
  1620. <Bit>
  1621. <Name>WWDG_SW</Name>
  1622. <Description>IWDG control mode option status bit.</Description>
  1623. <BitOffset>0x4</BitOffset>
  1624. <BitWidth>0x1</BitWidth>
  1625. <Access>R</Access>
  1626. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  1627. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  1628. </Bit>
  1629. </AssignedBits>
  1630. </Field>
  1631. <Field>
  1632. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1633. <AssignedBits>
  1634. <Bit>
  1635. <Name>WWDG_SW</Name>
  1636. <Description>IWDG control mode option status bit.</Description>
  1637. <BitOffset>0x4</BitOffset>
  1638. <BitWidth>0x1</BitWidth>
  1639. <Access>W</Access>
  1640. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  1641. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  1642. </Bit>
  1643. </AssignedBits>
  1644. </Field>
  1645. <Field>
  1646. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1647. <AssignedBits>
  1648. <Bit>
  1649. <Name>NRST_SHDWN</Name>
  1650. <Description>Core domain Shutdown entry reset option status bit.</Description>
  1651. <BitOffset>0x5</BitOffset>
  1652. <BitWidth>0x1</BitWidth>
  1653. <Access>R</Access>
  1654. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  1655. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  1656. </Bit>
  1657. </AssignedBits>
  1658. </Field>
  1659. <Field>
  1660. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1661. <AssignedBits>
  1662. <Bit>
  1663. <Name>NRST_SHDWN</Name>
  1664. <Description>Core domain Shutdown entry reset option status bit.</Description>
  1665. <BitOffset>0x5</BitOffset>
  1666. <BitWidth>0x1</BitWidth>
  1667. <Access>W</Access>
  1668. <Val value="0x0">IWDG watchdog is controlled by hardware</Val>
  1669. <Val value="0x1">IWDG watchdog is controlled by software</Val>
  1670. </Bit>
  1671. </AssignedBits>
  1672. </Field>
  1673. <Field>
  1674. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1675. <AssignedBits>
  1676. <Bit>
  1677. <Name>NRST_STOP</Name>
  1678. <Description>Core domain DStop entry reset option status bit.</Description>
  1679. <BitOffset>0x6</BitOffset>
  1680. <BitWidth>0x1</BitWidth>
  1681. <Access>R</Access>
  1682. <Val value="0x0">a reset is generated when entering DStop or DStop2 mode on core domain</Val>
  1683. <Val value="0x1">no reset generated when entering DStop or DStop2 mode on core domain</Val>
  1684. </Bit>
  1685. </AssignedBits>
  1686. </Field>
  1687. <Field>
  1688. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1689. <AssignedBits>
  1690. <Bit>
  1691. <Name>NRST_STOP</Name>
  1692. <Description>Core domain DStop entry reset option status bit.</Description>
  1693. <BitOffset>0x6</BitOffset>
  1694. <BitWidth>0x1</BitWidth>
  1695. <Access>W</Access>
  1696. <Val value="0x0">a reset is generated when entering DStop or DStop2 mode on core domain</Val>
  1697. <Val value="0x1">no reset generated when entering DStop or DStop2 mode on core domain</Val>
  1698. </Bit>
  1699. </AssignedBits>
  1700. </Field>
  1701. <Field>
  1702. <Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
  1703. <AssignedBits>
  1704. <Bit>
  1705. <Name>NRST_STDY</Name>
  1706. <Description>Core domain Standby entry reset option status bit.</Description>
  1707. <BitOffset>0x7</BitOffset>
  1708. <BitWidth>0x1</BitWidth>
  1709. <Access>R</Access>
  1710. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  1711. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  1712. </Bit>
  1713. </AssignedBits>
  1714. </Field>
  1715. <Field>
  1716. <Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
  1717. <AssignedBits>
  1718. <Bit>
  1719. <Name>NRST_STDY</Name>
  1720. <Description>Core domain Standby entry reset option status bit.</Description>
  1721. <BitOffset>0x7</BitOffset>
  1722. <BitWidth>0x1</BitWidth>
  1723. <Access>W</Access>
  1724. <Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
  1725. <Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
  1726. </Bit>
  1727. </AssignedBits>
  1728. </Field>
  1729. <Field>
  1730. <Parameters address="0x50022058" name="FLASH_SECIPR" size="0x4"/>
  1731. <AssignedBits>
  1732. <Bit>
  1733. <Name>USB_EN</Name>
  1734. <Description>USB peripheral enable bit</Description>
  1735. <BitOffset>0xE</BitOffset>
  1736. <BitWidth>0x1</BitWidth>
  1737. <Access>R</Access>
  1738. <Values>
  1739. <Val value="0x0">USB communication disabled</Val>
  1740. <Val value="0x1">USB communication enabled</Val>
  1741. </Values>
  1742. </Bit>
  1743. <Bit>
  1744. <Name>HASH_EN</Name>
  1745. <Description>HASH SHA IP enable bit.</Description>
  1746. <BitOffset>0xD</BitOffset>
  1747. <BitWidth>0x1</BitWidth>
  1748. <Access>R</Access>
  1749. <Values>
  1750. <Val value="0x0">HASH feature disabled</Val>
  1751. <Val value="0x1">HASH feature enabled</Val>
  1752. </Values>
  1753. </Bit>
  1754. <Bit>
  1755. <Name>RNG_EN</Name>
  1756. <Description>random number generator IP enable bit</Description>
  1757. <BitOffset>0xC</BitOffset>
  1758. <BitWidth>0x1</BitWidth>
  1759. <Access>R</Access>
  1760. <Values>
  1761. <Val value="0x0">HASH feature disabled</Val>
  1762. <Val value="0x1">HASH feature enabled</Val>
  1763. </Values>
  1764. </Bit>
  1765. <Bit>
  1766. <Name>PKA_EN</Name>
  1767. <Description>public key cryptography IP enable bit</Description>
  1768. <BitOffset>0xB</BitOffset>
  1769. <BitWidth>0x1</BitWidth>
  1770. <Access>R</Access>
  1771. <Values>
  1772. <Val value="0x0">HASH feature disabled</Val>
  1773. <Val value="0x1">HASH feature enabled</Val>
  1774. </Values>
  1775. </Bit>
  1776. <Bit>
  1777. <Name>AES_EN</Name>
  1778. <Description/>
  1779. <BitOffset>0xA</BitOffset>
  1780. <BitWidth>0x1</BitWidth>
  1781. <Access>R</Access>
  1782. <Values>
  1783. <Val value="0x0">HASH feature disabled</Val>
  1784. <Val value="0x1">HASH feature enabled</Val>
  1785. </Values>
  1786. </Bit>
  1787. <Bit>
  1788. <Name>RSS_OPT</Name>
  1789. <Description/>
  1790. <BitOffset>0x7</BitOffset>
  1791. <BitWidth>0x3</BitWidth>
  1792. <Access>R</Access>
  1793. <Values>
  1794. <!--Val value="0x0">Freeze IWDG counter in stop mode</Val-->
  1795. <!--Val value="0x1">IWDG counter active in stop mode</Val-->
  1796. </Values>
  1797. </Bit>
  1798. <Bit>
  1799. <Name>FLASH_SIZE</Name>
  1800. <Description/>
  1801. <BitOffset>0x4</BitOffset>
  1802. <BitWidth>0x3</BitWidth>
  1803. <Access>R</Access>
  1804. <Values>
  1805. <Val value="0x0">512kB product</Val>
  1806. <Val value="0x1">1MB product</Val>
  1807. <Val value="0x2">2MB product</Val>
  1808. </Values>
  1809. </Bit>
  1810. <Bit>
  1811. <Name>GFX_EN</Name>
  1812. <Description>GFX module option status bit</Description>
  1813. <BitOffset>0x3</BitOffset>
  1814. <BitWidth>0x1</BitWidth>
  1815. <Access>R</Access>
  1816. <Values>
  1817. <Val value="0x0">GFX disabled</Val>
  1818. <Val value="0x1">GFX enabled</Val>
  1819. </Values>
  1820. </Bit>
  1821. <Bit>
  1822. <Name>OTFDEC_EN</Name>
  1823. <Description>OTFDEC option status bit. Controls on the fly decryption of external memory</Description>
  1824. <BitOffset>0x2</BitOffset>
  1825. <BitWidth>0x1</BitWidth>
  1826. <Access>R</Access>
  1827. <Values>
  1828. <Val value="0x0">OTFDEC disabled</Val>
  1829. <Val value="0x1">OTFDEC enbled</Val>
  1830. </Values>
  1831. </Bit>
  1832. <Bit>
  1833. <Name>SAES_EN</Name>
  1834. <Description>Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage</Description>
  1835. <BitOffset>0x1</BitOffset>
  1836. <BitWidth>0x1</BitWidth>
  1837. <Access>R</Access>
  1838. <Values>
  1839. <Val value="0x0">SAES disabled</Val>
  1840. <Val value="0x1">SAES enabled</Val>
  1841. </Values>
  1842. </Bit>
  1843. <Bit>
  1844. <Name>CAN_EN</Name>
  1845. <Description>CAN module control bit</Description>
  1846. <BitOffset>0x0</BitOffset>
  1847. <BitWidth>0x1</BitWidth>
  1848. <Access>R</Access>
  1849. <Values>
  1850. <Val value="0x0">CAN disabled</Val>
  1851. <Val value="0x1">CAN enabled</Val>
  1852. </Values>
  1853. </Bit>
  1854. </AssignedBits>
  1855. </Field>
  1856. <Field>
  1857. <Parameters address="0x5002205C" name="FLASH_SECIPR" size="0x4"/>
  1858. <AssignedBits>
  1859. <Bit>
  1860. <Name>USB_EN</Name>
  1861. <Description>USB peripheral enable bit.</Description>
  1862. <BitOffset>0xE</BitOffset>
  1863. <BitWidth>0x1</BitWidth>
  1864. <Access>W</Access>
  1865. <Values>
  1866. <Val value="0x0">USB communication disabled</Val>
  1867. <Val value="0x1">USB communication enabled</Val>
  1868. </Values>
  1869. </Bit>
  1870. <Bit>
  1871. <Name>HASH_EN</Name>
  1872. <Description>HASH SHA IP enable bit.</Description>
  1873. <BitOffset>0xD</BitOffset>
  1874. <BitWidth>0x1</BitWidth>
  1875. <Access>W</Access>
  1876. <Values>
  1877. <Val value="0x0">HASH feature disabled</Val>
  1878. <Val value="0x1">HASH feature enabled</Val>
  1879. </Values>
  1880. </Bit>
  1881. <Bit>
  1882. <Name>RNG_EN</Name>
  1883. <Description>random number generator IP enable bit</Description>
  1884. <BitOffset>0xC</BitOffset>
  1885. <BitWidth>0x1</BitWidth>
  1886. <Access>W</Access>
  1887. <Values>
  1888. <Val value="0x0">HASH feature disabled</Val>
  1889. <Val value="0x1">HASH feature enabled</Val>
  1890. </Values>
  1891. </Bit>
  1892. <Bit>
  1893. <Name>PKA_EN</Name>
  1894. <Description>public key cryptography IP enable bit</Description>
  1895. <BitOffset>0xB</BitOffset>
  1896. <BitWidth>0x1</BitWidth>
  1897. <Access>W</Access>
  1898. <Values>
  1899. <Val value="0x0">HASH feature disabled</Val>
  1900. <Val value="0x1">HASH feature enabled</Val>
  1901. </Values>
  1902. </Bit>
  1903. <Bit>
  1904. <Name>AES_EN</Name>
  1905. <Description/>
  1906. <BitOffset>0xA</BitOffset>
  1907. <BitWidth>0x1</BitWidth>
  1908. <Access>W</Access>
  1909. <Values>
  1910. <Val value="0x0">HASH feature disabled</Val>
  1911. <Val value="0x1">HASH feature enabled</Val>
  1912. </Values>
  1913. </Bit>
  1914. <Bit>
  1915. <Name>RSS_OPT</Name>
  1916. <Description/>
  1917. <BitOffset>0x7</BitOffset>
  1918. <BitWidth>0x3</BitWidth>
  1919. <Access>W</Access>
  1920. <Values>
  1921. <!--Val value="0x0">Freeze IWDG counter in stop mode</Val-->
  1922. <!--Val value="0x1">IWDG counter active in stop mode</Val-->
  1923. </Values>
  1924. </Bit>
  1925. <Bit>
  1926. <Name>FLASH_SIZE</Name>
  1927. <Description/>
  1928. <BitOffset>0x4</BitOffset>
  1929. <BitWidth>0x3</BitWidth>
  1930. <Access>W</Access>
  1931. <Values>
  1932. <Val value="0x0">512kB product</Val>
  1933. <Val value="0x1">1MB product</Val>
  1934. <Val value="0x2">2MB product</Val>
  1935. </Values>
  1936. </Bit>
  1937. <Bit>
  1938. <Name>GFX_EN</Name>
  1939. <Description>GFX module option status bit</Description>
  1940. <BitOffset>0x3</BitOffset>
  1941. <BitWidth>0x1</BitWidth>
  1942. <Access>W</Access>
  1943. <Values>
  1944. <Val value="0x0">GFX disabled</Val>
  1945. <Val value="0x1">GFX enabled</Val>
  1946. </Values>
  1947. </Bit>
  1948. <Bit>
  1949. <Name>OTFDEC_EN</Name>
  1950. <Description>OTFDEC option status bit. Controls on the fly decryption of external memory</Description>
  1951. <BitOffset>0x2</BitOffset>
  1952. <BitWidth>0x1</BitWidth>
  1953. <Access>W</Access>
  1954. <Values>
  1955. <Val value="0x0">OTFDEC disabled</Val>
  1956. <Val value="0x1">OTFDEC enbled</Val>
  1957. </Values>
  1958. </Bit>
  1959. <Bit>
  1960. <Name>SAES_EN</Name>
  1961. <Description>Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage</Description>
  1962. <BitOffset>0x1</BitOffset>
  1963. <BitWidth>0x1</BitWidth>
  1964. <Access>W</Access>
  1965. <Values>
  1966. <Val value="0x0">SAES disabled</Val>
  1967. <Val value="0x1">SAES enabled</Val>
  1968. </Values>
  1969. </Bit>
  1970. <Bit>
  1971. <Name>CAN_EN</Name>
  1972. <Description>CAN module control bit</Description>
  1973. <BitOffset>0x0</BitOffset>
  1974. <BitWidth>0x1</BitWidth>
  1975. <Access>W</Access>
  1976. <Values>
  1977. <Val value="0x0">CAN disabled</Val>
  1978. <Val value="0x1">CAN enabled</Val>
  1979. </Values>
  1980. </Bit>
  1981. </AssignedBits>
  1982. </Field>
  1983. </Category>
  1984. </Bank>
  1985. <Bank interface="JTAG_SWD">
  1986. <Parameters address="0x50022070" name="Bank 2" size="0x10"/>
  1987. <Category>
  1988. <Name>User Configuration 2</Name>
  1989. <Field>
  1990. <Parameters address="0x50022070" name="FLASH_WRP1AR" size="0x4"/>
  1991. <AssignedBits>
  1992. <Bit>
  1993. <Name>TZEN</Name>
  1994. <Description>Trust Zone Enable configuration bits</Description>
  1995. <BitOffset>0x18</BitOffset>
  1996. <BitWidth>0x8</BitWidth>
  1997. <Access>R</Access>
  1998. <Values>
  1999. <Val value="0xC3">Trust zone disabled</Val>
  2000. <Val value="0xB4">Trust zone enabled</Val>
  2001. </Values>
  2002. </Bit>
  2003. <Bit>
  2004. <Name>HUK_PUF</Name>
  2005. <Description>This bit configures the nature and use of the unique key</Description>
  2006. <BitOffset>0xF</BitOffset>
  2007. <BitWidth>0x1</BitWidth>
  2008. <Access>R</Access>
  2009. <Values>
  2010. <Val value="0x0">The key is treated as HUK</Val>
  2011. <Val value="0x1">The key is treated as PUF</Val>
  2012. </Values>
  2013. </Bit>
  2014. <Bit>
  2015. <Name>USBPD_DB_DIS</Name>
  2016. <Description>USB power delivery configuration option bit</Description>
  2017. <BitOffset>0x8</BitOffset>
  2018. <BitWidth>0x1</BitWidth>
  2019. <Access>R</Access>
  2020. <Values>
  2021. <Val value="0x0">Disabled</Val>
  2022. <Val value="0x1">Enabled</Val>
  2023. </Values>
  2024. </Bit>
  2025. <Bit>
  2026. <Name>SRAM2_PAR</Name>
  2027. <Description>Parity in SRAM2 region configuration bit</Description>
  2028. <BitOffset>0x7</BitOffset>
  2029. <BitWidth>0x1</BitWidth>
  2030. <Access>R</Access>
  2031. <Values>
  2032. <Val value="0x0">The key is treated as HUK</Val>
  2033. <Val value="0x1">The key is treated as PUF</Val>
  2034. </Values>
  2035. </Bit>
  2036. <Bit>
  2037. <Name>SRAM2_ECC</Name>
  2038. <Description>ECC in SRAM2 region configuration bit</Description>
  2039. <BitOffset>0x6</BitOffset>
  2040. <BitWidth>0x1</BitWidth>
  2041. <Access>R</Access>
  2042. <Values>
  2043. <Val value="0x0">Disabled</Val>
  2044. <Val value="0x1">Enabled</Val>
  2045. </Values>
  2046. </Bit>
  2047. <Bit>
  2048. <Name>SRAM3_ECC</Name>
  2049. <Description>ECC in SRAM3 region configuration bit</Description>
  2050. <BitOffset>0x5</BitOffset>
  2051. <BitWidth>0x1</BitWidth>
  2052. <Access>R</Access>
  2053. <Values>
  2054. <Val value="0x0">Disabled</Val>
  2055. <Val value="0x1">Enabled</Val>
  2056. </Values>
  2057. </Bit>
  2058. <Bit>
  2059. <Name>BKPRAM_ECC</Name>
  2060. <Description>ECC in BKPRAM region configuration bit</Description>
  2061. <BitOffset>0x4</BitOffset>
  2062. <BitWidth>0x1</BitWidth>
  2063. <Access>R</Access>
  2064. <Values>
  2065. <Val value="0x0">Disabled</Val>
  2066. <Val value="0x1">Enabled</Val>
  2067. </Values>
  2068. </Bit>
  2069. <Bit>
  2070. <Name>SRAM2_RST</Name>
  2071. <Description/>
  2072. <BitOffset>0x3</BitOffset>
  2073. <BitWidth>0x1</BitWidth>
  2074. <Access>R</Access>
  2075. <Values>
  2076. <Val value="0x0">Disabled</Val>
  2077. <Val value="0x1">Enabled</Val>
  2078. </Values>
  2079. </Bit>
  2080. <Bit>
  2081. <Name>SRAM1_3_RST</Name>
  2082. <Description/>
  2083. <BitOffset>0x2</BitOffset>
  2084. <BitWidth>0x1</BitWidth>
  2085. <Access>R</Access>
  2086. <Values>
  2087. <Val value="0x0">Disabled</Val>
  2088. <Val value="0x1">Enabled</Val>
  2089. </Values>
  2090. </Bit>
  2091. </AssignedBits>
  2092. </Field>
  2093. <Field>
  2094. <Parameters address="0x50022074" name="FLASH_WRP1AR" size="0x4"/>
  2095. <AssignedBits>
  2096. <Bit>
  2097. <Name>TZEN</Name>
  2098. <Description>Trust Zone Enable configuration bits</Description>
  2099. <BitOffset>0x18</BitOffset>
  2100. <BitWidth>0x8</BitWidth>
  2101. <Access>W</Access>
  2102. <Values>
  2103. <Val value="0xC3">Trust zone disabled</Val>
  2104. <Val value="0xB4">Trust zone enabled</Val>
  2105. </Values>
  2106. </Bit>
  2107. <Bit>
  2108. <Name>HUK_PUF</Name>
  2109. <Description>This bit configures the nature and use of the unique key</Description>
  2110. <BitOffset>0xF</BitOffset>
  2111. <BitWidth>0x1</BitWidth>
  2112. <Access>W</Access>
  2113. <Values>
  2114. <Val value="0x0">The key is treated as HUK</Val>
  2115. <Val value="0x1">The key is treated as PUF</Val>
  2116. </Values>
  2117. </Bit>
  2118. <Bit>
  2119. <Name>USBPD_DB_DIS</Name>
  2120. <Description>USB power delivery configuration option bit</Description>
  2121. <BitOffset>0x8</BitOffset>
  2122. <BitWidth>0x1</BitWidth>
  2123. <Access>W</Access>
  2124. <Values>
  2125. <Val value="0x0">Disabled</Val>
  2126. <Val value="0x1">Enabled</Val>
  2127. </Values>
  2128. </Bit>
  2129. <Bit>
  2130. <Name>SRAM2_PAR</Name>
  2131. <Description>Parity in SRAM2 region configuration bit</Description>
  2132. <BitOffset>0x7</BitOffset>
  2133. <BitWidth>0x1</BitWidth>
  2134. <Access>W</Access>
  2135. <Values>
  2136. <Val value="0x0">The key is treated as HUK</Val>
  2137. <Val value="0x1">The key is treated as PUF</Val>
  2138. </Values>
  2139. </Bit>
  2140. <Bit>
  2141. <Name>SRAM2_ECC</Name>
  2142. <Description>ECC in SRAM2 region configuration bit</Description>
  2143. <BitOffset>0x6</BitOffset>
  2144. <BitWidth>0x1</BitWidth>
  2145. <Access>W</Access>
  2146. <Values>
  2147. <Val value="0x0">Disabled</Val>
  2148. <Val value="0x1">Enabled</Val>
  2149. </Values>
  2150. </Bit>
  2151. <Bit>
  2152. <Name>SRAM3_ECC</Name>
  2153. <Description>ECC in SRAM3 region configuration bit</Description>
  2154. <BitOffset>0x5</BitOffset>
  2155. <BitWidth>0x1</BitWidth>
  2156. <Access>W</Access>
  2157. <Values>
  2158. <Val value="0x0">Disabled</Val>
  2159. <Val value="0x1">Enabled</Val>
  2160. </Values>
  2161. </Bit>
  2162. <Bit>
  2163. <Name>BKPRAM_ECC</Name>
  2164. <Description>ECC in BKPRAM region configuration bit</Description>
  2165. <BitOffset>0x4</BitOffset>
  2166. <BitWidth>0x1</BitWidth>
  2167. <Access>W</Access>
  2168. <Values>
  2169. <Val value="0x0">Disabled</Val>
  2170. <Val value="0x1">Enabled</Val>
  2171. </Values>
  2172. </Bit>
  2173. <Bit>
  2174. <Name>SRAM2_RST</Name>
  2175. <Description></Description>
  2176. <BitOffset>0x3</BitOffset>
  2177. <BitWidth>0x1</BitWidth>
  2178. <Access>W</Access>
  2179. <Values>
  2180. <Val value="0x0">Disabled</Val>
  2181. <Val value="0x1">Enabled</Val>
  2182. </Values>
  2183. </Bit>
  2184. <Bit>
  2185. <Name>SRAM1_3_RST</Name>
  2186. <Description/>
  2187. <BitOffset>0x2</BitOffset>
  2188. <BitWidth>0x1</BitWidth>
  2189. <Access>W</Access>
  2190. <Values>
  2191. <Val value="0x0">Disabled</Val>
  2192. <Val value="0x1">Enabled</Val>
  2193. </Values>
  2194. </Bit>
  2195. </AssignedBits>
  2196. </Field>
  2197. </Category>
  2198. </Bank>
  2199. <Bank interface="JTAG_SWD">
  2200. <Parameters address="0x50022080" name="Bank 3" size="0x8"/>
  2201. <Category>
  2202. <Name>Boot Configuration</Name>
  2203. <Field>
  2204. <Parameters address="0x50022080" name="FLASH_WRP2AR" size="0x4"/>
  2205. <AssignedBits>
  2206. <Bit>
  2207. <Name>BOOT_ADDR_NS</Name>
  2208. <Description>Unique Boot Entry Secure Address</Description>
  2209. <BitOffset>0x8</BitOffset>
  2210. <BitWidth>0x10</BitWidth>
  2211. <Access>R</Access>
  2212. <Equation multiplier="0x2000" offset="0x08000000"/>
  2213. </Bit>
  2214. <Bit>
  2215. <Name>BOOT_LOCK_NS</Name>
  2216. <Description>A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings</Description>
  2217. <BitOffset>0x0</BitOffset>
  2218. <BitWidth>0x8</BitWidth>
  2219. <Access>R</Access>
  2220. <Equation multiplier="0x2000" offset="0x08000000"/>
  2221. </Bit>
  2222. </AssignedBits>
  2223. </Field>
  2224. <Field>
  2225. <Parameters address="0x50022084" name="FLASH_WRP2AR" size="0x4"/>
  2226. <AssignedBits>
  2227. <Bit>
  2228. <Name>BOOT_ADDR_NS</Name>
  2229. <Description>Unique Boot Entry Secure Address</Description>
  2230. <BitOffset>0x8</BitOffset>
  2231. <BitWidth>0x10</BitWidth>
  2232. <Access>W</Access>
  2233. <Equation multiplier="0x2000" offset="0x08000000"/>
  2234. </Bit>
  2235. <Bit>
  2236. <Name>BOOT_LOCK_NS</Name>
  2237. <Description>A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings</Description>
  2238. <BitOffset>0x0</BitOffset>
  2239. <BitWidth>0x8</BitWidth>
  2240. <Access>W</Access>
  2241. <Equation multiplier="0x2000" offset="0x08000000"/>
  2242. </Bit>
  2243. </AssignedBits>
  2244. </Field>
  2245. </Category>
  2246. </Bank>
  2247. <Bank interface="JTAG_SWD">
  2248. <Parameters address="0x500220E8" name="Bank 4" size="0x8"/>
  2249. <Category>
  2250. <Name>Write sector group protection 1</Name>
  2251. <Field>
  2252. <Parameters address="0x500220E8" name="FLASH_WRP2BR" size="0x4"/>
  2253. <AssignedBits>
  2254. <Bit>
  2255. <Name>WRPSGn1</Name>
  2256. <Description>Bank 1 sector group protection option status byte</Description>
  2257. <BitOffset>0x0</BitOffset>
  2258. <BitWidth>0x20</BitWidth>
  2259. <Access>R</Access>
  2260. <Equation multiplier="0x2000" offset="0x08000000"/>
  2261. </Bit>
  2262. </AssignedBits>
  2263. </Field>
  2264. <Field>
  2265. <Parameters address="0x500220EC" name="FLASH_WRP2BR" size="0x4"/>
  2266. <AssignedBits>
  2267. <Bit>
  2268. <Name>WRPSGn1</Name>
  2269. <Description>Bank 1 sector group protection option status byte</Description>
  2270. <BitOffset>0x0</BitOffset>
  2271. <BitWidth>0x20</BitWidth>
  2272. <Access>W</Access>
  2273. <Equation multiplier="0x2000" offset="0x08000000"/>
  2274. </Bit>
  2275. </AssignedBits>
  2276. </Field>
  2277. </Category>
  2278. </Bank>
  2279. <Bank interface="JTAG_SWD">
  2280. <Parameters address="0x500221E8" name="Bank 5" size="0x8"/>
  2281. <Category>
  2282. <Name>Write sector group protection 2</Name>
  2283. <Field>
  2284. <Parameters address="0x500221E8" name="FLASH_WRP2BR" size="0x4"/>
  2285. <AssignedBits>
  2286. <Bit>
  2287. <Name>WRPSGn2</Name>
  2288. <Description>Bank 2 sector group protection option status byte</Description>
  2289. <BitOffset>0x0</BitOffset>
  2290. <BitWidth>0x20</BitWidth>
  2291. <Access>R</Access>
  2292. <Equation multiplier="0x2000" offset="0x08000000"/>
  2293. </Bit>
  2294. </AssignedBits>
  2295. </Field>
  2296. <Field>
  2297. <Parameters address="0x500221E8" name="FLASH_WRP2BR" size="0x4"/>
  2298. <AssignedBits>
  2299. <Bit>
  2300. <Name>WRPSGn2</Name>
  2301. <Description>Bank 2 sector group protection option status byte</Description>
  2302. <BitOffset>0x0</BitOffset>
  2303. <BitWidth>0x20</BitWidth>
  2304. <Access>W</Access>
  2305. <Equation multiplier="0x2000" offset="0x08000000"/>
  2306. </Bit>
  2307. </AssignedBits>
  2308. </Field>
  2309. </Category>
  2310. </Bank>
  2311. <Bank interface="JTAG_SWD">
  2312. <Parameters address="0x50022090" name="Bank 6" size="0x8"/>
  2313. <Category>
  2314. <Name>OTP write protection</Name>
  2315. <Field>
  2316. <Parameters address="0x50022090" name="FLASH_WRP2BR" size="0x4"/>
  2317. <AssignedBits>
  2318. <Bit>
  2319. <Name>LOCKBL</Name>
  2320. <Description>OTP Block Lock</Description>
  2321. <BitOffset>0x0</BitOffset>
  2322. <BitWidth>0x20</BitWidth>
  2323. <Access>R</Access>
  2324. <Equation multiplier="0x2000" offset="0x00000000"/>
  2325. </Bit>
  2326. </AssignedBits>
  2327. </Field>
  2328. <Field>
  2329. <Parameters address="0x50022094" name="FLASH_WRP2BR" size="0x4"/>
  2330. <AssignedBits>
  2331. <Bit>
  2332. <Name>LOCKBL</Name>
  2333. <Description>OTP Block Lock</Description>
  2334. <BitOffset>0x0</BitOffset>
  2335. <BitWidth>0x20</BitWidth>
  2336. <Access>W</Access>
  2337. <Equation multiplier="0x2000" offset="0x00000000"/>
  2338. </Bit>
  2339. </AssignedBits>
  2340. </Field>
  2341. </Category>
  2342. </Bank>
  2343. <Bank interface="JTAG_SWD">
  2344. <Parameters address="0x500220F0" name="Bank 7" size="0x8"/>
  2345. <Category>
  2346. <Name>Flash data sectors</Name>
  2347. <Field>
  2348. <Parameters address="0x500220F0" name="FLASH_WRP2BR" size="0x4"/>
  2349. <AssignedBits>
  2350. <Bit>
  2351. <Name>DATA_EN</Name>
  2352. <Description>Bank1 Flash high-cycle data enable</Description>
  2353. <BitOffset>0xF</BitOffset>
  2354. <BitWidth>0x1</BitWidth>
  2355. <Access>R</Access>
  2356. <Values>
  2357. <Val value="0x0">No Flash high-cycle data area</Val>
  2358. <Val value="0x1">Flash high-cycle data is used</Val>
  2359. </Values>
  2360. </Bit>
  2361. <Bit>
  2362. <Name>DATA_SECTOR_START_1</Name>
  2363. <Description>DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1.</Description>
  2364. <BitOffset>0x0</BitOffset>
  2365. <BitWidth>0x3</BitWidth>
  2366. <Access>R</Access>
  2367. <Equation multiplier="0x1" offset="0x0"/>
  2368. </Bit>
  2369. </AssignedBits>
  2370. </Field>
  2371. <Field>
  2372. <Parameters address="0x500220F4" name="FLASH_WRP2BR" size="0x4"/>
  2373. <AssignedBits>
  2374. <Bit>
  2375. <Name>DATA_EN</Name>
  2376. <Description>Bank1 Flash high-cycle data enable</Description>
  2377. <BitOffset>0xF</BitOffset>
  2378. <BitWidth>0x1</BitWidth>
  2379. <Access>W</Access>
  2380. <Values>
  2381. <Val value="0x0">No Flash high-cycle data area</Val>
  2382. <Val value="0x1">Flash high-cycle data is used</Val>
  2383. </Values>
  2384. </Bit>
  2385. <Bit>
  2386. <Name>DATA_SECTOR_START_1</Name>
  2387. <Description>DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1.</Description>
  2388. <BitOffset>0x0</BitOffset>
  2389. <BitWidth>0x3</BitWidth>
  2390. <Access>W</Access>
  2391. <Equation multiplier="0x1" offset="0x0"/>
  2392. </Bit>
  2393. </AssignedBits>
  2394. </Field>
  2395. </Category>
  2396. </Bank>
  2397. <Bank interface="JTAG_SWD">
  2398. <Parameters address="0x500221F0" name="Bank 8" size="0x8"/>
  2399. <Category>
  2400. <Name>Flash data sectors</Name>
  2401. <Field>
  2402. <Parameters address="0x500221F0" name="FLASH_WRP2BR" size="0x4"/>
  2403. <AssignedBits>
  2404. <Bit>
  2405. <Name>DATA_EN_2</Name>
  2406. <Description>Bank1 Flash high-cycle data enable</Description>
  2407. <BitOffset>0xF</BitOffset>
  2408. <BitWidth>0x1</BitWidth>
  2409. <Access>R</Access>
  2410. <Values>
  2411. <Val value="0x0">No Flash high-cycle data area</Val>
  2412. <Val value="0x1">Flash high-cycle data is used</Val>
  2413. </Values>
  2414. </Bit>
  2415. <Bit>
  2416. <Name>DATA_SECTOR_START_2</Name>
  2417. <Description>DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2.</Description>
  2418. <BitOffset>0x0</BitOffset>
  2419. <BitWidth>0x3</BitWidth>
  2420. <Access>R</Access>
  2421. <Equation multiplier="0x1" offset="0x0"/>
  2422. </Bit>
  2423. </AssignedBits>
  2424. </Field>
  2425. <Field>
  2426. <Parameters address="0x500221F4" name="FLASH_WRP2BR" size="0x4"/>
  2427. <AssignedBits>
  2428. <Bit>
  2429. <Name>DATA_EN_2</Name>
  2430. <Description>Bank1 Flash high-cycle data enable</Description>
  2431. <BitOffset>0xF</BitOffset>
  2432. <BitWidth>0x1</BitWidth>
  2433. <Access>W</Access>
  2434. <Values>
  2435. <Val value="0x0">No Flash high-cycle data area</Val>
  2436. <Val value="0x1">Flash high-cycle data is used</Val>
  2437. </Values>
  2438. </Bit>
  2439. <Bit>
  2440. <Name>DATA_SECTOR_START_2</Name>
  2441. <Description>DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2.</Description>
  2442. <BitOffset>0x0</BitOffset>
  2443. <BitWidth>0x3</BitWidth>
  2444. <Access>W</Access>
  2445. <Equation multiplier="0x1" offset="0x0"/>
  2446. </Bit>
  2447. </AssignedBits>
  2448. </Field>
  2449. </Category>
  2450. </Bank>
  2451. <Bank interface="JTAG_SWD">
  2452. <Parameters address="0x50022060" name="Bank 9" size="0x10"/>
  2453. <Category>
  2454. <Name>Flash EPOCH</Name>
  2455. <Field>
  2456. <Parameters address="0x50022060" name="FLASH_WRP2BR" size="0x4"/>
  2457. <AssignedBits>
  2458. <Bit>
  2459. <Name>NS_EPOCH</Name>
  2460. <Description>Non Volatile Non Secure EPOCH counter</Description>
  2461. <BitOffset>0x0</BitOffset>
  2462. <BitWidth>0x18</BitWidth>
  2463. <Access>R</Access>
  2464. <Equation multiplier="0x1" offset="0x00000001"/>
  2465. </Bit>
  2466. </AssignedBits>
  2467. </Field>
  2468. <Field>
  2469. <Parameters address="0x50022064" name="FLASH_WRP2BR" size="0x4"/>
  2470. <AssignedBits>
  2471. <Bit>
  2472. <Name>NS_EPOCH</Name>
  2473. <Description>Non Volatile Non Secure EPOCH counter</Description>
  2474. <BitOffset>0x0</BitOffset>
  2475. <BitWidth>0x18</BitWidth>
  2476. <Access>W</Access>
  2477. <Equation multiplier="0x1" offset="0x00000001"/>
  2478. </Bit>
  2479. </AssignedBits>
  2480. </Field>
  2481. <Field>
  2482. <Parameters address="0x50022064" name="FLASH_WRP2BR" size="0x4"/>
  2483. <AssignedBits>
  2484. <Bit>
  2485. <Name>SEC_EPOCH</Name>
  2486. <Description>Non Volatile Secure EPOCH counter</Description>
  2487. <BitOffset>0x0</BitOffset>
  2488. <BitWidth>0x18</BitWidth>
  2489. <Access>R</Access>
  2490. <Equation multiplier="0x1" offset="0x00000001"/>
  2491. </Bit>
  2492. </AssignedBits>
  2493. </Field>
  2494. <Field>
  2495. <Parameters address="0x50022068" name="FLASH_WRP2BR" size="0x4"/>
  2496. <AssignedBits>
  2497. <Bit>
  2498. <Name>SEC_EPOCH</Name>
  2499. <Description>Non Volatile Secure EPOCH counter</Description>
  2500. <BitOffset>0x0</BitOffset>
  2501. <BitWidth>0x18</BitWidth>
  2502. <Access>W</Access>
  2503. <Equation multiplier="0x1" offset="0x00000001"/>
  2504. </Bit>
  2505. </AssignedBits>
  2506. </Field>
  2507. </Category>
  2508. </Bank>
  2509. <Bank interface="JTAG_SWD">
  2510. <Parameters address="0x500220F8" name="Bank 10" size="0x8"/>
  2511. <Category>
  2512. <Name>Flash HDP bank 1</Name>
  2513. <Field>
  2514. <Parameters address="0x500220F8" name="FLASH_WRP2BR" size="0x4"/>
  2515. <AssignedBits>
  2516. <Bit>
  2517. <Name>HDP1_STRT</Name>
  2518. <Description>TIL barrier start set in number of 8kb sectors</Description>
  2519. <BitOffset>0x0</BitOffset>
  2520. <BitWidth>0x7</BitWidth>
  2521. <Access>R</Access>
  2522. <Equation multiplier="0x2000" offset="0x00000001"/>
  2523. </Bit>
  2524. <Bit>
  2525. <Name>HDP1_END</Name>
  2526. <Description>TIL barrier end set in number of 8kb sectors</Description>
  2527. <BitOffset>0x10</BitOffset>
  2528. <BitWidth>0x7</BitWidth>
  2529. <Access>R</Access>
  2530. <Equation multiplier="0x2000" offset="0x00000001"/>
  2531. </Bit>
  2532. </AssignedBits>
  2533. </Field>
  2534. <Field>
  2535. <Parameters address="0x500220FC" name="FLASH_WRP2BR" size="0x4"/>
  2536. <AssignedBits>
  2537. <Bit>
  2538. <Name>HDP1_STRT</Name>
  2539. <Description>TIL barrier start set in number of 8kb sectors</Description>
  2540. <BitOffset>0x0</BitOffset>
  2541. <BitWidth>0x7</BitWidth>
  2542. <Access>W</Access>
  2543. <Equation multiplier="0x2000" offset="0x00000001"/>
  2544. </Bit>
  2545. <Bit>
  2546. <Name>HDP1_END</Name>
  2547. <Description>TIL barrier end set in number of 8kb sectors</Description>
  2548. <BitOffset>0x10</BitOffset>
  2549. <BitWidth>0x7</BitWidth>
  2550. <Access>W</Access>
  2551. <Equation multiplier="0x2000" offset="0x00000001"/>
  2552. </Bit>
  2553. </AssignedBits>
  2554. </Field>
  2555. </Category>
  2556. </Bank>
  2557. <Bank interface="JTAG_SWD">
  2558. <Parameters address="0x500221F8" name="Bank 11" size="0x8"/>
  2559. <Category>
  2560. <Name>Flash HDP bank 2</Name>
  2561. <Field>
  2562. <Parameters address="0x500221F8" name="FLASH_WRP2BR" size="0x4"/>
  2563. <AssignedBits>
  2564. <Bit>
  2565. <Name>HDP2_STRT</Name>
  2566. <Description>TIL barrier start set in number of 8kb sectors</Description>
  2567. <BitOffset>0x0</BitOffset>
  2568. <BitWidth>0x7</BitWidth>
  2569. <Access>R</Access>
  2570. <Equation multiplier="0x2000" offset="0x00000001"/>
  2571. </Bit>
  2572. <Bit>
  2573. <Name>HDP2_END</Name>
  2574. <Description>TIL barrier end set in number of 8kb sectors</Description>
  2575. <BitOffset>0x10</BitOffset>
  2576. <BitWidth>0x7</BitWidth>
  2577. <Access>R</Access>
  2578. <Equation multiplier="0x2000" offset="0x00000001"/>
  2579. </Bit>
  2580. </AssignedBits>
  2581. </Field>
  2582. <Field>
  2583. <Parameters address="0x500221FC" name="FLASH_WRP2BR" size="0x4"/>
  2584. <AssignedBits>
  2585. <Bit>
  2586. <Name>HDP2_STRT</Name>
  2587. <Description>TIL barrier start set in number of 8kb sectors</Description>
  2588. <BitOffset>0x0</BitOffset>
  2589. <BitWidth>0x7</BitWidth>
  2590. <Access>W</Access>
  2591. <Equation multiplier="0x2000" offset="0x00000001"/>
  2592. </Bit>
  2593. <Bit>
  2594. <Name>HDP2_END</Name>
  2595. <Description>TIL barrier end set in number of 8kb sectors</Description>
  2596. <BitOffset>0x10</BitOffset>
  2597. <BitWidth>0x7</BitWidth>
  2598. <Access>W</Access>
  2599. <Equation multiplier="0x2000" offset="0x00000001"/>
  2600. </Bit>
  2601. </AssignedBits>
  2602. </Field>
  2603. </Category>
  2604. </Bank>
  2605. </Configuration>
  2606. </Peripheral>
  2607. </Peripherals>
  2608. </Device>
  2609. </Root>