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- <?xml version="1.0" encoding="UTF-8"?>
- <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
- <Device>
- <DeviceID>0x450</DeviceID>
- <Vendor>STMicroelectronics</Vendor>
- <Type>MCU</Type>
- <CPU>Cortex-M7</CPU>
- <Name>STM32H7xx</Name>
- <Series>STM32H7</Series>
- <Description>ARM 32-bit Cortex-M7 and ARM 32-bit Cortex-M4 dual core based device</Description>
- <Configurations>
- <!-- JTAG_SWD Interface -->
- <Interface name="JTAG_SWD">
- <Configuration number="0x0"> <!-- Security extension available && multi-core-->
- <SecurityEx>
- <WriteRegister address="0x580244F4" value="0x2"/>
- <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
- </SecurityEx>
- <MultiCore>
- <ReadRegister address="0x0" mask="0x0" value="0x4"/>
- </MultiCore>
- <!--<RomLess>
- <ReadRegister address="0x1FF1E880" mask="0x80" value="0x00"/>
- </RomLess>-->
- </Configuration>
- <Configuration number="0x1"> <!-- Security extension not available && multi-core -->
- <SecurityEx>
- <WriteRegister address="0x580244F4" value="0x2"/>
- <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
- </SecurityEx>
- <MultiCore>
- <ReadRegister address="0x0" mask="0x0" value="0x4"/>
- </MultiCore>
- <!-- <RomLess>
- <ReadRegister address="0x1FF1E880" mask="0x80" value="0x00"/>
- </RomLess> -->
- </Configuration>
- <Configuration number="0x2"> <!-- Security extension available && single core -->
- <SecurityEx>
- <WriteRegister address="0x580244F4" value="0x2"/>
- <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
- </SecurityEx>
- <MultiCore>
- <ReadRegister address="0x0" mask="0x0" value="0x3"/>
- </MultiCore>
- <RomLess>
- <ReadRegister address="0x1FF1E880" mask="0x80" value="0x00"/>
- </RomLess>
- </Configuration>
- <Configuration number="0x3"> <!-- Security extension not available && single core -->
- <SecurityEx>
- <WriteRegister address="0x580244F4" value="0x2"/>
- <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
- </SecurityEx>
- <MultiCore>
- <ReadRegister address="0x0" mask="0x0" value="0x3"/>
- </MultiCore>
- <RomLess>
- <ReadRegister address="0x1FF1E880" mask="0x80" value="0x00"/>
- </RomLess>
- </Configuration>
- <!-- ROMLESS Configurations -->
- <Configuration number="0x4"> <!-- Security extension available && multi-core-->
- <SecurityEx>
- <WriteRegister address="0x580244F4" value="0x2"/>
- <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
- </SecurityEx>
- <MultiCore>
- <ReadRegister address="0x0" mask="0x0" value="0x4"/>
- </MultiCore>
- <RomLess>
- <ReadRegister address="0x1FF1E880" mask="0x80" value="0x80"/>
- </RomLess>
- </Configuration>
- <Configuration number="0x5"> <!-- Security extension not available && multi-core -->
- <SecurityEx>
- <WriteRegister address="0x580244F4" value="0x2"/>
- <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
- </SecurityEx>
- <MultiCore>
- <ReadRegister address="0x0" mask="0x0" value="0x4"/>
- </MultiCore>
- <RomLess>
- <ReadRegister address="0x1FF1E880" mask="0x80" value="0x80"/>
- </RomLess>
- </Configuration>
- <Configuration number="0x6"> <!-- Security extension available && single core -->
- <SecurityEx>
- <WriteRegister address="0x580244F4" value="0x2"/>
- <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
- </SecurityEx>
- <MultiCore>
- <ReadRegister address="0x0" mask="0x0" value="0x3"/>
- </MultiCore>
- <RomLess>
- <ReadRegister address="0x1FF1E880" mask="0x80" value="0x80"/>
- </RomLess>
- </Configuration>
- <Configuration number="0x7"> <!-- Security extension not available && single core -->
- <RomLess>
- <ReadRegister address="0x1FF1E880" mask="0x80" value="0x80"/>
- </RomLess>
- <SecurityEx>
- <WriteRegister address="0x580244F4" value="0x2"/>
- <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
- </SecurityEx>
- <MultiCore>
- <ReadRegister address="0x0" mask="0x0" value="0x3"/>
- </MultiCore>
- </Configuration>
- </Interface>
- <!-- Bootloader Interface -->
- <Interface name="Bootloader">
- <Configuration number="0x0"> <!-- Security extension availabe && multicore--> <!-- dummy always true -->
- <Dummy>
- <ReadRegister address="0x08000000" mask="0x0" value="0x0"/>
- </Dummy>
- </Configuration>
- </Interface>
- </Configurations>
- <!-- Peripherals -->
- <Peripherals>
- <!-- Embedded SRAM -->
- <Peripheral>
- <Name>Embedded SRAM</Name>
- <Type>Storage</Type>
- <Description/>
- <ErasedValue>0x00</ErasedValue>
- <Access>RWE</Access>
- <!-- 512 KB -->
- <Configuration>
- <Parameters address="0x24000000" name="SRAM" size="0x80000"/>
- <Description/>
- <Organization>Single</Organization>
- <Bank name="Bank 1">
- <Field>
- <Parameters address="0x24000000" name="SRAM" occurence="0x1" size="0x80000"/>
- </Field>
- </Bank>
- </Configuration>
- </Peripheral>
- <!-- Embedded Flash -->
- <Peripheral>
- <Name>Embedded Flash</Name>
- <Type>Storage</Type>
- <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
- <ErasedValue>0xFF</ErasedValue>
- <Access>RWE</Access>
- <FlashSize address="0x1FF1E880" default="0x200000"/>
- <!-- 2MB Dual Bank -->
- <Configuration config="0,1,2,3">
- <Parameters address="0x08000000" name="2 MBytes Dual Bank Embedded Flash" size="0x200000"/>
- <Description/>
- <Organization>Dual</Organization>
- <Allignement>0x20</Allignement>
- <Bank name="Bank 1">
- <Field>
- <Parameters address="0x08000000" name="sector0" occurence="0x8" size="0x20000"/>
- </Field>
- </Bank>
- <Bank name="Bank 2">
- <Field>
- <Parameters address="0x08100000" name="sector8" occurence="0x8" size="0x20000"/>
- </Field>
- </Bank>
- </Configuration>
- <!-- RomLess 128KB -->
- <Configuration config="4,5,6,7">
- <Parameters address="0x08000000" name="RomLess 128 KB Embedded Flash" size="0x20000"/>
- <Description/>
- <Organization>Single</Organization>
- <Allignement>0x20</Allignement>
- <Bank name="Bank 1">
- <Field>
- <Parameters address="0x08000000" name="sector0" occurence="0x1" size="0x20000"/>
- </Field>
- </Bank>
- </Configuration>
- </Peripheral>
- <!-- ITCM Flash -->
- <Peripheral>
- <Name>ITCM Flash</Name>
- <Type>Storage</Type>
- <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
- <ErasedValue>0xFF</ErasedValue>
- <Access>RWE</Access>
- <!-- 2MB Dual Bank -->
- <Configuration config="0,1,2,3">
- <Parameters address="0x00200000" name="2 MBytes Dual Bank Embedded Flash" size="0x200000"/>
- <Description/>
- <Organization>Dual</Organization>
- <Allignement>0x20</Allignement>
- <Bank name="Bank 1">
- <Field>
- <Parameters address="0x00200000" name="sector0" occurence="0x8" size="0x20000"/>
- </Field>
- </Bank>
- <Bank name="Bank 2">
- <Field>
- <Parameters address="0x00300000" name="sector8" occurence="0x8" size="0x20000"/>
- </Field>
- </Bank>
- </Configuration>
- <!-- RomLess 128KB -->
- <Configuration config="4,5,6,7">
- <Parameters address="0x00200000" name="RomLess 128 KB Embedded Flash" size="0x20000"/>
- <Description/>
- <Organization>Single</Organization>
- <Allignement>0x20</Allignement>
- <Bank name="Bank 1">
- <Field>
- <Parameters address="0x00200000" name="sector0" occurence="0x1" size="0x20000"/>
- </Field>
- </Bank>
- </Configuration>
- </Peripheral>
- <!-- Option Bytes -->
- <Peripheral>
- <Name>Option Bytes</Name>
- <Type>Configuration</Type>
- <Description/>
- <Access>RW</Access>
- <Bank>
- <Parameters address="0x5200201C" name="Bank 1" size="0x134"/>
- <Category>
- <Name>Read Out Protection</Name>
- <Field>
- <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>RDP</Name>
- <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
- <BitOffset>0x8</BitOffset>
- <BitWidth>0x8</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0xAA">Level 0, no protection</Val>
- <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
- <Val value="0xCC">Level 2, chip protection</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>RDP</Name>
- <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
- <BitOffset>0x8</BitOffset>
- <BitWidth>0x8</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0xAA">Level 0, no protection</Val>
- <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
- <Val value="0xCC">Level 2, chip protection</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- </Category>
- <Category>
- <Name>RSS</Name>
- <Field>
- <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>RSS1</Name>
- <Description/>
- <BitOffset>0x1A</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">No SFI process on going</Val>
- <Val value="0x1">SFI process started</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>RSS1</Name>
- <Description/>
- <BitOffset>0x1A</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">No SFI process on going</Val>
- <Val value="0x1">SFI process started</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- </Category>
- <Category>
- <Name>BOR Level</Name>
- <Field>
- <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>BOR_LEV</Name>
- <Description>These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds.</Description>
- <BitOffset>0x2</BitOffset>
- <BitWidth>0x2</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">reset level is set to VBOR0</Val>
- <Val value="0x1">reset level is set to VBOR1</Val>
- <Val value="0x2">reset level is set to VBOR2</Val>
- <Val value="0x3">reset level is set to VBOR3</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>BOR_LEV</Name>
- <Description>These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds.</Description>
- <BitOffset>0x2</BitOffset>
- <BitWidth>0x2</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">reset level is set to VBOR0</Val>
- <Val value="0x1">reset level is set to VBOR1</Val>
- <Val value="0x2">reset level is set to VBOR2</Val>
- <Val value="0x3">reset level is set to VBOR3</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- </Category>
- <Category>
- <Name>User Configuration</Name>
- <Field>
- <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>IWDG1_SW</Name>
- <Description/>
- <BitOffset>0x4</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">Independent watchdog is controlled by hardware</Val>
- <Val value="0x1">Independent watchdog is controlled by software</Val>
- </Values>
- </Bit>
- <Bit config="0,1,4,5">
- <Name>IWDG2_SW</Name>
- <Description/>
- <BitOffset>0x5</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">Independent watchdog is controlled by hardware</Val>
- <Val value="0x1">Independent watchdog is controlled by software</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>NRST_STOP_D1</Name>
- <Description/>
- <BitOffset>0x6</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
- <Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>NRST_STBY_D1</Name>
- <Description/>
- <BitOffset>0x7</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
- <Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>FZ_IWDG_STOP</Name>
- <Description/>
- <BitOffset>0x11</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
- <Val value="0x1">Independent watchdog is running in STOP mode</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>FZ_IWDG_SDBY</Name>
- <Description/>
- <BitOffset>0x12</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
- <Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
- </Values>
- </Bit>
- <Bit config="0,2">
- <Name>SECURITY</Name>
- <Description/>
- <BitOffset>0x15</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">Security feature disabled</Val>
- <Val value="0x1">Security feature enabled</Val>
- </Values>
- </Bit>
- <Bit config="0,1">
- <Name>BCM4</Name>
- <Description/>
- <BitOffset>0x16</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">CM4 boot disabled</Val>
- <Val value="0x1">CM4 boot enabled</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>BCM7</Name>
- <Description/>
- <BitOffset>0x17</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">CM7 boot disabled</Val>
- <Val value="0x1">CM7 boot enabled</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>NRST_STOP_D2</Name>
- <Description/>
- <BitOffset>0x18</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">STOP mode on Domain 2 is entering with reset</Val>
- <Val value="0x1">STOP mode on Domain 2 is entering without reset</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>NRST_STBY_D2</Name>
- <Description/>
- <BitOffset>0x19</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">STANDBY mode on Domain 2 is entering with reset</Val>
- <Val value="0x1">STANDBY mode on Domain 2 is entering without reset</Val>
- </Values>
- </Bit>
- <Bit config="0,1,2,3">
- <Name>SWAP_BANK</Name>
- <Description/>
- <BitOffset>0x1F</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">after boot loading, no swap for user sectors</Val>
- <Val value="0x1">after boot loading, user sectors swapped</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>IO_HSLV</Name>
- <Description> I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V</Description>
- <BitOffset>0x1D</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
- <Val value="0x1">Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>IWDG1_SW</Name>
- <Description/>
- <BitOffset>0x4</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">Independent watchdog is controlled by hardware</Val>
- <Val value="0x1">Independent watchdog is controlled by software</Val>
- </Values>
- </Bit>
- <Bit config="0,1,4,5">
- <Name>IWDG2_SW</Name>
- <Description/>
- <BitOffset>0x5</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">Independent watchdog is controlled by hardware</Val>
- <Val value="0x1">Independent watchdog is controlled by software</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>NRST_STOP_D1</Name>
- <Description/>
- <BitOffset>0x6</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
- <Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>NRST_STBY_D1</Name>
- <Description/>
- <BitOffset>0x7</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
- <Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>FZ_IWDG_STOP</Name>
- <Description/>
- <BitOffset>0x11</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
- <Val value="0x1">Independent watchdog is running in STOP mode</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>FZ_IWDG_SDBY</Name>
- <Description/>
- <BitOffset>0x12</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
- <Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
- </Values>
- </Bit>
- <Bit config="0,2,4,6">
- <Name>SECURITY</Name>
- <Description/>
- <BitOffset>0x15</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">Security feature disabled</Val>
- <Val value="0x1">Security feature enabled</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>IO_HSLV</Name>
- <Description> I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V</Description>
- <BitOffset>0x1D</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
- <Val value="0x1">Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
- </Values>
- </Bit>
- <Bit config="0,1,4,5">
- <Name>BCM4</Name>
- <Description/>
- <BitOffset>0x16</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">CM4 boot disabled</Val>
- <Val value="0x1">CM4 boot enabled</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>BCM7</Name>
- <Description/>
- <BitOffset>0x17</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">CM7 boot disabled</Val>
- <Val value="0x1">CM7 boot enabled</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>NRST_STOP_D2</Name>
- <Description/>
- <BitOffset>0x18</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">STOP mode on Domain 2 is entering with reset</Val>
- <Val value="0x1">STOP mode on Domain 2 is entering without reset</Val>
- </Values>
- </Bit>
- <Bit>
- <Name>NRST_STBY_D2</Name>
- <Description/>
- <BitOffset>0x19</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">STANDBY mode on Domain 2 is entering with reset</Val>
- <Val value="0x1">STANDBY mode on Domain 2 is entering without reset</Val>
- </Values>
- </Bit>
- <Bit config="0,1,2,3">
- <Name>SWAP_BANK</Name>
- <Description/>
- <BitOffset>0x1F</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">after boot loading, no swap for user sectors</Val>
- <Val value="0x1">after boot loading, user sectors swapped</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- </Category>
- <Category>
- <Name>Boot address Option Bytes</Name>
- <Field>
- <Parameters address="0x52002040" name="FBOOT7_CUR" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>BOOT_CM7_ADD0</Name>
- <Description>Define the boot address for Cortex-M7 when BOOT0=0</Description>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0x10</BitWidth>
- <Access>R</Access>
- <Equation multiplier="0x10000" offset="0x0"/>
- </Bit>
- <Bit>
- <Name>BOOT_CM7_ADD1</Name>
- <Description>Define the boot address for Cortex-M7 when BOOT0=1</Description>
- <BitOffset>0x10</BitOffset>
- <BitWidth>0x10</BitWidth>
- <Access>R</Access>
- <Equation multiplier="0x10000" offset="0x0"/>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x52002048" name="FBOOT4_CUR" size="0x4"/>
- <AssignedBits>
- <Bit config="0,1,4,5">
- <Name>BOOT_CM4_ADD0</Name>
- <Description>Define the boot address for Cortex-M4 when BOOT0=0</Description>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0x10</BitWidth>
- <Access>R</Access>
- <Equation multiplier="0x10000" offset="0x0"/>
- </Bit>
- <Bit config="0,1,4,5">
- <Name>BOOT_CM4_ADD1</Name>
- <Description>Define the boot address for Cortex-M4 when BOOT0=1</Description>
- <BitOffset>0x10</BitOffset>
- <BitWidth>0x10</BitWidth>
- <Access>R</Access>
- <Equation multiplier="0x10000" offset="0x0"/>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x52002044" name="FBOOT7_PRG" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>BOOT_CM7_ADD0</Name>
- <Description/>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0x10</BitWidth>
- <Access>W</Access>
- <Equation multiplier="0x10000" offset="0x0"/>
- </Bit>
- <Bit>
- <Name>BOOT_CM7_ADD1</Name>
- <Description/>
- <BitOffset>0x10</BitOffset>
- <BitWidth>0x10</BitWidth>
- <Access>W</Access>
- <Equation multiplier="0x10000" offset="0x0"/>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x5200204C" name="FBOOT4_PRG" size="0x4"/>
- <AssignedBits>
- <Bit config="0,1,4,5">
- <Name>BOOT_CM4_ADD0</Name>
- <Description/>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0x10</BitWidth>
- <Access>W</Access>
- <Equation multiplier="0x10000" offset="0x0"/>
- </Bit>
- <Bit config="0,1,4,5">
- <Name>BOOT_CM4_ADD1</Name>
- <Description/>
- <BitOffset>0x10</BitOffset>
- <BitWidth>0x10</BitWidth>
- <Access>W</Access>
- <Equation multiplier="0x10000" offset="0x0"/>
- </Bit>
- </AssignedBits>
- </Field>
- </Category>
- <Category>
- <Name>PCROP Protection</Name>
- <Field>
- <Parameters address="0x52002028" name="FPRAR_CUR_A" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>PROT_AREA_START1</Name>
- <Description>Flash Bank 1 PCROP start address</Description>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>R</Access>
- <Equation multiplier="0x100" offset="0x08000000"/>
- </Bit>
- <Bit>
- <Name>PROT_AREA_END1</Name>
- <Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address.</Description>
- <BitOffset>0x10</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>R</Access>
- <Equation multiplier="0x100" offset="0x080000FF"/>
- </Bit>
- <Bit>
- <Name>DMEP1</Name>
- <Description/>
- <BitOffset>0x1F</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
- <Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x5200202C" name="FPRAR_PRG_A" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>PROT_AREA_START1</Name>
- <Description>Flash Bank 1 PCROP start address</Description>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>W</Access>
- <Equation multiplier="0x100" offset="0x08000000"/>
- </Bit>
- <Bit>
- <Name>PROT_AREA_END1</Name>
- <Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
- <BitOffset>0x10</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>W</Access>
- <Equation multiplier="0x100" offset="0x080000FF"/>
- </Bit>
- <Bit>
- <Name>DMEP1</Name>
- <Description/>
- <BitOffset>0x1F</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
- <Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x52002128" name="FPRAR_CUR_B" size="0x4"/>
- <AssignedBits>
- <Bit config="0,1,2,3">
- <Name>PROT_AREA_START2</Name>
- <Description>Flash Bank 2 PCROP start address</Description>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>R</Access>
- <Equation multiplier="0x100" offset="0x08100000"/>
- </Bit>
- <Bit config="0,1,2,3">
- <Name>PROT_AREA_END2</Name>
- <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
- <BitOffset>0x10</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>R</Access>
- <Equation multiplier="0x100" offset="0x081000FF"/>
- </Bit>
- <Bit config="0,1,2,3">
- <Name>DMEP2</Name>
- <Description/>
- <BitOffset>0x1F</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
- <Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x5200212C" name="FPRAR_PRG_B" size="0x4"/>
- <AssignedBits>
- <Bit config="0,1,2,3">
- <Name>PROT_AREA_START2</Name>
- <Description>Flash Bank 2 PCROP start address</Description>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>W</Access>
- <Equation multiplier="0x100" offset="0x08100000"/>
- </Bit>
- <Bit config="0,1,2,3">
- <Name>PROT_AREA_END2</Name>
- <Description>Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
- <BitOffset>0x10</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>W</Access>
- <Equation multiplier="0x100" offset="0x081000FF"/>
- </Bit>
- <Bit config="0,1,2,3">
- <Name>DMEP2</Name>
- <Description/>
- <BitOffset>0x1F</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
- <Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- </Category>
- <Category>
- <Name>Secure Protection</Name>
- <Field>
- <Parameters address="0x52002030" name="FSCAR_CUR_A" size="0x4"/>
- <AssignedBits>
- <Bit config="0,2,4,6">
- <Name>SEC_AREA_START1</Name>
- <Description>Flash Bank 1 secure area start address</Description>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>R</Access>
- <Equation multiplier="0x100" offset="0x08000000"/>
- </Bit>
- <Bit config="0,2,4,6">
- <Name>SEC_AREA_END1</Name>
- <Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
- <BitOffset>0x10</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>R</Access>
- <Equation multiplier="0x100" offset="0x080000FF"/>
- </Bit>
- <Bit config="0,2,4,6">
- <Name>DMES1</Name>
- <Description/>
- <BitOffset>0x1F</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
- <Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x52002034" name="FSCAR_PRG_A" size="0x4"/>
- <AssignedBits>
- <Bit config="0,2,4,6">
- <Name>SEC_AREA_START1</Name>
- <Description>Flash Bank 1 secure area start address</Description>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>W</Access>
- <Equation multiplier="0x100" offset="0x08000000"/>
- </Bit>
- <Bit config="0,2,4,6">
- <Name>SEC_AREA_END1</Name>
- <Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
- <BitOffset>0x10</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>W</Access>
- <Equation multiplier="0x100" offset="0x080000FF"/>
- </Bit>
- <Bit config="0,2,4,6">
- <Name>DMES1</Name>
- <Description/>
- <BitOffset>0x1F</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
- <Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x52002130" name="FSCAR_CUR_B" size="0x4"/>
- <AssignedBits>
- <Bit config="0,2">
- <Name>SEC_AREA_START2</Name>
- <Description>Flash Bank 2 secure area start address</Description>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>R</Access>
- <Equation multiplier="0x100" offset="0x08100000"/>
- </Bit>
- <Bit config="0,2">
- <Name>SEC_AREA_END2</Name>
- <Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
- <BitOffset>0x10</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>R</Access>
- <Equation multiplier="0x100" offset="0x081000FF"/>
- </Bit>
- <Bit config="0,2">
- <Name>DMES2</Name>
- <Description/>
- <BitOffset>0x1F</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
- <Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x52002134" name="FSCAR_PRG_B" size="0x4"/>
- <AssignedBits>
- <Bit config="0,2">
- <Name>SEC_AREA_START2</Name>
- <Description>Flash Bank 2 secure area start address</Description>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>W</Access>
- <Equation multiplier="0x100" offset="0x08100000"/>
- </Bit>
- <Bit config="0,2">
- <Name>SEC_AREA_END2</Name>
- <Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
- <BitOffset>0x10</BitOffset>
- <BitWidth>0xC</BitWidth>
- <Access>W</Access>
- <Equation multiplier="0x100" offset="0x081000FF"/>
- </Bit>
- <Bit config="0,2">
- <Name>DMES2</Name>
- <Description/>
- <BitOffset>0x1F</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
- <Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- </Category>
- <Category>
- <Name>DTCM RAM Protection</Name>
- <Field>
- <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>ST_RAM_SIZE</Name>
- <Description/>
- <BitOffset>0x13</BitOffset>
- <BitWidth>0x2</BitWidth>
- <Access>R</Access>
- <Values>
- <Val value="0x0">2 KB</Val>
- <Val value="0x1">4 KB</Val>
- <Val value="0x2">8 KB</Val>
- <Val value="0x3">16 KB</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
- <AssignedBits>
- <Bit>
- <Name>ST_RAM_SIZE</Name>
- <Description/>
- <BitOffset>0x13</BitOffset>
- <BitWidth>0x2</BitWidth>
- <Access>W</Access>
- <Values>
- <Val value="0x0">2 KB</Val>
- <Val value="0x1">4 KB</Val>
- <Val value="0x2">8 KB</Val>
- <Val value="0x3">16 KB</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- </Category>
- <Category>
- <Name>Write Protection</Name>
- <Field>
- <Parameters address="0x52002038" name="FWPSN_CUR_A" size="0x4"/>
- <AssignedBits>
- <Bit config="0,1,2,3">
- <Name>nWRP0</Name>
- <Description/>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0x8</BitWidth>
- <Access>R</Access>
- <Values ByBit="true">
- <Val value="0x0">Write protection active on this sector</Val>
- <Val value="0x1">Write protection not active on this sector</Val>
- </Values>
- </Bit>
- <Bit config="4,5,6,7">
- <Name>nWRP0</Name>
- <Description/>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>R</Access>
- <Values ByBit="true">
- <Val value="0x0">Write protection active on this sector</Val>
- <Val value="0x1">Write protection not active on this sector</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x5200203C" name="FWPSN_PRG_A" size="0x4"/>
- <AssignedBits>
- <Bit config="0,1,2,3">
- <Name>nWRP0</Name>
- <Description/>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0x8</BitWidth>
- <Access>W</Access>
- <Values ByBit="true">
- <Val value="0x0">Write protection active on this sector</Val>
- <Val value="0x1">Write protection not active on this sector</Val>
- </Values>
- </Bit>
- <Bit config="4,5,6,7">
- <Name>nWRP0</Name>
- <Description/>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0x1</BitWidth>
- <Access>W</Access>
- <Values ByBit="true">
- <Val value="0x0">Write protection active on this sector</Val>
- <Val value="0x1">Write protection not active on this sector</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x52002138" name="FWPSN_CUR_B" size="0x4"/>
- <AssignedBits>
- <Bit config="0,1,2,3">
- <Name>nWRP8</Name>
- <Description/>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0x8</BitWidth>
- <Access>R</Access>
- <Values ByBit="true">
- <Val value="0x0">Write protection active on this sector</Val>
- <Val value="0x1">Write protection not active on this sector</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- <Field>
- <Parameters address="0x5200213C" name="FWPSN_PRG_B" size="0x4"/>
- <AssignedBits>
- <Bit config="0,1,2,3">
- <Name>nWRP8</Name>
- <Description/>
- <BitOffset>0x0</BitOffset>
- <BitWidth>0x8</BitWidth>
- <Access>W</Access>
- <Values ByBit="true">
- <Val value="0x0">Write protection active on this sector</Val>
- <Val value="0x1">Write protection not active on this sector</Val>
- </Values>
- </Bit>
- </AssignedBits>
- </Field>
- </Category>
- </Bank>
- </Peripheral>
- </Peripherals>
- </Device>
- </Root>
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