STM32_Prog_DB_0x450.xml 40 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x450</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M7</CPU>
  8. <Name>STM32H7xx</Name>
  9. <Series>STM32H7</Series>
  10. <Description>ARM 32-bit Cortex-M7 and ARM 32-bit Cortex-M4 dual core based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- Security extension available && multi-core-->
  15. <SecurityEx>
  16. <WriteRegister address="0x580244F4" value="0x2"/>
  17. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  18. </SecurityEx>
  19. <MultiCore>
  20. <ReadRegister address="0x0" mask="0x0" value="0x4"/>
  21. </MultiCore>
  22. <!--<RomLess>
  23. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x00"/>
  24. </RomLess>-->
  25. </Configuration>
  26. <Configuration number="0x1"> <!-- Security extension not available && multi-core -->
  27. <SecurityEx>
  28. <WriteRegister address="0x580244F4" value="0x2"/>
  29. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  30. </SecurityEx>
  31. <MultiCore>
  32. <ReadRegister address="0x0" mask="0x0" value="0x4"/>
  33. </MultiCore>
  34. <!-- <RomLess>
  35. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x00"/>
  36. </RomLess> -->
  37. </Configuration>
  38. <Configuration number="0x2"> <!-- Security extension available && single core -->
  39. <SecurityEx>
  40. <WriteRegister address="0x580244F4" value="0x2"/>
  41. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  42. </SecurityEx>
  43. <MultiCore>
  44. <ReadRegister address="0x0" mask="0x0" value="0x3"/>
  45. </MultiCore>
  46. <RomLess>
  47. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x00"/>
  48. </RomLess>
  49. </Configuration>
  50. <Configuration number="0x3"> <!-- Security extension not available && single core -->
  51. <SecurityEx>
  52. <WriteRegister address="0x580244F4" value="0x2"/>
  53. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  54. </SecurityEx>
  55. <MultiCore>
  56. <ReadRegister address="0x0" mask="0x0" value="0x3"/>
  57. </MultiCore>
  58. <RomLess>
  59. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x00"/>
  60. </RomLess>
  61. </Configuration>
  62. <!-- ROMLESS Configurations -->
  63. <Configuration number="0x4"> <!-- Security extension available && multi-core-->
  64. <SecurityEx>
  65. <WriteRegister address="0x580244F4" value="0x2"/>
  66. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  67. </SecurityEx>
  68. <MultiCore>
  69. <ReadRegister address="0x0" mask="0x0" value="0x4"/>
  70. </MultiCore>
  71. <RomLess>
  72. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x80"/>
  73. </RomLess>
  74. </Configuration>
  75. <Configuration number="0x5"> <!-- Security extension not available && multi-core -->
  76. <SecurityEx>
  77. <WriteRegister address="0x580244F4" value="0x2"/>
  78. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  79. </SecurityEx>
  80. <MultiCore>
  81. <ReadRegister address="0x0" mask="0x0" value="0x4"/>
  82. </MultiCore>
  83. <RomLess>
  84. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x80"/>
  85. </RomLess>
  86. </Configuration>
  87. <Configuration number="0x6"> <!-- Security extension available && single core -->
  88. <SecurityEx>
  89. <WriteRegister address="0x580244F4" value="0x2"/>
  90. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  91. </SecurityEx>
  92. <MultiCore>
  93. <ReadRegister address="0x0" mask="0x0" value="0x3"/>
  94. </MultiCore>
  95. <RomLess>
  96. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x80"/>
  97. </RomLess>
  98. </Configuration>
  99. <Configuration number="0x7"> <!-- Security extension not available && single core -->
  100. <RomLess>
  101. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x80"/>
  102. </RomLess>
  103. <SecurityEx>
  104. <WriteRegister address="0x580244F4" value="0x2"/>
  105. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  106. </SecurityEx>
  107. <MultiCore>
  108. <ReadRegister address="0x0" mask="0x0" value="0x3"/>
  109. </MultiCore>
  110. </Configuration>
  111. </Interface>
  112. <!-- Bootloader Interface -->
  113. <Interface name="Bootloader">
  114. <Configuration number="0x0"> <!-- Security extension availabe && multicore--> <!-- dummy always true -->
  115. <Dummy>
  116. <ReadRegister address="0x08000000" mask="0x0" value="0x0"/>
  117. </Dummy>
  118. </Configuration>
  119. </Interface>
  120. </Configurations>
  121. <!-- Peripherals -->
  122. <Peripherals>
  123. <!-- Embedded SRAM -->
  124. <Peripheral>
  125. <Name>Embedded SRAM</Name>
  126. <Type>Storage</Type>
  127. <Description/>
  128. <ErasedValue>0x00</ErasedValue>
  129. <Access>RWE</Access>
  130. <!-- 512 KB -->
  131. <Configuration>
  132. <Parameters address="0x24000000" name="SRAM" size="0x80000"/>
  133. <Description/>
  134. <Organization>Single</Organization>
  135. <Bank name="Bank 1">
  136. <Field>
  137. <Parameters address="0x24000000" name="SRAM" occurence="0x1" size="0x80000"/>
  138. </Field>
  139. </Bank>
  140. </Configuration>
  141. </Peripheral>
  142. <!-- Embedded Flash -->
  143. <Peripheral>
  144. <Name>Embedded Flash</Name>
  145. <Type>Storage</Type>
  146. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  147. <ErasedValue>0xFF</ErasedValue>
  148. <Access>RWE</Access>
  149. <FlashSize address="0x1FF1E880" default="0x200000"/>
  150. <BootloaderVersion address="0x1FF1E7FE"/>
  151. <!-- 2MB Dual Bank -->
  152. <Configuration config="0,1,2,3">
  153. <Parameters address="0x08000000" name="2 MBytes Dual Bank Embedded Flash" size="0x200000"/>
  154. <Description/>
  155. <Organization>Dual</Organization>
  156. <Allignement>0x20</Allignement>
  157. <Bank name="Bank 1">
  158. <Field>
  159. <Parameters address="0x08000000" name="sector0" occurence="0x8" size="0x20000"/>
  160. </Field>
  161. </Bank>
  162. <Bank name="Bank 2">
  163. <Field>
  164. <Parameters address="0x08100000" name="sector8" occurence="0x8" size="0x20000"/>
  165. </Field>
  166. </Bank>
  167. </Configuration>
  168. <!-- RomLess 128KB -->
  169. <Configuration config="4,5,6,7">
  170. <Parameters address="0x08000000" name="RomLess 128 KB Embedded Flash" size="0x20000"/>
  171. <Description/>
  172. <Organization>Single</Organization>
  173. <Allignement>0x20</Allignement>
  174. <Bank name="Bank 1">
  175. <Field>
  176. <Parameters address="0x08000000" name="sector0" occurence="0x1" size="0x20000"/>
  177. </Field>
  178. </Bank>
  179. </Configuration>
  180. </Peripheral>
  181. <!-- ITCM Flash -->
  182. <Peripheral>
  183. <Name>ITCM Flash</Name>
  184. <Type>Storage</Type>
  185. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  186. <ErasedValue>0xFF</ErasedValue>
  187. <Access>RWE</Access>
  188. <!-- 2MB Dual Bank -->
  189. <Configuration config="0,1,2,3">
  190. <Parameters address="0x00200000" name="2 MBytes Dual Bank Embedded Flash" size="0x200000"/>
  191. <Description/>
  192. <Organization>Dual</Organization>
  193. <Allignement>0x20</Allignement>
  194. <Bank name="Bank 1">
  195. <Field>
  196. <Parameters address="0x00200000" name="sector0" occurence="0x8" size="0x20000"/>
  197. </Field>
  198. </Bank>
  199. <Bank name="Bank 2">
  200. <Field>
  201. <Parameters address="0x00300000" name="sector8" occurence="0x8" size="0x20000"/>
  202. </Field>
  203. </Bank>
  204. </Configuration>
  205. <!-- RomLess 128KB -->
  206. <Configuration config="4,5,6,7">
  207. <Parameters address="0x00200000" name="RomLess 128 KB Embedded Flash" size="0x20000"/>
  208. <Description/>
  209. <Organization>Single</Organization>
  210. <Allignement>0x20</Allignement>
  211. <Bank name="Bank 1">
  212. <Field>
  213. <Parameters address="0x00200000" name="sector0" occurence="0x1" size="0x20000"/>
  214. </Field>
  215. </Bank>
  216. </Configuration>
  217. </Peripheral>
  218. <!-- Option Bytes -->
  219. <Peripheral>
  220. <Name>Option Bytes</Name>
  221. <Type>Configuration</Type>
  222. <Description/>
  223. <Access>RW</Access>
  224. <Bank>
  225. <Parameters address="0x5200201C" name="Bank 1" size="0x134"/>
  226. <Category>
  227. <Name>Read Out Protection</Name>
  228. <Field>
  229. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  230. <AssignedBits>
  231. <Bit>
  232. <Name>RDP</Name>
  233. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  234. <BitOffset>0x8</BitOffset>
  235. <BitWidth>0x8</BitWidth>
  236. <Access>R</Access>
  237. <Values>
  238. <Val value="0xAA">Level 0, no protection</Val>
  239. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  240. <Val value="0xCC">Level 2, chip protection</Val>
  241. </Values>
  242. </Bit>
  243. </AssignedBits>
  244. </Field>
  245. <Field>
  246. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  247. <AssignedBits>
  248. <Bit>
  249. <Name>RDP</Name>
  250. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  251. <BitOffset>0x8</BitOffset>
  252. <BitWidth>0x8</BitWidth>
  253. <Access>W</Access>
  254. <Values>
  255. <Val value="0xAA">Level 0, no protection</Val>
  256. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  257. <Val value="0xCC">Level 2, chip protection</Val>
  258. </Values>
  259. </Bit>
  260. </AssignedBits>
  261. </Field>
  262. </Category>
  263. <Category>
  264. <Name>RSS</Name>
  265. <Field>
  266. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  267. <AssignedBits>
  268. <!--Bit>
  269. <Name>RSS1</Name>
  270. <Description/>
  271. <BitOffset>0x1A</BitOffset>
  272. <BitWidth>0x1</BitWidth>
  273. <Access>R</Access>
  274. <Values>
  275. <Val value="0x0">No SFI process on going</Val>
  276. <Val value="0x1">SFI process started</Val>
  277. </Values>
  278. </Bit-->
  279. </AssignedBits>
  280. </Field>
  281. <Field>
  282. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  283. <AssignedBits>
  284. <!--Bit>
  285. <Name>RSS1</Name>
  286. <Description/>
  287. <BitOffset>0x1A</BitOffset>
  288. <BitWidth>0x1</BitWidth>
  289. <Access>W</Access>
  290. <Values>
  291. <Val value="0x0">No SFI process on going</Val>
  292. <Val value="0x1">SFI process started</Val>
  293. </Values>
  294. </Bit-->
  295. </AssignedBits>
  296. </Field>
  297. </Category>
  298. <Category>
  299. <Name>BOR Level</Name>
  300. <Field>
  301. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  302. <AssignedBits>
  303. <Bit>
  304. <Name>BOR_LEV</Name>
  305. <Description>These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds.</Description>
  306. <BitOffset>0x2</BitOffset>
  307. <BitWidth>0x2</BitWidth>
  308. <Access>R</Access>
  309. <Values>
  310. <Val value="0x0">reset level is set to VBOR0</Val>
  311. <Val value="0x1">reset level is set to VBOR1</Val>
  312. <Val value="0x2">reset level is set to VBOR2</Val>
  313. <Val value="0x3">reset level is set to VBOR3</Val>
  314. </Values>
  315. </Bit>
  316. </AssignedBits>
  317. </Field>
  318. <Field>
  319. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  320. <AssignedBits>
  321. <Bit>
  322. <Name>BOR_LEV</Name>
  323. <Description>These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds.</Description>
  324. <BitOffset>0x2</BitOffset>
  325. <BitWidth>0x2</BitWidth>
  326. <Access>W</Access>
  327. <Values>
  328. <Val value="0x0">reset level is set to VBOR0</Val>
  329. <Val value="0x1">reset level is set to VBOR1</Val>
  330. <Val value="0x2">reset level is set to VBOR2</Val>
  331. <Val value="0x3">reset level is set to VBOR3</Val>
  332. </Values>
  333. </Bit>
  334. </AssignedBits>
  335. </Field>
  336. </Category>
  337. <Category>
  338. <Name>User Configuration</Name>
  339. <Field>
  340. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  341. <AssignedBits>
  342. <Bit>
  343. <Name>IWDG1_SW</Name>
  344. <Description/>
  345. <BitOffset>0x4</BitOffset>
  346. <BitWidth>0x1</BitWidth>
  347. <Access>R</Access>
  348. <Values>
  349. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  350. <Val value="0x1">Independent watchdog is controlled by software</Val>
  351. </Values>
  352. </Bit>
  353. <Bit config="0,1,4,5">
  354. <Name>IWDG2_SW</Name>
  355. <Description/>
  356. <BitOffset>0x5</BitOffset>
  357. <BitWidth>0x1</BitWidth>
  358. <Access>R</Access>
  359. <Values>
  360. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  361. <Val value="0x1">Independent watchdog is controlled by software</Val>
  362. </Values>
  363. </Bit>
  364. <Bit>
  365. <Name>NRST_STOP_D1</Name>
  366. <Description/>
  367. <BitOffset>0x6</BitOffset>
  368. <BitWidth>0x1</BitWidth>
  369. <Access>R</Access>
  370. <Values>
  371. <Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
  372. <Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
  373. </Values>
  374. </Bit>
  375. <Bit>
  376. <Name>NRST_STBY_D1</Name>
  377. <Description/>
  378. <BitOffset>0x7</BitOffset>
  379. <BitWidth>0x1</BitWidth>
  380. <Access>R</Access>
  381. <Values>
  382. <Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
  383. <Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
  384. </Values>
  385. </Bit>
  386. <Bit>
  387. <Name>FZ_IWDG_STOP</Name>
  388. <Description/>
  389. <BitOffset>0x11</BitOffset>
  390. <BitWidth>0x1</BitWidth>
  391. <Access>R</Access>
  392. <Values>
  393. <Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
  394. <Val value="0x1">Independent watchdog is running in STOP mode</Val>
  395. </Values>
  396. </Bit>
  397. <Bit>
  398. <Name>FZ_IWDG_SDBY</Name>
  399. <Description/>
  400. <BitOffset>0x12</BitOffset>
  401. <BitWidth>0x1</BitWidth>
  402. <Access>R</Access>
  403. <Values>
  404. <Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
  405. <Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
  406. </Values>
  407. </Bit>
  408. <Bit config="0,2,4,6">
  409. <Name>SECURITY</Name>
  410. <Description/>
  411. <BitOffset>0x15</BitOffset>
  412. <BitWidth>0x1</BitWidth>
  413. <Access>R</Access>
  414. <Values>
  415. <Val value="0x0">Security feature disabled</Val>
  416. <Val value="0x1">Security feature enabled</Val>
  417. </Values>
  418. </Bit>
  419. <Bit config="0,1">
  420. <Name>BCM4</Name>
  421. <Description/>
  422. <BitOffset>0x16</BitOffset>
  423. <BitWidth>0x1</BitWidth>
  424. <Access>R</Access>
  425. <Values>
  426. <Val value="0x0">CM4 boot disabled</Val>
  427. <Val value="0x1">CM4 boot enabled</Val>
  428. </Values>
  429. </Bit>
  430. <Bit>
  431. <Name>BCM7</Name>
  432. <Description/>
  433. <BitOffset>0x17</BitOffset>
  434. <BitWidth>0x1</BitWidth>
  435. <Access>R</Access>
  436. <Values>
  437. <Val value="0x0">CM7 boot disabled</Val>
  438. <Val value="0x1">CM7 boot enabled</Val>
  439. </Values>
  440. </Bit>
  441. <Bit>
  442. <Name>NRST_STOP_D2</Name>
  443. <Description/>
  444. <BitOffset>0x18</BitOffset>
  445. <BitWidth>0x1</BitWidth>
  446. <Access>R</Access>
  447. <Values>
  448. <Val value="0x0">STOP mode on Domain 2 is entering with reset</Val>
  449. <Val value="0x1">STOP mode on Domain 2 is entering without reset</Val>
  450. </Values>
  451. </Bit>
  452. <Bit>
  453. <Name>NRST_STBY_D2</Name>
  454. <Description/>
  455. <BitOffset>0x19</BitOffset>
  456. <BitWidth>0x1</BitWidth>
  457. <Access>R</Access>
  458. <Values>
  459. <Val value="0x0">STANDBY mode on Domain 2 is entering with reset</Val>
  460. <Val value="0x1">STANDBY mode on Domain 2 is entering without reset</Val>
  461. </Values>
  462. </Bit>
  463. <Bit config="0,1,2,3">
  464. <Name>SWAP_BANK</Name>
  465. <Description/>
  466. <BitOffset>0x1F</BitOffset>
  467. <BitWidth>0x1</BitWidth>
  468. <Access>R</Access>
  469. <Values>
  470. <Val value="0x0">after boot loading, no swap for user sectors</Val>
  471. <Val value="0x1">after boot loading, user sectors swapped</Val>
  472. </Values>
  473. </Bit>
  474. <Bit>
  475. <Name>IO_HSLV</Name>
  476. <Description> I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V</Description>
  477. <BitOffset>0x1D</BitOffset>
  478. <BitWidth>0x1</BitWidth>
  479. <Access>R</Access>
  480. <Values>
  481. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  482. <Val value="0x1">Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  483. </Values>
  484. </Bit>
  485. </AssignedBits>
  486. </Field>
  487. <Field>
  488. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  489. <AssignedBits>
  490. <Bit>
  491. <Name>IWDG1_SW</Name>
  492. <Description/>
  493. <BitOffset>0x4</BitOffset>
  494. <BitWidth>0x1</BitWidth>
  495. <Access>W</Access>
  496. <Values>
  497. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  498. <Val value="0x1">Independent watchdog is controlled by software</Val>
  499. </Values>
  500. </Bit>
  501. <Bit config="0,1,4,5">
  502. <Name>IWDG2_SW</Name>
  503. <Description/>
  504. <BitOffset>0x5</BitOffset>
  505. <BitWidth>0x1</BitWidth>
  506. <Access>W</Access>
  507. <Values>
  508. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  509. <Val value="0x1">Independent watchdog is controlled by software</Val>
  510. </Values>
  511. </Bit>
  512. <Bit>
  513. <Name>NRST_STOP_D1</Name>
  514. <Description/>
  515. <BitOffset>0x6</BitOffset>
  516. <BitWidth>0x1</BitWidth>
  517. <Access>W</Access>
  518. <Values>
  519. <Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
  520. <Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
  521. </Values>
  522. </Bit>
  523. <Bit>
  524. <Name>NRST_STBY_D1</Name>
  525. <Description/>
  526. <BitOffset>0x7</BitOffset>
  527. <BitWidth>0x1</BitWidth>
  528. <Access>W</Access>
  529. <Values>
  530. <Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
  531. <Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
  532. </Values>
  533. </Bit>
  534. <Bit>
  535. <Name>FZ_IWDG_STOP</Name>
  536. <Description/>
  537. <BitOffset>0x11</BitOffset>
  538. <BitWidth>0x1</BitWidth>
  539. <Access>W</Access>
  540. <Values>
  541. <Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
  542. <Val value="0x1">Independent watchdog is running in STOP mode</Val>
  543. </Values>
  544. </Bit>
  545. <Bit>
  546. <Name>FZ_IWDG_SDBY</Name>
  547. <Description/>
  548. <BitOffset>0x12</BitOffset>
  549. <BitWidth>0x1</BitWidth>
  550. <Access>W</Access>
  551. <Values>
  552. <Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
  553. <Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
  554. </Values>
  555. </Bit>
  556. <Bit config="0,2,4,6">
  557. <Name>SECURITY</Name>
  558. <Description/>
  559. <BitOffset>0x15</BitOffset>
  560. <BitWidth>0x1</BitWidth>
  561. <Access>W</Access>
  562. <Values>
  563. <Val value="0x0">Security feature disabled</Val>
  564. <Val value="0x1">Security feature enabled</Val>
  565. </Values>
  566. </Bit>
  567. <Bit>
  568. <Name>IO_HSLV</Name>
  569. <Description> I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V</Description>
  570. <BitOffset>0x1D</BitOffset>
  571. <BitWidth>0x1</BitWidth>
  572. <Access>W</Access>
  573. <Values>
  574. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  575. <Val value="0x1">Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  576. </Values>
  577. </Bit>
  578. <Bit config="0,1,4,5">
  579. <Name>BCM4</Name>
  580. <Description/>
  581. <BitOffset>0x16</BitOffset>
  582. <BitWidth>0x1</BitWidth>
  583. <Access>W</Access>
  584. <Values>
  585. <Val value="0x0">CM4 boot disabled</Val>
  586. <Val value="0x1">CM4 boot enabled</Val>
  587. </Values>
  588. </Bit>
  589. <Bit>
  590. <Name>BCM7</Name>
  591. <Description/>
  592. <BitOffset>0x17</BitOffset>
  593. <BitWidth>0x1</BitWidth>
  594. <Access>W</Access>
  595. <Values>
  596. <Val value="0x0">CM7 boot disabled</Val>
  597. <Val value="0x1">CM7 boot enabled</Val>
  598. </Values>
  599. </Bit>
  600. <Bit>
  601. <Name>NRST_STOP_D2</Name>
  602. <Description/>
  603. <BitOffset>0x18</BitOffset>
  604. <BitWidth>0x1</BitWidth>
  605. <Access>W</Access>
  606. <Values>
  607. <Val value="0x0">STOP mode on Domain 2 is entering with reset</Val>
  608. <Val value="0x1">STOP mode on Domain 2 is entering without reset</Val>
  609. </Values>
  610. </Bit>
  611. <Bit>
  612. <Name>NRST_STBY_D2</Name>
  613. <Description/>
  614. <BitOffset>0x19</BitOffset>
  615. <BitWidth>0x1</BitWidth>
  616. <Access>W</Access>
  617. <Values>
  618. <Val value="0x0">STANDBY mode on Domain 2 is entering with reset</Val>
  619. <Val value="0x1">STANDBY mode on Domain 2 is entering without reset</Val>
  620. </Values>
  621. </Bit>
  622. <Bit config="0,1,2,3">
  623. <Name>SWAP_BANK</Name>
  624. <Description/>
  625. <BitOffset>0x1F</BitOffset>
  626. <BitWidth>0x1</BitWidth>
  627. <Access>W</Access>
  628. <Values>
  629. <Val value="0x0">after boot loading, no swap for user sectors</Val>
  630. <Val value="0x1">after boot loading, user sectors swapped</Val>
  631. </Values>
  632. </Bit>
  633. </AssignedBits>
  634. </Field>
  635. </Category>
  636. <Category>
  637. <Name>Boot address Option Bytes</Name>
  638. <Field>
  639. <Parameters address="0x52002040" name="FBOOT7_CUR" size="0x4"/>
  640. <AssignedBits>
  641. <Bit>
  642. <Name>BOOT_CM7_ADD0</Name>
  643. <Description>Define the boot address for Cortex-M7 when BOOT0=0</Description>
  644. <BitOffset>0x0</BitOffset>
  645. <BitWidth>0x10</BitWidth>
  646. <Access>R</Access>
  647. <Equation multiplier="0x10000" offset="0x0"/>
  648. </Bit>
  649. <Bit>
  650. <Name>BOOT_CM7_ADD1</Name>
  651. <Description>Define the boot address for Cortex-M7 when BOOT0=1</Description>
  652. <BitOffset>0x10</BitOffset>
  653. <BitWidth>0x10</BitWidth>
  654. <Access>R</Access>
  655. <Equation multiplier="0x10000" offset="0x0"/>
  656. </Bit>
  657. </AssignedBits>
  658. </Field>
  659. <Field>
  660. <Parameters address="0x52002048" name="FBOOT4_CUR" size="0x4"/>
  661. <AssignedBits>
  662. <Bit config="0,1,4,5">
  663. <Name>BOOT_CM4_ADD0</Name>
  664. <Description>Define the boot address for Cortex-M4 when BOOT0=0</Description>
  665. <BitOffset>0x0</BitOffset>
  666. <BitWidth>0x10</BitWidth>
  667. <Access>R</Access>
  668. <Equation multiplier="0x10000" offset="0x0"/>
  669. </Bit>
  670. <Bit config="0,1,4,5">
  671. <Name>BOOT_CM4_ADD1</Name>
  672. <Description>Define the boot address for Cortex-M4 when BOOT0=1</Description>
  673. <BitOffset>0x10</BitOffset>
  674. <BitWidth>0x10</BitWidth>
  675. <Access>R</Access>
  676. <Equation multiplier="0x10000" offset="0x0"/>
  677. </Bit>
  678. </AssignedBits>
  679. </Field>
  680. <Field>
  681. <Parameters address="0x52002044" name="FBOOT7_PRG" size="0x4"/>
  682. <AssignedBits>
  683. <Bit>
  684. <Name>BOOT_CM7_ADD0</Name>
  685. <Description/>
  686. <BitOffset>0x0</BitOffset>
  687. <BitWidth>0x10</BitWidth>
  688. <Access>W</Access>
  689. <Equation multiplier="0x10000" offset="0x0"/>
  690. </Bit>
  691. <Bit>
  692. <Name>BOOT_CM7_ADD1</Name>
  693. <Description/>
  694. <BitOffset>0x10</BitOffset>
  695. <BitWidth>0x10</BitWidth>
  696. <Access>W</Access>
  697. <Equation multiplier="0x10000" offset="0x0"/>
  698. </Bit>
  699. </AssignedBits>
  700. </Field>
  701. <Field>
  702. <Parameters address="0x5200204C" name="FBOOT4_PRG" size="0x4"/>
  703. <AssignedBits>
  704. <Bit config="0,1,4,5">
  705. <Name>BOOT_CM4_ADD0</Name>
  706. <Description/>
  707. <BitOffset>0x0</BitOffset>
  708. <BitWidth>0x10</BitWidth>
  709. <Access>W</Access>
  710. <Equation multiplier="0x10000" offset="0x0"/>
  711. </Bit>
  712. <Bit config="0,1,4,5">
  713. <Name>BOOT_CM4_ADD1</Name>
  714. <Description/>
  715. <BitOffset>0x10</BitOffset>
  716. <BitWidth>0x10</BitWidth>
  717. <Access>W</Access>
  718. <Equation multiplier="0x10000" offset="0x0"/>
  719. </Bit>
  720. </AssignedBits>
  721. </Field>
  722. </Category>
  723. <Category>
  724. <Name>PCROP Protection</Name>
  725. <Field>
  726. <Parameters address="0x52002028" name="FPRAR_CUR_A" size="0x4"/>
  727. <AssignedBits>
  728. <Bit>
  729. <Name>PROT_AREA_START1</Name>
  730. <Description>Flash Bank 1 PCROP start address</Description>
  731. <BitOffset>0x0</BitOffset>
  732. <BitWidth>0xC</BitWidth>
  733. <Access>R</Access>
  734. <Equation multiplier="0x100" offset="0x08000000"/>
  735. </Bit>
  736. <Bit>
  737. <Name>PROT_AREA_END1</Name>
  738. <Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address.</Description>
  739. <BitOffset>0x10</BitOffset>
  740. <BitWidth>0xC</BitWidth>
  741. <Access>R</Access>
  742. <Equation multiplier="0x100" offset="0x080000FF"/>
  743. </Bit>
  744. <Bit>
  745. <Name>DMEP1</Name>
  746. <Description/>
  747. <BitOffset>0x1F</BitOffset>
  748. <BitWidth>0x1</BitWidth>
  749. <Access>R</Access>
  750. <Values>
  751. <Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  752. <Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  753. </Values>
  754. </Bit>
  755. </AssignedBits>
  756. </Field>
  757. <Field>
  758. <Parameters address="0x5200202C" name="FPRAR_PRG_A" size="0x4"/>
  759. <AssignedBits>
  760. <Bit>
  761. <Name>PROT_AREA_START1</Name>
  762. <Description>Flash Bank 1 PCROP start address</Description>
  763. <BitOffset>0x0</BitOffset>
  764. <BitWidth>0xC</BitWidth>
  765. <Access>W</Access>
  766. <Equation multiplier="0x100" offset="0x08000000"/>
  767. </Bit>
  768. <Bit>
  769. <Name>PROT_AREA_END1</Name>
  770. <Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
  771. <BitOffset>0x10</BitOffset>
  772. <BitWidth>0xC</BitWidth>
  773. <Access>W</Access>
  774. <Equation multiplier="0x100" offset="0x080000FF"/>
  775. </Bit>
  776. <Bit>
  777. <Name>DMEP1</Name>
  778. <Description/>
  779. <BitOffset>0x1F</BitOffset>
  780. <BitWidth>0x1</BitWidth>
  781. <Access>W</Access>
  782. <Values>
  783. <Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  784. <Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  785. </Values>
  786. </Bit>
  787. </AssignedBits>
  788. </Field>
  789. <Field>
  790. <Parameters address="0x52002128" name="FPRAR_CUR_B" size="0x4"/>
  791. <AssignedBits>
  792. <Bit config="0,1,2,3">
  793. <Name>PROT_AREA_START2</Name>
  794. <Description>Flash Bank 2 PCROP start address</Description>
  795. <BitOffset>0x0</BitOffset>
  796. <BitWidth>0xC</BitWidth>
  797. <Access>R</Access>
  798. <Equation multiplier="0x100" offset="0x08100000"/>
  799. </Bit>
  800. <Bit config="0,1,2,3">
  801. <Name>PROT_AREA_END2</Name>
  802. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
  803. <BitOffset>0x10</BitOffset>
  804. <BitWidth>0xC</BitWidth>
  805. <Access>R</Access>
  806. <Equation multiplier="0x100" offset="0x081000FF"/>
  807. </Bit>
  808. <Bit config="0,1,2,3">
  809. <Name>DMEP2</Name>
  810. <Description/>
  811. <BitOffset>0x1F</BitOffset>
  812. <BitWidth>0x1</BitWidth>
  813. <Access>R</Access>
  814. <Values>
  815. <Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  816. <Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  817. </Values>
  818. </Bit>
  819. </AssignedBits>
  820. </Field>
  821. <Field>
  822. <Parameters address="0x5200212C" name="FPRAR_PRG_B" size="0x4"/>
  823. <AssignedBits>
  824. <Bit config="0,1,2,3">
  825. <Name>PROT_AREA_START2</Name>
  826. <Description>Flash Bank 2 PCROP start address</Description>
  827. <BitOffset>0x0</BitOffset>
  828. <BitWidth>0xC</BitWidth>
  829. <Access>W</Access>
  830. <Equation multiplier="0x100" offset="0x08100000"/>
  831. </Bit>
  832. <Bit config="0,1,2,3">
  833. <Name>PROT_AREA_END2</Name>
  834. <Description>Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
  835. <BitOffset>0x10</BitOffset>
  836. <BitWidth>0xC</BitWidth>
  837. <Access>W</Access>
  838. <Equation multiplier="0x100" offset="0x081000FF"/>
  839. </Bit>
  840. <Bit config="0,1,2,3">
  841. <Name>DMEP2</Name>
  842. <Description/>
  843. <BitOffset>0x1F</BitOffset>
  844. <BitWidth>0x1</BitWidth>
  845. <Access>W</Access>
  846. <Values>
  847. <Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  848. <Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  849. </Values>
  850. </Bit>
  851. </AssignedBits>
  852. </Field>
  853. </Category>
  854. <Category>
  855. <Name>Secure Protection</Name>
  856. <Field>
  857. <Parameters address="0x52002030" name="FSCAR_CUR_A" size="0x4"/>
  858. <AssignedBits>
  859. <Bit config="0,2,4,6">
  860. <Name>SEC_AREA_START1</Name>
  861. <Description>Flash Bank 1 secure area start address</Description>
  862. <BitOffset>0x0</BitOffset>
  863. <BitWidth>0xC</BitWidth>
  864. <Access>R</Access>
  865. <Equation multiplier="0x100" offset="0x08000000"/>
  866. </Bit>
  867. <Bit config="0,2,4,6">
  868. <Name>SEC_AREA_END1</Name>
  869. <Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
  870. <BitOffset>0x10</BitOffset>
  871. <BitWidth>0xC</BitWidth>
  872. <Access>R</Access>
  873. <Equation multiplier="0x100" offset="0x080000FF"/>
  874. </Bit>
  875. <Bit config="0,2,4,6">
  876. <Name>DMES1</Name>
  877. <Description/>
  878. <BitOffset>0x1F</BitOffset>
  879. <BitWidth>0x1</BitWidth>
  880. <Access>R</Access>
  881. <Values>
  882. <Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  883. <Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  884. </Values>
  885. </Bit>
  886. </AssignedBits>
  887. </Field>
  888. <Field>
  889. <Parameters address="0x52002034" name="FSCAR_PRG_A" size="0x4"/>
  890. <AssignedBits>
  891. <Bit config="0,2,4,6">
  892. <Name>SEC_AREA_START1</Name>
  893. <Description>Flash Bank 1 secure area start address</Description>
  894. <BitOffset>0x0</BitOffset>
  895. <BitWidth>0xC</BitWidth>
  896. <Access>W</Access>
  897. <Equation multiplier="0x100" offset="0x08000000"/>
  898. </Bit>
  899. <Bit config="0,2,4,6">
  900. <Name>SEC_AREA_END1</Name>
  901. <Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
  902. <BitOffset>0x10</BitOffset>
  903. <BitWidth>0xC</BitWidth>
  904. <Access>W</Access>
  905. <Equation multiplier="0x100" offset="0x080000FF"/>
  906. </Bit>
  907. <Bit config="0,2,4,6">
  908. <Name>DMES1</Name>
  909. <Description/>
  910. <BitOffset>0x1F</BitOffset>
  911. <BitWidth>0x1</BitWidth>
  912. <Access>W</Access>
  913. <Values>
  914. <Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  915. <Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  916. </Values>
  917. </Bit>
  918. </AssignedBits>
  919. </Field>
  920. <Field>
  921. <Parameters address="0x52002130" name="FSCAR_CUR_B" size="0x4"/>
  922. <AssignedBits>
  923. <Bit config="0,2">
  924. <Name>SEC_AREA_START2</Name>
  925. <Description>Flash Bank 2 secure area start address</Description>
  926. <BitOffset>0x0</BitOffset>
  927. <BitWidth>0xC</BitWidth>
  928. <Access>R</Access>
  929. <Equation multiplier="0x100" offset="0x08100000"/>
  930. </Bit>
  931. <Bit config="0,2">
  932. <Name>SEC_AREA_END2</Name>
  933. <Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
  934. <BitOffset>0x10</BitOffset>
  935. <BitWidth>0xC</BitWidth>
  936. <Access>R</Access>
  937. <Equation multiplier="0x100" offset="0x081000FF"/>
  938. </Bit>
  939. <Bit config="0,2">
  940. <Name>DMES2</Name>
  941. <Description/>
  942. <BitOffset>0x1F</BitOffset>
  943. <BitWidth>0x1</BitWidth>
  944. <Access>R</Access>
  945. <Values>
  946. <Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  947. <Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  948. </Values>
  949. </Bit>
  950. </AssignedBits>
  951. </Field>
  952. <Field>
  953. <Parameters address="0x52002134" name="FSCAR_PRG_B" size="0x4"/>
  954. <AssignedBits>
  955. <Bit config="0,2">
  956. <Name>SEC_AREA_START2</Name>
  957. <Description>Flash Bank 2 secure area start address</Description>
  958. <BitOffset>0x0</BitOffset>
  959. <BitWidth>0xC</BitWidth>
  960. <Access>W</Access>
  961. <Equation multiplier="0x100" offset="0x08100000"/>
  962. </Bit>
  963. <Bit config="0,2">
  964. <Name>SEC_AREA_END2</Name>
  965. <Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
  966. <BitOffset>0x10</BitOffset>
  967. <BitWidth>0xC</BitWidth>
  968. <Access>W</Access>
  969. <Equation multiplier="0x100" offset="0x081000FF"/>
  970. </Bit>
  971. <Bit config="0,2">
  972. <Name>DMES2</Name>
  973. <Description/>
  974. <BitOffset>0x1F</BitOffset>
  975. <BitWidth>0x1</BitWidth>
  976. <Access>W</Access>
  977. <Values>
  978. <Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  979. <Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  980. </Values>
  981. </Bit>
  982. </AssignedBits>
  983. </Field>
  984. </Category>
  985. <Category>
  986. <Name>DTCM RAM Protection</Name>
  987. <Field>
  988. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  989. <AssignedBits>
  990. <Bit>
  991. <Name>ST_RAM_SIZE</Name>
  992. <Description/>
  993. <BitOffset>0x13</BitOffset>
  994. <BitWidth>0x2</BitWidth>
  995. <Access>R</Access>
  996. <Values>
  997. <Val value="0x0">2 KB</Val>
  998. <Val value="0x1">4 KB</Val>
  999. <Val value="0x2">8 KB</Val>
  1000. <Val value="0x3">16 KB</Val>
  1001. </Values>
  1002. </Bit>
  1003. </AssignedBits>
  1004. </Field>
  1005. <Field>
  1006. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  1007. <AssignedBits>
  1008. <Bit>
  1009. <Name>ST_RAM_SIZE</Name>
  1010. <Description/>
  1011. <BitOffset>0x13</BitOffset>
  1012. <BitWidth>0x2</BitWidth>
  1013. <Access>W</Access>
  1014. <Values>
  1015. <Val value="0x0">2 KB</Val>
  1016. <Val value="0x1">4 KB</Val>
  1017. <Val value="0x2">8 KB</Val>
  1018. <Val value="0x3">16 KB</Val>
  1019. </Values>
  1020. </Bit>
  1021. </AssignedBits>
  1022. </Field>
  1023. </Category>
  1024. <Category>
  1025. <Name>Write Protection</Name>
  1026. <Field>
  1027. <Parameters address="0x52002038" name="FWPSN_CUR_A" size="0x4"/>
  1028. <AssignedBits>
  1029. <Bit config="0,1,2,3">
  1030. <Name>nWRP0</Name>
  1031. <Description/>
  1032. <BitOffset>0x0</BitOffset>
  1033. <BitWidth>0x8</BitWidth>
  1034. <Access>R</Access>
  1035. <Values ByBit="true">
  1036. <Val value="0x0">Write protection active on this sector</Val>
  1037. <Val value="0x1">Write protection not active on this sector</Val>
  1038. </Values>
  1039. </Bit>
  1040. <Bit config="4,5,6,7">
  1041. <Name>nWRP0</Name>
  1042. <Description/>
  1043. <BitOffset>0x0</BitOffset>
  1044. <BitWidth>0x1</BitWidth>
  1045. <Access>R</Access>
  1046. <Values ByBit="true">
  1047. <Val value="0x0">Write protection active on this sector</Val>
  1048. <Val value="0x1">Write protection not active on this sector</Val>
  1049. </Values>
  1050. </Bit>
  1051. </AssignedBits>
  1052. </Field>
  1053. <Field>
  1054. <Parameters address="0x5200203C" name="FWPSN_PRG_A" size="0x4"/>
  1055. <AssignedBits>
  1056. <Bit config="0,1,2,3">
  1057. <Name>nWRP0</Name>
  1058. <Description/>
  1059. <BitOffset>0x0</BitOffset>
  1060. <BitWidth>0x8</BitWidth>
  1061. <Access>W</Access>
  1062. <Values ByBit="true">
  1063. <Val value="0x0">Write protection active on this sector</Val>
  1064. <Val value="0x1">Write protection not active on this sector</Val>
  1065. </Values>
  1066. </Bit>
  1067. <Bit config="4,5,6,7">
  1068. <Name>nWRP0</Name>
  1069. <Description/>
  1070. <BitOffset>0x0</BitOffset>
  1071. <BitWidth>0x1</BitWidth>
  1072. <Access>W</Access>
  1073. <Values ByBit="true">
  1074. <Val value="0x0">Write protection active on this sector</Val>
  1075. <Val value="0x1">Write protection not active on this sector</Val>
  1076. </Values>
  1077. </Bit>
  1078. </AssignedBits>
  1079. </Field>
  1080. <Field>
  1081. <Parameters address="0x52002138" name="FWPSN_CUR_B" size="0x4"/>
  1082. <AssignedBits>
  1083. <Bit config="0,1,2,3">
  1084. <Name>nWRP8</Name>
  1085. <Description/>
  1086. <BitOffset>0x0</BitOffset>
  1087. <BitWidth>0x8</BitWidth>
  1088. <Access>R</Access>
  1089. <Values ByBit="true">
  1090. <Val value="0x0">Write protection active on this sector</Val>
  1091. <Val value="0x1">Write protection not active on this sector</Val>
  1092. </Values>
  1093. </Bit>
  1094. </AssignedBits>
  1095. </Field>
  1096. <Field>
  1097. <Parameters address="0x5200213C" name="FWPSN_PRG_B" size="0x4"/>
  1098. <AssignedBits>
  1099. <Bit config="0,1,2,3">
  1100. <Name>nWRP8</Name>
  1101. <Description/>
  1102. <BitOffset>0x0</BitOffset>
  1103. <BitWidth>0x8</BitWidth>
  1104. <Access>W</Access>
  1105. <Values ByBit="true">
  1106. <Val value="0x0">Write protection active on this sector</Val>
  1107. <Val value="0x1">Write protection not active on this sector</Val>
  1108. </Values>
  1109. </Bit>
  1110. </AssignedBits>
  1111. </Field>
  1112. </Category>
  1113. </Bank>
  1114. </Peripheral>
  1115. </Peripherals>
  1116. </Device>
  1117. </Root>