STM32_Prog_DB_0x470.xml 52 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352
  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x470</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M4</CPU>
  8. <Name>STM32L4Rxxx/STM32L4Sxxx</Name>
  9. <Series>STM32L4</Series>
  10. <Description>ARM 32-bit Cortex-M4 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0">
  15. <flashSize> <!-- 2M --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x800"/> </flashSize>
  16. <DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
  17. </Configuration>
  18. <Configuration number="0x1">
  19. <flashSize> <!-- 2M --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x800"/> </flashSize>
  20. <DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
  21. </Configuration>
  22. <Configuration number="0x2">
  23. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x400"/> </flashSize>
  24. <DB1M reference="0x0"> <ReadRegister address="0x40022020" mask="0x200000" value="0x0"/> </DB1M>
  25. <DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
  26. </Configuration>
  27. <Configuration number="0x3">
  28. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x400"/> </flashSize>
  29. <DB1M reference="0x1"> <ReadRegister address="0x40022020" mask="0x200000" value="0x200000"/> </DB1M>
  30. <DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
  31. </Configuration>
  32. <Configuration number="0x4">
  33. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x400"/> </flashSize>
  34. <DB1M reference="0x1"> <ReadRegister address="0x40022020" mask="0x200000" value="0x200000"/> </DB1M>
  35. <DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
  36. </Configuration>
  37. <Configuration number="0x5">
  38. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x400"/> </flashSize>
  39. <DB1M reference="0x0"> <ReadRegister address="0x40022020" mask="0x200000" value="0x0"/> </DB1M>
  40. <DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
  41. </Configuration>
  42. <Configuration number="0x6">
  43. <flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x400"/> </flashSize>
  44. <DB1M reference="0x0"> <ReadRegister address="0x40022020" mask="0x200000" value="0x0"/> </DB1M>
  45. <DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
  46. </Configuration>
  47. <Configuration number="0x7">
  48. <flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x400"/> </flashSize>
  49. <DB1M reference="0x0"> <ReadRegister address="0x40022020" mask="0x200000" value="0x0"/> </DB1M>
  50. <DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
  51. </Configuration>
  52. <Configuration number="0x8">
  53. <flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x400"/> </flashSize>
  54. <DB1M reference="0x1"> <ReadRegister address="0x40022020" mask="0x200000" value="0x200000"/> </DB1M>
  55. <DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
  56. </Configuration>
  57. <Configuration number="0x9">
  58. <flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x400"/> </flashSize>
  59. <DB1M reference="0x1"> <ReadRegister address="0x40022020" mask="0x200000" value="0x200000"/> </DB1M>
  60. <DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
  61. </Configuration>
  62. <Configuration number="0xA">
  63. <dummy> <ReadRegister address="0x20000000" mask="0" value="0"/> </dummy>
  64. </Configuration>
  65. </Interface>
  66. <!-- Bootloader Interface -->
  67. <Interface name="Bootloader">
  68. <Configuration number="0x0">
  69. <DBANK reference="0x0"> <ReadRegister address="0x1FF00000" mask="0x400000" value="0x0"/> </DBANK>
  70. </Configuration>
  71. <Configuration number="0x1">
  72. <DBANK reference="0x1"> <ReadRegister address="0x1FF00000" mask="0x400000" value="0x400000"/> </DBANK>
  73. </Configuration>
  74. <Configuration number="0xA">
  75. <dummy> <ReadRegister address="0x1FF00000" mask="0" value="0"/> </dummy>
  76. </Configuration>
  77. </Interface>
  78. </Configurations>
  79. <!-- Peripherals -->
  80. <Peripherals>
  81. <!-- Embedded SRAM -->
  82. <Peripheral>
  83. <Name>Embedded SRAM</Name>
  84. <Type>Storage</Type>
  85. <Description/>
  86. <ErasedValue>0x00</ErasedValue>
  87. <Access>RWE</Access>
  88. <!-- 96 KB -->
  89. <Configuration>
  90. <Parameters address="0x20000000" name="SRAM" size="0x30000"/>
  91. <Description/>
  92. <Organization>Single</Organization>
  93. <Bank name="Bank 1">
  94. <Field>
  95. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x30000"/>
  96. </Field>
  97. </Bank>
  98. </Configuration>
  99. </Peripheral>
  100. <!-- Embedded Flash -->
  101. <Peripheral>
  102. <Name>Embedded Flash</Name>
  103. <Type>Storage</Type>
  104. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  105. <ErasedValue>0xFF</ErasedValue>
  106. <Access>RWE</Access>
  107. <FlashSize address="0x1FFF75E0" default="0x200000"/>
  108. <DBGMCU_CR address="0xE0042004" mask="0x007"/>
  109. <DBGMCU_APB1_FZ address="0xE0042008" mask="0x1800"/>
  110. <Configuration config="0,2,3,6,9"> <!-- 2MB Single Bank -->
  111. <Parameters address="0x08000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  112. <Description/>
  113. <Organization>Single</Organization>
  114. <Allignement>0x8</Allignement>
  115. <Bank name="Bank 1">
  116. <Field>
  117. <Parameters address="0x08000000" name="sector0" occurence="0x100" size="0x2000"/>
  118. </Field>
  119. </Bank>
  120. </Configuration>
  121. <Configuration config="1,4,5,7,8"> <!-- 2MB dual Bank -->
  122. <Parameters address="0x08000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  123. <Description/>
  124. <Organization>Dual</Organization>
  125. <Allignement>0x8</Allignement>
  126. <Bank name="Bank 1">
  127. <Field>
  128. <Parameters address="0x08000000" name="sector0" occurence="0x100" size="0x1000"/>
  129. </Field>
  130. </Bank>
  131. <Bank name="Bank 2">
  132. <Field>
  133. <Parameters address="0x08100000" name="sector256" occurence="0x100" size="0x1000"/>
  134. </Field>
  135. </Bank>
  136. </Configuration>
  137. <Configuration config="2"> <!-- 2MB dual Bank -->
  138. <Parameters address="0x08000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  139. <Description/>
  140. <Organization>Dual</Organization>
  141. <Allignement>0x8</Allignement>
  142. <Bank name="Bank 1">
  143. <Field>
  144. <Parameters address="0x08000000" name="sector0" occurence="0x100" size="0x2000"/>
  145. </Field>
  146. </Bank>
  147. <Bank name="Bank 2">
  148. <Field>
  149. <Parameters address="0x08100000" name="sector256" occurence="0x100" size="0x2000"/>
  150. </Field>
  151. </Bank>
  152. </Configuration>
  153. </Peripheral>
  154. <!-- OTP -->
  155. <Peripheral>
  156. <Name>OTP</Name>
  157. <Type>Storage</Type>
  158. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  159. <ErasedValue>0xFF</ErasedValue>
  160. <Access>RW</Access>
  161. <!-- 1 KBytes single bank -->
  162. <Configuration>
  163. <Parameters address="0x1FFF7000" name=" 1 KBytes Data OTP" size="0x400"/>
  164. <Description/>
  165. <Organization>Single</Organization>
  166. <Allignement>0x4</Allignement>
  167. <Bank name="OTP">
  168. <Field>
  169. <Parameters address="0x1FFF7000" name="OTP" occurence="0x1" size="0x400"/>
  170. </Field>
  171. </Bank>
  172. </Configuration>
  173. </Peripheral>
  174. <!-- Mirror Option Bytes -->
  175. <Peripheral>
  176. <Name>MirrorOptionBytes</Name>
  177. <Type>Storage</Type>
  178. <Description>Mirror Option Bytes contains the extra area.</Description>
  179. <ErasedValue>0xFF</ErasedValue>
  180. <Access>RW</Access>
  181. <!-- 64 Bytes Dual bank -->
  182. <Configuration>
  183. <Parameters address="0x1FFF7800" name=" 64 Bytes Data MirrorOptionBytes" size="0x40"/>
  184. <Description/>
  185. <Organization>Dual</Organization>
  186. <Allignement>0x4</Allignement>
  187. <Bank name="Bank 1">
  188. <Field>
  189. <Parameters address="0x1FF00000" name="Bank1" occurence="0x1" size="0x24"/>
  190. </Field>
  191. </Bank>
  192. <Bank name="Bank 2">
  193. <Field>
  194. <Parameters address="0x1FF01008" name="Bank2" occurence="0x1" size="0x1C"/>
  195. </Field>
  196. </Bank>
  197. </Configuration>
  198. </Peripheral>
  199. <!-- Option Bytes -->
  200. <Peripheral>
  201. <Name>Option Bytes</Name>
  202. <Type>Configuration</Type>
  203. <Description/>
  204. <Access>RW</Access>
  205. <Bank interface="JTAG_SWD">
  206. <Parameters address="0x40022020" name="Bank 1" size="0x14"/>
  207. <Category>
  208. <Name>Read Out Protection</Name>
  209. <Field>
  210. <Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
  211. <AssignedBits>
  212. <Bit>
  213. <Name>RDP</Name>
  214. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  215. <BitOffset>0x0</BitOffset>
  216. <BitWidth>0x8</BitWidth>
  217. <Access>RW</Access>
  218. <Values>
  219. <Val value="0xAA">Level 0, no protection</Val>
  220. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  221. <Val value="0xCC">Level 2, chip protection</Val>
  222. </Values>
  223. </Bit>
  224. </AssignedBits>
  225. </Field>
  226. </Category>
  227. <Category>
  228. <Name>BOR Level</Name>
  229. <Field>
  230. <Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
  231. <AssignedBits>
  232. <Bit>
  233. <Name>BOR_LEV</Name>
  234. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  235. <BitOffset>0x8</BitOffset>
  236. <BitWidth>0x3</BitWidth>
  237. <Access>RW</Access>
  238. <Values>
  239. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  240. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  241. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  242. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  243. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  244. </Values>
  245. </Bit>
  246. </AssignedBits>
  247. </Field>
  248. </Category>
  249. <Category>
  250. <Name>User Configuration</Name>
  251. <Field>
  252. <Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
  253. <AssignedBits>
  254. <Bit>
  255. <Name>nRST_STOP</Name>
  256. <Description/>
  257. <BitOffset>0xC</BitOffset>
  258. <BitWidth>0x1</BitWidth>
  259. <Access>RW</Access>
  260. <Values>
  261. <Val value="0x0">Reset generated when entering Stop mode</Val>
  262. <Val value="0x1">No reset generated when entering Stop mode</Val>
  263. </Values>
  264. </Bit>
  265. <Bit>
  266. <Name>nRST_STDBY</Name>
  267. <Description/>
  268. <BitOffset>0xD</BitOffset>
  269. <BitWidth>0x1</BitWidth>
  270. <Access>RW</Access>
  271. <Values>
  272. <Val value="0x0">Reset generated when entering Standby mode</Val>
  273. <Val value="0x1">No reset generated when entering Standby mode</Val>
  274. </Values>
  275. </Bit>
  276. <Bit>
  277. <Name>nRST_SHDW</Name>
  278. <Description/>
  279. <BitOffset>0xE</BitOffset>
  280. <BitWidth>0x1</BitWidth>
  281. <Access>RW</Access>
  282. <Values>
  283. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  284. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  285. </Values>
  286. </Bit>
  287. <Bit>
  288. <Name>IWDG_SW</Name>
  289. <Description/>
  290. <BitOffset>0x10</BitOffset>
  291. <BitWidth>0x1</BitWidth>
  292. <Access>RW</Access>
  293. <Values>
  294. <Val value="0x0">Hardware independant watchdog</Val>
  295. <Val value="0x1">Software independant watchdog</Val>
  296. </Values>
  297. </Bit>
  298. <Bit>
  299. <Name>IWDG_STOP</Name>
  300. <Description/>
  301. <BitOffset>0x11</BitOffset>
  302. <BitWidth>0x1</BitWidth>
  303. <Access>RW</Access>
  304. <Values>
  305. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  306. <Val value="0x1">IWDG counter active in stop mode</Val>
  307. </Values>
  308. </Bit>
  309. <Bit>
  310. <Name>IWDG_STDBY</Name>
  311. <Description/>
  312. <BitOffset>0x12</BitOffset>
  313. <BitWidth>0x1</BitWidth>
  314. <Access>RW</Access>
  315. <Values>
  316. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  317. <Val value="0x1">IWDG counter active in standby mode</Val>
  318. </Values>
  319. </Bit>
  320. <Bit>
  321. <Name>WWDG_SW</Name>
  322. <Description/>
  323. <BitOffset>0x13</BitOffset>
  324. <BitWidth>0x1</BitWidth>
  325. <Access>RW</Access>
  326. <Values>
  327. <Val value="0x0">Hardware window watchdog</Val>
  328. <Val value="0x1">Software window watchdog</Val>
  329. </Values>
  330. </Bit>
  331. <Bit>
  332. <Name>BFB2</Name>
  333. <Description/>
  334. <BitOffset>0x14</BitOffset>
  335. <BitWidth>0x1</BitWidth>
  336. <Access>RW</Access>
  337. <Values>
  338. <Val value="0x0">Dual-bank boot disable</Val>
  339. <Val value="0x1">Dual-bank boot enable</Val>
  340. </Values>
  341. </Bit>
  342. <Bit config="2,3,4,5,6,7,8,9,10">
  343. <Name>DB1M</Name>
  344. <Description>Dual-Bank on 1 MB Flash or 512 KB Flash memory devices</Description>
  345. <BitOffset>0x15</BitOffset>
  346. <BitWidth>0x1</BitWidth>
  347. <Access>RW</Access>
  348. <Values>
  349. <Val value="0x0">1 MB or 512 Kb single Flash: contiguous address in bank1</Val>
  350. <Val value="0x1">1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb.</Val>
  351. </Values>
  352. </Bit>
  353. <Bit>
  354. <Name>DBANK</Name>
  355. <Description>This bit can only be written when PCROPA/B is disabled</Description>
  356. <BitOffset>0x16</BitOffset>
  357. <BitWidth>0x1</BitWidth>
  358. <Access>RW</Access>
  359. <Values>
  360. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  361. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  362. </Values>
  363. </Bit>
  364. <Bit>
  365. <Name>nBOOT1</Name>
  366. <Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory.</Description>
  367. <BitOffset>0x17</BitOffset>
  368. <BitWidth>0x1</BitWidth>
  369. <Access>RW</Access>
  370. <Values>
  371. <Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
  372. <Val value="0x1">Boot from system memory when BOOT0=1</Val>
  373. </Values>
  374. </Bit>
  375. <Bit>
  376. <Name>SRAM2_PE</Name>
  377. <Description>SRAM2 parity check enable</Description>
  378. <BitOffset>0x18</BitOffset>
  379. <BitWidth>0x1</BitWidth>
  380. <Access>RW</Access>
  381. <Values>
  382. <Val value="0x0">SRAM2 parity check enable</Val>
  383. <Val value="0x1">SRAM2 parity check disable</Val>
  384. </Values>
  385. </Bit>
  386. <Bit>
  387. <Name>SRAM2_RST</Name>
  388. <Description>SRAM2 Erase when system reset</Description>
  389. <BitOffset>0x19</BitOffset>
  390. <BitWidth>0x1</BitWidth>
  391. <Access>RW</Access>
  392. <Values>
  393. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  394. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  395. </Values>
  396. </Bit>
  397. <Bit>
  398. <Name>nSWBOOT0</Name>
  399. <Description>Software BOOT0</Description>
  400. <BitOffset>0x1A</BitOffset>
  401. <BitWidth>0x1</BitWidth>
  402. <Access>RW</Access>
  403. <Values>
  404. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  405. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  406. </Values>
  407. </Bit>
  408. <Bit>
  409. <Name>nBOOT0</Name>
  410. <Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
  411. <BitOffset>0x1B</BitOffset>
  412. <BitWidth>0x1</BitWidth>
  413. <Access>RW</Access>
  414. <Values>
  415. <Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
  416. <Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
  417. </Values>
  418. </Bit>
  419. </AssignedBits>
  420. </Field>
  421. </Category>
  422. <Category>
  423. <Name>PCROP Protection (Bank 1)</Name>
  424. <Field>
  425. <Parameters address="0x40022024" name="FLASH_PCROP1SR" size="0x4"/>
  426. <AssignedBits>
  427. <Bit config="0,2,3,6,9,10">
  428. <Name>PCROP1_STRT</Name>
  429. <Description>Flash Bank 1 PCROP start address</Description>
  430. <BitOffset>0x0</BitOffset>
  431. <BitWidth>0x11</BitWidth>
  432. <Access>RW</Access>
  433. <Equation multiplier="0x16" offset="0x08000000"/>
  434. </Bit>
  435. <Bit config="1,4,5,7,8">
  436. <Name>PCROP1_STRT</Name>
  437. <Description>Flash Bank 1 PCROP start address</Description>
  438. <BitOffset>0x0</BitOffset>
  439. <BitWidth>0x11</BitWidth>
  440. <Access>RW</Access>
  441. <Equation multiplier="0x8" offset="0x08000000"/>
  442. </Bit>
  443. </AssignedBits>
  444. </Field>
  445. <Field>
  446. <Parameters address="0x40022028" name="FLASH_PCROP1ER" size="0x4"/>
  447. <AssignedBits>
  448. <Bit config="0,2,3,6,9,10">
  449. <Name>PCROP1_END</Name>
  450. <Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  451. <BitOffset>0x0</BitOffset>
  452. <BitWidth>0x11</BitWidth>
  453. <Access>RW</Access>
  454. <Equation multiplier="0x16" offset="0x08000000"/>
  455. </Bit>
  456. <Bit config="1,4,5,7,8">
  457. <Name>PCROP1_END</Name>
  458. <Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  459. <BitOffset>0x0</BitOffset>
  460. <BitWidth>0x11</BitWidth>
  461. <Access>RW</Access>
  462. <Equation multiplier="0x8" offset="0x08000000"/>
  463. </Bit>
  464. <Bit>
  465. <Name>PCROP_RDP</Name>
  466. <Description/>
  467. <BitOffset>0x1F</BitOffset>
  468. <BitWidth>0x1</BitWidth>
  469. <Access>RW</Access>
  470. <Values>
  471. <Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
  472. <Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
  473. </Values>
  474. </Bit>
  475. </AssignedBits>
  476. </Field>
  477. </Category>
  478. <Category>
  479. <Name>Write Protection (Bank 1)</Name>
  480. <Field>
  481. <Parameters address="0x4002202C" name="FLASH_WRP1AR" size="0x4"/>
  482. <AssignedBits>
  483. <Bit config="0,2,3,6,9,10">
  484. <Name>WRP1A_STRT</Name>
  485. <Description>The address of the first page of the Bank 1 WRP first area</Description>
  486. <BitOffset>0x0</BitOffset>
  487. <BitWidth>0x8</BitWidth>
  488. <Access>RW</Access>
  489. <Equation multiplier="0x2000" offset="0x08000000"/>
  490. </Bit>
  491. <Bit config="1,4,5,7,8">
  492. <Name>WRP1A_STRT</Name>
  493. <Description>The address of the first page of the Bank 1 WRP first area</Description>
  494. <BitOffset>0x0</BitOffset>
  495. <BitWidth>0x8</BitWidth>
  496. <Access>RW</Access>
  497. <Equation multiplier="0x1000" offset="0x08000000"/>
  498. </Bit>
  499. <Bit config="0,2,3,6,9,10">
  500. <Name>WRP1A_END</Name>
  501. <Description>The address of the last page of the Bank 1 WRP first area</Description>
  502. <BitOffset>0x10</BitOffset>
  503. <BitWidth>0x8</BitWidth>
  504. <Access>RW</Access>
  505. <Equation multiplier="0x2000" offset="0x08000000"/>
  506. </Bit>
  507. <Bit config="1,4,5,7,8">
  508. <Name>WRP1A_END</Name>
  509. <Description>The address of the last page of the Bank 1 WRP first area</Description>
  510. <BitOffset>0x10</BitOffset>
  511. <BitWidth>0x8</BitWidth>
  512. <Access>RW</Access>
  513. <Equation multiplier="0x1000" offset="0x08000000"/>
  514. </Bit>
  515. </AssignedBits>
  516. </Field>
  517. <Field>
  518. <Parameters address="0x40022030" name="FLASH_WRP1BR" size="0x4"/>
  519. <AssignedBits>
  520. <Bit config="0,2,3,6,9,10">
  521. <Name>WRP1B_STRT</Name>
  522. <Description>The address of the first page of the Bank 1 WRP second area</Description>
  523. <BitOffset>0x0</BitOffset>
  524. <BitWidth>0x8</BitWidth>
  525. <Access>RW</Access>
  526. <Equation multiplier="0x2000" offset="0x08000000"/>
  527. </Bit>
  528. <Bit config="1,4,5,7,8">
  529. <Name>WRP1B_STRT</Name>
  530. <Description>The address of the last page of the Bank 1 WRP second area</Description>
  531. <BitOffset>0x0</BitOffset>
  532. <BitWidth>0x8</BitWidth>
  533. <Access>RW</Access>
  534. <Equation multiplier="0x1000" offset="0x08000000"/>
  535. </Bit>
  536. <Bit config="0,2,3,6,9,10">
  537. <Name>WRP1B_END</Name>
  538. <Description>The address of the last page of the Bank 1 WRP second area</Description>
  539. <BitOffset>0x10</BitOffset>
  540. <BitWidth>0x8</BitWidth>
  541. <Access>RW</Access>
  542. <Equation multiplier="0x2000" offset="0x08000000"/>
  543. </Bit>
  544. <Bit config="1,4,5,7,8">
  545. <Name>WRP1B_END</Name>
  546. <Description>The address of the last page of the Bank 1 WRP second area</Description>
  547. <BitOffset>0x10</BitOffset>
  548. <BitWidth>0x8</BitWidth>
  549. <Access>RW</Access>
  550. <Equation multiplier="0x1000" offset="0x08000000"/>
  551. </Bit>
  552. </AssignedBits>
  553. </Field>
  554. </Category>
  555. </Bank>
  556. <Bank interface="JTAG_SWD">
  557. <Parameters address="0x40022044" name="Bank 2" size="0x10"/>
  558. <Category>
  559. <Name>PCROP Protection (Bank 2)</Name>
  560. <Field>
  561. <Parameters address="0x40022044" name="FLASH_PCROP2SR" size="0x4"/>
  562. <AssignedBits>
  563. <Bit config="0,10"> <!-- 2M whith offset 1M></!-->
  564. <Name>PCROP2_STRT</Name>
  565. <Description>Flash Bank 2 PCROP start address</Description>
  566. <BitOffset>0x0</BitOffset>
  567. <BitWidth>0x11</BitWidth>
  568. <Access>RW</Access>
  569. <Equation multiplier="0x16" offset="0x08100000"/>
  570. </Bit>
  571. <Bit config="2,3"> <!-- 1M whith offset 512K></!-->
  572. <Name>PCROP2_STRT</Name>
  573. <Description>Flash Bank 2 PCROP start address</Description>
  574. <BitOffset>0x0</BitOffset>
  575. <BitWidth>0x11</BitWidth>
  576. <Access>RW</Access>
  577. <Equation multiplier="0x16" offset="0x08080000"/>
  578. </Bit>
  579. <Bit config="6,9"> <!-- 512K whith offset 256K></!-->
  580. <Name>PCROP2_STRT</Name>
  581. <Description>Flash Bank 2 PCROP start address</Description>
  582. <BitOffset>0x0</BitOffset>
  583. <BitWidth>0x11</BitWidth>
  584. <Access>RW</Access>
  585. <Equation multiplier="0x16" offset="0x08040000"/>
  586. </Bit>
  587. <Bit config="1">
  588. <Name>PCROP2_STRT</Name>
  589. <Description>Flash Bank 2 PCROP start address</Description>
  590. <BitOffset>0x0</BitOffset>
  591. <BitWidth>0x11</BitWidth>
  592. <Access>RW</Access>
  593. <Equation multiplier="0x8" offset="0x08100000"/>
  594. </Bit>
  595. <Bit config="4,5">
  596. <Name>PCROP2_STRT</Name>
  597. <Description>Flash Bank 2 PCROP start address</Description>
  598. <BitOffset>0x0</BitOffset>
  599. <BitWidth>0x11</BitWidth>
  600. <Access>RW</Access>
  601. <Equation multiplier="0x8" offset="0x08080000"/>
  602. </Bit>
  603. <Bit config="7,8">
  604. <Name>PCROP2_STRT</Name>
  605. <Description>Flash Bank 2 PCROP start address</Description>
  606. <BitOffset>0x0</BitOffset>
  607. <BitWidth>0x11</BitWidth>
  608. <Access>RW</Access>
  609. <Equation multiplier="0x8" offset="0x08040000"/>
  610. </Bit>
  611. </AssignedBits>
  612. </Field>
  613. <Field>
  614. <Parameters address="0x40022048" name="FLASH_PCROP2ER" size="0x4"/>
  615. <AssignedBits>
  616. <Bit config="0,10">
  617. <Name>PCROP2_END</Name>
  618. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  619. <BitOffset>0x0</BitOffset>
  620. <BitWidth>0x11</BitWidth>
  621. <Access>RW</Access>
  622. <Equation multiplier="0x16" offset="0x08100000"/>
  623. </Bit>
  624. <Bit config="2,3">
  625. <Name>PCROP2_END</Name>
  626. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  627. <BitOffset>0x0</BitOffset>
  628. <BitWidth>0x11</BitWidth>
  629. <Access>RW</Access>
  630. <Equation multiplier="0x16" offset="0x08080000"/>
  631. </Bit>
  632. <Bit config="6,9">
  633. <Name>PCROP2_END</Name>
  634. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  635. <BitOffset>0x0</BitOffset>
  636. <BitWidth>0x11</BitWidth>
  637. <Access>RW</Access>
  638. <Equation multiplier="0x16" offset="0x08040000"/>
  639. </Bit>
  640. <Bit config="1">
  641. <Name>PCROP2_END</Name>
  642. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  643. <BitOffset>0x0</BitOffset>
  644. <BitWidth>0x11</BitWidth>
  645. <Access>RW</Access>
  646. <Equation multiplier="0x8" offset="0x08100000"/>
  647. </Bit>
  648. <Bit config="4,5">
  649. <Name>PCROP2_END</Name>
  650. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  651. <BitOffset>0x0</BitOffset>
  652. <BitWidth>0x11</BitWidth>
  653. <Access>RW</Access>
  654. <Equation multiplier="0x8" offset="0x08080000"/>
  655. </Bit>
  656. <Bit config="7,8">
  657. <Name>PCROP2_END</Name>
  658. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  659. <BitOffset>0x0</BitOffset>
  660. <BitWidth>0x11</BitWidth>
  661. <Access>RW</Access>
  662. <Equation multiplier="0x8" offset="0x08040000"/>
  663. </Bit>
  664. </AssignedBits>
  665. </Field>
  666. </Category>
  667. <Category>
  668. <Name>Write Protection (Bank 2)</Name>
  669. <Field>
  670. <Parameters address="0x4002204C" name="FLASH_WRP2AR" size="0x4"/>
  671. <AssignedBits>
  672. <Bit config="0,10">
  673. <Name>WRP2A_STRT</Name>
  674. <Description>The address of first page of the Bank 2 WRP first area</Description>
  675. <BitOffset>0x0</BitOffset>
  676. <BitWidth>0x8</BitWidth>
  677. <Access>RW</Access>
  678. <Equation multiplier="0x2000" offset="0x08100000"/>
  679. </Bit>
  680. <Bit config="2,3">
  681. <Name>WRP2A_STRT</Name>
  682. <Description>The address of first page of the Bank 2 WRP first area</Description>
  683. <BitOffset>0x0</BitOffset>
  684. <BitWidth>0x8</BitWidth>
  685. <Access>RW</Access>
  686. <Equation multiplier="0x2000" offset="0x08080000"/>
  687. </Bit>
  688. <Bit config="6,9">
  689. <Name>WRP2A_STRT</Name>
  690. <Description>The address of first page of the Bank 2 WRP first area</Description>
  691. <BitOffset>0x0</BitOffset>
  692. <BitWidth>0x8</BitWidth>
  693. <Access>RW</Access>
  694. <Equation multiplier="0x2000" offset="0x08040000"/>
  695. </Bit>
  696. <Bit config="1">
  697. <Name>WRP2A_STRT</Name>
  698. <Description>The address of first page of the Bank 2 WRP first area</Description>
  699. <BitOffset>0x0</BitOffset>
  700. <BitWidth>0x8</BitWidth>
  701. <Access>RW</Access>
  702. <Equation multiplier="0x1000" offset="0x08100000"/>
  703. </Bit>
  704. <Bit config="4,5">
  705. <Name>WRP2A_STRT</Name>
  706. <Description>The address of first page of the Bank 2 WRP first area</Description>
  707. <BitOffset>0x0</BitOffset>
  708. <BitWidth>0x8</BitWidth>
  709. <Access>RW</Access>
  710. <Equation multiplier="0x1000" offset="0x08080000"/>
  711. </Bit>
  712. <Bit config="6,9">
  713. <Name>WRP2A_STRT</Name>
  714. <Description>The address of first page of the Bank 2 WRP first area</Description>
  715. <BitOffset>0x0</BitOffset>
  716. <BitWidth>0x8</BitWidth>
  717. <Access>RW</Access>
  718. <Equation multiplier="0x1000" offset="0x08040000"/>
  719. </Bit>
  720. <Bit config="0,10">
  721. <Name>WRP2A_END</Name>
  722. <Description>The address of last page of the Bank 2 WRP first area</Description>
  723. <BitOffset>0x10</BitOffset>
  724. <BitWidth>0x8</BitWidth>
  725. <Access>RW</Access>
  726. <Equation multiplier="0x2000" offset="0x08100000"/>
  727. </Bit>
  728. <Bit config="2,3">
  729. <Name>WRP2A_END</Name>
  730. <Description>The address of last page of the Bank 2 WRP first area</Description>
  731. <BitOffset>0x10</BitOffset>
  732. <BitWidth>0x8</BitWidth>
  733. <Access>RW</Access>
  734. <Equation multiplier="0x2000" offset="0x08080000"/>
  735. </Bit>
  736. <Bit config="6,9">
  737. <Name>WRP2A_END</Name>
  738. <Description>The address of last page of the Bank 2 WRP first area</Description>
  739. <BitOffset>0x10</BitOffset>
  740. <BitWidth>0x8</BitWidth>
  741. <Access>RW</Access>
  742. <Equation multiplier="0x2000" offset="0x08040000"/>
  743. </Bit>
  744. <Bit config="1">
  745. <Name>WRP2A_END</Name>
  746. <Description>The address of last page of the Bank 2 WRP first area</Description>
  747. <BitOffset>0x10</BitOffset>
  748. <BitWidth>0x8</BitWidth>
  749. <Access>RW</Access>
  750. <Equation multiplier="0x1000" offset="0x08100000"/>
  751. </Bit>
  752. <Bit config="4,5">
  753. <Name>WRP2A_END</Name>
  754. <Description>The address of last page of the Bank 2 WRP first area</Description>
  755. <BitOffset>0x10</BitOffset>
  756. <BitWidth>0x8</BitWidth>
  757. <Access>RW</Access>
  758. <Equation multiplier="0x1000" offset="0x08080000"/>
  759. </Bit>
  760. <Bit config="7,8">
  761. <Name>WRP2A_END</Name>
  762. <Description>The address of last page of the Bank 2 WRP first area</Description>
  763. <BitOffset>0x10</BitOffset>
  764. <BitWidth>0x8</BitWidth>
  765. <Access>RW</Access>
  766. <Equation multiplier="0x1000" offset="0x08040000"/>
  767. </Bit>
  768. </AssignedBits>
  769. </Field>
  770. <Field>
  771. <Parameters address="0x40022050" name="FLASH_WRP2BR" size="0x4"/>
  772. <AssignedBits>
  773. <Bit config="0,10">
  774. <Name>WRP2B_STRT</Name>
  775. <Description>The address of first page of the Bank 2 WRP second area</Description>
  776. <BitOffset>0x0</BitOffset>
  777. <BitWidth>0x8</BitWidth>
  778. <Access>RW</Access>
  779. <Equation multiplier="0x2000" offset="0x08100000"/>
  780. </Bit>
  781. <Bit config="2,3">
  782. <Name>WRP2B_STRT</Name>
  783. <Description>The address of first page of the Bank 2 WRP second area</Description>
  784. <BitOffset>0x0</BitOffset>
  785. <BitWidth>0x8</BitWidth>
  786. <Access>RW</Access>
  787. <Equation multiplier="0x2000" offset="0x08080000"/>
  788. </Bit>
  789. <Bit config="6,9">
  790. <Name>WRP2B_STRT</Name>
  791. <Description>The address of first page of the Bank 2 WRP second area</Description>
  792. <BitOffset>0x0</BitOffset>
  793. <BitWidth>0x8</BitWidth>
  794. <Access>RW</Access>
  795. <Equation multiplier="0x2000" offset="0x08040000"/>
  796. </Bit>
  797. <Bit config="1">
  798. <Name>WRP2B_STRT</Name>
  799. <Description>The address of first page of the Bank 2 WRP second area</Description>
  800. <BitOffset>0x0</BitOffset>
  801. <BitWidth>0x8</BitWidth>
  802. <Access>RW</Access>
  803. <Equation multiplier="0x1000" offset="0x08100000"/>
  804. </Bit>
  805. <Bit config="4,5">
  806. <Name>WRP2B_STRT</Name>
  807. <Description>The address of first page of the Bank 2 WRP second area</Description>
  808. <BitOffset>0x0</BitOffset>
  809. <BitWidth>0x8</BitWidth>
  810. <Access>RW</Access>
  811. <Equation multiplier="0x1000" offset="0x08080000"/>
  812. </Bit>
  813. <Bit config="7,8">
  814. <Name>WRP2B_STRT</Name>
  815. <Description>The address of first page of the Bank 2 WRP second area</Description>
  816. <BitOffset>0x0</BitOffset>
  817. <BitWidth>0x8</BitWidth>
  818. <Access>RW</Access>
  819. <Equation multiplier="0x1000" offset="0x08040000"/>
  820. </Bit>
  821. <Bit config="0,10">
  822. <Name>WRP2B_END</Name>
  823. <Description>The address of last page of the Bank 2 WRP second area</Description>
  824. <BitOffset>0x10</BitOffset>
  825. <BitWidth>0x8</BitWidth>
  826. <Access>RW</Access>
  827. <Equation multiplier="0x2000" offset="0x08100000"/>
  828. </Bit>
  829. <Bit config="2,3">
  830. <Name>WRP2B_END</Name>
  831. <Description>The address of last page of the Bank 2 WRP second area</Description>
  832. <BitOffset>0x10</BitOffset>
  833. <BitWidth>0x8</BitWidth>
  834. <Access>RW</Access>
  835. <Equation multiplier="0x2000" offset="0x08080000"/>
  836. </Bit>
  837. <Bit config="6,9">
  838. <Name>WRP2B_END</Name>
  839. <Description>The address of last page of the Bank 2 WRP second area</Description>
  840. <BitOffset>0x10</BitOffset>
  841. <BitWidth>0x8</BitWidth>
  842. <Access>RW</Access>
  843. <Equation multiplier="0x2000" offset="0x08040000"/>
  844. </Bit>
  845. <Bit config="1">
  846. <Name>WRP2B_END</Name>
  847. <Description>The address of last page of the Bank 2 WRP second area</Description>
  848. <BitOffset>0x10</BitOffset>
  849. <BitWidth>0x8</BitWidth>
  850. <Access>RW</Access>
  851. <Equation multiplier="0x1000" offset="0x08100000"/>
  852. </Bit>
  853. <Bit config="4,5">
  854. <Name>WRP2B_END</Name>
  855. <Description>The address of last page of the Bank 2 WRP second area</Description>
  856. <BitOffset>0x10</BitOffset>
  857. <BitWidth>0x8</BitWidth>
  858. <Access>RW</Access>
  859. <Equation multiplier="0x1000" offset="0x08080000"/>
  860. </Bit>
  861. <Bit config="7,8">
  862. <Name>WRP2B_END</Name>
  863. <Description>The address of last page of the Bank 2 WRP second area</Description>
  864. <BitOffset>0x10</BitOffset>
  865. <BitWidth>0x8</BitWidth>
  866. <Access>RW</Access>
  867. <Equation multiplier="0x1000" offset="0x08040000"/>
  868. </Bit>
  869. </AssignedBits>
  870. </Field>
  871. </Category>
  872. </Bank>
  873. <Bank interface="Bootloader">
  874. <Parameters address="0x1FF00000" name="Bank 1" size="0x24"/>
  875. <Category>
  876. <Name>Read Out Protection</Name>
  877. <Field>
  878. <Parameters address="0x1FF00000" name="FLASH_OPTR" size="0x4"/>
  879. <AssignedBits>
  880. <Bit>
  881. <Name>RDP</Name>
  882. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  883. <BitOffset>0x0</BitOffset>
  884. <BitWidth>0x8</BitWidth>
  885. <Access>RW</Access>
  886. <Values>
  887. <Val value="0xAA">Level 0, no protection</Val>
  888. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  889. <Val value="0xCC">Level 2, chip protection</Val>
  890. </Values>
  891. </Bit>
  892. </AssignedBits>
  893. </Field>
  894. </Category>
  895. <Category>
  896. <Name>BOR Level</Name>
  897. <Field>
  898. <Parameters address="0x1FF00000" name="FLASH_OPTR" size="0x4"/>
  899. <AssignedBits>
  900. <Bit>
  901. <Name>BOR_LEV</Name>
  902. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  903. <BitOffset>0x8</BitOffset>
  904. <BitWidth>0x3</BitWidth>
  905. <Access>RW</Access>
  906. <Values>
  907. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  908. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  909. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  910. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  911. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  912. </Values>
  913. </Bit>
  914. </AssignedBits>
  915. </Field>
  916. </Category>
  917. <Category>
  918. <Name>User Configuration</Name>
  919. <Field>
  920. <Parameters address="0x1FF00000" name="FLASH_OPTR" size="0x4"/>
  921. <AssignedBits>
  922. <Bit>
  923. <Name>nRST_STOP</Name>
  924. <Description/>
  925. <BitOffset>0xC</BitOffset>
  926. <BitWidth>0x1</BitWidth>
  927. <Access>RW</Access>
  928. <Values>
  929. <Val value="0x0">Reset generated when entering Stop mode</Val>
  930. <Val value="0x1">No reset generated</Val>
  931. </Values>
  932. </Bit>
  933. <Bit>
  934. <Name>nRST_STDBY</Name>
  935. <Description/>
  936. <BitOffset>0xD</BitOffset>
  937. <BitWidth>0x1</BitWidth>
  938. <Access>RW</Access>
  939. <Values>
  940. <Val value="0x0">Reset generated when entering Standby mode</Val>
  941. <Val value="0x1">No reset generated</Val>
  942. </Values>
  943. </Bit>
  944. <Bit>
  945. <Name>nRST_SHDW</Name>
  946. <Description/>
  947. <BitOffset>0xE</BitOffset>
  948. <BitWidth>0x1</BitWidth>
  949. <Access>RW</Access>
  950. <Values>
  951. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  952. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  953. </Values>
  954. </Bit>
  955. <Bit>
  956. <Name>IWDG_SW</Name>
  957. <Description/>
  958. <BitOffset>0x10</BitOffset>
  959. <BitWidth>0x1</BitWidth>
  960. <Access>RW</Access>
  961. <Values>
  962. <Val value="0x0">Hardware independant watchdog</Val>
  963. <Val value="0x1">Software independant watchdog</Val>
  964. </Values>
  965. </Bit>
  966. <Bit>
  967. <Name>IWDG_STOP</Name>
  968. <Description/>
  969. <BitOffset>0x11</BitOffset>
  970. <BitWidth>0x1</BitWidth>
  971. <Access>RW</Access>
  972. <Values>
  973. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  974. <Val value="0x1">IWDG counter active in stop mode</Val>
  975. </Values>
  976. </Bit>
  977. <Bit>
  978. <Name>IWDG_STDBY</Name>
  979. <Description/>
  980. <BitOffset>0x12</BitOffset>
  981. <BitWidth>0x1</BitWidth>
  982. <Access>RW</Access>
  983. <Values>
  984. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  985. <Val value="0x1">IWDG counter active in standby mode</Val>
  986. </Values>
  987. </Bit>
  988. <Bit>
  989. <Name>WWDG_SW</Name>
  990. <Description/>
  991. <BitOffset>0x13</BitOffset>
  992. <BitWidth>0x1</BitWidth>
  993. <Access>RW</Access>
  994. <Values>
  995. <Val value="0x0">Hardware window watchdog</Val>
  996. <Val value="0x1">Software window watchdog</Val>
  997. </Values>
  998. </Bit>
  999. <Bit>
  1000. <Name>BFB2</Name>
  1001. <Description/>
  1002. <BitOffset>0x14</BitOffset>
  1003. <BitWidth>0x1</BitWidth>
  1004. <Access>RW</Access>
  1005. <Values>
  1006. <Val value="0x0">Dual-bank boot disable</Val>
  1007. <Val value="0x1">Dual-bank boot enable</Val>
  1008. </Values>
  1009. </Bit>
  1010. <Bit config="10">
  1011. <Name>DB1M</Name>
  1012. <Description>Dual-Bank on 1 MB Flash or 512 KB Flash memory devices</Description>
  1013. <BitOffset>0x15</BitOffset>
  1014. <BitWidth>0x1</BitWidth>
  1015. <Access>RW</Access>
  1016. <Values>
  1017. <Val value="0x0">1 MB or 512 Kb single Flash: contiguous address in bank1</Val>
  1018. <Val value="0x1">1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb.</Val>
  1019. </Values>
  1020. </Bit>
  1021. <Bit>
  1022. <Name>DBANK</Name>
  1023. <Description>This bit can only be written when PCROPA/B is disabled.</Description>
  1024. <BitOffset>0x16</BitOffset>
  1025. <BitWidth>0x1</BitWidth>
  1026. <Access>RW</Access>
  1027. <Values>
  1028. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  1029. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  1030. </Values>
  1031. </Bit>
  1032. <Bit>
  1033. <Name>nBOOT1</Name>
  1034. <Description/>
  1035. <BitOffset>0x17</BitOffset>
  1036. <BitWidth>0x1</BitWidth>
  1037. <Access>RW</Access>
  1038. <Values>
  1039. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  1040. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  1041. </Values>
  1042. </Bit>
  1043. <Bit>
  1044. <Name>SRAM2_PE</Name>
  1045. <Description/>
  1046. <BitOffset>0x18</BitOffset>
  1047. <BitWidth>0x1</BitWidth>
  1048. <Access>RW</Access>
  1049. <Values>
  1050. <Val value="0x0">SRAM2 parity check enable</Val>
  1051. <Val value="0x1">SRAM2 parity check disable</Val>
  1052. </Values>
  1053. </Bit>
  1054. <Bit>
  1055. <Name>SRAM2_RST</Name>
  1056. <Description/>
  1057. <BitOffset>0x19</BitOffset>
  1058. <BitWidth>0x1</BitWidth>
  1059. <Access>RW</Access>
  1060. <Values>
  1061. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  1062. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  1063. </Values>
  1064. </Bit>
  1065. <Bit>
  1066. <Name>nSWBOOT0</Name>
  1067. <Description>Software BOOT0</Description>
  1068. <BitOffset>0x1A</BitOffset>
  1069. <BitWidth>0x1</BitWidth>
  1070. <Access>RW</Access>
  1071. <Values>
  1072. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  1073. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  1074. </Values>
  1075. </Bit>
  1076. <Bit>
  1077. <Name>nBOOT0</Name>
  1078. <Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
  1079. <BitOffset>0x1B</BitOffset>
  1080. <BitWidth>0x1</BitWidth>
  1081. <Access>RW</Access>
  1082. <Values>
  1083. <Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
  1084. <Val value="0x1">BOOT0 = 0, boot from main flash memory</Val>
  1085. </Values>
  1086. </Bit>
  1087. </AssignedBits>
  1088. </Field>
  1089. </Category>
  1090. <Category>
  1091. <Name>PCROP Protection (Bank 1)</Name>
  1092. <Field>
  1093. <Parameters address="0x1FF00008" name="FLASH_PCROP1SR" size="0x4"/>
  1094. <AssignedBits>
  1095. <Bit config="0,10">
  1096. <Name>PCROP1_STRT</Name>
  1097. <Description>Flash Bank 1 PCROP start address</Description>
  1098. <BitOffset>0x0</BitOffset>
  1099. <BitWidth>0x10</BitWidth>
  1100. <Access>RW</Access>
  1101. <Equation multiplier="0x16" offset="0x08000000"/>
  1102. </Bit>
  1103. <Bit config="1">
  1104. <Name>PCROP1_STRT</Name>
  1105. <Description>Flash Bank 1 PCROP start address</Description>
  1106. <BitOffset>0x0</BitOffset>
  1107. <BitWidth>0x11</BitWidth>
  1108. <Access>RW</Access>
  1109. <Equation multiplier="0x8" offset="0x08000000"/>
  1110. </Bit>
  1111. </AssignedBits>
  1112. </Field>
  1113. <Field>
  1114. <Parameters address="0x1FF00010" name="FLASH_PCROP1ER" size="0x4"/>
  1115. <AssignedBits>
  1116. <Bit config="0,10">
  1117. <Name>PCROP1_END</Name>
  1118. <Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  1119. <BitOffset>0x0</BitOffset>
  1120. <BitWidth>0x10</BitWidth>
  1121. <Access>RW</Access>
  1122. <Equation multiplier="0x16" offset="0x08000000"/>
  1123. </Bit>
  1124. <Bit config="1">
  1125. <Name>PCROP1_END</Name>
  1126. <Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  1127. <BitOffset>0x0</BitOffset>
  1128. <BitWidth>0x10</BitWidth>
  1129. <Access>RW</Access>
  1130. <Equation multiplier="0x8" offset="0x08000000"/>
  1131. </Bit>
  1132. <Bit>
  1133. <Name>PCROP_RDP</Name>
  1134. <Description/>
  1135. <BitOffset>0x1F</BitOffset>
  1136. <BitWidth>0x1</BitWidth>
  1137. <Access>RW</Access>
  1138. <Values>
  1139. <Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
  1140. <Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
  1141. </Values>
  1142. </Bit>
  1143. </AssignedBits>
  1144. </Field>
  1145. </Category>
  1146. <Category>
  1147. <Name>Write Protection (Bank 1)</Name>
  1148. <Field>
  1149. <Parameters address="0x1FF00018" name="FLASH_WRP1AR" size="0x4"/>
  1150. <AssignedBits>
  1151. <Bit config="0,10">
  1152. <Name>WRP1A_STRT</Name>
  1153. <Description>The address of the first page of the Bank 1 WRP first area</Description>
  1154. <BitOffset>0x0</BitOffset>
  1155. <BitWidth>0x8</BitWidth>
  1156. <Access>RW</Access>
  1157. <Equation multiplier="0x2000" offset="0x08000000"/>
  1158. </Bit>
  1159. <Bit config="1">
  1160. <Name>WRP1A_STRT</Name>
  1161. <Description>The address of the first page of the Bank 1 WRP first area</Description>
  1162. <BitOffset>0x0</BitOffset>
  1163. <BitWidth>0x8</BitWidth>
  1164. <Access>RW</Access>
  1165. <Equation multiplier="0x1000" offset="0x08000000"/>
  1166. </Bit>
  1167. <Bit config="0,10">
  1168. <Name>WRP1A_END</Name>
  1169. <Description>The address of the last page of the Bank 1 WRP first area</Description>
  1170. <BitOffset>0x10</BitOffset>
  1171. <BitWidth>0x8</BitWidth>
  1172. <Access>RW</Access>
  1173. <Equation multiplier="0x2000" offset="0x08000000"/>
  1174. </Bit>
  1175. <Bit config="1">
  1176. <Name>WRP1A_END</Name>
  1177. <Description>The address of the last page of the Bank 1 WRP first area</Description>
  1178. <BitOffset>0x10</BitOffset>
  1179. <BitWidth>0x8</BitWidth>
  1180. <Access>RW</Access>
  1181. <Equation multiplier="0x1000" offset="0x08000000"/>
  1182. </Bit>
  1183. </AssignedBits>
  1184. </Field>
  1185. <Field>
  1186. <Parameters address="0x1FF00020" name="FLASH_WRP1BR" size="0x4"/>
  1187. <AssignedBits>
  1188. <Bit config="0,10">
  1189. <Name>WRP1B_STRT</Name>
  1190. <Description>The address of the first page of the Bank 1 WRP second area</Description>
  1191. <BitOffset>0x0</BitOffset>
  1192. <BitWidth>0x8</BitWidth>
  1193. <Access>RW</Access>
  1194. <Equation multiplier="0x2000" offset="0x08000000"/>
  1195. </Bit>
  1196. <Bit config="1">
  1197. <Name>WRP1B_STRT</Name>
  1198. <Description>The address of the first page of the Bank 1 WRP second area</Description>
  1199. <BitOffset>0x0</BitOffset>
  1200. <BitWidth>0x8</BitWidth>
  1201. <Access>RW</Access>
  1202. <Equation multiplier="0x1000" offset="0x08000000"/>
  1203. </Bit>
  1204. <Bit config="0,10">
  1205. <Name>WRP1B_END</Name>
  1206. <Description>The address of the last page of the Bank 1 WRP second area</Description>
  1207. <BitOffset>0x10</BitOffset>
  1208. <BitWidth>0x8</BitWidth>
  1209. <Access>RW</Access>
  1210. <Equation multiplier="0x2000" offset="0x08000000"/>
  1211. </Bit>
  1212. <Bit config="1">
  1213. <Name>WRP1B_END</Name>
  1214. <Description>The address of the last page of the Bank 1 WRP second area</Description>
  1215. <BitOffset>0x10</BitOffset>
  1216. <BitWidth>0x8</BitWidth>
  1217. <Access>RW</Access>
  1218. <Equation multiplier="0x1000" offset="0x08000000"/>
  1219. </Bit>
  1220. </AssignedBits>
  1221. </Field>
  1222. </Category>
  1223. </Bank>
  1224. <Bank interface="Bootloader">
  1225. <Parameters address="0x1FF01008" name="Bank 2" size="0x1C"/>
  1226. <Category>
  1227. <Name>PCROP Protection (Bank 2)</Name>
  1228. <Field>
  1229. <Parameters address="0x1FF01008" name="FLASH_PCROP2SR" size="0x4"/>
  1230. <AssignedBits>
  1231. <Bit config="0,10">
  1232. <Name>PCROP2_STRT</Name>
  1233. <Description>Flash Bank 2 PCROP start address</Description>
  1234. <BitOffset>0x0</BitOffset>
  1235. <BitWidth>0x10</BitWidth>
  1236. <Access>RW</Access>
  1237. <Equation multiplier="0x16" offset="0x08100000"/>
  1238. </Bit>
  1239. <Bit config="1">
  1240. <Name>PCROP2_STRT</Name>
  1241. <Description>Flash Bank 2 PCROP start address</Description>
  1242. <BitOffset>0x0</BitOffset>
  1243. <BitWidth>0x10</BitWidth>
  1244. <Access>RW</Access>
  1245. <Equation multiplier="0x8" offset="0x08100000"/>
  1246. </Bit>
  1247. </AssignedBits>
  1248. </Field>
  1249. <Field>
  1250. <Parameters address="0x1FF01010" name="FLASH_PCROP2ER" size="0x4"/>
  1251. <AssignedBits>
  1252. <Bit config="0,10">
  1253. <Name>PCROP2_END</Name>
  1254. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  1255. <BitOffset>0x0</BitOffset>
  1256. <BitWidth>0x10</BitWidth>
  1257. <Access>RW</Access>
  1258. <Equation multiplier="0x16" offset="0x08100000"/>
  1259. </Bit>
  1260. <Bit config="1">
  1261. <Name>PCROP2_END</Name>
  1262. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  1263. <BitOffset>0x0</BitOffset>
  1264. <BitWidth>0x10</BitWidth>
  1265. <Access>RW</Access>
  1266. <Equation multiplier="0x8" offset="0x08100000"/>
  1267. </Bit>
  1268. </AssignedBits>
  1269. </Field>
  1270. </Category>
  1271. <Category>
  1272. <Name>Write Protection (Bank 2)</Name>
  1273. <Field>
  1274. <Parameters address="0x1FF01018" name="FLASH_WRP2AR" size="0x4"/>
  1275. <AssignedBits>
  1276. <Bit config="0,10">
  1277. <Name>WRP2A_STRT</Name>
  1278. <Description>The address of first page of the Bank 2 WRP first area</Description>
  1279. <BitOffset>0x0</BitOffset>
  1280. <BitWidth>0x8</BitWidth>
  1281. <Access>RW</Access>
  1282. <Equation multiplier="0x2000" offset="0x08100000"/>
  1283. </Bit>
  1284. <Bit config="1">
  1285. <Name>WRP2A_STRT</Name>
  1286. <Description>The address of first page of the Bank 2 WRP first area</Description>
  1287. <BitOffset>0x0</BitOffset>
  1288. <BitWidth>0x8</BitWidth>
  1289. <Access>RW</Access>
  1290. <Equation multiplier="0x1000" offset="0x08100000"/>
  1291. </Bit>
  1292. <Bit config="0,10">
  1293. <Name>WRP2A_END</Name>
  1294. <Description>The address of last page of the Bank 2 WRP first area</Description>
  1295. <BitOffset>0x10</BitOffset>
  1296. <BitWidth>0x8</BitWidth>
  1297. <Access>RW</Access>
  1298. <Equation multiplier="0x2000" offset="0x08100000"/>
  1299. </Bit>
  1300. <Bit config="1">
  1301. <Name>WRP2A_END</Name>
  1302. <Description>The address of last page of the Bank 2 WRP first area</Description>
  1303. <BitOffset>0x10</BitOffset>
  1304. <BitWidth>0x8</BitWidth>
  1305. <Access>RW</Access>
  1306. <Equation multiplier="0x1000" offset="0x08100000"/>
  1307. </Bit>
  1308. </AssignedBits>
  1309. </Field>
  1310. <Field>
  1311. <Parameters address="0x1FF01020" name="FLASH_WRP2BR" size="0x4"/>
  1312. <AssignedBits>
  1313. <Bit config="0,10">
  1314. <Name>WRP2B_STRT</Name>
  1315. <Description>The address of first page of the Bank 2 WRP second area</Description>
  1316. <BitOffset>0x0</BitOffset>
  1317. <BitWidth>0x8</BitWidth>
  1318. <Access>RW</Access>
  1319. <Equation multiplier="0x2000" offset="0x08100000"/>
  1320. </Bit>
  1321. <Bit config="1">
  1322. <Name>WRP2B_STRT</Name>
  1323. <Description>The address of first page of the Bank 2 WRP second area</Description>
  1324. <BitOffset>0x0</BitOffset>
  1325. <BitWidth>0x8</BitWidth>
  1326. <Access>RW</Access>
  1327. <Equation multiplier="0x1000" offset="0x08100000"/>
  1328. </Bit>
  1329. <Bit config="0,10">
  1330. <Name>WRP2B_END</Name>
  1331. <Description>The address of last page of the Bank 2 WRP second area</Description>
  1332. <BitOffset>0x10</BitOffset>
  1333. <BitWidth>0x8</BitWidth>
  1334. <Access>RW</Access>
  1335. <Equation multiplier="0x2000" offset="0x08100000"/>
  1336. </Bit>
  1337. <Bit config="1">
  1338. <Name>WRP2B_END</Name>
  1339. <Description>The address of last page of the Bank 2 WRP second area</Description>
  1340. <BitOffset>0x10</BitOffset>
  1341. <BitWidth>0x8</BitWidth>
  1342. <Access>RW</Access>
  1343. <Equation multiplier="0x1000" offset="0x08100000"/>
  1344. </Bit>
  1345. </AssignedBits>
  1346. </Field>
  1347. </Category>
  1348. </Bank>
  1349. </Peripheral>
  1350. </Peripherals>
  1351. </Device>
  1352. </Root>