STM32_Prog_DB_0x485.xml 25 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x485</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M7</CPU>
  8. <Name>STM32H7Rxx</Name>
  9. <Series>STM32H7</Series>
  10. <Description>ARM 32-bit Cortex-M7 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- Security extension available -->
  15. <SecurityEx>
  16. <WriteRegister address="0x580244F4" value="0x2"/>
  17. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  18. </SecurityEx>
  19. </Configuration>
  20. <Configuration number="0x1"> <!-- Security extension not available -->
  21. <SecurityEx>
  22. <WriteRegister address="0x580244F4" value="0x2"/>
  23. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  24. </SecurityEx>
  25. </Configuration>
  26. </Interface>
  27. <!-- Bootloader Interface -->
  28. <Interface name="Bootloader">
  29. <Configuration number="0x0"> <!-- dummy always true, security extension is checked using dedicated cmd -->
  30. <Dummy>
  31. <ReadRegister address="0x08000000" mask="0x0" value="0x0"/>
  32. </Dummy>
  33. </Configuration>
  34. </Interface>
  35. </Configurations>
  36. <!-- Peripherals -->
  37. <Peripherals>
  38. <!-- Embedded SRAM -->
  39. <Peripheral>
  40. <Name>Embedded SRAM</Name>
  41. <Type>Storage</Type>
  42. <Description/>
  43. <ErasedValue>0x00</ErasedValue>
  44. <Access>RWE</Access>
  45. <!-- 1024 KB -->
  46. <Configuration>
  47. <Parameters address="0x20000000" name="SRAM" size="0x10000"/>
  48. <Description/>
  49. <Organization>Single</Organization>
  50. <Bank name="Bank 1">
  51. <Field>
  52. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x10000"/>
  53. </Field>
  54. </Bank>
  55. </Configuration>
  56. </Peripheral>
  57. <!-- Embedded Flash -->
  58. <Peripheral>
  59. <Name>Embedded Flash</Name>
  60. <Type>Storage</Type>
  61. <Description>The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  62. <ErasedValue>0xFF</ErasedValue>
  63. <Access>RWE</Access>
  64. <FlashSize address="0x08fff80c" default="0x10000"/>
  65. <!-- 1MB Single Bank -->
  66. <Configuration config="0,1">
  67. <Parameters address="0x08000000" name="64 KBytes Single Bank Embedded Flash" size="0x10000"/>
  68. <Description/>
  69. <Organization>Single</Organization>
  70. <Allignement>0x80</Allignement>
  71. <Bank name="Bank 1">
  72. <Field>
  73. <Parameters address="0x08000000" name="sector0" occurence="0x8" size="0x2000"/>
  74. </Field>
  75. </Bank>
  76. </Configuration>
  77. </Peripheral>
  78. <!-- Option Bytes -->
  79. <Peripheral>
  80. <Name>Option Bytes</Name>
  81. <Type>Configuration</Type>
  82. <Description/>
  83. <Access>RW</Access>
  84. <Bank>
  85. <Parameters address="0x52002200" name="Bank 1" size="0x70"/>
  86. <Category>
  87. <Name>Flash Non Volatile State</Name>
  88. <Field>
  89. <Parameters address="0x52002200" name="FLASH_NVSR" size="0x4"/>
  90. <AssignedBits>
  91. <Bit>
  92. <Name>FLASH_NVSR</Name>
  93. <Description>FLASH security status register programming.</Description>
  94. <BitOffset>0x0</BitOffset>
  95. <BitWidth>0x8</BitWidth>
  96. <Access>R</Access>
  97. <Values>
  98. <Val value="0xB4">OPEN device</Val>
  99. <Val value="0x51">CLOSED device</Val>
  100. </Values>
  101. </Bit>
  102. </AssignedBits>
  103. </Field>
  104. <Field>
  105. <Parameters address="0x52002204" name="FLASH_NVSR" size="0x4"/>
  106. <AssignedBits>
  107. <Bit>
  108. <Name>FLASH_NVSR</Name>
  109. <Description>FLASH security status register programming.</Description>
  110. <BitOffset>0x0</BitOffset>
  111. <BitWidth>0x8</BitWidth>
  112. <Access>W</Access>
  113. <Values>
  114. <Val value="0xB4">OPEN device</Val>
  115. <Val value="0x51">CLOSED device</Val>
  116. </Values>
  117. </Bit>
  118. </AssignedBits>
  119. </Field>
  120. </Category>
  121. <Category>
  122. <Name>BOR Level</Name>
  123. <Field>
  124. <Parameters address="0x52002260" name="FOPTSR_CUR" size="0x4"/>
  125. <AssignedBits>
  126. <Bit>
  127. <Name>BOR_LEV</Name>
  128. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  129. <BitOffset>0x2</BitOffset>
  130. <BitWidth>0x2</BitWidth>
  131. <Access>R</Access>
  132. <Values>
  133. <Val value="0x0">BOR OFF</Val>
  134. <Val value="0x1">BOR level1: 2.1V</Val>
  135. <Val value="0x2">BOR level2: 2.4 V</Val>
  136. <Val value="0x3">BOR level3: 2.7 V</Val>
  137. </Values>
  138. </Bit>
  139. </AssignedBits>
  140. </Field>
  141. <Field>
  142. <Parameters address="0x52002264" name="FOPTSR_PRG" size="0x4"/>
  143. <AssignedBits>
  144. <Bit>
  145. <Name>BOR_LEV</Name>
  146. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  147. <BitOffset>0x2</BitOffset>
  148. <BitWidth>0x2</BitWidth>
  149. <Access>W</Access>
  150. <Values>
  151. <Val value="0x0">reset level is set to 0.0 V</Val>
  152. <Val value="0x1">reset level is set to 2.1 V</Val>
  153. <Val value="0x2">reset level is set to 2.4 V</Val>
  154. <Val value="0x3">reset level is set to 2.7 V</Val>
  155. </Values>
  156. </Bit>
  157. </AssignedBits>
  158. </Field>
  159. </Category>
  160. <Category>
  161. <Name>User Configuration1</Name>
  162. <Field>
  163. <Parameters address="0x52002260" name="FOPTSR1_CUR" size="0x4"/>
  164. <AssignedBits>
  165. <Bit>
  166. <Name>IWDG1_SW</Name>
  167. <Description/>
  168. <BitOffset>0x4</BitOffset>
  169. <BitWidth>0x1</BitWidth>
  170. <Access>R</Access>
  171. <Values>
  172. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  173. <Val value="0x1">Independent watchdog is controlled by software</Val>
  174. </Values>
  175. </Bit>
  176. <Bit>
  177. <Name>NRST_STOP</Name>
  178. <Description/>
  179. <BitOffset>0x6</BitOffset>
  180. <BitWidth>0x1</BitWidth>
  181. <Access>R</Access>
  182. <Values>
  183. <Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
  184. <Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
  185. </Values>
  186. </Bit>
  187. <Bit>
  188. <Name>NRST_STBY</Name>
  189. <Description/>
  190. <BitOffset>0x7</BitOffset>
  191. <BitWidth>0x1</BitWidth>
  192. <Access>R</Access>
  193. <Values>
  194. <Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
  195. <Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
  196. </Values>
  197. </Bit>
  198. <Bit>
  199. <Name>IO_HSLV</Name>
  200. <Description/>
  201. <BitOffset>0x1D</BitOffset>
  202. <BitWidth>0x1</BitWidth>
  203. <Access>R</Access>
  204. <Values>
  205. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  206. <Val value="0x1">Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  207. </Values>
  208. </Bit>
  209. <Bit>
  210. <Name>FZ_IWDG_STOP</Name>
  211. <Description/>
  212. <BitOffset>0x11</BitOffset>
  213. <BitWidth>0x1</BitWidth>
  214. <Access>R</Access>
  215. <Values>
  216. <Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
  217. <Val value="0x1">Independent watchdog is running in STOP mode</Val>
  218. </Values>
  219. </Bit>
  220. <Bit>
  221. <Name>FZ_IWDG_SDBY</Name>
  222. <Description/>
  223. <BitOffset>0x12</BitOffset>
  224. <BitWidth>0x1</BitWidth>
  225. <Access>R</Access>
  226. <Values>
  227. <Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
  228. <Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
  229. </Values>
  230. </Bit>
  231. <Bit>
  232. <Name>OCTO1_HSLV</Name>
  233. <Description/>
  234. <BitOffset>0x8</BitOffset>
  235. <BitWidth>0x1</BitWidth>
  236. <Access>R</Access>
  237. <Values>
  238. <Val value="0x0">I/O Octo1 High-Speed option disabled</Val>
  239. <Val value="0x1">I/O Octo1 High-Speed option enabled</Val>
  240. </Values>
  241. </Bit>
  242. <Bit>
  243. <Name>OCTO2_HSLV</Name>
  244. <Description/>
  245. <BitOffset>0x9</BitOffset>
  246. <BitWidth>0x1</BitWidth>
  247. <Access>R</Access>
  248. <Values>
  249. <Val value="0x0">I/O Octo2 High-Speed option disabled</Val>
  250. <Val value="0x1">I/O Octo2 High-Speed option enabled</Val>
  251. </Values>
  252. </Bit>
  253. </AssignedBits>
  254. </Field>
  255. <Field>
  256. <Parameters address="0x52002264" name="FOPTSR1_PRG" size="0x4"/>
  257. <AssignedBits>
  258. <Bit>
  259. <Name>IWDG1_SW</Name>
  260. <Description/>
  261. <BitOffset>0x4</BitOffset>
  262. <BitWidth>0x1</BitWidth>
  263. <Access>W</Access>
  264. <Values>
  265. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  266. <Val value="0x1">Independent watchdog is controlled by software</Val>
  267. </Values>
  268. </Bit>
  269. <Bit>
  270. <Name>NRST_STOP</Name>
  271. <Description/>
  272. <BitOffset>0x6</BitOffset>
  273. <BitWidth>0x1</BitWidth>
  274. <Access>W</Access>
  275. <Values>
  276. <Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
  277. <Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
  278. </Values>
  279. </Bit>
  280. <Bit>
  281. <Name>NRST_STBY</Name>
  282. <Description/>
  283. <BitOffset>0x7</BitOffset>
  284. <BitWidth>0x1</BitWidth>
  285. <Access>W</Access>
  286. <Values>
  287. <Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
  288. <Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
  289. </Values>
  290. </Bit>
  291. <Bit>
  292. <Name>IO_HSLV</Name>
  293. <Description/>
  294. <BitOffset>0x1D</BitOffset>
  295. <BitWidth>0x1</BitWidth>
  296. <Access>W</Access>
  297. <Values>
  298. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  299. <Val value="0x1">Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  300. </Values>
  301. </Bit>
  302. <Bit>
  303. <Name>FZ_IWDG_STOP</Name>
  304. <Description/>
  305. <BitOffset>0x11</BitOffset>
  306. <BitWidth>0x1</BitWidth>
  307. <Access>W</Access>
  308. <Values>
  309. <Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
  310. <Val value="0x1">Independent watchdog is running in STOP mode</Val>
  311. </Values>
  312. </Bit>
  313. <Bit>
  314. <Name>FZ_IWDG_SDBY</Name>
  315. <Description/>
  316. <BitOffset>0x12</BitOffset>
  317. <BitWidth>0x1</BitWidth>
  318. <Access>W</Access>
  319. <Values>
  320. <Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
  321. <Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
  322. </Values>
  323. </Bit>
  324. <Bit>
  325. <Name>OCTO1_HSLV</Name>
  326. <Description/>
  327. <BitOffset>0x8</BitOffset>
  328. <BitWidth>0x1</BitWidth>
  329. <Access>W</Access>
  330. <Values>
  331. <Val value="0x0">I/O Octo1 High-Speed option disabled</Val>
  332. <Val value="0x1">I/O Octo1 High-Speed option enabled</Val>
  333. </Values>
  334. </Bit>
  335. <Bit>
  336. <Name>OCTO2_HSLV</Name>
  337. <Description/>
  338. <BitOffset>0x9</BitOffset>
  339. <BitWidth>0x1</BitWidth>
  340. <Access>W</Access>
  341. <Values>
  342. <Val value="0x0">I/O Octo2 High-Speed option disabled</Val>
  343. <Val value="0x1">I/O Octo2 High-Speed option enabled</Val>
  344. </Values>
  345. </Bit>
  346. </AssignedBits>
  347. </Field>
  348. </Category>
  349. <Category>
  350. <Name>User Configuration 2</Name>
  351. <Field>
  352. <Parameters address="0x52002268" name="FOPTSR2_CUR" size="0x4"/>
  353. <AssignedBits>
  354. <Bit>
  355. <Name>I2c_NI3C</Name>
  356. <Description/>
  357. <BitOffset>0x9</BitOffset>
  358. <BitWidth>0x1</BitWidth>
  359. <Access>R</Access>
  360. <Values>
  361. <Val value="0x0">I3C is selected</Val>
  362. <Val value="0x1">I2C is delected</Val>
  363. </Values>
  364. </Bit>
  365. <Bit>
  366. <Name>ECC_ON_SRAM</Name>
  367. <Description/>
  368. <BitOffset>0x8</BitOffset>
  369. <BitWidth>0x1</BitWidth>
  370. <Access>R</Access>
  371. <Values>
  372. <Val value="0x0">ECC_ON_SRAM disabled</Val>
  373. <Val value="0x1">ECC_ON_SRAM enabled</Val>
  374. </Values>
  375. </Bit>
  376. </AssignedBits>
  377. </Field>
  378. <Field>
  379. <Parameters address="0x5200226C" name="FOPTSR2_PRG" size="0x4"/>
  380. <AssignedBits>
  381. <Bit>
  382. <Name>I2c_NI3C</Name>
  383. <Description/>
  384. <BitOffset>0x9</BitOffset>
  385. <BitWidth>0x1</BitWidth>
  386. <Access>W</Access>
  387. <Values>
  388. <Val value="0x0">I3C is selected</Val>
  389. <Val value="0x1">I2C is delected</Val>
  390. </Values>
  391. </Bit>
  392. <Bit>
  393. <Name>ECC_ON_SRAM</Name>
  394. <Description/>
  395. <BitOffset>0x8</BitOffset>
  396. <BitWidth>0x1</BitWidth>
  397. <Access>W</Access>
  398. <Values>
  399. <Val value="0x0">ECC_ON_SRAM disabled</Val>
  400. <Val value="0x1">ECC_ON_SRAM enabled</Val>
  401. </Values>
  402. </Bit>
  403. </AssignedBits>
  404. </Field>
  405. </Category>
  406. <Category>
  407. <Name>DTCM RAM Protection</Name>
  408. <Field>
  409. <Parameters address="0x52002268" name="FOPTSR2_CUR" size="0x4"/>
  410. <AssignedBits>
  411. <Bit config="0">
  412. <Name>DTCM_AXI_SHARE</Name>
  413. <Description/>
  414. <BitOffset>0x4</BitOffset>
  415. <BitWidth>0x3</BitWidth>
  416. <Access>R</Access>
  417. <Values>
  418. <Val value="0x0">2 KB reserved to ST code</Val>
  419. <Val value="0x1">4 KB reserved to ST code</Val>
  420. <Val value="0x2">8 KB reserved to ST code</Val>
  421. <Val value="0x3">16 KB reserved to ST code</Val>
  422. </Values>
  423. </Bit>
  424. </AssignedBits>
  425. </Field>
  426. <Field>
  427. <Parameters address="0x5200226C" name="FOPTSR2_PRG" size="0x4"/>
  428. <AssignedBits>
  429. <Bit config="0">
  430. <Name>DTCM_AXI_SHARE</Name>
  431. <Description/>
  432. <BitOffset>0x4</BitOffset>
  433. <BitWidth>0x3</BitWidth>
  434. <Access>W</Access>
  435. <Values>
  436. <Val value="0x0">2 KB reserved to ST code</Val>
  437. <Val value="0x1">4 KB reserved to ST code</Val>
  438. <Val value="0x2">8 KB reserved to ST code</Val>
  439. <Val value="0x3">16 KB reserved to ST code</Val>
  440. </Values>
  441. </Bit>
  442. </AssignedBits>
  443. </Field>
  444. </Category>
  445. <Category>
  446. <Name>ITCM RAM Protection</Name>
  447. <Field>
  448. <Parameters address="0x52002268" name="FOPTSR2_CUR" size="0x4"/>
  449. <AssignedBits>
  450. <Bit config="0">
  451. <Name>ITCM_AXI_SHARE</Name>
  452. <Description/>
  453. <BitOffset>0x0</BitOffset>
  454. <BitWidth>0x3</BitWidth>
  455. <Access>R</Access>
  456. <Values>
  457. <Val value="0x0">2 KB reserved to ST code</Val>
  458. <Val value="0x1">4 KB reserved to ST code</Val>
  459. <Val value="0x2">8 KB reserved to ST code</Val>
  460. <Val value="0x3">16 KB reserved to ST code</Val>
  461. </Values>
  462. </Bit>
  463. </AssignedBits>
  464. </Field>
  465. <Field>
  466. <Parameters address="0x5200226C" name="FOPTSR2_PRG" size="0x4"/>
  467. <AssignedBits>
  468. <Bit config="0">
  469. <Name>ITCM_AXI_SHARE</Name>
  470. <Description/>
  471. <BitOffset>0x0</BitOffset>
  472. <BitWidth>0x3</BitWidth>
  473. <Access>W</Access>
  474. <Values>
  475. <Val value="0x0">2 KB reserved to ST code</Val>
  476. <Val value="0x1">4 KB reserved to ST code</Val>
  477. <Val value="0x2">8 KB reserved to ST code</Val>
  478. <Val value="0x3">16 KB reserved to ST code</Val>
  479. </Values>
  480. </Bit>
  481. </AssignedBits>
  482. </Field>
  483. </Category>
  484. <Category>
  485. <Name>Write Protection</Name>
  486. <Field>
  487. <Parameters address="0x52002218" name="FWPSN_CUR_A" size="0x4"/>
  488. <AssignedBits>
  489. <Bit config="0,1">
  490. <Name>nWRP0</Name>
  491. <Description/>
  492. <BitOffset>0x0</BitOffset>
  493. <BitWidth>0x8</BitWidth>
  494. <Access>R</Access>
  495. <Values ByBit="true">
  496. <Val value="0x0">Write protection active</Val>
  497. <Val value="0x1">Write protection not active</Val>
  498. </Values>
  499. </Bit>
  500. </AssignedBits>
  501. </Field>
  502. <Field>
  503. <Parameters address="0x5200221C" name="FWPSN_PRG_A" size="0x4"/>
  504. <AssignedBits>
  505. <Bit config="0,1">
  506. <Name>nWRP0</Name>
  507. <Description/>
  508. <BitOffset>0x0</BitOffset>
  509. <BitWidth>0x8</BitWidth>
  510. <Access>W</Access>
  511. <Values ByBit="true">
  512. <Val value="0x0">Write protection active</Val>
  513. <Val value="0x1">Write protection not active</Val>
  514. </Values>
  515. </Bit>
  516. </AssignedBits>
  517. </Field>
  518. </Category>
  519. <Category>
  520. <Name>Flash HDP bank </Name>
  521. <Field>
  522. <Parameters address="0x52002230" name="FLASH_HDP" size="0x4"/>
  523. <AssignedBits>
  524. <Bit>
  525. <Name>HDP1_STRT</Name>
  526. <Description>TIL barrier start set in number of 8kb sectors</Description>
  527. <BitOffset>0x0</BitOffset>
  528. <BitWidth>0x9</BitWidth>
  529. <Access>R</Access>
  530. <Equation multiplier="0x2000" offset="0x00000001"/>
  531. </Bit>
  532. <Bit>
  533. <Name>HDP1_END</Name>
  534. <Description>TIL barrier end set in number of 8kb sectors</Description>
  535. <BitOffset>0x10</BitOffset>
  536. <BitWidth>0x9</BitWidth>
  537. <Access>R</Access>
  538. <Equation multiplier="0x2000" offset="0x00000001"/>
  539. </Bit>
  540. </AssignedBits>
  541. </Field>
  542. <Field>
  543. <Parameters address="0x52002234" name="FLASH_HDP" size="0x4"/>
  544. <AssignedBits>
  545. <Bit>
  546. <Name>HDP1_STRT</Name>
  547. <Description>TIL barrier start set in number of 8kb sectors</Description>
  548. <BitOffset>0x0</BitOffset>
  549. <BitWidth>0x9</BitWidth>
  550. <Access>W</Access>
  551. <Equation multiplier="0x2000" offset="0x00000001"/>
  552. </Bit>
  553. <Bit>
  554. <Name>HDP1_END</Name>
  555. <Description>TIL barrier end set in number of 8kb sectors</Description>
  556. <BitOffset>0x10</BitOffset>
  557. <BitWidth>0x9</BitWidth>
  558. <Access>W</Access>
  559. <Equation multiplier="0x2000" offset="0x00000001"/>
  560. </Bit>
  561. </AssignedBits>
  562. </Field>
  563. </Category>
  564. <Category>
  565. <Name>Flash EPOCH</Name>
  566. <Field>
  567. <Parameters address="0x52002250" name="FLASH_EPOCH" size="0x4"/>
  568. <AssignedBits>
  569. <Bit>
  570. <Name>EPOCH</Name>
  571. <Description>Non Volatile Non Secure EPOCH counter</Description>
  572. <BitOffset>0x0</BitOffset>
  573. <BitWidth>0x18</BitWidth>
  574. <Access>R</Access>
  575. </Bit>
  576. </AssignedBits>
  577. </Field>
  578. <Field>
  579. <Parameters address="0x52002254" name="FLASH_EPOCH" size="0x4"/>
  580. <AssignedBits>
  581. <Bit>
  582. <Name>EPOCH</Name>
  583. <Description>Non Volatile Secure EPOCH counter</Description>
  584. <BitOffset>0x0</BitOffset>
  585. <BitWidth>0x18</BitWidth>
  586. <Access>W</Access>
  587. </Bit>
  588. </AssignedBits>
  589. </Field>
  590. </Category>
  591. <Category>
  592. <Name>OTP write protection</Name>
  593. <Field>
  594. <Parameters address="0x52002210" name="FLASH_OTP" size="0x4"/>
  595. <AssignedBits>
  596. <Bit>
  597. <Name>LOCKBL</Name>
  598. <Description>OTP Lock</Description>
  599. <BitOffset>0x0</BitOffset>
  600. <BitWidth>0x10</BitWidth>
  601. <Access>R</Access>
  602. <Equation multiplier="0x2000" offset="0x00000000"/>
  603. </Bit>
  604. </AssignedBits>
  605. </Field>
  606. <Field>
  607. <Parameters address="0x52002214" name="FLASH_OTP" size="0x4"/>
  608. <AssignedBits>
  609. <Bit>
  610. <Name>LOCKBL</Name>
  611. <Description>OTP Lock</Description>
  612. <BitOffset>0x0</BitOffset>
  613. <BitWidth>0x10</BitWidth>
  614. <Access>W</Access>
  615. <Equation multiplier="0x2000" offset="0x00000000"/>
  616. </Bit>
  617. </AssignedBits>
  618. </Field>
  619. </Category>
  620. <Category>
  621. <Name>FLASH ROT programming</Name>
  622. <Field>
  623. <Parameters address="0x52002208" name="FLASH_IROT" size="0x4"/>
  624. <AssignedBits>
  625. <Bit>
  626. <Name>OEM_PROV</Name>
  627. <Description>OEM provisioned device</Description>
  628. <BitOffset>0x0</BitOffset>
  629. <BitWidth>0x8</BitWidth>
  630. <Access>R</Access>
  631. </Bit>
  632. <Bit>
  633. <Name>IROT_SELECT</Name>
  634. <Description>OEM provisioned device</Description>
  635. <BitOffset>0x18</BitOffset>
  636. <BitWidth>0x8</BitWidth>
  637. <Access>R</Access>
  638. </Bit>
  639. <Bit>
  640. <Name>DBG_AUTH</Name>
  641. <Description>Debug authentication method</Description>
  642. <BitOffset>0x8</BitOffset>
  643. <BitWidth>0x8</BitWidth>
  644. <Access>R</Access>
  645. </Bit>
  646. </AssignedBits>
  647. </Field>
  648. <Field>
  649. <Parameters address="0x52002214" name="FLASH_IROT_prog" size="0x4"/>
  650. <AssignedBits>
  651. <Bit>
  652. <Name>IROT_SELECT</Name>
  653. <Description>OEM provisioned device</Description>
  654. <BitOffset>0x18</BitOffset>
  655. <BitWidth>0x8</BitWidth>
  656. <Access>W</Access>
  657. </Bit>
  658. <Bit>
  659. <Name>DBG_AUTH</Name>
  660. <Description>Debug authentication method</Description>
  661. <BitOffset>0x8</BitOffset>
  662. <BitWidth>0x8</BitWidth>
  663. <Access>W</Access>
  664. </Bit>
  665. <Bit>
  666. <Name>OEM_PROV</Name>
  667. <Description>OEM provisioned device</Description>
  668. <BitOffset>0x0</BitOffset>
  669. <BitWidth>0x8</BitWidth>
  670. <Access>W</Access>
  671. </Bit>
  672. </AssignedBits>
  673. </Field>
  674. </Category>
  675. <Category>
  676. <Name>FLASH fixed bank</Name>
  677. <Field>
  678. <Parameters address="0x52002248" name="FLASH_FIXED" size="0x4"/>
  679. <AssignedBits>
  680. <Bit>
  681. <Name>NUM_FIXED_SECT</Name>
  682. <Description>Number of fixed sectors</Description>
  683. <BitOffset>0x1</BitOffset>
  684. <BitWidth>0x3</BitWidth>
  685. <Access>R</Access>
  686. </Bit>
  687. <Bit>
  688. <Name>EN_SWAP_BANK</Name>
  689. <Description>enable swap bank</Description>
  690. <BitOffset>0x10</BitOffset>
  691. <BitWidth>0x1</BitWidth>
  692. <Access>R</Access>
  693. <Values ByBit="true">
  694. <Val value="0x0">swap bank disable</Val>
  695. <Val value="0x1">swap bank enable</Val>
  696. </Values>
  697. </Bit>
  698. <Bit>
  699. <Name>LOCK_FIXED</Name>
  700. <Description>lock fixed</Description>
  701. <BitOffset>0x14</BitOffset>
  702. <BitWidth>0x1</BitWidth>
  703. <Access>R</Access>
  704. <Values ByBit="true">
  705. <Val value="0x0">lock disable</Val>
  706. <Val value="0x1">lock enable</Val>
  707. </Values>
  708. </Bit>
  709. </AssignedBits>
  710. </Field>
  711. <Field>
  712. <Parameters address="0x5200224C" name="FLASH_FIXED_PROG" size="0x4"/>
  713. <AssignedBits>
  714. <Bit>
  715. <Name>NUM_FIXED_SECT</Name>
  716. <Description>Number of fixed sectors</Description>
  717. <BitOffset>0x1</BitOffset>
  718. <BitWidth>0x3</BitWidth>
  719. <Access>W</Access>
  720. </Bit>
  721. <Bit>
  722. <Name>EN_SWAP_BANK</Name>
  723. <Description>enable swap bank</Description>
  724. <BitOffset>0x10</BitOffset>
  725. <BitWidth>0x1</BitWidth>
  726. <Access>W</Access>
  727. <Values ByBit="true">
  728. <Val value="0x0">swap bank disable</Val>
  729. <Val value="0x1">swap bank enable</Val>
  730. </Values>
  731. </Bit>
  732. <Bit>
  733. <Name>LOCK_FIXED</Name>
  734. <Description>lock fixed</Description>
  735. <BitOffset>0x14</BitOffset>
  736. <BitWidth>0x1</BitWidth>
  737. <Access>W</Access>
  738. <Values ByBit="true">
  739. <Val value="0x0">lock disable</Val>
  740. <Val value="0x1">lock enable</Val>
  741. </Values>
  742. </Bit>
  743. </AssignedBits>
  744. </Field>
  745. </Category>
  746. </Bank>
  747. </Peripheral>
  748. </Peripherals>
  749. </Device>
  750. </Root>