Merge pull request #1 from yangjie11/dev-315

更新至 nano 3.1.5

ChangeLog.md

@@ -1,1203 +1,23 @@
-# RT-Thread v3.1.3 Change Log
+# RT-Thread nano v3.1.5 Change Log
 
-## Kernel
-
-* Fix the `rt_tick_from_millisecond()` compilation warning issue;
-* Fix the issue that the system object is not detached when handling defunct threads. 
-* Add the value checking of semaphore (the maximum value of semaphore is up to 65535)
-* Add the checking and assertion of re-initialization of object.
-* In the rt_enter_critical/rt_exit_critical function, add the checking of whether scheduler is startup or not.
-* Fix the definition issue of `ENOTSUP` in libc_errno.h.
-* Simplify the rtdbg.h file and use ulog to make log/debug system easier to use.
-* Add the configuration of RT_USING_ARCH_DATA_TYPE, `rt_int8_t/.../rt_uint32_t` and other basic data types can be defined by BSP itself. (It is recommended to put them into the rtconfig_project.h file, so that this file can be automatically included in rtconfig.h when menuconfig generates it.)
-* Add `RT_Device_Class_Sensor` type devices;
-* In the case of single core, the definition of `rt_hw_spin_lock/rt_hw_spin_unlock` is redefined as the disable/enable interrupt.
-* Add the `rt_strnlen()` function in kservice.c.
-* Support the long long type in rt_kprintf (HubertXie);
-
-## Components
-
-* Remove CMSIS and move to software package as CMSIS package.
-* Remove logtrace component. The system log system switches to ulog;
-* Add more code to support AC6 tool chain in some BSP and components;
-* In DFS file system component, clean up the log and fix the mkfs issue when index may be out of range.
-* Split the running mode from sleep mode in power management, and the frequency change should be clearer. Power management is not use idle hook but execute the sleep action in idle thread directly. (How to use power management, please visit programming document for details)
-* Cleanup the log of MMC/SD driver framework;
-* Rewrite Sensor Framework, replace the original C++ implementation with C version, and add some corresponding sensor software packages; To use the sensor packages, please use this release;
-* Add the DMA transmission operation in the serial driver framework;
-* Add the consistency protection to tc_flush routine of serial driver (loogg).
-* Add rt_sfud_flash_find_by_dev_name API in SFUD.
-* When the Pipe device closed, if it is an unnamed Pipe device and the open count is 0, this Pipe device will be deleted.
-* The delayed work implementation is added to workqueue, and the workqueue of the system is added as an option.
-* Fix the data loss issue when using DMA transmission in USB CDC.
-* Change the return type of finsh_getchar to int;
-* Fix the errno issue in newlib/GCC tool chain.
-* Change the management of pthreads to POSIX thread array instead of mapping pthread_t directly to rt_thread_t; Change the fields definition more similar with newlib/glibc in pthreads.
-* Fix the thread name output in ulog.
-* Add loop parameter in utest, then executes test cases repeatedly; Add thread parameter in utest to execute testcase in a new thread.
-* Add delay in handshake phase to protect incomplete data reception in YModem component.
-* Add netdev component, abstract netdev concept, used to management and control network interface device, and provide netdev operation commands, including ping/ifconfig/dns/netstat etc;
-* Modify SAL for netdev, that is, adds the judgment of netdev status and information when the socket creating and data transmitting;
-* Add options and types for UDP multicast traffic handling and IPPROTO_IP in SAL;
-* Fix `itctrol()` function not support to control socketfd issues in SAL;
-* Improve error log processing in AT socket;
-* Fix serial receive data failed issues when AT client initialization is not completed;
-
-## BSP
-
-* Add IMXRT1021-EVK BSP (NXP provides maintenance and support);
-* Add the ETH hardware checksum option in IMXRT1052 ETH driver;
-* Cleanup the LPC 4088 BSP to use main function entry and support menuconfig;
-* The double Frame Buffer mechanism and touch screen driver are added in Godson 1C BSP, then it can better to support Persimmon UI (sundm75).
-* Add watchdog driver in Godson 1C BSP(sundm75);
-* Fix the SysTick interrupt handling issue in nRF52832 and add menuconfig configuration file.
-* Add QSPI and SPI flash driver to Nuvoton M487 BSP (bluebear 233)
-* Change the CPU porting to libcpu/arm/cortex-a folder in QEMU-VExpress A9/IMX6UL BSP;
-* In QEMU-VExpress A9 BSP, the MAC address associated with the local MAC address is used for a unified MAC address in the network.
-* remove stm32f0x, stm32f7-disco, stm32f107, stm32f40x, stm32l072, stm32l475-iot-disco, stm32l476-nucleo BSP (when the new STM32 BSP can completely replace these old BSP, these BSP will be removed);
-* For the new STM32 BSP:
-  * Add CAN driver (ylz0923)
-  * Add CAN driver to stm32f103-fire-arbitrary (ylz0923)
-  * stm32f746-st-disco with LCD, watchdog, SDCard, ethernet, Flash and other drivers (Jinsheng)
-* More board support is added to the new STM32 BSP:
-  * stm32f103-atk-warship V3 ATK Warship V3 (daizhiwang)
-  * STm32f103-dofly-M3S Dofly STM32F103 Development Board
-  * stm32f103-mini-system, the minimum system board for STM32F103 (daizhiwang)
-  * stm32f401-st-nucleo
-  * stm32f405-smdz-breadfruit sanmu electronic stm32405 development board (sunlichao)
-  * stm32f469-st-disco
-  * stm32h743-atk-apollo (whj4674672)
-  * stm32l4r9-st-eval
-  * stm32l053-st-nucleo (sun_shine)
-  * stm32l475-st-discovery
-  * stm32l476-st-nucleo (Vincent-VG)
-  * stm32l496-ali-developer
-* The SCI driver is added to the TMS320F28379D BSP (xuzuoyi).
-* Add W60X Wi-Fi SoC chip BSP from Winner Microelectronics Co.,Ltd. (Winner Micro and RealThread provide maintenance and support);
-* Fix the UART2 IO configuration issue in X1000 UART driver (Zhou Yanjie);
-* Cleanup the libcpu/arm/cortex-a code;
-* The _rt_hw_context_switch_interrupt/_rt_hw_context_switch is separated in TI DSP TMS320F28379D BSP (xuzuoyi);
-
-## Tool
-
-* Add Makefile generation feature in scons with command `scons –target=makefile -s`. Then developer can use make to build RT-Thread under Linux or Windows.
-* Add Eclipse project generation feature in scons with command `scons –target=eclipse -s`, which will put the necessary information in `.cproject` and `.project` files in current BSP folder. The developer can use Eclipse to build RT-Thread.
-* Fix the multi-group same name issue when generating Keil MDK project file and add a library file into the SConscript (Eric Qiang);
-* Fix the GCC Version Comparing issue
-* ENV version updated to v1.1.2
-  * Update scons version to 3.0.5
-  * Fix VC++ warning issue
-  * Fix Unicode error issue
-
-# RT-Thread v3.1.2 Change Log
-
-## Kernel
-
-* nothing
-
-## Components
-
-* When formatting the file system, adds FM_SFD option to create a volume in SFD format for FatFs; (HubretXie)
-* Add file system handle pointer in `struct dfs_fd' structure;
-* Fix stdio fd issue when POSIX api is used; (gbcwbz)
-* Fix the `fd_is_open()` issue: when the sub-path is the same in different mounted filesystem. 
-* Change the critical lock/unlock to dfs_lock/unlock in `getcwd()` function of DFS (the critical lock/unlock is different in SMP environment);
-* Fix the `aio_result` issue, which is returned by `aio_read_work` in AIO; (fullhan)
-* Fix the mmap issue when the addr parameter is NULL; (fullhan)
-* Modify the `_sys_istty` function in armlibc to correctly handle STDIN/STDOUT/STDERR; (gbcwbz)
-* Modify the `_write_r` function in newlib to correctly handle stdout.
-* Fix the at_socket issue when socket is a null pointer; (thomas onegd)
-* Fix the select event issue in `at_recvfrom()` function in at_socket;
-* Divide SAL into `sal_socket_ops/sal_proto_ops` and sal_proto_ops is implemented with gethostbyname/getaddrinfo ops etc.
-* Add socket TLS layer in SAL, that is, upper application can be supported by encrypted transmission without considering lowlevel TLS at all.
-* Fix the length issue of `ulog_strcpy`, which should be not exceed `ULOG_LINE_BUF_SIZE`;
-* Add the macro definition of hexadecimal log output to ulog; (HubretXie)
-* Add uTest component. The uTest is a unit test framework on RT-Thread, and can also be used for automatic testing on board with external Python scripts.
-* Fix some compilation warnings and enumeration mismatches in drivers/audio;
-* Fix the `can_rx/can_tx` issue, which is not cleared to NULL when CAN device is closed in drivers/can; (xeonxu)
-* Fix drivers/hwtimer, time acquisition issue with counting down mode;
-* Add drivers/adc driver framework;
-* Fix the tick compensation issue when enable interrupt too early; (geniusgogo)
-* Add `RT_SERIAL_USING_DMA` option in drivers/serial;
-* Add QSPI support in drivers/spi framework;
-* Add QSPI support in SFUD (based on the QSPI peripheral of stm32); SFUD is upgraded to version 1.1.0;
-* Optimize SPI take/release function call in spi_msd;
-* Fix the `blk_size` issue in `rt_rbb_blk_alloc()`;
-* Fix the FS USB issue in `_get_descriptor` function;
-* Fix the empty password issue in AP mode of drivers/wlan;
-* Fix the return type issue in drivers/wlan;
-* Remove the duplicate opening file check when open a file;
-
-# BSP
-
-* Change the name parameter to `cosnt char *` in `rt_hw_interrupt_install` function; (liruncong)
-* Fix `$` warning issue in Kconfig files of each BSP;
-* Add the LPC54114-lite BSP, including GPIO, I2C, SDCard, SPI, SPI Flash, UART driver;
-* Add Nuvoton-M487 BSP, including UART, EMAC driver; (Bluebear 233)
-* Fix the CAN driver issue in STM32F4XX-HAL BSP; (xeonxu)
-* Fix UART DMA settings issue in STM32F10x/STM32F40x BSP; (zhouchuanfu)
-* Fix the HEAP_BEGIN definition issue in STM32H743-Nucleo BSP; (nongxiaoming)
-* Fix GPIO configuration issue in stm32f10x-HAL; (Wu Han)
-* Change stm32f107 BSP as main function entry; (whj4674672)
-* Fix the serial interrupt handling issue in stm32f10x BSP;
-* Add PWM, RTC and watchdog drivers to stm32f10x-HAL BSP; (XXXXzzzz000)
-* Fix the watchdog driver issue in stm32f4xx-HAL BSP; (XXXXzzzz000)
-* Use lwIP version 2.x in stm32f40x/stm32f107 BSP.
-* Fix the link issue when enable CmBacktrace package in stm32f4xx-HAL BSP; (xeonxu)
-* Support Audio and microphones features in stm32f429-apollo BSP;
-* Enable dlmodule support in x86 BSP; (SASANO Takayoshi)
-* Addd uTest section in the link script of qemu-vexpress-a9/stm32f429-atk-apollo BSP for automatic testing;
-* Change the license to Apache License v2.0 in Godson 1C BSP; (sundm75)
-* Add the new BSP framework for STM32 serial chip, such as STM32 G0/F0/L0/F1/F4/F7/H7. In new BSP framework, the SoC drivers is reused. And in same time, lots of STM32 boards are supportted with new BSP framework:
-  * STM32F091-Nucleo Development Board BSP
-  * STM32F411-Nucleo Development Board BSP
-  * STM32L432-Nucleo Development Board BSP; (sun_shine)
-  * STM32F407-Discovery Development Board BSP
-  * STM32F446-Nucleo Development Board BSP; (andeyqi)
-  * STM32F746-Discovery Development Board BSP; (jinsheng)
-  * STM32F767-Nucleo Development Board BSP; (e31207077)
-  * STM32G071-Nucleo Development Board BSP;
-  * ATK STM32F103 NANO Development Board BSP
-  * ATK STM32F407 Explorer Development Board BSP
-  * ATK STM32F429 Apollo Development Board BSP
-  * ATK STM32F767 Apollo Development Board BSP
-  * ATK STM32L475 Pandora IoT Development Board BSP
-  * Fire STM32F103 Arbitrary Development Board BSP
-  * Fire STM32F429 Challenger Development Board BSP
-  * Fire STM32F767 Challenger Development Board BSP; (Hao Zhu)
-  * ArmFly STM32F429-v6 Development Board BSP
-  * STM32F103 iBox development board BSP; (dingo1688)
-  * Dofly STM32F103 Development Board; (FindYGL)
-  * STM32F107 uC/Eval Development Board BSP; (whj4674672)
-  * and more, there are more developers involved for stm32 BSP framework, they are HubretXie, Hao Zhu, e190, etc. to improve the STM32 public driver.
-* Add SWM320 BSP of Synwit.cn, including GPIO, HW Timer, I2C, Watchdog, PWM, RTC, SPI, UART, etc.; (provided and maintained by Synwit)
-* Add TI TMS320F28379D BSP, the first DSP chip supported on RT-Thread; (xuzhuoyi)
-* Fix USB driver issue in X1000; (Zhou YanJie)
-
-# Tool
-
-* Provide more inforamtion when the tool chain does not exist;
-* Add a draft Segger Embedded Studio project file generation command. Note that the tool chain in SES is a special version not the newlib.
-* Fix the IAR library link command issue when use scons command line under;
-* Fix the BSP path issue in scons `str(Dir('#'))`;
-* Add `scons --pyconfig-silent` command to add some Kconfig configurations and to generate `.config` and `rtconfig.h` files;
-* Update the `scons --dist` command to adapt to the new BSP framework;
-* Modify the mkromfs.py script. Fix the corresponding C code generation When the romfs contains empty files or empty folders;
-* Fix the issue of version string comparison issue for GNU GCC version in utils.py;
-* ENV updated to V1.1.0
-  * Provide better prompt information to improve user experience;
-  * Add `system32` path to environment variables to avoid the `cmd` command cannot be found;
-  * Add `PYTHONHOME` variable to environment variables to avoid PYTHON environment issue;
-
-# RT-Thread v3.1.1 Change Log
-
-## Kernel
-
-* Support the configuration of the upward growth stack which is defined by the `ARCH_CPU_STACK_GROWS_UPWARD` macro. Because there are fewer ARCH for stacks growing upward, this configuration item does not display directly in menuconfig. When a CPU ARCH needs stacks growing upward, the configuration of `ARCH_CPU_STACK_GROWS_UPWARD` can be selected by BSP Kconfig file in default.
-* Support for ARMCC V6 and later compiler (LLVM-based Compiler); currently it's mainly used in Keil MDK IDE. Please notes that the "Warnings" needs to use `Moderate Warnings` in project configuration in C/C++ (AC6) TAB; After using ARMCC v6, RT-Thread will add an additional `CLANG_ARM` macro definition; (liruncong, nongxiaoming, bernard)
-* The `RT_USING_IDLE_HOOK` configuration in Kconfig becomes a separate configuration item, not limited to `RT_USING_HOOK`; (geniusgogo)
-
-## Components
-
-* Improve the PWM driver framework and add more interfaces.
-* Fix the F_SETFL handling in ioctrl function; Fix the return value issue of fcntl function which is always 0 value.
-* Fix the memheap object type issue when creating a ramfs object.
-* Add power management framework for low power applications.
-* Add multi-segment support for read and write operations in MC/SDIO driver framework (for stm32, you can choose a separate stm32_sdio package); (weety)
-* Add ringblk_buf component for the block mode but in ringbuffer applications;
-* Improve WLAN management framework with unified interfaces, management, commands, to provide more friendly support to developers and users;
-* Add the conditional macro in the finsh when the MSH component is not enabled, even if the code files are compiled.
-* Remove gdbstub and move to rt-thread packages.
-* Upgrade and improve SAL and AT components: (linuxhan, eddylin83, slyant, luofanlu, Hubert Xie, Lawlieta, zhaojuntao, armink)
-  * Fix the none cleared issue when closing socket in SAL, which lead to the socket is always holding.
-  * Fix the `select()` issue for UDP communication in AT component. Add the receiving data handling to complete the clearing of received event;
-  * Add the errno value when receive data timeout in at_recvfrom function in the AT component.
-  * Add the receive data timeout handling in at_client_recv function in the AT component.
-* Fix a possible issue in fputc function implementation when using microlib;
-* Add gmtime_r implementation for ARMCC, IAR tool chain;
-* Improve time function support in IAR and support 64bit time; (hichard)
-* DHCPD's support for IPv6;
-* Remove lwIP-1.3.2 porting and add lwIP-2.1.0 porting; lwIP-2.0.2 is still the default version.
-* Add a lightweight ulog component and automatically replace the debug macro of the original rtdbg.h when it's enable.
-* USB stack update
-  * HOST, optimize the USB HOST timeout mechanism; fix the un-alignment visit issue in F4xx-HAL USB host driver;
-  * Device: Add the check when class drivers are illegally registered; Fix the un-aligned access issue in some platforms; optimize CDC VCOM classes, add the timeout mechanism and ID definition.
-
-## BSP
-
-* Upgrade the wlan adaptor to the new version of Wi-Fi management framework in amebaz BSP.
-* Add airkiss wifi configuration code to amebaz BSP.
-* Update Apollo2 BSP with ADC, GPIO, I2C, PDM, SPI, UART and other drivers; (Haleyl)
-* BeagleBone BSP is changed to main function mode, and adds Kconfig configuration file.
-* DM365 BSP adds Kconfig configuration file;
-* Update HiFive1 BSP and add more documentation.
-* Update imx6sx BSP to main function mode, and add Kconfig configuration file.
-* Change the old imxrt1052-evk BSP. The imxrt1052-related BSPs are classified into the `bsp/imxrt` directory; A touch framework is added to `bsp/imxrt`, and later will be moved into `components/drivers` directory;
-* Improve stm32f4xx-HAL BSP with PWM, I2C, USB Host driver; (XuanZe, xuzhuoyi)
-* Improve stm32f10x BSP with CAN driver and increase I2C driver; (wuhanstudio, AubrCool)
-* Improve stm32f10x-HAL BSP with I2C, IWG, PWM, RTC and other drivers, improve UART driver; (XuanZe)
-* Improve stm32f429-disco BSP and add I2C, LCD, Touch driver; (xuzhuoyi)
-* Improve x86 BSP, support dlmodule function; (SASANO Takayoshi, parai)
-
-## Tool
-
-* Modify the building script to support Python 3; <Python 3 patches have been submitted to scons and need to wait for next scons release，maybe scons-3.0.2> (Arda)
-* Add `scons --pyconfig` mode, which has a TK UI configurator; (weety)
-* Support for GNU GCC 7/8 version toolchains (The `-std=c99` is not added into C-compiler flags), but please note: PThreads component failed in 2.5 and new version of newlib.
-
-# RT-Thread 3.1.0 Change Log
-
-## Kernel
-
-* The main thread priority can be configured by Kconfig;
-* Add the checking of kernel object type, which can effectively avoid the problem of continuing to use kernel objects after they are destroyed.
-* Add the idle hook list to mount multiple idle hook, and can be configured by Kconfig.
-* Add the device_ops operation set to reduce the footprint of device object.
-* Remove the special memory operation in application module when using SLAB memory management algorithm.
-* Move application module from the kernel to `libc/libdl`.
-* Enhance the debug information output of `rtdbg.h` file.
-* In Keil/IAR tool chain, the `RT_USED` is used to keep symbols and avoid to add more argument or section in link phrase.
-
-## Components
-
-* Remove all of external codes, which will be moved to packages in the future.
-* Add initialization flag for shell, file system, network protocol stack etc to prevent repeated initialization;
-* Enable the long file name feature of ELM FatFs in default.
-* Change DFS FD to dynamic allocation mode. The maximum number of allocation is still DFS_FD_MAX.
-* Add dfs_fdtable_get() function to get different fdtable;
-* Add more DFS error messages, and provide easy to understand log when abnormal.
-* Fix the disk format issue of FatFs file system when multiple FatFs file systems are mounted.
-* Remove the folder enter feature in msh when input a folder name;
-* Add `int finsh_set_prompt (const char * prompt);` routine for setting a custom prompt for msh;
-* Add the VBUS configuration in Kconfig.
-* Move the application module from kernel to `libc/libdl` component;
-* Rewrite most of the management code for application module: replace the original object container with the object list; split the symbol resolution code into different processor architecture etc.
-* Update the application module chapter in the programming guide, and change it into dynamic module chapter.
-* Overwrite the exit() function of newlib to take over the processing of exit for a dlmodule.
-* Add SAL (Socket Abstraction Layer) component for adapting different protocol stacks and network implementations, and update the relevant sections of the programming guide;
-* Add AT component, including AT client, AT server and AT Socket function;
-* Remove the poll/select API of DFS_NET and move them to SAL component.
-* Remove the strong dependence of lwIP component for DFS_NET and replace it with Kconfig configuration in SAL.
-* Add the DHCP server function with lwIP raw API;
-* Fix the wait queue none-initialization issue in socket allocation of lwIP.
-* When a thread is about to block on a wait queue, fix the wake up issue for `rt_wqueue_wakeup' is executed to wake up that thread;
-* Add the PWM driver framework;
-* Fix the sdio_irq_wakeup release issue in the MMC/SD framework.
-* Fix the problem of DMA handling in the serial driver framework.
-* Update SFUD to v1.0.6 version;
-
-## BSP
-
-* Fix the SP issue when hard fault occurs for ARM Cortex-M arch;
-* Add C-Sky CK802 architecture porting;
-* Add Realtek amebaz WiFi SOC (rtl8710bn) BSP;
-* Update imxrt1052-evk firmware SDK to support B model chip.
-* Fix the copying packets issue in the Godson 1C BSP when sending message.
-* The Nuvoton m05x/m451 BSP are changed into the main() entry mode, and supports GCC compilation;
-* Fix the inconsistency issue between touch range and LCD resolution in qemu-vexpress-a9.
-* Add qemu-vexpress-gemini BSP for dual core A9 (RT-Thread + Linux) arch;
-* Add the basic porting for Raspberry Pi 2B ;
-* Add CAN and PWM drivers in stm32f4xx-HAL BSP;
-* Optimize the GPIO driver in stm32f4xx-HAL BSP;
-* Add UART3 driver in stm32f4xx-HAL BSP;
-* Fix the I2C1 driver clock in stm32f10x BSP and WDG control interface.
-* Add rt_hw_us_delay interface in stm32f10x-HAL BSP;
-* Optimize the GPIO driver in stm32f10x-HAL BSP;
-* Add GPIO driver and RTC driver in stm32f107 BSP;
-
-## Tool
-
-* ENV update to v1.0.0 final version.
-* ENV added the China mirror for software package, which can speed up the software package download, update  etc.
-* Fix the ENV known bugs and enhance the interaction with users.
-* Add building script to detect the version of GCC & newlib;
-* Add building script to detect the version of armcc;
-* Add `scons --dist` function to make distribution for a BSP.
-* Add `scons - dist - strip' function to make a minimal files of distribution for a BSP.
-* Add `ASFLAGS/LOCAL_ASFLAGS' parameters for defined a group and pass them to assembler;
-* Fix some errors in building script under the Linux environment.
-* Add the C-Sky CDK IDE project generation.
-* Add `scons --target=vsc -s` to generate friendly configuration files for VSCode;
-
-# RT-Thread 3.0.4 Change Log
+Change log since v3.1.3
 
 ## Kernel
 
-* Change the location of hook invoking in rt_event_send, which can better reflect the event value to the system view.
-* Fix the rt_realloc() issue in memheap;
-* Fix the vstart_addr issue in the dynamic library.
-* Ensure that signal is more standardized and remove si_errno members from siginfo_t;
-* Add rt_thread_mdelay() API for millisecond delay in thread.
-
-## Components
-
-* Fix the DFS mkfs issue of FatFs (which is a merge issue introduced in RT-Thread V3.0 upgrade).
-* Fix dfs_net poll issue, if there is already received data, the upper layer can not wake up and deal with data.
-* Fix the socket issue in dfs_net if lwip_socket failed(Bluebear233);
-* If the dfs_net/socket feature is used within lwIP 1.x version, a compiler error will be returned.
-* Fix the DFS df() information issue;
-* Fix the audio device write issue while the interrupt is not properly recovered.
-* Fix the one-shot timeout issue in the hardware timer driver framework.
-* In ENC28J60 driver, the "link change interrupt" is enable in initialization.
-* Fix the data issue in put data into ringbuffer.
-* Add UDP information display in netstat command;
-* Fix the USB HS issue when sending 1 bytes of data will cause two times of transmission.
-* Change the registration mechanism of USB Class Driver and Class Driver can be registered in package.
-* Add USB Device driver framework for HS USB.
-* Enhance the compatibility of time() function for different compilers;
-* Add more configuration items for DHCPD in menuconfig.
-
-## BSP
-
-* Temporarily remove the Andes AE210P transplant because of the mistakenly use SVC for context switching.
-* Add SD/MMC drive in Allwinner ARM9 BSP;
-* Add SPI and SPI Flash drivers to Allwinner ARM9 BSP.
-* Add GD32's gd32303e-eval development board support;
-* gd32450z-eval supports GNU GCC compilation;
-* Rewriting the hifive1 board level support package for the risc-v architecture;
-* About i.MX RT1052, we have completed various development board support: ATK, Fire, seeed studio;
-* On i.MX RT1052, add the cache-ops functions;
-* On i.MX RT1052, add I2S driver and WM8960 codec driver support;
-* Improve ETH driver support (including support for Fire development board) on i.MX RT1052.
-* Add Hardware Timer driver support on i.MX RT1052.
-* On i.MX RT1052, add GPIO driver;
-* On i.MX RT1052, add RTC driver;
-* On i.MX RT1052, improve SD/MMC driver;
-* On i.MX RT1052, add SPI driver and SPI Flash driver (connect to SFUD component);
-* Add USB Device driver on i.MX RT1052.
-* Add README files and KConfig files in LPC408x BSP;
-* Add README documents in LPC5460x-LPCXpresso BSP;
-* Add the display controller driver (Sundm75) in Godson 1C BSP.
-* Add CAN driver in Loongson 1C BSP(Sundm75);
-* In GPIO driver of Loongson 1C BSP, add (external) interrupt feature (Zhuangwei);
-* Use SPI automatic initialization in Loongson 1C BSP.
-* Add I2C driver in Loongson1C BSP(Sundm75);
-* Add resistive touch screen driver in Loongson 1C BSP(Sundm75);
-* In Loongson 1C BSP, the components initiliazation and main function is enable(Zhuangwei).
-* Add self bootup in Loongson1C BSP (Zhuangwei);
-* Add README files and KConfig files to Loongson 1C BSP(Zhuangwei).
-* Fix the rx descriptor issue in init_rx_desc function in NUC472 BSP (Bluebear233);
-* Add AC97 Audio driver in QEMU-VExpress-A9 BSP;
-* Add README description file in QEMU-VExpress-A9;
-* Add I2C driver in stm32f4xx-HAL BSP, and README description file;
-* Add cache-ops in stm32f7-disco BSP, and README description file;
-* Add README description file in stm32f10x/stm32f10x-HAL;
-* Add README specification files and KConfig configuration files in stm32f40x BSP;
-* Add KConfig configuration file in stm32f20x BSP;
-* Add README description file to stm32f411-nucleo BSP and enable GNU GCC tool chain support;
-* Add GPIO driver and README description file in stm32f429-apollo BSP;
-* Add KConfig configuration files in stm32f429-armfly BSP;
-* Add README description file in stm32l476-nucleo BSP;
-* Because V2M-MPS2 does not support in 32-bit machine simulation operation, temporarily remove this BSP.
-* Add README description file and some firmware file, such as u-boot.bin, wifi firmware etc, in X1000 BSP;
-Tools
-* Add detection feature for the version of GNU GCC tool chain and libc function feature.
-* Add the function of VSCode editor assistance, and support scons --target=vsc -s under BSP folder to generate configuration files for VSCode.
-* Add the detection of verson of IAR;
-* Add the ProjectInfo (Env) function to get information about target: all source files should be compiled, all header files, all macro definitions, the search paths for header file etc.
-
-# RT-Thread 3.0.3 Change Log
-
-## Kernel
-
-* Add scheduler protection when do cleanup for a detached thread;
-* Fix the object_find issue when enable module feature;
-* Improve POSIX signal support and add rt_signal_wait function and POSIX sigwait interface;
-* When enable finsh shell, rtthread.h header file includes the API file of finsh. Therefore, the application code can use command export feature without finsh.h file;
-* Improve the comments of rtdbg.h file. In RT-Thread, just use following code to add debug log feature:
-
-```c
-    #define DBG_ENABLE
-
-    #define DBG_SECTION_NAME    "[ MOD]"
-    #define DBG_LEVEL           DBG_INFO
-    #define DBG_COLOR
-    #include <rtdbg.h>
-```
-
-When close the DBG_ENABLE definition, the debug log will be closed. Otherwise, the `dbg_log(level, fmt, ...)` can be used to print debug information. 
-
-DBG_SECTION_NAME - The prefix information for each log line;
-DBG_LEVEL - The debug log level;
-DBG_COLOR - Whether use color log in console.
-
-## Components
-
-* Fix the flag issue of fopen in GNU GCC;
-* Fix the pthread_detach issue when used for a detached pthread;
-* Fix the _TIMESPEC_DEFINED issue in IAR 8;
-* Add libc_stdio_get_console() interface for returns the fd of console;
-* Move UI engine component as a standalone package;
-* Add a unify TF/SD card driver on SPI device bus;
-* Add soft-RTC device, therefore device can synchronize with network time and maintains the time with OS tick later;
-* Change the open/fcntl/ioctl API to POSIX standard  interface;
-* Fix ramfs issue when update with RTT 3.0.x;
-* Fix the elm fatfs umount issue; (liu2guang)
-* ignore the O_CREAT flag when open a device file;
-* Improve VCOM class driver in USB stack; (ChunfengMu, Aubr.Cool)
-
-## BSP
-
-* Fix the potential issue when enable Cortex-M hardware FPU;
-* Add v2m-mps2 bsp, which is used in Keil MDK5 for Cortex-M4/M7/M23/M33 simulation;
-* Add sdcard driver for stm32f10x-HAL;(liu2guang)
-* Improve GNU GCC support for stm32f10x-HAL;(Xeon Xu)
-* simulator bsp can be used in Windows/Visual C++ and update SDL to v2.0.7;
-* Add gk7102 bsp by gokemicro;(gokemicro)
-* Add allwinner F1C100s ARM9 bsp;(uestczyh222)
-* Fix some issues in peripherals drive library of NXP LPC54608/i.MX RT; (Valeriy Van)
-
-## Tools
-
-* scons building script will automatically add `_REENT_SMALL` macro when enable newlib nanao;
-* Modify building script for Python 3.x and scons 3.0
-
-# RT-Thread v3.0.2 Change log
-
-## Platform
-
-* Make sure the Object_Class to a fixed value
-* Add `rt_device_create/destroy` API
-* Add memory trace for small memory management algorithm for memory leak and overwritten.
-* Add a first version of asynchronous I/O API
-* Add cputime for high resolution counter
-* Add pipe device functions in DeviceDrivers
-* USB Host available in stm32f4 with mass storage class
-* Add 'df' command in msh
-* Update UI engine and add an example
-* Split `clock_time` from pthreads and add a new clock id: `CLOCK_CPUTIME_ID`
-* Enable IPv6 in lwIP 2.0.2 version
-* Add memlog in logtrace
-* Fix closesocket issue in dfs_net
-* Fix IPv6 issue in NFS
-* Update JFFS2 file system with new DFS API
-* Fix the issue of stat "/.." of lwext4 (parai)
-* Fix the fs type search issue in mkfs
-* Fix the select issue in dfs_net
-
-## Tools
-
-* scons: add '--useconfig' command to use an exist config file
-* scons: force to use g++ for link when enable `RT_USING_CPLUSPLUS` in GNU GCC configuration
-* Enable package feature in Linux/MacOS host
-
-## BSP
-
-* Add NUC472 bsp (bluebear)
-* Update SD/MMC driver for qemu-vexpress-A9
-* Add keyboard/mouse driver for qemu-vexpress-a9
-* Add ADC/I2C/Flash/PWM/RTC/smbus/SPI driver for apollo2 (Haleyl)
-* Add I2C/LCD/Touch driver for i.MXRT1052-EVK
-* Update SD/MMC driver for mini2440 (kuangdazzidd)
-* Update simulator to adapt VC++ compiler
-* Add USB host driver in stm32f4xx-HAL (uestczyh222)
-* Update EMAC driver for IPv6 in stm32f40x/stm32f107
-* Add stm32h743-nucleo bsp (polariss)
-
-# RT-Thread v3.0.1 Change log
-
-## Platform:
-
-* Add mmap()/munmap() API for POSIX compatibility.
-* Fix the filesystem_operation_table issue.
-* Enhance USB stack for USB slave (HID/ECM/RNDIS/WINUSB or composite device);
-* Enhance USB stack for USB host (HID/MSC etc);
-* Fix memory leak issue when close a pipe.  
-* Fix the romfs open issue;
-* Add SoftAP device in Wi-Fi framework;
-* Re-order the lwIP/ETH initialization;
-* Add IPv6 options in Kconfig;
-* Fix the module_id issue in _rt_thread_init;
-
-## Tools:
-
-* Add menuconfig for Linux/Mac platform: use `scons --memuconfig` to enable it;
-* Add LIBS feature for IAR project;
-
-## BSP:
-
-* Enhance LPC54608 BSP for kinds of compiler;
-* Add GPIO/I2C/SPI driver for Loongson 1C;
-* Add csd cmd in sdcard driver of mini2440;
-* Add SDIO/EMAC driver for qemu-vexpress-a9 bsp;
-* Enable VC++ to compile simulator bsp;
-* Add stm32f4xx-HAL bsp for kinds of STM32F4 series <User can use menuconfig to select chip>;
-* Fix the PHY reset in stm32f429-apollo bsp;
-* Add Audio/MMC/SLCD/Touch/USB slave/RTC/SPI/SFC Flash driver in Ingenic X1000 bsp;
-
-# RT-Thread v3.0.0 Change log
-## Platform:
-
-* Add more POSIX features, for example poll/select, signal, termios etc.
-* Add waitqueue for poll feature.
-* Use fops for file operation. There are two ways to visit device object: rt_device_* API, the file API(open/read/write/close etc).
-* Change the type of cmd from uint8_t to int in control interface.
-* Add more C++ object for RT-Thread Kernel Object.
-* Add wlan driver framework for wlan device operation.
-* Integrate SFUD into RT-Thread to unify the operations of spi flash.
-* Update lwIP to v2.0.2 version.
-
-## Tools:
-
-* Enable packages, with ENV tool.
-* menuconfig & Kconfig.
-* Add scons --dist for make a distribution for specified BSP.
-
-## BSP:
-
-* more MCU porting.
-
-## IoT:
-
-* put more IoT components as packages, for example, MQTT, CoAP, HTTP, TLS etc.
-
-# RT-Thread v2.1.0 Change log
-
-This release is the final release for RT-Thread v2.1.0 branch. This release has been delayed many time. After committed fh8620 and x1000 bsp, we are proud to announce this branch release of the official version.
-
-The change log since last stable version:
-
-## Kernel:
-
-* Move the init component to the kernel.
-* Fix the device open flag issue.
-* Add assertion hook.
-* Better application module support.
-* Does not lock scheduler when invoking soft-timer timeout function.
-
-## Board Support Package:
-
-* fh8620, which is provided by Shanghai Fullhan Microelectronics Co., Ltd. It's a IP camera chip with ARM1176, 300MHz, 16KB I-Cache and 16kB D-Cache.
-* x1000 bsp. The CPU is a XBurst CPU 1.0GHz, MIPS-based, from Ingenic Semiconductor Co.,Ltd.
-* imx6sx bsp, only the Cortex-A9 core porting in the NXP i.MX6 solox. BTW, another full Kinetis series porting was created in rt-thread_fsl, which is maintained by NXP employee.
-* lpc5410x bsp, only the Cortex-M4 core porting.
-* ls1cdev bsp for Loogson1C board.
-* dm365 bsp.
-* nRF51822/nRF52832 bsp.
-* stm32f7-disco bsp, the first ARM Cortex-M7 porting in RT-Thread.
-* stm32f411-nucleo bsp.
-* Add IAR compiler support in beaglebone bsp.
-
-## Components:
-
-* Add more socket fd operators in DFS with a virtual lwIP file system ops.
-* Add CAN/Hardware Timer device drivers.
-* Fix the SDIO issue to support sdio wifi device.
-* Add eMMC support in SD/MMC device drivers;
-* Fix the NAT configured enter reset issue in lwIP NAT.
-* RTGUI come back, but as a UI engine for blend point/line/rect and bitmap etc.
-* Add nanopb porting, a small code-size Protocol Buffers implementation;
-* Add paho-mqtt porting, the Eclipse Paho MQTT C/C++ client for Embedded platforms;
-* Update freetype to 2.5.4 version.
-* Enhance msh for file operations.
-* Split the exported commands of finsh shell to a standalone section: ".rodata.name"
-
-# RT-Thread v2.1.0 beta版本更改说明
-
-## BSP部分
-
-* BeagleBone加入GPIO驱动；
-* 京微雅格M7，更新驱动库并改进EMAC驱动程序；
-* 新加入dm365移植（包括EMAC、GPIO、I2C、MMC/SD、SPI等驱动）；
-* LPC4088加入EMC、硬件定时器、CAN驱动；
-* 新加入龙芯1C，智龙v2开发板移植（包括多串口驱动）；
-* 更改mini2440移植为applications/drivers等的目录方式；
-* 更新simulator在MS VC++上的移植，处理好初始化代码工作，完善UART控制台驱动；
-* 新加入stm32f7-disco移植；
-* 在stm32f10x中新加入CAN驱动及应用代码示例；
-* 在stm32f40x中加入硬件定时器驱动，RTC驱动；
-* 调整stm32f107为新的串口驱动框架；
-
-## 组件
-
-* DFS的struct stat定义中移除st_blksize成员（可以兼容于VC++中的stat定义）；
-* 修正DFS中select实现的问题；
-* 修正DFS中文件操作出错、关闭时的fd处理问题；
-* 修正DFS中mkdir和lseek出错时的fd处理问题；
-* 修正lwIP中SYS_ARCH_PROTECT/SYS_ARCH_UNPROTECT保护的问题；
-* 增加CAN驱动框架；
-* 增加硬件定时器驱动框架；
-* SD/MMC驱动框架中增加eMMC支持；
-* 修正注册SDIO驱动时驱动关联的问题；
-* 修正串口驱动框架DMA发送时激活标志的问题；
-* SPI Flash驱动中加入对GD25Q spi flash芯片支持；
-* 增加paho-mqtt组件移植；
-* 增加msh的脚本执行能力，可以在msh下执行*.sh脚本；
-* 增加msh下的mkfs命令；
-* 修正在Linux Telnet下使用finsh shell回车符处理的问题；
-* 增加应用模块在使用armcc、gnu gcc编译器时的libc符号导出；
-* 在以太网网卡驱动框架中增加ETHIF_LINK_AUTOUP/PHYUP参数用于指定初始时的链路Up/Down状态；
-* 在组件初始化中导出log_trace组件；
-
-## 内核
-
-* 更改UNUSED/USED等更改成RT_UNUSED/RT_USED；
-* 链接时增加.rodata.name section，当空间资源受限时可以把它放到性能低的内存区域；
-* 完善IAR编译器下的组件自动初始化；
-* 增加rt_assert_hook，在触发断言时可以执行这个钩子函数；
-* 修正应用模块分散加载情况下的问题；
-
-## 工具
-
-* scons中定义Group时加入了本Group内的编译参数定义；
-* 修正了如果Group中即包含代码，也包含二进制库时，生成的Keil MDK工程文件有两个重名Group的问题；
-
-版本: RT-Threadv2.0.1及v2.1.0 alpha
-
-RT-Thread v2.0.1是2.0这个系列的bug修正版，而v2.1.0 alpha则是当前开发主干的一个技术预览版本，它给出了v2.1.0这个版本系列的技术预览情况，不建议用于实际产品中，因为它可能存在大量的一些bug。
-
-# RT-Thread v2.0.1更改说明
-
-*  IAR用的dlib，加入THREAD_SUPPORT 和 FILE_DESCRIPTOR的支持；
-*  修正finsh中echo回显模式的问题；
-*  修正USB host代码的编译错误；
-*  修正sensor框架回调函数的问题；
-*  修正pin设备注册时的设备名称问题；
-
-而v2.1.0 alpha这个技术预览版则沿着最初设定的roadmap技术路线进行，这其中主要包括：
-
-*  lwip更深度的集成：把它集成到RT-Thread的文件系统接口中，这样Linux/Unix下的一些socket网络应用能够更顺利的移植到RT-Thread上，也为以后可以应用到更多地方的select接口铺路。
-
-*  这部分是和RT-Thread发布本身无关，但也是这个版本系列设定的目标之一：开启一个云端集成开发环境的时代！云端会是什么样的，请用现代化的浏览器打开[CloudIDE](http://lab.rt-thread.org/cloudide/simulator/index.html)
-
-# RT-Thread 2.0.0正式版更改说明
-
-经历了大约1年的时间，RT-Thread v2.0.0的最终版本终于发布出来了。自这个版本开发以来，引入了多项功能、修改、增强等。感谢参与的诸位开发人员！
-以下是自v2.0.0 RC版本以来的详细更改记录。后续我还会给出v2.0.0版本自v1.2.x版本的主要不同、看点，以及给出下一个版本的roadmap规划。
-
-## 内核
+- update src from released rt-thread v3.1.5
+- update code style and license
 
-*  console以RT_DEVICE_FLAG_STREAM参数打开字符设备；
-*  在rt_memheap_free中加入更多的断言检查；
+## libcpu
 
-## 组件
+- add cortex-m23 
+- add cortex-m33 
 
-*  更新RW009驱动以支持Wi-Fi SoftAP模式（aozima）；
-*  修正sensor框架的一些问题，并加入C API接口（睿赛德服务公司提供）；
-*  加入MPU6050 sensor的代码（bernard, Coing）；
-*  加入BMI055 sensor的代码（Coing）；
-*  当未使能heap时，修正finsh/msh中list_memheap的问题；
-*  修正LIBC编译的警告；
-*  加入IAR dlib相关的移植，使得应用能够使用标准的API接口；
-*  修正YMode握手时可能引起的竞争问题（grissiom）；
-*  更新FreeType版本到2.5.4
-*  单独把C++的全局对象初始化放到cplusplus_system_init函数中，并在初始化线程中调用；
-*  finsh中以RT_DEVICE_FLAG_STREAM参数打开字符设备；
-*  添加VBUS组件用于Linux与RT-Thread系统之间，RT-Thread与RT-Thread系统之间通信（睿赛德服务公司捐赠）；
-*  增加lwIP/NAT组件，可以做多个网口间的地址转换（Hicard）；
-*  增加lwIP/DHCP服务端，用于向客户端分配IP地址（睿赛德服务公司提供）；
+## components
 
-## BSP
-
-*  修正LPC4357串口驱动初始化时过早打开中断的问题（nongxiaoming）；
-*  重写LPC4357串口驱动，并让芯片上M4/M0核心分别都执行RT-Thread系统，两核心之间以VBUS组件进行系统间通信（睿赛德服务公司捐赠）；
-*  新增RX移植（limxuzheng）；
-*  新增NuMicro M051 Series移植，支持GCC、Keil MDK编译器（bright-pan）；
-*  新增LPC54102移植（Coing）；
-*  移除STM32F4 BSP中不需要的RT_TIMER_TICK_PER_SECOND配置（pangweishen）；
-*  在Linux Clang编译分析中，强制以32位模式进行编译（grissiom）；
-*  修正STM32F103中串口驱动中断过早打开的问题（armink）；
-
-## 工具
-
-*  增加scons中的MD5支持（bright-pan）；
-
-# RT-Thread 2.0.0 RC 更改说明
-
-发布时间:2014/11/4
-
-随着RT-Thread功能越来越多，如何发布版本也成为一件头疼的事情，因为需要仔细对比最近三个月来的修改记录。这次的发布距离上一次beta版本依然是三个月的时间，但按照发布计划已然推迟了一个月进行发布。 
-
-在这三个月中，开源社区上也发生了很多有趣的事情：
-
-阿嘉的使用RT-Thread的四轴飞行器毕业设计惊艳亮相，采用了1个STM32F4 + 8个STM32F1进行飞行控制，总计9个MCU的另类实现方式；沿循四轴飞行器的路线，与国内匿名团队合作，采用RW009 Wi-Fi控制的迷你四轴飞行器也在稳步推进过程中。
-
-RT-Thread做为一个开源组织参与的CSDN开源夏令营结出了丰硕的果实：
-由hduffddybz参与的IPv6协议栈移植（最新版本的lwIP-head版本移植）在这次发布中已经包括进来，从而能够在使用RT-Thread的小型设备上实现TCP/IP v4/v6双栈的支持；
-由wzyy2参与的GDB stub实现，也完美的支持BeagleBoneBlack开发板和STM32F4平台；
-CSDN开源夏令营其他的成果，例如bluedroid移植也有了初步的成果，希望能够在后续的版本（可能会是2.1.0系列版本？）包含进来。CSDN开源夏令营是一次非常棒的活动，能够让学生提前进入实战，了解软件开发的初步知识。对开源社区来说，也是一次非常有益的社区互动活动。希望明年这个活动可以继续，关注RT-Thread、嵌入式开发的同学可以关注明年的动向。
-
-当前智能化设备是一个备受关注的领域，针对这一领域的特点，RT-Thread也相应的做出了积极的响应，所以这个版本开始加入sensor的应用框架（APP/算法 <--> sensor framework <--> RT-Thread device driver <--> 硬件外设）。希望在小型化的RT-Thread操作系统基础上融合智能化相关的技术，让RT-Thread成为这方面可选的OS系统之一。RT-Thread操作系统的sensor框架也尝试新的实现方式，即采用C++的方式来实现（当然也会考虑C方面的兼容，无疑C++的面向对象特性会更好，所以最终选择了C++），在这个基础上也可能融合其他的一些生态技术，例如ARM mbed平台上的一些社区组件技术。所以这个发布版本中既包括sensor框架，也包括了C++底层的一些基础支撑。
-
-这个版本是RT-Thread 2.0.0系列正式版本的候选版本，正式版本预计会在年底正式发布，距离正式版本还会加入更完善的一些支撑（例如各种传感器驱动）。也计划2014年11月22日，在上海浦东举行RT-Thread嵌入式系统沙龙活动，欢迎大家关注并参与进行RT-Thread方方面面的技术交流。
-
-以下是这个版本的更改记录:
-
-## 内核
-
-* 修正当采用高级别优化编译时，idle任务中查询是否有僵尸线程的潜在bug；
-
-* 修正memory pool中的竞争问题；
-
-* 在console中打开设备时，加入流标志进行打开；
-
-## 组件
-
-* 加入C++基础支撑组件。C++组件依赖于RT_USING_LIBC库，当使用GCC编译器时请注意查看其中的说明文档并更改ld script；
-* 修正DFS中NFS打开目录的bug；
-* 更改DFS ROMFS默认romfs_root为弱化符号；
-* 添加DFS中dfs_file_lseek接口中关于fs的检查；
-* 移除I2C core中无用的core lock锁；
-* 添加sensor framework（采用C++的方式支持各种sensor）；
-* 修正serial框架中DMA发送的bug（heyuanjie87）；
-* 移除SPI框架中不必要的device初始化代码；
-* 完善SPI Wi-Fi网卡RW009驱动并提供RSSI相关的命令；
-* 修正MSH中未定义DFS_USING_WORKDIR时更改当前目录的bug；
-* 修正MSH中未定义RT_LWIP_TCP时依然定义了netstat命令的bug；
-* 修正MSH中未定义RT_USING_HEAP时依然定义了free命令的bug；
-* 修正finsh中FINSH_USING_HISTORY相关的裁剪；
-* 加入gdb stub组件，当前支持ARM Cortex-A8和Cortex-M3/4（wzyy2）；
-* 统一不同编译器下使用LIBC的宏为RT_USING_LIBC，原有的宏定义RT_USING_NEWLIB/RT_USING_ARM_LIBC需要从rtconfig.h中移除，并替换成RT_USING_LIBC；
-* 加入最新的lwIP分支：lwip-head，以提供IPv4/v6双栈的功能（hduffddybz）；
-* YMode中打开串口设备时，添加open flag（armink）；
+- add device.c
 
 ## bsp
 
-* 加入北京京微雅格的M7（华山）低功耗FPGA的ARM Cortex-M3移植（aozima）；
-* 加入北京京微雅格的M7 EMAC以太网驱动（aozima）；
-* AT91SAM9260分支中更改RT_USING_NEWLIB为RT_USING_LIBC；
-* BeagleBoneBlack分支中加入gdb stub支持（wzyy2）；
-* LPC176x分支中加入C++支持；
-* LPC176x分支中修正SD卡驱动返回卡信息的bug；
-* 修正LPC408x分支中GCC编译时的问题；
-* LPC408x分支中加入C++支持；
-* 龙芯1B分支中加入UART3驱动；
-* 加入飞索半导体的MB9BF568 FM4分支移植（yangfasheng）；
-* mini2440分支中更改RT_USING_NEWLIB为 RT_USING_LIBC；
-* stm32f0x分支中移除不同编译器下的LIBC定义，统一更改为RT_USING_LIBC；
-* stm32f0x分支中加入串口接收溢出中断处理（armink）；
-* stm32f40x分支中加入gdb stub支持并添加UART6驱动（wzzy2）；
-* zynq7000分支中更改RT_USING_NEWLIB为RT_USING_LIBC；
-* 加入ARM Cortex-M4芯片指令级的ffs实现；
-* 修正MB0BF618S分支中缺少timer初始化的bug（mike mao）；
-
-## 工具
-
-* 移除Python 2.6中未支持的语法（xfguo）；
-* 移除Windows平台中的startupinfo信息（对Python版本兼容性更好）；
-* 修正CPPPATH被打乱的bug；
-
-# RT-Thread 2.0.0 Beta更改说明
-
-发布时间:2014/8/1
-
-v2.0.0这个版本系列是RT-Thread当前的开发分支，如果要上新项目，建议使用这个版本来进行，预计这个版本的正式版会在年底发布。欢迎对这个版本进行测试、并反馈问题，能够早日进入到稳定版。
-
-v2.0.0版本的开发相对活跃些，开源社区提供了强有力的支持：如Arda贡献的TM4C129x移植，Romeo贡献的frdm-k64f移植，xiaonong的LPC4300移植等，以及睿赛德服务公司捐赠的Zynq7000移植，MB9BF618S移植，以及SPI WiFi网卡的驱动代码等。
-
-更改记录
-
-## 内核
-
-* 移除rt_device_init_all()函数：在系统启动时不需要再调用这个函数来初始化驱动，而是由上层应用执行rt_device_open时自动进行设备初始化；
-* 修正设备对象引用计数在打开设备失败依然递增的问题；
-* 增加WEAK宏用于定义/声明弱符号；
-* 在执行静态内存块分配前，重置线程的errno；
-* 修正timer未打开调试选项时，无用的静态函数定义（导致编译警告）；
-* 启动timer前，对timer进行强制移除；
-* 在执行soft timer超时函数时，打开调度器锁；
-* 新增块设备的自动刷新参数，RT_DEVICE_CTRL_BLK_AUTOREFRESH；
-
-## 工具
-
-* 修正scons命令编译时，选择keil mdk (armcc)编译器时，命令行太长编译失败的问题；
-
-## 移植
-
-* 移除rt_device_init_all()相关的调用；
-* 根据串口框架调整相关的驱动代码；
-* 新增frdm-k64f移植（FreeScale K64芯片）；
-* 移除K60Fxxxx移植；
-* 新增LPC43xx移植（NXP LPC4357芯片）；
-* 移除LPC176x中的组件初始化配置；
-* 修正龙芯1B移植（ls1bdev）中链接脚本关于组件初始化部分的配置；
-* 修正STM32F40x中UART3的配置；
-* 修正STM32F40x中GNU GCC连接脚本中ROM/RAM大小的配置；
-* 移除STM32F107中的组件初始化配置；
-* 增强STM32F107 EMAC驱动性能，同时加入自动查找PHY芯片地址功能；
-* 重写xplorer4330（NXP LPC4330芯片）移植（xiaonong完成）；
-* 新增Zynq7000 ARM Dual Cortex-A9移植；
-* 新增MB9BF618S移植；
-* 新增tm4c129x移植，并加入相应的EMAC以太网驱动；
-
-## 组件
-
-* DFS: 新增根据设备对象获得其上装载文件系统路径的函数：dfs_filesystem_get_mounted_path(struct rt_device* device);
-* DFS: 修正readdir在GNU GCC下的编译警告；
-* DeviceDrivers：新增workqueue实现；
-* DeviceDrivers: 修正USB Device栈中的一些拼写错误；
-* DeviceDrivers: 重写serial框架，能够让串口设备驱动同时支持三种模式：poll、interrupt、DMA。模式选择需要在执行rt_device_open时，由open flags指定；
-* DeviceDrivers: 加入更多的SPI设备驱动，例如RW009的SPI WiFi网口驱动（2.4G 802.11 b/g/n，WEP/WPA/WPA2，SoftAP/Station），SPI NorFlash块设备驱动，ENC28J60以太网网卡驱动；
-* Finsh: list_device()命令中增加refcount的信息；
-* Finsh: 修正'0'零常量无法识别的错误；
-* Finsh: mv命令，实现把一个文件移动到一个目录中；
-* Finsh: ifconfig命令支持对一个网络接口的基本配置；
-* Finsh: 新增netstat命令，用于显示当前系统中TCP连接的状态；
-* Finsh: 修正当命令行太长导致的缓冲区移除的问题；
-* libc: 修正arm libc中未使用DFS时的编译警告；
-* libc: 修正newlib中使用DFS时的系统调用编译警告（GNU GCC下）；
-* lwIP 1.4.1: 默认打开LWIP_SO_SNDTIMEO以支持连接发送超时；
-* lwIP 1.4.1: 修正MEMP_NUM_TCP_SEG定义错误的问题；
-* lwIP 1.4.1: 加入RT_LWIP_REASSEMBLY_FRAG选项定义以支持IP分组及合并；
-* lwIP 1.4.1: ethnet网络接口支持定义LWIP_NO_TX_THREAD/LWIP_NO_RX_THREAD，以关闭etx/erx线程；
-* lwIP 1.4.1: 用户可以重新定义RT_LWIP_ETH_MTU，以修改网络中的MTU值；
-* lwIP 1.4.1: 修正LWIP_NETIF_LINK_CALLBACK条件编译的问题；
-* lwIP 1.4.1: 完善移植相关的注释；
-* log trace: 增加log_session_lvl接口；
-* log trace: log trace中的session引用更改成常量形式；
-* ymodem: 增强数据接收的稳定性；
-
-# RT-Thread 2.0.0 Alpha更改说明
-
-发布时间:2014/4/8
-​	
-RT-Thread 2.0.0分支的第一个技术预览版本，仅用于展示2.0.0发展分支的演化动向(按照roadmap，2.0.0这个分支会有一部分RT-Thread和Linux互补性的技术，为Linux增加更好的实时性，为RT-Thread增加更多的功能性，这份技术预览版正是朝着这个目标而努力)，欢迎反馈建议和问题。
-
-## 组件
-
-* msh： bugfix 和功能性增强。新的 msh 在调用外部模块方面更加方便。
-* DFS： nfs 的 bugfix 和内置命令的增强。ELM FatFS加入对扇区不匹配情况下的信息输出，这样能够及时定位问题。
-* JS：新添了轻量级Javascript引擎，可以在RT-Thread中直接运行javascript脚本。
-* VMM：可以在qemu中运行的 Virtual Machine Module 组件。暂时只支持 realview-pb-a8 的 bsp。
-* CMSIS：版本更新至 3.20
-* drivers：USB 协议栈的重构。新的框架中编写驱动变得更加容易了。
-
-## BSP
-
-* beaglebone：串口驱动更新
-* realview-a8：添加了 VMM 组件
-
-## 工具
-
-* 固件加入scons --target=ua -s，用于准备用户应用环境；
-
-[发布后记]
-
-RT-Thread 2.0.0. Alpha版本相比于RT-Thread 1.2.1，新的特性主要有两部分：
-- RT-Thread + Linux双系统，这部分以RealView-A8处理器(ARM Cortex-A8单核)为蓝本，给出一个简单的双系统并行运行的demo；在没有硬件的环境下，可以使用QEMU软件虚拟方式的执行。这个链接中包含一个编译好的Linux及RT-Thread二进制包，可以直接下载进行体验。
-
-目录中有 Linux 的内核镜像 zImage，ramdisk rootfs.cpio.gz。可以用
-qemu-system-arm -M realview-pb-a8 -kernel zImage -initrd rootfs.cpio.gz -serial vc -serial vc
-来启动。启动之后 Linux 的控制台在第一个串口上(Atl + Ctrl + 3)，可以直接无密码以 root 用户登录。登录之后加载内核模块：
-insmod rtvmm.ko
-来启动 RT-Thread。RT-Thread 启动之后控制台在第二个串口上(Atl + Ctrl + 4)。第一个串口Linux shell依然可以使用，第二个串口则是RT-Thread的shell。
-- JavaScript解析器，这个是由牛头哥移植的，可以在一个非常小资料的MCU上以JavaScript脚本方式进行编程、开发。根据这种方式，也提供了RN001JS的以太网硬件模块：以JavaScript脚本语言作为二次开发，提供在线web(即WebIDE)进行编程并运行JavaScript程序。JavaScript作为一门轻量级、解释型的语言，更容易上手，配合WebIDE、及提供的一些example可以使得开发变得非常的轻松，也包括一些传感器的JavaScript例子，让做网页的人也可以玩硬件了！
-
-# RT-Thread 1.2.1更改说明
-
-发布时间: 2014/4/8
-​	
-在原有的1.2.0版本的bug修正版本，也是1.2.0系列的第一个修正版本，原则上不添加任何的新功能，我们尽量会按照每个季度一个修订版本的方式推进。大家在使用的过程中有什么问题还请反馈给我们，这些问题很可能会在下个版本中修正！
-
-以下是更改记录：
-
-## 内核
-
-* 用户应用，增加用户应用命令行参数支持；
-* 在挂起一个任务时，把相应的定时器也关闭；
-
-## BSP
-
-* BeagleBone，加入更多串口驱动支持；
-* 移除BSP中rt_device_init_all函数调用，改成打开设备时自动进行初始化；
-* LPC176x，移除components初始化管理器；
-* LPC4088，修正LED驱动的问题；
-* STM32F107，移除components初始化管理器；
-
-## 组件
-
-* 文件系统，ELM FatFS加入对扇区不匹配情况下的信息输出，这样能够及时定位问题；
-* 文件系统，NFS网络文件系统修正相关的一些编译警告信息；
-* 文件系统，copy命令加入文件夹方式复制功能；
-* 文件系统，RAMFS，加入到components初始化管理器中；
-* 文件系统，ROMFS，用于转换文件的工具mkromfs.py，增加Linux主机的支持；
-* CMSIS更新到3.2.0版本；
-* 串口驱动框架加入serial->ops->control的调用；
-* 命令行系统，优化msh，支持用户应用的命令行参数；
-* 命令行系统，当使用msh时，默认使用msh >的命令行提示符；
-* TCP/IP协议栈，导出更多的lwIP接口给用户应用；
-* POSIX thread，修正了同时使用lwIP组件时的编译警告；
-* 第三方组件，加入TJPGD的移植，加入libpng的移植；
-
-## 工具
-
-* 固件加入scons --target=ua -s，用于准备用户应用环境；
-
-[发布后记]
-* RT-Thread携带了众多的BSP，不一定能够一一保证每个分支上把RT-Thread上相应的功能使用起来。所以针对这种情况，我们有一款评估用的硬件开发板：RealBoard 4088，在上面力求把一些相关例程都添加上，这样在一个基本的BSP基础上，可以对照着把其他的组件、功能添加进去；
-* RealBoard 4088使用的RT-Thread版本主要以RT-Thread 1.2.1版本为主。
-
-# RT-Thread 1.2.0正式版本更改说明
-
-发布时间: 2014/1/6 
-
-实现roadmap中提到的大部分内容
-​	
-1，文档方面已完成《RT-Thread编程手册》，同时还有论坛上jiezhi童鞋的《一起来学RT-Thread系列连载教程》
-2，BSP分支方面新增cortext-A8(beaglebone)，cortext-R4(rm48x50)，UNITY-2(SEP6200),lpc408x的移植
-3，组件方面：
-- 加入msh(类似linux shell的风格)，能够直接执行应用程序
-- 新增freemodbus 1.6.0的移植
-- 新增开源的嵌入式关系数据库SQLite 3.8.1的移植
-- 新增Ymodem协议
-- 默认使用lwIP 1.4.1
-
-下面是自RT-Thread 1.2.0 RC版本发布以来具体的变更履历：
-
-## 内核
-
-* timer.c - 使用跳跃表(skip list)实现系统定时器链表，并在bsp中的startup.c中重新加入定时器初始化函数rt_system_timer_init()
-* rtdebug.h - 新增宏定义RT_DEBUG_IN_THREAD_CONTEXT
-* idle.c - 在函数rt_thread_idle_excute()中一次清除所有的死线程
-* scheduler.c - 新增API rt_critical_level()返回调度器上锁次数
-
-## 移植
-
-* cortex-m0 - 修正 cortex-m0 GCC移植中hardfault的问题点
-* cortex-r4 - 在startup后释放IRQ堆栈空间
-* cortex-r4 - 按字节长度分配堆栈空间
-
-## BSP分支
-
-* 新增lpc408x移植
-* bsp/stm32f0x - 增加USART1，USART2驱动，支持finsh，支持组件初始化
-* bsp/simulator - 当RTGUI配置无效时打印错误信息
-* bsp/simulator - 默认情况下关闭RTGUI选项
-* bsp/simulator - 增加createdef.py文件来生成VS的def文件
-* bsp/simulator - 当使用VC++编译时去除_TIME_T_DEFINED的定义
-* bsp/xplorer4330 - 重命名文件Retarget.c为retarget.c,否则linux系统中编译会报错
-* bsp/xplorer4330 - 修正GCC编译链接时关于ENTRY的警告
-* bsp/rm48x50 - 新增GCC的移植
-* bsp/K60Fxxxx - 修正一个编译错误
-
-## 组件
-
-* dfs - 正确处理mkfs未实现的情况
-* dfs - 使用指针代替index变量
-* dfs - 在函数dfs_filesystem_lookup()将含义模糊的指针变量名称empty重命名为fs
-* dfs - 修正dfs_unmount问题点
-* dfs - 在设备打开错误时令挂载失败
-* dfs/elmfat - 令elmfatfs每次都检查扇区大小
-* net - 新增freemodbus 1.6.0的移植
-* finsh - 新增FINSH_USING_MSH_ONLY选项
-* finsh - 只有当shell设备为空时调用rt_console_get_device()
-* finsh - 修正FINSH_USING_SYMTAB未定义的错误
-* finsh - 重构control按键的处理
-* msh - 增加文件和路径名称自动补全的功能
-* msh - msh内增加执行module的功能
-* msh - msh内增加更多的命令
-* libc - 修正 _sys_read()/_sys_write()问题点
-* external - 增加开源的嵌入式关系数据库SQLite 3.8.1的移植
-* pthreads - 避免ESHUTDOWN重复定义
-* mtd_nand - 在MTD nand中增加更多的调试措施
-* mtd_nand - 修正操作MTD nand时起始块错误的问题
-* lwip-1.4.1 - 在lwIP内加入更多的RT-Thread选项设置
-* log_trace - 修正函数memmove()参数使用错误的问题
-* drivers/pipe - 增加一个control命令来获得pipe剩余的空间
-* drivers/serial - 如果读写长度为0，则立即返回
-
-## 例程
-
-* examples - 用rt_sem_control()中的RT_IPC_CMD_RESET命令rt_sem_trytake()来清除信号量
-* examples - 始终打印输出测试结果
-* examples - 在所有的测试结束后打印输出简报
-* examples - 在TC线程中清除变量_tc_stat的TC_STAT_RUNNING状态
-* examples - 重新实现loop功能，并新增finsh命令tc_loop
-* examples - 在tc_stop中增加延时，由原来的延时RT_TICK_PER_SECOND/2调整为10 * RT_TICK_PER_SECOND
-* examples - 在SConscript中判断TC如果被使能，在CPPPATH中增加TC路径
-* examples - 新增一个in-mem-log的例子
-* semaphore_priority.c - 在cleanup时释放信号量
-* heap_realloc.c - 检查调用realloc(ptr, 0)是否成功
-* thread_delete.c - tc线程的延时应该比tid2的延时长，保证其测试过程中正常运行
-* thread_delay.c - 放宽超时判断条件，因为当RT_TICK_PER_SECOND为1000时，容易产生1个tick的误差
-* semaphore_static.c - 放宽超时判断条件，因为当RT_TICK_PER_SECOND为1000时，容易产生1个tick的误差
-* semaphore_dynamic.c - 放宽超时判断条件，因为当RT_TICK_PER_SECOND为1000时，容易产生1个tick的误差
-
-其他：
-* 更新README.md
-	
-# RT-Thread 1.2.0RC更改说明
-
-发布时间: 2013/10/10/ 10:19
-​	 
-主要说明: 该版本新增ARM Cortex-A8的支持(BeagleBone)，新增UNITY-2内核的支持(SEP6200)，新增Ymodem协议。
-
-变更履历
-========
-
-[内核]
-
-* 修正rtdef.h中的拼写错误(_MSC_VER_ -> _MSC_VER)
-* 修正scheduler.c中的调试打印输出错误
-* ipc - 在函数rt_event_recv()中增加对参数option有效性的检查
-* device - 增加统计设备引用次数的变量ref_count
-* memheap - 修正内存块分割问题点
-* memheap - 优化函数rt_memheap_realloc()
-* kservice - 函数声明使用rt_vsnprintf代替vsnprintf
-
-
-[组件]
-
-* dfs - 修正dfs_file.c中一处变量参数类型错误的问题
-* dfs - 增加mount table
-* dfs - 在building脚本中加入ramfs的支持
-* dfs - 修正ramfs中O_APPEND write的问题
-* dfs/elm - 在mkfs中加入device_open/close
-* dfs/jffs2 - 修正jffs2_opn/opendir中的f_flag初始化问题
-* dfs/jffs2 - 修正jffs2卸载问题
-* pthread - 修正一处编译警告
-* drivers/pipe - 增加rt_pipe_init/rt_pipe_detach
-* drivers/pipe - 增加非阻塞读写和强制写模式
-* drivers/pipe - 当恢复读的时候调用函数rx_indicate()
-* drivers/pipe - 增加一个设备类型(pipe类型)
-* drivers/portal - 实现portal设备类型
-* drivers/ringbuffer - 修改一些模糊不清的函数名称
-* drivers/ringbuffer - 新增put_force和putchar_force接口函数
-* finsh - 当set_device时增加设备检查
-* finsh - 在rx_ind中增加对shell设备的自动设置
-* finsh - 增加pipe和portal设备的描述
-* finsh - 在变量定义时使用别名
-* finsh - 当关闭设备时注销rx_indicate
-* finsh - 修正命令行太长的问题
-* finsh/msh - 只有当DFS_USING_WORKDIR使能时才声明cd/pwd
-* init - 为新的组件初始化机制更新连接脚本
-* init - 增加组件初始化调试代码
-* logtrace - 整理代码，去除编译警告
-* logtrace - 增加LOG_TRACE_VERBOSE
-* logtrace - 调整log values
-* logtrace - 只有当finsh使能的时候才声明cmd
-* libc/minilibc - 在sys/time.h中增加gettimeofday的声明
-* utilities - 新增ymodem
-
-工具:
-
-* building.py - 增加clang静态缝隙器的支持
-* building.py - 为Keil MDK增加buildlib功能
-* building.py - 在clang-analyze中执行'clang -Wall -fsyntas-only'
-* clang-analyze.py - 增加一个定制工具实现clang静态分析
-
-分支:
-
-* 新增BeagleBone的移植
-* 新增SEP6200的移植
-* 新增K60Fxxxx的移植
-* 修正Linux中的编译错误(lm4f232, stm32f40x, xplorer4330)
-* cortex-m3 - 加强hard fault的异常处理函数
-* at91sam9260 - 更新串口驱动，使用组件中的通用串口驱动
-* at91sam9260 - 更新工程目录结构
-* at91sam9260 - 修正编译错误
-* at91sam9260 - 内嵌GPLv2许可
-* stm32f10x - 删除无用的文件
-* stm32f10x - 更新工程目录结构
-* stm32f10x - 更新工程文件
-* stm32f10x - 为使用新的组件初始化更新连接脚本
-* stm32f10x - 为使用新的组件初始化更新SD card驱动
-* stm32f10x - 为使用新的组件初始化更新DM9000驱动
-* stm32f10x - 更新串口驱动，使用组件中的通用串口驱动
-* stm32f10x - 修正rtgui初始化问题
-* simulator - 为使用新的组件初始化更新代码，以便支持mingw
-* simulator - 支持Linux系统
-* simulator - 修正Linux系统中的SDL初始化问题
-* simulator - 在rt_components_init之后初始化SDL
-* simulator - 将对SDL设置的内容移入drivers/SConstruct
-* simulator - 在env中获得CORSS_TOOL和EXEC_PATH的值
-* simulator - 支持clang-analyze
-* simulator - 增加tap netif driver
-
-//----------------------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------------------
-
-
-版本: RT-Thread 1.2.0 Beta 版本
-
-发布时间: 2013/6/30
-​		
-进过开发人员三个月的努力，RT-Thread 1.2.0 Beta 版本如期发布。
-该版本默认采用lwIP 1.4.1协议栈，USB device stack也进一步完善。加入 log_trace 子系统，加入组件初始化升级版本，加入 ARM Cortex-R 的移植。
-
-主要变化：
-
-* 1，新增组件初始化功能
-- 详情请看论坛帖子[新功能] 组件初始化
-* 2，支持ARM Cortex-R系列处理器
-- Grissiom 完成 ARM Cortex-R 的移植，目前BSP中已有TI RM48x50分支（仅支持TI CCS开发环境）
-* 3，文件系统中新增 RAMFS
-* 4，加入 log_trace 子系统
-* 5，优化Cortex-M4线程上下文切换，使用了浮点运算的线程才保存及恢复FPU寄存器
-- 详情请看论坛帖子[优化]cortex-m4f线程切换，优化FPU寄存器
-* 6，新增API rt_memheap_realloc()
-* 7，重新实现ringbuffer，采用镜像的方法区分“满”和“空”，同时支持任意大小的buffer
-* 8，内核中加入RT_KERNEL_MALLOC/RT_KERNEL_FREE/RT_KERNEL_REALLOC宏。
-如果用户未定义这些宏，将默认指向rt_malloc/rt_free/rt_realloc。
-同时内核仅局限于使用这些宏来使用动态内存
-* 9，在 building.py 中新增生成 cscope database 的选项
-* 10，USB组件新增reset函数，支持热插拔
-* 11，scons编译系统支持CCS开发环境
-* 12，USB组件新增状态信息（USB_STATE_NOTATTACHED，USB_STATE_ATTACHED，USB_STATE_POWERED...）
-
-修复问题点：
-
-* 1，USB组件HOST可以挂起endpoints
-* 2，simulator分支，修复 serial_write 问题
-* 3，udisk可以被弹出
-* 4，iar.py中修复绝对路径的问题
-* 5，dfs_fs.h内增加dfs_mkfs()函数的申明
-* 6，生成MDK工程文件的时候加入library文件
-* 7，当PC不再接受数据的时候，重置VCOM相应的状态
-* 8，USB组件：返回正确的LangID字符串长度给HOST
-* 9，Cortex-M0，Cortex-M3，Cortex-M4上下文切换时，回收系统初始化时用到的栈空间
-
-//----------------------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------------------
-
-//----------------------------------------------------------------------------------------
-
-
-
-版本: RT-Thread 1.2.0 Alpha版本
-
-发布时间: 2013/4/10
-​	
-遵循2013年RT-Thread roadmap，RT-Thread 1.2.0 Alpha版本发布，Alpha意味着此版本为技术预览版，仅用于展示RT-Thread 1.2.0未来的发展方向，并不适合于开发正式产品。RT-Thread 1.2.0版本是1.1.x系列的下一个分支，这个分支主要体现的是RT-Thread 1.x系列的文档情况。当然也有一些功能、代码方面的增强。
-
-伴随着新版本的到来，RT-Thread有几个重大的转变：
-1，代码托管从google code(SVN)迁移到github(GIT)
-2，RT-Thread与RTGUI区分开来，并成为两个独立的开发分支
-3，重视文档，将文档建设作为1.2.0版本的首要任务来抓
-
-内核主要变化：
-1，加入__rt_ffs函数用于实现32位整数中获取第一个置1的位；同时调度器中位图相关算法直接使用__rt_ffs函数；CPU移植时，可定义RT_USING_CPU_FFS，使用芯片指令完成。
-
-2，新的中断注册机制
-weety加入interrupt description功能，用于为interrupt增加更多的信息，同时中断服务例程也可以携带用户自定义的参数类型。
-* 这部分对ARM7、ARM9、MIPS等影响很大，需要对CPU移植做相应的一些修改。
-* 这部分对ARM Cortex-M系列芯片没有影响。
-
-3，调整定时器插入位置，为相同超时定时的后面。
-
-组件主要变化：
-1，添加lwIP 1.4.1。
-2，在finsh shell中加入module shell功能。finsh shell本身是一个C语言表达式的shell命令行，而module shell更类似于一个传统的命令行，由命令，参数等方式构成。
-
-分支主要变化：
-1，完善simulator分支，支持RTGUI，支持应用模块。
-2，完善at91sam9260分支的移植及驱动更新。
-
-编译系统主要变化：
-1，开启省略编译时长命令特性，如果需要查看编译时命令行，可以使用scons --verbose查看。
-2，加入生成CodeBlocks工程特性。
-3，修正当系统安装使用Keil MDK 4.6+版本的问题。
+- add samples for gd32e230k-msh
+- add samples for lpc55s69-blink
 
-github主要提交履历:
-5646189b29: elm fatfs支持mkfs，并且无需提前执行dfs_mount; mount/umount/mkfs操作也不会引起reset
-22786f8817: 允许用户自定义PID和VID
-0001344105: 更明确的定时器运行机制，如果两个定时器在同一个时刻发生超时，那么先开始的定时器先处理
-5d68ef8ec1: 修正使用64位GCC时编译finsh过程中发生错误的问题
-a4d661dcf1: 修正dfs_elm.c中一处内存泄露，并且在mount fatfs失败时执行 umount fatfs操作
-43228aeb9c: 修正list_tcps问题：ipaddr_ntoa不是可重入的函数。
-3de4b92a68: 修正AT91SAM9260分支中PHY link状态错误的问题。
-1abaa0492d

components/finsh/Kconfig

@@ -10,14 +10,6 @@ if RT_USING_FINSH
 config FINSH_THREAD_NAME
     string "The finsh thread name"
     default "tshell"
-config FINSH_USING_HISTORY
-    bool "Enable command history feature"
-    default y
-if FINSH_USING_HISTORY
-config FINSH_HISTORY_LINES
-    int "The command history line number"
-    default 5
-endif
 
 config FINSH_USING_SYMTAB
     bool
@@ -26,10 +18,6 @@ config FINSH_USING_SYMTAB
 config FINSH_USING_DESCRIPTION
     bool "Keeping description in symbol table"
     default y
-
-config FINSH_ECHO_DISABLE_DEFAULT
-    bool "Disable the echo mode in default"
-    default n
     
 config FINSH_THREAD_PRIORITY
     int "The priority level value of finsh thread"
@@ -43,22 +31,6 @@ config FINSH_CMD_SIZE
     int "The command line size for shell"
     default 80
 
-config FINSH_USING_AUTH
-    bool "shell support authentication"
-    default n
-
-if FINSH_USING_AUTH
-config FINSH_DEFAULT_PASSWORD
-    string "The default password for shell authentication"
-    default "rtthread"
-config FINSH_PASSWORD_MIN
-    int "The password min length"
-    default 6
-config FINSH_PASSWORD_MAX
-    int "The password max length"
-    default RT_NAME_MAX
-endif
-
 config FINSH_USING_MSH
     bool
     default y

components/finsh/SConscript

@@ -3,35 +3,11 @@ from building import *
 
 cwd     = GetCurrentDir()
 src     = Split('''
-shell.c
 cmd.c
+msh.c
+shell.c
 ''')
 
-fsh_src = Split('''
-finsh_compiler.c
-finsh_error.c
-finsh_heap.c
-finsh_init.c
-finsh_node.c
-finsh_ops.c
-finsh_parser.c
-finsh_var.c
-finsh_vm.c
-finsh_token.c
-''')
-
-msh_src = Glob('msh.c')
-
-if GetDepend('RT_USING_DFS'):
-    msh_src += ['msh_file.c']
-
-if not GetDepend('FINSH_USING_SYMTAB'):
-    src += ['symbol.c']
-if GetDepend('FINSH_USING_MSH'):
-	src = src + msh_src
-if not GetDepend('FINSH_USING_MSH_ONLY'):
-    src = src + fsh_src
-
 CPPPATH = [cwd]
 
 group = DefineGroup('finsh', src, depend = ['RT_USING_FINSH'], CPPPATH = CPPPATH)

components/finsh/cmd.c

@@ -1,6 +1,5 @@
-
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +26,7 @@
  * 2012-10-22     Bernard      add MS VC++ patch.
  * 2016-06-02     armink       beautify the list_thread command
  * 2018-11-22     Jesven       list_thread add smp support
- * 2018-12-27     Jesven       Fix the problem that disable interrupt too long in list_thread 
+ * 2018-12-27     Jesven       Fix the problem that disable interrupt too long in list_thread
  *                             Provide protection for the "first layer of objects" when list_*
  */
 
@@ -146,7 +145,7 @@ static rt_list_t *list_get_next(rt_list_t *current, list_get_next_t *arg)
             break;
         }
     }
-    
+
     rt_hw_interrupt_enable(level);
     arg->nr_out = nr;
     return node;

components/finsh/finsh.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

components/finsh/finsh_api.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

components/finsh/msh.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -297,7 +297,7 @@ int system(const char *command)
 
     return ret;
 }
-RTM_EXPORT(system);
+
 #endif
 
 static int _msh_exec_cmd(char *cmd, rt_size_t length, int *retp)
@@ -374,7 +374,7 @@ int msh_exec(char *cmd, rt_size_t length)
     int cmd_ret;
 
     /* strim the beginning of command */
-    while (*cmd  == ' ' || *cmd == '\t')
+    while ((length > 0) && (*cmd == ' ' || *cmd == '\t'))
     {
         cmd++;
         length--;

components/finsh/msh.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

components/finsh/shell.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -173,15 +173,21 @@ static int finsh_getchar(void)
     char ch = 0;
 
     RT_ASSERT(shell != RT_NULL);
-    while (rt_device_read(shell->device, -1, &ch, 1) != 1)
-        rt_sem_take(&shell->rx_sem, RT_WAITING_FOREVER);
 
-    return (int)ch;
+    if(shell->device)
+    {
+        while (rt_device_read(shell->device, -1, &ch, 1) != 1)
+            rt_sem_take(&shell->rx_sem, RT_WAITING_FOREVER);
+
+        return (int)ch;
+    }
+    else
 #endif
-#else
-    extern char rt_hw_console_getchar(void);
-    return rt_hw_console_getchar();
 #endif
+    {
+        extern char rt_hw_console_getchar(void);
+        return rt_hw_console_getchar();
+    }
 }
 
 #if !defined(RT_USING_POSIX) && defined(RT_USING_DEVICE)
@@ -844,7 +850,7 @@ int finsh_system_init(void)
     finsh_system_var_init(&__vsymtab_start, &__vsymtab_end);
 #elif defined(_MSC_VER)
     unsigned int *ptr_begin, *ptr_end;
-		
+
     if(shell)
     {
         rt_kprintf("finsh shell already init.\n");

components/finsh/shell.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

include/libc/libc_dirent.h

@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef LIBC_DIRENT_H__
-#define LIBC_DIRENT_H__
-
-#define DT_UNKNOWN           0x00
-#define DT_REG               0x01
-#define DT_DIR               0x02
-
-#endif

include/libc/libc_errno.h

@@ -1,206 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016-11-12     Bernard      The first version
- */
-
-#ifndef LIBC_ERRNO_H__
-#define LIBC_ERRNO_H__
-
-#include <rtconfig.h>
-
-#if defined(RT_USING_NEWLIB) || defined(_WIN32)
-/* use errno.h file in toolchains */
-#include <errno.h>
-#endif
-
-#if defined(__CC_ARM)
-/*
-defined in armcc/errno.h
-
-#define EDOM    1
-#define ERANGE  2
-#define EILSEQ  4
-#define ESIGNUM 3
-#define EINVAL  5
-#define ENOMEM  6
-*/
-#define ERROR_BASE_NO    7
-
-#elif defined(__IAR_SYSTEMS_ICC__)
-/* defined in iar/errno.h
-#define EDOM    33
-#define ERANGE  34
-#define EFPOS   35
-#define EILSEQ  36
-*/
-#define ERROR_BASE_NO    36
-
-#else
-
-#define ERROR_BASE_NO    0
-#endif
-
-#if !defined(RT_USING_NEWLIB) && !defined(_WIN32)
-
-#define EPERM            (ERROR_BASE_NO + 1)
-#define ENOENT           (ERROR_BASE_NO + 2)
-#define ESRCH            (ERROR_BASE_NO + 3)
-#define EINTR            (ERROR_BASE_NO + 4)
-#define EIO              (ERROR_BASE_NO + 5)
-#define ENXIO            (ERROR_BASE_NO + 6)
-#define E2BIG            (ERROR_BASE_NO + 7)
-#define ENOEXEC          (ERROR_BASE_NO + 8)
-#define EBADF            (ERROR_BASE_NO + 9)
-#define ECHILD          (ERROR_BASE_NO + 10)
-#define EAGAIN          (ERROR_BASE_NO + 11)
-
-#ifndef ENOMEM
-#define ENOMEM          (ERROR_BASE_NO + 12)
-#endif
-
-#define EACCES          (ERROR_BASE_NO + 13)
-#define EFAULT          (ERROR_BASE_NO + 14)
-#define ENOTBLK         (ERROR_BASE_NO + 15)
-#define EBUSY           (ERROR_BASE_NO + 16)
-#define EEXIST          (ERROR_BASE_NO + 17)
-#define EXDEV           (ERROR_BASE_NO + 18)
-#define ENODEV          (ERROR_BASE_NO + 19)
-#define ENOTDIR         (ERROR_BASE_NO + 20)
-#define EISDIR          (ERROR_BASE_NO + 21)
-
-#ifndef EINVAL
-#define EINVAL          (ERROR_BASE_NO + 22)
-#endif
-
-#define ENFILE          (ERROR_BASE_NO + 23)
-#define EMFILE          (ERROR_BASE_NO + 24)
-#define ENOTTY          (ERROR_BASE_NO + 25)
-#define ETXTBSY         (ERROR_BASE_NO + 26)
-#define EFBIG           (ERROR_BASE_NO + 27)
-#define ENOSPC          (ERROR_BASE_NO + 28)
-#define ESPIPE          (ERROR_BASE_NO + 29)
-#define EROFS           (ERROR_BASE_NO + 30)
-#define EMLINK          (ERROR_BASE_NO + 31)
-#define EPIPE           (ERROR_BASE_NO + 32)
-
-#ifndef EDOM
-#define EDOM            (ERROR_BASE_NO + 33)
-#endif
-
-#ifndef ERANGE
-#define ERANGE          (ERROR_BASE_NO + 34)
-#endif
-
-#define EDEADLK         (ERROR_BASE_NO + 35)
-#define ENAMETOOLONG    (ERROR_BASE_NO + 36)
-#define ENOLCK          (ERROR_BASE_NO + 37)
-#define ENOSYS          (ERROR_BASE_NO + 38)
-#define ENOTEMPTY       (ERROR_BASE_NO + 39)
-#define ELOOP           (ERROR_BASE_NO + 40)
-#define EWOULDBLOCK     EAGAIN
-#define ENOMSG          (ERROR_BASE_NO + 42)
-#define EIDRM           (ERROR_BASE_NO + 43)
-#define ECHRNG          (ERROR_BASE_NO + 44)
-#define EL2NSYNC        (ERROR_BASE_NO + 45)
-#define EL3HLT          (ERROR_BASE_NO + 46)
-#define EL3RST          (ERROR_BASE_NO + 47)
-#define ELNRNG          (ERROR_BASE_NO + 48)
-#define EUNATCH         (ERROR_BASE_NO + 49)
-#define ENOCSI          (ERROR_BASE_NO + 50)
-#define EL2HLT          (ERROR_BASE_NO + 51)
-#define EBADE           (ERROR_BASE_NO + 52)
-#define EBADR           (ERROR_BASE_NO + 53)
-#define EXFULL          (ERROR_BASE_NO + 54)
-#define ENOANO          (ERROR_BASE_NO + 55)
-#define EBADRQC         (ERROR_BASE_NO + 56)
-#define EBADSLT         (ERROR_BASE_NO + 57)
-#define EDEADLOCK       EDEADLK
-#define EBFONT          (ERROR_BASE_NO + 59)
-#define ENOSTR          (ERROR_BASE_NO + 60)
-#define ENODATA         (ERROR_BASE_NO + 61)
-#define ETIME           (ERROR_BASE_NO + 62)
-#define ENOSR           (ERROR_BASE_NO + 63)
-#define ENONET          (ERROR_BASE_NO + 64)
-#define ENOPKG          (ERROR_BASE_NO + 65)
-#define EREMOTE         (ERROR_BASE_NO + 66)
-#define ENOLINK         (ERROR_BASE_NO + 67)
-#define EADV            (ERROR_BASE_NO + 68)
-#define ESRMNT          (ERROR_BASE_NO + 69)
-#define ECOMM           (ERROR_BASE_NO + 70)
-#define EPROTO          (ERROR_BASE_NO + 71)
-#define EMULTIHOP       (ERROR_BASE_NO + 72)
-#define EDOTDOT         (ERROR_BASE_NO + 73)
-#define EBADMSG         (ERROR_BASE_NO + 74)
-#define EOVERFLOW       (ERROR_BASE_NO + 75)
-#define ENOTUNIQ        (ERROR_BASE_NO + 76)
-#define EBADFD          (ERROR_BASE_NO + 77)
-#define EREMCHG         (ERROR_BASE_NO + 78)
-#define ELIBACC         (ERROR_BASE_NO + 79)
-#define ELIBBAD         (ERROR_BASE_NO + 80)
-#define ELIBSCN         (ERROR_BASE_NO + 81)
-#define ELIBMAX         (ERROR_BASE_NO + 82)
-#define ELIBEXEC        (ERROR_BASE_NO + 83)
-
-#ifndef EILSEQ
-#define EILSEQ          (ERROR_BASE_NO + 84)
-#endif
-
-#define ERESTART        (ERROR_BASE_NO + 85)
-#define ESTRPIPE        (ERROR_BASE_NO + 86)
-#define EUSERS          (ERROR_BASE_NO + 87)
-#define ENOTSOCK        (ERROR_BASE_NO + 88)
-#define EDESTADDRREQ    (ERROR_BASE_NO + 89)
-#define EMSGSIZE        (ERROR_BASE_NO + 90)
-#define EPROTOTYPE      (ERROR_BASE_NO + 91)
-#define ENOPROTOOPT     (ERROR_BASE_NO + 92)
-#define EPROTONOSUPPORT (ERROR_BASE_NO + 93)
-#define ESOCKTNOSUPPORT (ERROR_BASE_NO + 94)
-#define EOPNOTSUPP      (ERROR_BASE_NO + 95)
-#define ENOTSUP         EOPNOTSUPP         
-#define EPFNOSUPPORT    (ERROR_BASE_NO + 96)
-#define EAFNOSUPPORT    (ERROR_BASE_NO + 97)
-#define EADDRINUSE      (ERROR_BASE_NO + 98)
-#define EADDRNOTAVAIL   (ERROR_BASE_NO + 99)
-#define ENETDOWN        (ERROR_BASE_NO + 100)
-#define ENETUNREACH     (ERROR_BASE_NO + 101)
-#define ENETRESET       (ERROR_BASE_NO + 102)
-#define ECONNABORTED    (ERROR_BASE_NO + 103)
-#define ECONNRESET      (ERROR_BASE_NO + 104)
-#define ENOBUFS         (ERROR_BASE_NO + 105)
-#define EISCONN         (ERROR_BASE_NO + 106)
-#define ENOTCONN        (ERROR_BASE_NO + 107)
-#define ESHUTDOWN       (ERROR_BASE_NO + 108)
-#define ETOOMANYREFS    (ERROR_BASE_NO + 109)
-#define ETIMEDOUT       (ERROR_BASE_NO + 110)
-#define ECONNREFUSED    (ERROR_BASE_NO + 111)
-#define EHOSTDOWN       (ERROR_BASE_NO + 112)
-#define EHOSTUNREACH    (ERROR_BASE_NO + 113)
-#define EALREADY        (ERROR_BASE_NO + 114)
-#define EINPROGRESS     (ERROR_BASE_NO + 115)
-#define ESTALE          (ERROR_BASE_NO + 116)
-#define EUCLEAN         (ERROR_BASE_NO + 117)
-#define ENOTNAM         (ERROR_BASE_NO + 118)
-#define ENAVAIL         (ERROR_BASE_NO + 119)
-#define EISNAM          (ERROR_BASE_NO + 120)
-#define EREMOTEIO       (ERROR_BASE_NO + 121)
-#define EDQUOT          (ERROR_BASE_NO + 122)
-#define ENOMEDIUM       (ERROR_BASE_NO + 123)
-#define EMEDIUMTYPE     (ERROR_BASE_NO + 124)
-#define ECANCELED       (ERROR_BASE_NO + 125)
-#define ENOKEY          (ERROR_BASE_NO + 126)
-#define EKEYEXPIRED     (ERROR_BASE_NO + 127)
-#define EKEYREVOKED     (ERROR_BASE_NO + 128)
-#define EKEYREJECTED    (ERROR_BASE_NO + 129)
-#define EOWNERDEAD      (ERROR_BASE_NO + 130)
-#define ENOTRECOVERABLE (ERROR_BASE_NO + 131)
-#define ERFKILL         (ERROR_BASE_NO + 132)
-#define EHWPOISON       (ERROR_BASE_NO + 133)
-
-#endif
-
-#endif

include/libc/libc_fcntl.h

@@ -1,102 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*
- * File      : libc_fcntl.h
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-02-07     Bernard      Add O_DIRECTORY definition in NEWLIB mode.
- * 2018-02-09     Bernard      Add O_BINARY definition
- */
-
-#ifndef LIBC_FCNTL_H__
-#define LIBC_FCNTL_H__
-
-#if defined(RT_USING_NEWLIB) || defined(_WIN32)
-#include <fcntl.h>
-
-#ifndef O_NONBLOCK
-#define O_NONBLOCK   0x4000
-#endif
-
-#if defined(_WIN32)
-#define O_ACCMODE   (_O_RDONLY | _O_WRONLY | _O_RDWR)
-#endif
-
-#ifndef F_GETFL
-#define F_GETFL  3
-#endif
-#ifndef F_SETFL
-#define F_SETFL  4
-#endif
-
-#ifndef O_DIRECTORY
-#define O_DIRECTORY 0x200000
-#endif
-
-#ifndef O_BINARY
-#ifdef  _O_BINARY
-#define O_BINARY _O_BINARY
-#else
-#define O_BINARY	     0
-#endif
-#endif
-
-#else
-#define O_RDONLY         00
-#define O_WRONLY         01
-#define O_RDWR           02
-
-#define O_CREAT        0100
-#define O_EXCL         0200
-#define O_NOCTTY       0400
-#define O_TRUNC       01000
-#define O_APPEND      02000
-#define O_NONBLOCK    04000
-#define O_DSYNC      010000
-#define O_SYNC     04010000
-#define O_RSYNC    04010000
-#define O_BINARY    0100000
-#define O_DIRECTORY 0200000
-#define O_NOFOLLOW  0400000
-#define O_CLOEXEC  02000000
-
-#define O_ASYNC      020000
-#define O_DIRECT     040000
-#define O_LARGEFILE 0100000
-#define O_NOATIME  01000000
-#define O_PATH    010000000
-#define O_TMPFILE 020200000
-#define O_NDELAY O_NONBLOCK
-
-#define O_SEARCH  O_PATH
-#define O_EXEC    O_PATH
-
-#define O_ACCMODE (03|O_SEARCH)
-
-#define F_DUPFD  0
-#define F_GETFD  1
-#define F_SETFD  2
-#define F_GETFL  3
-#define F_SETFL  4
-
-#define F_SETOWN 8
-#define F_GETOWN 9
-#define F_SETSIG 10
-#define F_GETSIG 11
-
-#define F_GETLK 12
-#define F_SETLK 13
-#define F_SETLKW 14
-
-#define F_SETOWN_EX 15
-#define F_GETOWN_EX 16
-
-#define F_GETOWNER_UIDS 17
-#endif
-
-#endif

include/libc/libc_fdset.h

@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*
- * File      : libc_errno.h
- *
- * Change Logs:
- * Date           Author       Notes
- * 2017-10-30     Bernard      The first version
- */
-
-#ifndef LIBC_FDSET_H__
-#define LIBC_FDSET_H__
-
-#include <rtconfig.h>
-
-#if defined(RT_USING_NEWLIB) || defined(_WIN32)
-#include <sys/types.h>
-#if defined(HAVE_SYS_SELECT_H)
-#include <sys/select.h>
-#endif
-
-#else
-
-#ifdef SAL_USING_POSIX
-
-#ifdef FD_SETSIZE
-#undef FD_SETSIZE
-#endif
-
-#define FD_SETSIZE      DFS_FD_MAX
-#endif
-
-#  ifndef   FD_SETSIZE
-#   define  FD_SETSIZE  32
-#  endif
-
-#  define   NBBY    8       /* number of bits in a byte */
-
-typedef long    fd_mask;
-#  define   NFDBITS (sizeof (fd_mask) * NBBY)   /* bits per mask */
-#  ifndef   howmany
-#   define  howmany(x,y)    (((x)+((y)-1))/(y))
-#  endif
-
-/* We use a macro for fd_set so that including Sockets.h afterwards
-   can work.  */
-typedef struct _types_fd_set {
-    fd_mask fds_bits[howmany(FD_SETSIZE, NFDBITS)];
-} _types_fd_set;
-
-#define fd_set _types_fd_set
-
-#  define   FD_SET(n, p)    ((p)->fds_bits[(n)/NFDBITS] |= (1L << ((n) % NFDBITS)))
-#  define   FD_CLR(n, p)    ((p)->fds_bits[(n)/NFDBITS] &= ~(1L << ((n) % NFDBITS)))
-#  define   FD_ISSET(n, p)  ((p)->fds_bits[(n)/NFDBITS] & (1L << ((n) % NFDBITS)))
-#  define   FD_ZERO(p)      memset((void*)(p), 0, sizeof(*(p)))
-
-#endif
-
-#endif

include/libc/libc_ioctl.h

@@ -1,234 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*
- * File      : libc_ioctl.h
- *
- * Change Logs:
- * Date           Author       Notes
- * 2017-01-21     Bernard      the first version
- */
-
-#ifndef LIBC_IOCTL_H__
-#define LIBC_IOCTL_H__
-
-#define _IOC(a,b,c,d) ( ((a)<<30) | ((b)<<8) | (c) | ((d)<<16) )
-#define _IOC_NONE  0U
-#define _IOC_WRITE 1U
-#define _IOC_READ  2U
-
-#ifndef _WIN32
-#define _IO(a,b)    _IOC(_IOC_NONE,(a),(b),0)
-#define _IOW(a,b,c) _IOC(_IOC_WRITE,(a),(b),sizeof(c))
-#define _IOR(a,b,c) _IOC(_IOC_READ,(a),(b),sizeof(c))
-#define _IOWR(a,b,c) _IOC(_IOC_READ|_IOC_WRITE,(a),(b),sizeof(c))
-
-#define FIONREAD    _IOR('f', 127, int) /* get # bytes to read */
-#define FIONBIO     _IOW('f', 126, int) /* set/clear non-blocking i/o */
-#define FIONWRITE   _IOR('f', 121, int) /* get # bytes outstanding
-                         * in send queue. */
-#endif
-
-#define TCGETS		0x5401
-#define TCSETS		0x5402
-#define TCSETSW		0x5403
-#define TCSETSF		0x5404
-#define TCGETA		0x5405
-#define TCSETA		0x5406
-#define TCSETAW		0x5407
-#define TCSETAF		0x5408
-#define TCSBRK		0x5409
-#define TCXONC		0x540A
-#define TCFLSH		0x540B
-#define TIOCEXCL	0x540C
-#define TIOCNXCL	0x540D
-#define TIOCSCTTY	0x540E
-#define TIOCGPGRP	0x540F
-#define TIOCSPGRP	0x5410
-#define TIOCOUTQ	0x5411
-#define TIOCSTI		0x5412
-#define TIOCGWINSZ	0x5413
-#define TIOCSWINSZ	0x5414
-#define TIOCMGET	0x5415
-#define TIOCMBIS	0x5416
-#define TIOCMBIC	0x5417
-#define TIOCMSET	0x5418
-#define TIOCGSOFTCAR	0x5419
-#define TIOCSSOFTCAR	0x541A
-// #define FIONREAD	0x541B
-#define TIOCINQ		FIONREAD
-#define TIOCLINUX	0x541C
-#define TIOCCONS	0x541D
-#define TIOCGSERIAL	0x541E
-#define TIOCSSERIAL	0x541F
-#define TIOCPKT		0x5420
-// #define FIONBIO		0x5421
-#define TIOCNOTTY	0x5422
-#define TIOCSETD	0x5423
-#define TIOCGETD	0x5424
-#define TCSBRKP		0x5425
-#define TIOCSBRK	0x5427
-#define TIOCCBRK	0x5428
-#define TIOCGSID	0x5429
-#define TIOCGRS485	0x542E
-#define TIOCSRS485	0x542F
-#define TIOCGPTN	0x80045430
-#define TIOCSPTLCK	0x40045431
-#define TIOCGDEV	0x80045432
-#define TCGETX		0x5432
-#define TCSETX		0x5433
-#define TCSETXF		0x5434
-#define TCSETXW		0x5435
-#define TIOCSIG		0x40045436
-#define TIOCVHANGUP	0x5437
-#define TIOCGPKT	0x80045438
-#define TIOCGPTLCK	0x80045439
-#define TIOCGEXCL	0x80045440
-
-#define FIONCLEX	0x5450
-#define FIOCLEX		0x5451
-
-#ifndef _WIN32
-#define FIOASYNC	0x5452
-#endif
-
-#define TIOCSERCONFIG	0x5453
-#define TIOCSERGWILD	0x5454
-#define TIOCSERSWILD	0x5455
-#define TIOCGLCKTRMIOS	0x5456
-#define TIOCSLCKTRMIOS	0x5457
-#define TIOCSERGSTRUCT	0x5458
-#define TIOCSERGETLSR   0x5459
-#define TIOCSERGETMULTI 0x545A
-#define TIOCSERSETMULTI 0x545B
-
-#define TIOCMIWAIT	0x545C
-#define TIOCGICOUNT	0x545D
-#define FIOQSIZE	0x5460
-
-#define TIOCPKT_DATA		 0
-#define TIOCPKT_FLUSHREAD	 1
-#define TIOCPKT_FLUSHWRITE	 2
-#define TIOCPKT_STOP		 4
-#define TIOCPKT_START		 8
-#define TIOCPKT_NOSTOP		16
-#define TIOCPKT_DOSTOP		32
-#define TIOCPKT_IOCTL		64
-
-#define TIOCSER_TEMT    0x01
-
-struct winsize {
-	unsigned short ws_row;
-	unsigned short ws_col;
-	unsigned short ws_xpixel;
-	unsigned short ws_ypixel;
-};
-
-#define TIOCM_LE        0x001
-#define TIOCM_DTR       0x002
-#define TIOCM_RTS       0x004
-#define TIOCM_ST        0x008
-#define TIOCM_SR        0x010
-#define TIOCM_CTS       0x020
-#define TIOCM_CAR       0x040
-#define TIOCM_RNG       0x080
-#define TIOCM_DSR       0x100
-#define TIOCM_CD        TIOCM_CAR
-#define TIOCM_RI        TIOCM_RNG
-#define TIOCM_OUT1      0x2000
-#define TIOCM_OUT2      0x4000
-#define TIOCM_LOOP      0x8000
-
-#define N_TTY           0
-#define N_SLIP          1
-#define N_MOUSE         2
-#define N_PPP           3
-#define N_STRIP         4
-#define N_AX25          5
-#define N_X25           6
-#define N_6PACK         7
-#define N_MASC          8
-#define N_R3964         9
-#define N_PROFIBUS_FDL  10
-#define N_IRDA          11
-#define N_SMSBLOCK      12
-#define N_HDLC          13
-#define N_SYNC_PPP      14
-#define N_HCI           15
-
-#define FIOSETOWN       0x8901
-#define SIOCSPGRP       0x8902
-#define FIOGETOWN       0x8903
-#define SIOCGPGRP       0x8904
-// #define SIOCATMARK      0x8905
-#define SIOCGSTAMP      0x8906
-#define SIOCGSTAMPNS    0x8907
-
-#define SIOCADDRT       0x890B
-#define SIOCDELRT       0x890C
-#define SIOCRTMSG       0x890D
-
-#define SIOCGIFNAME     0x8910
-#define SIOCSIFLINK     0x8911
-#define SIOCGIFCONF     0x8912
-#define SIOCGIFFLAGS    0x8913
-#define SIOCSIFFLAGS    0x8914
-#define SIOCGIFADDR     0x8915
-#define SIOCSIFADDR     0x8916
-#define SIOCGIFDSTADDR  0x8917
-#define SIOCSIFDSTADDR  0x8918
-#define SIOCGIFBRDADDR  0x8919
-#define SIOCSIFBRDADDR  0x891a
-#define SIOCGIFNETMASK  0x891b
-#define SIOCSIFNETMASK  0x891c
-#define SIOCGIFMETRIC   0x891d
-#define SIOCSIFMETRIC   0x891e
-#define SIOCGIFMEM      0x891f
-#define SIOCSIFMEM      0x8920
-#define SIOCGIFMTU      0x8921
-#define SIOCSIFMTU      0x8922
-#define SIOCSIFNAME     0x8923
-#define SIOCSIFHWADDR   0x8924
-#define SIOCGIFENCAP    0x8925
-#define SIOCSIFENCAP    0x8926
-#define SIOCGIFHWADDR   0x8927
-#define SIOCGIFSLAVE    0x8929
-#define SIOCSIFSLAVE    0x8930
-#define SIOCADDMULTI    0x8931
-#define SIOCDELMULTI    0x8932
-#define SIOCGIFINDEX    0x8933
-#define SIOGIFINDEX     SIOCGIFINDEX
-#define SIOCSIFPFLAGS   0x8934
-#define SIOCGIFPFLAGS   0x8935
-#define SIOCDIFADDR     0x8936
-#define SIOCSIFHWBROADCAST 0x8937
-#define SIOCGIFCOUNT    0x8938
-
-#define SIOCGIFBR       0x8940
-#define SIOCSIFBR       0x8941
-
-#define SIOCGIFTXQLEN   0x8942
-#define SIOCSIFTXQLEN   0x8943
-
-#define SIOCDARP        0x8953
-#define SIOCGARP        0x8954
-#define SIOCSARP        0x8955
-
-#define SIOCDRARP       0x8960
-#define SIOCGRARP       0x8961
-#define SIOCSRARP       0x8962
-
-#define SIOCGIFMAP      0x8970
-#define SIOCSIFMAP      0x8971
-
-#define SIOCADDDLCI     0x8980
-#define SIOCDELDLCI     0x8981
-
-#define SIOCDEVPRIVATE		0x89F0
-#define SIOCPROTOPRIVATE	0x89E0
-
-#endif
-

include/libc/libc_signal.h

@@ -1,188 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2017-09-12     Bernard      The first version
- */
-
-#ifndef LIBC_SIGNAL_H__
-#define LIBC_SIGNAL_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef HAVE_CCONFIG_H
-#include <cconfig.h>
-#endif
-
-#ifndef HAVE_SIGVAL
-/*  Signal Generation and Delivery, P1003.1b-1993, p. 63
-    NOTE: P1003.1c/D10, p. 34 adds sigev_notify_function and
-          sigev_notify_attributes to the sigevent structure.  */
-
-union sigval 
-{
-    int    sival_int;    /* Integer signal value */
-    void  *sival_ptr;    /* Pointer signal value */
-};
-#endif
-
-#ifndef HAVE_SIGEVENT
-struct sigevent
-{
-    int          sigev_notify;               /* Notification type */
-    int          sigev_signo;                /* Signal number */
-    union sigval sigev_value;                /* Signal value */
-    void         (*sigev_notify_function)( union sigval );
-                                             /* Notification function */
-    void         *sigev_notify_attributes;   /* Notification Attributes, really pthread_attr_t */
-};
-#endif
-
-#ifndef HAVE_SIGINFO
-struct siginfo
-{
-    rt_uint16_t si_signo;
-    rt_uint16_t si_code;
-
-    union sigval si_value;
-};
-typedef struct siginfo siginfo_t;
-#endif
-
-#define SI_USER     0x01    /* Signal sent by kill(). */
-#define SI_QUEUE    0x02    /* Signal sent by sigqueue(). */
-#define SI_TIMER    0x03    /* Signal generated by expiration of a 
-                               timer set by timer_settime(). */
-#define SI_ASYNCIO  0x04    /* Signal generated by completion of an 
-                               asynchronous I/O request. */
-#define SI_MESGQ    0x05    /* Signal generated by arrival of a 
-                               message on an empty message queue. */
-
-#ifdef RT_USING_NEWLIB
-#include <sys/signal.h>
-#endif
-
-#if defined(__CC_ARM) || defined(__CLANG_ARM)
-#include <signal.h>
-typedef unsigned long sigset_t;
-
-#define SIGHUP       1
-/* #define SIGINT       2 */
-#define SIGQUIT      3
-/* #define SIGILL       4 */
-#define SIGTRAP      5
-/* #define SIGABRT      6 */
-#define SIGEMT       7
-/* #define SIGFPE       8 */
-#define SIGKILL      9
-#define SIGBUS      10
-/* #define SIGSEGV     11 */
-#define SIGSYS      12
-#define SIGPIPE     13
-#define SIGALRM     14
-/* #define SIGTERM     15 */
-#define SIGURG      16
-#define SIGSTOP     17
-#define SIGTSTP     18
-#define SIGCONT     19
-#define SIGCHLD     20
-#define SIGTTIN     21
-#define SIGTTOU     22
-#define SIGPOLL     23
-#define SIGWINCH    24
-/* #define SIGUSR1     25 */
-/* #define SIGUSR2     26 */
-#define SIGRTMIN    27
-#define SIGRTMAX    31
-#define NSIG        32
-
-#define SIG_SETMASK 0   /* set mask with sigprocmask() */
-#define SIG_BLOCK   1   /* set of signals to block */
-#define SIG_UNBLOCK 2   /* set of signals to, well, unblock */
-
-typedef void (*_sig_func_ptr)(int);
-
-struct sigaction 
-{
-    _sig_func_ptr sa_handler;
-    sigset_t sa_mask;
-    int sa_flags;
-};
-
-#define sigaddset(what,sig) (*(what) |= (1<<(sig)), 0)
-#define sigdelset(what,sig) (*(what) &= ~(1<<(sig)), 0)
-#define sigemptyset(what)   (*(what) = 0, 0)
-#define sigfillset(what)    (*(what) = ~(0), 0)
-#define sigismember(what,sig) (((*(what)) & (1<<(sig))) != 0)
-
-int sigprocmask (int how, const sigset_t *set, sigset_t *oset);
-int sigaction(int signum, const struct sigaction *act, struct sigaction *oldact);
-
-#elif defined(__IAR_SYSTEMS_ICC__)
-#include <signal.h>
-typedef unsigned long sigset_t;
-
-#define SIGHUP       1
-#define SIGINT       2
-#define SIGQUIT      3
-#define SIGILL       4
-#define SIGTRAP      5
-/* #define SIGABRT      6 */
-#define SIGEMT       7
-#define SIGFPE       8
-#define SIGKILL      9
-#define SIGBUS      10
-#define SIGSEGV     11
-#define SIGSYS      12
-#define SIGPIPE     13
-#define SIGALRM     14
-#define SIGTERM     15
-#define SIGURG      16
-#define SIGSTOP     17
-#define SIGTSTP     18
-#define SIGCONT     19
-#define SIGCHLD     20
-#define SIGTTIN     21
-#define SIGTTOU     22
-#define SIGPOLL     23
-#define SIGWINCH    24
-#define SIGUSR1     25
-#define SIGUSR2     26
-#define SIGRTMIN    27
-#define SIGRTMAX    31
-#define NSIG        32
-
-#define SIG_SETMASK 0   /* set mask with sigprocmask() */
-#define SIG_BLOCK   1   /* set of signals to block */
-#define SIG_UNBLOCK 2   /* set of signals to, well, unblock */
-
-typedef void (*_sig_func_ptr)(int);
-
-struct sigaction 
-{
-    _sig_func_ptr sa_handler;
-    sigset_t sa_mask;
-    int sa_flags;
-};
-
-#define sigaddset(what,sig) (*(what) |= (1<<(sig)), 0)
-#define sigdelset(what,sig) (*(what) &= ~(1<<(sig)), 0)
-#define sigemptyset(what)   (*(what) = 0, 0)
-#define sigfillset(what)    (*(what) = ~(0), 0)
-#define sigismember(what,sig) (((*(what)) & (1<<(sig))) != 0)
-
-int sigprocmask (int how, const sigset_t *set, sigset_t *oset);
-int sigaction(int signum, const struct sigaction *act, struct sigaction *oldact);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-

include/libc/libc_stat.h

@@ -1,107 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef LIBC_STAT_H__
-#define LIBC_STAT_H__
-
-#include <rtconfig.h>
-
-#if defined(RT_USING_NEWLIB)
-/* use header file of newlib */
-#include <sys/stat.h>
-
-#elif defined(_WIN32)
-#include <sys/stat.h>
-
-#define S_IRWXU              00700
-#define S_IRUSR              00400
-#define S_IWUSR              00200
-#define S_IXUSR              00100
-
-#define S_IRWXG              00070
-#define S_IRGRP              00040
-#define S_IWGRP              00020
-#define S_IXGRP              00010
-
-#define S_IRWXO              00007
-#define S_IROTH              00004
-#define S_IWOTH              00002
-#define S_IXOTH              00001
-
-#define S_IFSOCK             0140000
-#define S_IFLNK              0120000
-#define S_IFBLK              0060000
-#define S_IFIFO              0010000
-#define S_ISUID              0004000
-#define S_ISGID              0002000
-#define S_ISVTX              0001000
-
-#define S_ISDIR(m)           (((m) & S_IFMT) == S_IFDIR)
-
-#else
-#define S_IFMT               00170000
-#define S_IFSOCK             0140000
-#define S_IFLNK              0120000
-#define S_IFREG              0100000
-#define S_IFBLK              0060000
-#define S_IFDIR              0040000
-#define S_IFCHR              0020000
-#define S_IFIFO              0010000
-#define S_ISUID              0004000
-#define S_ISGID              0002000
-#define S_ISVTX              0001000
-
-#define S_ISLNK(m)           (((m) & S_IFMT) == S_IFLNK)
-#define S_ISREG(m)           (((m) & S_IFMT) == S_IFREG)
-#define S_ISDIR(m)           (((m) & S_IFMT) == S_IFDIR)
-#define S_ISCHR(m)           (((m) & S_IFMT) == S_IFCHR)
-#define S_ISBLK(m)           (((m) & S_IFMT) == S_IFBLK)
-#define S_ISFIFO(m)          (((m) & S_IFMT) == S_IFIFO)
-#define S_ISSOCK(m)          (((m) & S_IFMT) == S_IFSOCK)
-
-#define S_IRWXU              00700
-#define S_IRUSR              00400
-#define S_IWUSR              00200
-#define S_IXUSR              00100
-
-#define S_IRWXG              00070
-#define S_IRGRP              00040
-#define S_IWGRP              00020
-#define S_IXGRP              00010
-
-#define S_IRWXO              00007
-#define S_IROTH              00004
-#define S_IWOTH              00002
-#define S_IXOTH              00001
-
-/* stat structure */
-#include <stdint.h>
-#include <time.h>
-
-struct stat
-{
-    struct rt_device *st_dev;
-    uint16_t  st_ino;
-    uint16_t  st_mode;
-    uint16_t  st_nlink;
-    uint16_t  st_uid;
-    uint16_t  st_gid;
-    struct rt_device *st_rdev;
-    uint32_t  st_size;
-    time_t    st_atime;
-    long      st_spare1;
-    time_t    st_mtime;
-    long      st_spare2;
-    time_t    st_ctime;
-    long      st_spare3;
-    uint32_t  st_blksize;
-    uint32_t  st_blocks;
-    long      st_spare4[2];
-};
-
-#endif
-
-#endif

include/rtdbg.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -32,6 +32,10 @@
 
 #include <rtconfig.h>
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /* the debug log will force enable when RT_DEBUG macro is defined */
 #if defined(RT_DEBUG) && !defined(DBG_ENABLE)
 #define DBG_ENABLE
@@ -91,13 +95,13 @@
 #ifdef DBG_COLOR
 #define _DBG_COLOR(n)        rt_kprintf("\033["#n"m")
 #define _DBG_LOG_HDR(lvl_name, color_n)                    \
-    rt_kprintf("\033["#color_n"m["lvl_name"/"DBG_SECTION_NAME"] ")
+    rt_kprintf("\033["#color_n"m[" lvl_name "/" DBG_SECTION_NAME "] ")
 #define _DBG_LOG_X_END                                     \
     rt_kprintf("\033[0m\n")
 #else
 #define _DBG_COLOR(n)
 #define _DBG_LOG_HDR(lvl_name, color_n)                    \
-    rt_kprintf("["lvl_name"/"DBG_SECTION_NAME"] ")
+    rt_kprintf("[" lvl_name "/" DBG_SECTION_NAME "] ")
 #define _DBG_LOG_X_END                                     \
     rt_kprintf("\n")
 #endif /* DBG_COLOR */
@@ -176,4 +180,8 @@
 
 #endif /* defined(RT_USING_ULOG) && define(DBG_ENABLE) */
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* RT_DBG_H__ */

include/rtdebug.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,22 +10,6 @@
 #include <rtconfig.h>
 
 /* settings depend check */
-#ifdef RT_USING_POSIX
-#if !defined(RT_USING_DFS) || !defined(RT_USING_DFS_DEVFS)
-#error "POSIX poll/select, stdin need file system(RT_USING_DFS) and device file system(RT_USING_DFS_DEVFS)"
-#endif
-
-#if !defined(RT_USING_LIBC)
-#error "POSIX layer need standard C library(RT_USING_LIBC)"
-#endif
-
-#endif
-
-#ifdef RT_USING_POSIX_TERMIOS
-#if !defined(RT_USING_POSIX)
-#error "termios need POSIX layer(RT_USING_POSIX)"
-#endif
-#endif
 
 /* Using this macro to control all kernel debug features. */
 #ifdef RT_DEBUG

include/rtdef.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,6 +26,8 @@
  * 2018-09-14     Bernard      apply Apache License v2.0 to RT-Thread Kernel
  * 2018-12-28     armink       change version number to v3.1.2
  * 2019-03-14     armink       change version number to v3.1.3
+ * 2019-06-12     armink       change version number to v3.1.4
+ * 2020-05-14     armink       change version number to v3.1.5
  */
 
 #ifndef __RT_DEF_H__
@@ -47,7 +49,7 @@ extern "C" {
 /* RT-Thread version information */
 #define RT_VERSION                      3L              /**< major version number */
 #define RT_SUBVERSION                   1L              /**< minor version number */
-#define RT_REVISION                     3L              /**< revise version number */
+#define RT_REVISION                     5L              /**< revise version number */
 
 /* RT-Thread version */
 #define RTTHREAD_VERSION                ((RT_VERSION * 10000) + \
@@ -57,16 +59,21 @@ extern "C" {
 #ifndef RT_USING_ARCH_DATA_TYPE
 typedef signed   char                   rt_int8_t;      /**<  8bit integer type */
 typedef signed   short                  rt_int16_t;     /**< 16bit integer type */
-typedef signed   long                   rt_int32_t;     /**< 32bit integer type */
-typedef signed long long                rt_int64_t;     /**< 64bit integer type */
+typedef signed   int                    rt_int32_t;     /**< 32bit integer type */
 typedef unsigned char                   rt_uint8_t;     /**<  8bit unsigned integer type */
 typedef unsigned short                  rt_uint16_t;    /**< 16bit unsigned integer type */
-typedef unsigned long                   rt_uint32_t;    /**< 32bit unsigned integer type */
+typedef unsigned int                    rt_uint32_t;    /**< 32bit unsigned integer type */
+
+#ifdef ARCH_CPU_64BIT
+typedef signed long                     rt_int64_t;     /**< 64bit integer type */
+typedef unsigned long                   rt_uint64_t;    /**< 64bit unsigned integer type */
+#else
+typedef signed long long                rt_int64_t;     /**< 64bit integer type */
 typedef unsigned long long              rt_uint64_t;    /**< 64bit unsigned integer type */
 #endif
-typedef int                             rt_bool_t;      /**< boolean type */
+#endif
 
-/* 32bit CPU */
+typedef int                             rt_bool_t;      /**< boolean type */
 typedef long                            rt_base_t;      /**< Nbit CPU related date type */
 typedef unsigned long                   rt_ubase_t;     /**< Nbit unsigned CPU related data type */
 
@@ -90,6 +97,13 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
 #define RT_UINT32_MAX                   0xffffffff      /**< Maxium number of UINT32 */
 #define RT_TICK_MAX                     RT_UINT32_MAX   /**< Maxium number of tick */
 
+/* maximum value of ipc type */
+#define RT_SEM_VALUE_MAX                RT_UINT16_MAX   /**< Maxium number of semaphore .value */
+#define RT_MUTEX_VALUE_MAX              RT_UINT16_MAX   /**< Maxium number of mutex .value */
+#define RT_MUTEX_HOLD_MAX               RT_UINT8_MAX    /**< Maxium number of mutex .hold */
+#define RT_MB_ENTRY_MAX                 RT_UINT16_MAX   /**< Maxium number of mailbox .entry */
+#define RT_MQ_ENTRY_MAX                 RT_UINT16_MAX   /**< Maxium number of message queue .entry */
+
 #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
 #define __CLANG_ARM
 #endif
@@ -104,12 +118,6 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
 
     #define RT_WEAK                     __attribute__((weak))
     #define rt_inline                   static __inline
-    /* module compiling */
-    #ifdef RT_USING_MODULE
-        #define RTT_API                 __declspec(dllimport)
-    #else
-        #define RTT_API                 __declspec(dllexport)
-    #endif
 
 #elif defined (__IAR_SYSTEMS_ICC__)     /* for IAR Compiler */
     #include <stdarg.h>
@@ -120,7 +128,6 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define ALIGN(n)                    PRAGMA(data_alignment=n)
     #define RT_WEAK                     __weak
     #define rt_inline                   static inline
-    #define RTT_API
 
 #elif defined (__GNUC__)                /* GNU GCC Compiler */
     #ifdef RT_USING_NEWLIB
@@ -140,7 +147,6 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define ALIGN(n)                    __attribute__((aligned(n)))
     #define RT_WEAK                     __attribute__((weak))
     #define rt_inline                   static __inline
-    #define RTT_API
 #elif defined (__ADSPBLACKFIN__)        /* for VisualDSP++ Compiler */
     #include <stdarg.h>
     #define SECTION(x)                  __attribute__((section(x)))
@@ -149,7 +155,6 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define ALIGN(n)                    __attribute__((aligned(n)))
     #define RT_WEAK                     __attribute__((weak))
     #define rt_inline                   static inline
-    #define RTT_API
 #elif defined (_MSC_VER)
     #include <stdarg.h>
     #define SECTION(x)
@@ -158,7 +163,6 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define ALIGN(n)                    __declspec(align(n))
     #define RT_WEAK
     #define rt_inline                   static __inline
-    #define RTT_API
 #elif defined (__TI_COMPILER_VERSION__)
     #include <stdarg.h>
     /* The way that TI compiler set section is different from other(at least
@@ -171,7 +175,6 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #define ALIGN(n)
     #define RT_WEAK
     #define rt_inline                   static inline
-    #define RTT_API
 #else
     #error not supported tool chain
 #endif
@@ -190,11 +193,11 @@ typedef int (*init_fn_t)(void);
         };
         #define INIT_EXPORT(fn, level)                                                       \
             const char __rti_##fn##_name[] = #fn;                                            \
-            RT_USED const struct rt_init_desc __rt_init_desc_##fn SECTION(".rti_fn."level) = \
+            RT_USED const struct rt_init_desc __rt_init_desc_##fn SECTION(".rti_fn." level) = \
             { __rti_##fn##_name, fn};
     #else
         #define INIT_EXPORT(fn, level)                                                       \
-            RT_USED const init_fn_t __rt_init_##fn SECTION(".rti_fn."level) = fn
+            RT_USED const init_fn_t __rt_init_##fn SECTION(".rti_fn." level) = fn
     #endif
 #endif
 #else
@@ -324,7 +327,6 @@ typedef struct rt_slist_node rt_slist_t;                /**< Type for single lis
 /*
  * kernel object macros
  */
-#define RT_OBJECT_FLAG_MODULE           0x80            /**< is module object. */
 
 /**
  * Base structure of Kernel object
@@ -335,9 +337,6 @@ struct rt_object
     rt_uint8_t type;                                    /**< type of kernel object */
     rt_uint8_t flag;                                    /**< flag of kernel object */
 
-#ifdef RT_USING_MODULE
-    void      *module_id;                               /**< id of application module */
-#endif
     rt_list_t  list;                                    /**< list node of kernel object */
 };
 typedef struct rt_object *rt_object_t;                  /**< Type for kernel objects. */
@@ -355,26 +354,24 @@ typedef struct rt_object *rt_object_t;                  /**< Type for kernel obj
  *  - MemPool
  *  - Device
  *  - Timer
- *  - Module
  *  - Unknown
  *  - Static
  */
 enum rt_object_class_type
 {
-    RT_Object_Class_Null   = 0,                         /**< The object is not used. */
-    RT_Object_Class_Thread,                             /**< The object is a thread. */
-    RT_Object_Class_Semaphore,                          /**< The object is a semaphore. */
-    RT_Object_Class_Mutex,                              /**< The object is a mutex. */
-    RT_Object_Class_Event,                              /**< The object is a event. */
-    RT_Object_Class_MailBox,                            /**< The object is a mail box. */
-    RT_Object_Class_MessageQueue,                       /**< The object is a message queue. */
-    RT_Object_Class_MemHeap,                            /**< The object is a memory heap */
-    RT_Object_Class_MemPool,                            /**< The object is a memory pool. */
-    RT_Object_Class_Device,                             /**< The object is a device */
-    RT_Object_Class_Timer,                              /**< The object is a timer. */
-    RT_Object_Class_Module,                             /**< The object is a module. */
-    RT_Object_Class_Unknown,                            /**< The object is unknown. */
-    RT_Object_Class_Static = 0x80                       /**< The object is a static object. */
+    RT_Object_Class_Null          = 0x00,      /**< The object is not used. */
+    RT_Object_Class_Thread        = 0x01,      /**< The object is a thread. */
+    RT_Object_Class_Semaphore     = 0x02,      /**< The object is a semaphore. */
+    RT_Object_Class_Mutex         = 0x03,      /**< The object is a mutex. */
+    RT_Object_Class_Event         = 0x04,      /**< The object is a event. */
+    RT_Object_Class_MailBox       = 0x05,      /**< The object is a mail box. */
+    RT_Object_Class_MessageQueue  = 0x06,      /**< The object is a message queue. */
+    RT_Object_Class_MemHeap       = 0x07,      /**< The object is a memory heap. */
+    RT_Object_Class_MemPool       = 0x08,      /**< The object is a memory pool. */
+    RT_Object_Class_Device        = 0x09,      /**< The object is a device. */
+    RT_Object_Class_Timer         = 0x0a,      /**< The object is a timer. */
+    RT_Object_Class_Unknown       = 0x0c,      /**< The object is unknown. */
+    RT_Object_Class_Static        = 0x80       /**< The object is a static object. */
 };
 
 /**
@@ -420,6 +417,7 @@ struct rt_object_information
 #define RT_TIMER_CTRL_GET_TIME          0x1             /**< get timer control command */
 #define RT_TIMER_CTRL_SET_ONESHOT       0x2             /**< change timer to one shot */
 #define RT_TIMER_CTRL_SET_PERIODIC      0x3             /**< change timer to periodic */
+#define RT_TIMER_CTRL_GET_STATE         0x4             /**< get timer run state active or deactive*/
 
 #ifndef RT_TIMER_SKIP_LIST_LEVEL
 #define RT_TIMER_SKIP_LIST_LEVEL          1
@@ -449,19 +447,6 @@ typedef struct rt_timer *rt_timer_t;
 
 /**@}*/
 
-/**
- * @addtogroup Signal
- */
-#ifdef RT_USING_SIGNALS
-#include <libc/libc_signal.h>
-typedef unsigned long rt_sigset_t;
-typedef void (*rt_sighandler_t)(int signo);
-typedef siginfo_t rt_siginfo_t;
-
-#define RT_SIG_MAX          32
-#endif
-/**@}*/
-
 /**
  * @addtogroup Thread
  */
@@ -483,12 +468,6 @@ typedef siginfo_t rt_siginfo_t;
 #define RT_THREAD_CLOSE                 0x04                /**< Closed status */
 #define RT_THREAD_STAT_MASK             0x0f
 
-#define RT_THREAD_STAT_SIGNAL           0x10                /**< task hold signals */
-#define RT_THREAD_STAT_SIGNAL_READY     (RT_THREAD_STAT_SIGNAL | RT_THREAD_READY)
-#define RT_THREAD_STAT_SIGNAL_WAIT      0x20                /**< task is waiting for signals */
-#define RT_THREAD_STAT_SIGNAL_PENDING   0x40                /**< signals is held and it has not been procressed */
-#define RT_THREAD_STAT_SIGNAL_MASK      0xf0
-
 /**
  * thread control command definitions
  */
@@ -507,10 +486,6 @@ struct rt_thread
     rt_uint8_t  type;                                   /**< type of object */
     rt_uint8_t  flags;                                  /**< thread's flags */
 
-#ifdef RT_USING_MODULE
-    void       *module_id;                              /**< id of application module */
-#endif
-
     rt_list_t   list;                                   /**< the object list */
     rt_list_t   tlist;                                  /**< the thread list */
 
@@ -541,15 +516,6 @@ struct rt_thread
     rt_uint8_t  event_info;
 #endif
 
-#if defined(RT_USING_SIGNALS)
-    rt_sigset_t     sig_pending;                        /**< the pending signals */
-    rt_sigset_t     sig_mask;                           /**< the mask bits of signal */
-
-    void            *sig_ret;                           /**< the return stack pointer from signal */
-    rt_sighandler_t *sig_vectors;                       /**< vectors of signal handler */
-    void            *si_list;                           /**< the signal infor list */
-#endif
-
     rt_ubase_t  init_tick;                              /**< thread's initialized tick */
     rt_ubase_t  remaining_tick;                         /**< remaining tick */
 
@@ -557,12 +523,7 @@ struct rt_thread
 
     void (*cleanup)(struct rt_thread *tid);             /**< cleanup function when thread exit */
 
-    /* light weight process if present */
-#ifdef RT_USING_LWP
-    void        *lwp;
-#endif
-
-    rt_uint32_t user_data;                             /**< private user data beyond this thread */
+    rt_uint32_t user_data;                              /**< private user data beyond this thread */
 };
 typedef struct rt_thread *rt_thread_t;
 
@@ -656,7 +617,7 @@ struct rt_mailbox
 {
     struct rt_ipc_object parent;                        /**< inherit from ipc_object */
 
-    rt_uint32_t         *msg_pool;                      /**< start address of message buffer */
+    rt_ubase_t          *msg_pool;                      /**< start address of message buffer */
 
     rt_uint16_t          size;                          /**< size of message pool */
 
@@ -687,6 +648,8 @@ struct rt_messagequeue
     void                *msg_queue_head;                /**< list head */
     void                *msg_queue_tail;                /**< list tail */
     void                *msg_queue_free;                /**< pointer indicated the free node of queue */
+
+    rt_list_t            suspend_sender_thread;         /**< sender thread suspended on this message queue */
 };
 typedef struct rt_messagequeue *rt_mq_t;
 #endif
@@ -760,7 +723,6 @@ struct rt_mempool
     rt_size_t        block_free_count;                  /**< numbers of free memory block */
 
     rt_list_t        suspend_thread;                    /**< threads pended on this resource */
-    rt_size_t        suspend_thread_count;              /**< numbers of thread pended on this resource */
 };
 typedef struct rt_mempool *rt_mp_t;
 #endif
@@ -799,6 +761,7 @@ enum rt_device_class_type
     RT_Device_Class_Timer,                              /**< Timer device */
     RT_Device_Class_Miscellaneous,                      /**< Miscellaneous device */
     RT_Device_Class_Sensor,                             /**< Sensor device */
+    RT_Device_Class_Touch,                              /**< Touch device */
     RT_Device_Class_Unknown                             /**< unknown device */
 };
 
@@ -835,26 +798,12 @@ enum rt_device_class_type
 #define RT_DEVICE_CTRL_RESUME           0x01            /**< resume device */
 #define RT_DEVICE_CTRL_SUSPEND          0x02            /**< suspend device */
 #define RT_DEVICE_CTRL_CONFIG           0x03            /**< configure device */
+#define RT_DEVICE_CTRL_CLOSE            0x04            /**< close device */
 
 #define RT_DEVICE_CTRL_SET_INT          0x10            /**< set interrupt */
 #define RT_DEVICE_CTRL_CLR_INT          0x11            /**< clear interrupt */
 #define RT_DEVICE_CTRL_GET_INT          0x12            /**< get interrupt status */
 
-/**
- * special device commands
- */
-#define RT_DEVICE_CTRL_CHAR_STREAM      0x10            /**< stream mode on char device */
-#define RT_DEVICE_CTRL_BLK_GETGEOME     0x10            /**< get geometry information   */
-#define RT_DEVICE_CTRL_BLK_SYNC         0x11            /**< flush data to block device */
-#define RT_DEVICE_CTRL_BLK_ERASE        0x12            /**< erase block on block device */
-#define RT_DEVICE_CTRL_BLK_AUTOREFRESH  0x13            /**< block device : enter/exit auto refresh mode */
-#define RT_DEVICE_CTRL_NETIF_GETMAC     0x10            /**< get mac address */
-#define RT_DEVICE_CTRL_MTD_FORMAT       0x10            /**< format a MTD device */
-#define RT_DEVICE_CTRL_RTC_GET_TIME     0x10            /**< get time */
-#define RT_DEVICE_CTRL_RTC_SET_TIME     0x11            /**< set time */
-#define RT_DEVICE_CTRL_RTC_GET_ALARM    0x12            /**< get alarm */
-#define RT_DEVICE_CTRL_RTC_SET_ALARM    0x13            /**< set alarm */
-
 typedef struct rt_device *rt_device_t;
 /**
  * operations set for device object
@@ -870,16 +819,6 @@ struct rt_device_ops
     rt_err_t  (*control)(rt_device_t dev, int cmd, void *args);
 };
 
-/**
- * WaitQueue structure
- */
-struct rt_wqueue
-{
-    rt_uint32_t flag;
-    rt_list_t waiting_list;
-};
-typedef struct rt_wqueue rt_wqueue_t;
-
 /**
  * Device structure
  */
@@ -910,121 +849,12 @@ struct rt_device
     rt_err_t  (*control)(rt_device_t dev, int cmd, void *args);
 #endif
 
-#if defined(RT_USING_POSIX)
-    const struct dfs_file_ops *fops;
-    struct rt_wqueue wait_queue;
-#endif
-
     void                     *user_data;                /**< device private data */
 };
 
-/**
- * block device geometry structure
- */
-struct rt_device_blk_geometry
-{
-    rt_uint32_t sector_count;                           /**< count of sectors */
-    rt_uint32_t bytes_per_sector;                       /**< number of bytes per sector */
-    rt_uint32_t block_size;                             /**< number of bytes to erase one block */
-};
-
-/**
- * sector arrange struct on block device
- */
-struct rt_device_blk_sectors
-{
-    rt_uint32_t sector_begin;                           /**< begin sector */
-    rt_uint32_t sector_end;                             /**< end sector   */
-};
-
-/**
- * cursor control command
- */
-#define RT_DEVICE_CTRL_CURSOR_SET_POSITION  0x10
-#define RT_DEVICE_CTRL_CURSOR_SET_TYPE      0x11
-
-/**
- * graphic device control command
- */
-#define RTGRAPHIC_CTRL_RECT_UPDATE      0
-#define RTGRAPHIC_CTRL_POWERON          1
-#define RTGRAPHIC_CTRL_POWEROFF         2
-#define RTGRAPHIC_CTRL_GET_INFO         3
-#define RTGRAPHIC_CTRL_SET_MODE         4
-#define RTGRAPHIC_CTRL_GET_EXT          5
-
-/* graphic deice */
-enum
-{
-    RTGRAPHIC_PIXEL_FORMAT_MONO = 0,
-    RTGRAPHIC_PIXEL_FORMAT_GRAY4,
-    RTGRAPHIC_PIXEL_FORMAT_GRAY16,
-    RTGRAPHIC_PIXEL_FORMAT_RGB332,
-    RTGRAPHIC_PIXEL_FORMAT_RGB444,
-    RTGRAPHIC_PIXEL_FORMAT_RGB565,
-    RTGRAPHIC_PIXEL_FORMAT_RGB565P,
-    RTGRAPHIC_PIXEL_FORMAT_BGR565 = RTGRAPHIC_PIXEL_FORMAT_RGB565P,
-    RTGRAPHIC_PIXEL_FORMAT_RGB666,
-    RTGRAPHIC_PIXEL_FORMAT_RGB888,
-    RTGRAPHIC_PIXEL_FORMAT_ARGB888,
-    RTGRAPHIC_PIXEL_FORMAT_ABGR888,
-    RTGRAPHIC_PIXEL_FORMAT_ARGB565,
-    RTGRAPHIC_PIXEL_FORMAT_ALPHA,
-    RTGRAPHIC_PIXEL_FORMAT_COLOR,
-};
-
-/**
- * build a pixel position according to (x, y) coordinates.
- */
-#define RTGRAPHIC_PIXEL_POSITION(x, y)  ((x << 16) | y)
-
-/**
- * graphic device information structure
- */
-struct rt_device_graphic_info
-{
-    rt_uint8_t  pixel_format;                           /**< graphic format */
-    rt_uint8_t  bits_per_pixel;                         /**< bits per pixel */
-    rt_uint16_t reserved;                               /**< reserved field */
-
-    rt_uint16_t width;                                  /**< width of graphic device */
-    rt_uint16_t height;                                 /**< height of graphic device */
-
-    rt_uint8_t *framebuffer;                            /**< frame buffer */
-};
-
-/**
- * rectangle information structure
- */
-struct rt_device_rect_info
-{
-    rt_uint16_t x;                                      /**< x coordinate */
-    rt_uint16_t y;                                      /**< y coordinate */
-    rt_uint16_t width;                                  /**< width */
-    rt_uint16_t height;                                 /**< height */
-};
-
-/**
- * graphic operations
- */
-struct rt_device_graphic_ops
-{
-    void (*set_pixel) (const char *pixel, int x, int y);
-    void (*get_pixel) (char *pixel, int x, int y);
-
-    void (*draw_hline)(const char *pixel, int x1, int x2, int y);
-    void (*draw_vline)(const char *pixel, int x, int y1, int y2);
-
-    void (*blit_line) (const char *pixel, int x, int y, rt_size_t size);
-};
-#define rt_graphix_ops(device)          ((struct rt_device_graphic_ops *)(device->user_data))
-
 /**@}*/
 #endif
 
-/* definitions for libc */
-#include "rtlibc.h"
-
 #ifdef __cplusplus
 }
 #endif

include/rthw.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -35,7 +35,7 @@ extern "C" {
 #endif
 
 #ifndef RT_CPU_CACHE_LINE_SZ
-#define RT_CPU_CACHE_LINE_SZ	32
+#define RT_CPU_CACHE_LINE_SZ    32
 #endif
 
 enum RT_HW_CACHE_OPS
@@ -98,14 +98,14 @@ void rt_hw_interrupt_enable(rt_base_t level);
 /*
  * Context interfaces
  */
-void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to);
-void rt_hw_context_switch_to(rt_uint32_t to);
-void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to);
+void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
+void rt_hw_context_switch_to(rt_ubase_t to);
+void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
 
 void rt_hw_console_output(const char *str);
 
-void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry);
-void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size);
+void rt_hw_backtrace(rt_uint32_t *fp, rt_ubase_t thread_entry);
+void rt_hw_show_memory(rt_uint32_t addr, rt_size_t size);
 
 /*
  * Exception interfaces
@@ -117,7 +117,7 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context));
  */
 void rt_hw_us_delay(rt_uint32_t us);
 
-#define RT_DEFINE_SPINLOCK(x)  
+#define RT_DEFINE_SPINLOCK(x)
 #define RT_DECLARE_SPINLOCK(x)    rt_ubase_t x
 
 #define rt_hw_spin_lock(lock)     *(lock) = rt_hw_interrupt_disable()

include/rtlibc.h

@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2017-01-21     Bernard      the first version
- */
-
-#ifndef RTLIBC_H__
-#define RTLIBC_H__
-
-/* definitions for libc if toolchain has no these definitions */
-#include "libc/libc_stat.h"
-#include "libc/libc_errno.h"
-
-#include "libc/libc_fcntl.h"
-#include "libc/libc_ioctl.h"
-#include "libc/libc_dirent.h"
-#include "libc/libc_signal.h"
-//#include "libc/libc_fdset.h"
-
-#if defined(__CC_ARM) || defined(__CLANG_ARM) || defined(__IAR_SYSTEMS_ICC__)
-typedef signed long off_t;
-typedef int mode_t;
-#endif
-
-#if defined(__MINGW32__) || defined(_WIN32)
-typedef signed long off_t;
-typedef int mode_t;
-#endif
-
-#endif
-

include/rtm.h

@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __RTM_H__
-#define __RTM_H__
-
-#include <rtdef.h>
-#include <rtthread.h>
-
-#ifdef RT_USING_MODULE
-struct rt_module_symtab
-{
-    void       *addr;
-    const char *name;
-};
-
-#if defined(_MSC_VER)
-#pragma section("RTMSymTab$f",read)
-#define RTM_EXPORT(symbol)                                            \
-__declspec(allocate("RTMSymTab$f"))const char __rtmsym_##symbol##_name[] = "__vs_rtm_"#symbol;
-#pragma comment(linker, "/merge:RTMSymTab=mytext")
-
-#elif defined(__MINGW32__)
-#define RTM_EXPORT(symbol)
-
-#else
-#define RTM_EXPORT(symbol)                                            \
-const char __rtmsym_##symbol##_name[] SECTION(".rodata.name") = #symbol;     \
-const struct rt_module_symtab __rtmsym_##symbol SECTION("RTMSymTab")= \
-{                                                                     \
-    (void *)&symbol,                                                  \
-    __rtmsym_##symbol##_name                                          \
-};
-#endif
-
-#else
-#define RTM_EXPORT(symbol)
-#endif
-
-#endif

include/rtservice.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -128,21 +128,21 @@ rt_inline unsigned int rt_list_len(const rt_list_t *l)
 
 /**
  * rt_list_for_each - iterate over a list
- * @pos:	the rt_list_t * to use as a loop cursor.
- * @head:	the head for your list.
+ * @pos:    the rt_list_t * to use as a loop cursor.
+ * @head:   the head for your list.
  */
 #define rt_list_for_each(pos, head) \
     for (pos = (head)->next; pos != (head); pos = pos->next)
 
 /**
  * rt_list_for_each_safe - iterate over a list safe against removal of list entry
- * @pos:	the rt_list_t * to use as a loop cursor.
- * @n:		another rt_list_t * to use as temporary storage
- * @head:	the head for your list.
+ * @pos:    the rt_list_t * to use as a loop cursor.
+ * @n:      another rt_list_t * to use as temporary storage
+ * @head:   the head for your list.
  */
 #define rt_list_for_each_safe(pos, n, head) \
-	for (pos = (head)->next, n = pos->next; pos != (head); \
-		pos = n, n = pos->next)
+    for (pos = (head)->next, n = pos->next; pos != (head); \
+        pos = n, n = pos->next)
 
 /**
  * rt_list_for_each_entry  -   iterate over list of given type

include/rtthread.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,7 +22,6 @@
 #include <rtdebug.h>
 #include <rtdef.h>
 #include <rtservice.h>
-#include <rtm.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -40,6 +39,9 @@ extern "C" {
 void rt_system_object_init(void);
 struct rt_object_information *
 rt_object_get_information(enum rt_object_class_type type);
+int rt_object_get_length(enum rt_object_class_type type);
+int rt_object_get_pointers(enum rt_object_class_type type, rt_object_t *pointers, int maxlen);
+
 void rt_object_init(struct rt_object         *object,
                     enum rt_object_class_type type,
                     const char               *name);
@@ -137,18 +139,13 @@ rt_err_t rt_thread_delete(rt_thread_t thread);
 
 rt_err_t rt_thread_yield(void);
 rt_err_t rt_thread_delay(rt_tick_t tick);
+rt_err_t rt_thread_delay_until(rt_tick_t *tick, rt_tick_t inc_tick);
 rt_err_t rt_thread_mdelay(rt_int32_t ms);
 rt_err_t rt_thread_control(rt_thread_t thread, int cmd, void *arg);
 rt_err_t rt_thread_suspend(rt_thread_t thread);
 rt_err_t rt_thread_resume(rt_thread_t thread);
 void rt_thread_timeout(void *parameter);
 
-#ifdef RT_USING_SIGNALS
-void rt_thread_alloc_sig(rt_thread_t tid);
-void rt_thread_free_sig(rt_thread_t tid);
-int  rt_thread_kill(rt_thread_t tid, int sig);
-#endif
-
 #ifdef RT_USING_HOOK
 void rt_thread_suspend_sethook(void (*hook)(rt_thread_t thread));
 void rt_thread_resume_sethook (void (*hook)(rt_thread_t thread));
@@ -186,20 +183,6 @@ void rt_scheduler_sethook(void (*hook)(rt_thread_t from, rt_thread_t to));
 
 /**@}*/
 
-/**
- * @addtogroup Signals
- * @{
- */
-#ifdef RT_USING_SIGNALS
-void rt_signal_mask(int signo);
-void rt_signal_unmask(int signo);
-rt_sighandler_t rt_signal_install(int signo, rt_sighandler_t handler);
-int rt_signal_wait(const rt_sigset_t *set, rt_siginfo_t *si, rt_int32_t timeout);
-
-int rt_system_signal_init(void);
-#endif
-/*@}*/
-
 /**
  * @addtogroup MM
  */
@@ -348,11 +331,11 @@ rt_err_t rt_mb_detach(rt_mailbox_t mb);
 rt_mailbox_t rt_mb_create(const char *name, rt_size_t size, rt_uint8_t flag);
 rt_err_t rt_mb_delete(rt_mailbox_t mb);
 
-rt_err_t rt_mb_send(rt_mailbox_t mb, rt_uint32_t value);
+rt_err_t rt_mb_send(rt_mailbox_t mb, rt_ubase_t value);
 rt_err_t rt_mb_send_wait(rt_mailbox_t mb,
-                         rt_uint32_t  value,
+                         rt_ubase_t  value,
                          rt_int32_t   timeout);
-rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_uint32_t *value, rt_int32_t timeout);
+rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout);
 rt_err_t rt_mb_control(rt_mailbox_t mb, int cmd, void *arg);
 #endif
 
@@ -373,8 +356,12 @@ rt_mq_t rt_mq_create(const char *name,
                      rt_uint8_t  flag);
 rt_err_t rt_mq_delete(rt_mq_t mq);
 
-rt_err_t rt_mq_send(rt_mq_t mq, void *buffer, rt_size_t size);
-rt_err_t rt_mq_urgent(rt_mq_t mq, void *buffer, rt_size_t size);
+rt_err_t rt_mq_send(rt_mq_t mq, const void *buffer, rt_size_t size);
+rt_err_t rt_mq_send_wait(rt_mq_t     mq,
+                         const void *buffer,
+                         rt_size_t   size,
+                         rt_int32_t  timeout);
+rt_err_t rt_mq_urgent(rt_mq_t mq, const void *buffer, rt_size_t size);
 rt_err_t rt_mq_recv(rt_mq_t    mq,
                     void      *buffer,
                     rt_size_t  size,
@@ -509,7 +496,7 @@ rt_int32_t rt_sscanf(const char *buf, const char *fmt, ...);
 char *rt_strncpy(char *dest, const char *src, rt_ubase_t n);
 void *rt_memmove(void *dest, const void *src, rt_ubase_t n);
 rt_int32_t rt_memcmp(const void *cs, const void *ct, rt_ubase_t count);
-rt_uint32_t rt_strcasecmp(const char *a, const char *b);
+rt_int32_t rt_strcasecmp(const char *a, const char *b);
 
 void rt_show_version(void);
 

libcpu/arm/arm926/context_gcc.S

@@ -10,6 +10,7 @@
 
 #define NOINT   0xC0
 
+.text
 ;/*
 ; * rt_base_t rt_hw_interrupt_disable();
 ; */

libcpu/arm/arm926/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,30 +23,30 @@ rt_inline rt_uint32_t cp15_rd(void)
 {
     rt_uint32_t i;
 
-    __asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    __asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r"(i));
     return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
     __asm volatile(\
-                         "mrc  p15,0,r0,c1,c0,0\n\t"    \
-                         "orr  r0,r0,%0\n\t"            \
-                         "mcr  p15,0,r0,c1,c0,0"        \
-                         :                              \
-                         :"r" (bit)                     \
-                         :"memory");
+                   "mrc  p15,0,r0,c1,c0,0\n\t"    \
+                   "orr  r0,r0,%0\n\t"            \
+                   "mcr  p15,0,r0,c1,c0,0"        \
+                   :                              \
+                   : "r"(bit)                     \
+                   : "memory");
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
     __asm volatile(\
-                         "mrc  p15,0,r0,c1,c0,0\n\t"    \
-                         "bic  r0,r0,%0\n\t"            \
-                         "mcr  p15,0,r0,c1,c0,0"        \
-                         :                              \
-                         :"r" (bit)                     \
-                         :"memory");
+                   "mrc  p15,0,r0,c1,c0,0\n\t"    \
+                   "bic  r0,r0,%0\n\t"            \
+                   "mcr  p15,0,r0,c1,c0,0"        \
+                   :                              \
+                   : "r"(bit)                     \
+                   : "memory");
 }
 #endif
 
@@ -152,7 +152,7 @@ void rt_hw_cpu_reset()
     rt_kprintf("Restarting system...\n");
     machine_reset();
 
-    while(1);    /* loop forever and wait for reset to happen */
+    while (1);   /* loop forever and wait for reset to happen */
 
     /* NEVER REACHED */
 }
@@ -206,21 +206,7 @@ int __rt_ffs(int value)
 #elif defined(__GNUC__) || defined(__ICCARM__)
 int __rt_ffs(int value)
 {
-    register rt_uint32_t x;
-
-    if (value == 0)
-        return value;
-
-    __asm
-    (
-        "rsb %[temp], %[val], #0\n"
-        "and %[temp], %[temp], %[val]\n"
-        "clz %[temp], %[temp]\n"
-        "rsb %[temp], %[temp], #32\n"
-        :[temp] "=r"(x)
-        :[val] "r"(value)
-    );
-    return x;
+    return __builtin_ffs(value);
 }
 #endif
 

libcpu/arm/arm926/machine.c

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-02-08     RT-Thread    the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+RT_WEAK void machine_reset(void)
+{
+    rt_kprintf("reboot system...\n");
+    rt_hw_interrupt_disable();
+    while (1);
+}
+
+RT_WEAK void machine_shutdown(void)
+{
+    rt_kprintf("shutdown...\n");
+    rt_hw_interrupt_disable();
+    while (1);
+}
+

libcpu/arm/arm926/mmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -140,7 +140,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-    while(ptr < buffer + size)
+    while (ptr < buffer + size)
     {
         __asm volatile { MCR p15, 0, ptr, c7, c14, 1 }
         ptr += CACHE_LINE_SIZE;
@@ -211,18 +211,18 @@ void mmu_setttbase(register rt_uint32_t i)
      * set by page table entry
      */
     value = 0;
-    asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
+    asm volatile("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
 
     value = 0x55555555;
-    asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
+    asm volatile("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
 
-    asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
+    asm volatile("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
 
 }
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-    asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+    asm volatile("mcr p15,0, %0, c3, c0,  0": :"r"(i));
 }
 
 void mmu_enable()
@@ -321,7 +321,7 @@ void mmu_disable_alignfault()
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-    asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+    asm volatile("mcr p15, 0, %0, c7, c14, 2": :"r"(index));
 }
 
 void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
@@ -330,9 +330,9 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-    while(ptr < buffer + size)
+    while (ptr < buffer + size)
     {
-        asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
+        asm volatile("mcr p15, 0, %0, c7, c14, 1": :"r"(ptr));
 
         ptr += CACHE_LINE_SIZE;
     }
@@ -347,7 +347,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     while (ptr < buffer + size)
     {
-        asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+        asm volatile("mcr p15, 0, %0, c7, c10, 1": :"r"(ptr));
 
         ptr += CACHE_LINE_SIZE;
     }
@@ -361,7 +361,7 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     while (ptr < buffer + size)
     {
-        asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+        asm volatile("mcr p15, 0, %0, c7, c6, 1": :"r"(ptr));
 
         ptr += CACHE_LINE_SIZE;
     }
@@ -369,19 +369,19 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 void mmu_invalidate_tlb()
 {
-    asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+    asm volatile("mcr p15, 0, %0, c8, c7, 0": :"r"(0));
 
 }
 
 void mmu_invalidate_icache()
 {
-    asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+    asm volatile("mcr p15, 0, %0, c7, c5, 0": :"r"(0));
 
 }
 
 void mmu_invalidate_dcache_all()
 {
-    asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
+    asm volatile("mcr p15, 0, %0, c7, c6, 0": :"r"(0));
 
 }
 #endif
@@ -389,10 +389,10 @@ void mmu_invalidate_dcache_all()
 /* level1 page table */
 #if defined(__ICCARM__)
 #pragma data_alignment=(16*1024)
-static volatile rt_uint32_t _page_table[4*1024];
+static volatile rt_uint32_t _page_table[4 * 1024];
 #else
-static volatile rt_uint32_t _page_table[4*1024] \
-    __attribute__((aligned(16*1024)));
+static volatile rt_uint32_t _page_table[4 * 1024] \
+__attribute__((aligned(16 * 1024)));
 #endif
 
 void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
@@ -401,11 +401,11 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
     volatile rt_uint32_t *pTT;
     volatile int nSec;
     int i = 0;
-    pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
-    nSec=(vaddrEnd>>20)-(vaddrStart>>20);
-    for(i=0; i<=nSec; i++)
+    pTT = (rt_uint32_t *)_page_table + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for (i = 0; i <= nSec; i++)
     {
-        *pTT = attr |(((paddrStart>>20)+i)<<20);
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
         pTT++;
     }
 }

libcpu/arm/arm926/mmu.h

@@ -1,10 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
+ * 2018-02-08     RT-Thread    the first version
  */
 
 #ifndef __MMU_H__
@@ -45,5 +46,7 @@ struct mem_desc
 };
 
 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
-
+void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size);
+void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
+void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
 #endif

libcpu/arm/arm926/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,7 +38,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
 
     stack_addr += sizeof(rt_uint32_t);
     stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
-    stk      = (rt_uint32_t *)stack_addr;
+    stk  = (rt_uint32_t *)stack_addr;
 
     *(--stk) = (rt_uint32_t)tentry;         /* entry point */
     *(--stk) = (rt_uint32_t)texit;          /* lr */

libcpu/arm/arm926/start_gcc.S

@@ -11,295 +11,320 @@
  * 2015-06-04     aozima     Align stack address to 8 byte.
  */
 
-#include "rt_low_level_init.h"
-
-#define S_FRAME_SIZE    (18*4)   //72
-
-@#define S_SPSR          (17*4)   //SPSR
-@#define S_CPSR          (16*4)   //CPSR
-#define S_PC            (15*4)   //R15
-@#define S_LR            (14*4)   //R14
-@#define S_SP            (13*4)   //R13
-
-@#define S_IP            (12*4)   //R12
-@#define S_FP            (11*4)   //R11
-@#define S_R10           (10*4)
-@#define S_R9            (9*4)
-@#define S_R8            (8*4)
-@#define S_R7            (7*4)
-@#define S_R6            (6*4)
-@#define S_R5            (5*4)
-@#define S_R4            (4*4)
-@#define S_R3            (3*4)
-@#define S_R2            (2*4)
-@#define S_R1            (1*4)
-@#define S_R0            (0*4)
-
-#define MODE_SYS        0x1F
-#define MODE_FIQ        0x11
-#define MODE_IRQ        0x12
-#define MODE_SVC        0x13
-#define MODE_ABT        0x17
-#define MODE_UND        0x1B
-#define MODEMASK        0x1F
-
-#define NOINT           0xC0
-
-@;----------------------- Stack and Heap Definitions ---------------------------
-    .section .nobss, "w"
-
-    .space UND_STK_SIZE
+.equ MODE_USR,        0x10
+.equ MODE_FIQ,        0x11
+.equ MODE_IRQ,        0x12
+.equ MODE_SVC,        0x13
+.equ MODE_ABT,        0x17
+.equ MODE_UND,        0x1B
+.equ MODE_SYS,        0x1F
+.equ MODEMASK,        0x1F
+.equ NOINT,           0xC0
+
+.equ I_BIT,           0x80
+.equ F_BIT,           0x40
+
+.equ UND_STACK_SIZE,  0x00000100
+.equ SVC_STACK_SIZE,  0x00000100
+.equ ABT_STACK_SIZE,  0x00000100
+.equ FIQ_STACK_SIZE,  0x00000100
+.equ IRQ_STACK_SIZE,  0x00000100
+.equ SYS_STACK_SIZE,  0x00000100
+
+ /*
+ ***************************************
+ * Interrupt vector table
+ ***************************************
+ */
+.section .vectors
+.code 32
+
+.global system_vectors
+system_vectors:
+    ldr pc, _vector_reset
+    ldr pc, _vector_undef
+    ldr pc, _vector_swi
+    ldr pc, _vector_pabt
+    ldr pc, _vector_dabt
+    ldr pc, _vector_resv
+    ldr pc, _vector_irq
+    ldr pc, _vector_fiq
+
+_vector_reset:
+    .word reset
+_vector_undef:
+    .word vector_undef
+_vector_swi:
+    .word vector_swi
+_vector_pabt:
+    .word vector_pabt
+_vector_dabt:
+    .word vector_dabt
+_vector_resv:
+    .word vector_resv
+_vector_irq:
+    .word vector_irq
+_vector_fiq:
+    .word vector_fiq
+
+.balignl    16,0xdeadbeef
+
+ /*
+ ***************************************
+ *  Stack and Heap Definitions 
+ ***************************************
+ */
+    .section .data
+    .space UND_STACK_SIZE
     .align 3
-    .global UND_STACK_START
-UND_STACK_START:
+    .global und_stack_start
+und_stack_start:
 
-    .space ABT_STK_SIZE
+    .space ABT_STACK_SIZE
     .align 3
-    .global ABT_STACK_START
-ABT_STACK_START:
+    .global abt_stack_start
+abt_stack_start:
 
-    .space FIQ_STK_SIZE
+    .space FIQ_STACK_SIZE
     .align 3
-    .global FIQ_STACK_START
-FIQ_STACK_START:
+    .global fiq_stack_start
+fiq_stack_start:
 
-    .space IRQ_STK_SIZE
+    .space IRQ_STACK_SIZE
     .align 3
-    .global IRQ_STACK_START
-IRQ_STACK_START:
+    .global irq_stack_start
+irq_stack_start:
 
-    .skip SYS_STK_SIZE
+    .skip SYS_STACK_SIZE
     .align 3
-    .global SYS_STACK_START
-SYS_STACK_START:
+    .global sys_stack_start
+sys_stack_start:
 
-    .space SVC_STK_SIZE
+    .space SVC_STACK_SIZE
     .align 3
-    .global SVC_STACK_START
-SVC_STACK_START:
-
-@;--------------Jump vector table-----------------------------------------------
-    .section .init, "ax"
-    .arm
-
-    .global start
-start:
-    LDR     PC, vector_reset
-    LDR     PC, vector_undef
-    LDR     PC, vector_swi
-    LDR     PC, vector_pabt
-    LDR     PC, vector_dabt
-    LDR     PC, vector_resv
-    LDR     PC, vector_irq
-    LDR     PC, vector_fiq
-
-vector_reset:
-    .word  Reset_Handler
-vector_undef:
-    .word  Undef_Handler
-vector_swi:
-    .word  SWI_Handler
-vector_pabt:
-    .word  PAbt_Handler
-vector_dabt:
-    .word  DAbt_Handler
-vector_resv:
-    .word  Resv_Handler
-vector_irq:
-    .word  IRQ_Handler
-vector_fiq:
-    .word  FIQ_Handler
-
-    .balignl     16,0xdeadbeef
-
-@;----------------- Reset Handler ---------------------------------------------
-    .global rt_low_level_init
-    .global main
-    .global Reset_Handler
-Reset_Handler:
-    @; Set the cpu to SVC32 mode
-    MRS     R0, CPSR
-    BIC     R0, R0, #MODEMASK
-    ORR     R0, R0, #MODE_SVC|NOINT
-    MSR     CPSR_cxsf, R0
+    .global svc_stack_start
+svc_stack_start:
+
+/*
+ ***************************************
+ * Startup Code 
+ ***************************************
+ */
+    .section .text
+    .global reset
+reset:
+    /* Enter svc mode and mask interrupts */
+    mrs r0, cpsr
+    bic r0, r0, #MODEMASK
+    orr r0, r0, #MODE_SVC|NOINT
+    msr cpsr_cxsf, r0
+
+    /* init cpu  */
+    bl  cpu_init_crit
+    
+    /* todo:copyself to link address */
+    
+    /* Copy vector to the correct address */
+    ldr r0, =system_vectors
+    mrc p15, 0, r2, c1, c0, 0
+    ands r2, r2, #(1 << 13)
+    ldreq r1, =0x00000000
+    ldrne r1, =0xffff0000
+    ldmia r0!, {r2-r8, r10}
+    stmia r1!, {r2-r8, r10}
+    ldmia r0!, {r2-r8, r10}
+    stmia r1!, {r2-r8, r10}
+
+    /* turn off the watchdog */
+    ldr r0, =0x01C20CB8
+    mov     r1, #0x0
+    str     r1, [r0]
+
+    /* mask all IRQs source */
+    ldr r1, =0xffffffff
+    ldr r0, =0x01C20430
+    str r1, [r0], #0x04
+    str r1, [r0]
+    
+    /* Call low level init function */
+    ldr     sp, =svc_stack_start
+    ldr     r0, =rt_low_level_init
+    blx     r0
+    
+    /* init stack */
+    bl stack_setup
     
-    @; Set CO-Processor
-    @; little-end锛宒isbale I/D Cache MMU, vector table is 0x00000000
-    MRC     P15, 0, R0, C1, C0, 0   @; Read CP15
-    LDR     R1, =0x00003085         @; set clear bits
-    BIC     R0, R0, R1
-    MCR     P15, 0, R0, C1, C0, 0   @; Write CP15
-
-    @; Call low level init function,
-    @; disable and clear all IRQs, Init MMU, Init interrupt controller, etc.
-    LDR     SP, =SVC_STACK_START
-    LDR     R0, =rt_low_level_init
-    BLX     R0
-
-Setup_Stack:
-    @; Setup Stack for each mode
-    MRS     R0, CPSR
-    BIC     R0, R0, #MODEMASK
-
-    ORR     R1, R0, #MODE_UND|NOINT
-    MSR     CPSR_cxsf, R1            @; Undef mode
-    LDR     SP, =UND_STACK_START
-
-    ORR     R1, R0, #MODE_ABT|NOINT
-    MSR     CPSR_cxsf, R1            @; Abort mode
-    LDR     SP, =ABT_STACK_START
-
-    ORR     R1, R0, #MODE_IRQ|NOINT
-    MSR     CPSR_cxsf, R1            @; IRQ mode
-    LDR     SP, =IRQ_STACK_START
-
-    ORR     R1, R0, #MODE_FIQ|NOINT
-    MSR     CPSR_cxsf, R1            @; FIQ mode
-    LDR     SP, =FIQ_STACK_START
-
-    ORR     R1, R0, #MODE_SYS|NOINT
-    MSR     CPSR_cxsf,R1             @; SYS/User mode
-    LDR     SP, =SYS_STACK_START
-
-    ORR     R1, R0, #MODE_SVC|NOINT
-    MSR     CPSR_cxsf, R1            @; SVC mode
-    LDR     SP, =SVC_STACK_START
-
-    @; clear .bss
-    MOV     R0, #0                   @; get a zero
-    LDR     R1, =__bss_start__       @; bss start
-    LDR     R2, =__bss_end__         @; bss end
+    /* clear bss */
+    mov     r0, #0
+    ldr     r1, =__bss_start
+    ldr     r2, =__bss_end
 
 bss_clear_loop:
-    CMP     R1, R2                   @; check if data to clear
-    STRLO   R0, [R1], #4             @; clear 4 bytes
-    BLO     bss_clear_loop           @; loop until done
-
-    @; call C++ constructors of global objects
-    LDR     R0, =__ctors_start__
-    LDR     R1, =__ctors_end__
+    cmp     r1, r2
+    strlo   r0, [r1], #4
+    blo     bss_clear_loop
+       
+    /* call c++ constructors of global objects */
+    /*
+    ldr     r0, =__ctors_start__
+    ldr     r1, =__ctors_end__
 
 ctor_loop:
-    CMP     R0, R1
-    BEQ     ctor_end
-    LDR     R2, [R0], #4
-    STMFD   SP!, {R0-R1}
-    MOV     LR, PC
-    BX      R2
-    LDMFD   SP!, {R0-R1}
-    B       ctor_loop
+    cmp     r0, r1
+    beq     ctor_end
+    ldr     r2, [r0], #4
+    stmfd   sp!, {r0-r1}
+    mov     lr, pc
+    bx      r2
+    ldmfd   sp!, {r0-r1}
+    b       ctor_loop
 ctor_end:
+    */
+    /* start RT-Thread Kernel */
+    ldr     pc, _rtthread_startup
+_rtthread_startup:
+    .word  rtthread_startup
+
+
+
+cpu_init_crit:
+    /* invalidate I/D caches */
+    mov r0, #0
+    mcr p15, 0, r0, c7, c7, 0
+    mcr p15, 0, r0, c8, c7, 0
+
+    /* disable MMU stuff and caches */
+    mrc p15, 0, r0, c1, c0, 0
+    bic r0, r0, #0x00002300
+    bic r0, r0, #0x00000087
+    orr r0, r0, #0x00000002
+    orr r0, r0, #0x00001000
+    mcr p15, 0, r0, c1, c0, 0
+
+    bx lr
+ 
+stack_setup:
+    /* Setup Stack for each mode */
+    mrs     r0, cpsr
+    bic     r0, r0, #MODEMASK
+
+    orr     r1, r0, #MODE_UND|NOINT
+    msr     cpsr_cxsf, r1
+    ldr     sp, =und_stack_start
+
+    orr     r1, r0, #MODE_ABT|NOINT
+    msr     cpsr_cxsf, r1
+    ldr     sp, =abt_stack_start
+
+    orr     r1, r0, #MODE_IRQ|NOINT
+    msr     cpsr_cxsf, r1
+    ldr     sp, =irq_stack_start
+
+    orr     r1, r0, #MODE_FIQ|NOINT
+    msr     cpsr_cxsf, r1
+    ldr     sp, =fiq_stack_start
+
+    orr     r1, r0, #MODE_SYS|NOINT
+    msr     cpsr_cxsf,r1
+    ldr     sp, =sys_stack_start
+
+    orr     r1, r0, #MODE_SVC|NOINT
+    msr     cpsr_cxsf, r1
+    ldr     sp, =svc_stack_start
+
+    bx      lr
+ 
+/*
+ ***************************************
+ * exception handlers 
+ ***************************************
+ */
+    /* Interrupt */
+vector_fiq:
+    stmfd   sp!,{r0-r7,lr}
+    bl      rt_hw_trap_fiq
+    ldmfd   sp!,{r0-r7,lr}
+    subs    pc, lr, #4
 
-    @; Enter the C code
-    LDR     R0, =rtthread_startup
-    BLX     R0
-
-@;----------------- Exception Handler -----------------------------------------
-    .global rt_hw_trap_udef
-    .global rt_hw_trap_swi
-    .global rt_hw_trap_pabt
-    .global rt_hw_trap_dabt
-    .global rt_hw_trap_resv
-    .global rt_hw_trap_irq
-    .global rt_hw_trap_fiq
-
-    .global rt_interrupt_enter
-    .global rt_interrupt_leave
-    .global rt_thread_switch_interrupt_flag
-    .global rt_interrupt_from_thread
-    .global rt_interrupt_to_thread
-    
-    .align  5
-Undef_Handler:
-    SUB     SP, SP, #S_FRAME_SIZE
-    STMIA   SP, {R0 - R12}          @; Calling R0-R12
-    ADD     R8, SP, #S_PC
-    STMDB   R8, {SP, LR}            @; Calling SP, LR
-    STR     LR, [R8, #0]            @; Save calling PC
-    MRS     R6, SPSR
-    STR     R6, [R8, #4]            @; Save CPSR
-    STR     R0, [R8, #8]            @; Save SPSR
-    MOV     R0, SP
-    BL      rt_hw_trap_udef
-    
-    .align  5
-SWI_Handler:
-    BL      rt_hw_trap_swi
-    
-    .align  5
-PAbt_Handler:
-    BL      rt_hw_trap_pabt
-
-    .align  5
-DAbt_Handler:
-    SUB     SP, SP, #S_FRAME_SIZE
-    STMIA   SP, {R0 - R12}          @; Calling R0-R12
-    ADD     R8, SP, #S_PC
-    STMDB   R8, {SP, LR}            @; Calling SP, LR
-    STR     LR, [R8, #0]            @; Save calling PC
-    MRS     R6, SPSR
-    STR     R6, [R8, #4]            @; Save CPSR
-    STR     R0, [R8, #8]            @; Save SPSR
-    MOV     R0, SP
-    BL      rt_hw_trap_dabt
-
-    .align  5
-Resv_Handler:
-    BL      rt_hw_trap_resv
-
-    .align  5
-FIQ_Handler:
-    STMFD   SP!, {R0-R7,LR}
-    BL      rt_hw_trap_fiq
-    LDMFD   SP!, {R0-R7,LR}
-    SUBS    PC, LR, #4
-
-    .align  5
-IRQ_Handler:
-    STMFD   SP!, {R0-R12,LR}
-    BL      rt_interrupt_enter
-    BL      rt_hw_trap_irq
-    BL      rt_interrupt_leave
-
-    @; If rt_thread_switch_interrupt_flag set,
-    @; jump to rt_hw_context_switch_interrupt_do and don't return
-    LDR     R0, =rt_thread_switch_interrupt_flag
-    LDR     R1, [R0]
-    CMP     R1, #1
-    BEQ     rt_hw_context_switch_interrupt_do
-
-    LDMFD   SP!, {R0-R12,LR}
-    SUBS    PC, LR, #4
-
-@;------ void rt_hw_context_switch_interrupt_do(rt_base_t flag) -----------------
-rt_hw_context_switch_interrupt_do:
-    MOV     R1,  #0                 @; Clear flag
-    STR     R1,  [R0]               @; Save to flag variable
+vector_irq:
+    stmfd   sp!, {r0-r12,lr}
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
 
-    LDMFD   SP!, {R0-R12,LR}        @; Reload saved registers
-    STMFD   SP, {R0-R2}             @; Save R0-R2
-    SUB     R1,  SP, #4*3           @; Save old task's SP to R1
-    SUB     R2,  LR, #4             @; Save old task's PC to R2
+    ldr     r0, =rt_thread_switch_interrupt_flag
+    ldr     r1, [r0]
+    cmp     r1, #1
+    beq     rt_hw_context_switch_interrupt_do
 
-    MRS     R0,  SPSR               @; Get CPSR of interrupt thread
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc,  lr, #4
 
-    MSR     CPSR_c, #MODE_SVC|NOINT @; Switch to SVC mode and no interrupt
+rt_hw_context_switch_interrupt_do:
+    mov     r1,  #0         
+    str     r1,  [r0]
+
+    mov     r1, sp          
+    add     sp, sp, #4*4
+    ldmfd   sp!, {r4-r12,lr}
+    mrs     r0,  spsr       
+    sub     r2,  lr, #4     
+
+    msr     cpsr_c, #I_BIT|F_BIT|MODE_SVC
+
+    stmfd   sp!, {r2}       
+    stmfd   sp!, {r4-r12,lr}
+    ldmfd   r1,  {r1-r4}    
+    stmfd   sp!, {r1-r4}    
+    stmfd   sp!, {r0}       
+
+    ldr     r4,  =rt_interrupt_from_thread
+    ldr     r5,  [r4]
+    str     sp,  [r5]       
+
+    ldr     r6,  =rt_interrupt_to_thread
+    ldr     r6,  [r6]
+    ldr     sp,  [r6]       
+
+    ldmfd   sp!, {r4}       
+    msr     spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}^ 
+
+    /* Exception */
+.macro push_svc_reg
+    sub     sp, sp, #17 * 4
+    stmia   sp, {r0 - r12} 
+    mov     r0, sp
+    mrs     r6, spsr       
+    str     lr, [r0, #15*4]
+    str     r6, [r0, #16*4]
+    str     sp, [r0, #13*4]
+    str     lr, [r0, #14*4]
+.endm
 
-    STMFD   SP!, {R2}               @; Push old task's PC
-    STMFD   SP!, {R3-R12,LR}        @; Push old task's LR,R12-R3
-    LDMFD   R1, {R1-R3}
-    STMFD   SP!, {R1-R3}            @; Push old task's R2-R0
-    STMFD   SP!, {R0}               @; Push old task's CPSR
+vector_swi:
+    push_svc_reg
+    bl      rt_hw_trap_swi
+    b       .
 
-    LDR     R4,  =rt_interrupt_from_thread
-    LDR     R5,  [R4]               @; R5 = stack ptr in old tasks's TCB
-    STR     SP,  [R5]               @; Store SP in preempted tasks's TCB
+vector_undef:
+    push_svc_reg
+    bl      rt_hw_trap_udef
+    b       .
 
-    LDR     R6,  =rt_interrupt_to_thread
-    LDR     R6,  [R6]               @; R6 = stack ptr in new tasks's TCB
-    LDR     SP,  [R6]               @; Get new task's stack pointer
+vector_pabt:
+    push_svc_reg
+    bl      rt_hw_trap_pabt
+    b       .
 
-    LDMFD   SP!, {R4}               @; Pop new task's SPSR
-    MSR     SPSR_cxsf, R4
+vector_dabt:
+    push_svc_reg
+    bl      rt_hw_trap_dabt
+    b       .
 
-    LDMFD   SP!, {R0-R12,LR,PC}^    @; pop new task's R0-R12,LR & PC SPSR 2 CPSR
+vector_resv:
+    push_svc_reg
+    bl      rt_hw_trap_resv
+    b       .

libcpu/arm/arm926/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -41,14 +41,18 @@ struct rt_hw_register
     rt_uint32_t cpsr;
     rt_uint32_t ORIG_r0;
 };
-
+static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
+void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
+{
+    rt_exception_hook = exception_handle;
+}
 /**
  * this function will show registers of CPU
  *
  * @param regs the registers point
  */
 
-void rt_hw_show_register (struct rt_hw_register *regs)
+void rt_hw_show_register(struct rt_hw_register *regs)
 {
     rt_kprintf("Execption:\n");
     rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n",
@@ -74,6 +78,13 @@ void rt_hw_show_register (struct rt_hw_register *regs)
  */
 void rt_hw_trap_udef(struct rt_hw_register *regs)
 {
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(regs);
+        if (result == RT_EOK) return;
+    }
     rt_hw_show_register(regs);
 
     rt_kprintf("undefined instruction\n");
@@ -96,6 +107,13 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
  */
 void rt_hw_trap_swi(struct rt_hw_register *regs)
 {
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(regs);
+        if (result == RT_EOK) return;
+    }
     rt_hw_show_register(regs);
 
     rt_kprintf("software interrupt\n");
@@ -112,6 +130,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
  */
 void rt_hw_trap_pabt(struct rt_hw_register *regs)
 {
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(regs);
+        if (result == RT_EOK) return;
+    }
     rt_hw_show_register(regs);
 
     rt_kprintf("prefetch abort\n");
@@ -133,6 +158,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_dabt(struct rt_hw_register *regs)
 {
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(regs);
+        if (result == RT_EOK) return;
+    }
     rt_hw_show_register(regs);
 
     rt_kprintf("data abort\n");
@@ -153,55 +185,26 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_resv(struct rt_hw_register *regs)
 {
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(regs);
+        if (result == RT_EOK) return;
+    }
     rt_kprintf("not used\n");
     rt_hw_show_register(regs);
     rt_hw_cpu_shutdown();
 }
 
-extern struct rt_irq_desc irq_desc[];
-extern rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq);
-extern void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id);
-    
-void rt_hw_trap_irq()
-{
-    rt_isr_handler_t isr_func;
-    rt_uint32_t irq;
-    void *param;
-
-    /* get irq number */
-    irq = rt_hw_interrupt_get_active(INT_IRQ);
+extern void rt_interrupt_dispatch(rt_uint32_t fiq_irq);
 
-    /* get interrupt service routine */
-    isr_func = irq_desc[irq].handler;
-    param = irq_desc[irq].param;
-
-    /* turn to interrupt service routine */
-    isr_func(irq, param);
-
-    rt_hw_interrupt_ack(INT_IRQ, irq);
-#ifdef RT_USING_INTERRUPT_INFO
-    irq_desc[irq].counter ++;
-#endif
+void rt_hw_trap_irq(void)
+{
+    rt_interrupt_dispatch(INT_IRQ);
 }
 
-void rt_hw_trap_fiq()
+void rt_hw_trap_fiq(void)
 {
-    rt_isr_handler_t isr_func;
-    rt_uint32_t irq;
-    void *param;
-
-    /* get irq number */
-    irq = rt_hw_interrupt_get_active(INT_FIQ);
-
-    /* get interrupt service routine */
-    isr_func = irq_desc[irq].handler;
-    param = irq_desc[irq].param;
-
-    /* turn to interrupt service routine */
-    isr_func(irq, param);
-
-    rt_hw_interrupt_ack(INT_FIQ, irq);
-#ifdef RT_USING_INTERRUPT_INFO
-    irq_desc[irq].counter ++;
-#endif
+    rt_interrupt_dispatch(INT_FIQ);
 }

libcpu/arm/armv6/armv6.h

@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef __ARMV6_H__
 #define __ARMV6_H__
 
@@ -26,7 +26,7 @@
 #ifndef __ASSEMBLY__
 struct rt_hw_register
 {
-	rt_uint32_t cpsr;
+    rt_uint32_t cpsr;
     rt_uint32_t r0;
     rt_uint32_t r1;
     rt_uint32_t r2;
@@ -46,24 +46,24 @@ struct rt_hw_register
 };
 #if(0)
 struct rt_hw_register{
-	rt_uint32_t r0;
-	rt_uint32_t r1;
-	rt_uint32_t r2;
-	rt_uint32_t r3;
-	rt_uint32_t r4;
-	rt_uint32_t r5;
-	rt_uint32_t r6;
-	rt_uint32_t r7;
-	rt_uint32_t r8;
-	rt_uint32_t r9;
-	rt_uint32_t r10;
-	rt_uint32_t fp;
-	rt_uint32_t ip;
-	rt_uint32_t sp;
-	rt_uint32_t lr;
-	rt_uint32_t pc;
-	rt_uint32_t cpsr;
-	rt_uint32_t ORIG_r0;
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t fp;
+    rt_uint32_t ip;
+    rt_uint32_t sp;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t cpsr;
+    rt_uint32_t ORIG_r0;
 };
 #endif
 #endif

libcpu/arm/armv6/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,8 +11,8 @@
 #include <rthw.h>
 #include <rtthread.h>
 
-#define ICACHE_MASK	(rt_uint32_t)(1 << 12)
-#define DCACHE_MASK	(rt_uint32_t)(1 << 2)
+#define ICACHE_MASK (rt_uint32_t)(1 << 12)
+#define DCACHE_MASK (rt_uint32_t)(1 << 2)
 
 extern void machine_reset(void);
 extern void machine_shutdown(void);
@@ -20,32 +20,32 @@ extern void machine_shutdown(void);
 #ifdef __GNUC__
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	return i;
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"orr  r0,r0,%0\n\t"			\
-	   	"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "orr  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"bic  r0,r0,%0\n\t"			\
-		"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "bic  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 
 
@@ -54,38 +54,38 @@ rt_inline void cache_disable(rt_uint32_t bit)
 #ifdef __CC_ARM
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	__asm
-	{
-		mrc p15, 0, i, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, i, c1, c0, 0
+    }
 
-	return i;
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
+    rt_uint32_t value;
 
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		orr value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
+    rt_uint32_t value;
 
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		bic value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 #endif
 
@@ -95,7 +95,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
  */
 void rt_hw_cpu_icache_enable()
 {
-	cache_enable(ICACHE_MASK);
+    cache_enable(ICACHE_MASK);
 }
 
 /**
@@ -104,7 +104,7 @@ void rt_hw_cpu_icache_enable()
  */
 void rt_hw_cpu_icache_disable()
 {
-	cache_disable(ICACHE_MASK);
+    cache_disable(ICACHE_MASK);
 }
 
 /**
@@ -113,7 +113,7 @@ void rt_hw_cpu_icache_disable()
  */
 rt_base_t rt_hw_cpu_icache_status()
 {
-	return (cp15_rd() & ICACHE_MASK);
+    return (cp15_rd() & ICACHE_MASK);
 }
 
 /**
@@ -122,7 +122,7 @@ rt_base_t rt_hw_cpu_icache_status()
  */
 void rt_hw_cpu_dcache_enable()
 {
-	cache_enable(DCACHE_MASK);
+    cache_enable(DCACHE_MASK);
 }
 
 /**
@@ -131,7 +131,7 @@ void rt_hw_cpu_dcache_enable()
  */
 void rt_hw_cpu_dcache_disable()
 {
-	cache_disable(DCACHE_MASK);
+    cache_disable(DCACHE_MASK);
 }
 
 /**
@@ -140,7 +140,7 @@ void rt_hw_cpu_dcache_disable()
  */
 rt_base_t rt_hw_cpu_dcache_status()
 {
-	return (cp15_rd() & DCACHE_MASK);
+    return (cp15_rd() & DCACHE_MASK);
 }
 
 /**
@@ -149,13 +149,13 @@ rt_base_t rt_hw_cpu_dcache_status()
  */
 void rt_hw_cpu_reset()
 {
-	
-	rt_kprintf("Restarting system...\n");
-	machine_reset();
 
-	while(1);	/* loop forever and wait for reset to happen */
+    rt_kprintf("Restarting system...\n");
+    machine_reset();
 
-	/* NEVER REACHED */
+    while(1);   /* loop forever and wait for reset to happen */
+
+    /* NEVER REACHED */
 }
 
 /**
@@ -164,67 +164,67 @@ void rt_hw_cpu_reset()
  */
 void rt_hw_cpu_shutdown()
 {
-	rt_uint32_t level;
-	rt_kprintf("shutdown...\n");
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
 
-	level = rt_hw_interrupt_disable();
-	machine_shutdown();
-	while (level)
-	{
-		RT_ASSERT(0);
-	}
+    level = rt_hw_interrupt_disable();
+    machine_shutdown();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
 }
 
 #ifdef RT_USING_CPU_FFS
 /**
- * This function finds the first bit set (beginning with the least significant bit) 
+ * This function finds the first bit set (beginning with the least significant bit)
  * in value and return the index of that bit.
  *
- * Bits are numbered starting at 1 (the least significant bit).  A return value of 
+ * Bits are numbered starting at 1 (the least significant bit).  A return value of
  * zero from any of these functions means that the argument was zero.
- * 
- * @return return the index of the first bit set. If value is 0, then this function 
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
  * shall return 0.
  */
 #if defined(__CC_ARM)
 int __rt_ffs(int value)
 {
-	register rt_uint32_t x;
+    register rt_uint32_t x;
+
+    if (value == 0)
+        return value;
 
-	if (value == 0)
-		return value;
-	
-	__asm
-	{
-		rsb x, value, #0
-		and x, x, value
-		clz x, x
-		rsb x, x, #32
-	}
+    __asm
+    {
+        rsb x, value, #0
+        and x, x, value
+        clz x, x
+        rsb x, x, #32
+    }
 
-	return x;
+    return x;
 }
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {
-	if (value == 0)
-		return value;
+    if (value == 0)
+        return value;
 
-	__ASM("RSB  r4, r0, #0");
-	__ASM("AND  r4, r4, r0");
-	__ASM("CLZ  r4, r4");
-	__ASM("RSB  r0, r4, #32");
+    __ASM("RSB  r4, r0, #0");
+    __ASM("AND  r4, r4, r0");
+    __ASM("CLZ  r4, r4");
+    __ASM("RSB  r0, r4, #32");
 }
 #elif defined(__GNUC__)
 int __rt_ffs(int value)
 {
-	if (value == 0)
-		return value;
+    if (value == 0)
+        return value;
 
-	value &= (-value);
-	asm ("clz %0, %1": "=r"(value) :"r"(value));
+    value &= (-value);
+    asm ("clz %0, %1": "=r"(value) :"r"(value));
 
-	return (32 - value);
+    return (32 - value);
 }
 #endif
 

libcpu/arm/armv6/mmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,411 +12,411 @@
 #ifdef __CC_ARM
 void mmu_setttbase(rt_uint32_t i)
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	/* Invalidates all TLBs.Domain access is selected as
-	 * client by configuring domain access register,
-	 * in that case access controlled by permission value
-	 * set by page table entry
-	 */
-	value = 0;
-	__asm volatile
-	{
-		mcr p15, 0, value, c8, c7, 0
-	}
+    /* Invalidates all TLBs.Domain access is selected as
+     * client by configuring domain access register,
+     * in that case access controlled by permission value
+     * set by page table entry
+     */
+    value = 0;
+    __asm volatile
+    {
+        mcr p15, 0, value, c8, c7, 0
+    }
 
-	value = 0x55555555;
-	__asm volatile
-	{
-		mcr p15, 0, value, c3, c0, 0
-			mcr p15, 0, i, c2, c0, 0
-	}
+    value = 0x55555555;
+    __asm volatile
+    {
+        mcr p15, 0, value, c3, c0, 0
+            mcr p15, 0, i, c2, c0, 0
+    }
 }
 
 void mmu_set_domain(rt_uint32_t i)
 {
-	__asm volatile
-	{
-		mcr p15,0, i, c3, c0,  0
-	}
+    __asm volatile
+    {
+        mcr p15,0, i, c3, c0,  0
+    }
 }
 
 void mmu_enable()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			orr value, value, #0x01
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            orr value, value, #0x01
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_disable()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			bic value, value, #0x01
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            bic value, value, #0x01
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_enable_icache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			orr value, value, #0x1000
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            orr value, value, #0x1000
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_enable_dcache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			orr value, value, #0x04
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            orr value, value, #0x04
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_disable_icache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			bic value, value, #0x1000
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            bic value, value, #0x1000
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_disable_dcache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			bic value, value, #0x04
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            bic value, value, #0x04
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_enable_alignfault()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			orr value, value, #0x02
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            orr value, value, #0x02
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_disable_alignfault()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			bic value, value, #0x02
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            bic value, value, #0x02
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	__asm volatile
-	{
-		mcr p15, 0, index, c7, c14, 2
-	}
+    __asm volatile
+    {
+        mcr p15, 0, index, c7, c14, 2
+    }
 }
 
 void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while(ptr < buffer + size)
-	{
-		__asm volatile
-		{
-			MCR p15, 0, ptr, c7, c14, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while(ptr < buffer + size)
+    {
+        __asm volatile
+        {
+            MCR p15, 0, ptr, c7, c14, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		__asm volatile
-		{
-			MCR p15, 0, ptr, c7, c10, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        __asm volatile
+        {
+            MCR p15, 0, ptr, c7, c10, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		__asm volatile
-		{
-			MCR p15, 0, ptr, c7, c6, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        __asm volatile
+        {
+            MCR p15, 0, ptr, c7, c6, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_tlb()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	value = 0;
-	__asm volatile
-	{
-		mcr p15, 0, value, c8, c7, 0
-	}
+    value = 0;
+    __asm volatile
+    {
+        mcr p15, 0, value, c8, c7, 0
+    }
 }
 
 void mmu_invalidate_icache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	value = 0;
+    value = 0;
 
-	__asm volatile
-	{
-		mcr p15, 0, value, c7, c5, 0
-	}
+    __asm volatile
+    {
+        mcr p15, 0, value, c7, c5, 0
+    }
 }
 
 
 void mmu_invalidate_dcache_all()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	value = 0;
+    value = 0;
 
-	__asm volatile
-	{
-		mcr p15, 0, value, c7, c6, 0
-	}
+    __asm volatile
+    {
+        mcr p15, 0, value, c7, c6, 0
+    }
 }
 #elif defined(__GNUC__)
 void mmu_setttbase(register rt_uint32_t i)
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	/* Invalidates all TLBs.Domain access is selected as
-	 * client by configuring domain access register,
-	 * in that case access controlled by permission value
-	 * set by page table entry
-	 */
-	value = 0;
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
+    /* Invalidates all TLBs.Domain access is selected as
+     * client by configuring domain access register,
+     * in that case access controlled by permission value
+     * set by page table entry
+     */
+    value = 0;
+    asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
 
-	value = 0x55555555;
-	asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
-	asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
+    value = 0x55555555;
+    asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
+    asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
 }
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-	asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+    asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
 }
 
 void mmu_enable()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= 0x1;
-	/* Enables the extended page tables to be configured for
-	   the hardware page translation mechanism, Subpage AP bits disabled */
-	i |= (1 << 23); /* support for ARMv6 MMU features */
-	i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
+    i |= 0x1;
+    /* Enables the extended page tables to be configured for
+       the hardware page translation mechanism, Subpage AP bits disabled */
+    i |= (1 << 23); /* support for ARMv6 MMU features */
+    i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~0x1;
+    i &= ~0x1;
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_icache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 12);
+    i |= (1 << 12);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_dcache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 2);
+    i |= (1 << 2);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_icache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 12);
+    i &= ~(1 << 12);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_dcache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 2);
+    i &= ~(1 << 2);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 1);
+    i |= (1 << 1);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 1);
+    i &= ~(1 << 1);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+    asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
 }
 
 void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while(ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while(ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_tlb()
 {
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
 }
 
 void mmu_invalidate_icache()
 {
-	asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
 
 void mmu_invalidate_dcache_all()
 {
-	asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
 }
 #endif
 
@@ -426,123 +426,123 @@ static volatile unsigned int _pgd_table[4*1024] ALIGN(16*1024);
  * level2 page table
  * RT_MMU_PTE_SIZE must be 1024*n
  */
-#define RT_MMU_PTE_SIZE		4096
+#define RT_MMU_PTE_SIZE     4096
 static volatile unsigned int _pte_table[RT_MMU_PTE_SIZE] ALIGN(1*1024);
 
 void mmu_create_pgd(struct mem_desc *mdesc)
 {
-	volatile rt_uint32_t *pTT;
-	volatile int i, nSec;
-	pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20);
-	nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20);
-	for(i = 0; i <= nSec; i++)
-	{
-		*pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20);
-		pTT++;
-	}
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20);
+    nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20);
+    for(i = 0; i <= nSec; i++)
+    {
+        *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20);
+        pTT++;
+    }
 }
 
 void mmu_create_pte(struct mem_desc *mdesc)
 {
-	volatile rt_uint32_t *pTT;
-	volatile rt_uint32_t *p_pteentry;
-	int i;
-	rt_uint32_t vaddr;
-	rt_uint32_t total_page = 0;
-	rt_uint32_t pte_offset = 0;
-	rt_uint32_t sect_attr = 0;
-
-	total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1;
-	pte_offset = mdesc->sect_attr & 0xfffffc00;
-	sect_attr = mdesc->sect_attr & 0x3ff;
-	vaddr = mdesc->vaddr_start;
-
-	for(i = 0; i < total_page; i++)
-	{
-		pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20);
-		if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */
-		{
-			*pTT = pte_offset | sect_attr;
-			p_pteentry = (rt_uint32_t *)pte_offset +
-				((vaddr & 0x000ff000) >> 12);
-			pte_offset += 1024;
-		}
-		else /* using old Level 1 page table item */
-		{
-			p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) +
-				((vaddr & 0x000ff000) >> 12);
-		}
-
-
-		*p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12);
-		vaddr += 0x1000;
-	}
+    volatile rt_uint32_t *pTT;
+    volatile rt_uint32_t *p_pteentry;
+    int i;
+    rt_uint32_t vaddr;
+    rt_uint32_t total_page = 0;
+    rt_uint32_t pte_offset = 0;
+    rt_uint32_t sect_attr = 0;
+
+    total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1;
+    pte_offset = mdesc->sect_attr & 0xfffffc00;
+    sect_attr = mdesc->sect_attr & 0x3ff;
+    vaddr = mdesc->vaddr_start;
+
+    for(i = 0; i < total_page; i++)
+    {
+        pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20);
+        if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */
+        {
+            *pTT = pte_offset | sect_attr;
+            p_pteentry = (rt_uint32_t *)pte_offset +
+                ((vaddr & 0x000ff000) >> 12);
+            pte_offset += 1024;
+        }
+        else /* using old Level 1 page table item */
+        {
+            p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) +
+                ((vaddr & 0x000ff000) >> 12);
+        }
+
+
+        *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12);
+        vaddr += 0x1000;
+    }
 }
 
 static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size)
 {
-	rt_uint32_t pte_offset = 0;
-	rt_uint32_t nsec = 0;
-	/* set page table */
-	for (; size > 0; size--)
-	{
-		if (mdesc->mapped_mode == PAGE_MAPPED)
-		{
-			nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20;
-			mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset;
-			pte_offset += nsec << 10;
-		}
-		if (pte_offset >= RT_MMU_PTE_SIZE)
-		{
-			rt_kprintf("PTE table size too little\n");
-			RT_ASSERT(0);
-		}
+    rt_uint32_t pte_offset = 0;
+    rt_uint32_t nsec = 0;
+    /* set page table */
+    for (; size > 0; size--)
+    {
+        if (mdesc->mapped_mode == PAGE_MAPPED)
+        {
+            nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20;
+            mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset;
+            pte_offset += nsec << 10;
+        }
+        if (pte_offset >= RT_MMU_PTE_SIZE)
+        {
+            rt_kprintf("PTE table size too little\n");
+            RT_ASSERT(0);
+        }
 
-		mdesc++;
-	}
+        mdesc++;
+    }
 }
 
 
 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
 {
-	/* disable I/D cache */
-	mmu_disable_dcache();
-	mmu_disable_icache();
-	mmu_disable();
-	mmu_invalidate_tlb();
-
-	/* clear pgd and pte table */
-	rt_memset((void *)_pgd_table, 0, 16*1024);
-	rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE);
-	build_pte_mem_desc(mdesc, size);
-	/* set page table */
-	for (; size > 0; size--)
-	{
-		if (mdesc->mapped_mode == SECT_MAPPED)
-		{
-			mmu_create_pgd(mdesc);
-		}
-		else
-		{
-			mmu_create_pte(mdesc);
-		}
-
-		mdesc++;
-	}
-
-	/* set MMU table address */
-	mmu_setttbase((rt_uint32_t)_pgd_table);
-
-	/* enables MMU */
-	mmu_enable();
-
-	/* enable Instruction Cache */
-	mmu_enable_icache();
-
-	/* enable Data Cache */
-	mmu_enable_dcache();
-
-	mmu_invalidate_icache();
-	mmu_invalidate_dcache_all();
+    /* disable I/D cache */
+    mmu_disable_dcache();
+    mmu_disable_icache();
+    mmu_disable();
+    mmu_invalidate_tlb();
+
+    /* clear pgd and pte table */
+    rt_memset((void *)_pgd_table, 0, 16*1024);
+    rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE);
+    build_pte_mem_desc(mdesc, size);
+    /* set page table */
+    for (; size > 0; size--)
+    {
+        if (mdesc->mapped_mode == SECT_MAPPED)
+        {
+            mmu_create_pgd(mdesc);
+        }
+        else
+        {
+            mmu_create_pte(mdesc);
+        }
+
+        mdesc++;
+    }
+
+    /* set MMU table address */
+    mmu_setttbase((rt_uint32_t)_pgd_table);
+
+    /* enables MMU */
+    mmu_enable();
+
+    /* enable Instruction Cache */
+    mmu_enable_icache();
+
+    /* enable Data Cache */
+    mmu_enable_dcache();
+
+    mmu_invalidate_icache();
+    mmu_invalidate_dcache_all();
 }
 

libcpu/arm/armv6/mmu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,7 +12,7 @@
 
 #include <rtthread.h>
 
-#define CACHE_LINE_SIZE	32
+#define CACHE_LINE_SIZE 32
 
 /*
  * Hardware page table definitions.
@@ -30,7 +30,7 @@
 /*
  *   - section
  */
-#define PGD_SECT_BUFFERABLE	(1 << 2)
+#define PGD_SECT_BUFFERABLE (1 << 2)
 #define PGD_SECT_CACHEABLE  (1 << 3)
 #define PGD_SECT_XN         (1 << 4)    /* ARMv6 */
 #define PGD_SECT_AP0        (1 << 10)
@@ -155,35 +155,35 @@
 #define PAGE_RONX_FAULT  (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */
 
 
-#define DESC_SEC		(0x2|(1<<4))
-#define CB				(3<<2)  //cache_on, write_back
-#define CNB				(2<<2)  //cache_on, write_through
-#define NCB				(1<<2)  //cache_off,WR_BUF on
-#define NCNB			(0<<2)  //cache_off,WR_BUF off
-#define AP_RW			(3<<10) //supervisor=RW, user=RW
-#define AP_RO			(2<<10) //supervisor=RW, user=RO
+#define DESC_SEC        (0x2|(1<<4))
+#define CB              (3<<2)  //cache_on, write_back
+#define CNB             (2<<2)  //cache_on, write_through
+#define NCB             (1<<2)  //cache_off,WR_BUF on
+#define NCNB            (0<<2)  //cache_off,WR_BUF off
+#define AP_RW           (3<<10) //supervisor=RW, user=RW
+#define AP_RO           (2<<10) //supervisor=RW, user=RO
 
-#define DOMAIN_FAULT	(0x0)
-#define DOMAIN_CHK		(0x1)
-#define DOMAIN_NOTCHK	(0x3)
-#define DOMAIN0			(0x0<<5)
-#define DOMAIN1			(0x1<<5)
+#define DOMAIN_FAULT    (0x0)
+#define DOMAIN_CHK      (0x1)
+#define DOMAIN_NOTCHK   (0x3)
+#define DOMAIN0         (0x0<<5)
+#define DOMAIN1         (0x1<<5)
 
-#define DOMAIN0_ATTR	(DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR	(DOMAIN_FAULT<<2)
+#define DOMAIN0_ATTR    (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR    (DOMAIN_FAULT<<2)
 
-#define RW_CB		(AP_RW|DOMAIN0|CB|DESC_SEC)		/* Read/Write, cache, write back */
-#define RW_CNB		(AP_RW|DOMAIN0|CNB|DESC_SEC)	/* Read/Write, cache, write through */
-#define RW_NCNB		(AP_RW|DOMAIN0|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
-#define RW_FAULT	(AP_RW|DOMAIN1|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
+#define RW_CB       (AP_RW|DOMAIN0|CB|DESC_SEC)     /* Read/Write, cache, write back */
+#define RW_CNB      (AP_RW|DOMAIN0|CNB|DESC_SEC)    /* Read/Write, cache, write through */
+#define RW_NCNB     (AP_RW|DOMAIN0|NCNB|DESC_SEC)   /* Read/Write without cache and write buffer */
+#define RW_FAULT    (AP_RW|DOMAIN1|NCNB|DESC_SEC)   /* Read/Write without cache and write buffer */
 
 struct mem_desc {
-	rt_uint32_t vaddr_start;
-	rt_uint32_t vaddr_end;
-	rt_uint32_t paddr_start;
-	rt_uint32_t sect_attr;   /* when page mapped */
-	rt_uint32_t page_attr;   /* only sector mapped valid */
-	rt_uint32_t mapped_mode;
+    rt_uint32_t vaddr_start;
+    rt_uint32_t vaddr_end;
+    rt_uint32_t paddr_start;
+    rt_uint32_t sect_attr;   /* when page mapped */
+    rt_uint32_t page_attr;   /* only sector mapped valid */
+    rt_uint32_t mapped_mode;
 #define     SECT_MAPPED  0
 #define     PAGE_MAPPED  1
 };

libcpu/arm/armv6/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/armv6/vfp.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/armv6/vfp.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -87,7 +87,7 @@
  })
 
 #define vmsr(vfp, var) \
-    asm("vmsr  "#vfp",  %0"	\
+    asm("vmsr  "#vfp",  %0" \
        : : "r" (var) : "cc")
 
 

libcpu/arm/common/backtrace.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/common/div0.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,5 +8,5 @@
  */
 void __div0 (void)
 {
-	while (1) ;
+    while (1) ;
 }

libcpu/arm/common/showmem.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,27 +12,27 @@
 
 void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size)
 {
-	int i = 0, j =0;
+    int i = 0, j =0;
 
-	RT_ASSERT(addr);
+    RT_ASSERT(addr);
 
-	addr = addr & ~0xF;
-	size = 4*((size + 3)/4);
+    addr = addr & ~0xF;
+    size = 4*((size + 3)/4);
 
-	while(i < size)
-	{
-		rt_kprintf("0x%08x: ", addr );
+    while(i < size)
+    {
+        rt_kprintf("0x%08x: ", addr );
 
-		for(j=0; j<4; j++)
-		{
-			rt_kprintf("0x%08x  ", *(rt_uint32_t *)addr);
+        for(j=0; j<4; j++)
+        {
+            rt_kprintf("0x%08x  ", *(rt_uint32_t *)addr);
 
-			addr += 4;
-			i++;
-		}
+            addr += 4;
+            i++;
+        }
 
-		rt_kprintf("\n");
-	}
+        rt_kprintf("\n");
+    }
 
-	return;
+    return;
 }

libcpu/arm/cortex-a/armv7.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,43 +12,43 @@
 /* the exception stack without VFP registers */
 struct rt_hw_exp_stack
 {
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long sp;
-	unsigned long lr;
-	unsigned long pc;
-	unsigned long cpsr;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
 };
 
 struct rt_hw_stack
 {
-	unsigned long cpsr;
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long lr;
-	unsigned long pc;
+    unsigned long cpsr;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long lr;
+    unsigned long pc;
 };
 
 #define USERMODE    0x10

libcpu/arm/cortex-a/cache.c

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-29     quanzhao     the first version
+ */
+#include <rthw.h>
+#include <rtdef.h>
+
+rt_inline rt_uint32_t rt_cpu_icache_line_size(void)
+{
+    rt_uint32_t ctr;
+    asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr));
+    return 4 << (ctr & 0xF);
+}
+
+rt_inline rt_uint32_t rt_cpu_dcache_line_size(void)
+{
+    rt_uint32_t ctr;
+    asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr));
+    return 4 << ((ctr >> 16) & 0xF);
+}
+
+void rt_hw_cpu_icache_invalidate(void *addr, int size)
+{
+    rt_uint32_t line_size = rt_cpu_icache_line_size();
+    rt_uint32_t start_addr = (rt_uint32_t)addr;
+    rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
+
+    asm volatile ("dmb":::"memory");
+    start_addr &= ~(line_size-1);
+    end_addr &= ~(line_size-1);
+    while (start_addr < end_addr)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr));  /* icimvau */
+        start_addr += line_size;
+    }
+    asm volatile ("dsb\n\tisb":::"memory");
+}
+
+void rt_hw_cpu_dcache_invalidate(void *addr, int size)
+{
+    rt_uint32_t line_size = rt_cpu_dcache_line_size();
+    rt_uint32_t start_addr = (rt_uint32_t)addr;
+    rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
+
+    asm volatile ("dmb":::"memory");
+    start_addr &= ~(line_size-1);
+    end_addr &= ~(line_size-1);
+    while (start_addr < end_addr)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr));  /* dcimvac */
+        start_addr += line_size;
+    }
+    asm volatile ("dsb":::"memory");
+}
+
+void rt_hw_cpu_dcache_clean(void *addr, int size)
+{
+    rt_uint32_t line_size = rt_cpu_dcache_line_size();
+    rt_uint32_t start_addr = (rt_uint32_t)addr;
+    rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
+
+    asm volatile ("dmb":::"memory");
+    start_addr &= ~(line_size-1);
+    end_addr &= ~(line_size-1);
+    while (start_addr < end_addr)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */
+        start_addr += line_size;
+    }
+    asm volatile ("dsb":::"memory");
+}
+
+void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
+{
+    if (ops == RT_HW_CACHE_INVALIDATE)
+        rt_hw_cpu_icache_invalidate(addr, size);
+}
+
+void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
+{
+    if (ops == RT_HW_CACHE_FLUSH)
+        rt_hw_cpu_dcache_clean(addr, size);
+    else if (ops == RT_HW_CACHE_INVALIDATE)
+        rt_hw_cpu_dcache_invalidate(addr, size);
+}
+
+rt_base_t rt_hw_cpu_icache_status(void)
+{
+    return 0;
+}
+
+rt_base_t rt_hw_cpu_dcache_status(void)
+{
+    return 0;
+}

libcpu/arm/cortex-a/context_gcc.S

@@ -76,6 +76,18 @@ rt_hw_context_switch:
     stmfd sp, {r13, r14}^   @ push usr_sp usr_lr
     sub sp, #8
 #endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb sp!, {d0-d15}
+    vstmdb sp!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd sp!, {r5}
+1:
+    stmfd sp!, {r6}
+#endif
 
     str sp, [r0]            @ store sp in preempted tasks TCB
     ldr sp, [r1]            @ get new task stack pointer
@@ -147,6 +159,18 @@ rt_hw_context_switch_exit:
     mov     sp, r0
 #endif
 #endif
+#ifdef RT_USING_FPU
+/* fpu context */
+    ldmfd sp!, {r6}
+    vmsr fpexc, r6
+    tst  r6, #(1<<30)
+    beq 1f
+    ldmfd sp!, {r5}
+    vmsr fpscr, r5
+    vldmia sp!, {d16-d31}
+    vldmia sp!, {d0-d15}
+1:
+#endif
 
 #ifdef RT_USING_LWP
     ldmfd   sp, {r13, r14}^ /* usr_sp, usr_lr */

libcpu/arm/cortex-a/cp15.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,6 +14,7 @@
 #include <board.h>
 
 #ifdef RT_USING_SMP
+
 int rt_hw_cpu_id(void)
 {
     int cpu_id;
@@ -25,6 +26,11 @@ int rt_hw_cpu_id(void)
     return cpu_id;
 };
 
+void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
+{
+    lock->slock = 0;
+}
+
 void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
 {
     unsigned long tmp;

libcpu/arm/cortex-a/gic.c

@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ * 2014-04-03     Grissiom     many enhancements
+ * 2018-11-22     Jesven       add rt_hw_ipi_send()
+ *                             add rt_hw_ipi_handler_install()
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "gic.h"
+#include "cp15.h"
+
+struct arm_gic
+{
+    rt_uint32_t offset;         /* the first interrupt index in the vector table */
+
+    rt_uint32_t dist_hw_base;   /* the base address of the gic distributor */
+    rt_uint32_t cpu_hw_base;    /* the base addrees of the gic cpu interface */
+};
+
+/* 'ARM_GIC_MAX_NR' is the number of cores */
+static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
+
+#define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00)
+#define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04)
+#define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08)
+#define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0c)
+#define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10)
+#define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14)
+#define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18)
+
+#define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000)
+#define GIC_DIST_TYPE(hw_base)              __REG32((hw_base) + 0x004)
+#define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380 + ((n)/32) * 4)
+#define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  ((n)/4) * 4)
+#define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  ((n)/4) * 4)
+#define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
+#define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00)
+#define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
+#define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8)
+
+static unsigned int _gic_max_irq;
+
+int arm_gic_get_active_irq(rt_uint32_t index)
+{
+    int irq;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
+    irq += _gic_table[index].offset;
+    return irq;
+}
+
+void arm_gic_ack(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
+}
+
+void arm_gic_mask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_clear_pending(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_clear_active(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+/* Set up the cpu mask for the specific interrupt */
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
+{
+    rt_uint32_t old_tgt;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
+
+    old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
+    old_tgt |=   cpumask << ((irq % 4)*8);
+
+    GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
+}
+
+void arm_gic_umask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_dump_type(rt_uint32_t index)
+{
+    unsigned int gic_type;
+
+    gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
+    rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
+               (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
+               _gic_table[index].dist_hw_base,
+               _gic_max_irq,
+               gic_type & (1 << 10) ? "has" : "no",
+               gic_type);
+}
+
+void arm_gic_dump(rt_uint32_t index)
+{
+    unsigned int i, k;
+
+    k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
+    rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
+    rt_kprintf("--- hw mask ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
+    }
+    rt_kprintf("\n--- hw pending ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
+                                        i * 32));
+    }
+    rt_kprintf("\n--- hw active ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
+    }
+    rt_kprintf("\n");
+}
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
+#endif
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
+{
+    unsigned int gic_type, i;
+    rt_uint32_t cpumask = 1 << 0;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].dist_hw_base = dist_base;
+    _gic_table[index].offset = irq_start;
+
+    /* Find out how many interrupts are supported. */
+    gic_type = GIC_DIST_TYPE(dist_base);
+    _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
+
+    /*
+     * The GIC only supports up to 1020 interrupt sources.
+     * Limit this to either the architected maximum, or the
+     * platform maximum.
+     */
+    if (_gic_max_irq > 1020)
+        _gic_max_irq = 1020;
+    if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
+        _gic_max_irq = ARM_GIC_NR_IRQS;
+
+    cpumask |= cpumask << 8;
+    cpumask |= cpumask << 16;
+    cpumask |= cpumask << 24;
+
+    GIC_DIST_CTRL(dist_base) = 0x0;
+
+    /* Set all global interrupts to be level triggered, active low. */
+    for (i = 32; i < _gic_max_irq; i += 16)
+        GIC_DIST_CONFIG(dist_base, i) = 0x0;
+
+    /* Set all global interrupts to this CPU only. */
+    for (i = 32; i < _gic_max_irq; i += 4)
+        GIC_DIST_TARGET(dist_base, i) = cpumask;
+
+    /* Set priority on all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 4)
+        GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
+
+    /* Disable all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
+
+#if 0
+    /* All interrupts defaults to IGROUP1(IRQ). */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
+#endif
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_IGROUP(dist_base, i) = 0;
+
+    /* Enable group0 and group1 interrupt forwarding. */
+    GIC_DIST_CTRL(dist_base) = 0x01;
+
+    return 0;
+}
+
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].cpu_hw_base = cpu_base;
+
+    GIC_CPU_PRIMASK(cpu_base) = 0xf0;
+    GIC_CPU_BINPOINT(cpu_base) = 0x7;
+    /* Enable CPU interrupt */
+    GIC_CPU_CTRL(cpu_base) = 0x01;
+
+    return 0;
+}
+
+void arm_gic_set_group(rt_uint32_t index, int vector, int group)
+{
+    /* As for GICv2, there are only group0 and group1. */
+    RT_ASSERT(group <= 1);
+    RT_ASSERT(vector < _gic_max_irq);
+
+    if (group == 0)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) &= ~(1 << (vector % 32));
+    }
+    else if (group == 1)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) |=  (1 << (vector % 32));
+    }
+}
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
+ {
+     /* note: ipi_vector maybe different with irq_vector */
+     GIC_DIST_SOFTINT(_gic_table[0].dist_hw_base) = (cpu_mask << 16) | ipi_vector;
+}
+#endif
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
+{
+    /* note: ipi_vector maybe different with irq_vector */
+    rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
+}
+#endif

libcpu/arm/cortex-a/gic.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#ifndef __GIC_H__
+#define __GIC_H__
+
+#include <rthw.h>
+#include <board.h>
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
+
+void arm_gic_mask(rt_uint32_t index, int irq);
+void arm_gic_umask(rt_uint32_t index, int irq);
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
+void arm_gic_set_group(rt_uint32_t index, int vector, int group);
+
+int arm_gic_get_active_irq(rt_uint32_t index);
+void arm_gic_ack(rt_uint32_t index, int irq);
+
+void arm_gic_clear_active(rt_uint32_t index, int irq);
+void arm_gic_clear_pending(rt_uint32_t index, int irq);
+
+void arm_gic_dump_type(rt_uint32_t index);
+void arm_gic_dump(rt_uint32_t index);
+
+#endif
+

libcpu/arm/cortex-a/interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/interrupt.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-06     Bernard      first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+void rt_hw_vector_init(void);
+
+void rt_hw_interrupt_control(int vector, int priority, int route);
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+
+int rt_hw_interrupt_get_irq(void);
+void rt_hw_interrupt_ack(int vector);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif

libcpu/arm/cortex-a/mmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/mmu.h

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-25     quanzhao     the first version
+ */
+#ifndef __MMU_H_
+#define __MMU_H_
+
+#include <rtthread.h>
+
+#define DESC_SEC       (0x2)
+#define MEMWBWA        ((1<<12)|(3<<2))     /* write back, write allocate */
+#define MEMWB          (3<<2)  /* write back, no write allocate */
+#define MEMWT          (2<<2)  /* write through, no write allocate */
+#define SHAREDEVICE    (1<<2)  /* shared device */
+#define STRONGORDER    (0<<2)  /* strong ordered */
+#define XN             (1<<4)  /* eXecute Never */
+#define AP_RW          (3<<10) /* supervisor=RW, user=RW */
+#define AP_RO          (2<<10) /* supervisor=RW, user=RO */
+#define SHARED         (1<<16) /* shareable */
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0<<5)
+#define DOMAIN1        (0x1<<5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
+
+/* device mapping type */
+#define DEVICE_MEM     (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN)
+/* normal memory mapping type */
+#define NORMAL_MEM     (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC)
+
+struct mem_desc
+{
+    rt_uint32_t vaddr_start;
+    rt_uint32_t vaddr_end;
+    rt_uint32_t paddr_start;
+    rt_uint32_t attr;
+};
+
+
+#endif

libcpu/arm/cortex-a/pmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/pmu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -60,6 +60,9 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
     *(--stk) = 0;       /* user lr */
     *(--stk) = 0;       /* user sp*/
 #endif
+#ifdef RT_USING_FPU
+    *(--stk) = 0;       /* not use fpu*/
+#endif
 
     /* return task's current stack address */
     return (rt_uint8_t *)stk;

libcpu/arm/cortex-a/start_gcc.S

@@ -22,7 +22,11 @@
 .equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
 .equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
 
+#ifdef RT_USING_FPU
+.equ UND_Stack_Size,     0x00000400
+#else
 .equ UND_Stack_Size,     0x00000000
+#endif
 .equ SVC_Stack_Size,     0x00000400
 .equ ABT_Stack_Size,     0x00000000
 .equ RT_FIQ_STACK_PGSZ,  0x00000000
@@ -37,6 +41,7 @@
 .globl stack_start
 .globl stack_top
 
+.align 3
 stack_start:
 .rept ISR_Stack_Size
 .byte 0
@@ -50,6 +55,11 @@ _reset:
     /* set the cpu to SVC32 mode and disable interrupt */
     cps #Mode_SVC
 
+#ifdef RT_USING_FPU
+    mov r4, #0xfffffff
+    mcr p15, 0, r4, c1, c0, 2
+#endif
+
     /* disable the data alignment check */
     mrc p15, 0, r1, c1, c0, 0
     bic r1, #(1<<1)
@@ -176,6 +186,19 @@ vector_irq:
     stmfd   r0, {r13, r14}^ /* usr_sp, usr_lr */
     sub   r0, #8
 #endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb r0!, {d0-d15}
+    vstmdb r0!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd r0!, {r5}
+1:
+    stmfd r0!, {r6}
+#endif
+
     /* now irq stack is clean */
     /* r0 is task svc_sp */
     /* backup r0 -> r8 */
@@ -234,6 +257,18 @@ rt_hw_context_switch_interrupt_do:
     stmfd sp, {r13, r14}^  @push usr_sp, usr_lr
     sub sp, #8
 #endif
+#ifdef RT_USING_FPU
+    /* fpu context */
+    vmrs r6, fpexc
+    tst  r6, #(1<<30)
+    beq 1f
+    vstmdb sp!, {d0-d15}
+    vstmdb sp!, {d16-d31}
+    vmrs r5, fpscr
+    stmfd sp!, {r5}
+1:
+    stmfd sp!, {r6}
+#endif
 
     ldr     r4,  =rt_interrupt_from_thread
     ldr     r5,  [r4]
@@ -243,6 +278,19 @@ rt_hw_context_switch_interrupt_do:
     ldr     r6,  [r6]
     ldr     sp,  [r6]       @ get new task's stack pointer
 
+#ifdef RT_USING_FPU
+/* fpu context */
+    ldmfd sp!, {r6}
+    vmsr fpexc, r6
+    tst  r6, #(1<<30)
+    beq 1f
+    ldmfd sp!, {r5}
+    vmsr fpscr, r5
+    vldmia sp!, {d16-d31}
+    vldmia sp!, {d0-d15}
+1:
+#endif
+
 #ifdef RT_USING_LWP
     ldmfd sp, {r13, r14}^  @pop usr_sp, usr_lr
     add sp, #8
@@ -278,7 +326,14 @@ vector_swi:
     .globl  vector_undef
 vector_undef:
     push_svc_reg
+    cps #Mode_UND
     bl      rt_hw_trap_undef
+#ifdef RT_USING_FPU
+    ldr     lr, [sp, #15*4]
+    ldmia   sp, {r0 - r12}
+    add     sp, sp, #17 * 4
+    movs    pc, lr
+#endif
     b       .
 
     .align  5
@@ -315,6 +370,12 @@ set_secondary_cpu_boot_address:
 
 .global secondary_cpu_start
 secondary_cpu_start:
+
+#ifdef RT_USING_FPU
+    mov r4, #0xfffffff
+    mcr p15, 0, r4, c1, c0, 2
+#endif
+
     mrc p15, 0, r1, c1, c0, 1
     mov r0, #(1<<6)
     orr r1, r0
@@ -324,6 +385,11 @@ secondary_cpu_start:
     bic r0, #(1<<13)
     mcr p15, 0, r0, c1, c0, 0
 
+#ifdef RT_USING_FPU
+    cps #Mode_UND
+    ldr sp, =und_stack_2_limit
+#endif
+
     cps #Mode_IRQ
     ldr sp, =irq_stack_2_limit
 
@@ -349,3 +415,8 @@ irq_stack_2:
     .space (1 << 10)
 irq_stack_2_limit:
 
+#ifdef RT_USING_FPU
+und_stack_2:
+    .space (1 << 10)
+und_stack_2_limit:
+#endif

libcpu/arm/cortex-a/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -45,6 +45,39 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs)
  */
 void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
 {
+#ifdef RT_USING_FPU
+    {
+        uint32_t ins;
+        uint32_t addr;
+
+        if (regs->cpsr & (1 << 5))
+        {
+            /* thumb mode */
+            addr = regs->pc - 2;
+            ins = (uint32_t)*(uint16_t*)addr;
+            if ((ins & (3 << 11)) != 0)
+            {
+                /* 32 bit ins */
+                ins <<= 16;
+                ins += *(uint16_t*)(addr + 2);
+            }
+        }
+        else
+        {
+            addr = regs->pc - 4;
+            ins = *(uint32_t*)addr;
+        }
+        if ((ins & 0xe00) == 0xa00)
+        {
+            /* float ins */
+            uint32_t val = (1U << 30);
+
+            asm volatile ("vmsr fpexc, %0"::"r"(val):"memory");
+            regs->pc = addr;
+            return;
+        }
+    }
+#endif
     rt_kprintf("undefined instruction:\n");
     rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH

libcpu/arm/cortex-m0/context_gcc.S

@@ -22,7 +22,7 @@
 	.equ 	SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
 	.equ 	NVIC_INT_CTRL, 0xE000ED04       /* interrupt control state register */
 	.equ 	NVIC_SHPR3, 0xE000ED20          /* system priority register (3) */
-	.equ 	NVIC_PENDSV_PRI, 0x00FF0000     /* PendSV priority value (lowest) */
+	.equ 	NVIC_PENDSV_PRI, 0xFFFF0000     /* PendSV and SysTick priority value (lowest) */
 	.equ 	NVIC_PENDSVSET, 0x10000000      /* value to trigger PendSV exception */
 
 /*
@@ -159,7 +159,7 @@ rt_hw_context_switch_to:
     MOVS    R0, #1
     STR     R0, [R1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR     R0, =NVIC_SHPR3
     LDR     R1, =NVIC_PENDSV_PRI
     LDR     R2, [R0,#0x00]       /* read */

libcpu/arm/cortex-m0/context_iar.S

@@ -19,7 +19,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -163,7 +163,7 @@ rt_hw_context_switch_to:
     MOVS    r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SHPR3
     LDR     r1, =NVIC_PENDSV_PRI
     LDR     r2, [r0,#0x00]       ; read

libcpu/arm/cortex-m0/context_rvds.S

@@ -19,7 +19,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -168,7 +168,7 @@ rt_hw_context_switch_to    PROC
     MOVS    r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SHPR3
     LDR     r1, =NVIC_PENDSV_PRI
     LDR     r2, [r0,#0x00]       ; read

libcpu/arm/cortex-m0/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -119,7 +119,7 @@ void rt_hw_hard_fault_exception(struct exception_stack_frame *contex)
 #define SCB_HFSR        (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
 #define SCB_MMAR        (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
 #define SCB_BFAR        (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
-#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED00)  /* Reset control Address Register */
+#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED0C)  /* Reset control Address Register */
 #define SCB_RESET_VALUE 0x05FA0004                               /* Reset value, write to SCB_AIRCR can reset cpu */
 
 #define SCB_CFSR_MFSR   (*(volatile const unsigned char*)0xE000ED28)  /* Memory-management Fault Status Register */

libcpu/arm/cortex-m23/context_gcc.S

@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date         Author       Notes
+ * 2010-01-25   Bernard      first version
+ * 2012-06-01   aozima       set pendsv priority to 0xFF.
+ * 2012-08-17   aozima       fixed bug: store r8 - r11.
+ * 2013-02-20   aozima       port to gcc.
+ * 2013-06-18   aozima       add restore MSP feature.
+ * 2013-11-04   bright       fixed hardfault bug for gcc.
+ * 2019-03-31   xuzhuoyi     port to Cortex-M23.
+ */
+ 
+    .cpu    cortex-m23
+    .fpu    softvfp
+    .syntax unified
+    .thumb
+    .text
+
+	.equ 	SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
+	.equ 	NVIC_INT_CTRL, 0xE000ED04       /* interrupt control state register */
+	.equ 	NVIC_SHPR3, 0xE000ED20          /* system priority register (3) */
+	.equ 	NVIC_PENDSV_PRI, 0xFFFF0000     /* PendSV and SysTick priority value (lowest) */
+	.equ 	NVIC_PENDSVSET, 0x10000000      /* value to trigger PendSV exception */
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+    .global rt_hw_interrupt_disable
+    .type rt_hw_interrupt_disable, %function
+rt_hw_interrupt_disable:
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+    .global rt_hw_interrupt_enable
+    .type rt_hw_interrupt_enable, %function
+rt_hw_interrupt_enable:
+    MSR     PRIMASK, R0
+    BX      LR
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * R0 --> from
+ * R1 --> to
+ */
+    .global rt_hw_context_switch_interrupt
+    .type rt_hw_context_switch_interrupt, %function
+    .global rt_hw_context_switch
+    .type rt_hw_context_switch, %function
+rt_hw_context_switch_interrupt:
+rt_hw_context_switch:
+    /* set rt_thread_switch_interrupt_flag to 1 */
+    LDR     R2, =rt_thread_switch_interrupt_flag
+    LDR     R3, [R2]
+    CMP     R3, #1
+    BEQ     _reswitch
+    MOVS    R3, #1
+    STR     R3, [R2]
+
+    LDR     R2, =rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
+    STR     R0, [R2]
+
+_reswitch:
+    LDR     R2, =rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
+    STR     R1, [R2]
+
+    LDR     R0, =NVIC_INT_CTRL           /* trigger the PendSV exception (causes context switch) */
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+/* R0 --> switch from thread stack
+ * R1 --> switch to thread stack
+ * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
+ */
+    .global PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    /* disable interrupt to protect context switch */
+    MRS     R2, PRIMASK
+    CPSID   I
+
+    /* get rt_thread_switch_interrupt_flag */
+    LDR     R0, =rt_thread_switch_interrupt_flag
+    LDR     R1, [R0]
+    CMP     R1, #0x00
+    BEQ     pendsv_exit		/* pendsv aLReady handled */
+
+    /* clear rt_thread_switch_interrupt_flag to 0 */
+    MOVS    R1, #0
+    STR     R1, [R0]
+
+    LDR     R0, =rt_interrupt_from_thread
+    LDR     R1, [R0]
+    CMP     R1, #0x00
+    BEQ     switch_to_thread    /* skip register save at the first time */
+
+	MRS     R1, PSP                 /* get from thread stack pointer */
+
+    SUBS    R1, R1, #0x20           /* space for {R4 - R7} and {R8 - R11} */
+    LDR     R0, [R0]
+    STR     R1, [R0]                /* update from thread stack pointer */
+
+    STMIA   R1!, {R4 - R7}          /* push thread {R4 - R7} register to thread stack */
+
+    MOV     R4, R8                  /* mov thread {R8 - R11} to {R4 - R7} */
+    MOV     R5, R9
+    MOV     R6, R10
+    MOV     R7, R11
+    STMIA   R1!, {R4 - R7}          /* push thread {R8 - R11} high register to thread stack */
+switch_to_thread:
+    LDR     R1, =rt_interrupt_to_thread
+    LDR     R1, [R1]
+    LDR     R1, [R1]                /* load thread stack pointer */
+
+	LDMIA   R1!, {R4 - R7}          /* pop thread {R4 - R7} register from thread stack */
+    PUSH    {R4 - R7}               /* push {R4 - R7} to MSP for copy {R8 - R11} */
+
+    LDMIA   R1!, {R4 - R7}          /* pop thread {R8 - R11} high register from thread stack to {R4 - R7} */
+    MOV     R8,  R4                 /* mov {R4 - R7} to {R8 - R11} */
+    MOV     R9,  R5
+    MOV     R10, R6
+    MOV     R11, R7
+
+    POP     {R4 - R7}               /* pop {R4 - R7} from MSP */
+
+    MSR     PSP, R1                 /* update stack pointer */
+
+pendsv_exit:
+    /* restore interrupt */
+    MSR     PRIMASK, R2
+
+    MOVS    R0, #0x03
+    RSBS    R0, R0, #0x00
+    BX      R0
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * R0 --> to
+ */
+    .global rt_hw_context_switch_to
+    .type rt_hw_context_switch_to, %function
+rt_hw_context_switch_to:
+    LDR     R1, =rt_interrupt_to_thread
+    STR     R0, [R1]
+
+    /* set from thread to 0 */
+    LDR     R1, =rt_interrupt_from_thread
+    MOVS    R0, #0
+    STR     R0, [R1]
+
+    /* set interrupt flag to 1 */
+    LDR     R1, =rt_thread_switch_interrupt_flag
+    MOVS    R0, #1
+    STR     R0, [R1]
+
+    /* set the PendSV and SysTick exception priority */
+    LDR     R0, =NVIC_SHPR3
+    LDR     R1, =NVIC_PENDSV_PRI
+    LDR     R2, [R0,#0x00]       /* read */
+    ORRS    R1, R1, R2             /* modify */
+    STR     R1, [R0]             /* write-back */
+
+    LDR     R0, =NVIC_INT_CTRL               /* trigger the PendSV exception (causes context switch) */
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    NOP
+    /* restore MSP */
+    LDR     R0, =SCB_VTOR
+    LDR     R0, [R0]
+    LDR     R0, [R0]
+    NOP
+    MSR     MSP, R0
+
+    /* enable interrupts at processor level */
+    CPSIE   I
+
+    /* never reach here! */
+
+/* compatible with old version */
+    .global rt_hw_interrupt_thread_switch
+    .type rt_hw_interrupt_thread_switch, %function
+rt_hw_interrupt_thread_switch:
+    BX      LR
+    NOP
+
+    .global HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    /* get current context */
+    MRS     R0, PSP                 /* get fault thread stack pointer */
+    PUSH    {LR}
+    BL      rt_hw_hard_fault_exception
+    POP     {PC}
+
+
+/*
+ * rt_uint32_t rt_hw_interrupt_check(void);
+ * R0 --> state
+ */
+    .global rt_hw_interrupt_check
+    .type rt_hw_interrupt_check, %function
+rt_hw_interrupt_check:
+    MRS     R0, IPSR
+    BX      LR

libcpu/arm/cortex-m23/context_iar.S

@@ -0,0 +1,207 @@
+;/*
+; * Copyright (c) 2006-2019, RT-Thread Development Team
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2010-01-25     Bernard      first version
+; * 2012-06-01     aozima       set pendsv priority to 0xFF.
+; * 2012-08-17     aozima       fixed bug: store r8 - r11.
+; * 2013-06-18     aozima       add restore MSP feature.
+; * 2019-03-31     xuzhuoyi     port to Cortex-M23.
+; */
+
+;/**
+; * @addtogroup CORTEX-M23
+; */
+;/*@{*/
+
+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
+NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
+NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
+NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
+
+    SECTION    .text:CODE(2)
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+    EXPORT rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+    EXPORT  rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    MSR     PRIMASK, r0
+    BX      LR
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+    EXPORT rt_hw_context_switch_interrupt
+    EXPORT rt_hw_context_switch
+rt_hw_context_switch_interrupt:
+rt_hw_context_switch:
+    ; set rt_thread_switch_interrupt_flag to 1
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOVS    r3, #0x1
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    STR     r0, [r2]
+
+_reswitch
+    LDR     r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    STR     r1, [r2]
+
+    LDR     r0, =NVIC_INT_CTRL              ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+    BX      LR
+
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+    EXPORT PendSV_Handler
+PendSV_Handler:
+
+    ; disable interrupt to protect context switch
+    MRS     r2, PRIMASK
+    CPSID   I
+
+    ; get rt_thread_switch_interrupt_flag
+    LDR     r0, =rt_thread_switch_interrupt_flag
+    LDR     r1, [r0]
+    CMP     r1, #0x00
+    BEQ     pendsv_exit                ; pendsv already handled
+
+    ; clear rt_thread_switch_interrupt_flag to 0
+    MOVS    r1, #0x00
+    STR     r1, [r0]
+
+    LDR     r0, =rt_interrupt_from_thread
+    LDR     r1, [r0]
+    CMP     r1, #0x00
+    BEQ     switch_to_thread        ; skip register save at the first time
+
+    MRS     r1, psp                 ; get from thread stack pointer
+
+    SUBS    r1, r1, #0x20           ; space for {r4 - r7} and {r8 - r11}
+    LDR     r0, [r0]
+    STR     r1, [r0]                ; update from thread stack pointer
+
+    STMIA   r1!, {r4 - r7}          ; push thread {r4 - r7} register to thread stack
+
+    MOV     r4, r8                  ; mov thread {r8 - r11} to {r4 - r7}
+    MOV     r5, r9
+    MOV     r6, r10
+    MOV     r7, r11
+    STMIA   r1!, {r4 - r7}          ; push thread {r8 - r11} high register to thread stack
+
+switch_to_thread
+    LDR     r1, =rt_interrupt_to_thread
+    LDR     r1, [r1]
+    LDR     r1, [r1]                ; load thread stack pointer
+
+    LDMIA   r1!, {r4 - r7}          ; pop thread {r4 - r7} register from thread stack
+    PUSH    {r4 - r7}               ; push {r4 - r7} to MSP for copy {r8 - r11}
+
+    LDMIA   r1!, {r4 - r7}          ; pop thread {r8 - r11} high register from thread stack to {r4 - r7}
+    MOV     r8,  r4                 ; mov {r4 - r7} to {r8 - r11}
+    MOV     r9,  r5
+    MOV     r10, r6
+    MOV     r11, r7
+
+    POP     {r4 - r7}               ; pop {r4 - r7} from MSP
+
+    MSR     psp, r1                 ; update stack pointer
+
+pendsv_exit
+    ; restore interrupt
+    MSR     PRIMASK, r2
+
+    MOVS    r0, #0x03
+    RSBS    r0, r0, #0x00
+    BX      r0
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; * this fucntion is used to perform the first thread switch
+; */
+    EXPORT rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    ; set to thread
+    LDR     r1, =rt_interrupt_to_thread
+    STR     r0, [r1]
+
+    ; set from thread to 0
+    LDR     r1, =rt_interrupt_from_thread
+    MOVS    r0, #0x0
+    STR     r0, [r1]
+
+    ; set interrupt flag to 1
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOVS    r0, #1
+    STR     r0, [r1]
+
+    ; set the PendSV and SysTick exception priority
+    LDR     r0, =NVIC_SHPR3
+    LDR     r1, =NVIC_PENDSV_PRI
+    LDR     r2, [r0,#0x00]       ; read
+    ORRS    r1,r1,r2             ; modify
+    STR     r1, [r0]             ; write-back
+
+    ; trigger the PendSV exception (causes context switch)
+    LDR     r0, =NVIC_INT_CTRL
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+    NOP
+
+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
+    ; enable interrupts at processor level
+    CPSIE   I
+
+    ; never reach here!
+
+; compatible with old version
+    EXPORT rt_hw_interrupt_thread_switch
+rt_hw_interrupt_thread_switch:
+    BX      lr
+
+    IMPORT rt_hw_hard_fault_exception
+    EXPORT HardFault_Handler
+HardFault_Handler:
+
+    ; get current context
+    MRS     r0, psp                 ; get fault thread stack pointer
+    PUSH    {lr}
+    BL      rt_hw_hard_fault_exception
+    POP     {pc}
+
+    END

libcpu/arm/cortex-m23/context_rvds.S

@@ -0,0 +1,216 @@
+;/*
+; * Copyright (c) 2006-2019, RT-Thread Development Team
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2010-01-25     Bernard      first version
+; * 2012-06-01     aozima       set pendsv priority to 0xFF.
+; * 2012-08-17     aozima       fixed bug: store r8 - r11.
+; * 2013-06-18     aozima       add restore MSP feature.
+; * 2019-03-31     xuzhuoyi     port to Cortex-M23.
+; */
+
+;/**
+; * @addtogroup CORTEX-M23
+; */
+;/*@{*/
+
+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
+NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
+NVIC_SHPR3      EQU     0xE000ED20               ; system priority register (2)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
+NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+rt_hw_interrupt_disable    PROC
+    EXPORT  rt_hw_interrupt_disable
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+    ENDP
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+rt_hw_interrupt_enable    PROC
+    EXPORT  rt_hw_interrupt_enable
+    MSR		PRIMASK, r0
+    BX		LR
+    ENDP
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+rt_hw_context_switch_interrupt
+    EXPORT rt_hw_context_switch_interrupt
+rt_hw_context_switch    PROC
+    EXPORT rt_hw_context_switch
+
+    ; set rt_thread_switch_interrupt_flag to 1
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOVS    r3, #0x01
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    STR     r0, [r2]
+
+_reswitch
+    LDR     r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    STR     r1, [r2]
+
+    LDR     r0, =NVIC_INT_CTRL              ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+    BX      LR
+    ENDP
+
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+PendSV_Handler    PROC
+    EXPORT PendSV_Handler
+
+    ; disable interrupt to protect context switch
+    MRS     r2, PRIMASK
+    CPSID   I
+
+    ; get rt_thread_switch_interrupt_flag
+    LDR     r0, =rt_thread_switch_interrupt_flag
+    LDR     r1, [r0]
+    CMP     r1, #0x00
+    BEQ     pendsv_exit                ; pendsv already handled
+
+    ; clear rt_thread_switch_interrupt_flag to 0
+    MOVS    r1, #0x00
+    STR     r1, [r0]
+
+    LDR     r0, =rt_interrupt_from_thread
+    LDR     r1, [r0]
+    CMP     r1, #0x00
+    BEQ     switch_to_thread        ; skip register save at the first time
+
+    MRS     r1, psp                 ; get from thread stack pointer
+
+    SUBS    r1, r1, #0x20           ; space for {r4 - r7} and {r8 - r11}
+    LDR     r0, [r0]
+    STR     r1, [r0]                ; update from thread stack pointer
+
+    STMIA   r1!, {r4 - r7}          ; push thread {r4 - r7} register to thread stack
+
+    MOV     r4, r8                  ; mov thread {r8 - r11} to {r4 - r7}
+    MOV     r5, r9
+    MOV     r6, r10
+    MOV     r7, r11
+    STMIA   r1!, {r4 - r7}          ; push thread {r8 - r11} high register to thread stack
+
+switch_to_thread
+    LDR     r1, =rt_interrupt_to_thread
+    LDR     r1, [r1]
+    LDR     r1, [r1]                ; load thread stack pointer
+
+    LDMIA   r1!, {r4 - r7}          ; pop thread {r4 - r7} register from thread stack
+    PUSH    {r4 - r7}               ; push {r4 - r7} to MSP for copy {r8 - r11}
+
+    LDMIA   r1!, {r4 - r7}          ; pop thread {r8 - r11} high register from thread stack to {r4 - r7}
+    MOV     r8,  r4                 ; mov {r4 - r7} to {r8 - r11}
+    MOV     r9,  r5
+    MOV     r10, r6
+    MOV     r11, r7
+
+    POP     {r4 - r7}               ; pop {r4 - r7} from MSP
+
+    MSR     psp, r1                 ; update stack pointer
+
+pendsv_exit
+    ; restore interrupt
+    MSR     PRIMASK, r2
+
+    MOVS    r0, #0x03
+    RSBS    r0, r0, #0x00
+    BX      r0
+    ENDP
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; * this fucntion is used to perform the first thread switch
+; */
+rt_hw_context_switch_to    PROC
+    EXPORT rt_hw_context_switch_to
+    ; set to thread
+    LDR     r1, =rt_interrupt_to_thread
+    STR     r0, [r1]
+
+    ; set from thread to 0
+    LDR     r1, =rt_interrupt_from_thread
+    MOVS    r0, #0x0
+    STR     r0, [r1]
+
+    ; set interrupt flag to 1
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOVS    r0, #1
+    STR     r0, [r1]
+
+    ; set the PendSV and SysTick exception priority
+    LDR     r0, =NVIC_SHPR3
+    LDR     r1, =NVIC_PENDSV_PRI
+    LDR     r2, [r0,#0x00]       ; read
+    ORRS    r1,r1,r2             ; modify
+    STR     r1, [r0]             ; write-back
+
+    ; trigger the PendSV exception (causes context switch)
+    LDR     r0, =NVIC_INT_CTRL
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+
+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    MSR     msp, r0
+
+    ; enable interrupts at processor level
+    CPSIE   I
+
+    ; never reach here!
+    ENDP
+
+; compatible with old version
+rt_hw_interrupt_thread_switch PROC
+    EXPORT rt_hw_interrupt_thread_switch
+    BX      lr
+    ENDP
+
+    IMPORT rt_hw_hard_fault_exception
+
+HardFault_Handler    PROC
+    EXPORT HardFault_Handler
+
+    ; get current context
+    MRS     r0, psp                 ; get fault thread stack pointer
+    PUSH    {lr}
+    BL      rt_hw_hard_fault_exception
+    POP     {pc}
+    ENDP
+
+    ALIGN   4
+
+    END

libcpu/arm/cortex-m23/cpuport.c

@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-01-25     Bernard      first version
+ * 2012-05-31     aozima       Merge all of the C source code into cpuport.c
+ * 2012-08-17     aozima       fixed bug: store r8 - r11.
+ * 2012-12-23     aozima       stack addr align to 8byte.
+ * 2019-03-31     xuzhuoyi     port to Cortex-M23.
+ */
+
+#include <rtthread.h>
+
+struct exception_stack_frame
+{
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r12;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t psr;
+};
+
+struct stack_frame
+{
+    /* r4 ~ r7 low register */
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+
+    /* r8 ~ r11 high register */
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t r11;
+
+    struct exception_stack_frame exception_stack_frame;
+};
+
+/* flag in interrupt handling */
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void       *tentry,
+                             void       *parameter,
+                             rt_uint8_t *stack_addr,
+                             void       *texit)
+{
+    struct stack_frame *stack_frame;
+    rt_uint8_t         *stk;
+    unsigned long       i;
+
+    stk  = stack_addr + sizeof(rt_uint32_t);
+    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
+    stk -= sizeof(struct stack_frame);
+
+    stack_frame = (struct stack_frame *)stk;
+
+    /* init all register */
+    for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
+    {
+        ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
+    }
+
+    stack_frame->exception_stack_frame.r0  = (unsigned long)parameter; /* r0 : argument */
+    stack_frame->exception_stack_frame.r1  = 0;                        /* r1 */
+    stack_frame->exception_stack_frame.r2  = 0;                        /* r2 */
+    stack_frame->exception_stack_frame.r3  = 0;                        /* r3 */
+    stack_frame->exception_stack_frame.r12 = 0;                        /* r12 */
+    stack_frame->exception_stack_frame.lr  = (unsigned long)texit;     /* lr */
+    stack_frame->exception_stack_frame.pc  = (unsigned long)tentry;    /* entry point, pc */
+    stack_frame->exception_stack_frame.psr = 0x01000000L;              /* PSR */
+
+    /* return task's current stack address */
+    return stk;
+}
+
+extern long list_thread(void);
+extern rt_thread_t rt_current_thread;
+/**
+ * fault exception handling
+ */
+void rt_hw_hard_fault_exception(struct exception_stack_frame *contex)
+{
+    rt_kprintf("psr: 0x%08x\n", contex->psr);
+    rt_kprintf(" pc: 0x%08x\n", contex->pc);
+    rt_kprintf(" lr: 0x%08x\n", contex->lr);
+    rt_kprintf("r12: 0x%08x\n", contex->r12);
+    rt_kprintf("r03: 0x%08x\n", contex->r3);
+    rt_kprintf("r02: 0x%08x\n", contex->r2);
+    rt_kprintf("r01: 0x%08x\n", contex->r1);
+    rt_kprintf("r00: 0x%08x\n", contex->r0);
+
+    rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
+
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+
+    while (1);
+}
+
+#define SCB_CFSR        (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
+#define SCB_HFSR        (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
+#define SCB_MMAR        (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
+#define SCB_BFAR        (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
+#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED00)  /* Reset control Address Register */
+#define SCB_RESET_VALUE 0x05FA0004                               /* Reset value, write to SCB_AIRCR can reset cpu */
+
+#define SCB_CFSR_MFSR   (*(volatile const unsigned char*)0xE000ED28)  /* Memory-management Fault Status Register */
+#define SCB_CFSR_BFSR   (*(volatile const unsigned char*)0xE000ED29)  /* Bus Fault Status Register */
+#define SCB_CFSR_UFSR   (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
+
+/**
+ * reset CPU
+ */
+RT_WEAK void rt_hw_cpu_reset(void)
+{
+    SCB_AIRCR  = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk);
+}

libcpu/arm/cortex-m3/context_gcc.S

@@ -24,7 +24,7 @@
     .equ    PENDSVSET_BIT, 0x10000000       /* value to trigger PendSV exception */
     
     .equ    SHPR3, 0xE000ED20               /* system priority register (3) */
-    .equ    PENDSV_PRI_LOWEST, 0x00FF0000   /* PendSV priority value (lowest) */
+    .equ    PENDSV_PRI_LOWEST, 0xFFFF0000   /* PendSV and SysTick priority value (lowest) */
 
 /*
  * rt_base_t rt_hw_interrupt_disable();
@@ -140,7 +140,7 @@ rt_hw_context_switch_to:
     MOV     R0, #1
     STR     R0, [R1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR     R0, =SHPR3
     LDR     R1, =PENDSV_PRI_LOWEST
     LDR.W   R2, [R0,#0]             /* read */

libcpu/arm/cortex-m3/context_iar.S

@@ -19,7 +19,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -139,7 +139,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read

libcpu/arm/cortex-m3/context_rvds.S

@@ -18,7 +18,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -145,7 +145,7 @@ rt_hw_context_switch_to    PROC
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read

libcpu/arm/cortex-m3/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,6 +11,7 @@
  * 2012-12-23   aozima      stack addr align to 8byte.
  * 2012-12-29   Bernard     Add exception hook.
  * 2013-07-09   aozima      enhancement hard fault exception handler.
+ * 2019-07-03   yangjie     add __rt_ffs() for armclang.
  */
 
 #include <rtthread.h>
@@ -382,6 +383,24 @@ __asm int __rt_ffs(int value)
 exit
     BX      lr
 }
+#elif defined(__CLANG_ARM)
+int __rt_ffs(int value)
+{
+    __asm volatile(
+        "CMP     r0, #0x00            \n"
+        "BEQ     1f                   \n"
+
+        "RBIT    r0, r0               \n"
+        "CLZ     r0, r0               \n"
+        "ADDS    r0, r0, #0x01        \n"
+
+        "1:                           \n"
+
+        : "=r"(value)
+        : "r"(value)
+    );
+    return value;
+}
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {

libcpu/arm/cortex-m33/context_gcc.S

@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-10-11     Bernard      first version
+ * 2012-01-01     aozima       support context switch load/store FPU register.
+ * 2013-06-18     aozima       add restore MSP feature.
+ * 2013-06-23     aozima       support lazy stack optimized.
+ * 2018-07-24     aozima       enhancement hard fault exception handler.
+ */
+
+/**
+ * @addtogroup cortex-m4
+ */
+/*@{*/
+
+.cpu cortex-m4
+.syntax unified
+.thumb
+.text
+
+.equ    SCB_VTOR,           0xE000ED08              /* Vector Table Offset Register */
+.equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
+.equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
+.equ    NVIC_PENDSV_PRI,    0xFFFF0000              /* PendSV and SysTick priority value (lowest) */
+.equ    NVIC_PENDSVSET,     0x10000000              /* value to trigger PendSV exception */
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.global rt_hw_interrupt_disable
+.type rt_hw_interrupt_disable, %function
+rt_hw_interrupt_disable:
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.global rt_hw_interrupt_enable
+.type rt_hw_interrupt_enable, %function
+rt_hw_interrupt_enable:
+    MSR     PRIMASK, r0
+    BX      LR
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.global rt_hw_context_switch_interrupt
+.type rt_hw_context_switch_interrupt, %function
+.global rt_hw_context_switch
+.type rt_hw_context_switch, %function
+
+rt_hw_context_switch_interrupt:
+rt_hw_context_switch:
+    /* set rt_thread_switch_interrupt_flag to 1 */
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOV     r3, #1
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
+    STR     r0, [r2]
+
+_reswitch:
+    LDR     r2, =rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
+    STR     r1, [r2]
+
+    LDR r0, =NVIC_INT_CTRL              /* trigger the PendSV exception (causes context switch) */
+    LDR r1, =NVIC_PENDSVSET
+    STR r1, [r0]
+    BX  LR
+
+/* r0 --> switch from thread stack
+ * r1 --> switch to thread stack
+ * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+ */
+.global PendSV_Handler
+.type PendSV_Handler, %function
+PendSV_Handler:
+    /* disable interrupt to protect context switch */
+    MRS r2, PRIMASK
+    CPSID   I
+
+    /* get rt_thread_switch_interrupt_flag */
+    LDR     r0, =rt_thread_switch_interrupt_flag    /* r0 = &rt_thread_switch_interrupt_flag */
+    LDR     r1, [r0]                                /* r1 = *r1 */
+    CMP     r1, #0x00                               /* compare r1 == 0x00 */
+    BNE     schedule
+    MSR     PRIMASK, r2                             /* if r1 == 0x00, do msr PRIMASK, r2 */
+    BX      lr                                      /* if r1 == 0x00, do bx lr */
+
+schedule:
+    PUSH    {r2}                                    /* store interrupt state */
+
+    /* clear rt_thread_switch_interrupt_flag to 0 */
+    MOV     r1, #0x00                               /* r1 = 0x00 */
+    STR     r1, [r0]                                /* *r0 = r1 */
+
+    /* skip register save at the first time */
+    LDR     r0, =rt_interrupt_from_thread           /* r0 = &rt_interrupt_from_thread */
+    LDR     r1, [r0]                                /* r1 = *r0 */
+    CBZ     r1, switch_to_thread                    /* if r1 == 0, goto switch_to_thread */
+
+    /* Whether TrustZone thread stack exists */
+    LDR     r1,  =rt_trustzone_current_context      /* r1 = &rt_secure_current_context */
+    LDR     r1, [r1]                                /* r1 = *r1 */
+    CBZ     r1, contex_ns_store                     /* if r1 == 0, goto contex_ns_store */
+
+    /*call TrustZone fun, Save TrustZone stack */
+    STMFD   sp!, {r0-r1, lr}                        /* push register */
+    MOV     r0, r1                                  /* r0 = rt_secure_current_context */
+    BL rt_trustzone_context_store                   /* call TrustZone store fun */
+    LDMFD   sp!, {r0-r1, lr}                        /* pop register */
+
+    /* check break from TrustZone */
+    MOV     r2, lr                                  /* r2 = lr */
+    TST     r2, #0x40                               /* if EXC_RETURN[6] is 1, TrustZone stack was used */
+    BEQ     contex_ns_store                         /* if r2 & 0x40 == 0, goto contex_ns_store */
+
+    /* push PSPLIM CONTROL PSP LR current_context to stack */
+    MRS     r3, psplim                              /* r3 = psplim */
+    MRS     r4, control                             /* r4 = control */
+    MRS     r5, psp                                 /* r5 = psp */
+    STMFD   r5!, {r1-r4}                            /* push to thread stack */
+
+    /* update from thread stack pointer */
+    LDR     r0, [r0]                                /* r0 = rt_thread_switch_interrupt_flag */
+    STR     r5, [r0]                                /* *r0 = r5 */
+    b switch_to_thread                              /* goto switch_to_thread */
+
+contex_ns_store:
+
+    MRS     r1, psp                                 /* get from thread stack pointer */
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    TST     lr, #0x10                               /* if(!EXC_RETURN[4]) */
+    VSTMDBEQ  r1!, {d8 - d15}                       /* push FPU register s16~s31 */
+#endif
+
+    STMFD   r1!, {r4 - r11}                         /* push r4 - r11 register */
+
+    LDR     r2,  =rt_trustzone_current_context      /* r2 = &rt_secure_current_context */
+    LDR     r2, [r2]                                /* r2 = *r2 */
+    MOV     r3, lr                                  /* r3 = lr */
+    MRS     r4, psplim                              /* r4 = psplim */
+    MRS     r5, control                             /* r5 = control */
+    STMFD   r1!, {r2-r5}                            /* push to thread stack */
+
+    LDR     r0, [r0]
+    STR     r1, [r0]                                /* update from thread stack pointer */
+
+switch_to_thread:
+    LDR     r1, =rt_interrupt_to_thread
+    LDR     r1, [r1]
+    LDR     r1, [r1]                                /* load thread stack pointer */
+
+    /* update current TrustZone context */
+    LDMFD   r1!, {r2-r5}                            /* pop thread stack */
+    MSR     psplim, r4                              /* psplim = r4 */
+    MSR     control, r5                             /* control = r5 */
+    MOV     lr, r3                                  /* lr = r3 */
+    LDR     r6,  =rt_trustzone_current_context      /* r6 = &rt_secure_current_context */
+    STR     r2, [r6]                                /* *r6 = r2 */
+    MOV     r0, r2                                  /* r0 = r2 */
+
+    /* Whether TrustZone thread stack exists */
+    CBZ     r0, contex_ns_load                      /* if r0 == 0, goto contex_ns_load */
+    PUSH    {r1, r3}                                /* push lr, thread_stack */
+    BL rt_trustzone_context_load                    /* call TrustZone load fun */
+    POP     {r1, r3}                                /* pop lr, thread_stack */
+    MOV     lr, r3                                  /* lr = r1 */
+    TST     r3, #0x40                               /* if EXC_RETURN[6] is 1, TrustZone stack was used */
+    BEQ     contex_ns_load                          /* if r1 & 0x40 == 0, goto contex_ns_load */
+    B pendsv_exit
+
+contex_ns_load:
+    LDMFD   r1!, {r4 - r11}                         /* pop r4 - r11 register */
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    TST     lr, #0x10                               /* if(!EXC_RETURN[4]) */
+    VLDMIAEQ  r1!, {d8 - d15}                       /* pop FPU register s16~s31 */
+#endif
+
+pendsv_exit:
+    MSR     psp, r1                                 /* update stack pointer */
+    /* restore interrupt */
+    POP    {r2}
+    MSR     PRIMASK, r2
+
+    BX      lr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.global rt_hw_context_switch_to
+.type rt_hw_context_switch_to, %function
+rt_hw_context_switch_to:
+    LDR r1, =rt_interrupt_to_thread
+    STR r0, [r1]
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    /* CLEAR CONTROL.FPCA */
+    MRS     r2, CONTROL         /* read */
+    BIC     r2, #0x04           /* modify */
+    MSR     CONTROL, r2         /* write-back */
+#endif
+
+    /* set from thread to 0 */
+    LDR r1, =rt_interrupt_from_thread
+    MOV r0, #0x0
+    STR r0, [r1]
+
+    /* set interrupt flag to 1 */
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOV     r0, #1
+    STR     r0, [r1]
+
+    /* set the PendSV and SysTick exception priority */
+    LDR r0, =NVIC_SYSPRI2
+    LDR r1, =NVIC_PENDSV_PRI
+    LDR.W   r2, [r0,#0x00]       /* read       */
+    ORR     r1,r1,r2             /* modify     */
+    STR     r1, [r0]             /* write-back */
+
+    LDR r0, =NVIC_INT_CTRL      /* trigger the PendSV exception (causes context switch) */
+    LDR r1, =NVIC_PENDSVSET
+    STR r1, [r0]
+
+    /* restore MSP */
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
+    /* enable interrupts at processor level */
+    CPSIE   F
+    CPSIE   I
+
+    /* never reach here! */
+
+/* compatible with old version */
+.global rt_hw_interrupt_thread_switch
+.type rt_hw_interrupt_thread_switch, %function
+rt_hw_interrupt_thread_switch:
+    BX  lr
+    NOP
+
+.global HardFault_Handler
+.type HardFault_Handler, %function
+HardFault_Handler:
+    /* get current context */
+    MRS     r0, msp                                 /* get fault context from handler. */
+    TST     lr, #0x04                               /* if(!EXC_RETURN[2]) */
+    BEQ     get_sp_done
+    MRS     r0, psp                                 /* get fault context from thread. */
+get_sp_done:
+
+    STMFD   r0!, {r4 - r11}                         /* push r4 - r11 register */
+
+    LDR     r2,  =rt_trustzone_current_context      /* r2 = &rt_secure_current_context */
+    LDR     r2, [r2]                                /* r2 = *r2 */
+    MOV     r3, lr                                  /* r3 = lr */
+    MRS     r4, psplim                              /* r4 = psplim */
+    MRS     r5, control                             /* r5 = control */
+    STMFD   r0!, {r2-r5}                            /* push to thread stack */
+
+    STMFD   r0!, {lr}                               /* push exec_return register */
+
+    TST     lr, #0x04                               /* if(!EXC_RETURN[2]) */
+    BEQ     update_msp
+    MSR     psp, r0                                 /* update stack pointer to PSP. */
+    B       update_done
+update_msp:
+    MSR     msp, r0                                 /* update stack pointer to MSP. */
+update_done:
+
+    PUSH    {LR}
+    BL      rt_hw_hard_fault_exception
+    POP     {LR}
+
+    ORR     lr, lr, #0x04
+    BX      lr

libcpu/arm/cortex-m33/context_iar.S

@@ -0,0 +1,300 @@
+;/*
+; * Copyright (c) 2006-2018, RT-Thread Development Team
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2009-01-17     Bernard      first version
+; * 2009-09-27     Bernard      add protect when contex switch occurs
+; * 2012-01-01     aozima       support context switch load/store FPU register.
+; * 2013-06-18     aozima       add restore MSP feature.
+; * 2013-06-23     aozima       support lazy stack optimized.
+; * 2018-07-24     aozima       enhancement hard fault exception handler.
+; */
+
+;/**
+; * @addtogroup cortex-m33
+; */
+;/*@{*/
+
+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
+NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
+NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
+NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
+
+    SECTION    .text:CODE(2)
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
+    IMPORT rt_trustzone_current_context
+    IMPORT rt_trustzone_context_load
+    IMPORT rt_trustzone_context_store
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+    EXPORT rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+    EXPORT  rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    MSR     PRIMASK, r0
+    BX      LR
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+    EXPORT rt_hw_context_switch_interrupt
+    EXPORT rt_hw_context_switch
+rt_hw_context_switch_interrupt:
+rt_hw_context_switch:
+    ; set rt_thread_switch_interrupt_flag to 1
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOV     r3, #1
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    STR     r0, [r2]
+
+_reswitch
+    LDR     r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    STR     r1, [r2]
+
+    LDR     r0, =NVIC_INT_CTRL              ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+    BX      LR
+
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+    EXPORT PendSV_Handler
+PendSV_Handler:
+
+    ; disable interrupt to protect context switch
+    MRS     r2, PRIMASK
+    CPSID   I
+
+    ; get rt_thread_switch_interrupt_flag
+    LDR     r0, =rt_thread_switch_interrupt_flag    ; r0 = &rt_thread_switch_interrupt_flag
+    LDR     r1, [r0]                                ; r1 = *r1
+    CMP     r1, #0x00                               ; compare r1 == 0x00
+    BNE     schedule
+    MSR     PRIMASK, r2                             ; if r1 == 0x00, do msr PRIMASK, r2
+    BX      lr                                      ; if r1 == 0x00, do bx lr
+
+schedule
+    PUSH    {r2}                                    ; store interrupt state
+
+    ; clear rt_thread_switch_interrupt_flag to 0
+    MOV     r1, #0x00                               ; r1 = 0x00
+    STR     r1, [r0]                                ; *r0 = r1
+
+    ; skip register save at the first time
+    LDR     r0, =rt_interrupt_from_thread           ; r0 = &rt_interrupt_from_thread
+    LDR     r1, [r0]                                ; r1 = *r0
+    CBZ     r1, switch_to_thread                    ; if r1 == 0, goto switch_to_thread
+
+    ; Whether TrustZone thread stack exists
+    LDR     r1,  =rt_trustzone_current_context      ; r1 = &rt_secure_current_context
+    LDR     r1, [r1]                                ; r1 = *r1
+    CBZ     r1, contex_ns_store                     ; if r1 == 0, goto contex_ns_store
+
+    ;call TrustZone fun, Save TrustZone stack
+    STMFD   sp!, {r0-r1, lr}                        ; push register
+    MOV     r0, r1                                  ; r0 = rt_secure_current_context
+    BL rt_trustzone_context_store                   ; call TrustZone store fun
+    LDMFD   sp!, {r0-r1, lr}                        ; pop register
+
+    ; check break from TrustZone
+    MOV     r2, lr                                  ; r2 = lr
+    TST     r2, #0x40                               ; if EXC_RETURN[6] is 1, TrustZone stack was used
+    BEQ     contex_ns_store                         ; if r2 & 0x40 == 0, goto contex_ns_store
+
+    ; push PSPLIM CONTROL PSP LR current_context to stack
+    MRS     r3, psplim                              ; r3 = psplim
+    MRS     r4, control                             ; r4 = control
+    MRS     r5, psp                                 ; r5 = psp
+    STMFD   r5!, {r1-r4}                            ; push to thread stack
+
+    ; update from thread stack pointer
+    LDR     r0, [r0]                                ; r0 = rt_thread_switch_interrupt_flag
+    STR     r5, [r0]                                ; *r0 = r5
+    b switch_to_thread                              ; goto switch_to_thread
+
+contex_ns_store
+
+    MRS     r1, psp                                 ; get from thread stack pointer
+
+#if defined ( __ARMVFP__ )
+    TST     lr, #0x10                               ; if(!EXC_RETURN[4])
+    BNE     skip_push_fpu
+    VSTMDB  r1!, {d8 - d15}                         ; push FPU register s16~s31
+skip_push_fpu
+#endif
+
+    STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
+
+    LDR     r2,  =rt_trustzone_current_context      ; r2 = &rt_secure_current_context
+    LDR     r2, [r2]                                ; r2 = *r2
+    MOV     r3, lr                                  ; r3 = lr
+    MRS     r4, psplim                              ; r4 = psplim
+    MRS     r5, control                             ; r5 = control
+    STMFD   r1!, {r2-r5}                            ; push to thread stack
+
+    LDR     r0, [r0]
+    STR     r1, [r0]                                ; update from thread stack pointer
+
+switch_to_thread
+
+    LDR     r1, =rt_interrupt_to_thread
+    LDR     r1, [r1]
+    LDR     r1, [r1]                ; load thread stack pointer
+
+    ; update current TrustZone context
+    LDMFD   r1!, {r2-r5}                            ; pop thread stack
+    MSR     psplim, r4                              ; psplim = r4
+    MSR     control, r5                             ; control = r5
+    MOV     lr, r3                                  ; lr = r3
+    LDR     r6,  =rt_trustzone_current_context      ; r6 = &rt_secure_current_context
+    STR     r2, [r6]                                ; *r6 = r2
+    MOV     r0, r2                                  ; r0 = r2
+
+    ; Whether TrustZone thread stack exists
+    CBZ     r0, contex_ns_load                      ; if r0 == 0, goto contex_ns_load
+    PUSH    {r1, r3}                                ; push lr, thread_stack
+    BL rt_trustzone_context_load                    ; call TrustZone load fun
+    POP     {r1, r3}                                ; pop lr, thread_stack
+    MOV     lr, r3                                  ; lr = r1
+    TST     r3, #0x40                               ; if EXC_RETURN[6] is 1, TrustZone stack was used
+    BEQ     contex_ns_load                          ; if r1 & 0x40 == 0, goto contex_ns_load
+    B pendsv_exit
+
+contex_ns_load
+    LDMFD   r1!, {r4 - r11}                         ; pop r4 - r11 register
+
+#if defined ( __ARMVFP__ )
+    TST     lr, #0x10                               ; if(!EXC_RETURN[4])
+    BNE     skip_pop_fpu
+    VLDMIA  r1!, {d8 - d15}                         ; pop FPU register s16~s31
+skip_pop_fpu
+#endif
+
+pendsv_exit
+    MSR     psp, r1                                 ; update stack pointer
+    ; restore interrupt
+    POP    {r2}
+    MSR     PRIMASK, r2
+
+    BX      lr
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; */
+    EXPORT rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    LDR     r1, =rt_interrupt_to_thread
+    STR     r0, [r1]
+
+#if defined ( __ARMVFP__ )
+    ; CLEAR CONTROL.FPCA
+    MRS     r2, CONTROL             ; read
+    BIC     r2, r2, #0x04           ; modify
+    MSR     CONTROL, r2             ; write-back
+#endif
+
+    ; set from thread to 0
+    LDR     r1, =rt_interrupt_from_thread
+    MOV     r0, #0x0
+    STR     r0, [r1]
+
+    ; set interrupt flag to 1
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOV     r0, #1
+    STR     r0, [r1]
+
+    ; set the PendSV and SysTick exception priority
+    LDR     r0, =NVIC_SYSPRI2
+    LDR     r1, =NVIC_PENDSV_PRI
+    LDR.W   r2, [r0,#0x00]       ; read
+    ORR     r1,r1,r2             ; modify
+    STR     r1, [r0]             ; write-back
+
+    LDR     r0, =NVIC_INT_CTRL      ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+
+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
+    ; enable interrupts at processor level
+    CPSIE   F
+    CPSIE   I
+
+    ; never reach here!
+
+; compatible with old version
+    EXPORT rt_hw_interrupt_thread_switch
+rt_hw_interrupt_thread_switch:
+    BX      lr
+
+    IMPORT rt_hw_hard_fault_exception
+    EXPORT HardFault_Handler
+HardFault_Handler:
+
+    ; get current context
+    MRS     r0, msp                                 ; get fault context from handler.
+    TST     lr, #0x04                               ; if(!EXC_RETURN[2])
+    BEQ     get_sp_done
+    MRS     r0, psp                                 ; get fault context from thread.
+get_sp_done
+
+    STMFD   r0!, {r4 - r11}                         ; push r4 - r11 register
+    
+    LDR     r2,  =rt_trustzone_current_context      ; r2 = &rt_secure_current_context
+    LDR     r2, [r2]                                ; r2 = *r2
+    MOV     r3, lr                                  ; r3 = lr
+    MRS     r4, psplim                              ; r4 = psplim
+    MRS     r5, control                             ; r5 = control
+    STMFD   r0!, {r2-r5}                            ; push to thread stack
+
+    STMFD   r0!, {lr}                               ; push exec_return register
+
+    TST     lr, #0x04                               ; if(!EXC_RETURN[2])
+    BEQ     update_msp
+    MSR     psp, r0                                 ; update stack pointer to PSP.
+    B       update_done
+update_msp
+    MSR     msp, r0                                 ; update stack pointer to MSP.
+update_done
+
+    PUSH    {lr}
+    BL      rt_hw_hard_fault_exception
+    POP     {lr}
+
+    ORR     lr, lr, #0x04
+    BX      lr
+
+    END

libcpu/arm/cortex-m33/context_rvds.S

@@ -0,0 +1,306 @@
+;/*
+;* Copyright (c) 2006-2018, RT-Thread Development Team
+;*
+;* SPDX-License-Identifier: Apache-2.0
+;*
+; * Change Logs:
+; * Date           Author       Notes
+; * 2009-01-17     Bernard      first version.
+; * 2012-01-01     aozima       support context switch load/store FPU register.
+; * 2013-06-18     aozima       add restore MSP feature.
+; * 2013-06-23     aozima       support lazy stack optimized.
+; * 2018-07-24     aozima       enhancement hard fault exception handler.
+; */
+
+;/**
+; * @addtogroup cortex-m33
+; */
+;/*@{*/
+
+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
+NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
+NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
+NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
+    IMPORT rt_trustzone_current_context
+    IMPORT rt_trustzone_context_load
+    IMPORT rt_trustzone_context_store
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+rt_hw_interrupt_disable    PROC
+    EXPORT  rt_hw_interrupt_disable
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+    ENDP
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+rt_hw_interrupt_enable    PROC
+    EXPORT  rt_hw_interrupt_enable
+    MSR     PRIMASK, r0
+    BX      LR
+    ENDP
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+rt_hw_context_switch_interrupt
+    EXPORT rt_hw_context_switch_interrupt
+rt_hw_context_switch    PROC
+    EXPORT rt_hw_context_switch
+
+    ; set rt_thread_switch_interrupt_flag to 1
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOV     r3, #1
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    STR     r0, [r2]
+
+_reswitch
+    LDR     r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    STR     r1, [r2]
+
+    LDR     r0, =NVIC_INT_CTRL              ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+    BX      LR
+    ENDP
+
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+PendSV_Handler   PROC
+    EXPORT PendSV_Handler
+
+    ; disable interrupt to protect context switch
+    MRS     r2, PRIMASK                             ; R2 = PRIMASK
+    CPSID   I                                       ; disable all interrupt
+
+    ; get rt_thread_switch_interrupt_flag
+    LDR     r0, =rt_thread_switch_interrupt_flag    ; r0 = &rt_thread_switch_interrupt_flag
+    LDR     r1, [r0]                                ; r1 = *r1
+    CMP     r1, #0x00                               ; compare r1 == 0x00
+    BNE     schedule
+    MSR     PRIMASK, r2                             ; if r1 == 0x00, do msr PRIMASK, r2
+    BX      lr                                      ; if r1 == 0x00, do bx lr
+
+schedule
+    PUSH    {r2}                                    ; store interrupt state
+
+    ; clear rt_thread_switch_interrupt_flag to 0
+    MOV     r1, #0x00                               ; r1 = 0x00
+    STR     r1, [r0]                                ; *r0 = r1
+
+    ; skip register save at the first time
+    LDR     r0, =rt_interrupt_from_thread           ; r0 = &rt_interrupt_from_thread
+    LDR     r1, [r0]                                ; r1 = *r0
+    CBZ     r1, switch_to_thread                    ; if r1 == 0, goto switch_to_thread
+
+    ; Whether TrustZone thread stack exists
+    LDR     r1,  =rt_trustzone_current_context      ; r1 = &rt_secure_current_context
+    LDR     r1, [r1]                                ; r1 = *r1
+    CBZ     r1, contex_ns_store                     ; if r1 == 0, goto contex_ns_store
+
+    ;call TrustZone fun, Save TrustZone stack
+    STMFD   sp!, {r0-r1, lr}                        ; push register
+    MOV     r0, r1                                  ; r0 = rt_secure_current_context
+    BL rt_trustzone_context_store                   ; call TrustZone store fun
+    LDMFD   sp!, {r0-r1, lr}                        ; pop register
+
+    ; check break from TrustZone
+    MOV     r2, lr                                  ; r2 = lr
+    TST     r2, #0x40                               ; if EXC_RETURN[6] is 1, TrustZone stack was used
+    BEQ     contex_ns_store                         ; if r2 & 0x40 == 0, goto contex_ns_store
+
+    ; push PSPLIM CONTROL PSP LR current_context to stack
+    MRS     r3, psplim                              ; r3 = psplim
+    MRS     r4, control                             ; r4 = control
+    MRS     r5, psp                                 ; r5 = psp
+    STMFD   r5!, {r1-r4}                            ; push to thread stack
+
+    ; update from thread stack pointer
+    LDR     r0, [r0]                                ; r0 = rt_thread_switch_interrupt_flag
+    STR     r5, [r0]                                ; *r0 = r5
+    b switch_to_thread                              ; goto switch_to_thread
+
+contex_ns_store
+
+    MRS     r1, psp                                 ; get from thread stack pointer
+
+    IF      {FPU} != "SoftVFP"
+    TST     lr, #0x10                               ; if(!EXC_RETURN[4])
+    VSTMFDEQ  r1!, {d8 - d15}                       ; push FPU register s16~s31
+    ENDIF
+
+    STMFD   r1!, {r4 - r11}                         ; push r4 - r11 register
+
+    LDR     r2,  =rt_trustzone_current_context      ; r2 = &rt_secure_current_context
+    LDR     r2, [r2]                                ; r2 = *r2
+    MOV     r3, lr                                  ; r3 = lr
+    MRS     r4, psplim                              ; r4 = psplim
+    MRS     r5, control                             ; r5 = control
+    STMFD   r1!, {r2-r5}                            ; push to thread stack
+
+    LDR     r0, [r0]
+    STR     r1, [r0]                                ; update from thread stack pointer
+
+switch_to_thread
+    LDR     r1, =rt_interrupt_to_thread
+    LDR     r1, [r1]
+    LDR     r1, [r1]                                ; load thread stack pointer
+
+    ; update current TrustZone context
+    LDMFD   r1!, {r2-r5}                            ; pop thread stack
+    MSR     psplim, r4                              ; psplim = r4
+    MSR     control, r5                             ; control = r5
+    MOV     lr, r3                                  ; lr = r3
+    LDR     r6,  =rt_trustzone_current_context      ; r6 = &rt_secure_current_context
+    STR     r2, [r6]                                ; *r6 = r2
+    MOV     r0, r2                                  ; r0 = r2
+
+    ; Whether TrustZone thread stack exists
+    CBZ     r0, contex_ns_load                      ; if r0 == 0, goto contex_ns_load
+    PUSH    {r1, r3}                                ; push lr, thread_stack
+    BL rt_trustzone_context_load                    ; call TrustZone load fun
+    POP     {r1, r3}                                ; pop lr, thread_stack
+    MOV     lr, r3                                  ; lr = r1
+    TST     r3, #0x40                               ; if EXC_RETURN[6] is 1, TrustZone stack was used
+    BEQ     contex_ns_load                          ; if r1 & 0x40 == 0, goto contex_ns_load
+    B pendsv_exit
+
+contex_ns_load
+    LDMFD   r1!, {r4 - r11}                         ; pop r4 - r11 register
+
+    IF      {FPU} != "SoftVFP"
+    TST     lr, #0x10                               ; if(!EXC_RETURN[4])
+    VLDMFDEQ  r1!, {d8 - d15}                       ; pop FPU register s16~s31
+    ENDIF
+
+pendsv_exit
+    MSR     psp, r1                                 ; update stack pointer
+    ; restore interrupt
+    POP    {r2}
+    MSR     PRIMASK, r2
+
+    BX      lr
+    ENDP
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; * this fucntion is used to perform the first thread switch
+; */
+rt_hw_context_switch_to    PROC
+    EXPORT rt_hw_context_switch_to
+    ; set to thread
+    LDR     r1, =rt_interrupt_to_thread
+    STR     r0, [r1]
+
+    IF      {FPU} != "SoftVFP"
+    ; CLEAR CONTROL.FPCA
+    MRS     r2, CONTROL             ; read
+    BIC     r2, #0x04               ; modify
+    MSR     CONTROL, r2             ; write-back
+    ENDIF
+
+    ; set from thread to 0
+    LDR     r1, =rt_interrupt_from_thread
+    MOV     r0, #0x0
+    STR     r0, [r1]
+
+    ; set interrupt flag to 1
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOV     r0, #1
+    STR     r0, [r1]
+
+    ; set the PendSV and SysTick exception priority
+    LDR     r0, =NVIC_SYSPRI2
+    LDR     r1, =NVIC_PENDSV_PRI
+    LDR.W   r2, [r0,#0x00]       ; read
+    ORR     r1,r1,r2             ; modify
+    STR     r1, [r0]             ; write-back
+
+    ; trigger the PendSV exception (causes context switch)
+    LDR     r0, =NVIC_INT_CTRL
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+
+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    MSR     msp, r0
+
+    ; enable interrupts at processor level
+    CPSIE   F
+    CPSIE   I
+
+    ; never reach here!
+    ENDP
+
+; compatible with old version
+rt_hw_interrupt_thread_switch PROC
+    EXPORT rt_hw_interrupt_thread_switch
+    BX      lr
+    ENDP
+
+    IMPORT rt_hw_hard_fault_exception
+    EXPORT HardFault_Handler
+HardFault_Handler    PROC
+
+    ; get current context
+    MRS     r0, msp                 ;get fault context from handler
+    TST     lr, #0x04               ;if(!EXC_RETURN[2])
+    BEQ     get_sp_done
+    MRS     r0, psp                 ;get fault context from thread
+get_sp_done
+
+    STMFD   r0!, {r4 - r11}         ; push r4 - r11 register
+
+    LDR     r2,  =rt_trustzone_current_context      ; r2 = &rt_secure_current_context
+    LDR     r2, [r2]                                ; r2 = *r2
+    MOV     r3, lr                                  ; r3 = lr
+    MRS     r4, psplim                              ; r4 = psplim
+    MRS     r5, control                             ; r5 = control
+    STMFD   r0!, {r2-r5}                            ; push to thread stack
+
+    STMFD   r0!, {lr}               ; push exec_return register
+
+    TST     lr, #0x04               ; if(!EXC_RETURN[2])
+    BEQ     update_msp
+    MSR     psp, r0                 ; update stack pointer to PSP
+    B       update_done
+update_msp
+    MSR     msp, r0                 ; update stack pointer to MSP
+update_done
+
+    PUSH    {lr}
+    BL      rt_hw_hard_fault_exception
+    POP     {lr}
+
+    ORR     lr, lr, #0x04
+    BX      lr
+    ENDP
+
+    ALIGN   4
+
+    END

libcpu/arm/cortex-m33/cpuport.c

@@ -0,0 +1,506 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-10-21     Bernard      the first version.
+ * 2011-10-27     aozima       update for cortex-M4 FPU.
+ * 2011-12-31     aozima       fixed stack align issues.
+ * 2012-01-01     aozima       support context switch load/store FPU register.
+ * 2012-12-11     lgnq         fixed the coding style.
+ * 2012-12-23     aozima       stack addr align to 8byte.
+ * 2012-12-29     Bernard      Add exception hook.
+ * 2013-06-23     aozima       support lazy stack optimized.
+ * 2018-07-24     aozima       enhancement hard fault exception handler.
+ * 2019-07-03     yangjie      add __rt_ffs() for armclang.
+ */
+
+#include <rtthread.h>
+
+#if               /* ARMCC */ (  (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP ))    \
+                  /* Clang */ || (defined ( __CLANG_ARM ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) \
+                  /* IAR */   || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ ))        \
+                  /* GNU */   || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) )
+#define USE_FPU   1
+#else
+#define USE_FPU   0
+#endif
+
+/* exception and interrupt handler table */
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+/* exception hook */
+static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
+
+struct exception_stack_frame
+{
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r12;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t psr;
+};
+
+struct stack_frame
+{
+    rt_uint32_t tz;
+    rt_uint32_t lr;
+    rt_uint32_t psplim;
+    rt_uint32_t control;
+
+    /* r4 ~ r11 register */
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t r11;
+
+    struct exception_stack_frame exception_stack_frame;
+};
+
+struct exception_stack_frame_fpu
+{
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r12;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t psr;
+
+#if USE_FPU
+    /* FPU register */
+    rt_uint32_t S0;
+    rt_uint32_t S1;
+    rt_uint32_t S2;
+    rt_uint32_t S3;
+    rt_uint32_t S4;
+    rt_uint32_t S5;
+    rt_uint32_t S6;
+    rt_uint32_t S7;
+    rt_uint32_t S8;
+    rt_uint32_t S9;
+    rt_uint32_t S10;
+    rt_uint32_t S11;
+    rt_uint32_t S12;
+    rt_uint32_t S13;
+    rt_uint32_t S14;
+    rt_uint32_t S15;
+    rt_uint32_t FPSCR;
+    rt_uint32_t NO_NAME;
+#endif
+};
+
+struct stack_frame_fpu
+{
+    rt_uint32_t flag;
+
+    /* r4 ~ r11 register */
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t r11;
+
+#if USE_FPU
+    /* FPU register s16 ~ s31 */
+    rt_uint32_t s16;
+    rt_uint32_t s17;
+    rt_uint32_t s18;
+    rt_uint32_t s19;
+    rt_uint32_t s20;
+    rt_uint32_t s21;
+    rt_uint32_t s22;
+    rt_uint32_t s23;
+    rt_uint32_t s24;
+    rt_uint32_t s25;
+    rt_uint32_t s26;
+    rt_uint32_t s27;
+    rt_uint32_t s28;
+    rt_uint32_t s29;
+    rt_uint32_t s30;
+    rt_uint32_t s31;
+#endif
+
+    struct exception_stack_frame_fpu exception_stack_frame;
+};
+
+rt_uint8_t *rt_hw_stack_init(void       *tentry,
+                             void       *parameter,
+                             rt_uint8_t *stack_addr,
+                             void       *texit)
+{
+    struct stack_frame *stack_frame;
+    rt_uint8_t         *stk;
+    unsigned long       i;
+
+    stk  = stack_addr + sizeof(rt_uint32_t);
+    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
+    stk -= sizeof(struct stack_frame);
+
+    stack_frame = (struct stack_frame *)stk;
+
+    /* init all register */
+    for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
+    {
+        ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
+    }
+
+    stack_frame->exception_stack_frame.r0  = (unsigned long)parameter; /* r0 : argument */
+    stack_frame->exception_stack_frame.r1  = 0;                        /* r1 */
+    stack_frame->exception_stack_frame.r2  = 0;                        /* r2 */
+    stack_frame->exception_stack_frame.r3  = 0;                        /* r3 */
+    stack_frame->exception_stack_frame.r12 = 0;                        /* r12 */
+    stack_frame->exception_stack_frame.lr  = (unsigned long)texit;     /* lr */
+    stack_frame->exception_stack_frame.pc  = (unsigned long)tentry;    /* entry point, pc */
+    stack_frame->exception_stack_frame.psr = 0x01000000L;              /* PSR */
+
+    stack_frame->tz = 0x00;
+    stack_frame->lr = 0xFFFFFFBC;
+    stack_frame->psplim = 0x00;
+    stack_frame->control = 0x00;
+
+    /* return task's current stack address */
+    return stk;
+}
+
+/**
+ * This function set the hook, which is invoked on fault exception handling.
+ *
+ * @param exception_handle the exception handling hook function.
+ */
+void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
+{
+    rt_exception_hook = exception_handle;
+}
+
+#define SCB_CFSR        (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
+#define SCB_HFSR        (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
+#define SCB_MMAR        (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
+#define SCB_BFAR        (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
+#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED0C)  /* Reset control Address Register */
+#define SCB_RESET_VALUE 0x05FA0004                               /* Reset value, write to SCB_AIRCR can reset cpu */
+
+#define SCB_CFSR_MFSR   (*(volatile const unsigned char*)0xE000ED28)  /* Memory-management Fault Status Register */
+#define SCB_CFSR_BFSR   (*(volatile const unsigned char*)0xE000ED29)  /* Bus Fault Status Register */
+#define SCB_CFSR_UFSR   (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
+
+#ifdef RT_USING_FINSH
+static void usage_fault_track(void)
+{
+    rt_kprintf("usage fault:\n");
+    rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR);
+
+    if(SCB_CFSR_UFSR & (1<<0))
+    {
+        /* [0]:UNDEFINSTR */
+        rt_kprintf("UNDEFINSTR ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<1))
+    {
+        /* [1]:INVSTATE */
+        rt_kprintf("INVSTATE ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<2))
+    {
+        /* [2]:INVPC */
+        rt_kprintf("INVPC ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<3))
+    {
+        /* [3]:NOCP */
+        rt_kprintf("NOCP ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<8))
+    {
+        /* [8]:UNALIGNED */
+        rt_kprintf("UNALIGNED ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<9))
+    {
+        /* [9]:DIVBYZERO */
+        rt_kprintf("DIVBYZERO ");
+    }
+
+    rt_kprintf("\n");
+}
+
+static void bus_fault_track(void)
+{
+    rt_kprintf("bus fault:\n");
+    rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR);
+
+    if(SCB_CFSR_BFSR & (1<<0))
+    {
+        /* [0]:IBUSERR */
+        rt_kprintf("IBUSERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<1))
+    {
+        /* [1]:PRECISERR */
+        rt_kprintf("PRECISERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<2))
+    {
+        /* [2]:IMPRECISERR */
+        rt_kprintf("IMPRECISERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<3))
+    {
+        /* [3]:UNSTKERR */
+        rt_kprintf("UNSTKERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<4))
+    {
+        /* [4]:STKERR */
+        rt_kprintf("STKERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<7))
+    {
+        rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR);
+    }
+    else
+    {
+        rt_kprintf("\n");
+    }
+}
+
+static void mem_manage_fault_track(void)
+{
+    rt_kprintf("mem manage fault:\n");
+    rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR);
+
+    if(SCB_CFSR_MFSR & (1<<0))
+    {
+        /* [0]:IACCVIOL */
+        rt_kprintf("IACCVIOL ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<1))
+    {
+        /* [1]:DACCVIOL */
+        rt_kprintf("DACCVIOL ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<3))
+    {
+        /* [3]:MUNSTKERR */
+        rt_kprintf("MUNSTKERR ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<4))
+    {
+        /* [4]:MSTKERR */
+        rt_kprintf("MSTKERR ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<7))
+    {
+        /* [7]:MMARVALID */
+        rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR);
+    }
+    else
+    {
+        rt_kprintf("\n");
+    }
+}
+
+static void hard_fault_track(void)
+{
+    if(SCB_HFSR & (1UL<<1))
+    {
+        /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */
+        rt_kprintf("failed vector fetch\n");
+    }
+
+    if(SCB_HFSR & (1UL<<30))
+    {
+        /* [30]:FORCED, Indicates hard fault is taken because of bus fault,
+                        memory management fault, or usage fault. */
+        if(SCB_CFSR_BFSR)
+        {
+            bus_fault_track();
+        }
+
+        if(SCB_CFSR_MFSR)
+        {
+            mem_manage_fault_track();
+        }
+
+        if(SCB_CFSR_UFSR)
+        {
+            usage_fault_track();
+        }
+    }
+
+    if(SCB_HFSR & (1UL<<31))
+    {
+        /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */
+        rt_kprintf("debug event\n");
+    }
+}
+#endif /* RT_USING_FINSH */
+
+struct exception_info
+{
+    rt_uint32_t exc_return;
+    struct stack_frame stack_frame;
+};
+
+void rt_hw_hard_fault_exception(struct exception_info *exception_info)
+{
+    extern long list_thread(void);
+    struct exception_stack_frame *exception_stack = &exception_info->stack_frame.exception_stack_frame;
+    struct stack_frame *context = &exception_info->stack_frame;
+
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(exception_stack);
+        if (result == RT_EOK) return;
+    }
+
+    rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr);
+
+    rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0);
+    rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1);
+    rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2);
+    rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3);
+    rt_kprintf("r04: 0x%08x\n", context->r4);
+    rt_kprintf("r05: 0x%08x\n", context->r5);
+    rt_kprintf("r06: 0x%08x\n", context->r6);
+    rt_kprintf("r07: 0x%08x\n", context->r7);
+    rt_kprintf("r08: 0x%08x\n", context->r8);
+    rt_kprintf("r09: 0x%08x\n", context->r9);
+    rt_kprintf("r10: 0x%08x\n", context->r10);
+    rt_kprintf("r11: 0x%08x\n", context->r11);
+    rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12);
+    rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr);
+    rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc);
+
+    if (exception_info->exc_return & (1 << 2))
+    {
+        rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->name);
+
+#ifdef RT_USING_FINSH
+        list_thread();
+#endif
+    }
+    else
+    {
+        rt_kprintf("hard fault on handler\r\n\r\n");
+    }
+
+    if ( (exception_info->exc_return & 0x10) == 0)
+    {
+        rt_kprintf("FPU active!\r\n");
+    }
+
+#ifdef RT_USING_FINSH
+    hard_fault_track();
+#endif /* RT_USING_FINSH */
+
+    while (1);
+}
+
+/**
+ * shutdown CPU
+ */
+RT_WEAK void rt_hw_cpu_shutdown(void)
+{
+    rt_kprintf("shutdown...\n");
+
+    RT_ASSERT(0);
+}
+
+/**
+ * reset CPU
+ */
+RT_WEAK void rt_hw_cpu_reset(void)
+{
+    SCB_AIRCR = SCB_RESET_VALUE;
+}
+
+#ifdef RT_USING_CPU_FFS
+/**
+ * This function finds the first bit set (beginning with the least significant bit)
+ * in value and return the index of that bit.
+ *
+ * Bits are numbered starting at 1 (the least significant bit).  A return value of
+ * zero from any of these functions means that the argument was zero.
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
+ * shall return 0.
+ */
+#if defined(__CC_ARM)
+__asm int __rt_ffs(int value)
+{
+    CMP     r0, #0x00
+    BEQ     exit
+
+    RBIT    r0, r0
+    CLZ     r0, r0
+    ADDS    r0, r0, #0x01
+
+exit
+    BX      lr
+}
+#elif defined(__CLANG_ARM)
+int __rt_ffs(int value)
+{
+    if (value == 0) return value;
+
+    __asm volatile(
+        "RBIT    r0, r0               \n"
+        "CLZ     r0, r0               \n"
+        "ADDS    r0, r0, #0x01        \n"
+
+        : "=r"(value)
+        : "r"(value)
+    );
+    return value;
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+int __rt_ffs(int value)
+{
+    if (value == 0) return value;
+
+    asm("RBIT %0, %1" : "=r"(value) : "r"(value));
+    asm("CLZ  %0, %1" : "=r"(value) : "r"(value));
+    asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value));
+
+    return value;
+}
+#elif defined(__GNUC__)
+int __rt_ffs(int value)
+{
+    return __builtin_ffs(value);
+}
+#endif
+
+#endif

libcpu/arm/cortex-m33/syscall_gcc.S

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-10-25     tyx          first version
+ */
+
+.cpu cortex-m4
+.syntax unified
+.thumb
+.text
+
+/*
+ * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
+ */
+.global tzcall
+.type tzcall, %function
+tzcall:
+	SVC     1                       /* call SVC 1 */
+    BX      LR
+
+tzcall_entry:
+    PUSH    {R1, R4, LR}
+    MOV     R4, R1                  /* copy thread SP to R4 */
+    LDMFD   R4!, {r0 - r3}          /* pop user stack, get input arg0, arg1, arg2 */
+    STMFD   R4!, {r0 - r3}          /* push stack, user stack recovery */
+    BL      rt_secure_svc_handle    /* call fun */
+    POP     {R1, R4, LR}
+    STR     R0, [R1]                /* update return value */
+    BX      LR                      /* return to thread */
+
+syscall_entry:
+    BX      LR                      /* return to user app */
+
+.global SVC_Handler
+.type SVC_Handler, %function
+SVC_Handler:
+
+    /* get SP, save to R1 */
+    MRS     R1, MSP                 /* get fault context from handler. */
+    TST     LR, #0x04               /* if(!EXC_RETURN[2]) */
+    BEQ     get_sp_done
+    MRS     R1, PSP                 /* get fault context from thread. */
+get_sp_done:
+
+    /* get svc index */
+    LDR     R0, [R1, #24]
+    LDRB    R0, [R0, #-2]
+
+    /* if svc == 0, do system call */
+    CMP     R0, #0x0
+    BEQ    syscall_entry
+
+    /* if svc == 1, do TrustZone call */
+    CMP     R0, #0x1
+    BEQ    tzcall_entry

libcpu/arm/cortex-m33/syscall_iar.S

@@ -0,0 +1,63 @@
+;/*
+; * Copyright (c) 2006-2018, RT-Thread Development Team
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2019-10-25     tyx          first version
+; */
+
+;/*
+; * @addtogroup cortex-m33
+; */
+
+    SECTION    .text:CODE(2)
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+;/*
+; * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
+; */
+.global tzcall
+.type tzcall, %function
+tzcall:
+	SVC     1                       ;/* call SVC 1 */
+    BX      LR
+
+tzcall_entry:
+    PUSH    {R1, R4, LR}
+    MOV     R4, R1                  ;/* copy thread SP to R4 */
+    LDMFD   R4!, {r0 - r3}          ;/* pop user stack, get input arg0, arg1, arg2 */
+    STMFD   R4!, {r0 - r3}          ;/* push stack, user stack recovery */
+    BL      rt_secure_svc_handle    ;/* call fun */
+    POP     {R1, R4, LR}
+    STR     R0, [R1]                ;/* update return value */
+    BX      LR                      ;/* return to thread */
+
+syscall_entry:
+    BX      LR                      ;/* return to user app */
+
+.global SVC_Handler
+.type SVC_Handler, %function
+SVC_Handler:
+
+    ;/* get SP, save to R1 */
+    MRS     R1, MSP                 ;/* get fault context from handler. */
+    TST     LR, #0x04               ;/* if(!EXC_RETURN[2]) */
+    BEQ     get_sp_done
+    MRS     R1, PSP                 ;/* get fault context from thread. */
+get_sp_done:
+
+    ;/* get svc index */
+    LDR     R0, [R1, #24]
+    LDRB    R0, [R0, #-2]
+
+    ;/* if svc == 0, do system call */
+    CMP     R0, #0x0
+    BEQ    syscall_entry
+
+    ;/* if svc == 1, do TrustZone call */
+    CMP     R0, #0x1
+    BEQ    tzcall_entry

libcpu/arm/cortex-m33/syscall_rvds.S

@@ -0,0 +1,74 @@
+;/*
+; * Copyright (c) 2006-2018, RT-Thread Development Team
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2019-10-25     tyx          first version
+; */
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_secure_svc_handle
+
+;/*
+; * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
+; */
+tzcall PROC
+    EXPORT tzcall
+	SVC     1                       ;call SVC 1
+    BX      LR
+
+    ENDP
+
+tzcall_entry     PROC
+    PUSH    {R1, R4, LR}
+    MOV     R4, R1                  ; copy thread SP to R4
+    LDMFD   R4!, {r0 - r3}          ; pop user stack, get input arg0, arg1, arg2 
+    STMFD   R4!, {r0 - r3}          ; push stack, user stack recovery
+    BL      rt_secure_svc_handle    ; call fun
+    POP     {R1, R4, LR}
+    STR     R0, [R1]                ; update return value
+    BX      LR                      ; return to thread
+
+    ENDP
+
+syscall_entry     PROC
+    BX      LR                      ; return to user app
+
+    ENDP
+
+;/*
+; * void SVC_Handler(void);
+; */
+SVC_Handler    PROC
+    EXPORT SVC_Handler
+
+    ; get SP, save to R1
+    MRS     R1, MSP                 ;get fault context from handler
+    TST     LR, #0x04               ;if(!EXC_RETURN[2])
+    BEQ     get_sp_done
+    MRS     R1, PSP                 ;get fault context from thread
+get_sp_done
+
+    ; get svc index
+    LDR     R0, [R1, #24]
+    LDRB    R0, [R0, #-2]
+
+    ;if svc == 0, do system call
+    CMP     R0, #0x0
+    BEQ    syscall_entry
+
+    ;if svc == 1, do TrustZone call
+    CMP     R0, #0x1
+    BEQ    tzcall_entry
+
+    ENDP
+
+    ALIGN
+
+    END

libcpu/arm/cortex-m33/trustzone.c

@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-10-28     tyx          the first version.
+ */
+
+#include <rtthread.h>
+
+#ifdef ARM_CM33_ENABLE_TRUSTZONE
+extern void TZ_InitContextSystem_S(void);
+extern rt_uint32_t TZ_AllocModuleContext_S (rt_uint32_t module);
+extern rt_uint32_t TZ_FreeModuleContext_S(rt_uint32_t id);
+extern rt_uint32_t TZ_LoadContext_S(rt_uint32_t id);
+extern rt_uint32_t TZ_StoreContext_S(rt_uint32_t id);
+#else
+void TZ_InitContextSystem_S(void){}
+rt_uint32_t TZ_AllocModuleContext_S (rt_uint32_t module){return 0;}
+rt_uint32_t TZ_FreeModuleContext_S(rt_uint32_t id) {return 0;}
+rt_uint32_t TZ_LoadContext_S(rt_uint32_t id){return 0;};
+rt_uint32_t TZ_StoreContext_S(rt_uint32_t id){return 0;};
+#endif
+extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
+
+#define TZ_INIT_CONTEXT_ID     (0x1001)
+#define TZ_ALLOC_CONTEXT_ID    (0x1002)
+#define TZ_FREE_CONTEXT_ID     (0x1003)
+
+rt_ubase_t rt_trustzone_current_context;
+
+#if defined(__CC_ARM)
+static __inline rt_uint32_t __get_IPSR(void)
+{
+  register rt_uint32_t result          __asm("ipsr");
+  return(result);
+}
+#elif defined(__CLANG_ARM)
+__attribute__((always_inline)) static __inline rt_uint32_t __get_IPSR(void)
+{
+    rt_uint32_t result;
+
+    __asm volatile ("MRS %0, ipsr" : "=r" (result) );
+    return(result);
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+_Pragma("inline=forced") static inline int __get_IPSR(int value)
+{
+    rt_uint32_t result;
+
+    asm("MRS  %0, ipsr" : "=r"(result));
+    return result;
+}
+#elif defined(__GNUC__)
+__attribute__((always_inline)) static inline rt_uint32_t __get_IPSR(void)
+{
+  rt_uint32_t result;
+
+  __asm volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+#endif
+
+void rt_trustzone_init(void)
+{
+    static rt_uint8_t _init;
+
+    if (_init)
+        return;
+    tzcall(TZ_INIT_CONTEXT_ID, 0, 0, 0);
+    _init = 1;
+}
+
+rt_err_t rt_trustzone_enter(rt_ubase_t module)
+{
+    rt_trustzone_init();
+    if (tzcall(TZ_ALLOC_CONTEXT_ID, module, 0, 0))
+    {
+        return RT_EOK;
+    }
+    return -RT_ERROR;
+}
+
+rt_err_t rt_trustzone_exit(void)
+{
+    tzcall(TZ_FREE_CONTEXT_ID, 0, 0, 0);
+    return RT_EOK;
+}
+
+void rt_trustzone_context_store(rt_ubase_t context)
+{
+    TZ_StoreContext_S(context);
+}
+
+void rt_trustzone_context_load(rt_ubase_t context)
+{
+    TZ_LoadContext_S(context);
+}
+
+int rt_secure_svc_handle(int svc_id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2)
+{
+    rt_ubase_t tmp;
+    int res = 0;
+
+    switch (svc_id)
+    {
+    case TZ_INIT_CONTEXT_ID:
+        TZ_InitContextSystem_S();
+        break;
+    case TZ_ALLOC_CONTEXT_ID:
+        res = TZ_AllocModuleContext_S(arg0);
+        if (res <= 0)
+        {
+            rt_kprintf("Alloc Context Failed\n");
+        }
+        else
+        {
+            rt_trustzone_current_context = res;
+            TZ_LoadContext_S(res);
+        }
+        break;
+    case TZ_FREE_CONTEXT_ID:
+        TZ_FreeModuleContext_S(rt_trustzone_current_context);
+        rt_trustzone_current_context = 0;
+        break;
+    }
+    return res;
+}
+

libcpu/arm/cortex-m4/context_gcc.S

@@ -25,7 +25,7 @@
 .equ    SCB_VTOR,           0xE000ED08              /* Vector Table Offset Register */
 .equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
 .equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
-.equ    NVIC_PENDSV_PRI,    0x00FF0000              /* PendSV priority value (lowest) */
+.equ    NVIC_PENDSV_PRI,    0xFFFF0000              /* PendSV and SysTick priority value (lowest) */
 .equ    NVIC_PENDSVSET,     0x10000000              /* value to trigger PendSV exception */
 
 /*
@@ -182,7 +182,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    /* set the PendSV exception priority */
+    /* set the PendSV and SysTick exception priority */
     LDR r0, =NVIC_SYSPRI2
     LDR r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       /* read       */

libcpu/arm/cortex-m4/context_iar.S

@@ -21,7 +21,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     SECTION    .text:CODE(2)
@@ -186,7 +186,7 @@ rt_hw_context_switch_to:
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read

libcpu/arm/cortex-m4/context_rvds.S

@@ -20,7 +20,7 @@
 SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
 NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
 NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
-NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
 NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
 
     AREA |.text|, CODE, READONLY, ALIGN=2
@@ -186,7 +186,7 @@ rt_hw_context_switch_to    PROC
     MOV     r0, #1
     STR     r0, [r1]
 
-    ; set the PendSV exception priority
+    ; set the PendSV and SysTick exception priority
     LDR     r0, =NVIC_SYSPRI2
     LDR     r1, =NVIC_PENDSV_PRI
     LDR.W   r2, [r0,#0x00]       ; read

libcpu/arm/cortex-m4/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,6 +14,7 @@
  * 2012-12-29     Bernard      Add exception hook.
  * 2013-06-23     aozima       support lazy stack optimized.
  * 2018-07-24     aozima       enhancement hard fault exception handler.
+ * 2019-07-03     yangjie      add __rt_ffs() for armclang.
  */
 
 #include <rtthread.h>
@@ -453,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void)
  * @return return the index of the first bit set. If value is 0, then this function
  * shall return 0.
  */
-#if defined(__CC_ARM) || defined(__CLANG_ARM)
+#if defined(__CC_ARM)
 __asm int __rt_ffs(int value)
 {
     CMP     r0, #0x00
@@ -466,6 +467,24 @@ __asm int __rt_ffs(int value)
 exit
     BX      lr
 }
+#elif defined(__CLANG_ARM)
+int __rt_ffs(int value)
+{
+    __asm volatile(
+        "CMP     r0, #0x00            \n"
+        "BEQ     1f                   \n"
+
+        "RBIT    r0, r0               \n"
+        "CLZ     r0, r0               \n"
+        "ADDS    r0, r0, #0x01        \n"
+
+        "1:                           \n"
+
+        : "=r"(value)
+        : "r"(value)
+    );
+    return value;
+}
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {

libcpu/arm/cortex-m7/cpu_cache.c

@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-04-02     tanek        first implementation
+ * 2019-04-27     misonyo      update to cortex-m7 series
+ */
+
+#include <rthw.h>
+#include <rtdef.h>
+#include <board.h>
+
+/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */
+#define L1CACHE_LINESIZE_BYTE       (32)
+
+void rt_hw_cpu_icache_enable(void)
+{
+    SCB_EnableICache();
+}
+
+void rt_hw_cpu_icache_disable(void)
+{
+    SCB_DisableICache();
+}
+
+rt_base_t rt_hw_cpu_icache_status(void)
+{
+    return 0;
+}
+
+void rt_hw_cpu_icache_ops(int ops, void* addr, int size)
+{
+    rt_uint32_t address = (rt_uint32_t)addr & (rt_uint32_t) ~(L1CACHE_LINESIZE_BYTE - 1);
+    rt_int32_t size_byte = size + address - (rt_uint32_t)addr;
+    rt_uint32_t linesize = 32U;
+    if (ops & RT_HW_CACHE_INVALIDATE)
+    {
+        __DSB();
+        while (size_byte > 0)
+        {
+            SCB->ICIMVAU = address;
+            address += linesize;
+            size_byte -= linesize;
+        }
+        __DSB();
+        __ISB();
+    }
+}
+
+void rt_hw_cpu_dcache_enable(void)
+{
+    SCB_EnableDCache();
+}
+
+void rt_hw_cpu_dcache_disable(void)
+{
+    SCB_DisableDCache();
+}
+
+rt_base_t rt_hw_cpu_dcache_status(void)
+{
+    return 0;
+}
+
+void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
+{
+    rt_uint32_t startAddr = (rt_uint32_t)addr & (rt_uint32_t)~(L1CACHE_LINESIZE_BYTE - 1);
+    rt_uint32_t size_byte = size + (rt_uint32_t)addr - startAddr;
+
+    if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE))
+    {
+        SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte);
+    }
+    else if (ops & RT_HW_CACHE_FLUSH)
+    {
+        SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size_byte);
+    }
+    else if (ops & RT_HW_CACHE_INVALIDATE)
+    {
+        SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte);
+    }
+    else
+    {
+        RT_ASSERT(0);
+    }
+}

libcpu/arm/cortex-m7/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,6 +14,7 @@
  * 2012-12-29     Bernard      Add exception hook.
  * 2013-06-23     aozima       support lazy stack optimized.
  * 2018-07-24     aozima       enhancement hard fault exception handler.
+ * 2019-07-03     yangjie      add __rt_ffs() for armclang.
  */
 
 #include <rtthread.h>
@@ -453,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void)
  * @return return the index of the first bit set. If value is 0, then this function
  * shall return 0.
  */
-#if defined(__CC_ARM) || defined(__CLANG_ARM)
+#if defined(__CC_ARM)
 __asm int __rt_ffs(int value)
 {
     CMP     r0, #0x00
@@ -466,6 +467,24 @@ __asm int __rt_ffs(int value)
 exit
     BX      lr
 }
+#elif defined(__CLANG_ARM)
+int __rt_ffs(int value)
+{
+    __asm volatile(
+        "CMP     r0, #0x00            \n"
+        "BEQ     exit                 \n"
+
+        "RBIT    r0, r0               \n"
+        "CLZ     r0, r0               \n"
+        "ADDS    r0, r0, #0x01        \n"
+
+        "exit:                        \n"
+
+        : "=r"(value)
+        : "r"(value)
+    );
+    return value;
+}
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {

libcpu/arm/cortex-r4/armv7.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,23 +16,23 @@
 /* the exception stack without VFP registers */
 struct rt_hw_exp_stack
 {
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long sp;
-	unsigned long lr;
-	unsigned long pc;
-	unsigned long cpsr;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
 };
 
 #define USERMODE    0x10

libcpu/arm/cortex-r4/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -30,22 +30,22 @@ void rt_hw_cpu_reset()
  */
 void rt_hw_cpu_shutdown()
 {
-	rt_kprintf("shutdown...\n");
+    rt_kprintf("shutdown...\n");
 
-	while (1);
+    while (1);
 }
 
 #ifdef __TI_COMPILER_VERSION__
 #ifdef RT_USING_CPU_FFS
 int __rt_ffs(int value)
 {
-	if (value == 0)
-		return value;
+    if (value == 0)
+        return value;
 
-	__asm("    rsb r1, r0, #0");
-	__asm("    and r1, r1, r0");
-	__asm("    clz r1, r1");
-	__asm("    rsb r0, r1, #32");
+    __asm("    rsb r1, r0, #0");
+    __asm("    and r1, r1, r0");
+    __asm("    clz r1, r1");
+    __asm("    rsb r0, r1, #32");
 }
 #endif
 

libcpu/arm/cortex-r4/interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,7 +17,7 @@
 
 #include "armv7.h"
 
-#define MAX_HANDLERS	96
+#define MAX_HANDLERS    96
 
 /* exception and interrupt handler table */
 struct rt_irq_desc irq_desc[MAX_HANDLERS];
@@ -36,16 +36,16 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
 
 static void rt_hw_int_not_handle(int vector, void *param)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
 #define vimRAM (0xFFF82000U)
 
 void rt_hw_interrupt_init(void)
 {
-	register int i;
+    register int i;
 
-	rt_uint32_t *vect_addr;
+    rt_uint32_t *vect_addr;
 
     /* the initialization is done in sys_startup.c */
 
@@ -55,15 +55,15 @@ void rt_hw_interrupt_init(void)
     {
         irq_desc[i].handler = rt_hw_int_not_handle;
 
-		vect_addr  = (rt_uint32_t *)(vimRAM + i*4);
-		*vect_addr = (rt_uint32_t)&irq_desc[i];
+        vect_addr  = (rt_uint32_t *)(vimRAM + i*4);
+        *vect_addr = (rt_uint32_t)&irq_desc[i];
     }
 
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 void rt_hw_interrupt_mask(int vector)
@@ -86,21 +86,21 @@ void rt_hw_interrupt_umask(int vector)
  * @return the old handler
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-									void *param, const char *name)
+                                    void *param, const char *name)
 {
-	rt_isr_handler_t old_handler = RT_NULL;
-
-	if(vector >= 0 && vector < MAX_HANDLERS)
-	{
-		old_handler = irq_desc[vector].handler;
-		if (handler != RT_NULL)
-		{
-			irq_desc[vector].handler = handler;
-			irq_desc[vector].param = param;
-		}
-	}
-
-	return old_handler;
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if(vector >= 0 && vector < MAX_HANDLERS)
+    {
+        old_handler = irq_desc[vector].handler;
+        if (handler != RT_NULL)
+        {
+            irq_desc[vector].handler = handler;
+            irq_desc[vector].param = param;
+        }
+    }
+
+    return old_handler;
 }
 
 /*@}*/

libcpu/arm/cortex-r4/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-r4/start_gcc.S

@@ -36,6 +36,7 @@
 .globl stack_start
 .globl stack_top
 
+.align 3
 stack_start:
 .rept (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
 .byte 0

libcpu/arm/cortex-r4/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,13 +28,13 @@
  */
 void rt_hw_show_register (struct rt_hw_exp_stack *regs)
 {
-	rt_kprintf("Execption:\n");
-	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
 }
 
 /**
@@ -49,8 +49,8 @@ void rt_hw_trap_udef(struct rt_hw_exp_stack *regs)
 {
     rt_kprintf("undefined instruction\n");
     rt_hw_show_register(regs);
-	if (rt_thread_self() != RT_NULL)
-		rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
+    if (rt_thread_self() != RT_NULL)
+        rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
     rt_hw_cpu_shutdown();
 }
 
@@ -68,7 +68,7 @@ void rt_hw_trap_svc(struct rt_hw_exp_stack *regs)
     rt_kprintf("software interrupt\n");
     rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
     rt_hw_cpu_shutdown();
 }
@@ -86,7 +86,7 @@ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
     rt_kprintf("prefetch abort\n");
     rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
     rt_hw_cpu_shutdown();
 }
@@ -104,7 +104,7 @@ void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
     rt_kprintf("Data Abort ");
     rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
     rt_hw_cpu_shutdown();
 }
@@ -121,7 +121,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
     rt_kprintf("Reserved trap\n");
     rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
     rt_hw_cpu_shutdown();
 }
@@ -129,15 +129,15 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
 extern rt_isr_handler_t isr_table[];
 void rt_hw_trap_irq(void)
 {
-	int irqno;
-	struct rt_irq_desc* irq;
-	extern struct rt_irq_desc irq_desc[];
+    int irqno;
+    struct rt_irq_desc* irq;
+    extern struct rt_irq_desc irq_desc[];
 
-	irq = (struct rt_irq_desc*) vimREG->IRQVECREG;
-	irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc);
+    irq = (struct rt_irq_desc*) vimREG->IRQVECREG;
+    irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc);
 
-	/* invoke isr */
-	irq->handler(irqno, irq->param);
+    /* invoke isr */
+    irq->handler(irqno, irq->param);
 }
 
 void rt_hw_trap_fiq(void)

libcpu/risc-v/common/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/risc-v/common/cpuport.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/risc-v/common/riscv-ops.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/risc-v/common/riscv-plic.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/risc-v/e310/context_gcc.S

@@ -1,21 +1,7 @@
 ;/*
-; * File      : context_gcc.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2018, RT-Thread Development Team
+; * Copyright (c) 2006-2021, RT-Thread Development Team
 ; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes

libcpu/risc-v/e310/entry_gcc.S

@@ -1,21 +1,7 @@
 /*
- * File      : context_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

libcpu/risc-v/e310/stack.c

@@ -1,21 +1,7 @@
 /*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

libcpu/risc-v/k210/cpuport_smp.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/risc-v/k210/interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *