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@@ -1,2832 +0,0 @@
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-/*
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- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
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- *
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- * SPDX-License-Identifier: Apache-2.0
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- */
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-#ifndef _SOC_DSPI_MEM_REG_H_
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-#define _SOC_DSPI_MEM_REG_H_
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-
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-
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-#ifdef __cplusplus
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-extern "C" {
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-#endif
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-#include "soc.h"
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-
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-#define DSPI_MEM_CMD_REG (DR_REG_DSPI_MEM_BASE + 0x0)
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-/* DSPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */
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-/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operat
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-ion will be triggered when the bit is set. The bit will be cleared once the oper
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-ation done.1: enable 0: disable..*/
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-#define DSPI_MEM_USR (BIT(18))
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-#define DSPI_MEM_USR_M (BIT(18))
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-#define DSPI_MEM_USR_V 0x1
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-#define DSPI_MEM_USR_S 18
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-/* DSPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
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-/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta
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-te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
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-ate, 6:write data state, 7: done state, 8: read data end state..*/
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-#define DSPI_MEM_SLV_ST 0x0000000F
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-#define DSPI_MEM_SLV_ST_M ((DSPI_MEM_SLV_ST_V)<<(DSPI_MEM_SLV_ST_S))
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-#define DSPI_MEM_SLV_ST_V 0xF
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-#define DSPI_MEM_SLV_ST_S 4
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-/* DSPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
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-/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT
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-, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se
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-nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
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-#define DSPI_MEM_MST_ST 0x0000000F
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-#define DSPI_MEM_MST_ST_M ((DSPI_MEM_MST_ST_V)<<(DSPI_MEM_MST_ST_S))
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-#define DSPI_MEM_MST_ST_V 0xF
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-#define DSPI_MEM_MST_ST_S 0
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-
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-#define DSPI_MEM_CTRL_REG (DR_REG_DSPI_MEM_BASE + 0x8)
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-/* DSPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
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-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a
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-lways 1. 0: Others..*/
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-#define DSPI_MEM_DATA_IE_ALWAYS_ON (BIT(31))
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-#define DSPI_MEM_DATA_IE_ALWAYS_ON_M (BIT(31))
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-#define DSPI_MEM_DATA_IE_ALWAYS_ON_V 0x1
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-#define DSPI_MEM_DATA_IE_ALWAYS_ON_S 31
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-/* DSPI_MEM_DQS_IE_ALWAYS_ON : R/W ;bitpos:[30] ;default: 1'b0 ; */
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-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway
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-s 1. 0: Others..*/
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-#define DSPI_MEM_DQS_IE_ALWAYS_ON (BIT(30))
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-#define DSPI_MEM_DQS_IE_ALWAYS_ON_M (BIT(30))
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-#define DSPI_MEM_DQS_IE_ALWAYS_ON_V 0x1
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-#define DSPI_MEM_DQS_IE_ALWAYS_ON_S 30
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-/* DSPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
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-/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
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-ble 0: disable..*/
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-#define DSPI_MEM_FREAD_QIO (BIT(24))
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-#define DSPI_MEM_FREAD_QIO_M (BIT(24))
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-#define DSPI_MEM_FREAD_QIO_V 0x1
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-#define DSPI_MEM_FREAD_QIO_S 24
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-/* DSPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
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-/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
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-ble 0: disable..*/
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-#define DSPI_MEM_FREAD_DIO (BIT(23))
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-#define DSPI_MEM_FREAD_DIO_M (BIT(23))
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-#define DSPI_MEM_FREAD_DIO_V 0x1
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-#define DSPI_MEM_FREAD_DIO_S 23
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-/* DSPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
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-/*description: Write protect signal output when SPI is idle. 1: output high, 0: output low..*/
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-#define DSPI_MEM_WP_REG (BIT(21))
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-#define DSPI_MEM_WP_REG_M (BIT(21))
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-#define DSPI_MEM_WP_REG_V 0x1
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-#define DSPI_MEM_WP_REG_S 21
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-/* DSPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
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-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
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-#define DSPI_MEM_FREAD_QUAD (BIT(20))
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-#define DSPI_MEM_FREAD_QUAD_M (BIT(20))
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-#define DSPI_MEM_FREAD_QUAD_V 0x1
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-#define DSPI_MEM_FREAD_QUAD_S 20
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-/* DSPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
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-/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
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-#define DSPI_MEM_D_POL (BIT(19))
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-#define DSPI_MEM_D_POL_M (BIT(19))
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-#define DSPI_MEM_D_POL_V 0x1
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-#define DSPI_MEM_D_POL_S 19
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-/* DSPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
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-/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
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-#define DSPI_MEM_Q_POL (BIT(18))
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-#define DSPI_MEM_Q_POL_M (BIT(18))
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-#define DSPI_MEM_Q_POL_V 0x1
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-#define DSPI_MEM_Q_POL_S 18
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-/* DSPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
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-/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
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-#define DSPI_MEM_FREAD_DUAL (BIT(14))
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-#define DSPI_MEM_FREAD_DUAL_M (BIT(14))
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-#define DSPI_MEM_FREAD_DUAL_V 0x1
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-#define DSPI_MEM_FREAD_DUAL_S 14
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-/* DSPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
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-/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
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-UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
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-#define DSPI_MEM_FASTRD_MODE (BIT(13))
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-#define DSPI_MEM_FASTRD_MODE_M (BIT(13))
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-#define DSPI_MEM_FASTRD_MODE_V 0x1
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-#define DSPI_MEM_FASTRD_MODE_S 13
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-/* DSPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */
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-/*description: Apply 8 signals during command phase 1:enable 0: disable.*/
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-#define DSPI_MEM_FCMD_OCT (BIT(9))
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-#define DSPI_MEM_FCMD_OCT_M (BIT(9))
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-#define DSPI_MEM_FCMD_OCT_V 0x1
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-#define DSPI_MEM_FCMD_OCT_S 9
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-/* DSPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
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-/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
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-#define DSPI_MEM_FCMD_QUAD (BIT(8))
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-#define DSPI_MEM_FCMD_QUAD_M (BIT(8))
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-#define DSPI_MEM_FCMD_QUAD_V 0x1
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-#define DSPI_MEM_FCMD_QUAD_S 8
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-/* DSPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */
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-/*description: Apply 8 signals during address phase 1:enable 0: disable.*/
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-#define DSPI_MEM_FADDR_OCT (BIT(6))
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-#define DSPI_MEM_FADDR_OCT_M (BIT(6))
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-#define DSPI_MEM_FADDR_OCT_V 0x1
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-#define DSPI_MEM_FADDR_OCT_S 6
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-/* DSPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */
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-/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/
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-#define DSPI_MEM_FDIN_OCT (BIT(5))
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-#define DSPI_MEM_FDIN_OCT_M (BIT(5))
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-#define DSPI_MEM_FDIN_OCT_V 0x1
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-#define DSPI_MEM_FDIN_OCT_S 5
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-/* DSPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */
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-/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/
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-#define DSPI_MEM_FDOUT_OCT (BIT(4))
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-#define DSPI_MEM_FDOUT_OCT_M (BIT(4))
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-#define DSPI_MEM_FDOUT_OCT_V 0x1
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-#define DSPI_MEM_FDOUT_OCT_S 4
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-/* DSPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */
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-/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0]
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-is output by the MSPI controller in the second half part of dummy phase. It is u
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-sed to pre-drive flash..*/
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-#define DSPI_MEM_FDUMMY_WOUT (BIT(3))
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-#define DSPI_MEM_FDUMMY_WOUT_M (BIT(3))
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-#define DSPI_MEM_FDUMMY_WOUT_V 0x1
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-#define DSPI_MEM_FDUMMY_WOUT_S 3
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-/* DSPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */
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-/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i
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-s output by the MSPI controller in the first half part of dummy phase. It is use
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-d to mask invalid SPI_DQS in the half part of dummy phase..*/
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-#define DSPI_MEM_FDUMMY_RIN (BIT(2))
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-#define DSPI_MEM_FDUMMY_RIN_M (BIT(2))
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-#define DSPI_MEM_FDUMMY_RIN_V 0x1
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-#define DSPI_MEM_FDUMMY_RIN_S 2
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-/* DSPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
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-/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
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-vel of SPI_IO[7:0] is output by the MSPI controller..*/
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-#define DSPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1))
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-#define DSPI_MEM_WDUMMY_ALWAYS_OUT_M (BIT(1))
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-#define DSPI_MEM_WDUMMY_ALWAYS_OUT_V 0x1
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-#define DSPI_MEM_WDUMMY_ALWAYS_OUT_S 1
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-/* DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
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-/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
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-vel of SPI_DQS is output by the MSPI controller..*/
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-#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0))
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-#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(0))
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-#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1
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-#define DSPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0
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-
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-#define DSPI_MEM_CTRL1_REG (DR_REG_DSPI_MEM_BASE + 0xC)
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-/* DSPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
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-/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
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- send signals to AXI. Set this bit to reset these FIFO..*/
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-#define DSPI_MEM_TXFIFO_RST (BIT(31))
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-#define DSPI_MEM_TXFIFO_RST_M (BIT(31))
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-#define DSPI_MEM_TXFIFO_RST_V 0x1
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-#define DSPI_MEM_TXFIFO_RST_S 31
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-/* DSPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
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-/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
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- receive signals from AXI. Set this bit to reset these FIFO..*/
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-#define DSPI_MEM_RXFIFO_RST (BIT(30))
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-#define DSPI_MEM_RXFIFO_RST_M (BIT(30))
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-#define DSPI_MEM_RXFIFO_RST_V 0x1
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-#define DSPI_MEM_RXFIFO_RST_S 30
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-/* DSPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
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-/*description: Set this bit to write data faster, do not wait write data has been stored in tx_
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-bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
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-in tx_bus_fifo_l2..*/
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-#define DSPI_MEM_FAST_WRITE_EN (BIT(29))
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-#define DSPI_MEM_FAST_WRITE_EN_M (BIT(29))
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-#define DSPI_MEM_FAST_WRITE_EN_V 0x1
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-#define DSPI_MEM_FAST_WRITE_EN_S 29
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-/* DSPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */
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-/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at
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-the same time..*/
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-#define DSPI_MEM_DUAL_RAM_EN (BIT(28))
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-#define DSPI_MEM_DUAL_RAM_EN_M (BIT(28))
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-#define DSPI_MEM_DUAL_RAM_EN_V 0x1
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-#define DSPI_MEM_DUAL_RAM_EN_S 28
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-/* DSPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */
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-/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac
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-cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi
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-ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be ac
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-cessed at the same time..*/
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-#define DSPI_MEM_RAM0_EN (BIT(27))
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-#define DSPI_MEM_RAM0_EN_M (BIT(27))
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-#define DSPI_MEM_RAM0_EN_V 0x1
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-#define DSPI_MEM_RAM0_EN_S 27
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-/* DSPI_MEM_AW_SPLICE_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
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-/*description: Set this bit to enable AXI Write Splice-transfer..*/
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-#define DSPI_MEM_AW_SPLICE_EN (BIT(26))
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-#define DSPI_MEM_AW_SPLICE_EN_M (BIT(26))
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-#define DSPI_MEM_AW_SPLICE_EN_V 0x1
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-#define DSPI_MEM_AW_SPLICE_EN_S 26
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-/* DSPI_MEM_AR_SPLICE_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
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-/*description: Set this bit to enable AXI Read Splice-transfer..*/
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-#define DSPI_MEM_AR_SPLICE_EN (BIT(25))
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-#define DSPI_MEM_AR_SPLICE_EN_M (BIT(25))
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-#define DSPI_MEM_AR_SPLICE_EN_V 0x1
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-#define DSPI_MEM_AR_SPLICE_EN_S 25
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-/* DSPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
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-/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
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- when there is a ECC error in AXI read data. The ECC error information is record
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-ed in SPI_MEM_ECC_ERR_ADDR_REG..*/
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-#define DSPI_MEM_RRESP_ECC_ERR_EN (BIT(24))
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-#define DSPI_MEM_RRESP_ECC_ERR_EN_M (BIT(24))
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-#define DSPI_MEM_RRESP_ECC_ERR_EN_V 0x1
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-#define DSPI_MEM_RRESP_ECC_ERR_EN_S 24
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-/* DSPI_MEM_SPI_AXI_RDATA_BACK_FAST : R/W ;bitpos:[23] ;default: 1'b1 ; */
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-/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R
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-eply AXI read data to AXI bus when all the read data is available..*/
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-#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST (BIT(23))
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-#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST_M (BIT(23))
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-#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST_V 0x1
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-#define DSPI_MEM_SPI_AXI_RDATA_BACK_FAST_S 23
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-/* DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
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-/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
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-#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22))
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-#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_M (BIT(22))
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-#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_V 0x1
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-#define DSPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_S 22
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-/* DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
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-/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl
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-y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/
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-#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21))
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-#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_M (BIT(21))
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-#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_V 0x1
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-#define DSPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_S 21
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-/* DSPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
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-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
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-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
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-ve 3: SPI clock is alwasy on..*/
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-#define DSPI_MEM_CLK_MODE 0x00000003
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-#define DSPI_MEM_CLK_MODE_M ((DSPI_MEM_CLK_MODE_V)<<(DSPI_MEM_CLK_MODE_S))
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-#define DSPI_MEM_CLK_MODE_V 0x3
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-#define DSPI_MEM_CLK_MODE_S 0
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-
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-#define DSPI_MEM_CTRL2_REG (DR_REG_DSPI_MEM_BASE + 0x10)
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-/* DSPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
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-/*description: The spi0_mst_st and spi0_slv_st will be reset..*/
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-#define DSPI_MEM_SYNC_RESET (BIT(31))
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-#define DSPI_MEM_SYNC_RESET_M (BIT(31))
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-#define DSPI_MEM_SYNC_RESET_V 0x1
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-#define DSPI_MEM_SYNC_RESET_S 31
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-/* DSPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
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-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
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-sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
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- clock cycles..*/
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-#define DSPI_MEM_CS_HOLD_DELAY 0x0000003F
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-#define DSPI_MEM_CS_HOLD_DELAY_M ((DSPI_MEM_CS_HOLD_DELAY_V)<<(DSPI_MEM_CS_HOLD_DELAY_S))
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-#define DSPI_MEM_CS_HOLD_DELAY_V 0x3F
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-#define DSPI_MEM_CS_HOLD_DELAY_S 25
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-/* DSPI_MEM_SPLIT_TRANS_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
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-/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans
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-fers when one transfer will cross flash or EXT_RAM page corner, valid no matter
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-whether there is an ECC region or not..*/
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-#define DSPI_MEM_SPLIT_TRANS_EN (BIT(24))
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-#define DSPI_MEM_SPLIT_TRANS_EN_M (BIT(24))
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-#define DSPI_MEM_SPLIT_TRANS_EN_V 0x1
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-#define DSPI_MEM_SPLIT_TRANS_EN_S 24
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-/* DSPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
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-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
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-n accesses flash..*/
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-#define DSPI_MEM_ECC_16TO18_BYTE_EN (BIT(14))
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-#define DSPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14))
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-#define DSPI_MEM_ECC_16TO18_BYTE_EN_V 0x1
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-#define DSPI_MEM_ECC_16TO18_BYTE_EN_S 14
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-/* DSPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */
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-/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w
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-hen accesses flash..*/
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-#define DSPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13))
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-#define DSPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13))
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-#define DSPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1
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-#define DSPI_MEM_ECC_SKIP_PAGE_CORNER_S 13
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-/* DSPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
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-/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
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- mode when accessed flash..*/
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-#define DSPI_MEM_ECC_CS_HOLD_TIME 0x00000007
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-#define DSPI_MEM_ECC_CS_HOLD_TIME_M ((DSPI_MEM_ECC_CS_HOLD_TIME_V)<<(DSPI_MEM_ECC_CS_HOLD_TIME_S))
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-#define DSPI_MEM_ECC_CS_HOLD_TIME_V 0x7
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-#define DSPI_MEM_ECC_CS_HOLD_TIME_S 10
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-/* DSPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
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-/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi
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-th SPI_MEM_CS_HOLD bit..*/
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-#define DSPI_MEM_CS_HOLD_TIME 0x0000001F
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-#define DSPI_MEM_CS_HOLD_TIME_M ((DSPI_MEM_CS_HOLD_TIME_V)<<(DSPI_MEM_CS_HOLD_TIME_S))
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-#define DSPI_MEM_CS_HOLD_TIME_V 0x1F
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-#define DSPI_MEM_CS_HOLD_TIME_S 5
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-/* DSPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
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-/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME
|
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-M_CS_SETUP bit..*/
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-#define DSPI_MEM_CS_SETUP_TIME 0x0000001F
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-#define DSPI_MEM_CS_SETUP_TIME_M ((DSPI_MEM_CS_SETUP_TIME_V)<<(DSPI_MEM_CS_SETUP_TIME_S))
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-#define DSPI_MEM_CS_SETUP_TIME_V 0x1F
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-#define DSPI_MEM_CS_SETUP_TIME_S 0
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-
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-#define DSPI_MEM_CLOCK_REG (DR_REG_DSPI_MEM_BASE + 0x14)
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-/* DSPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
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-/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
|
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- clock..*/
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-#define DSPI_MEM_CLK_EQU_SYSCLK (BIT(31))
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-#define DSPI_MEM_CLK_EQU_SYSCLK_M (BIT(31))
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-#define DSPI_MEM_CLK_EQU_SYSCLK_V 0x1
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-#define DSPI_MEM_CLK_EQU_SYSCLK_S 31
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-/* DSPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
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-/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
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- system/(spi_mem_clkcnt_N+1).*/
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-#define DSPI_MEM_CLKCNT_N 0x000000FF
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-#define DSPI_MEM_CLKCNT_N_M ((DSPI_MEM_CLKCNT_N_V)<<(DSPI_MEM_CLKCNT_N_S))
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-#define DSPI_MEM_CLKCNT_N_V 0xFF
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-#define DSPI_MEM_CLKCNT_N_S 16
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-/* DSPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
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-/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
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-#define DSPI_MEM_CLKCNT_H 0x000000FF
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-#define DSPI_MEM_CLKCNT_H_M ((DSPI_MEM_CLKCNT_H_V)<<(DSPI_MEM_CLKCNT_H_S))
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-#define DSPI_MEM_CLKCNT_H_V 0xFF
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-#define DSPI_MEM_CLKCNT_H_S 8
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-/* DSPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
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-/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
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-#define DSPI_MEM_CLKCNT_L 0x000000FF
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-#define DSPI_MEM_CLKCNT_L_M ((DSPI_MEM_CLKCNT_L_V)<<(DSPI_MEM_CLKCNT_L_S))
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-#define DSPI_MEM_CLKCNT_L_V 0xFF
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-#define DSPI_MEM_CLKCNT_L_S 0
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-
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-#define DSPI_MEM_USER_REG (DR_REG_DSPI_MEM_BASE + 0x18)
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-/* DSPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
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-/*description: This bit enable the dummy phase of an operation..*/
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-#define DSPI_MEM_USR_DUMMY (BIT(29))
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-#define DSPI_MEM_USR_DUMMY_M (BIT(29))
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-#define DSPI_MEM_USR_DUMMY_V 0x1
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-#define DSPI_MEM_USR_DUMMY_S 29
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-/* DSPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
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-/*description: spi clock is disable in dummy phase when the bit is enable..*/
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-#define DSPI_MEM_USR_DUMMY_IDLE (BIT(26))
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-#define DSPI_MEM_USR_DUMMY_IDLE_M (BIT(26))
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-#define DSPI_MEM_USR_DUMMY_IDLE_V 0x1
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-#define DSPI_MEM_USR_DUMMY_IDLE_S 26
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-/* DSPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
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-/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/
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-#define DSPI_MEM_CK_OUT_EDGE (BIT(9))
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-#define DSPI_MEM_CK_OUT_EDGE_M (BIT(9))
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-#define DSPI_MEM_CK_OUT_EDGE_V 0x1
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-#define DSPI_MEM_CK_OUT_EDGE_S 9
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-/* DSPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
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-/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable..*/
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-#define DSPI_MEM_CS_SETUP (BIT(7))
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-#define DSPI_MEM_CS_SETUP_M (BIT(7))
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-#define DSPI_MEM_CS_SETUP_V 0x1
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-#define DSPI_MEM_CS_SETUP_S 7
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-/* DSPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
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-/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable..*/
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-#define DSPI_MEM_CS_HOLD (BIT(6))
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-#define DSPI_MEM_CS_HOLD_M (BIT(6))
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-#define DSPI_MEM_CS_HOLD_V 0x1
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-#define DSPI_MEM_CS_HOLD_S 6
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-
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-#define DSPI_MEM_USER1_REG (DR_REG_DSPI_MEM_BASE + 0x1C)
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-/* DSPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
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-/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
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-#define DSPI_MEM_USR_ADDR_BITLEN 0x0000003F
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-#define DSPI_MEM_USR_ADDR_BITLEN_M ((DSPI_MEM_USR_ADDR_BITLEN_V)<<(DSPI_MEM_USR_ADDR_BITLEN_S))
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-#define DSPI_MEM_USR_ADDR_BITLEN_V 0x3F
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-#define DSPI_MEM_USR_ADDR_BITLEN_S 26
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-/* DSPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */
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-/*description: SPI0 USR_CMD read or write data byte length -1.*/
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-#define DSPI_MEM_USR_DBYTELEN 0x00000007
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-#define DSPI_MEM_USR_DBYTELEN_M ((DSPI_MEM_USR_DBYTELEN_V)<<(DSPI_MEM_USR_DBYTELEN_S))
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-#define DSPI_MEM_USR_DBYTELEN_V 0x7
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-#define DSPI_MEM_USR_DBYTELEN_S 6
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-/* DSPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
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|
-/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
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|
|
-cle_num-1)..*/
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-#define DSPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F
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-#define DSPI_MEM_USR_DUMMY_CYCLELEN_M ((DSPI_MEM_USR_DUMMY_CYCLELEN_V)<<(DSPI_MEM_USR_DUMMY_CYCLELEN_S))
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-#define DSPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F
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-#define DSPI_MEM_USR_DUMMY_CYCLELEN_S 0
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-
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-#define DSPI_MEM_USER2_REG (DR_REG_DSPI_MEM_BASE + 0x20)
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-/* DSPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
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-/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
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-#define DSPI_MEM_USR_COMMAND_BITLEN 0x0000000F
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-#define DSPI_MEM_USR_COMMAND_BITLEN_M ((DSPI_MEM_USR_COMMAND_BITLEN_V)<<(DSPI_MEM_USR_COMMAND_BITLEN_S))
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-#define DSPI_MEM_USR_COMMAND_BITLEN_V 0xF
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-#define DSPI_MEM_USR_COMMAND_BITLEN_S 28
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-/* DSPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
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|
|
-/*description: The value of command..*/
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|
|
-#define DSPI_MEM_USR_COMMAND_VALUE 0x0000FFFF
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-#define DSPI_MEM_USR_COMMAND_VALUE_M ((DSPI_MEM_USR_COMMAND_VALUE_V)<<(DSPI_MEM_USR_COMMAND_VALUE_S))
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-#define DSPI_MEM_USR_COMMAND_VALUE_V 0xFFFF
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-#define DSPI_MEM_USR_COMMAND_VALUE_S 0
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-
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-#define DSPI_MEM_RD_STATUS_REG (DR_REG_DSPI_MEM_BASE + 0x2C)
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-/* DSPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
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|
-/*description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode b
|
|
|
-it..*/
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|
|
-#define DSPI_MEM_WB_MODE 0x000000FF
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-#define DSPI_MEM_WB_MODE_M ((DSPI_MEM_WB_MODE_V)<<(DSPI_MEM_WB_MODE_S))
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-#define DSPI_MEM_WB_MODE_V 0xFF
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-#define DSPI_MEM_WB_MODE_S 16
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-
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-#define DSPI_MEM_MISC_REG (DR_REG_DSPI_MEM_BASE + 0x34)
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-/* DSPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
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|
-/*description: SPI_CS line keep low when the bit is set..*/
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|
-#define DSPI_MEM_CS_KEEP_ACTIVE (BIT(10))
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-#define DSPI_MEM_CS_KEEP_ACTIVE_M (BIT(10))
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-#define DSPI_MEM_CS_KEEP_ACTIVE_V 0x1
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-#define DSPI_MEM_CS_KEEP_ACTIVE_S 10
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-/* DSPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
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-/*description: 1: SPI_CLK line is high when idle 0: spi clk line is low when idle.*/
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-#define DSPI_MEM_CK_IDLE_EDGE (BIT(9))
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-#define DSPI_MEM_CK_IDLE_EDGE_M (BIT(9))
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-#define DSPI_MEM_CK_IDLE_EDGE_V 0x1
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-#define DSPI_MEM_CK_IDLE_EDGE_S 9
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-/* DSPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */
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|
|
-/*description: For SPI0, sram is connected to SUBPINs..*/
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|
-#define DSPI_MEM_SSUB_PIN (BIT(8))
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|
-#define DSPI_MEM_SSUB_PIN_M (BIT(8))
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-#define DSPI_MEM_SSUB_PIN_V 0x1
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-#define DSPI_MEM_SSUB_PIN_S 8
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-/* DSPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */
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|
-/*description: For SPI0, flash is connected to SUBPINs..*/
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-#define DSPI_MEM_FSUB_PIN (BIT(7))
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-#define DSPI_MEM_FSUB_PIN_M (BIT(7))
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-#define DSPI_MEM_FSUB_PIN_V 0x1
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-#define DSPI_MEM_FSUB_PIN_S 7
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-
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-#define DSPI_MEM_CACHE_FCTRL_REG (DR_REG_DSPI_MEM_BASE + 0x3C)
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-/* DSPI_MEM_SPI_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
|
|
|
-/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV
|
|
|
-_ERR will be replied to BRESP/RRESP..*/
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|
|
-#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN (BIT(31))
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|
-#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN_M (BIT(31))
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|
-#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN_V 0x1
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-#define DSPI_MEM_SPI_CLOSE_AXI_INF_EN_S 31
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-/* DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
|
|
|
-/*description: Set this bit to check AXI read/write the same address region..*/
|
|
|
-#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30))
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|
-#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_M (BIT(30))
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|
-#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_V 0x1
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|
-#define DSPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_S 30
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-/* DSPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is
|
|
|
- the same with spi_mem_fread_qio..*/
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|
|
-#define DSPI_MEM_FADDR_QUAD (BIT(8))
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|
-#define DSPI_MEM_FADDR_QUAD_M (BIT(8))
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|
-#define DSPI_MEM_FADDR_QUAD_V 0x1
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|
-#define DSPI_MEM_FADDR_QUAD_S 8
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|
-/* DSPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is th
|
|
|
-e same with spi_mem_fread_qio..*/
|
|
|
-#define DSPI_MEM_FDOUT_QUAD (BIT(7))
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|
-#define DSPI_MEM_FDOUT_QUAD_M (BIT(7))
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|
-#define DSPI_MEM_FDOUT_QUAD_V 0x1
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|
-#define DSPI_MEM_FDOUT_QUAD_S 7
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-/* DSPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the
|
|
|
- same with spi_mem_fread_qio..*/
|
|
|
-#define DSPI_MEM_FDIN_QUAD (BIT(6))
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|
|
-#define DSPI_MEM_FDIN_QUAD_M (BIT(6))
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|
-#define DSPI_MEM_FDIN_QUAD_V 0x1
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|
-#define DSPI_MEM_FDIN_QUAD_S 6
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|
-/* DSPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is
|
|
|
- the same with spi_mem_fread_dio..*/
|
|
|
-#define DSPI_MEM_FADDR_DUAL (BIT(5))
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|
|
-#define DSPI_MEM_FADDR_DUAL_M (BIT(5))
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|
|
-#define DSPI_MEM_FADDR_DUAL_V 0x1
|
|
|
-#define DSPI_MEM_FADDR_DUAL_S 5
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|
|
-/* DSPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
|
|
|
- same with spi_mem_fread_dio..*/
|
|
|
-#define DSPI_MEM_FDOUT_DUAL (BIT(4))
|
|
|
-#define DSPI_MEM_FDOUT_DUAL_M (BIT(4))
|
|
|
-#define DSPI_MEM_FDOUT_DUAL_V 0x1
|
|
|
-#define DSPI_MEM_FDOUT_DUAL_S 4
|
|
|
-/* DSPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
|
|
|
-same with spi_mem_fread_dio..*/
|
|
|
-#define DSPI_MEM_FDIN_DUAL (BIT(3))
|
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|
-#define DSPI_MEM_FDIN_DUAL_M (BIT(3))
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-#define DSPI_MEM_FDIN_DUAL_V 0x1
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-#define DSPI_MEM_FDIN_DUAL_S 3
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-/* DSPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
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-/*description: For SPI0, cache read flash for user define command, 1: enable, 0:disable..*/
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-#define DSPI_MEM_CACHE_FLASH_USR_CMD (BIT(2))
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-#define DSPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2))
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-#define DSPI_MEM_CACHE_FLASH_USR_CMD_V 0x1
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-#define DSPI_MEM_CACHE_FLASH_USR_CMD_S 2
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-/* DSPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
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-/*description: For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable..*/
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-#define DSPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1))
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-#define DSPI_MEM_CACHE_USR_ADDR_4BYTE_M (BIT(1))
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-#define DSPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x1
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-#define DSPI_MEM_CACHE_USR_ADDR_4BYTE_S 1
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-/* DSPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
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-/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/
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-#define DSPI_MEM_AXI_REQ_EN (BIT(0))
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-#define DSPI_MEM_AXI_REQ_EN_M (BIT(0))
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-#define DSPI_MEM_AXI_REQ_EN_V 0x1
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-#define DSPI_MEM_AXI_REQ_EN_S 0
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-
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-#define DSPI_MEM_CACHE_SCTRL_REG (DR_REG_DSPI_MEM_BASE + 0x40)
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-/* DSPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */
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-/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas
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|
-e. The register value shall be (bit_num-1)..*/
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-#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F
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-#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((DSPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(DSPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
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-#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F
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-#define DSPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22
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-/* DSPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
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|
|
-/*description: reserved.*/
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-#define DSPI_MEM_SRAM_OCT (BIT(21))
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-#define DSPI_MEM_SRAM_OCT_M (BIT(21))
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-#define DSPI_MEM_SRAM_OCT_V 0x1
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-#define DSPI_MEM_SRAM_OCT_S 21
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-/* DSPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */
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-/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/
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-#define DSPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20))
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-#define DSPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20))
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-#define DSPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1
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-#define DSPI_MEM_CACHE_SRAM_USR_WCMD_S 20
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-/* DSPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */
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-/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T
|
|
|
-he register value shall be (bit_num-1)..*/
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-#define DSPI_MEM_SRAM_ADDR_BITLEN 0x0000003F
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-#define DSPI_MEM_SRAM_ADDR_BITLEN_M ((DSPI_MEM_SRAM_ADDR_BITLEN_V)<<(DSPI_MEM_SRAM_ADDR_BITLEN_S))
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-#define DSPI_MEM_SRAM_ADDR_BITLEN_V 0x3F
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-#define DSPI_MEM_SRAM_ADDR_BITLEN_S 14
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-/* DSPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */
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|
-/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase
|
|
|
-. The register value shall be (bit_num-1)..*/
|
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-#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F
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|
-#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((DSPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(DSPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
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-#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F
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-#define DSPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6
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-/* DSPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */
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|
|
-/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma
|
|
|
-nd..*/
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|
|
-#define DSPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5))
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|
-#define DSPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5))
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-#define DSPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1
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-#define DSPI_MEM_CACHE_SRAM_USR_RCMD_S 5
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-/* DSPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */
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|
-/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
|
|
|
- operations..*/
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|
|
-#define DSPI_MEM_USR_RD_SRAM_DUMMY (BIT(4))
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|
-#define DSPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4))
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-#define DSPI_MEM_USR_RD_SRAM_DUMMY_V 0x1
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-#define DSPI_MEM_USR_RD_SRAM_DUMMY_S 4
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-/* DSPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ
|
|
|
-e operations..*/
|
|
|
-#define DSPI_MEM_USR_WR_SRAM_DUMMY (BIT(3))
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|
-#define DSPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3))
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-#define DSPI_MEM_USR_WR_SRAM_DUMMY_V 0x1
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-#define DSPI_MEM_USR_WR_SRAM_DUMMY_S 3
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-/* DSPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab
|
|
|
-le.*/
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|
|
-#define DSPI_MEM_USR_SRAM_QIO (BIT(2))
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|
-#define DSPI_MEM_USR_SRAM_QIO_M (BIT(2))
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|
-#define DSPI_MEM_USR_SRAM_QIO_V 0x1
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|
-#define DSPI_MEM_USR_SRAM_QIO_S 2
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|
-/* DSPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab
|
|
|
-le.*/
|
|
|
-#define DSPI_MEM_USR_SRAM_DIO (BIT(1))
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|
|
-#define DSPI_MEM_USR_SRAM_DIO_M (BIT(1))
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|
|
-#define DSPI_MEM_USR_SRAM_DIO_V 0x1
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|
|
-#define DSPI_MEM_USR_SRAM_DIO_S 1
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|
-/* DSPI_MEM_CACHE_USR_SADDR_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en
|
|
|
-able, 0:disable..*/
|
|
|
-#define DSPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0))
|
|
|
-#define DSPI_MEM_CACHE_USR_SADDR_4BYTE_M (BIT(0))
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|
|
-#define DSPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x1
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|
|
-#define DSPI_MEM_CACHE_USR_SADDR_4BYTE_S 0
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|
-
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|
|
-#define DSPI_MEM_SRAM_CMD_REG (DR_REG_DSPI_MEM_BASE + 0x44)
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|
-/* DSPI_SMEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
|
|
|
-/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0
|
|
|
-] are always 1. 0: Others..*/
|
|
|
-#define DSPI_SMEM_DATA_IE_ALWAYS_ON (BIT(31))
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|
|
-#define DSPI_SMEM_DATA_IE_ALWAYS_ON_M (BIT(31))
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|
|
-#define DSPI_SMEM_DATA_IE_ALWAYS_ON_V 0x1
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|
|
-#define DSPI_SMEM_DATA_IE_ALWAYS_ON_S 31
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|
|
-/* DSPI_SMEM_DQS_IE_ALWAYS_ON : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
|
|
-/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar
|
|
|
-e always 1. 0: Others..*/
|
|
|
-#define DSPI_SMEM_DQS_IE_ALWAYS_ON (BIT(30))
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|
|
-#define DSPI_SMEM_DQS_IE_ALWAYS_ON_M (BIT(30))
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|
|
-#define DSPI_SMEM_DQS_IE_ALWAYS_ON_V 0x1
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|
-#define DSPI_SMEM_DQS_IE_ALWAYS_ON_S 30
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-/* DSPI_MEM_SDOUT_HEX : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable..*/
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|
|
-#define DSPI_MEM_SDOUT_HEX (BIT(27))
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|
-#define DSPI_MEM_SDOUT_HEX_M (BIT(27))
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|
-#define DSPI_MEM_SDOUT_HEX_V 0x1
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|
-#define DSPI_MEM_SDOUT_HEX_S 27
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|
-/* DSPI_MEM_SDIN_HEX : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable..*/
|
|
|
-#define DSPI_MEM_SDIN_HEX (BIT(26))
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|
-#define DSPI_MEM_SDIN_HEX_M (BIT(26))
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|
-#define DSPI_MEM_SDIN_HEX_V 0x1
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|
-#define DSPI_MEM_SDIN_HEX_S 26
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|
-/* DSPI_SMEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[25] ;default: 1'b0 ; */
|
|
|
-/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
|
|
|
- the level of SPI_IO[7:0] is output by the MSPI controller..*/
|
|
|
-#define DSPI_SMEM_WDUMMY_ALWAYS_OUT (BIT(25))
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|
-#define DSPI_SMEM_WDUMMY_ALWAYS_OUT_M (BIT(25))
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|
|
-#define DSPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x1
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|
|
-#define DSPI_SMEM_WDUMMY_ALWAYS_OUT_S 25
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|
|
-/* DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W ;bitpos:[24] ;default: 1'b0 ; */
|
|
|
-/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
|
|
|
- the level of SPI_DQS is output by the MSPI controller..*/
|
|
|
-#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24))
|
|
|
-#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(24))
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|
|
-#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1
|
|
|
-#define DSPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24
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|
|
-/* DSPI_MEM_SDUMMY_WOUT : R/W ;bitpos:[23] ;default: 1'b1 ; */
|
|
|
-/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM,
|
|
|
-the signal level of SPI bus is output by the MSPI controller..*/
|
|
|
-#define DSPI_MEM_SDUMMY_WOUT (BIT(23))
|
|
|
-#define DSPI_MEM_SDUMMY_WOUT_M (BIT(23))
|
|
|
-#define DSPI_MEM_SDUMMY_WOUT_V 0x1
|
|
|
-#define DSPI_MEM_SDUMMY_WOUT_S 23
|
|
|
-/* DSPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */
|
|
|
-/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t
|
|
|
-he signal level of SPI bus is output by the MSPI controller..*/
|
|
|
-#define DSPI_MEM_SDUMMY_RIN (BIT(22))
|
|
|
-#define DSPI_MEM_SDUMMY_RIN_M (BIT(22))
|
|
|
-#define DSPI_MEM_SDUMMY_RIN_V 0x1
|
|
|
-#define DSPI_MEM_SDUMMY_RIN_S 22
|
|
|
-/* DSPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/
|
|
|
-#define DSPI_MEM_SCMD_OCT (BIT(21))
|
|
|
-#define DSPI_MEM_SCMD_OCT_M (BIT(21))
|
|
|
-#define DSPI_MEM_SCMD_OCT_V 0x1
|
|
|
-#define DSPI_MEM_SCMD_OCT_S 21
|
|
|
-/* DSPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/
|
|
|
-#define DSPI_MEM_SADDR_OCT (BIT(20))
|
|
|
-#define DSPI_MEM_SADDR_OCT_M (BIT(20))
|
|
|
-#define DSPI_MEM_SADDR_OCT_V 0x1
|
|
|
-#define DSPI_MEM_SADDR_OCT_S 20
|
|
|
-/* DSPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/
|
|
|
-#define DSPI_MEM_SDOUT_OCT (BIT(19))
|
|
|
-#define DSPI_MEM_SDOUT_OCT_M (BIT(19))
|
|
|
-#define DSPI_MEM_SDOUT_OCT_V 0x1
|
|
|
-#define DSPI_MEM_SDOUT_OCT_S 19
|
|
|
-/* DSPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/
|
|
|
-#define DSPI_MEM_SDIN_OCT (BIT(18))
|
|
|
-#define DSPI_MEM_SDIN_OCT_M (BIT(18))
|
|
|
-#define DSPI_MEM_SDIN_OCT_V 0x1
|
|
|
-#define DSPI_MEM_SDIN_OCT_S 18
|
|
|
-/* DSPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit
|
|
|
- is the same with spi_mem_usr_sram_qio..*/
|
|
|
-#define DSPI_MEM_SCMD_QUAD (BIT(17))
|
|
|
-#define DSPI_MEM_SCMD_QUAD_M (BIT(17))
|
|
|
-#define DSPI_MEM_SCMD_QUAD_V 0x1
|
|
|
-#define DSPI_MEM_SCMD_QUAD_S 17
|
|
|
-/* DSPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
|
|
|
- bit is the same with spi_mem_usr_sram_qio..*/
|
|
|
-#define DSPI_MEM_SADDR_QUAD (BIT(16))
|
|
|
-#define DSPI_MEM_SADDR_QUAD_M (BIT(16))
|
|
|
-#define DSPI_MEM_SADDR_QUAD_V 0x1
|
|
|
-#define DSPI_MEM_SADDR_QUAD_S 16
|
|
|
-/* DSPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi
|
|
|
-t is the same with spi_mem_usr_sram_qio..*/
|
|
|
-#define DSPI_MEM_SDOUT_QUAD (BIT(15))
|
|
|
-#define DSPI_MEM_SDOUT_QUAD_M (BIT(15))
|
|
|
-#define DSPI_MEM_SDOUT_QUAD_V 0x1
|
|
|
-#define DSPI_MEM_SDOUT_QUAD_S 15
|
|
|
-/* DSPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit
|
|
|
- is the same with spi_mem_usr_sram_qio..*/
|
|
|
-#define DSPI_MEM_SDIN_QUAD (BIT(14))
|
|
|
-#define DSPI_MEM_SDIN_QUAD_M (BIT(14))
|
|
|
-#define DSPI_MEM_SDIN_QUAD_V 0x1
|
|
|
-#define DSPI_MEM_SDIN_QUAD_S 14
|
|
|
-/* DSPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
|
|
|
- bit is the same with spi_mem_usr_sram_dio..*/
|
|
|
-#define DSPI_MEM_SADDR_DUAL (BIT(12))
|
|
|
-#define DSPI_MEM_SADDR_DUAL_M (BIT(12))
|
|
|
-#define DSPI_MEM_SADDR_DUAL_V 0x1
|
|
|
-#define DSPI_MEM_SADDR_DUAL_S 12
|
|
|
-/* DSPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi
|
|
|
-t is the same with spi_mem_usr_sram_dio..*/
|
|
|
-#define DSPI_MEM_SDOUT_DUAL (BIT(11))
|
|
|
-#define DSPI_MEM_SDOUT_DUAL_M (BIT(11))
|
|
|
-#define DSPI_MEM_SDOUT_DUAL_V 0x1
|
|
|
-#define DSPI_MEM_SDOUT_DUAL_S 11
|
|
|
-/* DSPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */
|
|
|
-/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit
|
|
|
- is the same with spi_mem_usr_sram_dio..*/
|
|
|
-#define DSPI_MEM_SDIN_DUAL (BIT(10))
|
|
|
-#define DSPI_MEM_SDIN_DUAL_M (BIT(10))
|
|
|
-#define DSPI_MEM_SDIN_DUAL_V 0x1
|
|
|
-#define DSPI_MEM_SDIN_DUAL_S 10
|
|
|
-/* DSPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */
|
|
|
-/*description: Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd
|
|
|
-_mode bit..*/
|
|
|
-#define DSPI_MEM_SWB_MODE 0x000000FF
|
|
|
-#define DSPI_MEM_SWB_MODE_M ((DSPI_MEM_SWB_MODE_V)<<(DSPI_MEM_SWB_MODE_S))
|
|
|
-#define DSPI_MEM_SWB_MODE_V 0xFF
|
|
|
-#define DSPI_MEM_SWB_MODE_S 2
|
|
|
-/* DSPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
|
|
|
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
|
|
|
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
|
|
|
-ve 3: SPI clock is always on..*/
|
|
|
-#define DSPI_MEM_SCLK_MODE 0x00000003
|
|
|
-#define DSPI_MEM_SCLK_MODE_M ((DSPI_MEM_SCLK_MODE_V)<<(DSPI_MEM_SCLK_MODE_S))
|
|
|
-#define DSPI_MEM_SCLK_MODE_V 0x3
|
|
|
-#define DSPI_MEM_SCLK_MODE_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_SRAM_DRD_CMD_REG (DR_REG_DSPI_MEM_BASE + 0x48)
|
|
|
-/* DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
|
|
|
-/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for
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- sram. The register value shall be (bit_num-1)..*/
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-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F
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-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
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-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF
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-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28
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-/* DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
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-/*description: For SPI0,When cache mode is enable it is the read command value of command phase
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- for sram..*/
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-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF
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-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
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-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF
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-#define DSPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0
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-
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-#define DSPI_MEM_SRAM_DWR_CMD_REG (DR_REG_DSPI_MEM_BASE + 0x4C)
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-/* DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
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-/*description: For SPI0,When cache mode is enable it is the in bits of command phase for sram.
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- The register value shall be (bit_num-1)..*/
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-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F
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-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
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-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF
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-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28
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-/* DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
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-/*description: For SPI0,When cache mode is enable it is the write command value of command phas
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-e for sram..*/
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-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF
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-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
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-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF
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-#define DSPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0
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-
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-#define DSPI_MEM_SRAM_CLK_REG (DR_REG_DSPI_MEM_BASE + 0x50)
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-/* DSPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
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-/*description: For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c
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-lk is divided from system clock..*/
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-#define DSPI_MEM_SCLK_EQU_SYSCLK (BIT(31))
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-#define DSPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31))
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-#define DSPI_MEM_SCLK_EQU_SYSCLK_V 0x1
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-#define DSPI_MEM_SCLK_EQU_SYSCLK_S 31
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-/* DSPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
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-/*description: For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_c
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-lk frequency is system/(spi_mem_clkcnt_N+1).*/
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-#define DSPI_MEM_SCLKCNT_N 0x000000FF
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-#define DSPI_MEM_SCLKCNT_N_M ((DSPI_MEM_SCLKCNT_N_V)<<(DSPI_MEM_SCLKCNT_N_S))
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-#define DSPI_MEM_SCLKCNT_N_V 0xFF
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-#define DSPI_MEM_SCLKCNT_N_S 16
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-/* DSPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
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-/*description: For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
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-#define DSPI_MEM_SCLKCNT_H 0x000000FF
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-#define DSPI_MEM_SCLKCNT_H_M ((DSPI_MEM_SCLKCNT_H_V)<<(DSPI_MEM_SCLKCNT_H_S))
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-#define DSPI_MEM_SCLKCNT_H_V 0xFF
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-#define DSPI_MEM_SCLKCNT_H_S 8
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-/* DSPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
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-/*description: For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N..*/
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-#define DSPI_MEM_SCLKCNT_L 0x000000FF
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-#define DSPI_MEM_SCLKCNT_L_M ((DSPI_MEM_SCLKCNT_L_V)<<(DSPI_MEM_SCLKCNT_L_S))
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-#define DSPI_MEM_SCLKCNT_L_V 0xFF
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-#define DSPI_MEM_SCLKCNT_L_S 0
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-
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-#define DSPI_MEM_FSM_REG (DR_REG_DSPI_MEM_BASE + 0x54)
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-/* DSPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
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-/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
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-#define DSPI_MEM_LOCK_DELAY_TIME 0x0000001F
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-#define DSPI_MEM_LOCK_DELAY_TIME_M ((DSPI_MEM_LOCK_DELAY_TIME_V)<<(DSPI_MEM_LOCK_DELAY_TIME_S))
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-#define DSPI_MEM_LOCK_DELAY_TIME_V 0x1F
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-#define DSPI_MEM_LOCK_DELAY_TIME_S 7
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-
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-#define DSPI_MEM_INT_ENA_REG (DR_REG_DSPI_MEM_BASE + 0xC0)
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-/* DSPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/
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-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA (BIT(31))
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-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA_M (BIT(31))
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-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA_V 0x1
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-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ENA_S 31
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-/* DSPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/
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-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA (BIT(30))
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-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA_M (BIT(30))
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-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA_V 0x1
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-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ENA_S 30
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-/* DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA (BIT(29))
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M (BIT(29))
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V 0x1
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S 29
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-/* DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA (BIT(28))
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M (BIT(28))
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V 0x1
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S 28
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-/* DSPI_MEM_AXI_WADDR_ERR_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA (BIT(9))
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA_M (BIT(9))
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA_V 0x1
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_ENA_S 9
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-/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8))
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (BIT(8))
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x1
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8
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-/* DSPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7))
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA_M (BIT(7))
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x1
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7
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-/* DSPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
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-#define DSPI_MEM_PMS_REJECT_INT_ENA (BIT(6))
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-#define DSPI_MEM_PMS_REJECT_INT_ENA_M (BIT(6))
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-#define DSPI_MEM_PMS_REJECT_INT_ENA_V 0x1
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-#define DSPI_MEM_PMS_REJECT_INT_ENA_S 6
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-/* DSPI_MEM_ECC_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
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-#define DSPI_MEM_ECC_ERR_INT_ENA (BIT(5))
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-#define DSPI_MEM_ECC_ERR_INT_ENA_M (BIT(5))
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-#define DSPI_MEM_ECC_ERR_INT_ENA_V 0x1
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-#define DSPI_MEM_ECC_ERR_INT_ENA_S 5
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-/* DSPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
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-#define DSPI_MEM_MST_ST_END_INT_ENA (BIT(4))
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-#define DSPI_MEM_MST_ST_END_INT_ENA_M (BIT(4))
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-#define DSPI_MEM_MST_ST_END_INT_ENA_V 0x1
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-#define DSPI_MEM_MST_ST_END_INT_ENA_S 4
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-/* DSPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
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-#define DSPI_MEM_SLV_ST_END_INT_ENA (BIT(3))
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-#define DSPI_MEM_SLV_ST_END_INT_ENA_M (BIT(3))
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-#define DSPI_MEM_SLV_ST_END_INT_ENA_V 0x1
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-#define DSPI_MEM_SLV_ST_END_INT_ENA_S 3
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-
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-#define DSPI_MEM_INT_CLR_REG (DR_REG_DSPI_MEM_BASE + 0xC4)
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-/* DSPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT ;bitpos:[31] ;default: 1'b0 ; */
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-/*description: The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/
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-#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR (BIT(31))
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-#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR_M (BIT(31))
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-#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR_V 0x1
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-#define DSPI_MEM_BUS_FIFO0_UDF_INT_CLR_S 31
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-/* DSPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT ;bitpos:[30] ;default: 1'b0 ; */
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-/*description: The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/
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-#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR (BIT(30))
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-#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR_M (BIT(30))
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-#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR_V 0x1
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-#define DSPI_MEM_BUS_FIFO1_UDF_INT_CLR_S 30
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-/* DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT ;bitpos:[29] ;default: 1'b0 ; */
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-/*description: The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR (BIT(29))
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M (BIT(29))
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V 0x1
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S 29
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-/* DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT ;bitpos:[28] ;default: 1'b0 ; */
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-/*description: The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR (BIT(28))
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M (BIT(28))
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V 0x1
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S 28
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-/* DSPI_MEM_AXI_WADDR_ERR_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
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-/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9))
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR_M (BIT(9))
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x1
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9
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-/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
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-/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8))
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (BIT(8))
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x1
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8
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-/* DSPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
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-/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7))
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR_M (BIT(7))
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x1
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7
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-/* DSPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
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|
-/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
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|
-#define DSPI_MEM_PMS_REJECT_INT_CLR (BIT(6))
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-#define DSPI_MEM_PMS_REJECT_INT_CLR_M (BIT(6))
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-#define DSPI_MEM_PMS_REJECT_INT_CLR_V 0x1
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-#define DSPI_MEM_PMS_REJECT_INT_CLR_S 6
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-/* DSPI_MEM_ECC_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
|
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|
-/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/
|
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|
-#define DSPI_MEM_ECC_ERR_INT_CLR (BIT(5))
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-#define DSPI_MEM_ECC_ERR_INT_CLR_M (BIT(5))
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-#define DSPI_MEM_ECC_ERR_INT_CLR_V 0x1
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-#define DSPI_MEM_ECC_ERR_INT_CLR_S 5
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-/* DSPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
|
|
|
-/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
|
|
|
-#define DSPI_MEM_MST_ST_END_INT_CLR (BIT(4))
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|
-#define DSPI_MEM_MST_ST_END_INT_CLR_M (BIT(4))
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-#define DSPI_MEM_MST_ST_END_INT_CLR_V 0x1
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-#define DSPI_MEM_MST_ST_END_INT_CLR_S 4
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-/* DSPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
|
|
|
-/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
|
|
|
-#define DSPI_MEM_SLV_ST_END_INT_CLR (BIT(3))
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|
-#define DSPI_MEM_SLV_ST_END_INT_CLR_M (BIT(3))
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|
-#define DSPI_MEM_SLV_ST_END_INT_CLR_V 0x1
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|
-#define DSPI_MEM_SLV_ST_END_INT_CLR_S 3
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|
-
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|
-#define DSPI_MEM_INT_RAW_REG (DR_REG_DSPI_MEM_BASE + 0xC8)
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|
-/* DSPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS ;bitpos:[31] ;default: 1'b0 ; */
|
|
|
-/*description: The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO
|
|
|
- is underflow..*/
|
|
|
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW (BIT(31))
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|
|
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW_M (BIT(31))
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|
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW_V 0x1
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|
-#define DSPI_MEM_BUS_FIFO0_UDF_INT_RAW_S 31
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|
|
-/* DSPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS ;bitpos:[30] ;default: 1'b0 ; */
|
|
|
-/*description: The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO
|
|
|
- is underflow..*/
|
|
|
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW (BIT(30))
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|
|
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW_M (BIT(30))
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|
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW_V 0x1
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|
-#define DSPI_MEM_BUS_FIFO1_UDF_INT_RAW_S 30
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|
-/* DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[29] ;default: 1'b0 ; */
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-/*description: The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIF
|
|
|
-O connected to SPI_DQS is overflow..*/
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW (BIT(29))
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M (BIT(29))
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V 0x1
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S 29
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-/* DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[28] ;default: 1'b0 ; */
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-/*description: The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIF
|
|
|
-O connected to SPI_DQS1 is overflow..*/
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW (BIT(28))
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M (BIT(28))
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V 0x1
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S 28
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-/* DSPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
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-/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
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- address is invalid by compared to MMU configuration. 0: Others..*/
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9))
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW_M (BIT(9))
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x1
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9
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-/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
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-/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr
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-ite flash request is received. 0: Others..*/
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8))
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (BIT(8))
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x1
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8
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-/* DSPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
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-/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
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-address is invalid by compared to MMU configuration. 0: Others..*/
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7))
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW_M (BIT(7))
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x1
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7
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-/* DSPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
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-/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access
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|
-is rejected. 0: Others..*/
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-#define DSPI_MEM_PMS_REJECT_INT_RAW (BIT(6))
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-#define DSPI_MEM_PMS_REJECT_INT_RAW_M (BIT(6))
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-#define DSPI_MEM_PMS_REJECT_INT_RAW_V 0x1
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-#define DSPI_MEM_PMS_REJECT_INT_RAW_S 6
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-/* DSPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
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-/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s
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-et and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error
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- times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM
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-. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, t
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-his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
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-ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SP
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-I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
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-of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
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-RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleare
|
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-d, this bit will not be triggered..*/
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-#define DSPI_MEM_ECC_ERR_INT_RAW (BIT(5))
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-#define DSPI_MEM_ECC_ERR_INT_RAW_M (BIT(5))
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-#define DSPI_MEM_ECC_ERR_INT_RAW_V 0x1
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-#define DSPI_MEM_ECC_ERR_INT_RAW_S 5
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-/* DSPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
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-/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st
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-is changed from non idle state to idle state. 0: Others..*/
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-#define DSPI_MEM_MST_ST_END_INT_RAW (BIT(4))
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-#define DSPI_MEM_MST_ST_END_INT_RAW_M (BIT(4))
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-#define DSPI_MEM_MST_ST_END_INT_RAW_V 0x1
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-#define DSPI_MEM_MST_ST_END_INT_RAW_S 4
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-/* DSPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
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-/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st
|
|
|
-is changed from non idle state to idle state. It means that SPI_CS raises high.
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-0: Others.*/
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-#define DSPI_MEM_SLV_ST_END_INT_RAW (BIT(3))
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-#define DSPI_MEM_SLV_ST_END_INT_RAW_M (BIT(3))
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-#define DSPI_MEM_SLV_ST_END_INT_RAW_V 0x1
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-#define DSPI_MEM_SLV_ST_END_INT_RAW_S 3
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-
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-#define DSPI_MEM_INT_ST_REG (DR_REG_DSPI_MEM_BASE + 0xCC)
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-/* DSPI_MEM_BUS_FIFO0_UDF_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
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-/*description: The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt..*/
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-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST (BIT(31))
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-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST_M (BIT(31))
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-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST_V 0x1
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-#define DSPI_MEM_BUS_FIFO0_UDF_INT_ST_S 31
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-/* DSPI_MEM_BUS_FIFO1_UDF_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
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-/*description: The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt..*/
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-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST (BIT(30))
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-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST_M (BIT(30))
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-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST_V 0x1
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-#define DSPI_MEM_BUS_FIFO1_UDF_INT_ST_S 30
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-/* DSPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
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-/*description: The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt..*/
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST (BIT(29))
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST_M (BIT(29))
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST_V 0x1
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-#define DSPI_MEM_DQS1_AFIFO_OVF_INT_ST_S 29
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-/* DSPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
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-/*description: The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt..*/
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST (BIT(28))
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST_M (BIT(28))
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST_V 0x1
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-#define DSPI_MEM_DQS0_AFIFO_OVF_INT_ST_S 28
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-/* DSPI_MEM_AXI_WADDR_ERR_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9))
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_ST_M (BIT(9))
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x1
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-#define DSPI_MEM_AXI_WADDR_ERR_INT_ST_S 9
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-/* DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8))
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (BIT(8))
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x1
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-#define DSPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8
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-/* DSPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
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-/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7))
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_ST_M (BIT(7))
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x1
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-#define DSPI_MEM_AXI_RADDR_ERR_INT_ST_S 7
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-/* DSPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
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-/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
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-#define DSPI_MEM_PMS_REJECT_INT_ST (BIT(6))
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-#define DSPI_MEM_PMS_REJECT_INT_ST_M (BIT(6))
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-#define DSPI_MEM_PMS_REJECT_INT_ST_V 0x1
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-#define DSPI_MEM_PMS_REJECT_INT_ST_S 6
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-/* DSPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
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-/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
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-#define DSPI_MEM_ECC_ERR_INT_ST (BIT(5))
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-#define DSPI_MEM_ECC_ERR_INT_ST_M (BIT(5))
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-#define DSPI_MEM_ECC_ERR_INT_ST_V 0x1
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-#define DSPI_MEM_ECC_ERR_INT_ST_S 5
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-/* DSPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
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-/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
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-#define DSPI_MEM_MST_ST_END_INT_ST (BIT(4))
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-#define DSPI_MEM_MST_ST_END_INT_ST_M (BIT(4))
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-#define DSPI_MEM_MST_ST_END_INT_ST_V 0x1
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-#define DSPI_MEM_MST_ST_END_INT_ST_S 4
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-/* DSPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
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-/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
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-#define DSPI_MEM_SLV_ST_END_INT_ST (BIT(3))
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-#define DSPI_MEM_SLV_ST_END_INT_ST_M (BIT(3))
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-#define DSPI_MEM_SLV_ST_END_INT_ST_V 0x1
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-#define DSPI_MEM_SLV_ST_END_INT_ST_S 3
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-
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-#define DSPI_MEM_DDR_REG (DR_REG_DSPI_MEM_BASE + 0xD4)
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-/* DSPI_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
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-/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
|
|
|
-ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
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|
-#define DSPI_FMEM_HYPERBUS_CA (BIT(30))
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-#define DSPI_FMEM_HYPERBUS_CA_M (BIT(30))
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-#define DSPI_FMEM_HYPERBUS_CA_V 0x1
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-#define DSPI_FMEM_HYPERBUS_CA_S 30
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-/* DSPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
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-/*description: Set this bit to enable octa_ram address out when accesses to flash, which means
|
|
|
-ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
|
|
|
-..*/
|
|
|
-#define DSPI_FMEM_OCTA_RAM_ADDR (BIT(29))
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-#define DSPI_FMEM_OCTA_RAM_ADDR_M (BIT(29))
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-#define DSPI_FMEM_OCTA_RAM_ADDR_V 0x1
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-#define DSPI_FMEM_OCTA_RAM_ADDR_S 29
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-/* DSPI_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
|
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|
-/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
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|
-#define DSPI_FMEM_CLK_DIFF_INV (BIT(28))
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-#define DSPI_FMEM_CLK_DIFF_INV_M (BIT(28))
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-#define DSPI_FMEM_CLK_DIFF_INV_V 0x1
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-#define DSPI_FMEM_CLK_DIFF_INV_S 28
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-/* DSPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
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|
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
|
|
|
-ccesses flash or SPI1 accesses flash or sram..*/
|
|
|
-#define DSPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27))
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-#define DSPI_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27))
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-#define DSPI_FMEM_HYPERBUS_DUMMY_2X_V 0x1
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-#define DSPI_FMEM_HYPERBUS_DUMMY_2X_S 27
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-/* DSPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
|
|
|
-..*/
|
|
|
-#define DSPI_FMEM_DQS_CA_IN (BIT(26))
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-#define DSPI_FMEM_DQS_CA_IN_M (BIT(26))
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|
-#define DSPI_FMEM_DQS_CA_IN_V 0x1
|
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-#define DSPI_FMEM_DQS_CA_IN_S 26
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-/* DSPI_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to enable the differential SPI_CLK#..*/
|
|
|
-#define DSPI_FMEM_CLK_DIFF_EN (BIT(24))
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-#define DSPI_FMEM_CLK_DIFF_EN_M (BIT(24))
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|
-#define DSPI_FMEM_CLK_DIFF_EN_V 0x1
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|
-#define DSPI_FMEM_CLK_DIFF_EN_S 24
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-/* DSPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
|
|
|
-/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
|
|
|
-0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
|
|
|
-SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
|
|
|
-egative edge of SPI_DQS..*/
|
|
|
-#define DSPI_FMEM_DDR_DQS_LOOP (BIT(21))
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|
|
-#define DSPI_FMEM_DDR_DQS_LOOP_M (BIT(21))
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|
-#define DSPI_FMEM_DDR_DQS_LOOP_V 0x1
|
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|
-#define DSPI_FMEM_DDR_DQS_LOOP_S 21
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|
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-/* DSPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
|
|
|
-/*description: The delay number of data strobe which from memory based on SPI clock..*/
|
|
|
-#define DSPI_FMEM_USR_DDR_DQS_THD 0x0000007F
|
|
|
-#define DSPI_FMEM_USR_DDR_DQS_THD_M ((DSPI_FMEM_USR_DDR_DQS_THD_V)<<(DSPI_FMEM_USR_DDR_DQS_THD_S))
|
|
|
-#define DSPI_FMEM_USR_DDR_DQS_THD_V 0x7F
|
|
|
-#define DSPI_FMEM_USR_DDR_DQS_THD_S 14
|
|
|
-/* DSPI_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
|
|
|
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
|
|
|
-accesses to flash..*/
|
|
|
-#define DSPI_FMEM_RX_DDR_MSK_EN (BIT(13))
|
|
|
-#define DSPI_FMEM_RX_DDR_MSK_EN_M (BIT(13))
|
|
|
-#define DSPI_FMEM_RX_DDR_MSK_EN_V 0x1
|
|
|
-#define DSPI_FMEM_RX_DDR_MSK_EN_S 13
|
|
|
-/* DSPI_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
|
|
|
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
|
|
|
- accesses to flash..*/
|
|
|
-#define DSPI_FMEM_TX_DDR_MSK_EN (BIT(12))
|
|
|
-#define DSPI_FMEM_TX_DDR_MSK_EN_M (BIT(12))
|
|
|
-#define DSPI_FMEM_TX_DDR_MSK_EN_V 0x1
|
|
|
-#define DSPI_FMEM_TX_DDR_MSK_EN_S 12
|
|
|
-/* DSPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
|
|
|
-/*description: It is the minimum output data length in the panda device..*/
|
|
|
-#define DSPI_FMEM_OUTMINBYTELEN 0x0000007F
|
|
|
-#define DSPI_FMEM_OUTMINBYTELEN_M ((DSPI_FMEM_OUTMINBYTELEN_V)<<(DSPI_FMEM_OUTMINBYTELEN_S))
|
|
|
-#define DSPI_FMEM_OUTMINBYTELEN_V 0x7F
|
|
|
-#define DSPI_FMEM_OUTMINBYTELEN_S 5
|
|
|
-/* DSPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
|
|
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
|
|
|
-#define DSPI_FMEM_DDR_CMD_DIS (BIT(4))
|
|
|
-#define DSPI_FMEM_DDR_CMD_DIS_M (BIT(4))
|
|
|
-#define DSPI_FMEM_DDR_CMD_DIS_V 0x1
|
|
|
-#define DSPI_FMEM_DDR_CMD_DIS_S 4
|
|
|
-/* DSPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
|
|
-/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
|
|
|
-#define DSPI_FMEM_DDR_WDAT_SWP (BIT(3))
|
|
|
-#define DSPI_FMEM_DDR_WDAT_SWP_M (BIT(3))
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-#define DSPI_FMEM_DDR_WDAT_SWP_V 0x1
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-#define DSPI_FMEM_DDR_WDAT_SWP_S 3
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-/* DSPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
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-/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
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-#define DSPI_FMEM_DDR_RDAT_SWP (BIT(2))
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-#define DSPI_FMEM_DDR_RDAT_SWP_M (BIT(2))
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-#define DSPI_FMEM_DDR_RDAT_SWP_V 0x1
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-#define DSPI_FMEM_DDR_RDAT_SWP_S 2
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-/* DSPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
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-/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
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-#define DSPI_FMEM_VAR_DUMMY (BIT(1))
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-#define DSPI_FMEM_VAR_DUMMY_M (BIT(1))
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-#define DSPI_FMEM_VAR_DUMMY_V 0x1
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-#define DSPI_FMEM_VAR_DUMMY_S 1
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-/* DSPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
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-/*description: 1: in DDR mode, 0 in SDR mode.*/
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-#define DSPI_FMEM_DDR_EN (BIT(0))
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-#define DSPI_FMEM_DDR_EN_M (BIT(0))
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-#define DSPI_FMEM_DDR_EN_V 0x1
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-#define DSPI_FMEM_DDR_EN_S 0
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-
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-#define DSPI_SMEM_DDR_REG (DR_REG_DSPI_MEM_BASE + 0xD8)
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-/* DSPI_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
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-/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
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- means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
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-]}..*/
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-#define DSPI_SMEM_HYPERBUS_CA (BIT(30))
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-#define DSPI_SMEM_HYPERBUS_CA_M (BIT(30))
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-#define DSPI_SMEM_HYPERBUS_CA_V 0x1
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-#define DSPI_SMEM_HYPERBUS_CA_S 30
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-/* DSPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
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-/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
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- means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
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-, 1'b0}..*/
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-#define DSPI_SMEM_OCTA_RAM_ADDR (BIT(29))
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-#define DSPI_SMEM_OCTA_RAM_ADDR_M (BIT(29))
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-#define DSPI_SMEM_OCTA_RAM_ADDR_V 0x1
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-#define DSPI_SMEM_OCTA_RAM_ADDR_S 29
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-/* DSPI_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
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-/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
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-#define DSPI_SMEM_CLK_DIFF_INV (BIT(28))
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-#define DSPI_SMEM_CLK_DIFF_INV_M (BIT(28))
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-#define DSPI_SMEM_CLK_DIFF_INV_V 0x1
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-#define DSPI_SMEM_CLK_DIFF_INV_S 28
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-/* DSPI_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
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-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
|
|
|
-ccesses flash or SPI1 accesses flash or sram..*/
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-#define DSPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27))
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-#define DSPI_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27))
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-#define DSPI_SMEM_HYPERBUS_DUMMY_2X_V 0x1
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-#define DSPI_SMEM_HYPERBUS_DUMMY_2X_S 27
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-/* DSPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
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-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
|
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|
-..*/
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-#define DSPI_SMEM_DQS_CA_IN (BIT(26))
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-#define DSPI_SMEM_DQS_CA_IN_M (BIT(26))
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-#define DSPI_SMEM_DQS_CA_IN_V 0x1
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-#define DSPI_SMEM_DQS_CA_IN_S 26
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-/* DSPI_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
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-/*description: Set this bit to enable the differential SPI_CLK#..*/
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-#define DSPI_SMEM_CLK_DIFF_EN (BIT(24))
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-#define DSPI_SMEM_CLK_DIFF_EN_M (BIT(24))
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-#define DSPI_SMEM_CLK_DIFF_EN_V 0x1
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-#define DSPI_SMEM_CLK_DIFF_EN_S 24
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-/* DSPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
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-/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
|
|
|
-0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
|
|
|
-SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
|
|
|
-egative edge of SPI_DQS..*/
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-#define DSPI_SMEM_DDR_DQS_LOOP (BIT(21))
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-#define DSPI_SMEM_DDR_DQS_LOOP_M (BIT(21))
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-#define DSPI_SMEM_DDR_DQS_LOOP_V 0x1
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-#define DSPI_SMEM_DDR_DQS_LOOP_S 21
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-/* DSPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
|
|
|
-/*description: The delay number of data strobe which from memory based on SPI clock..*/
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|
-#define DSPI_SMEM_USR_DDR_DQS_THD 0x0000007F
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-#define DSPI_SMEM_USR_DDR_DQS_THD_M ((DSPI_SMEM_USR_DDR_DQS_THD_V)<<(DSPI_SMEM_USR_DDR_DQS_THD_S))
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-#define DSPI_SMEM_USR_DDR_DQS_THD_V 0x7F
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-#define DSPI_SMEM_USR_DDR_DQS_THD_S 14
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-/* DSPI_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
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|
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
|
|
|
-accesses to external RAM..*/
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|
|
-#define DSPI_SMEM_RX_DDR_MSK_EN (BIT(13))
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|
-#define DSPI_SMEM_RX_DDR_MSK_EN_M (BIT(13))
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-#define DSPI_SMEM_RX_DDR_MSK_EN_V 0x1
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-#define DSPI_SMEM_RX_DDR_MSK_EN_S 13
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-/* DSPI_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
|
|
|
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
|
|
|
- accesses to external RAM..*/
|
|
|
-#define DSPI_SMEM_TX_DDR_MSK_EN (BIT(12))
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|
-#define DSPI_SMEM_TX_DDR_MSK_EN_M (BIT(12))
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|
-#define DSPI_SMEM_TX_DDR_MSK_EN_V 0x1
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-#define DSPI_SMEM_TX_DDR_MSK_EN_S 12
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-/* DSPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
|
|
|
-/*description: It is the minimum output data length in the DDR psram..*/
|
|
|
-#define DSPI_SMEM_OUTMINBYTELEN 0x0000007F
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|
-#define DSPI_SMEM_OUTMINBYTELEN_M ((DSPI_SMEM_OUTMINBYTELEN_V)<<(DSPI_SMEM_OUTMINBYTELEN_S))
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|
-#define DSPI_SMEM_OUTMINBYTELEN_V 0x7F
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|
-#define DSPI_SMEM_OUTMINBYTELEN_S 5
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-/* DSPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
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|
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
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|
-#define DSPI_SMEM_DDR_CMD_DIS (BIT(4))
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|
-#define DSPI_SMEM_DDR_CMD_DIS_M (BIT(4))
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|
-#define DSPI_SMEM_DDR_CMD_DIS_V 0x1
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|
-#define DSPI_SMEM_DDR_CMD_DIS_S 4
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-/* DSPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
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|
-/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
|
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|
-#define DSPI_SMEM_DDR_WDAT_SWP (BIT(3))
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|
-#define DSPI_SMEM_DDR_WDAT_SWP_M (BIT(3))
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-#define DSPI_SMEM_DDR_WDAT_SWP_V 0x1
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-#define DSPI_SMEM_DDR_WDAT_SWP_S 3
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-/* DSPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
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|
|
-/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
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-#define DSPI_SMEM_DDR_RDAT_SWP (BIT(2))
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-#define DSPI_SMEM_DDR_RDAT_SWP_M (BIT(2))
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-#define DSPI_SMEM_DDR_RDAT_SWP_V 0x1
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-#define DSPI_SMEM_DDR_RDAT_SWP_S 2
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-/* DSPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
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|
|
-/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
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|
-#define DSPI_SMEM_VAR_DUMMY (BIT(1))
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-#define DSPI_SMEM_VAR_DUMMY_M (BIT(1))
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-#define DSPI_SMEM_VAR_DUMMY_V 0x1
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-#define DSPI_SMEM_VAR_DUMMY_S 1
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-/* DSPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
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|
-/*description: 1: in DDR mode, 0 in SDR mode.*/
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|
|
-#define DSPI_SMEM_DDR_EN (BIT(0))
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-#define DSPI_SMEM_DDR_EN_M (BIT(0))
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-#define DSPI_SMEM_DDR_EN_V 0x1
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-#define DSPI_SMEM_DDR_EN_S 0
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-
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-#define DSPI_FMEM_PMS0_ATTR_REG (DR_REG_DSPI_MEM_BASE + 0x100)
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-/* DSPI_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
|
|
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
|
|
|
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
|
|
|
-PMS$n_SIZE_REG..*/
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|
-#define DSPI_FMEM_PMS0_ECC (BIT(2))
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|
-#define DSPI_FMEM_PMS0_ECC_M (BIT(2))
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-#define DSPI_FMEM_PMS0_ECC_V 0x1
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|
-#define DSPI_FMEM_PMS0_ECC_S 2
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-/* DSPI_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_FMEM_PMS0_WR_ATTR (BIT(1))
|
|
|
-#define DSPI_FMEM_PMS0_WR_ATTR_M (BIT(1))
|
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|
-#define DSPI_FMEM_PMS0_WR_ATTR_V 0x1
|
|
|
-#define DSPI_FMEM_PMS0_WR_ATTR_S 1
|
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|
-/* DSPI_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_FMEM_PMS0_RD_ATTR (BIT(0))
|
|
|
-#define DSPI_FMEM_PMS0_RD_ATTR_M (BIT(0))
|
|
|
-#define DSPI_FMEM_PMS0_RD_ATTR_V 0x1
|
|
|
-#define DSPI_FMEM_PMS0_RD_ATTR_S 0
|
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|
-
|
|
|
-#define DSPI_FMEM_PMS1_ATTR_REG (DR_REG_DSPI_MEM_BASE + 0x104)
|
|
|
-/* DSPI_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
|
|
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
|
|
|
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
|
|
|
-PMS$n_SIZE_REG..*/
|
|
|
-#define DSPI_FMEM_PMS1_ECC (BIT(2))
|
|
|
-#define DSPI_FMEM_PMS1_ECC_M (BIT(2))
|
|
|
-#define DSPI_FMEM_PMS1_ECC_V 0x1
|
|
|
-#define DSPI_FMEM_PMS1_ECC_S 2
|
|
|
-/* DSPI_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_FMEM_PMS1_WR_ATTR (BIT(1))
|
|
|
-#define DSPI_FMEM_PMS1_WR_ATTR_M (BIT(1))
|
|
|
-#define DSPI_FMEM_PMS1_WR_ATTR_V 0x1
|
|
|
-#define DSPI_FMEM_PMS1_WR_ATTR_S 1
|
|
|
-/* DSPI_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_FMEM_PMS1_RD_ATTR (BIT(0))
|
|
|
-#define DSPI_FMEM_PMS1_RD_ATTR_M (BIT(0))
|
|
|
-#define DSPI_FMEM_PMS1_RD_ATTR_V 0x1
|
|
|
-#define DSPI_FMEM_PMS1_RD_ATTR_S 0
|
|
|
-
|
|
|
-#define DSPI_FMEM_PMS2_ATTR_REG (DR_REG_DSPI_MEM_BASE + 0x108)
|
|
|
-/* DSPI_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
|
|
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
|
|
|
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
|
|
|
-PMS$n_SIZE_REG..*/
|
|
|
-#define DSPI_FMEM_PMS2_ECC (BIT(2))
|
|
|
-#define DSPI_FMEM_PMS2_ECC_M (BIT(2))
|
|
|
-#define DSPI_FMEM_PMS2_ECC_V 0x1
|
|
|
-#define DSPI_FMEM_PMS2_ECC_S 2
|
|
|
-/* DSPI_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_FMEM_PMS2_WR_ATTR (BIT(1))
|
|
|
-#define DSPI_FMEM_PMS2_WR_ATTR_M (BIT(1))
|
|
|
-#define DSPI_FMEM_PMS2_WR_ATTR_V 0x1
|
|
|
-#define DSPI_FMEM_PMS2_WR_ATTR_S 1
|
|
|
-/* DSPI_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_FMEM_PMS2_RD_ATTR (BIT(0))
|
|
|
-#define DSPI_FMEM_PMS2_RD_ATTR_M (BIT(0))
|
|
|
-#define DSPI_FMEM_PMS2_RD_ATTR_V 0x1
|
|
|
-#define DSPI_FMEM_PMS2_RD_ATTR_S 0
|
|
|
-
|
|
|
-#define DSPI_FMEM_PMS3_ATTR_REG (DR_REG_DSPI_MEM_BASE + 0x10C)
|
|
|
-/* DSPI_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
|
|
-/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
|
|
|
- PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
|
|
|
-PMS$n_SIZE_REG..*/
|
|
|
-#define DSPI_FMEM_PMS3_ECC (BIT(2))
|
|
|
-#define DSPI_FMEM_PMS3_ECC_M (BIT(2))
|
|
|
-#define DSPI_FMEM_PMS3_ECC_V 0x1
|
|
|
-#define DSPI_FMEM_PMS3_ECC_S 2
|
|
|
-/* DSPI_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_FMEM_PMS3_WR_ATTR (BIT(1))
|
|
|
-#define DSPI_FMEM_PMS3_WR_ATTR_M (BIT(1))
|
|
|
-#define DSPI_FMEM_PMS3_WR_ATTR_V 0x1
|
|
|
-#define DSPI_FMEM_PMS3_WR_ATTR_S 1
|
|
|
-/* DSPI_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_FMEM_PMS3_RD_ATTR (BIT(0))
|
|
|
-#define DSPI_FMEM_PMS3_RD_ATTR_M (BIT(0))
|
|
|
-#define DSPI_FMEM_PMS3_RD_ATTR_V 0x1
|
|
|
-#define DSPI_FMEM_PMS3_RD_ATTR_S 0
|
|
|
-
|
|
|
-#define DSPI_FMEM_PMS0_ADDR_REG (DR_REG_DSPI_MEM_BASE + 0x110)
|
|
|
-/* DSPI_FMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
|
|
|
-/*description: SPI1 flash PMS section $n start address value.*/
|
|
|
-#define DSPI_FMEM_PMS0_ADDR_S 0x03FFFFFF
|
|
|
-#define DSPI_FMEM_PMS0_ADDR_S_M ((DSPI_FMEM_PMS0_ADDR_S_V)<<(DSPI_FMEM_PMS0_ADDR_S_S))
|
|
|
-#define DSPI_FMEM_PMS0_ADDR_S_V 0x3FFFFFF
|
|
|
-#define DSPI_FMEM_PMS0_ADDR_S_S 0
|
|
|
-
|
|
|
-#define DSPI_FMEM_PMS1_ADDR_REG (DR_REG_DSPI_MEM_BASE + 0x114)
|
|
|
-/* DSPI_FMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
|
|
|
-/*description: SPI1 flash PMS section $n start address value.*/
|
|
|
-#define DSPI_FMEM_PMS1_ADDR_S 0x03FFFFFF
|
|
|
-#define DSPI_FMEM_PMS1_ADDR_S_M ((DSPI_FMEM_PMS1_ADDR_S_V)<<(DSPI_FMEM_PMS1_ADDR_S_S))
|
|
|
-#define DSPI_FMEM_PMS1_ADDR_S_V 0x3FFFFFF
|
|
|
-#define DSPI_FMEM_PMS1_ADDR_S_S 0
|
|
|
-
|
|
|
-#define DSPI_FMEM_PMS2_ADDR_REG (DR_REG_DSPI_MEM_BASE + 0x118)
|
|
|
-/* DSPI_FMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
|
|
|
-/*description: SPI1 flash PMS section $n start address value.*/
|
|
|
-#define DSPI_FMEM_PMS2_ADDR_S 0x03FFFFFF
|
|
|
-#define DSPI_FMEM_PMS2_ADDR_S_M ((DSPI_FMEM_PMS2_ADDR_S_V)<<(DSPI_FMEM_PMS2_ADDR_S_S))
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-#define DSPI_FMEM_PMS2_ADDR_S_V 0x3FFFFFF
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-#define DSPI_FMEM_PMS2_ADDR_S_S 0
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-
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-#define DSPI_FMEM_PMS3_ADDR_REG (DR_REG_DSPI_MEM_BASE + 0x11C)
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-/* DSPI_FMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
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-/*description: SPI1 flash PMS section $n start address value.*/
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-#define DSPI_FMEM_PMS3_ADDR_S 0x03FFFFFF
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-#define DSPI_FMEM_PMS3_ADDR_S_M ((DSPI_FMEM_PMS3_ADDR_S_V)<<(DSPI_FMEM_PMS3_ADDR_S_S))
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-#define DSPI_FMEM_PMS3_ADDR_S_V 0x3FFFFFF
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-#define DSPI_FMEM_PMS3_ADDR_S_S 0
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-
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-#define DSPI_FMEM_PMS0_SIZE_REG (DR_REG_DSPI_MEM_BASE + 0x120)
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-/* DSPI_FMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
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-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
|
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-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
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-#define DSPI_FMEM_PMS0_SIZE 0x00003FFF
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-#define DSPI_FMEM_PMS0_SIZE_M ((DSPI_FMEM_PMS0_SIZE_V)<<(DSPI_FMEM_PMS0_SIZE_S))
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-#define DSPI_FMEM_PMS0_SIZE_V 0x3FFF
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-#define DSPI_FMEM_PMS0_SIZE_S 0
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-
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-#define DSPI_FMEM_PMS1_SIZE_REG (DR_REG_DSPI_MEM_BASE + 0x124)
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-/* DSPI_FMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
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|
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-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
|
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-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
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-#define DSPI_FMEM_PMS1_SIZE 0x00003FFF
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-#define DSPI_FMEM_PMS1_SIZE_M ((DSPI_FMEM_PMS1_SIZE_V)<<(DSPI_FMEM_PMS1_SIZE_S))
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-#define DSPI_FMEM_PMS1_SIZE_V 0x3FFF
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-#define DSPI_FMEM_PMS1_SIZE_S 0
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-
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-#define DSPI_FMEM_PMS2_SIZE_REG (DR_REG_DSPI_MEM_BASE + 0x128)
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-/* DSPI_FMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
|
|
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-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
|
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-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
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-#define DSPI_FMEM_PMS2_SIZE 0x00003FFF
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-#define DSPI_FMEM_PMS2_SIZE_M ((DSPI_FMEM_PMS2_SIZE_V)<<(DSPI_FMEM_PMS2_SIZE_S))
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-#define DSPI_FMEM_PMS2_SIZE_V 0x3FFF
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-#define DSPI_FMEM_PMS2_SIZE_S 0
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-
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-#define DSPI_FMEM_PMS3_SIZE_REG (DR_REG_DSPI_MEM_BASE + 0x12C)
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-/* DSPI_FMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
|
|
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-/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
|
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-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
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-#define DSPI_FMEM_PMS3_SIZE 0x00003FFF
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-#define DSPI_FMEM_PMS3_SIZE_M ((DSPI_FMEM_PMS3_SIZE_V)<<(DSPI_FMEM_PMS3_SIZE_S))
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-#define DSPI_FMEM_PMS3_SIZE_V 0x3FFF
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-#define DSPI_FMEM_PMS3_SIZE_S 0
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-
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-#define DSPI_SMEM_PMS0_ATTR_REG (DR_REG_DSPI_MEM_BASE + 0x130)
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-/* DSPI_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
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|
|
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
|
|
|
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
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- and SPI_SMEM_PMS$n_SIZE_REG..*/
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-#define DSPI_SMEM_PMS0_ECC (BIT(2))
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-#define DSPI_SMEM_PMS0_ECC_M (BIT(2))
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-#define DSPI_SMEM_PMS0_ECC_V 0x1
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-#define DSPI_SMEM_PMS0_ECC_S 2
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-/* DSPI_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
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-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
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-#define DSPI_SMEM_PMS0_WR_ATTR (BIT(1))
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-#define DSPI_SMEM_PMS0_WR_ATTR_M (BIT(1))
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-#define DSPI_SMEM_PMS0_WR_ATTR_V 0x1
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-#define DSPI_SMEM_PMS0_WR_ATTR_S 1
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-/* DSPI_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
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-#define DSPI_SMEM_PMS0_RD_ATTR (BIT(0))
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-#define DSPI_SMEM_PMS0_RD_ATTR_M (BIT(0))
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-#define DSPI_SMEM_PMS0_RD_ATTR_V 0x1
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-#define DSPI_SMEM_PMS0_RD_ATTR_S 0
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-
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-#define DSPI_SMEM_PMS1_ATTR_REG (DR_REG_DSPI_MEM_BASE + 0x134)
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-/* DSPI_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
|
|
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
|
|
|
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
|
|
|
- and SPI_SMEM_PMS$n_SIZE_REG..*/
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-#define DSPI_SMEM_PMS1_ECC (BIT(2))
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-#define DSPI_SMEM_PMS1_ECC_M (BIT(2))
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-#define DSPI_SMEM_PMS1_ECC_V 0x1
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-#define DSPI_SMEM_PMS1_ECC_S 2
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-/* DSPI_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
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|
-#define DSPI_SMEM_PMS1_WR_ATTR (BIT(1))
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-#define DSPI_SMEM_PMS1_WR_ATTR_M (BIT(1))
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|
-#define DSPI_SMEM_PMS1_WR_ATTR_V 0x1
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|
-#define DSPI_SMEM_PMS1_WR_ATTR_S 1
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|
|
-/* DSPI_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_SMEM_PMS1_RD_ATTR (BIT(0))
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|
-#define DSPI_SMEM_PMS1_RD_ATTR_M (BIT(0))
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|
-#define DSPI_SMEM_PMS1_RD_ATTR_V 0x1
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|
-#define DSPI_SMEM_PMS1_RD_ATTR_S 0
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|
-
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-#define DSPI_SMEM_PMS2_ATTR_REG (DR_REG_DSPI_MEM_BASE + 0x138)
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|
|
-/* DSPI_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
|
|
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
|
|
|
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
|
|
|
- and SPI_SMEM_PMS$n_SIZE_REG..*/
|
|
|
-#define DSPI_SMEM_PMS2_ECC (BIT(2))
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|
-#define DSPI_SMEM_PMS2_ECC_M (BIT(2))
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|
-#define DSPI_SMEM_PMS2_ECC_V 0x1
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-#define DSPI_SMEM_PMS2_ECC_S 2
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-/* DSPI_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_SMEM_PMS2_WR_ATTR (BIT(1))
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|
-#define DSPI_SMEM_PMS2_WR_ATTR_M (BIT(1))
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|
-#define DSPI_SMEM_PMS2_WR_ATTR_V 0x1
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-#define DSPI_SMEM_PMS2_WR_ATTR_S 1
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|
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-/* DSPI_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_SMEM_PMS2_RD_ATTR (BIT(0))
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|
-#define DSPI_SMEM_PMS2_RD_ATTR_M (BIT(0))
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-#define DSPI_SMEM_PMS2_RD_ATTR_V 0x1
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-#define DSPI_SMEM_PMS2_RD_ATTR_S 0
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-
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-#define DSPI_SMEM_PMS3_ATTR_REG (DR_REG_DSPI_MEM_BASE + 0x13C)
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|
-/* DSPI_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
|
|
-/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
|
|
|
-e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
|
|
|
- and SPI_SMEM_PMS$n_SIZE_REG..*/
|
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|
-#define DSPI_SMEM_PMS3_ECC (BIT(2))
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|
-#define DSPI_SMEM_PMS3_ECC_M (BIT(2))
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|
-#define DSPI_SMEM_PMS3_ECC_V 0x1
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|
-#define DSPI_SMEM_PMS3_ECC_S 2
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|
|
-/* DSPI_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_SMEM_PMS3_WR_ATTR (BIT(1))
|
|
|
-#define DSPI_SMEM_PMS3_WR_ATTR_M (BIT(1))
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|
|
-#define DSPI_SMEM_PMS3_WR_ATTR_V 0x1
|
|
|
-#define DSPI_SMEM_PMS3_WR_ATTR_S 1
|
|
|
-/* DSPI_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
|
|
|
-/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/
|
|
|
-#define DSPI_SMEM_PMS3_RD_ATTR (BIT(0))
|
|
|
-#define DSPI_SMEM_PMS3_RD_ATTR_M (BIT(0))
|
|
|
-#define DSPI_SMEM_PMS3_RD_ATTR_V 0x1
|
|
|
-#define DSPI_SMEM_PMS3_RD_ATTR_S 0
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|
-
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|
|
-#define DSPI_SMEM_PMS0_ADDR_REG (DR_REG_DSPI_MEM_BASE + 0x140)
|
|
|
-/* DSPI_SMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
|
|
|
-/*description: SPI1 external RAM PMS section $n start address value.*/
|
|
|
-#define DSPI_SMEM_PMS0_ADDR_S 0x03FFFFFF
|
|
|
-#define DSPI_SMEM_PMS0_ADDR_S_M ((DSPI_SMEM_PMS0_ADDR_S_V)<<(DSPI_SMEM_PMS0_ADDR_S_S))
|
|
|
-#define DSPI_SMEM_PMS0_ADDR_S_V 0x3FFFFFF
|
|
|
-#define DSPI_SMEM_PMS0_ADDR_S_S 0
|
|
|
-
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|
|
-#define DSPI_SMEM_PMS1_ADDR_REG (DR_REG_DSPI_MEM_BASE + 0x144)
|
|
|
-/* DSPI_SMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
|
|
|
-/*description: SPI1 external RAM PMS section $n start address value.*/
|
|
|
-#define DSPI_SMEM_PMS1_ADDR_S 0x03FFFFFF
|
|
|
-#define DSPI_SMEM_PMS1_ADDR_S_M ((DSPI_SMEM_PMS1_ADDR_S_V)<<(DSPI_SMEM_PMS1_ADDR_S_S))
|
|
|
-#define DSPI_SMEM_PMS1_ADDR_S_V 0x3FFFFFF
|
|
|
-#define DSPI_SMEM_PMS1_ADDR_S_S 0
|
|
|
-
|
|
|
-#define DSPI_SMEM_PMS2_ADDR_REG (DR_REG_DSPI_MEM_BASE + 0x148)
|
|
|
-/* DSPI_SMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
|
|
|
-/*description: SPI1 external RAM PMS section $n start address value.*/
|
|
|
-#define DSPI_SMEM_PMS2_ADDR_S 0x03FFFFFF
|
|
|
-#define DSPI_SMEM_PMS2_ADDR_S_M ((DSPI_SMEM_PMS2_ADDR_S_V)<<(DSPI_SMEM_PMS2_ADDR_S_S))
|
|
|
-#define DSPI_SMEM_PMS2_ADDR_S_V 0x3FFFFFF
|
|
|
-#define DSPI_SMEM_PMS2_ADDR_S_S 0
|
|
|
-
|
|
|
-#define DSPI_SMEM_PMS3_ADDR_REG (DR_REG_DSPI_MEM_BASE + 0x14C)
|
|
|
-/* DSPI_SMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
|
|
|
-/*description: SPI1 external RAM PMS section $n start address value.*/
|
|
|
-#define DSPI_SMEM_PMS3_ADDR_S 0x03FFFFFF
|
|
|
-#define DSPI_SMEM_PMS3_ADDR_S_M ((DSPI_SMEM_PMS3_ADDR_S_V)<<(DSPI_SMEM_PMS3_ADDR_S_S))
|
|
|
-#define DSPI_SMEM_PMS3_ADDR_S_V 0x3FFFFFF
|
|
|
-#define DSPI_SMEM_PMS3_ADDR_S_S 0
|
|
|
-
|
|
|
-#define DSPI_SMEM_PMS0_SIZE_REG (DR_REG_DSPI_MEM_BASE + 0x150)
|
|
|
-/* DSPI_SMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
|
|
|
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
|
|
|
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
|
|
|
-#define DSPI_SMEM_PMS0_SIZE 0x00003FFF
|
|
|
-#define DSPI_SMEM_PMS0_SIZE_M ((DSPI_SMEM_PMS0_SIZE_V)<<(DSPI_SMEM_PMS0_SIZE_S))
|
|
|
-#define DSPI_SMEM_PMS0_SIZE_V 0x3FFF
|
|
|
-#define DSPI_SMEM_PMS0_SIZE_S 0
|
|
|
-
|
|
|
-#define DSPI_SMEM_PMS1_SIZE_REG (DR_REG_DSPI_MEM_BASE + 0x154)
|
|
|
-/* DSPI_SMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
|
|
|
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
|
|
|
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
|
|
|
-#define DSPI_SMEM_PMS1_SIZE 0x00003FFF
|
|
|
-#define DSPI_SMEM_PMS1_SIZE_M ((DSPI_SMEM_PMS1_SIZE_V)<<(DSPI_SMEM_PMS1_SIZE_S))
|
|
|
-#define DSPI_SMEM_PMS1_SIZE_V 0x3FFF
|
|
|
-#define DSPI_SMEM_PMS1_SIZE_S 0
|
|
|
-
|
|
|
-#define DSPI_SMEM_PMS2_SIZE_REG (DR_REG_DSPI_MEM_BASE + 0x158)
|
|
|
-/* DSPI_SMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
|
|
|
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
|
|
|
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
|
|
|
-#define DSPI_SMEM_PMS2_SIZE 0x00003FFF
|
|
|
-#define DSPI_SMEM_PMS2_SIZE_M ((DSPI_SMEM_PMS2_SIZE_V)<<(DSPI_SMEM_PMS2_SIZE_S))
|
|
|
-#define DSPI_SMEM_PMS2_SIZE_V 0x3FFF
|
|
|
-#define DSPI_SMEM_PMS2_SIZE_S 0
|
|
|
-
|
|
|
-#define DSPI_SMEM_PMS3_SIZE_REG (DR_REG_DSPI_MEM_BASE + 0x15C)
|
|
|
-/* DSPI_SMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
|
|
|
-/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
|
|
|
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
|
|
|
-#define DSPI_SMEM_PMS3_SIZE 0x00003FFF
|
|
|
-#define DSPI_SMEM_PMS3_SIZE_M ((DSPI_SMEM_PMS3_SIZE_V)<<(DSPI_SMEM_PMS3_SIZE_S))
|
|
|
-#define DSPI_SMEM_PMS3_SIZE_V 0x3FFF
|
|
|
-#define DSPI_SMEM_PMS3_SIZE_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_PMS_REJECT_REG (DR_REG_DSPI_MEM_BASE + 0x164)
|
|
|
-/* DSPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */
|
|
|
-/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
|
|
|
- error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
|
|
|
-#define DSPI_MEM_PMS_IVD (BIT(31))
|
|
|
-#define DSPI_MEM_PMS_IVD_M (BIT(31))
|
|
|
-#define DSPI_MEM_PMS_IVD_V 0x1
|
|
|
-#define DSPI_MEM_PMS_IVD_S 31
|
|
|
-/* DSPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */
|
|
|
-/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It
|
|
|
- is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
|
|
|
-#define DSPI_MEM_PMS_MULTI_HIT (BIT(30))
|
|
|
-#define DSPI_MEM_PMS_MULTI_HIT_M (BIT(30))
|
|
|
-#define DSPI_MEM_PMS_MULTI_HIT_V 0x1
|
|
|
-#define DSPI_MEM_PMS_MULTI_HIT_S 30
|
|
|
-/* DSPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
|
|
|
-/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_M
|
|
|
-EM_PMS_REJECT_INT_CLR bit is set..*/
|
|
|
-#define DSPI_MEM_PMS_ST (BIT(29))
|
|
|
-#define DSPI_MEM_PMS_ST_M (BIT(29))
|
|
|
-#define DSPI_MEM_PMS_ST_V 0x1
|
|
|
-#define DSPI_MEM_PMS_ST_S 29
|
|
|
-/* DSPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */
|
|
|
-/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI
|
|
|
-_MEM_PMS_REJECT_INT_CLR bit is set..*/
|
|
|
-#define DSPI_MEM_PMS_LD (BIT(28))
|
|
|
-#define DSPI_MEM_PMS_LD_M (BIT(28))
|
|
|
-#define DSPI_MEM_PMS_LD_V 0x1
|
|
|
-#define DSPI_MEM_PMS_LD_S 28
|
|
|
-/* DSPI_MEM_PM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to enable SPI0/1 transfer permission control function..*/
|
|
|
-#define DSPI_MEM_PM_EN (BIT(26))
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|
-#define DSPI_MEM_PM_EN_M (BIT(26))
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-#define DSPI_MEM_PM_EN_V 0x1
|
|
|
-#define DSPI_MEM_PM_EN_S 26
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|
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-/* DSPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
|
|
|
-/*description: This bits show the first SPI1 access error address. It is cleared by when SPI_M
|
|
|
-EM_PMS_REJECT_INT_CLR bit is set..*/
|
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-#define DSPI_MEM_REJECT_ADDR 0x03FFFFFF
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-#define DSPI_MEM_REJECT_ADDR_M ((DSPI_MEM_REJECT_ADDR_V)<<(DSPI_MEM_REJECT_ADDR_S))
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-#define DSPI_MEM_REJECT_ADDR_V 0x3FFFFFF
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-#define DSPI_MEM_REJECT_ADDR_S 0
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|
-
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-#define DSPI_MEM_ECC_CTRL_REG (DR_REG_DSPI_MEM_BASE + 0x168)
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-/* DSPI_MEM_ECC_ERR_BITS : R/SS/WTC ;bitpos:[31:25] ;default: 7'd0 ; */
|
|
|
-/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding
|
|
|
- to byte 0 bit 0 to byte 15 bit 7).*/
|
|
|
-#define DSPI_MEM_ECC_ERR_BITS 0x0000007F
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-#define DSPI_MEM_ECC_ERR_BITS_M ((DSPI_MEM_ECC_ERR_BITS_V)<<(DSPI_MEM_ECC_ERR_BITS_S))
|
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-#define DSPI_MEM_ECC_ERR_BITS_V 0x7F
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-#define DSPI_MEM_ECC_ERR_BITS_S 25
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-/* DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
|
|
|
-/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd
|
|
|
-ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD
|
|
|
-R record the first ECC error information..*/
|
|
|
-#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24))
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|
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-#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (BIT(24))
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-#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x1
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-#define DSPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24
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-/* DSPI_MEM_USR_ECC_ADDR_EN : R/W ;bitpos:[21] ;default: 1'd0 ; */
|
|
|
-/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/
|
|
|
-#define DSPI_MEM_USR_ECC_ADDR_EN (BIT(21))
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-#define DSPI_MEM_USR_ECC_ADDR_EN_M (BIT(21))
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-#define DSPI_MEM_USR_ECC_ADDR_EN_V 0x1
|
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-#define DSPI_MEM_USR_ECC_ADDR_EN_S 21
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|
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-/* DSPI_FMEM_ECC_ADDR_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
|
|
|
-/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
|
|
|
-he ECC region or non-ECC region of flash. If there is no ECC region in flash, th
|
|
|
-is bit should be 0. Otherwise, this bit should be 1..*/
|
|
|
-#define DSPI_FMEM_ECC_ADDR_EN (BIT(20))
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|
-#define DSPI_FMEM_ECC_ADDR_EN_M (BIT(20))
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|
|
-#define DSPI_FMEM_ECC_ADDR_EN_V 0x1
|
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|
-#define DSPI_FMEM_ECC_ADDR_EN_S 20
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|
|
-/* DSPI_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
|
|
|
-/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
|
|
|
-1024 bytes. 3: 2048 bytes..*/
|
|
|
-#define DSPI_FMEM_PAGE_SIZE 0x00000003
|
|
|
-#define DSPI_FMEM_PAGE_SIZE_M ((DSPI_FMEM_PAGE_SIZE_V)<<(DSPI_FMEM_PAGE_SIZE_S))
|
|
|
-#define DSPI_FMEM_PAGE_SIZE_V 0x3
|
|
|
-#define DSPI_FMEM_PAGE_SIZE_S 18
|
|
|
-/* DSPI_FMEM_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
|
|
|
-h..*/
|
|
|
-#define DSPI_FMEM_ECC_ERR_INT_EN (BIT(17))
|
|
|
-#define DSPI_FMEM_ECC_ERR_INT_EN_M (BIT(17))
|
|
|
-#define DSPI_FMEM_ECC_ERR_INT_EN_V 0x1
|
|
|
-#define DSPI_FMEM_ECC_ERR_INT_EN_S 17
|
|
|
-/* DSPI_FMEM_ECC_ERR_INT_NUM : R/W ;bitpos:[16:11] ;default: 6'd10 ; */
|
|
|
-/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
|
|
|
-upt..*/
|
|
|
-#define DSPI_FMEM_ECC_ERR_INT_NUM 0x0000003F
|
|
|
-#define DSPI_FMEM_ECC_ERR_INT_NUM_M ((DSPI_FMEM_ECC_ERR_INT_NUM_V)<<(DSPI_FMEM_ECC_ERR_INT_NUM_S))
|
|
|
-#define DSPI_FMEM_ECC_ERR_INT_NUM_V 0x3F
|
|
|
-#define DSPI_FMEM_ECC_ERR_INT_NUM_S 11
|
|
|
-
|
|
|
-#define DSPI_MEM_ECC_ERR_ADDR_REG (DR_REG_DSPI_MEM_BASE + 0x16C)
|
|
|
-/* DSPI_MEM_ECC_ERR_CNT : R/SS/WTC ;bitpos:[31:26] ;default: 6'd0 ; */
|
|
|
-/*description: This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_
|
|
|
-ECC_ERR_INT_CLR bit is set..*/
|
|
|
-#define DSPI_MEM_ECC_ERR_CNT 0x0000003F
|
|
|
-#define DSPI_MEM_ECC_ERR_CNT_M ((DSPI_MEM_ECC_ERR_CNT_V)<<(DSPI_MEM_ECC_ERR_CNT_S))
|
|
|
-#define DSPI_MEM_ECC_ERR_CNT_V 0x3F
|
|
|
-#define DSPI_MEM_ECC_ERR_CNT_S 26
|
|
|
-/* DSPI_MEM_ECC_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
|
|
|
-/*description: This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_
|
|
|
-ECC_ERR_INT_CLR bit is set..*/
|
|
|
-#define DSPI_MEM_ECC_ERR_ADDR 0x03FFFFFF
|
|
|
-#define DSPI_MEM_ECC_ERR_ADDR_M ((DSPI_MEM_ECC_ERR_ADDR_V)<<(DSPI_MEM_ECC_ERR_ADDR_S))
|
|
|
-#define DSPI_MEM_ECC_ERR_ADDR_V 0x3FFFFFF
|
|
|
-#define DSPI_MEM_ECC_ERR_ADDR_S 0
|
|
|
-
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|
|
-#define DSPI_MEM_AXI_ERR_ADDR_REG (DR_REG_DSPI_MEM_BASE + 0x170)
|
|
|
-/* DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
|
|
|
-/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO
|
|
|
-and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/
|
|
|
-#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31))
|
|
|
-#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M (BIT(31))
|
|
|
-#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x1
|
|
|
-#define DSPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S 31
|
|
|
-/* DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */
|
|
|
-/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
|
|
|
-#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY (BIT(30))
|
|
|
-#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY_M (BIT(30))
|
|
|
-#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY_V 0x1
|
|
|
-#define DSPI_MEM_SPI_WBLEN_AFIFO_REMPTY_S 30
|
|
|
-/* DSPI_MEM_SPI_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */
|
|
|
-/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
|
|
|
-#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY (BIT(29))
|
|
|
-#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY_M (BIT(29))
|
|
|
-#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY_V 0x1
|
|
|
-#define DSPI_MEM_SPI_WDATA_AFIFO_REMPTY_S 29
|
|
|
-/* DSPI_MEM_SPI_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */
|
|
|
-/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
|
|
|
-#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY (BIT(28))
|
|
|
-#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY_M (BIT(28))
|
|
|
-#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY_V 0x1
|
|
|
-#define DSPI_MEM_SPI_RADDR_AFIFO_REMPTY_S 28
|
|
|
-/* DSPI_MEM_SPI_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */
|
|
|
-/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
|
|
|
-#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY (BIT(27))
|
|
|
-#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY_M (BIT(27))
|
|
|
-#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY_V 0x1
|
|
|
-#define DSPI_MEM_SPI_RDATA_AFIFO_REMPTY_S 27
|
|
|
-/* DSPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */
|
|
|
-/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
|
|
|
- and SPI0 transfers are done. 0: Others..*/
|
|
|
-#define DSPI_MEM_ALL_FIFO_EMPTY (BIT(26))
|
|
|
-#define DSPI_MEM_ALL_FIFO_EMPTY_M (BIT(26))
|
|
|
-#define DSPI_MEM_ALL_FIFO_EMPTY_V 0x1
|
|
|
-#define DSPI_MEM_ALL_FIFO_EMPTY_S 26
|
|
|
-/* DSPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
|
|
|
-/*description: This bits show the first AXI write/read invalid error or AXI write flash error a
|
|
|
-ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS
|
|
|
-H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
|
|
|
-#define DSPI_MEM_AXI_ERR_ADDR 0x03FFFFFF
|
|
|
-#define DSPI_MEM_AXI_ERR_ADDR_M ((DSPI_MEM_AXI_ERR_ADDR_V)<<(DSPI_MEM_AXI_ERR_ADDR_S))
|
|
|
-#define DSPI_MEM_AXI_ERR_ADDR_V 0x3FFFFFF
|
|
|
-#define DSPI_MEM_AXI_ERR_ADDR_S 0
|
|
|
-
|
|
|
-#define DSPI_SMEM_ECC_CTRL_REG (DR_REG_DSPI_MEM_BASE + 0x174)
|
|
|
-/* DSPI_SMEM_ECC_ADDR_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
|
|
|
-/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
|
|
|
-he ECC region or non-ECC region of external RAM. If there is no ECC region in ex
|
|
|
-ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/
|
|
|
-#define DSPI_SMEM_ECC_ADDR_EN (BIT(20))
|
|
|
-#define DSPI_SMEM_ECC_ADDR_EN_M (BIT(20))
|
|
|
-#define DSPI_SMEM_ECC_ADDR_EN_V 0x1
|
|
|
-#define DSPI_SMEM_ECC_ADDR_EN_S 20
|
|
|
-/* DSPI_SMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd2 ; */
|
|
|
-/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt
|
|
|
-es. 2: 1024 bytes. 3: 2048 bytes..*/
|
|
|
-#define DSPI_SMEM_PAGE_SIZE 0x00000003
|
|
|
-#define DSPI_SMEM_PAGE_SIZE_M ((DSPI_SMEM_PAGE_SIZE_V)<<(DSPI_SMEM_PAGE_SIZE_S))
|
|
|
-#define DSPI_SMEM_PAGE_SIZE_V 0x3
|
|
|
-#define DSPI_SMEM_PAGE_SIZE_S 18
|
|
|
-/* DSPI_SMEM_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
|
|
|
-rnal RAM..*/
|
|
|
-#define DSPI_SMEM_ECC_ERR_INT_EN (BIT(17))
|
|
|
-#define DSPI_SMEM_ECC_ERR_INT_EN_M (BIT(17))
|
|
|
-#define DSPI_SMEM_ECC_ERR_INT_EN_V 0x1
|
|
|
-#define DSPI_SMEM_ECC_ERR_INT_EN_S 17
|
|
|
-
|
|
|
-#define DSPI_MEM_TIMING_CALI_REG (DR_REG_DSPI_MEM_BASE + 0x180)
|
|
|
-/* DSPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/
|
|
|
-#define DSPI_MEM_TIMING_CALI_UPDATE (BIT(6))
|
|
|
-#define DSPI_MEM_TIMING_CALI_UPDATE_M (BIT(6))
|
|
|
-#define DSPI_MEM_TIMING_CALI_UPDATE_V 0x1
|
|
|
-#define DSPI_MEM_TIMING_CALI_UPDATE_S 6
|
|
|
-/* DSPI_MEM_DLL_TIMING_CALI : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f
|
|
|
-lash..*/
|
|
|
-#define DSPI_MEM_DLL_TIMING_CALI (BIT(5))
|
|
|
-#define DSPI_MEM_DLL_TIMING_CALI_M (BIT(5))
|
|
|
-#define DSPI_MEM_DLL_TIMING_CALI_V 0x1
|
|
|
-#define DSPI_MEM_DLL_TIMING_CALI_S 5
|
|
|
-/* DSPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
|
|
|
-/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
|
|
|
-#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007
|
|
|
-#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((DSPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(DSPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
|
|
|
-#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7
|
|
|
-#define DSPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2
|
|
|
-/* DSPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
|
|
-/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
|
|
|
-#define DSPI_MEM_TIMING_CALI (BIT(1))
|
|
|
-#define DSPI_MEM_TIMING_CALI_M (BIT(1))
|
|
|
-#define DSPI_MEM_TIMING_CALI_V 0x1
|
|
|
-#define DSPI_MEM_TIMING_CALI_S 1
|
|
|
-/* DSPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
|
|
-/*description: The bit is used to enable timing adjust clock for all reading operations..*/
|
|
|
-#define DSPI_MEM_TIMING_CLK_ENA (BIT(0))
|
|
|
-#define DSPI_MEM_TIMING_CLK_ENA_M (BIT(0))
|
|
|
-#define DSPI_MEM_TIMING_CLK_ENA_V 0x1
|
|
|
-#define DSPI_MEM_TIMING_CLK_ENA_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_DIN_MODE_REG (DR_REG_DSPI_MEM_BASE + 0x184)
|
|
|
-/* DSPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
|
|
|
-ut with the spi_clk.*/
|
|
|
-#define DSPI_MEM_DINS_MODE 0x00000007
|
|
|
-#define DSPI_MEM_DINS_MODE_M ((DSPI_MEM_DINS_MODE_V)<<(DSPI_MEM_DINS_MODE_S))
|
|
|
-#define DSPI_MEM_DINS_MODE_V 0x7
|
|
|
-#define DSPI_MEM_DINS_MODE_S 24
|
|
|
-/* DSPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
|
|
|
-ut with the spi_clk.*/
|
|
|
-#define DSPI_MEM_DIN7_MODE 0x00000007
|
|
|
-#define DSPI_MEM_DIN7_MODE_M ((DSPI_MEM_DIN7_MODE_V)<<(DSPI_MEM_DIN7_MODE_S))
|
|
|
-#define DSPI_MEM_DIN7_MODE_V 0x7
|
|
|
-#define DSPI_MEM_DIN7_MODE_S 21
|
|
|
-/* DSPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
|
|
|
-ut with the spi_clk.*/
|
|
|
-#define DSPI_MEM_DIN6_MODE 0x00000007
|
|
|
-#define DSPI_MEM_DIN6_MODE_M ((DSPI_MEM_DIN6_MODE_V)<<(DSPI_MEM_DIN6_MODE_S))
|
|
|
-#define DSPI_MEM_DIN6_MODE_V 0x7
|
|
|
-#define DSPI_MEM_DIN6_MODE_S 18
|
|
|
-/* DSPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
|
|
|
-ut with the spi_clk.*/
|
|
|
-#define DSPI_MEM_DIN5_MODE 0x00000007
|
|
|
-#define DSPI_MEM_DIN5_MODE_M ((DSPI_MEM_DIN5_MODE_V)<<(DSPI_MEM_DIN5_MODE_S))
|
|
|
-#define DSPI_MEM_DIN5_MODE_V 0x7
|
|
|
-#define DSPI_MEM_DIN5_MODE_S 15
|
|
|
-/* DSPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
|
|
|
-ut with the spi_clk.*/
|
|
|
-#define DSPI_MEM_DIN4_MODE 0x00000007
|
|
|
-#define DSPI_MEM_DIN4_MODE_M ((DSPI_MEM_DIN4_MODE_V)<<(DSPI_MEM_DIN4_MODE_S))
|
|
|
-#define DSPI_MEM_DIN4_MODE_V 0x7
|
|
|
-#define DSPI_MEM_DIN4_MODE_S 12
|
|
|
-/* DSPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
|
|
-#define DSPI_MEM_DIN3_MODE 0x00000007
|
|
|
-#define DSPI_MEM_DIN3_MODE_M ((DSPI_MEM_DIN3_MODE_V)<<(DSPI_MEM_DIN3_MODE_S))
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-#define DSPI_MEM_DIN3_MODE_V 0x7
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-#define DSPI_MEM_DIN3_MODE_S 9
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-/* DSPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
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|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
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-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
|
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-#define DSPI_MEM_DIN2_MODE 0x00000007
|
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-#define DSPI_MEM_DIN2_MODE_M ((DSPI_MEM_DIN2_MODE_V)<<(DSPI_MEM_DIN2_MODE_S))
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-#define DSPI_MEM_DIN2_MODE_V 0x7
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-#define DSPI_MEM_DIN2_MODE_S 6
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-/* DSPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
|
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-#define DSPI_MEM_DIN1_MODE 0x00000007
|
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-#define DSPI_MEM_DIN1_MODE_M ((DSPI_MEM_DIN1_MODE_V)<<(DSPI_MEM_DIN1_MODE_S))
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-#define DSPI_MEM_DIN1_MODE_V 0x7
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-#define DSPI_MEM_DIN1_MODE_S 3
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-/* DSPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
|
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-#define DSPI_MEM_DIN0_MODE 0x00000007
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-#define DSPI_MEM_DIN0_MODE_M ((DSPI_MEM_DIN0_MODE_V)<<(DSPI_MEM_DIN0_MODE_S))
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-#define DSPI_MEM_DIN0_MODE_V 0x7
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-#define DSPI_MEM_DIN0_MODE_S 0
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-
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-#define DSPI_MEM_DIN_NUM_REG (DR_REG_DSPI_MEM_BASE + 0x188)
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-/* DSPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
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|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
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|
-#define DSPI_MEM_DINS_NUM 0x00000003
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-#define DSPI_MEM_DINS_NUM_M ((DSPI_MEM_DINS_NUM_V)<<(DSPI_MEM_DINS_NUM_S))
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-#define DSPI_MEM_DINS_NUM_V 0x3
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|
-#define DSPI_MEM_DINS_NUM_S 16
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-/* DSPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_MEM_DIN7_NUM 0x00000003
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-#define DSPI_MEM_DIN7_NUM_M ((DSPI_MEM_DIN7_NUM_V)<<(DSPI_MEM_DIN7_NUM_S))
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-#define DSPI_MEM_DIN7_NUM_V 0x3
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|
-#define DSPI_MEM_DIN7_NUM_S 14
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-/* DSPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_MEM_DIN6_NUM 0x00000003
|
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|
-#define DSPI_MEM_DIN6_NUM_M ((DSPI_MEM_DIN6_NUM_V)<<(DSPI_MEM_DIN6_NUM_S))
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-#define DSPI_MEM_DIN6_NUM_V 0x3
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|
-#define DSPI_MEM_DIN6_NUM_S 12
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-/* DSPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_MEM_DIN5_NUM 0x00000003
|
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|
-#define DSPI_MEM_DIN5_NUM_M ((DSPI_MEM_DIN5_NUM_V)<<(DSPI_MEM_DIN5_NUM_S))
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|
-#define DSPI_MEM_DIN5_NUM_V 0x3
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|
-#define DSPI_MEM_DIN5_NUM_S 10
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|
-/* DSPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_MEM_DIN4_NUM 0x00000003
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|
-#define DSPI_MEM_DIN4_NUM_M ((DSPI_MEM_DIN4_NUM_V)<<(DSPI_MEM_DIN4_NUM_S))
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|
|
-#define DSPI_MEM_DIN4_NUM_V 0x3
|
|
|
-#define DSPI_MEM_DIN4_NUM_S 8
|
|
|
-/* DSPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_MEM_DIN3_NUM 0x00000003
|
|
|
-#define DSPI_MEM_DIN3_NUM_M ((DSPI_MEM_DIN3_NUM_V)<<(DSPI_MEM_DIN3_NUM_S))
|
|
|
-#define DSPI_MEM_DIN3_NUM_V 0x3
|
|
|
-#define DSPI_MEM_DIN3_NUM_S 6
|
|
|
-/* DSPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_MEM_DIN2_NUM 0x00000003
|
|
|
-#define DSPI_MEM_DIN2_NUM_M ((DSPI_MEM_DIN2_NUM_V)<<(DSPI_MEM_DIN2_NUM_S))
|
|
|
-#define DSPI_MEM_DIN2_NUM_V 0x3
|
|
|
-#define DSPI_MEM_DIN2_NUM_S 4
|
|
|
-/* DSPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_MEM_DIN1_NUM 0x00000003
|
|
|
-#define DSPI_MEM_DIN1_NUM_M ((DSPI_MEM_DIN1_NUM_V)<<(DSPI_MEM_DIN1_NUM_S))
|
|
|
-#define DSPI_MEM_DIN1_NUM_V 0x3
|
|
|
-#define DSPI_MEM_DIN1_NUM_S 2
|
|
|
-/* DSPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_MEM_DIN0_NUM 0x00000003
|
|
|
-#define DSPI_MEM_DIN0_NUM_M ((DSPI_MEM_DIN0_NUM_V)<<(DSPI_MEM_DIN0_NUM_S))
|
|
|
-#define DSPI_MEM_DIN0_NUM_V 0x3
|
|
|
-#define DSPI_MEM_DIN0_NUM_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_DOUT_MODE_REG (DR_REG_DSPI_MEM_BASE + 0x18C)
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|
|
-/* DSPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the spi_clk.*/
|
|
|
-#define DSPI_MEM_DOUTS_MODE (BIT(8))
|
|
|
-#define DSPI_MEM_DOUTS_MODE_M (BIT(8))
|
|
|
-#define DSPI_MEM_DOUTS_MODE_V 0x1
|
|
|
-#define DSPI_MEM_DOUTS_MODE_S 8
|
|
|
-/* DSPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the spi_clk.*/
|
|
|
-#define DSPI_MEM_DOUT7_MODE (BIT(7))
|
|
|
-#define DSPI_MEM_DOUT7_MODE_M (BIT(7))
|
|
|
-#define DSPI_MEM_DOUT7_MODE_V 0x1
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|
|
-#define DSPI_MEM_DOUT7_MODE_S 7
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|
|
-/* DSPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the spi_clk.*/
|
|
|
-#define DSPI_MEM_DOUT6_MODE (BIT(6))
|
|
|
-#define DSPI_MEM_DOUT6_MODE_M (BIT(6))
|
|
|
-#define DSPI_MEM_DOUT6_MODE_V 0x1
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|
|
-#define DSPI_MEM_DOUT6_MODE_S 6
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|
|
-/* DSPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the spi_clk.*/
|
|
|
-#define DSPI_MEM_DOUT5_MODE (BIT(5))
|
|
|
-#define DSPI_MEM_DOUT5_MODE_M (BIT(5))
|
|
|
-#define DSPI_MEM_DOUT5_MODE_V 0x1
|
|
|
-#define DSPI_MEM_DOUT5_MODE_S 5
|
|
|
-/* DSPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the spi_clk.*/
|
|
|
-#define DSPI_MEM_DOUT4_MODE (BIT(4))
|
|
|
-#define DSPI_MEM_DOUT4_MODE_M (BIT(4))
|
|
|
-#define DSPI_MEM_DOUT4_MODE_V 0x1
|
|
|
-#define DSPI_MEM_DOUT4_MODE_S 4
|
|
|
-/* DSPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_MEM_DOUT3_MODE (BIT(3))
|
|
|
-#define DSPI_MEM_DOUT3_MODE_M (BIT(3))
|
|
|
-#define DSPI_MEM_DOUT3_MODE_V 0x1
|
|
|
-#define DSPI_MEM_DOUT3_MODE_S 3
|
|
|
-/* DSPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_MEM_DOUT2_MODE (BIT(2))
|
|
|
-#define DSPI_MEM_DOUT2_MODE_M (BIT(2))
|
|
|
-#define DSPI_MEM_DOUT2_MODE_V 0x1
|
|
|
-#define DSPI_MEM_DOUT2_MODE_S 2
|
|
|
-/* DSPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_MEM_DOUT1_MODE (BIT(1))
|
|
|
-#define DSPI_MEM_DOUT1_MODE_M (BIT(1))
|
|
|
-#define DSPI_MEM_DOUT1_MODE_V 0x1
|
|
|
-#define DSPI_MEM_DOUT1_MODE_S 1
|
|
|
-/* DSPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_MEM_DOUT0_MODE (BIT(0))
|
|
|
-#define DSPI_MEM_DOUT0_MODE_M (BIT(0))
|
|
|
-#define DSPI_MEM_DOUT0_MODE_V 0x1
|
|
|
-#define DSPI_MEM_DOUT0_MODE_S 0
|
|
|
-
|
|
|
-#define DSPI_SMEM_TIMING_CALI_REG (DR_REG_DSPI_MEM_BASE + 0x190)
|
|
|
-/* DSPI_SMEM_DLL_TIMING_CALI : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E
|
|
|
-XT_RAM..*/
|
|
|
-#define DSPI_SMEM_DLL_TIMING_CALI (BIT(5))
|
|
|
-#define DSPI_SMEM_DLL_TIMING_CALI_M (BIT(5))
|
|
|
-#define DSPI_SMEM_DLL_TIMING_CALI_V 0x1
|
|
|
-#define DSPI_SMEM_DLL_TIMING_CALI_S 5
|
|
|
-/* DSPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
|
|
|
-/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/
|
|
|
-#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007
|
|
|
-#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_S))
|
|
|
-#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7
|
|
|
-#define DSPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2
|
|
|
-/* DSPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
|
|
-/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper
|
|
|
-ations..*/
|
|
|
-#define DSPI_SMEM_TIMING_CALI (BIT(1))
|
|
|
-#define DSPI_SMEM_TIMING_CALI_M (BIT(1))
|
|
|
-#define DSPI_SMEM_TIMING_CALI_V 0x1
|
|
|
-#define DSPI_SMEM_TIMING_CALI_S 1
|
|
|
-/* DSPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
|
|
-/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio
|
|
|
-ns..*/
|
|
|
-#define DSPI_SMEM_TIMING_CLK_ENA (BIT(0))
|
|
|
-#define DSPI_SMEM_TIMING_CLK_ENA_M (BIT(0))
|
|
|
-#define DSPI_SMEM_TIMING_CLK_ENA_V 0x1
|
|
|
-#define DSPI_SMEM_TIMING_CLK_ENA_S 0
|
|
|
-
|
|
|
-#define DSPI_SMEM_DIN_MODE_REG (DR_REG_DSPI_MEM_BASE + 0x194)
|
|
|
-/* DSPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DINS_MODE 0x00000007
|
|
|
-#define DSPI_SMEM_DINS_MODE_M ((DSPI_SMEM_DINS_MODE_V)<<(DSPI_SMEM_DINS_MODE_S))
|
|
|
-#define DSPI_SMEM_DINS_MODE_V 0x7
|
|
|
-#define DSPI_SMEM_DINS_MODE_S 24
|
|
|
-/* DSPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DIN7_MODE 0x00000007
|
|
|
-#define DSPI_SMEM_DIN7_MODE_M ((DSPI_SMEM_DIN7_MODE_V)<<(DSPI_SMEM_DIN7_MODE_S))
|
|
|
-#define DSPI_SMEM_DIN7_MODE_V 0x7
|
|
|
-#define DSPI_SMEM_DIN7_MODE_S 21
|
|
|
-/* DSPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DIN6_MODE 0x00000007
|
|
|
-#define DSPI_SMEM_DIN6_MODE_M ((DSPI_SMEM_DIN6_MODE_V)<<(DSPI_SMEM_DIN6_MODE_S))
|
|
|
-#define DSPI_SMEM_DIN6_MODE_V 0x7
|
|
|
-#define DSPI_SMEM_DIN6_MODE_S 18
|
|
|
-/* DSPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DIN5_MODE 0x00000007
|
|
|
-#define DSPI_SMEM_DIN5_MODE_M ((DSPI_SMEM_DIN5_MODE_V)<<(DSPI_SMEM_DIN5_MODE_S))
|
|
|
-#define DSPI_SMEM_DIN5_MODE_V 0x7
|
|
|
-#define DSPI_SMEM_DIN5_MODE_S 15
|
|
|
-/* DSPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
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-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
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-#define DSPI_SMEM_DIN4_MODE 0x00000007
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-#define DSPI_SMEM_DIN4_MODE_M ((DSPI_SMEM_DIN4_MODE_V)<<(DSPI_SMEM_DIN4_MODE_S))
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-#define DSPI_SMEM_DIN4_MODE_V 0x7
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-#define DSPI_SMEM_DIN4_MODE_S 12
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-/* DSPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
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-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
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-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
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-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
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-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
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-#define DSPI_SMEM_DIN3_MODE 0x00000007
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-#define DSPI_SMEM_DIN3_MODE_M ((DSPI_SMEM_DIN3_MODE_V)<<(DSPI_SMEM_DIN3_MODE_S))
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-#define DSPI_SMEM_DIN3_MODE_V 0x7
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-#define DSPI_SMEM_DIN3_MODE_S 9
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-/* DSPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
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-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
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-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
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-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
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-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
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-#define DSPI_SMEM_DIN2_MODE 0x00000007
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-#define DSPI_SMEM_DIN2_MODE_M ((DSPI_SMEM_DIN2_MODE_V)<<(DSPI_SMEM_DIN2_MODE_S))
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-#define DSPI_SMEM_DIN2_MODE_V 0x7
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-#define DSPI_SMEM_DIN2_MODE_S 6
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-/* DSPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
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-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
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|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
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-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
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-#define DSPI_SMEM_DIN1_MODE 0x00000007
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-#define DSPI_SMEM_DIN1_MODE_M ((DSPI_SMEM_DIN1_MODE_V)<<(DSPI_SMEM_DIN1_MODE_S))
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-#define DSPI_SMEM_DIN1_MODE_V 0x7
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-#define DSPI_SMEM_DIN1_MODE_S 3
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-/* DSPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
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-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
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-#define DSPI_SMEM_DIN0_MODE 0x00000007
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-#define DSPI_SMEM_DIN0_MODE_M ((DSPI_SMEM_DIN0_MODE_V)<<(DSPI_SMEM_DIN0_MODE_S))
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-#define DSPI_SMEM_DIN0_MODE_V 0x7
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-#define DSPI_SMEM_DIN0_MODE_S 0
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-
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-#define DSPI_SMEM_DIN_NUM_REG (DR_REG_DSPI_MEM_BASE + 0x198)
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-/* DSPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
|
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|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
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|
-#define DSPI_SMEM_DINS_NUM 0x00000003
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-#define DSPI_SMEM_DINS_NUM_M ((DSPI_SMEM_DINS_NUM_V)<<(DSPI_SMEM_DINS_NUM_S))
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-#define DSPI_SMEM_DINS_NUM_V 0x3
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-#define DSPI_SMEM_DINS_NUM_S 16
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-/* DSPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
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|
-#define DSPI_SMEM_DIN7_NUM 0x00000003
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|
-#define DSPI_SMEM_DIN7_NUM_M ((DSPI_SMEM_DIN7_NUM_V)<<(DSPI_SMEM_DIN7_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN7_NUM_V 0x3
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|
|
-#define DSPI_SMEM_DIN7_NUM_S 14
|
|
|
-/* DSPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN6_NUM 0x00000003
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|
-#define DSPI_SMEM_DIN6_NUM_M ((DSPI_SMEM_DIN6_NUM_V)<<(DSPI_SMEM_DIN6_NUM_S))
|
|
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-#define DSPI_SMEM_DIN6_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN6_NUM_S 12
|
|
|
-/* DSPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN5_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN5_NUM_M ((DSPI_SMEM_DIN5_NUM_V)<<(DSPI_SMEM_DIN5_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN5_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN5_NUM_S 10
|
|
|
-/* DSPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN4_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN4_NUM_M ((DSPI_SMEM_DIN4_NUM_V)<<(DSPI_SMEM_DIN4_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN4_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN4_NUM_S 8
|
|
|
-/* DSPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN3_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN3_NUM_M ((DSPI_SMEM_DIN3_NUM_V)<<(DSPI_SMEM_DIN3_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN3_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN3_NUM_S 6
|
|
|
-/* DSPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN2_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN2_NUM_M ((DSPI_SMEM_DIN2_NUM_V)<<(DSPI_SMEM_DIN2_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN2_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN2_NUM_S 4
|
|
|
-/* DSPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN1_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN1_NUM_M ((DSPI_SMEM_DIN1_NUM_V)<<(DSPI_SMEM_DIN1_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN1_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN1_NUM_S 2
|
|
|
-/* DSPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN0_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN0_NUM_M ((DSPI_SMEM_DIN0_NUM_V)<<(DSPI_SMEM_DIN0_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN0_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN0_NUM_S 0
|
|
|
-
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|
|
-#define DSPI_SMEM_DOUT_MODE_REG (DR_REG_DSPI_MEM_BASE + 0x19C)
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|
|
-/* DSPI_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUTS_MODE (BIT(8))
|
|
|
-#define DSPI_SMEM_DOUTS_MODE_M (BIT(8))
|
|
|
-#define DSPI_SMEM_DOUTS_MODE_V 0x1
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|
|
-#define DSPI_SMEM_DOUTS_MODE_S 8
|
|
|
-/* DSPI_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT7_MODE (BIT(7))
|
|
|
-#define DSPI_SMEM_DOUT7_MODE_M (BIT(7))
|
|
|
-#define DSPI_SMEM_DOUT7_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT7_MODE_S 7
|
|
|
-/* DSPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT6_MODE (BIT(6))
|
|
|
-#define DSPI_SMEM_DOUT6_MODE_M (BIT(6))
|
|
|
-#define DSPI_SMEM_DOUT6_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT6_MODE_S 6
|
|
|
-/* DSPI_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT5_MODE (BIT(5))
|
|
|
-#define DSPI_SMEM_DOUT5_MODE_M (BIT(5))
|
|
|
-#define DSPI_SMEM_DOUT5_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT5_MODE_S 5
|
|
|
-/* DSPI_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT4_MODE (BIT(4))
|
|
|
-#define DSPI_SMEM_DOUT4_MODE_M (BIT(4))
|
|
|
-#define DSPI_SMEM_DOUT4_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT4_MODE_S 4
|
|
|
-/* DSPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT3_MODE (BIT(3))
|
|
|
-#define DSPI_SMEM_DOUT3_MODE_M (BIT(3))
|
|
|
-#define DSPI_SMEM_DOUT3_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT3_MODE_S 3
|
|
|
-/* DSPI_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT2_MODE (BIT(2))
|
|
|
-#define DSPI_SMEM_DOUT2_MODE_M (BIT(2))
|
|
|
-#define DSPI_SMEM_DOUT2_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT2_MODE_S 2
|
|
|
-/* DSPI_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT1_MODE (BIT(1))
|
|
|
-#define DSPI_SMEM_DOUT1_MODE_M (BIT(1))
|
|
|
-#define DSPI_SMEM_DOUT1_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT1_MODE_S 1
|
|
|
-/* DSPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT0_MODE (BIT(0))
|
|
|
-#define DSPI_SMEM_DOUT0_MODE_M (BIT(0))
|
|
|
-#define DSPI_SMEM_DOUT0_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT0_MODE_S 0
|
|
|
-
|
|
|
-#define DSPI_SMEM_AC_REG (DR_REG_DSPI_MEM_BASE + 0x1A0)
|
|
|
-/* DSPI_SMEM_SPLIT_TRANS_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
|
|
|
-/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
|
|
|
- transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt
|
|
|
-er whether there is an ECC region or not..*/
|
|
|
-#define DSPI_SMEM_SPLIT_TRANS_EN (BIT(31))
|
|
|
-#define DSPI_SMEM_SPLIT_TRANS_EN_M (BIT(31))
|
|
|
-#define DSPI_SMEM_SPLIT_TRANS_EN_V 0x1
|
|
|
-#define DSPI_SMEM_SPLIT_TRANS_EN_S 31
|
|
|
-/* DSPI_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
|
|
|
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
|
|
|
-sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
|
|
|
-SPI core clock cycles..*/
|
|
|
-#define DSPI_SMEM_CS_HOLD_DELAY 0x0000003F
|
|
|
-#define DSPI_SMEM_CS_HOLD_DELAY_M ((DSPI_SMEM_CS_HOLD_DELAY_V)<<(DSPI_SMEM_CS_HOLD_DELAY_S))
|
|
|
-#define DSPI_SMEM_CS_HOLD_DELAY_V 0x3F
|
|
|
-#define DSPI_SMEM_CS_HOLD_DELAY_S 25
|
|
|
-/* DSPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
|
|
|
-n accesses external RAM..*/
|
|
|
-#define DSPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16))
|
|
|
-#define DSPI_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16))
|
|
|
-#define DSPI_SMEM_ECC_16TO18_BYTE_EN_V 0x1
|
|
|
-#define DSPI_SMEM_ECC_16TO18_BYTE_EN_S 16
|
|
|
-/* DSPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[15] ;default: 1'b1 ; */
|
|
|
-/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh
|
|
|
-en accesses external RAM..*/
|
|
|
-#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15))
|
|
|
-#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15))
|
|
|
-#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1
|
|
|
-#define DSPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15
|
|
|
-/* DSPI_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
|
|
|
-/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c
|
|
|
-ycles in ECC mode when accessed external RAM..*/
|
|
|
-#define DSPI_SMEM_ECC_CS_HOLD_TIME 0x00000007
|
|
|
-#define DSPI_SMEM_ECC_CS_HOLD_TIME_M ((DSPI_SMEM_ECC_CS_HOLD_TIME_V)<<(DSPI_SMEM_ECC_CS_HOLD_TIME_S))
|
|
|
-#define DSPI_SMEM_ECC_CS_HOLD_TIME_V 0x7
|
|
|
-#define DSPI_SMEM_ECC_CS_HOLD_TIME_S 12
|
|
|
-/* DSPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */
|
|
|
-/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a
|
|
|
-re combined with spi_mem_cs_hold bit..*/
|
|
|
-#define DSPI_SMEM_CS_HOLD_TIME 0x0000001F
|
|
|
-#define DSPI_SMEM_CS_HOLD_TIME_M ((DSPI_SMEM_CS_HOLD_TIME_V)<<(DSPI_SMEM_CS_HOLD_TIME_S))
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-#define DSPI_SMEM_CS_HOLD_TIME_V 0x1F
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-#define DSPI_SMEM_CS_HOLD_TIME_S 7
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-/* DSPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */
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-/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s
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-pi_mem_cs_setup bit..*/
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-#define DSPI_SMEM_CS_SETUP_TIME 0x0000001F
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-#define DSPI_SMEM_CS_SETUP_TIME_M ((DSPI_SMEM_CS_SETUP_TIME_V)<<(DSPI_SMEM_CS_SETUP_TIME_S))
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-#define DSPI_SMEM_CS_SETUP_TIME_V 0x1F
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-#define DSPI_SMEM_CS_SETUP_TIME_S 2
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-/* DSPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
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-/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab
|
|
|
-le..*/
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-#define DSPI_SMEM_CS_HOLD (BIT(1))
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-#define DSPI_SMEM_CS_HOLD_M (BIT(1))
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-#define DSPI_SMEM_CS_HOLD_V 0x1
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-#define DSPI_SMEM_CS_HOLD_S 1
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-/* DSPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */
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-/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d
|
|
|
-isable..*/
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-#define DSPI_SMEM_CS_SETUP (BIT(0))
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-#define DSPI_SMEM_CS_SETUP_M (BIT(0))
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-#define DSPI_SMEM_CS_SETUP_V 0x1
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-#define DSPI_SMEM_CS_SETUP_S 0
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-
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-#define DSPI_SMEM_DIN_HEX_MODE_REG (DR_REG_DSPI_MEM_BASE + 0x1A4)
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-/* DSPI_SMEM_DINS_HEX_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
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-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
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-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
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-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
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-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
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-#define DSPI_SMEM_DINS_HEX_MODE 0x00000007
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-#define DSPI_SMEM_DINS_HEX_MODE_M ((DSPI_SMEM_DINS_HEX_MODE_V)<<(DSPI_SMEM_DINS_HEX_MODE_S))
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-#define DSPI_SMEM_DINS_HEX_MODE_V 0x7
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-#define DSPI_SMEM_DINS_HEX_MODE_S 24
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-/* DSPI_SMEM_DIN15_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
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-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
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-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
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-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
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-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
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-#define DSPI_SMEM_DIN15_MODE 0x00000007
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-#define DSPI_SMEM_DIN15_MODE_M ((DSPI_SMEM_DIN15_MODE_V)<<(DSPI_SMEM_DIN15_MODE_S))
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-#define DSPI_SMEM_DIN15_MODE_V 0x7
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-#define DSPI_SMEM_DIN15_MODE_S 21
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-/* DSPI_SMEM_DIN14_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
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-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
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-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
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|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
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-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
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-#define DSPI_SMEM_DIN14_MODE 0x00000007
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-#define DSPI_SMEM_DIN14_MODE_M ((DSPI_SMEM_DIN14_MODE_V)<<(DSPI_SMEM_DIN14_MODE_S))
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-#define DSPI_SMEM_DIN14_MODE_V 0x7
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-#define DSPI_SMEM_DIN14_MODE_S 18
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-/* DSPI_SMEM_DIN13_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
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-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
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|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
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|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
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-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
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-#define DSPI_SMEM_DIN13_MODE 0x00000007
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-#define DSPI_SMEM_DIN13_MODE_M ((DSPI_SMEM_DIN13_MODE_V)<<(DSPI_SMEM_DIN13_MODE_S))
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-#define DSPI_SMEM_DIN13_MODE_V 0x7
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-#define DSPI_SMEM_DIN13_MODE_S 15
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-/* DSPI_SMEM_DIN12_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
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|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
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|
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-#define DSPI_SMEM_DIN12_MODE 0x00000007
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-#define DSPI_SMEM_DIN12_MODE_M ((DSPI_SMEM_DIN12_MODE_V)<<(DSPI_SMEM_DIN12_MODE_S))
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-#define DSPI_SMEM_DIN12_MODE_V 0x7
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-#define DSPI_SMEM_DIN12_MODE_S 12
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-/* DSPI_SMEM_DIN11_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
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|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
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|
|
-#define DSPI_SMEM_DIN11_MODE 0x00000007
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|
-#define DSPI_SMEM_DIN11_MODE_M ((DSPI_SMEM_DIN11_MODE_V)<<(DSPI_SMEM_DIN11_MODE_S))
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|
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-#define DSPI_SMEM_DIN11_MODE_V 0x7
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|
|
-#define DSPI_SMEM_DIN11_MODE_S 9
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|
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-/* DSPI_SMEM_DIN10_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DIN10_MODE 0x00000007
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|
|
-#define DSPI_SMEM_DIN10_MODE_M ((DSPI_SMEM_DIN10_MODE_V)<<(DSPI_SMEM_DIN10_MODE_S))
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|
|
-#define DSPI_SMEM_DIN10_MODE_V 0x7
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|
|
-#define DSPI_SMEM_DIN10_MODE_S 6
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|
|
-/* DSPI_SMEM_DIN09_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DIN09_MODE 0x00000007
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|
|
-#define DSPI_SMEM_DIN09_MODE_M ((DSPI_SMEM_DIN09_MODE_V)<<(DSPI_SMEM_DIN09_MODE_S))
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|
|
-#define DSPI_SMEM_DIN09_MODE_V 0x7
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|
|
-#define DSPI_SMEM_DIN09_MODE_S 3
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|
|
-/* DSPI_SMEM_DIN08_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
|
|
|
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in
|
|
|
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
|
|
|
-ith the spi_clk high edge, 6: input with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DIN08_MODE 0x00000007
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|
|
-#define DSPI_SMEM_DIN08_MODE_M ((DSPI_SMEM_DIN08_MODE_V)<<(DSPI_SMEM_DIN08_MODE_S))
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|
|
-#define DSPI_SMEM_DIN08_MODE_V 0x7
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|
|
-#define DSPI_SMEM_DIN08_MODE_S 0
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|
|
-
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|
|
-#define DSPI_SMEM_DIN_HEX_NUM_REG (DR_REG_DSPI_MEM_BASE + 0x1A8)
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|
|
-/* DSPI_SMEM_DINS_HEX_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DINS_HEX_NUM 0x00000003
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|
|
-#define DSPI_SMEM_DINS_HEX_NUM_M ((DSPI_SMEM_DINS_HEX_NUM_V)<<(DSPI_SMEM_DINS_HEX_NUM_S))
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|
|
-#define DSPI_SMEM_DINS_HEX_NUM_V 0x3
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|
|
-#define DSPI_SMEM_DINS_HEX_NUM_S 16
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|
|
-/* DSPI_SMEM_DIN15_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN15_NUM 0x00000003
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|
|
-#define DSPI_SMEM_DIN15_NUM_M ((DSPI_SMEM_DIN15_NUM_V)<<(DSPI_SMEM_DIN15_NUM_S))
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|
|
-#define DSPI_SMEM_DIN15_NUM_V 0x3
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|
|
-#define DSPI_SMEM_DIN15_NUM_S 14
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|
|
-/* DSPI_SMEM_DIN14_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN14_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN14_NUM_M ((DSPI_SMEM_DIN14_NUM_V)<<(DSPI_SMEM_DIN14_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN14_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN14_NUM_S 12
|
|
|
-/* DSPI_SMEM_DIN13_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN13_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN13_NUM_M ((DSPI_SMEM_DIN13_NUM_V)<<(DSPI_SMEM_DIN13_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN13_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN13_NUM_S 10
|
|
|
-/* DSPI_SMEM_DIN12_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN12_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN12_NUM_M ((DSPI_SMEM_DIN12_NUM_V)<<(DSPI_SMEM_DIN12_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN12_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN12_NUM_S 8
|
|
|
-/* DSPI_SMEM_DIN11_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN11_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN11_NUM_M ((DSPI_SMEM_DIN11_NUM_V)<<(DSPI_SMEM_DIN11_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN11_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN11_NUM_S 6
|
|
|
-/* DSPI_SMEM_DIN10_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN10_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN10_NUM_M ((DSPI_SMEM_DIN10_NUM_V)<<(DSPI_SMEM_DIN10_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN10_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN10_NUM_S 4
|
|
|
-/* DSPI_SMEM_DIN09_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN09_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN09_NUM_M ((DSPI_SMEM_DIN09_NUM_V)<<(DSPI_SMEM_DIN09_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN09_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN09_NUM_S 2
|
|
|
-/* DSPI_SMEM_DIN08_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
|
|
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
|
|
|
-delayed by 2 cycles,....*/
|
|
|
-#define DSPI_SMEM_DIN08_NUM 0x00000003
|
|
|
-#define DSPI_SMEM_DIN08_NUM_M ((DSPI_SMEM_DIN08_NUM_V)<<(DSPI_SMEM_DIN08_NUM_S))
|
|
|
-#define DSPI_SMEM_DIN08_NUM_V 0x3
|
|
|
-#define DSPI_SMEM_DIN08_NUM_S 0
|
|
|
-
|
|
|
-#define DSPI_SMEM_DOUT_HEX_MODE_REG (DR_REG_DSPI_MEM_BASE + 0x1AC)
|
|
|
-/* DSPI_SMEM_DOUTS_HEX_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUTS_HEX_MODE (BIT(8))
|
|
|
-#define DSPI_SMEM_DOUTS_HEX_MODE_M (BIT(8))
|
|
|
-#define DSPI_SMEM_DOUTS_HEX_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUTS_HEX_MODE_S 8
|
|
|
-/* DSPI_SMEM_DOUT15_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT15_MODE (BIT(7))
|
|
|
-#define DSPI_SMEM_DOUT15_MODE_M (BIT(7))
|
|
|
-#define DSPI_SMEM_DOUT15_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT15_MODE_S 7
|
|
|
-/* DSPI_SMEM_DOUT14_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT14_MODE (BIT(6))
|
|
|
-#define DSPI_SMEM_DOUT14_MODE_M (BIT(6))
|
|
|
-#define DSPI_SMEM_DOUT14_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT14_MODE_S 6
|
|
|
-/* DSPI_SMEM_DOUT13_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT13_MODE (BIT(5))
|
|
|
-#define DSPI_SMEM_DOUT13_MODE_M (BIT(5))
|
|
|
-#define DSPI_SMEM_DOUT13_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT13_MODE_S 5
|
|
|
-/* DSPI_SMEM_DOUT12_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT12_MODE (BIT(4))
|
|
|
-#define DSPI_SMEM_DOUT12_MODE_M (BIT(4))
|
|
|
-#define DSPI_SMEM_DOUT12_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT12_MODE_S 4
|
|
|
-/* DSPI_SMEM_DOUT11_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT11_MODE (BIT(3))
|
|
|
-#define DSPI_SMEM_DOUT11_MODE_M (BIT(3))
|
|
|
-#define DSPI_SMEM_DOUT11_MODE_V 0x1
|
|
|
-#define DSPI_SMEM_DOUT11_MODE_S 3
|
|
|
-/* DSPI_SMEM_DOUT10_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT10_MODE (BIT(2))
|
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|
-#define DSPI_SMEM_DOUT10_MODE_M (BIT(2))
|
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|
-#define DSPI_SMEM_DOUT10_MODE_V 0x1
|
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|
-#define DSPI_SMEM_DOUT10_MODE_S 2
|
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|
-/* DSPI_SMEM_DOUT09_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT09_MODE (BIT(1))
|
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|
-#define DSPI_SMEM_DOUT09_MODE_M (BIT(1))
|
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-#define DSPI_SMEM_DOUT09_MODE_V 0x1
|
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|
-#define DSPI_SMEM_DOUT09_MODE_S 1
|
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|
-/* DSPI_SMEM_DOUT08_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
|
|
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
|
|
|
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
|
|
|
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
|
|
|
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
|
|
-#define DSPI_SMEM_DOUT08_MODE (BIT(0))
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|
-#define DSPI_SMEM_DOUT08_MODE_M (BIT(0))
|
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|
-#define DSPI_SMEM_DOUT08_MODE_V 0x1
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-#define DSPI_SMEM_DOUT08_MODE_S 0
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|
-
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|
-#define DSPI_MEM_CLOCK_GATE_REG (DR_REG_DSPI_MEM_BASE + 0x200)
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|
-/* DSPI_MEM_SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
|
|
-/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
|
|
|
-#define DSPI_MEM_SPI_CLK_EN (BIT(0))
|
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|
-#define DSPI_MEM_SPI_CLK_EN_M (BIT(0))
|
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|
-#define DSPI_MEM_SPI_CLK_EN_V 0x1
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-#define DSPI_MEM_SPI_CLK_EN_S 0
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-
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-#define DSPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_DSPI_MEM_BASE + 0x300)
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-/* DSPI_MEM_SPI_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
|
|
-/*description: This field is only used to generate include file in c case. This field is useles
|
|
|
-s. Please do not use this field..*/
|
|
|
-#define DSPI_MEM_SPI_XTS_PLAIN 0xFFFFFFFF
|
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|
-#define DSPI_MEM_SPI_XTS_PLAIN_M ((DSPI_MEM_SPI_XTS_PLAIN_V)<<(DSPI_MEM_SPI_XTS_PLAIN_S))
|
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|
-#define DSPI_MEM_SPI_XTS_PLAIN_V 0xFFFFFFFF
|
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|
-#define DSPI_MEM_SPI_XTS_PLAIN_S 0
|
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|
-
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|
-#define DSPI_MEM_XTS_LINESIZE_REG (DR_REG_DSPI_MEM_BASE + 0x340)
|
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|
-/* DSPI_MEM_SPI_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
|
|
-/*description: This bits stores the line-size parameter which will be used in manual encryption
|
|
|
- calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
|
|
|
- 1: 32-bytes, 2: 64-bytes, 3:reserved..*/
|
|
|
-#define DSPI_MEM_SPI_XTS_LINESIZE 0x00000003
|
|
|
-#define DSPI_MEM_SPI_XTS_LINESIZE_M ((DSPI_MEM_SPI_XTS_LINESIZE_V)<<(DSPI_MEM_SPI_XTS_LINESIZE_S))
|
|
|
-#define DSPI_MEM_SPI_XTS_LINESIZE_V 0x3
|
|
|
-#define DSPI_MEM_SPI_XTS_LINESIZE_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_XTS_DESTINATION_REG (DR_REG_DSPI_MEM_BASE + 0x344)
|
|
|
-/* DSPI_MEM_SPI_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
|
|
-/*description: This bit stores the destination parameter which will be used in manual encryptio
|
|
|
-n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
|
|
|
-used..*/
|
|
|
-#define DSPI_MEM_SPI_XTS_DESTINATION (BIT(0))
|
|
|
-#define DSPI_MEM_SPI_XTS_DESTINATION_M (BIT(0))
|
|
|
-#define DSPI_MEM_SPI_XTS_DESTINATION_V 0x1
|
|
|
-#define DSPI_MEM_SPI_XTS_DESTINATION_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_DSPI_MEM_BASE + 0x348)
|
|
|
-/* DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
|
|
|
-/*description: This bits stores the physical-address parameter which will be used in manual enc
|
|
|
-ryption calculation. This value should aligned with byte number decided by line-
|
|
|
-size parameter..*/
|
|
|
-#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS 0x03FFFFFF
|
|
|
-#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_M ((DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V)<<(DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S))
|
|
|
-#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFF
|
|
|
-#define DSPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_XTS_TRIGGER_REG (DR_REG_DSPI_MEM_BASE + 0x34C)
|
|
|
-/* DSPI_MEM_SPI_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to trigger the process of manual encryption calculation. This actio
|
|
|
-n should only be asserted when manual encryption status is 0. After this action,
|
|
|
- manual encryption status becomes 1. After calculation is done, manual encryptio
|
|
|
-n status becomes 2..*/
|
|
|
-#define DSPI_MEM_SPI_XTS_TRIGGER (BIT(0))
|
|
|
-#define DSPI_MEM_SPI_XTS_TRIGGER_M (BIT(0))
|
|
|
-#define DSPI_MEM_SPI_XTS_TRIGGER_V 0x1
|
|
|
-#define DSPI_MEM_SPI_XTS_TRIGGER_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_XTS_RELEASE_REG (DR_REG_DSPI_MEM_BASE + 0x350)
|
|
|
-/* DSPI_MEM_SPI_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to release encrypted result to mspi. This action should only be ass
|
|
|
-erted when manual encryption status is 2. After this action, manual encryption s
|
|
|
-tatus will become 3..*/
|
|
|
-#define DSPI_MEM_SPI_XTS_RELEASE (BIT(0))
|
|
|
-#define DSPI_MEM_SPI_XTS_RELEASE_M (BIT(0))
|
|
|
-#define DSPI_MEM_SPI_XTS_RELEASE_V 0x1
|
|
|
-#define DSPI_MEM_SPI_XTS_RELEASE_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_XTS_DESTROY_REG (DR_REG_DSPI_MEM_BASE + 0x354)
|
|
|
-/* DSPI_MEM_SPI_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
|
|
|
-en manual encryption status is 3. After this action, manual encryption status wi
|
|
|
-ll become 0..*/
|
|
|
-#define DSPI_MEM_SPI_XTS_DESTROY (BIT(0))
|
|
|
-#define DSPI_MEM_SPI_XTS_DESTROY_M (BIT(0))
|
|
|
-#define DSPI_MEM_SPI_XTS_DESTROY_V 0x1
|
|
|
-#define DSPI_MEM_SPI_XTS_DESTROY_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_XTS_STATE_REG (DR_REG_DSPI_MEM_BASE + 0x358)
|
|
|
-/* DSPI_MEM_SPI_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
|
|
|
-/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
|
|
|
- calculation, 2: encryption calculation is done but the encrypted result is invi
|
|
|
-sible to mspi, 3: the encrypted result is visible to mspi..*/
|
|
|
-#define DSPI_MEM_SPI_XTS_STATE 0x00000003
|
|
|
-#define DSPI_MEM_SPI_XTS_STATE_M ((DSPI_MEM_SPI_XTS_STATE_V)<<(DSPI_MEM_SPI_XTS_STATE_S))
|
|
|
-#define DSPI_MEM_SPI_XTS_STATE_V 0x3
|
|
|
-#define DSPI_MEM_SPI_XTS_STATE_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_XTS_DATE_REG (DR_REG_DSPI_MEM_BASE + 0x35C)
|
|
|
-/* DSPI_MEM_SPI_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
|
|
|
-/*description: This bits stores the last modified-time of manual encryption feature..*/
|
|
|
-#define DSPI_MEM_SPI_XTS_DATE 0x3FFFFFFF
|
|
|
-#define DSPI_MEM_SPI_XTS_DATE_M ((DSPI_MEM_SPI_XTS_DATE_V)<<(DSPI_MEM_SPI_XTS_DATE_S))
|
|
|
-#define DSPI_MEM_SPI_XTS_DATE_V 0x3FFFFFFF
|
|
|
-#define DSPI_MEM_SPI_XTS_DATE_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_DSPI_MEM_BASE + 0x37C)
|
|
|
-/* DSPI_MEM_SPI_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
|
|
|
-/*description: MSPI-MMU item content.*/
|
|
|
-#define DSPI_MEM_SPI_MMU_ITEM_CONTENT 0xFFFFFFFF
|
|
|
-#define DSPI_MEM_SPI_MMU_ITEM_CONTENT_M ((DSPI_MEM_SPI_MMU_ITEM_CONTENT_V)<<(DSPI_MEM_SPI_MMU_ITEM_CONTENT_S))
|
|
|
-#define DSPI_MEM_SPI_MMU_ITEM_CONTENT_V 0xFFFFFFFF
|
|
|
-#define DSPI_MEM_SPI_MMU_ITEM_CONTENT_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_DSPI_MEM_BASE + 0x380)
|
|
|
-/* DSPI_MEM_SPI_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
|
|
-/*description: MSPI-MMU item index.*/
|
|
|
-#define DSPI_MEM_SPI_MMU_ITEM_INDEX 0xFFFFFFFF
|
|
|
-#define DSPI_MEM_SPI_MMU_ITEM_INDEX_M ((DSPI_MEM_SPI_MMU_ITEM_INDEX_V)<<(DSPI_MEM_SPI_MMU_ITEM_INDEX_S))
|
|
|
-#define DSPI_MEM_SPI_MMU_ITEM_INDEX_V 0xFFFFFFFF
|
|
|
-#define DSPI_MEM_SPI_MMU_ITEM_INDEX_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_MMU_POWER_CTRL_REG (DR_REG_DSPI_MEM_BASE + 0x384)
|
|
|
-/* DSPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */
|
|
|
-/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/
|
|
|
-#define DSPI_MEM_RDN_RESULT (BIT(31))
|
|
|
-#define DSPI_MEM_RDN_RESULT_M (BIT(31))
|
|
|
-#define DSPI_MEM_RDN_RESULT_V 0x1
|
|
|
-#define DSPI_MEM_RDN_RESULT_S 31
|
|
|
-/* DSPI_MEM_RDN_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
|
|
-/*description: ECO register enable bit.*/
|
|
|
-#define DSPI_MEM_RDN_ENA (BIT(30))
|
|
|
-#define DSPI_MEM_RDN_ENA_M (BIT(30))
|
|
|
-#define DSPI_MEM_RDN_ENA_V 0x1
|
|
|
-#define DSPI_MEM_RDN_ENA_S 30
|
|
|
-/* DSPI_MEM_AUX_CTRL : R/W ;bitpos:[29:16] ;default: 14'h1320 ; */
|
|
|
-/*description: MMU PSRAM aux control register.*/
|
|
|
-#define DSPI_MEM_AUX_CTRL 0x00003FFF
|
|
|
-#define DSPI_MEM_AUX_CTRL_M ((DSPI_MEM_AUX_CTRL_V)<<(DSPI_MEM_AUX_CTRL_S))
|
|
|
-#define DSPI_MEM_AUX_CTRL_V 0x3FFF
|
|
|
-#define DSPI_MEM_AUX_CTRL_S 16
|
|
|
-/* DSPI_MEM_SPI_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
|
|
-/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be
|
|
|
- controlled by rtc..*/
|
|
|
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU (BIT(2))
|
|
|
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU_M (BIT(2))
|
|
|
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU_V 0x1
|
|
|
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PU_S 2
|
|
|
-/* DSPI_MEM_SPI_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to force mmu-memory powerdown.*/
|
|
|
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD (BIT(1))
|
|
|
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD_M (BIT(1))
|
|
|
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD_V 0x1
|
|
|
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_PD_S 1
|
|
|
-/* DSPI_MEM_SPI_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
|
|
-/*description: Set this bit to enable mmu-memory clock force on.*/
|
|
|
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON (BIT(0))
|
|
|
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON_M (BIT(0))
|
|
|
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON_V 0x1
|
|
|
-#define DSPI_MEM_SPI_MMU_MEM_FORCE_ON_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_DPA_CTRL_REG (DR_REG_DSPI_MEM_BASE + 0x388)
|
|
|
-/* DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
|
|
-/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
|
|
|
-T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
|
|
|
-#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER (BIT(4))
|
|
|
-#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_M (BIT(4))
|
|
|
-#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_V 0x1
|
|
|
-#define DSPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_S 4
|
|
|
-/* DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
|
|
-/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
|
|
|
-ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
|
|
|
-ing key 1..*/
|
|
|
-#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN (BIT(3))
|
|
|
-#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_M (BIT(3))
|
|
|
-#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_V 0x1
|
|
|
-#define DSPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_S 3
|
|
|
-/* DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
|
|
|
-/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
|
|
|
-7: The bigger the number is, the more secure the cryption is. (Note that the per
|
|
|
-formance of cryption will decrease together with this number increasing).*/
|
|
|
-#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL 0x00000007
|
|
|
-#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_M ((DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V)<<(DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S))
|
|
|
-#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V 0x7
|
|
|
-#define DSPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_REGISTERRND_ECO_HIGH_REG (DR_REG_DSPI_MEM_BASE + 0x3F0)
|
|
|
-/* DSPI_MEM_REGISTERRND_ECO_HIGH : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
|
|
|
-/*description: ECO high register.*/
|
|
|
-#define DSPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFF
|
|
|
-#define DSPI_MEM_REGISTERRND_ECO_HIGH_M ((DSPI_MEM_REGISTERRND_ECO_HIGH_V)<<(DSPI_MEM_REGISTERRND_ECO_HIGH_S))
|
|
|
-#define DSPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFF
|
|
|
-#define DSPI_MEM_REGISTERRND_ECO_HIGH_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_REGISTERRND_ECO_LOW_REG (DR_REG_DSPI_MEM_BASE + 0x3F4)
|
|
|
-/* DSPI_MEM_REGISTERRND_ECO_LOW : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
|
|
|
-/*description: ECO low register.*/
|
|
|
-#define DSPI_MEM_REGISTERRND_ECO_LOW 0xFFFFFFFF
|
|
|
-#define DSPI_MEM_REGISTERRND_ECO_LOW_M ((DSPI_MEM_REGISTERRND_ECO_LOW_V)<<(DSPI_MEM_REGISTERRND_ECO_LOW_S))
|
|
|
-#define DSPI_MEM_REGISTERRND_ECO_LOW_V 0xFFFFFFFF
|
|
|
-#define DSPI_MEM_REGISTERRND_ECO_LOW_S 0
|
|
|
-
|
|
|
-#define DSPI_MEM_DATE_REG (DR_REG_DSPI_MEM_BASE + 0x3FC)
|
|
|
-/* DSPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2211210 ; */
|
|
|
-/*description: SPI0 register version..*/
|
|
|
-#define DSPI_MEM_DATE 0x0FFFFFFF
|
|
|
-#define DSPI_MEM_DATE_M ((DSPI_MEM_DATE_V)<<(DSPI_MEM_DATE_S))
|
|
|
-#define DSPI_MEM_DATE_V 0xFFFFFFF
|
|
|
-#define DSPI_MEM_DATE_S 0
|
|
|
-
|
|
|
-
|
|
|
-#ifdef __cplusplus
|
|
|
-}
|
|
|
-#endif
|
|
|
-
|
|
|
-
|
|
|
-
|
|
|
-#endif /*_SOC_DSPI_MEM_REG_H_ */
|
Armando