Merge branch 'feature/add_esp32s3_bootloader_ld_file' into 'master'

move part of esp32-s3 codes to master (bootloader linker, esp32s3 empty componnet)

See merge request espressif/esp-idf!9608

components/bootloader/CMakeLists.txt

@@ -13,9 +13,9 @@ if(NOT CONFIG_SECURE_BOOT)
 endif()
 
 esptool_py_custom_target(bootloader-flash bootloader "bootloader")
-esptool_py_flash_target_image(bootloader-flash bootloader "0x1000" "${BOOTLOADER_BUILD_DIR}/bootloader.bin")
+esptool_py_flash_target_image(bootloader-flash bootloader ${CONFIG_BOOTLOADER_OFFSET_IN_FLASH} "${BOOTLOADER_BUILD_DIR}/bootloader.bin")
 
 # Also attach an image to the project flash target
 if(NOT CONFIG_SECURE_BOOT)
-    esptool_py_flash_target_image(flash bootloader "0x1000" "${BOOTLOADER_BUILD_DIR}/bootloader.bin")
+    esptool_py_flash_target_image(flash bootloader ${CONFIG_BOOTLOADER_OFFSET_IN_FLASH} "${BOOTLOADER_BUILD_DIR}/bootloader.bin")
 endif()

components/bootloader/Kconfig.projbuild

@@ -1,5 +1,14 @@
 menu "Bootloader config"
 
+    config BOOTLOADER_OFFSET_IN_FLASH
+        hex
+        default 0x1000 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2
+        default 0x0
+        help
+            Offset address that 2nd bootloader will be flashed to.
+            The value is determined by the ROM bootloader.
+            It's not configurable in ESP-IDF.
+
     choice BOOTLOADER_COMPILER_OPTIMIZATION
         prompt "Bootloader optimization Level"
         default BOOTLOADER_COMPILER_OPTIMIZATION_SIZE

components/bootloader/project_include.cmake

@@ -1,4 +1,4 @@
-set(BOOTLOADER_OFFSET 0x1000)
+set(BOOTLOADER_OFFSET CONFIG_BOOTLOADER_OFFSET_IN_FLASH)
 
 # Do not generate flash file when building bootloader
 if(BOOTLOADER_BUILD OR NOT CONFIG_APP_BUILD_BOOTLOADER)

components/bootloader/subproject/main/ld/esp32s3/bootloader.ld

@@ -0,0 +1,183 @@
+/** Simplified memory map for the bootloader.
+ *  Make sure the bootloader can load into main memory without overwriting itself.
+ *  We put 2nd bootloader in the high address space (before ROM stack/data/bss).
+ *  See memory usage for ROM bootloader at the end of this file.
+ */
+
+MEMORY
+{
+  iram_seg (RWX) :                  org = 0x403B8000, len = 0x4000
+  iram_loader_seg (RWX) :           org = 0x403BC000, len = 0x4000
+  dram_seg (RW) :                   org = 0x3FCD0000, len = 0x4000
+}
+
+/* Default entry point: */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+
+  .iram_loader.text :
+  {
+    . = ALIGN (16);
+    _loader_text_start = ABSOLUTE(.);
+    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+     *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
+    *liblog.a:(.literal .text .literal.* .text.*)
+    *libgcc.a:(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_clock.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_common.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_efuse_esp32s3.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_signatures.*(.literal .text .literal.* .text.*)
+    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
+    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
+    *libsoc.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libsoc.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libefuse.a:*.*(.literal .text .literal.* .text.*)
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _loader_text_end = ABSOLUTE(.);
+  } > iram_loader_seg
+
+  .iram.text :
+  {
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+  } > iram_seg
+
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _dram_start = ABSOLUTE(.);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.data :
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+    _data_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame)
+    . = (. + 3) & ~ 3;
+    /* C++ constructor and destructor tables, properly ordered: */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+	  /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _dram_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .iram.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram .iram.*) /* catch stray IRAM_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } > iram_seg
+
+}
+
+
+/**
+ *  Appendix: Memory Usage of ROM bootloader
+ *
+ *  +--------+--------------+------+ 0x3FCD_8000
+ *  |        ^              |
+ *  |        |              |
+ *  |        | data/bss     |
+ *  |        |              |
+ *  |        v              |
+ *  +------------------------------+ 0x3FCE_9910
+ *  |        ^              |
+ *  |        |              |
+ *  |        | stack (pro)  |
+ *  |        |              |
+ *  |        v              |
+ *  +------------------------------+ 0x3FCE_B910
+ *  |        ^              |
+ *  |        |              |
+ *  |        | stack (app)  |
+ *  |        |              |
+ *  |        v              |
+ *  +--------+--------------+------+ 0x3FCE_D910
+ */

components/bootloader/subproject/main/ld/esp32s3/bootloader.rom.ld

@@ -0,0 +1,6 @@
+/**
+ * ESP32S3 ROM address table
+ * Generated for ROM with MD5sum: d20fb231463ce337432b1fa9cba0b3c9
+ */
+
+PROVIDE ( ets_update_cpu_frequency = 0x40043164 );

components/bootloader_support/include/esp_flash_partitions.h

@@ -44,7 +44,7 @@ extern "C" {
 
 /* Pre-partition table fixed flash offsets */
 #define ESP_BOOTLOADER_DIGEST_OFFSET 0x0
-#define ESP_BOOTLOADER_OFFSET 0x1000 /* Offset of bootloader image. Has matching value in bootloader KConfig.projbuild file. */
+#define ESP_BOOTLOADER_OFFSET CONFIG_BOOTLOADER_OFFSET_IN_FLASH  /* Offset of bootloader image. Has matching value in bootloader KConfig.projbuild file. */
 #define ESP_PARTITION_TABLE_OFFSET CONFIG_PARTITION_TABLE_OFFSET /* Offset of partition table. Backwards-compatible name.*/
 
 #define ESP_PARTITION_TABLE_MAX_LEN 0xC00 /* Maximum length of partition table data */

components/bootloader_support/src/bootloader_clock.c

@@ -69,19 +69,11 @@ void bootloader_clock_configure(void)
         */
     }
 
-    /* TODO: move the clock option into esp_system, so that this doesn't have
-     * to continue:
-     */
-#if CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
+#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
     if (!rtc_clk_32k_enabled()) {
-        rtc_clk_32k_bootstrap(CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES);
+        rtc_clk_32k_bootstrap(CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES);
     }
-#endif
-#if CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS
-    if (!rtc_clk_32k_enabled()) {
-        rtc_clk_32k_bootstrap(0);
-    }
-#endif
+#endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
 }
 
 #ifdef BOOTLOADER_BUILD

components/esp32/CMakeLists.txt

@@ -62,11 +62,6 @@ else()
     target_link_libraries(${COMPONENT_LIB} PUBLIC gcc)
     target_link_libraries(${COMPONENT_LIB} INTERFACE "-u call_user_start_cpu0")
 
-    #ld_include_panic_highint_hdl is added as an undefined symbol because otherwise the
-    #linker will ignore panic_highint_hdl.S as it has no other files depending on any
-    #symbols in it.
-    target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_panic_highint_hdl")
-
     idf_build_get_property(config_dir CONFIG_DIR)
     # Preprocess esp32.ld linker script to include configuration, becomes esp32_out.ld
     set(LD_DIR ${CMAKE_CURRENT_SOURCE_DIR}/ld)

components/esp32/Kconfig

@@ -558,6 +558,7 @@ menu "ESP32-specific"
             bool "Internal 150kHz RC oscillator"
         config ESP32_RTC_CLK_SRC_EXT_CRYS
             bool "External 32kHz crystal"
+            select ESP_SYSTEM_RTC_EXT_XTAL
         config ESP32_RTC_CLK_SRC_EXT_OSC
             bool "External 32kHz oscillator at 32K_XP pin"
         config ESP32_RTC_CLK_SRC_INT_8MD256
@@ -609,23 +610,6 @@ menu "ESP32-specific"
             Increase this option if the 32k crystal oscillator
             does not start and switches to internal RC.
 
-    config ESP32_RTC_XTAL_BOOTSTRAP_CYCLES
-        int "Bootstrap cycles for external 32kHz crystal"
-        depends on ESP32_RTC_CLK_SRC_EXT_CRYS
-        default 5
-        range 0 32768
-        help
-            To reduce the startup time of an external RTC crystal,
-            we bootstrap it with a 32kHz square wave for a fixed number of cycles.
-            Setting 0 will disable bootstrapping (if disabled, the crystal may take
-            longer to start up or fail to oscillate under some conditions).
-
-            If this value is too high, a faulty crystal may initially start and then fail.
-            If this value is too low, an otherwise good crystal may not start.
-
-            To accurately determine if the crystal has started,
-            set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000).
-
     config ESP32_DEEP_SLEEP_WAKEUP_DELAY
         int "Extra delay in deep sleep wake stub (in us)"
         default 2000

components/esp32s2/CMakeLists.txt

@@ -58,11 +58,6 @@ else()
     target_link_libraries(${COMPONENT_LIB} PUBLIC gcc)
     target_link_libraries(${COMPONENT_LIB} INTERFACE "-u call_user_start_cpu0")
 
-    #ld_include_panic_highint_hdl is added as an undefined symbol because otherwise the
-    #linker will ignore panic_highint_hdl.S as it has no other files depending on any
-    #symbols in it.
-    target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_panic_highint_hdl")
-
     idf_build_get_property(config_dir CONFIG_DIR)
     # Preprocess esp32s2.ld linker script to include configuration, becomes esp32s2_out.ld
     set(LD_DIR ${CMAKE_CURRENT_SOURCE_DIR}/ld)

components/esp32s2/Kconfig

@@ -427,6 +427,7 @@ menu "ESP32S2-specific"
             bool "Internal 90kHz RC oscillator"
         config ESP32S2_RTC_CLK_SRC_EXT_CRYS
             bool "External 32kHz crystal"
+            select ESP_SYSTEM_RTC_EXT_XTAL
         config ESP32S2_RTC_CLK_SRC_EXT_OSC
             bool "External 32kHz oscillator at 32K_XP pin"
         config ESP32S2_RTC_CLK_SRC_INT_8MD256
@@ -545,19 +546,6 @@ menu "Power Management"
             If disabled, DFS will not be active until the application
             configures it using esp_pm_configure function.
 
-    config PM_USE_RTC_TIMER_REF
-        bool "Use RTC timer to prevent time drift (EXPERIMENTAL)"
-        depends on PM_ENABLE && (ESP32S2_TIME_SYSCALL_USE_RTC || ESP32S2_TIME_SYSCALL_USE_RTC_FRC1)
-        default n
-        help
-            When APB clock frequency changes, high-resolution timer (esp_timer)
-            scale and base value need to be adjusted. Each adjustment may cause
-            small error, and over time such small errors may cause time drift.
-            If this option is enabled, RTC timer will be used as a reference to
-            compensate for the drift.
-            It is recommended that this option is only used if 32k XTAL is selected
-            as RTC clock source.
-
     config PM_PROFILING
         bool "Enable profiling counters for PM locks"
         depends on PM_ENABLE

components/esp32s3/CMakeLists.txt

@@ -0,0 +1,4 @@
+idf_build_get_property(target IDF_TARGET)
+if(NOT "${target}" STREQUAL "esp32s3")
+    return()
+endif()

components/esp32s3/Kconfig

@@ -0,0 +1,585 @@
+menu "ESP32S3-Specific"
+    visible if IDF_TARGET_ESP32S3
+
+    choice ESP32S3_DEFAULT_CPU_FREQ_MHZ
+        prompt "CPU frequency"
+        default ESP32S3_DEFAULT_CPU_FREQ_40 if IDF_ENV_FPGA
+        default ESP32S3_DEFAULT_CPU_FREQ_160 if !IDF_ENV_FPGA
+        help
+            CPU frequency to be set on application startup.
+
+        config ESP32S3_DEFAULT_CPU_FREQ_40
+            bool "40 MHz"
+            depends on IDF_ENV_FPGA
+        config ESP32S3_DEFAULT_CPU_FREQ_80
+            bool "80 MHz"
+        config ESP32S3_DEFAULT_CPU_FREQ_160
+            bool "160 MHz"
+        config ESP32S3_DEFAULT_CPU_FREQ_240
+            bool "240 MHz"
+    endchoice
+
+    config ESP32S3_DEFAULT_CPU_FREQ_MHZ
+        int
+        default 40 if ESP32S3_DEFAULT_CPU_FREQ_40
+        default 80 if ESP32S3_DEFAULT_CPU_FREQ_80
+        default 160 if ESP32S3_DEFAULT_CPU_FREQ_160
+        default 240 if ESP32S3_DEFAULT_CPU_FREQ_240
+
+    menu "Cache config"
+
+        choice ESP32S3_INSTRUCTION_CACHE_SIZE
+            prompt "Instruction cache size"
+            default ESP32S3_INSTRUCTION_CACHE_16KB
+            help
+                Instruction cache size to be set on application startup.
+                If you use 16KB instruction cache rather than 32KB instruction cache,
+                then the other 16KB will be managed by heap allocator.
+
+            config ESP32S3_INSTRUCTION_CACHE_16KB
+                bool "16KB"
+            config ESP32S3_INSTRUCTION_CACHE_32KB
+                bool "32KB"
+        endchoice
+
+        config ESP32S3_INSTRUCTION_CACHE_SIZE
+            hex
+            default 0x4000 if ESP32S3_INSTRUCTION_CACHE_16KB
+            default 0x8000 if ESP32S3_INSTRUCTION_CACHE_32KB
+
+        choice ESP32S3_ICACHE_ASSOCIATED_WAYS
+            prompt "Instruction cache associated ways"
+            default ESP32S3_INSTRUCTION_CACHE_8WAYS
+            help
+                Instruction cache associated ways to be set on application startup.
+
+            config ESP32S3_INSTRUCTION_CACHE_4WAYS
+                bool "4 ways"
+            config ESP32S3_INSTRUCTION_CACHE_8WAYS
+                bool "8 ways"
+        endchoice
+
+        config ESP32S3_ICACHE_ASSOCIATED_WAYS
+            int
+            default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS
+            default 8 if ESP32S3_INSTRUCTION_CACHE_8WAYS
+
+        choice ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
+            prompt "Instruction cache line size"
+            default ESP32S3_INSTRUCTION_CACHE_LINE_32B
+            help
+                Instruction cache line size to be set on application startup.
+
+            config ESP32S3_INSTRUCTION_CACHE_LINE_16B
+                bool "16 Bytes"
+                depends on ESP32S3_INSTRUCTION_CACHE_16KB
+            config ESP32S3_INSTRUCTION_CACHE_LINE_32B
+                bool "32 Bytes"
+        endchoice
+
+        config ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
+            int
+            default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B
+            default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B
+
+        config ESP32S3_INSTRUCTION_CACHE_WRAP
+            bool "Enable instruction cache wrap mode"
+            default "n"
+            help
+                If enabled, instruction cache will use wrap mode to read spi flash or spi ram.
+                The wrap length equals to ESP32S3_INSTRUCTION_CACHE_LINE_SIZE.
+                However, it depends on complex conditions.
+
+        choice ESP32S3_DATA_CACHE_SIZE
+            prompt "Data cache size"
+            default ESP32S3_DATA_CACHE_32KB
+            help
+                Data cache size to be set on application startup.
+                If you use 32KB data cache rather than 64KB data cache,
+                the other 32KB will be added to the heap.
+
+            config ESP32S3_DATA_CACHE_16KB
+                bool "16KB"
+            config ESP32S3_DATA_CACHE_32KB
+                bool "32KB"
+            config ESP32S3_DATA_CACHE_64KB
+                bool "64KB"
+        endchoice
+
+        config ESP32S3_DATA_CACHE_SIZE
+            hex
+            default 0x4000 if ESP32S3_DATA_CACHE_16KB
+            default 0x8000 if ESP32S3_DATA_CACHE_32KB
+            default 0x10000 if ESP32S3_DATA_CACHE_64KB
+
+        choice ESP32S3_DCACHE_ASSOCIATED_WAYS
+            prompt "Data cache associated ways"
+            default ESP32S3_DATA_CACHE_8WAYS
+            help
+                Data cache associated ways to be set on application startup.
+
+            config ESP32S3_DATA_CACHE_4WAYS
+                bool "4 ways"
+            config ESP32S3_DATA_CACHE_8WAYS
+                bool "8 ways"
+        endchoice
+
+        config ESP32S3_DCACHE_ASSOCIATED_WAYS
+            int
+            default 4 if ESP32S3_DATA_CACHE_4WAYS
+            default 8 if ESP32S3_DATA_CACHE_8WAYS
+
+        choice ESP32S3_DATA_CACHE_LINE_SIZE
+            prompt "Data cache line size"
+            default ESP32S3_DATA_CACHE_LINE_32B
+            help
+                Data cache line size to be set on application startup.
+
+            config ESP32S3_DATA_CACHE_LINE_16B
+                bool "16 Bytes"
+                depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB
+            config ESP32S3_DATA_CACHE_LINE_32B
+                bool "32 Bytes"
+        endchoice
+
+        config ESP32S3_DATA_CACHE_LINE_SIZE
+            int
+            default 16 if ESP32S3_DATA_CACHE_LINE_16B
+            default 32 if ESP32S3_DATA_CACHE_LINE_32B
+
+        config ESP32S3_DATA_CACHE_WRAP
+            bool "Enable data cache wrap mode"
+            default "n"
+            help
+                If enabled, data cache will use wrap mode to read spi flash or spi ram.
+                The wrap length equals to ESP32S3_DATA_CACHE_LINE_SIZE.
+                However, it depends on complex conditions.
+
+    endmenu  # Cache config
+
+    # Hint: to support SPIRAM across multiple chips, check CONFIG_SPIRAM instead
+    config ESP32S3_SPIRAM_SUPPORT
+        bool "Support for external, SPI-connected RAM"
+        default "n"
+        select SPIRAM
+        help
+            This enables support for an external SPI RAM chip, connected in parallel with the
+            main SPI flash chip.
+
+    menu "SPI RAM config"
+        depends on ESP32S3_SPIRAM_SUPPORT
+
+        choice SPIRAM_TYPE
+            prompt "Type of SPI RAM chip in use"
+            default SPIRAM_TYPE_ESPPSRAM32
+
+            config SPIRAM_TYPE_ESPPSRAM32
+                bool "ESP-PSRAM32 or IS25WP032"
+            config SPIRAM_TYPE_ESPPSRAM64
+                bool "ESP-PSRAM64 or LY68L6400"
+        endchoice
+
+        config SPIRAM_SIZE
+            int
+            default 4194304 if SPIRAM_TYPE_ESPPSRAM32
+            default 8388608 if SPIRAM_TYPE_ESPPSRAM64
+            default 0
+
+        menu "PSRAM Clock and CS IO for ESP32S3"
+            depends on ESP32S3_SPIRAM_SUPPORT
+            config DEFAULT_PSRAM_CLK_IO
+                int "PSRAM CLK IO number"
+                range 0 33
+                default 30
+                help
+                    The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design.
+
+            config DEFAULT_PSRAM_CS_IO
+                int "PSRAM CS IO number"
+                range 0 33
+                default 26
+                help
+                    The PSRAM CS IO can be any unused GPIO, please refer to your hardware design.
+        endmenu
+
+        config SPIRAM_SPIWP_SD3_PIN
+            int "SPI PSRAM WP(SD3) Pin when customizing pins via eFuse (read help)"
+            depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT
+            range 0 33
+            default 28
+            help
+                This value is ignored unless flash mode is set to DIO or DOUT and the SPI flash pins have been
+                overridden by setting the eFuses SPI_PAD_CONFIG_xxx.
+
+                Different from esp32 chip, on esp32-s3, the WP pin would also be defined in efuse.
+                This value would only be used if the WP pin recorded in efuse SPI_PAD_CONFIG_xxx is invalid.
+
+                When flash mode is set to QIO or QOUT,
+                the PSRAM WP pin will be set as the value configured in bootloader.
+
+        config SPIRAM_FETCH_INSTRUCTIONS
+            bool "Cache fetch instructions from SPI RAM"
+            default n
+            help
+                If enabled, instruction in flash will be copied into SPIRAM.
+                If SPIRAM_RODATA also enabled, you can run the instruction when erasing or programming the flash.
+
+        config SPIRAM_RODATA
+            bool "Cache load read only data from SPI RAM"
+            default n
+            help
+                If enabled, rodata in flash will be copied into SPIRAM.
+                If SPIRAM_FETCH_INSTRUCTIONS is also enabled,
+                you can run the instruction when erasing or programming the flash.
+
+        choice SPIRAM_SPEED
+            prompt "Set RAM clock speed"
+            default SPIRAM_SPEED_40M
+            help
+                Select the speed for the SPI RAM chip.
+                If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
+
+                1. Flash SPI running at 40Mhz and RAM SPI running at 40Mhz
+                2. Flash SPI running at 80Mhz and RAM SPI running at 40Mhz
+                3. Flash SPI running at 80Mhz and RAM SPI running at 80Mhz
+
+            config SPIRAM_SPEED_80M
+                bool "80MHz clock speed"
+            config SPIRAM_SPEED_40M
+                bool "40Mhz clock speed"
+            config SPIRAM_SPEED_26M
+                bool "26Mhz clock speed"
+            config SPIRAM_SPEED_20M
+                bool "20Mhz clock speed"
+        endchoice
+
+        # insert non-chip-specific items here
+        source "$IDF_PATH/components/esp_common/Kconfig.spiram.common"
+
+    endmenu
+
+    config ESP32S3_MEMMAP_TRACEMEM
+        bool
+        default "n"
+
+    config ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
+        bool
+        default "n"
+
+    config ESP32S3_TRAX
+        bool "Use TRAX tracing feature"
+        default "n"
+        select ESP32S3_MEMMAP_TRACEMEM
+        help
+            The esp32-s3 contains a feature which allows you to trace the execution path the processor
+            has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
+            of memory that can't be used for general purposes anymore. Disable this if you do not know
+            what this is.
+
+    config ESP32S3_TRAX_TWOBANKS
+        bool "Reserve memory for tracing both pro as well as app cpu execution"
+        default "n"
+        depends on ESP32S3_TRAX && !FREERTOS_UNICORE
+        select ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
+        help
+            The esp32-s3 contains a feature which allows you to trace the execution path the processor
+            has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
+            of memory that can't be used for general purposes anymore. Disable this if you do not know
+            what this is.
+
+    config ESP32S3_TRACEMEM_RESERVE_DRAM
+        hex
+        default 0x8000 if ESP32S3_MEMMAP_TRACEMEM && ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
+        default 0x4000 if ESP32S3_MEMMAP_TRACEMEM && !ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
+        default 0x0
+
+
+    choice ESP32S3_UNIVERSAL_MAC_ADDRESSES
+        bool "Number of universally administered (by IEEE) MAC address"
+        default ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO
+        help
+            Configure the number of universally administered (by IEEE) MAC addresses.
+            During initialization, MAC addresses for each network interface are generated or derived from a
+            single base MAC address.
+            If the number of universal MAC addresses is Two, all interfaces (WiFi station, WiFi softap) receive a
+            universally administered MAC address. They are generated sequentially by adding 0, and 1 (respectively)
+            to the final octet of the base MAC address. If the number of universal MAC addresses is one,
+            only WiFi station receives a universally administered MAC address.
+            It's generated by adding 0 to the base MAC address.
+            The WiFi softap receives local MAC addresses. It's derived from the universal WiFi station MAC addresses.
+            When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
+            a custom universal MAC address range, the correct setting will depend on the allocation of MAC
+            addresses in this range (either 1 or 2 per device.)
+
+        config ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO
+            bool "Two"
+            select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
+            select ESP_MAC_ADDR_UNIVERSE_BT
+        config ESP32S3_UNIVERSAL_MAC_ADDRESSES_THREE
+            bool "Three"
+            select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
+            select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
+            select ESP_MAC_ADDR_UNIVERSE_BT
+    endchoice
+
+    config ESP32S3_UNIVERSAL_MAC_ADDRESSES
+        int
+        default 2 if ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO
+        default 3 if ESP32S3_UNIVERSAL_MAC_ADDRESSES_THREE
+
+    config ESP_MAC_ADDR_UNIVERSE_BT_OFFSET
+        int
+        default 2 if ESP32S3_UNIVERSAL_MAC_ADDRESSES_THREE
+        default 1 if ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO
+
+    config ESP32S3_ULP_COPROC_ENABLED
+        bool "Enable Ultra Low Power (ULP) Coprocessor"
+        default "n"
+        help
+            Set to 'y' if you plan to load a firmware for the coprocessor.
+
+            If this option is enabled, further coprocessor configuration will appear in the Components menu.
+
+    config ESP32S3_ULP_COPROC_RESERVE_MEM
+        int
+        prompt "RTC slow memory reserved for coprocessor" if ESP32S3_ULP_COPROC_ENABLED
+        default 512 if ESP32S3_ULP_COPROC_ENABLED
+        range 32 8192 if ESP32S3_ULP_COPROC_ENABLED
+        default 0 if !ESP32S3_ULP_COPROC_ENABLED
+        range 0 0 if !ESP32S3_ULP_COPROC_ENABLED
+        help
+            Bytes of memory to reserve for ULP coprocessor firmware & data.
+
+            Data is reserved at the beginning of RTC slow memory.
+
+    config ESP32S3_DEBUG_OCDAWARE
+        bool "Make exception and panic handlers JTAG/OCD aware"
+        default y
+        select FREERTOS_DEBUG_OCDAWARE
+        help
+            The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and
+            instead of panicking, have the debugger stop on the offending instruction.
+
+    config ESP32S3_DEBUG_STUBS_ENABLE
+        bool "OpenOCD debug stubs"
+        default COMPILER_OPTIMIZATION_LEVEL_DEBUG
+        depends on !ESP32S3_TRAX
+        help
+            Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging,
+            e.g. GCOV data dump.
+
+    config ESP32S3_BROWNOUT_DET
+        bool "Hardware brownout detect & reset"
+        default y
+        help
+            The ESP32-S3 has a built-in brownout detector which can detect if the voltage is lower than
+            a specific value. If this happens, it will reset the chip in order to prevent unintended
+            behaviour.
+
+    choice ESP32S3_BROWNOUT_DET_LVL_SEL
+        prompt "Brownout voltage level"
+        depends on ESP32S3_BROWNOUT_DET
+        default ESP32S3_BROWNOUT_DET_LVL_SEL_7
+        help
+            The brownout detector will reset the chip when the supply voltage is approximately
+            below this level. Note that there may be some variation of brownout voltage level
+            between each ESP3-S3 chip.
+
+            #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
+            #of the brownout threshold levels.
+        config ESP32S3_BROWNOUT_DET_LVL_SEL_7
+            bool "2.44V"
+        config ESP32S3_BROWNOUT_DET_LVL_SEL_6
+            bool "2.56V"
+        config ESP32S3_BROWNOUT_DET_LVL_SEL_5
+            bool "2.67V"
+        config ESP32S3_BROWNOUT_DET_LVL_SEL_4
+            bool "2.84V"
+        config ESP32S3_BROWNOUT_DET_LVL_SEL_3
+            bool "2.98V"
+        config ESP32S3_BROWNOUT_DET_LVL_SEL_2
+            bool "3.19V"
+        config ESP32S3_BROWNOUT_DET_LVL_SEL_1
+            bool "3.30V"
+    endchoice
+
+    config ESP32S3_BROWNOUT_DET_LVL
+        int
+        default 1 if ESP32S3_BROWNOUT_DET_LVL_SEL_1
+        default 2 if ESP32S3_BROWNOUT_DET_LVL_SEL_2
+        default 3 if ESP32S3_BROWNOUT_DET_LVL_SEL_3
+        default 4 if ESP32S3_BROWNOUT_DET_LVL_SEL_4
+        default 5 if ESP32S3_BROWNOUT_DET_LVL_SEL_5
+        default 6 if ESP32S3_BROWNOUT_DET_LVL_SEL_6
+        default 7 if ESP32S3_BROWNOUT_DET_LVL_SEL_7
+
+
+        # Note about the use of "FRC1" name: currently FRC1 timer is not used for
+        # high resolution timekeeping anymore. Instead the esp_timer API, implemented
+        # using FRC2 timer, is used.
+        # FRC1 name in the option name is kept for compatibility.
+    choice ESP32S3_TIME_SYSCALL
+        prompt "Timers used for gettimeofday function"
+        default ESP32S3_TIME_SYSCALL_USE_RTC_FRC1
+        help
+            This setting defines which hardware timers are used to
+            implement 'gettimeofday' and 'time' functions in C library.
+
+            - If both high-resolution and RTC timers are used, timekeeping will
+              continue in deep sleep. Time will be reported at 1 microsecond
+              resolution. This is the default, and the recommended option.
+            - If only high-resolution timer is used, gettimeofday will
+              provide time at microsecond resolution.
+              Time will not be preserved when going into deep sleep mode.
+            - If only RTC timer is used, timekeeping will continue in
+              deep sleep, but time will be measured at 6.(6) microsecond
+              resolution. Also the gettimeofday function itself may take
+              longer to run.
+            - If no timers are used, gettimeofday and time functions
+              return -1 and set errno to ENOSYS.
+            - When RTC is used for timekeeping, two RTC_STORE registers are
+              used to keep time in deep sleep mode.
+
+        config ESP32S3_TIME_SYSCALL_USE_RTC_FRC1
+            bool "RTC and high-resolution timer"
+        config ESP32S3_TIME_SYSCALL_USE_RTC
+            bool "RTC"
+        config ESP32S3_TIME_SYSCALL_USE_FRC1
+            bool "High-resolution timer"
+        config ESP32S3_TIME_SYSCALL_USE_NONE
+            bool "None"
+    endchoice
+
+    choice ESP32S3_RTC_CLK_SRC
+        prompt "RTC clock source"
+        default ESP32S3_RTC_CLK_SRC_INT_RC
+        help
+            Choose which clock is used as RTC clock source.
+
+        config ESP32S3_RTC_CLK_SRC_INT_RC
+            bool "Internal 150kHz RC oscillator"
+        config ESP32S3_RTC_CLK_SRC_EXT_CRYS
+            bool "External 32kHz crystal"
+            select ESP_SYSTEM_RTC_EXT_XTAL
+        config ESP32S3_RTC_CLK_SRC_EXT_OSC
+            bool "External 32kHz oscillator at 32K_XP pin"
+        config ESP32S3_RTC_CLK_SRC_INT_8MD256
+            bool "Internal 8MHz oscillator, divided by 256 (~32kHz)"
+    endchoice
+
+    config ESP32S3_RTC_CLK_CAL_CYCLES
+        int "Number of cycles for RTC_SLOW_CLK calibration"
+        default 3000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS
+        default 1024 if ESP32S3_RTC_CLK_SRC_INT_RC
+        range 0 125000
+        help
+            When the startup code initializes RTC_SLOW_CLK, it can perform
+            calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
+            frequency. This option sets the number of RTC_SLOW_CLK cycles measured
+            by the calibration routine. Higher numbers increase calibration
+            precision, which may be important for applications which spend a lot of
+            time in deep sleep. Lower numbers reduce startup time.
+
+            When this option is set to 0, clock calibration will not be performed at
+            startup, and approximate clock frequencies will be assumed:
+
+            - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
+            - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
+              In case more value will help improve the definition of the launch of the crystal.
+              If the crystal could not start, it will be switched to internal RC.
+
+    config ESP32S3_NO_BLOBS
+        bool "No Binary Blobs"
+        depends on !BT_ENABLED
+        default n
+        help
+            If enabled, this disables the linking of binary libraries in the application build. Note
+            that after enabling this Wi-Fi/Bluetooth will not work.
+
+    config ESP32S3_RTCDATA_IN_FAST_MEM
+        bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
+        default n
+        help
+            This option allows to place .rtc_data and .rtc_rodata sections into
+            RTC fast memory segment to free the slow memory region for ULP programs.
+
+    config ESP32S3_USE_FIXED_STATIC_RAM_SIZE
+        bool "Use fixed static RAM size"
+        default n
+        help
+            If this option is disabled, the DRAM part of the heap starts right after the .bss section,
+            within the dram0_0 region. As a result, adding or removing some static variables
+            will change the available heap size.
+
+            If this option is enabled, the DRAM part of the heap starts right after the dram0_0 region,
+            where its length is set with ESP32S3_FIXED_STATIC_RAM_SIZE
+
+    config ESP32S3_FIXED_STATIC_RAM_SIZE
+        hex "Fixed Static RAM size"
+        default 0x10000
+        range 0 0x34000
+        depends on ESP32S3_USE_FIXED_STATIC_RAM_SIZE
+        help
+            RAM size dedicated for static variables (.data & .bss sections).
+
+    config ESP32S3_ALLOW_RTC_FAST_MEM_AS_HEAP
+        bool "Enable RTC fast memory for dynamic allocations"
+        depends on !ESP32S3_MEMPROT_FEATURE
+        default y
+        help
+            This config option allows to add RTC fast memory region to system heap with capability
+            similar to that of DRAM region but without DMA. This memory will be consumed first per
+            heap initialization order by early startup services and scheduler related code. Speed
+            wise RTC fast memory operates on APB clock and hence does not have much performance impact.
+
+endmenu  # ESP32S3-Specific
+
+menu "Power Management"
+    config PM_ENABLE
+        bool "Support for power management"
+        default n
+        help
+            If enabled, application is compiled with support for power management.
+            This option has run-time overhead (increased interrupt latency,
+            longer time to enter idle state), and it also reduces accuracy of
+            RTOS ticks and timers used for timekeeping.
+            Enable this option if application uses power management APIs.
+
+    config PM_DFS_INIT_AUTO
+        bool "Enable dynamic frequency scaling (DFS) at startup"
+        depends on PM_ENABLE
+        default n
+        help
+            If enabled, startup code configures dynamic frequency scaling.
+            Max CPU frequency is set to CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ setting,
+            min frequency is set to XTAL frequency.
+            If disabled, DFS will not be active until the application
+            configures it using esp_pm_configure function.
+
+    config PM_PROFILING
+        bool "Enable profiling counters for PM locks"
+        depends on PM_ENABLE
+        default n
+        help
+            If enabled, esp_pm_* functions will keep track of the amount of time
+            each of the power management locks has been held, and esp_pm_dump_locks
+            function will print this information.
+            This feature can be used to analyze which locks are preventing the chip
+            from going into a lower power state, and see what time the chip spends
+            in each power saving mode. This feature does incur some run-time
+            overhead, so should typically be disabled in production builds.
+
+    config PM_TRACE
+        bool "Enable debug tracing of PM using GPIOs"
+        depends on PM_ENABLE
+        default n
+        help
+            If enabled, some GPIOs will be used to signal events such as RTOS ticks,
+            frequency switching, entry/exit from idle state. Refer to pm_trace.c
+            file for the list of GPIOs.
+            This feature is intended to be used when analyzing/debugging behavior
+            of power management implementation, and should be kept disabled in
+            applications.
+
+
+endmenu # "Power Management"

components/esp32s3/README.md

@@ -0,0 +1,7 @@
+# ESP32-S3 component
+
+This directory contains support for the upcoming ESP32-S3 SoC. This code is **still work in progress and not intended for public use**.
+
+Please follow announcements on [espressif.com](https://www.espressif.com/) and [esp32.com](https://esp32.com/) to be informed about the ESP32-S3 SoC.
+
+*This note will be removed once the ESP32-S3 initial support is ready.*

components/esp32s3/component.mk

@@ -0,0 +1,5 @@
+#
+# Component Makefile
+#
+# ESP32-S3 is not supported in GNU Make build system
+COMPONENT_CONFIG_ONLY := 1

components/esp_system/Kconfig

@@ -38,4 +38,28 @@ menu "ESP System Settings"
         help
             Only initialize and use the main core.
 
+    config ESP_SYSTEM_RTC_EXT_XTAL
+        # This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option
+        # e.g. It will be selected on when ESP32_RTC_CLK_SRC_EXT_CRYS is on
+        bool
+        default n
+
+    config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES
+        int "Bootstrap cycles for external 32kHz crystal"
+        depends on ESP_SYSTEM_RTC_EXT_XTAL
+        default 5 if IDF_TARGET_ESP32
+        default 0
+        range 0 32768
+        help
+            To reduce the startup time of an external RTC crystal,
+            we bootstrap it with a 32kHz square wave for a fixed number of cycles.
+            Setting 0 will disable bootstrapping (if disabled, the crystal may take
+            longer to start up or fail to oscillate under some conditions).
+
+            If this value is too high, a faulty crystal may initially start and then fail.
+            If this value is too low, an otherwise good crystal may not start.
+
+            To accurately determine if the crystal has started,
+            set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000).
+
 endmenu  # ESP System Settings

components/esp_system/port/esp32/CMakeLists.txt

@@ -2,3 +2,8 @@ set(srcs "dport_panic_highint_hdl.S" "clk.c" "reset_reason.c")
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" ${srcs})
 
 target_sources(${COMPONENT_LIB} PRIVATE ${srcs})
+
+#ld_include_panic_highint_hdl is added as an undefined symbol because otherwise the
+#linker will ignore panic_highint_hdl.S as it has no other files depending on any
+#symbols in it.
+set_property(TARGET ${COMPONENT_LIB} APPEND PROPERTY INTERFACE_LINK_LIBRARIES "-u ld_include_panic_highint_hdl")

components/esp_system/port/esp32s2/CMakeLists.txt

@@ -5,3 +5,8 @@ target_sources(${COMPONENT_LIB} PRIVATE ${srcs})
 if(CONFIG_ESP_CONSOLE_USB_CDC)
     target_sources(${COMPONENT_LIB} PRIVATE "${CMAKE_CURRENT_LIST_DIR}/usb_console.c")
 endif()
+
+#ld_include_panic_highint_hdl is added as an undefined symbol because otherwise the
+#linker will ignore panic_highint_hdl.S as it has no other files depending on any
+#symbols in it.
+set_property(TARGET ${COMPONENT_LIB} APPEND PROPERTY INTERFACE_LINK_LIBRARIES "-u ld_include_panic_highint_hdl")

components/esp_system/port/esp32s2/dport_panic_highint_hdl.S

@@ -71,16 +71,6 @@ xt_highint4:
     movi    a0, PANIC_RSN_CACHEERR
     j 9f
 1:
-#if CONFIG_INT_WDT_CHECK_CPU1
-    /* Check if the cause is the app cpu failing to tick.*/
-    movi    a0, int_wdt_app_cpu_ticked
-    l32i    a0, a0, 0
-    bnez    a0, 2f
-    /* It is. Modify cause. */
-    movi    a0,PANIC_RSN_INTWDT_CPU1
-    j 9f
-2:
-#endif
     /* Set EXCCAUSE to reflect cause of the wdt int trigger */
     movi    a0,PANIC_RSN_INTWDT_CPU0
 9:

components/esp_system/port/esp32s3/CMakeLists.txt

@@ -0,0 +1,7 @@
+set(srcs "dport_panic_highint_hdl.S")
+add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" ${srcs})
+
+#ld_include_panic_highint_hdl is added as an undefined symbol because otherwise the
+#linker will ignore panic_highint_hdl.S as it has no other files depending on any
+#symbols in it.
+set_property(TARGET ${COMPONENT_LIB} APPEND PROPERTY INTERFACE_LINK_LIBRARIES "-u ld_include_panic_highint_hdl")

components/esp_system/port/esp32s3/dport_panic_highint_hdl.S

@@ -0,0 +1,130 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include <xtensa/coreasm.h>
+#include <xtensa/corebits.h>
+#include <xtensa/config/system.h>
+#include "freertos/xtensa_context.h"
+#include "esp_private/panic_reason.h"
+#include "sdkconfig.h"
+#include "soc/soc.h"
+#include "soc/dport_reg.h"
+#include "soc/soc_caps.h"
+
+/*
+
+Interrupt , a high-priority interrupt, is used for several things:
+- Cache error panic handler
+- Interrupt watchdog panic handler
+
+*/
+
+#define L4_INTR_STACK_SIZE  12
+#define L4_INTR_A2_OFFSET   0
+#define L4_INTR_A3_OFFSET   4
+#define L4_INTR_A4_OFFSET   8
+.data
+_l4_intr_stack:
+    .space      L4_INTR_STACK_SIZE*SOC_CPU_CORES_NUM /* This allocates stacks for each individual CPU. */
+    .section .iram1,"ax"
+    .global     xt_highint4
+    .type       xt_highint4,@function
+    .align      4
+xt_highint4:
+
+    /* Allocate exception frame and save minimal context. */
+    mov     a0, sp
+    addi    sp, sp, -XT_STK_FRMSZ
+    s32i    a0, sp, XT_STK_A1
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -12                     /* for debug backtrace */
+    #endif
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_4                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -16                     /* for debug backtrace */
+    #endif
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+
+    /* Save vaddr into exception frame */
+    rsr     a0, EXCVADDR
+    s32i    a0, sp, XT_STK_EXCVADDR
+
+    /* Figure out reason, save into EXCCAUSE reg */
+
+    rsr     a0, INTERRUPT
+    extui   a0, a0, ETS_CACHEERR_INUM, 1 /* get cacheerr int bit */
+    beqz    a0, 1f
+    /* Kill this interrupt; we cannot reset it. */
+    rsr     a0, INTENABLE
+    movi    a4, ~(1<<ETS_CACHEERR_INUM)
+    and     a0, a4, a0
+    wsr     a0, INTENABLE
+    movi    a0, PANIC_RSN_CACHEERR
+    j 9f
+
+1:
+#if CONFIG_ESP_INT_WDT_CHECK_CPU1
+    /* Check if the cause is the app cpu failing to tick.*/
+    movi    a0, int_wdt_app_cpu_ticked
+    l32i    a0, a0, 0
+    bnez    a0, 2f
+    /* It is. Modify cause. */
+    movi    a0,PANIC_RSN_INTWDT_CPU1
+    j 9f
+2:
+#endif
+
+    /* Set EXCCAUSE to reflect cause of the wdt int trigger */
+    movi    a0,PANIC_RSN_INTWDT_CPU0
+9:
+    /* Found the reason, now save it. */
+    s32i    a0, sp, XT_STK_EXCCAUSE
+
+    /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
+    rsr     a0, EXCSAVE_4                   /* save interruptee's a0 */
+
+    s32i    a0, sp, XT_STK_A0
+
+    /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
+    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
+    wsr     a0, PS
+
+    //Call panic handler
+    mov     a6,sp
+    call4   panicHandler
+
+    call0   _xt_context_restore
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, PS
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_4
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove exception frame */
+    rsync                                   /* ensure PS and EPC written */
+
+    rsr     a0, EXCSAVE_4                   /* restore a0 */
+    rfi     4
+
+/* The linker has no reason to link in this file; all symbols it exports are already defined
+   (weakly!) in the default int handler. Define a symbol here so we can use it to have the
+   linker inspect this anyway. */
+
+    .global ld_include_panic_highint_hdl
+ld_include_panic_highint_hdl:

components/esp_system/sdkconfig.rename

@@ -11,3 +11,4 @@ CONFIG_ESP32S2_PANIC_PRINT_REBOOT                       CONFIG_ESP_SYSTEM_PANIC_
 CONFIG_ESP32S2_PANIC_SILENT_REBOOT                      CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
 CONFIG_ESP32S2_PANIC_GDBSTUB                            CONFIG_ESP_SYSTEM_PANIC_GDBSTUB
 
+CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES                  CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES

components/soc/test/test_rtc_clk.c

@@ -171,7 +171,7 @@ static void start_freq(rtc_slow_freq_t required_src_freq, uint32_t start_delay_m
     rtc_slow_freq_t selected_src_freq;
     stop_rtc_external_quartz();
 #ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
-    uint32_t bootstrap_cycles = CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES;
+    uint32_t bootstrap_cycles = CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES;
     printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
             bootstrap_cycles,
             CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
@@ -232,7 +232,7 @@ TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=UT_T1_32kXTAL
     uint32_t end_time;
     stop_rtc_external_quartz();
 #ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
-    uint32_t bootstrap_cycles = CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES;
+    uint32_t bootstrap_cycles = CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES;
     printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
             bootstrap_cycles,
             CONFIG_ESP32_RTC_CLK_CAL_CYCLES);