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Merge branch 'feature/spiram_init_in_app' into 'master'

spiram: expose function to initialize SPI RAM cache

See merge request !1281

Ivan Grokhotkov %!s(int64=8) %!d(string=hai) anos
pai
achega
d3bb9de36a

+ 1 - 0
components/esp32/cpu_start.c

@@ -150,6 +150,7 @@ void IRAM_ATTR call_start_cpu0()
     }
     }
 
 
 #if CONFIG_SPIRAM_BOOT_INIT
 #if CONFIG_SPIRAM_BOOT_INIT
+    esp_spiram_init_cache();
     if (esp_spiram_init() != ESP_OK) {
     if (esp_spiram_init() != ESP_OK) {
         ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
         ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
         abort();
         abort();

+ 12 - 1
components/esp32/include/esp_spiram.h

@@ -27,6 +27,17 @@
  */
  */
 esp_err_t esp_spiram_init();
 esp_err_t esp_spiram_init();
 
 
+/**
+ * @brief Configure Cache/MMU for access to external SPI RAM.
+ *
+ * Normally this function is called from cpu_start, if CONFIG_SPIRAM_BOOT_INIT
+ * option is enabled. Applications which need to enable SPI RAM at run time
+ * can disable CONFIG_SPIRAM_BOOT_INIT, and call this function later.
+ *
+ * @attention this function must be called with flash cache disabled.
+ */
+void esp_spiram_init_cache();
+
 
 
 /**
 /**
  * @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and
  * @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and
@@ -76,4 +87,4 @@ void esp_spiram_writeback_cache();
 esp_err_t esp_spiram_reserve_dma_pool(size_t size);
 esp_err_t esp_spiram_reserve_dma_pool(size_t size);
 
 
 
 
-#endif
+#endif

+ 6 - 4
components/esp32/spiram.c

@@ -91,9 +91,7 @@ bool esp_spiram_test()
     }
     }
 }
 }
 
 
-
-
-esp_err_t esp_spiram_init()
+void IRAM_ATTR esp_spiram_init_cache()
 {
 {
     //Enable external RAM in MMU
     //Enable external RAM in MMU
     cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
     cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
@@ -102,7 +100,11 @@ esp_err_t esp_spiram_init()
     DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
     DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
     cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
     cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
 #endif
 #endif
+}
 
 
+
+esp_err_t esp_spiram_init()
+{
     esp_err_t r;
     esp_err_t r;
     r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
     r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
     if (r != ESP_OK) {
     if (r != ESP_OK) {
@@ -202,4 +204,4 @@ void IRAM_ATTR esp_spiram_writeback_cache()
 
 
 
 
 
 
-#endif
+#endif