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@@ -182,7 +182,7 @@ continue_exit:
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/* invalidate TLB, I-cache and branch predictor */
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mov r0, #0
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- mcr p15, 0, r0, c8, c7, 0 /* ITLBIALL */
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+ mcr p15, 0, r0, c8, c7, 0 /* TLBIALL */
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mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
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mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
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dsb
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@@ -268,7 +268,7 @@ enable_mmu_page_table_early:
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/* invalidate TLB, I-cache and branch predictor */
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mov r0, #0
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- mcr p15, 0, r0, c8, c7, 0 /* ITLBIALL */
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+ mcr p15, 0, r0, c8, c7, 0 /* TLBIALL */
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mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
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mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
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@@ -660,7 +660,7 @@ rt_hw_mmu_switch:
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/* invalidate TLB, I-cache and branch predictor */
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mov r0, #0
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- mcr p15, 0, r0, c8, c7, 0 /* ITLBIALL */
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+ mcr p15, 0, r0, c8, c7, 0 /* TLBIALL */
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mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
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mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
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