drv_i2c.c 24 KB

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  1. /* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
  2. *
  3. * Redistribution and use in source and binary forms, with or without
  4. * modification, are permitted provided that the following conditions are met:
  5. * 1. Redistributions of source code must retain the above copyright
  6. * notice, this list of conditions and the following disclaimer.
  7. * 2. Redistributions in binary form must reproduce the above copyright
  8. * notice, this list of conditions and the following disclaimer in the
  9. * documentation and/or other materials provided with the distribution.
  10. *
  11. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
  12. * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  13. * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  14. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  15. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
  16. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  17. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  18. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  20. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  21. * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  22. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  23. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24. */
  25. /*
  26. * Copyright (c) 2006-2025 RT-Thread Development Team
  27. *
  28. * SPDX-License-Identifier: Apache-2.0
  29. */
  30. #include <rtthread.h>
  31. #include <rthw.h>
  32. #include <rtdevice.h>
  33. #include <riscv_io.h>
  34. #include <ioremap.h>
  35. #include <mmu.h>
  36. #include "board.h"
  37. #include "drv_i2c.h"
  38. #include "sysctl_clk.h"
  39. #include "drv_pdma.h"
  40. #undef DBG_TAG
  41. #undef DBG_LVL
  42. #define DBG_TAG "drv_i2c"
  43. #define DBG_LVL DBG_INFO
  44. #include <rtdbg.h>
  45. /*
  46. * Note:
  47. * - When DMA is enabled, the PDMA driver requires both the address and
  48. * data to be 4-byte aligned.(Address alignment is handled internally
  49. * by this driver, so application developers do not need to worry about
  50. * address alignment.) Therefore, when using DMA for read/write operations,
  51. * if the data size is not 4-byte aligned, even with DMA enabled, the driver
  52. * will actually use CPU polling for read/write. Application code should be
  53. * aware of this and handle it accordingly. For example, if the data length
  54. * to be read or written is not 4-byte aligned, you can split the data into
  55. * an aligned part and an unaligned part, use DMA for the aligned part, and
  56. * use CPU polling for the unaligned part.
  57. */
  58. #ifdef BSP_USING_I2C_DMA
  59. #define K230_I2C_PDMA_CH_INVALID 0xFF
  60. #define K230_I2C_PDMA_CACHE_LINE_SIZE 64
  61. struct _i2c_pdma_cfg
  62. {
  63. rt_event_t event;
  64. rt_uint8_t ch;
  65. usr_pdma_cfg_t cfg;
  66. device_sel_e tx_dev;
  67. device_sel_e rx_dev;
  68. };
  69. typedef enum
  70. {
  71. K230_I2C_PDMA_EVENT_NONE = 0x00,
  72. K230_I2C_PDMA_EVENT_COMPLETE = 0x01,
  73. K230_I2C_PDMA_EVENT_TIMEOUT = 0x02,
  74. } k230_i2c_pdma_event_t;
  75. #endif
  76. struct _i2c_speed_cfg
  77. {
  78. rt_uint16_t hcnt;
  79. rt_uint16_t lcnt;
  80. rt_uint16_t spklen;
  81. };
  82. struct k230_i2c_dev
  83. {
  84. struct rt_i2c_bus_device dev;
  85. const char *name;
  86. rt_ubase_t base;
  87. rt_ubase_t base_pa;
  88. size_t size;
  89. int vector;
  90. rt_uint32_t clock;
  91. struct rt_i2c_msg *msg;
  92. struct _i2c_speed_cfg speed_cfg;
  93. #ifdef BSP_USING_I2C_DMA
  94. struct _i2c_pdma_cfg pdma_cfg;
  95. #endif
  96. };
  97. #ifdef BSP_USING_I2C_DMA
  98. static rt_err_t k230_i2c_pdma_read(struct k230_i2c_dev *dev);
  99. static rt_err_t k230_i2c_pdma_write(struct k230_i2c_dev *dev);
  100. #endif
  101. static rt_size_t k230_i2c_get_timer(rt_size_t base)
  102. {
  103. return rt_tick_get() - base ;
  104. }
  105. static void k230_i2c_enable(struct k230_i2c_dev *dev, rt_bool_t enable)
  106. {
  107. volatile i2c_t *i2c = (i2c_t *)dev->base;
  108. rt_uint32_t en_value = enable ? 1 : 0;
  109. int timeout = 100;
  110. do
  111. {
  112. i2c->enable.enable = en_value;
  113. if (i2c->enable_status.en == en_value)
  114. {
  115. return;
  116. }
  117. /*
  118. * Wait 10 times the signaling period of the highest I2C
  119. * transfer supported by the driver (for 400KHz this is
  120. * 25us) as described in the DesignWare I2C databook.
  121. */
  122. rt_hw_us_delay(25);
  123. } while(timeout--);
  124. LOG_E("timeout in %s i2c\n", enable ? "enable" : "disable");
  125. }
  126. static void k230_i2c_set_bus_timeout(struct k230_i2c_dev *dev, rt_uint32_t timeout)
  127. {
  128. float tick = 0;
  129. tick = RT_TICK_PER_SECOND / 1000.0f; /* ms to tick */
  130. dev->dev.timeout = (rt_uint32_t)(timeout * tick);
  131. }
  132. static int k230_i2c_set_bus_speed(struct k230_i2c_dev *dev, rt_uint32_t speed)
  133. {
  134. volatile i2c_t *i2c = (i2c_t *)dev->base;
  135. rt_uint32_t i2c_spd, period, spklen, ft;
  136. /*
  137. * Calculate clock counts for I2C speed
  138. * hcnt + lcnt + spklen + 7 + 1 + fall_time * clk = clk / speed
  139. * fall_time = 10ns
  140. * spklen = 0~50ns
  141. */
  142. spklen = dev->clock * 10 / 1e9;
  143. ft = dev->clock * 10 / 1e9;
  144. period = dev->clock / speed;
  145. period = period - spklen - 7 - 1 - ft;
  146. dev->speed_cfg.lcnt = period / 2;
  147. dev->speed_cfg.hcnt = period - dev->speed_cfg.lcnt;
  148. dev->speed_cfg.spklen = spklen;
  149. if (speed <= I2C_STANDARD_SPEED_UP)
  150. {
  151. i2c_spd = I2C_SPEED_MODE_STANDARD;
  152. }
  153. else if (speed <= I2C_FAST_SPEED_UP)
  154. {
  155. i2c_spd = I2C_SPEED_MODE_FAST;
  156. }
  157. else if (speed <= I2C_MAX_SPEED_UP)
  158. {
  159. i2c_spd = I2C_SPEED_MODE_MAX;
  160. }
  161. else
  162. {
  163. return -RT_EINVAL;
  164. }
  165. /* to set speed cltr must be disabled */
  166. k230_i2c_enable(dev, RT_FALSE);
  167. switch (i2c_spd)
  168. {
  169. case I2C_SPEED_MODE_STANDARD:
  170. i2c->ss_ufm_scl_hcnt.cnt = dev->speed_cfg.hcnt;
  171. i2c->ss_ufm_scl_lcnt.cnt = dev->speed_cfg.lcnt;
  172. i2c->fs_ufm_spklen.spklen = dev->speed_cfg.spklen;
  173. break;
  174. case I2C_SPEED_MODE_FAST:
  175. i2c->fs_scl_hcnt_ufm_tbuf_cnt.cnt = dev->speed_cfg.hcnt;
  176. i2c->fs_scl_lcnt.cnt = dev->speed_cfg.lcnt;
  177. i2c->fs_ufm_spklen.spklen = dev->speed_cfg.spklen;
  178. break;
  179. case I2C_SPEED_MODE_MAX:
  180. i2c->hs_scl_hcnt.cnt = dev->speed_cfg.hcnt;
  181. i2c->hs_scl_lcnt.cnt = dev->speed_cfg.lcnt;
  182. i2c->hs_spklen.spklen = dev->speed_cfg.spklen;
  183. break;
  184. default: break;
  185. }
  186. i2c->con.speed = i2c_spd;
  187. /* Enable back i2c now speed set */
  188. k230_i2c_enable(dev, RT_TRUE);
  189. return RT_EOK;
  190. }
  191. static void k230_i2c_set_addr(struct k230_i2c_dev *dev)
  192. {
  193. volatile i2c_t *i2c = (i2c_t *)dev->base;
  194. rt_uint16_t i2c_addr = dev->msg->addr;
  195. /* Disable i2c */
  196. k230_i2c_enable(dev, RT_FALSE);
  197. if (dev->msg->flags & RT_I2C_ADDR_10BIT || dev->dev.flags & RT_I2C_ADDR_10BIT)
  198. {
  199. i2c->tar.master_10bit_addr = 1;
  200. i2c_addr &= 0x3FF;
  201. }
  202. else
  203. {
  204. i2c->tar.master_10bit_addr = 0;
  205. i2c_addr &= 0x7F;
  206. }
  207. i2c->tar.tar = i2c_addr;
  208. /* Enable i2c */
  209. k230_i2c_enable(dev, RT_TRUE);
  210. }
  211. static void k230_i2c_flush_rxfifo(struct k230_i2c_dev *dev)
  212. {
  213. volatile i2c_t *i2c = (i2c_t *)dev->base;
  214. while (i2c->status.rfne)
  215. {
  216. readl(&i2c->data_cmd);
  217. }
  218. }
  219. static int k230_i2c_wait_for_bus_busy(struct k230_i2c_dev *dev)
  220. {
  221. rt_size_t start_time = k230_i2c_get_timer(0);
  222. volatile i2c_t *i2c = (i2c_t *)dev->base;
  223. while ((i2c->status.mst_activity) || !(i2c->status.tfe))
  224. {
  225. /* Evaluate timeout */
  226. if (k230_i2c_get_timer(start_time) > (rt_size_t)dev->dev.timeout * I2C_TX_FIFO_SIZE)
  227. {
  228. return -RT_ETIMEOUT;
  229. }
  230. }
  231. return RT_EOK;
  232. }
  233. static int k230_i2c_xfer_init(struct k230_i2c_dev *dev)
  234. {
  235. volatile i2c_t *i2c = (i2c_t *)dev->base;
  236. if (k230_i2c_wait_for_bus_busy(dev) != RT_EOK)
  237. {
  238. return -RT_EBUSY;
  239. }
  240. k230_i2c_set_addr(dev);
  241. return RT_EOK;
  242. }
  243. static int k230_i2c_xfer_finish(struct k230_i2c_dev *dev)
  244. {
  245. volatile i2c_t *i2c = (i2c_t *)dev->base;
  246. rt_uint32_t start_stop_det = k230_i2c_get_timer(0);
  247. while (1)
  248. {
  249. if (i2c->raw_intr_stat.stop_det)
  250. {
  251. readl(&i2c->clr_stop_det);
  252. break;
  253. }
  254. else if (k230_i2c_get_timer(start_stop_det) > dev->dev.timeout)
  255. {
  256. break;
  257. }
  258. }
  259. if (k230_i2c_wait_for_bus_busy(dev) != RT_EOK)
  260. {
  261. return -RT_EBUSY;
  262. }
  263. k230_i2c_flush_rxfifo(dev);
  264. return RT_EOK;
  265. }
  266. static int k230_i2c_read(struct k230_i2c_dev *dev)
  267. {
  268. #ifdef BSP_USING_I2C_DMA
  269. if (dev->msg->len % 4 == 0)
  270. {
  271. return k230_i2c_pdma_read(dev);
  272. }
  273. #endif
  274. volatile i2c_t *i2c = (i2c_t *)dev->base;
  275. rt_size_t start_time_rx = 0;
  276. rt_uint32_t recv_len = dev->msg->len;
  277. rt_uint32_t tran_len = dev->msg->len;
  278. rt_uint8_t *buffer = dev->msg->buf;
  279. rt_uint32_t cmd = 0;
  280. /* If no start condition is sent before reading, then send a repeated start. */
  281. if (dev->msg->flags & RT_I2C_NO_START)
  282. {
  283. cmd |= I2C_DATA_CMD_RESTART;
  284. }
  285. else
  286. {
  287. if (k230_i2c_xfer_init(dev) != RT_EOK)
  288. {
  289. return -RT_EBUSY;
  290. }
  291. }
  292. start_time_rx = k230_i2c_get_timer(0);
  293. while (recv_len || tran_len)
  294. {
  295. if (tran_len)
  296. {
  297. while (i2c->status.tfnf == 0);
  298. /* Write stop when the last byte */
  299. cmd = tran_len == 1 ? cmd | I2C_DATA_CMD_STOP : cmd;
  300. /* Write to data cmd register to trigger i2c */
  301. writel(cmd | I2C_DATA_CMD_READ, &i2c->data_cmd);
  302. cmd = 0;
  303. tran_len--;
  304. }
  305. if (i2c->status.rfne)
  306. {
  307. *buffer++ = i2c->data_cmd.dat;
  308. recv_len--;
  309. start_time_rx = k230_i2c_get_timer(0);
  310. }
  311. else if (k230_i2c_get_timer(start_time_rx) > dev->dev.timeout)
  312. {
  313. return -RT_ETIMEOUT;
  314. }
  315. }
  316. return k230_i2c_xfer_finish(dev);
  317. }
  318. static int k230_i2c_write(struct k230_i2c_dev *dev)
  319. {
  320. #ifdef BSP_USING_I2C_DMA
  321. if (dev->msg->len % 4 == 0)
  322. {
  323. return k230_i2c_pdma_write(dev);
  324. }
  325. #endif
  326. volatile i2c_t *i2c = (i2c_t *)dev->base;
  327. rt_size_t start_time_tx = 0;
  328. rt_uint32_t tran_len = dev->msg->len;
  329. rt_uint8_t *buffer = dev->msg->buf;
  330. rt_uint32_t cmd = 0;
  331. if (k230_i2c_xfer_init(dev) != RT_EOK)
  332. {
  333. return -RT_EBUSY;
  334. }
  335. start_time_tx = k230_i2c_get_timer(0);
  336. while (tran_len)
  337. {
  338. if (i2c->status.tfnf)
  339. {
  340. /* If there is no stop flag, the stop condition will not be sent at the last byte. */
  341. if (tran_len == 1 && !(dev->msg->flags & RT_I2C_NO_STOP))
  342. {
  343. cmd |= I2C_DATA_CMD_STOP;
  344. }
  345. else
  346. {
  347. cmd &= ~I2C_DATA_CMD_STOP;
  348. }
  349. cmd |= *buffer++;
  350. writel(cmd, &i2c->data_cmd);
  351. cmd = 0;
  352. tran_len--;
  353. start_time_tx = k230_i2c_get_timer(0);
  354. }
  355. else if (k230_i2c_get_timer(start_time_tx) > dev->dev.timeout)
  356. {
  357. return -RT_ETIMEOUT;
  358. }
  359. }
  360. if (dev->msg->flags & RT_I2C_NO_STOP)
  361. {
  362. return RT_EOK;
  363. }
  364. if (k230_i2c_wait_for_bus_busy(dev) != RT_EOK)
  365. {
  366. return -RT_EBUSY;
  367. }
  368. return RT_EOK;
  369. }
  370. static rt_ssize_t k230_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num)
  371. {
  372. struct k230_i2c_dev *i2c_dev = rt_container_of(bus, struct k230_i2c_dev, dev);
  373. volatile i2c_t *i2c = (i2c_t *)i2c_dev->base;
  374. int ret;
  375. rt_ssize_t send_mesgs = num;
  376. for (; num > 0; num--, msgs++)
  377. {
  378. i2c_dev->msg = msgs;
  379. if (msgs->flags & RT_I2C_RD)
  380. {
  381. ret = k230_i2c_read(i2c_dev);
  382. }
  383. else
  384. {
  385. ret = k230_i2c_write(i2c_dev);
  386. }
  387. if (ret != RT_EOK)
  388. {
  389. return -RT_EIO;
  390. }
  391. }
  392. return send_mesgs;
  393. }
  394. static rt_err_t k230_i2c_control(struct rt_i2c_bus_device *bus, int cmd, void *args)
  395. {
  396. struct k230_i2c_dev *i2c_dev = rt_container_of(bus, struct k230_i2c_dev, dev);
  397. rt_uint32_t arg = *(rt_uint32_t *)args;
  398. rt_err_t ret;
  399. RT_ASSERT(bus != RT_NULL);
  400. switch (cmd)
  401. {
  402. /* set 10-bit addr mode */
  403. case RT_I2C_DEV_CTRL_10BIT:
  404. if (arg & RT_I2C_ADDR_10BIT)
  405. {
  406. i2c_dev->dev.flags |= RT_I2C_ADDR_10BIT;
  407. }
  408. else
  409. {
  410. i2c_dev->dev.flags &= ~RT_I2C_ADDR_10BIT;
  411. }
  412. break;
  413. case RT_I2C_DEV_CTRL_TIMEOUT:
  414. k230_i2c_set_bus_timeout(i2c_dev, arg);
  415. break;
  416. case RT_I2C_DEV_CTRL_CLK:
  417. ret = k230_i2c_set_bus_speed(i2c_dev, arg);
  418. if (ret != RT_EOK)
  419. {
  420. return -RT_EIO;
  421. }
  422. break;
  423. default: break;
  424. }
  425. return RT_EOK;
  426. }
  427. static void k230_i2c_master_init(struct k230_i2c_dev *dev)
  428. {
  429. volatile i2c_t *i2c = (i2c_t *)dev->base;
  430. /* Disable i2c */
  431. k230_i2c_enable(dev, RT_FALSE);
  432. i2c->con.slave_disable = 1;
  433. i2c->con.restart_en = 1;
  434. i2c->con.master_mode = 1;
  435. i2c->tx_tl.tl = I2C_TX_TL;
  436. i2c->rx_tl.tl = I2C_RX_TL;
  437. i2c->intr_mask.m_stop_det = 1;
  438. /* Enable i2c */
  439. k230_i2c_enable(dev, RT_TRUE);
  440. }
  441. static const struct rt_i2c_bus_device_ops k230_i2c_ops =
  442. {
  443. .master_xfer = k230_i2c_xfer,
  444. .i2c_bus_control = k230_i2c_control,
  445. };
  446. static struct k230_i2c_dev k230_i2c_devs[] =
  447. {
  448. #ifdef BSP_USING_I2C0
  449. {
  450. .name = "i2c0",
  451. .base_pa = I2C0_BASE_ADDR,
  452. .size = I2C0_IO_SIZE,
  453. .vector = K230_IRQ_I2C0,
  454. #ifdef BSP_USING_I2C_DMA
  455. .pdma_cfg.tx_dev = I2C0_TX,
  456. .pdma_cfg.rx_dev = I2C0_RX,
  457. #endif
  458. },
  459. #endif
  460. #ifdef BSP_USING_I2C1
  461. {
  462. .name = "i2c1",
  463. .base_pa = I2C1_BASE_ADDR,
  464. .size = I2C1_IO_SIZE,
  465. .vector = K230_IRQ_I2C1,
  466. #ifdef BSP_USING_I2C_DMA
  467. .pdma_cfg.tx_dev = I2C1_TX,
  468. .pdma_cfg.rx_dev = I2C1_RX,
  469. #endif
  470. },
  471. #endif
  472. #ifdef BSP_USING_I2C2
  473. {
  474. .name = "i2c2",
  475. .base_pa = I2C2_BASE_ADDR,
  476. .size = I2C2_IO_SIZE,
  477. .vector = K230_IRQ_I2C2,
  478. #ifdef BSP_USING_I2C_DMA
  479. .pdma_cfg.tx_dev = I2C2_TX,
  480. .pdma_cfg.rx_dev = I2C2_RX,
  481. #endif
  482. },
  483. #endif
  484. #ifdef BSP_USING_I2C3
  485. {
  486. .name = "i2c3",
  487. .base_pa = I2C3_BASE_ADDR,
  488. .size = I2C3_IO_SIZE,
  489. .vector = K230_IRQ_I2C3,
  490. #ifdef BSP_USING_I2C_DMA
  491. .pdma_cfg.tx_dev = I2C3_TX,
  492. .pdma_cfg.rx_dev = I2C3_RX,
  493. #endif
  494. },
  495. #endif
  496. #ifdef BSP_USING_I2C4
  497. {
  498. .name = "i2c4",
  499. .base_pa = I2C4_BASE_ADDR,
  500. .size = I2C4_IO_SIZE,
  501. .vector = K230_IRQ_I2C4,
  502. #ifdef BSP_USING_I2C_DMA
  503. .pdma_cfg.tx_dev = I2C4_TX,
  504. .pdma_cfg.rx_dev = I2C4_RX,
  505. #endif
  506. },
  507. #endif
  508. };
  509. #ifdef BSP_USING_I2C_DMA
  510. static void k230_i2c_pdma_call_back(rt_uint8_t ch, rt_bool_t is_done)
  511. {
  512. k230_i2c_pdma_event_t event_type = is_done ? K230_I2C_PDMA_EVENT_COMPLETE : K230_I2C_PDMA_EVENT_TIMEOUT;
  513. for (rt_uint8_t i = 0; i < sizeof(k230_i2c_devs)/sizeof(k230_i2c_devs[0]); i++)
  514. {
  515. struct k230_i2c_dev *dev = &k230_i2c_devs[i];
  516. if (dev->pdma_cfg.event != RT_NULL && dev->pdma_cfg.ch == ch && dev->pdma_cfg.ch != K230_I2C_PDMA_CH_INVALID)
  517. {
  518. rt_event_send(dev->pdma_cfg.event, event_type);
  519. return;
  520. }
  521. }
  522. }
  523. static void k230_i2c_pdma_cleanup(struct k230_i2c_dev *dev)
  524. {
  525. rt_uint8_t ch = dev->pdma_cfg.ch;
  526. if (ch == K230_I2C_PDMA_CH_INVALID)
  527. {
  528. return;
  529. }
  530. dev->pdma_cfg.ch = K230_I2C_PDMA_CH_INVALID;
  531. k230_pdma_release_channel(ch);
  532. }
  533. static rt_err_t k230_i2c_pdma_read(struct k230_i2c_dev *dev)
  534. {
  535. volatile i2c_t *i2c = (i2c_t *)dev->base;
  536. rt_uint8_t *buffer = dev->msg->buf;
  537. rt_uint8_t *buf;
  538. void *buf_pa;
  539. rt_err_t err;
  540. rt_uint8_t ch;
  541. rt_uint32_t recv_event, read_len;
  542. rt_size_t start_time_tx = 0;
  543. rt_uint32_t cmd = 0;
  544. err = k230_pdma_request_channel(&ch);
  545. if (err != RT_EOK)
  546. {
  547. LOG_E("i2c pdma request channel failed");
  548. return err;
  549. }
  550. dev->pdma_cfg.ch = ch;
  551. err = k230_pdma_set_callback(ch, k230_i2c_pdma_call_back);
  552. if (err != RT_EOK)
  553. {
  554. LOG_E("i2c pdma set callback failed");
  555. k230_i2c_pdma_cleanup(dev);
  556. return err;
  557. }
  558. read_len = dev->msg->len;
  559. buf = (rt_uint8_t *)rt_malloc_align(read_len, K230_I2C_PDMA_CACHE_LINE_SIZE);
  560. if (buf == RT_NULL)
  561. {
  562. LOG_E("i2c pdma malloc buffer failed");
  563. k230_i2c_pdma_cleanup(dev);
  564. return -RT_ENOMEM;
  565. }
  566. buf_pa = rt_kmem_v2p(buf);
  567. if (buf_pa == RT_NULL)
  568. {
  569. LOG_E("i2c pdma get phy addr failed");
  570. k230_i2c_pdma_cleanup(dev);
  571. rt_free_align(buf);
  572. return -RT_ERROR;
  573. }
  574. rt_event_control(dev->pdma_cfg.event, RT_IPC_CMD_RESET, NULL);
  575. dev->pdma_cfg.cfg.device = dev->pdma_cfg.rx_dev;
  576. dev->pdma_cfg.cfg.src_addr = (rt_uint8_t *)(dev->base_pa + 0x10);
  577. dev->pdma_cfg.cfg.dst_addr = (rt_uint8_t *)buf_pa;
  578. dev->pdma_cfg.cfg.line_size = read_len;
  579. dev->pdma_cfg.cfg.pdma_ch_cfg.ch_src_type = FIXED;
  580. dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dev_hsize = PSBYTE1;
  581. dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dat_endian = PDEFAULT;
  582. dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dev_blen = PBURST_LEN_4;
  583. dev->pdma_cfg.cfg.pdma_ch_cfg.ch_priority = 7;
  584. dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dev_tout = 0xFFF;
  585. err = k230_pdma_config(ch, &dev->pdma_cfg.cfg);
  586. if (err != RT_EOK)
  587. {
  588. LOG_E("i2c pdma config failed");
  589. k230_i2c_pdma_cleanup(dev);
  590. rt_free_align(buf);
  591. return err;
  592. }
  593. /* If no start condition is sent before reading, then send a repeated start. */
  594. if (dev->msg->flags & RT_I2C_NO_START)
  595. {
  596. cmd |= I2C_DATA_CMD_RESTART;
  597. }
  598. else
  599. {
  600. if (k230_i2c_xfer_init(dev) != RT_EOK)
  601. {
  602. LOG_E("i2c pdma xfer init failed");
  603. k230_i2c_pdma_cleanup(dev);
  604. rt_free_align(buf);
  605. return -RT_EBUSY;
  606. }
  607. }
  608. start_time_tx = k230_i2c_get_timer(0);
  609. err = k230_pdma_start(ch);
  610. if (err != RT_EOK)
  611. {
  612. LOG_E("i2c pdma start failed");
  613. k230_i2c_pdma_cleanup(dev);
  614. rt_free_align(buf);
  615. return err;
  616. }
  617. for (rt_uint32_t i = 0; i < read_len; i++)
  618. {
  619. while (i2c->status.tfnf == 0);
  620. /* Write stop when the last byte */
  621. cmd = i == (read_len - 1) ? I2C_DATA_CMD_STOP : 0;
  622. /* Write to data cmd register to trigger i2c */
  623. writel(cmd | I2C_DATA_CMD_READ, &i2c->data_cmd);
  624. cmd = 0;
  625. }
  626. err = rt_event_recv(dev->pdma_cfg.event,
  627. K230_I2C_PDMA_EVENT_COMPLETE | K230_I2C_PDMA_EVENT_TIMEOUT,
  628. RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
  629. RT_WAITING_FOREVER,
  630. &recv_event);
  631. if (err != RT_EOK || (recv_event & K230_I2C_PDMA_EVENT_TIMEOUT))
  632. {
  633. LOG_E("i2c pdma read timeout");
  634. k230_pdma_stop(ch);
  635. k230_i2c_pdma_cleanup(dev);
  636. rt_free_align(buf);
  637. return -RT_ETIMEOUT;
  638. }
  639. rt_memcpy(buffer, buf, read_len);
  640. k230_pdma_stop(ch);
  641. k230_i2c_pdma_cleanup(dev);
  642. rt_free_align(buf);
  643. if (k230_i2c_get_timer(start_time_tx) > dev->dev.timeout)
  644. {
  645. return -RT_ETIMEOUT;
  646. }
  647. return k230_i2c_xfer_finish(dev);
  648. }
  649. static inline rt_uint32_t k230_i2c_make_data_cmd(rt_uint8_t data, rt_uint32_t flags)
  650. {
  651. return (rt_uint32_t)data | flags;
  652. }
  653. static rt_err_t k230_i2c_pdma_write(struct k230_i2c_dev *dev)
  654. {
  655. volatile i2c_t *i2c = (i2c_t *)dev->base;
  656. rt_uint8_t *buffer = dev->msg->buf;
  657. rt_uint32_t *buf;
  658. void *buf_pa;
  659. rt_err_t err;
  660. rt_uint8_t ch;
  661. rt_uint32_t recv_event, tran_len, flags;
  662. rt_size_t start_time_tx = 0;
  663. err = k230_pdma_request_channel(&ch);
  664. if (err != RT_EOK)
  665. {
  666. LOG_E("i2c pdma request channel failed");
  667. return err;
  668. }
  669. dev->pdma_cfg.ch = ch;
  670. err = k230_pdma_set_callback(ch, k230_i2c_pdma_call_back);
  671. if (err != RT_EOK)
  672. {
  673. LOG_E("i2c pdma set callback failed");
  674. k230_i2c_pdma_cleanup(dev);
  675. return err;
  676. }
  677. tran_len = dev->msg->len;
  678. buf = (rt_uint32_t *)rt_malloc_align(tran_len * sizeof(rt_uint32_t), K230_I2C_PDMA_CACHE_LINE_SIZE);
  679. if (buf == RT_NULL)
  680. {
  681. LOG_E("i2c pdma malloc buffer failed");
  682. k230_i2c_pdma_cleanup(dev);
  683. return -RT_ENOMEM;
  684. }
  685. for (rt_uint32_t i = 0; i < tran_len; i++)
  686. {
  687. flags = 0;
  688. if (i == (tran_len - 1) && !(dev->msg->flags & RT_I2C_NO_STOP))
  689. {
  690. flags |= I2C_DATA_CMD_STOP;
  691. }
  692. buf[i] = k230_i2c_make_data_cmd(buffer[i], flags);
  693. }
  694. buf_pa = rt_kmem_v2p(buf);
  695. if (buf_pa == RT_NULL)
  696. {
  697. LOG_E("i2c pdma get phy addr failed");
  698. k230_i2c_pdma_cleanup(dev);
  699. rt_free_align(buf);
  700. return -RT_ERROR;
  701. }
  702. rt_event_control(dev->pdma_cfg.event, RT_IPC_CMD_RESET, NULL);
  703. dev->pdma_cfg.cfg.device = dev->pdma_cfg.tx_dev;
  704. dev->pdma_cfg.cfg.src_addr = (rt_uint8_t *)buf_pa;
  705. dev->pdma_cfg.cfg.dst_addr = (rt_uint8_t *)(dev->base_pa + 0x10);
  706. dev->pdma_cfg.cfg.line_size = tran_len * sizeof(rt_uint32_t);
  707. dev->pdma_cfg.cfg.pdma_ch_cfg.ch_src_type = CONTINUE;
  708. dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dev_hsize = PSBYTE4;
  709. dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dat_endian = PDEFAULT;
  710. dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dev_blen = PBURST_LEN_4;
  711. dev->pdma_cfg.cfg.pdma_ch_cfg.ch_priority = 7;
  712. dev->pdma_cfg.cfg.pdma_ch_cfg.ch_dev_tout = 0xFFF;
  713. err = k230_pdma_config(ch, &dev->pdma_cfg.cfg);
  714. if (err != RT_EOK)
  715. {
  716. LOG_E("i2c pdma config failed");
  717. k230_i2c_pdma_cleanup(dev);
  718. rt_free_align(buf);
  719. return err;
  720. }
  721. if (k230_i2c_xfer_init(dev) != RT_EOK)
  722. {
  723. k230_i2c_pdma_cleanup(dev);
  724. rt_free_align(buf);
  725. return -RT_EBUSY;
  726. }
  727. start_time_tx = k230_i2c_get_timer(0);
  728. err = k230_pdma_start(ch);
  729. if (err != RT_EOK)
  730. {
  731. LOG_E("i2c pdma start failed");
  732. k230_i2c_pdma_cleanup(dev);
  733. rt_free_align(buf);
  734. return err;
  735. }
  736. err = rt_event_recv(dev->pdma_cfg.event,
  737. K230_I2C_PDMA_EVENT_COMPLETE | K230_I2C_PDMA_EVENT_TIMEOUT,
  738. RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
  739. RT_WAITING_FOREVER,
  740. &recv_event);
  741. if (err != RT_EOK || (recv_event & K230_I2C_PDMA_EVENT_TIMEOUT))
  742. {
  743. LOG_E("i2c pdma write timeout");
  744. k230_pdma_stop(ch);
  745. k230_i2c_pdma_cleanup(dev);
  746. rt_free_align(buf);
  747. return -RT_ETIMEOUT;
  748. }
  749. k230_pdma_stop(ch);
  750. k230_i2c_pdma_cleanup(dev);
  751. rt_free_align(buf);
  752. if (k230_i2c_get_timer(start_time_tx) > dev->dev.timeout)
  753. {
  754. return -RT_ETIMEOUT;
  755. }
  756. return RT_EOK;
  757. }
  758. static void k230_i2c_pdma_init(struct k230_i2c_dev *dev)
  759. {
  760. volatile i2c_t *i2c = (i2c_t *)dev->base;
  761. i2c->dma_cr.tdmae = 1;
  762. i2c->dma_cr.rdmae = 1;
  763. i2c->dma_tdlr.dmatdl = 15;
  764. i2c->dma_rdlr.dmardl = 3;
  765. }
  766. #endif
  767. int rt_hw_i2c_init(void)
  768. {
  769. int i;
  770. for (i = 0; i < sizeof(k230_i2c_devs) / sizeof(k230_i2c_devs[0]); i++)
  771. {
  772. k230_i2c_devs[i].base = (rt_ubase_t)rt_ioremap((void *)k230_i2c_devs[i].base_pa, k230_i2c_devs[i].size);
  773. k230_i2c_devs[i].dev.ops = &k230_i2c_ops;
  774. k230_i2c_devs[i].clock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_I2C0_CORE + i);
  775. k230_i2c_master_init(&k230_i2c_devs[i]);
  776. k230_i2c_set_bus_timeout(&k230_i2c_devs[i], I2C_DEFAULT_TIMEOUT);
  777. k230_i2c_set_bus_speed(&k230_i2c_devs[i], I2C_DEFAULT_SPEED);
  778. rt_i2c_bus_device_register(&k230_i2c_devs[i].dev, k230_i2c_devs[i].name);
  779. LOG_I("i2c%d master mode, i2c%d clock=%dHz\n", i, i, k230_i2c_devs[i].clock);
  780. #ifdef BSP_USING_I2C_DMA
  781. k230_i2c_pdma_init(&k230_i2c_devs[i]);
  782. k230_i2c_devs[i].pdma_cfg.ch = K230_I2C_PDMA_CH_INVALID;
  783. k230_i2c_devs[i].pdma_cfg.event = rt_event_create(k230_i2c_devs[i].name, RT_IPC_FLAG_FIFO);
  784. if (k230_i2c_devs[i].pdma_cfg.event == RT_NULL)
  785. {
  786. LOG_E("i2c pdma event(%s) create failed", k230_i2c_devs[i].name);
  787. for (int j = 0; j < i; j++)
  788. {
  789. rt_event_delete(k230_i2c_devs[j].pdma_cfg.event);
  790. }
  791. return -RT_ENOMEM;
  792. }
  793. #endif
  794. }
  795. return RT_EOK;
  796. }
  797. INIT_DEVICE_EXPORT(rt_hw_i2c_init);