 GuentherMartin
|
a18a6b7ad6
CMSIS-Core: aligned __disable_irq, __disable_fault_irq between supported compilers (#1187)
|
il y a 4 ans |
|
Kevin Bracey
|
f88880f4ec
ARMCC: remove explicit DSB/DMB/ISB barriers
|
il y a 7 ans |
|
Jonatan Antoni
|
3f3b67fd5d
Core(A): Fixed __FPU_Enable function not to mess registers. (#589)
|
il y a 6 ans |
|
Kevin Bracey
|
0c41122493
Add __COMPILER_BARRIER
|
il y a 7 ans |
|
Jonatan Antoni
|
282aa9920d
Revert "rtos: rtx5: ARMCC5: move the variables in .bss.os section to ZI section"
|
il y a 7 ans |
|
Tero Jääskö
|
0b4f11cfaa
rtos: rtx5: ARMCC5: move the variables in .bss.os section to ZI section
|
il y a 7 ans |
|
Wilfried Chauveau
|
5dfa246afd
make access to CP register volatile so it doesn't get optimised out
|
il y a 7 ans |
|
Jonatan Antoni
|
18cc96dc71
Updating company brand
|
il y a 8 ans |
|
Jonatan Antoni
|
d43938fac6
Core(A): Changed macro __DEPRECATED to CMSIS_DEPRECATED. (Issue #287)
|
il y a 8 ans |
|
Jonatan Antoni
|
17b53ef2a2
Core(A): Refactored L1 Cache maintenance to be compiler agnostic.
|
il y a 8 ans |
|
Robert Rostohar
|
d7783e4741
Core(A): Updated __FPU_Enable function (VFP register count detection)
|
il y a 8 ans |
|
Jonatan Antoni
|
59c9797136
Core(A): Fixed macro issues on coprocessor register access macros.
|
il y a 8 ans |
|
Jonatan Antoni
|
b91922ab72
Core: Fixed inline functions to use consistent code style.
|
il y a 8 ans |
|
Jonatan Antoni
|
bf63e30194
Core: Aligned intrinsic prototypes for REV, REV16, REVSH, RBIT and CLZ along all compilers to ACLE specification.
|
il y a 8 ans |
|
Jonatan Antoni
|
44c3918b78
Core-A: Add 64bit Generic Counter registers access functions
|
il y a 8 ans |
|
Jonatan Antoni
|
17947cc250
Core: Fixed core instruction prototypes of __REV and __REV16.
|
il y a 8 ans |
|
Daniel Brondani
|
e928a674c0
Core(A): Fixed common core functions to access CP15 registers in cmsis_armcc.h
|
il y a 8 ans |
|
Jonatan Antoni
|
ca5cf5dba4
Fixed documentation after Core(A) refactoring.
|
il y a 8 ans |
|
Jonatan Antoni
|
096b2f0fb6
Core(A): Refactored all Coprocessor 15 related core functions into a common header file.
|
il y a 8 ans |
|
Jonatan Antoni
|
74d87a927b
Core(A): Fixed various compiler intrinsics.
|
il y a 8 ans |
|
Jonatan Antoni
|
7b7dd34853
Core(A): Added __SSAT and __USAT intrinsics like for Core(M).
|
il y a 8 ans |
|
Jonatan Antoni
|
d6321460f4
CMSIS-Core(A): Added register correlation between CMSIS and TRMs.
|
il y a 8 ans |
|
Jonatan Antoni
|
03df35f394
CMSIS-Core(A): Enhanced register abstraction and documentation.
|
il y a 8 ans |
|
Daniel Brondani
|
650abfe4d5
Added OS Tick component for Cortex-A7: Generic Physical Timer
|
il y a 8 ans |
|
Daniel Brondani
|
d57483353b
CMSIS-Core(A): Updated documentation
|
il y a 8 ans |
|
Jonatan Antoni
|
18ce4edcff
CMSIS-Core(A): Enhanced documentation for cache access maintenance.
|
il y a 8 ans |
|
Daniel Brondani
|
948df5c68a
Added PL1_SetCounterFrequency into Core_A
|
il y a 8 ans |
|
Daniel Brondani
|
e48eaaca24
Updated Core_A documentation
|
il y a 8 ans |
|
Vladimir Umek
|
98876671b7
Corrected __set_mode for ARMCC AC5
|
il y a 8 ans |
|
Daniel Brondani
|
7bfe5d0c86
CMSIS-Core_A:
|
il y a 8 ans |
