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Config
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fc5be560c2
Added SIMD tests for Cortex-M devices.
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ConfigA
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0b16b65d51
CoreValidation: Added test case for __FPU_Enable.
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CV_CoreAFunc.c
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0b16b65d51
CoreValidation: Added test case for __FPU_Enable.
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CV_CoreFunc.c
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909f815d31
CoreValidation: Fixed TC_CoreFunc_IRQVect missing external declaration to ROM vector table.
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CV_CoreInstr.c
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57bc4c12fd
CoreValidation: Fixed TC_CoreFunc_APSR and TC_CoreInstr_RRX.
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CV_CoreSimd.c
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899e647d48
CMSIS CORE: Adding support for __SXTB16_RORn
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CV_Framework.c
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7cd9150812
CoreValidation: Implemented all unhandled exceptions to abort the test run
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CV_GenTimer.c
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44c3918b78
Core-A: Add 64bit Generic Counter registers access functions
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CV_L1Cache.c
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8962e22a96
CoreValidation: Fixed Cortex-A test cases.
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CV_MPU_ARMv7.c
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690bc33b33
CoreValidation: Reworked test structure.
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CV_MPU_ARMv8.c
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10ce922e95
CoreValidation: Enhanced test configurations for Cortex-M23/M33.
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CV_Report.c
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fc5be560c2
Added SIMD tests for Cortex-M devices.
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cmsis_cv.c
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0b16b65d51
CoreValidation: Added test case for __FPU_Enable.
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%!s(int64=6) %!d(string=hai) anos |
Gian Marco Iodice
899e647d48
CMSIS CORE: Adding support for __SXTB16_RORn